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49 lines
1.4 KiB
Verilog
49 lines
1.4 KiB
Verilog
/* This file is part of JTOPL.
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JTOPL program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JTOPL program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 20-6-2020
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*/
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module jtopl_acc(
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input rst,
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input clk,
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input cenop,
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input signed [12:0] op_result,
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input zero,
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input op, // 0 for modulator operators
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input con, // 0 for modulated connection
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output signed [15:0] snd
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);
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wire sum_en;
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assign sum_en = op | con;
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// Continuous output
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jtopl_single_acc u_acc(
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.clk ( clk ),
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.cenop ( cenop ),
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.op_result ( op_result ),
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.sum_en ( sum_en ),
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.zero ( zero ),
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.snd ( snd )
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);
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endmodule
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