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111 lines
3.0 KiB
Verilog
111 lines
3.0 KiB
Verilog
/* This file is part of JTOPL
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JTOPL program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JTOPL program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 28-5-2022
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*/
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module jtopl_reg_ch#( parameter
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CHCSRW = 10
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) (
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input rst,
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input clk,
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input cen,
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input zero,
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input rhy_en,
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input [4:0] rhy_kon,
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input [17:0] slot,
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input [1:0] group,
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input [CHCSRW-1:0] chcfg_inmux,
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output reg [CHCSRW-1:0] chcfg,
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output reg rhy_oen, // high for rhythm operators if rhy_en is set
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output rhyon_csr
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);
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// Rhythm key-on CSR
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localparam BD=4, SD=3, TOM=2, TC=1, HH=0;
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reg [CHCSRW-1:0] chcfg0_in, chcfg1_in, chcfg2_in;
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wire [CHCSRW-1:0] chcfg0_out, chcfg1_out, chcfg2_out;
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reg [5:0] rhy_csr;
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assign rhyon_csr = rhy_csr[5];
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always @(*) begin
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case( group )
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default: chcfg = chcfg0_out;
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2'd1: chcfg = chcfg1_out;
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2'd2: chcfg = chcfg2_out;
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endcase
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chcfg0_in = group==2'b00 ? chcfg_inmux : chcfg0_out;
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chcfg1_in = group==2'b01 ? chcfg_inmux : chcfg1_out;
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chcfg2_in = group==2'b10 ? chcfg_inmux : chcfg2_out;
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end
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`ifdef SIMULATION
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reg [CHCSRW-1:0] chsnap0, chsnap1,chsnap2;
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always @(posedge clk) if(zero) begin
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chsnap0 <= chcfg0_out;
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chsnap1 <= chcfg1_out;
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chsnap2 <= chcfg2_out;
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end
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`endif
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always @(posedge clk, posedge rst) begin
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if( rst ) begin
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rhy_csr <= 6'd0;
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rhy_oen <= 0;
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end else if(cen) begin
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if(slot[11]) rhy_oen <= rhy_en;
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if(slot[17]) begin
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rhy_csr <= { rhy_kon[BD], rhy_kon[HH], rhy_kon[TOM],
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rhy_kon[BD], rhy_kon[SD], rhy_kon[TC] };
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rhy_oen <= 0;
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end else
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rhy_csr <= { rhy_csr[4:0], rhy_csr[5] };
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end
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end
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jtopl_sh_rst #(.width(CHCSRW),.stages(3)) u_group0(
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.clk ( clk ),
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.cen ( cen ),
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.rst ( rst ),
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.din ( chcfg0_in ),
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.drop ( chcfg0_out )
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);
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jtopl_sh_rst #(.width(CHCSRW),.stages(3)) u_group1(
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.clk ( clk ),
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.cen ( cen ),
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.rst ( rst ),
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.din ( chcfg1_in ),
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.drop ( chcfg1_out )
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);
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jtopl_sh_rst #(.width(CHCSRW),.stages(3)) u_group2(
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.clk ( clk ),
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.cen ( cen ),
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.rst ( rst ),
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.din ( chcfg2_in ),
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.drop ( chcfg2_out )
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);
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endmodule |