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143 lines
7.2 KiB
VHDL
143 lines
7.2 KiB
VHDL
-------------------------------------------------------------------------------
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-- --
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-- X X XXXXXX XXXXXX XXXXXX XXXXXX X --
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-- XX XX X X X X X X X XX --
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-- X X X X X X X X X X X X --
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-- X X X X X X X X X X X X --
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-- X X X X XXXXXX X X XXXXXX X --
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-- X X X X X X X X X --
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-- X X X X X X X X X --
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-- X X X X X X X X X X --
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-- X X XXXXXX XXXXXX XXXXXX XXXXXX X --
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-- --
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-- --
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-- O R E G A N O S Y S T E M S --
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-- --
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-- Design & Consulting --
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-- --
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-------------------------------------------------------------------------------
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-- --
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-- Web: http://www.oregano.at/ --
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-- --
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-- Contact: mc8051@oregano.at --
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-- --
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-------------------------------------------------------------------------------
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-- --
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-- MC8051 - VHDL 8051 Microcontroller IP Core --
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-- Copyright (C) 2001 OREGANO SYSTEMS --
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-- --
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-- This library is free software; you can redistribute it and/or --
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-- modify it under the terms of the GNU Lesser General Public --
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-- License as published by the Free Software Foundation; either --
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-- version 2.1 of the License, or (at your option) any later version. --
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-- --
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-- This library is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
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-- Lesser General Public License for more details. --
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-- --
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-- Full details of the license can be found in the file LGPL.TXT. --
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-- --
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-- You should have received a copy of the GNU Lesser General Public --
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-- License along with this library; if not, write to the Free Software --
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
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-- --
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-------------------------------------------------------------------------------
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--
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--
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-- Author: Roland Höller
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--
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-- Filename: dcml_adjust_rtl.vhd
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--
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-- Date of Creation: Mon Aug 9 12:14:48 1999
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--
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-- Version: $Revision: 1.4 $
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--
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-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $
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--
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--
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-- Description: Combinational design to calculate the decimal
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-- representation (BCD) of a data bus.
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--
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--
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--
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--
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-------------------------------------------------------------------------------
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architecture rtl of dcml_adjust is
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begin -- rtl
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p_calc_adjst: process (data_i, cy_i)
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variable v_cy : std_logic_vector((DWIDTH-1)/4 downto 0);
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variable v_nxtcy : std_logic;
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variable v_tmpda : unsigned(DWIDTH downto 0);
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variable v_tmpda1 : unsigned(4 downto 0);
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variable v_compvl : unsigned(3 downto 0);
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begin -- process p_calc_adjst
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v_tmpda(DWIDTH-1 downto 0) := unsigned(data_i);
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v_tmpda(DWIDTH) := '0';
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v_cy := cy_i;
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v_nxtcy := '0';
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for i in 0 to (DWIDTH-1)/4 loop
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if DWIDTH-i*4 <= 4 then
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-- Calculate the decimal adjustment of the last nibble/rest of bits
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v_compvl := conv_unsigned(0,4);
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v_compvl(DWIDTH-1-i*4 downto 0) := v_tmpda(DWIDTH-1 downto i*4);
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if (v_cy(i) = '1') or (v_compvl > conv_unsigned(9,4)) then
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if DWIDTH-i*4 > 2 then
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v_tmpda(DWIDTH downto i*4) := v_tmpda(DWIDTH-1 downto i*4) +
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conv_unsigned(6,v_tmpda(DWIDTH downto i*4)'LENGTH);
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else
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v_tmpda(DWIDTH downto i*4) := v_tmpda(DWIDTH-1 downto i*4) +
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conv_unsigned(2,v_tmpda(DWIDTH downto i*4)'LENGTH);
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end if;
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end if;
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-- An already set intermediate carry flag must not be lost.
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v_cy(i) := v_tmpda(DWIDTH) or v_cy(i);
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else
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-- Calculate the decimal adjustment of all nibbles, but the last one.
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v_compvl := v_tmpda(i*4+3 downto i*4);
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v_tmpda1 := conv_unsigned(0,5);
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if (v_cy(i) = '1') or (v_compvl > conv_unsigned(9,4)) then
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for j in i to (DWIDTH-1)/4 loop
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if DWIDTH-1 > j*4+3 then
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-- Calculate all subsequent nibbles from the actual position up
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-- to the one before the last.
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if j=i then
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v_tmpda1 := v_tmpda(j*4+3 downto j*4) +
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conv_unsigned(6,5);
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v_nxtcy := v_tmpda1(4);
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v_tmpda(j*4+3 downto j*4) := v_tmpda1(3 downto 0);
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else
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v_tmpda1 := v_tmpda(j*4+3 downto j*4) +
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conv_unsigned(v_nxtcy,5);
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v_nxtcy := v_tmpda1(4);
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v_tmpda(j*4+3 downto j*4) := v_tmpda1(3 downto 0);
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end if;
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-- An already set intermediate carry flag must not be lost.
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v_cy(j) := v_tmpda1(4) or v_cy(j);
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else
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-- Calculate the last nibble.
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if j=i then
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v_tmpda(DWIDTH downto j*4) := v_tmpda(DWIDTH-1 downto j*4) +
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conv_unsigned(6,v_tmpda(DWIDTH downto j*4)'LENGTH);
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else
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v_tmpda(DWIDTH downto j*4) := v_tmpda(DWIDTH-1 downto j*4) +
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conv_unsigned(v_nxtcy,v_tmpda(DWIDTH downto j*4)'LENGTH);
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end if;
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-- An already set intermediate carry flag must not be lost.
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v_cy(j) := v_tmpda(DWIDTH) or v_cy(j);
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end if;
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end loop; -- j
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end if;
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end if;
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end loop; -- i
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-- Generate outputs
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cy_o <= v_cy(v_cy'HIGH);
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data_o <= std_logic_vector(v_tmpda(DWIDTH-1 downto 0));
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end process p_calc_adjst;
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end rtl;
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