mirror of
https://github.com/Gehstock/Mist_FPGA.git
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89 lines
2.4 KiB
VHDL
89 lines
2.4 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- SID 6581 (voice)
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--
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-- This piece of VHDL code describes a single SID voice (sound channel)
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--
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-------------------------------------------------------------------------------
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-- to do: - better resolution of result signal voice, this is now only 12bits,
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-- but it could be 20 !! Problem, it does not fit the PWM-dac
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.numeric_std.all;
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-------------------------------------------------------------------------------
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--
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-- Delta-Sigma DAC
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--
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-- Refer to Xilinx Application Note XAPP154.
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--
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-- This DAC requires an external RC low-pass filter:
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--
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-- dac_o 0---XXXXX---+---0 analog audio
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-- 3k3 |
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-- === 4n7
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-- |
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-- GND
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--
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-------------------------------------------------------------------------------
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--Implementation Digital to Analog converter
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entity pwm_sddac is
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generic (
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msbi_g : integer := 9
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);
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port (
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clk_i : in std_logic;
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reset : in std_logic;
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dac_i : in std_logic_vector(msbi_g downto 0);
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dac_o : out std_logic
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);
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end pwm_sddac;
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architecture rtl of pwm_sddac is
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signal sig_in : unsigned(msbi_g+2 downto 0) := (others => '0');
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begin
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seq: process (clk_i, reset)
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begin
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if reset = '1' then
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sig_in <= to_unsigned(2**(msbi_g+1), sig_in'length);
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dac_o <= '0';
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elsif rising_edge(clk_i) then
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sig_in <= sig_in + unsigned(sig_in(msbi_g+2) & sig_in(msbi_g+2) & dac_i);
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dac_o <= sig_in(msbi_g+2);
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end if;
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end process seq;
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end rtl;
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.numeric_std.all;
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entity pwm_sdadc is
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port (
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clk : in std_logic; -- main clock signal (the higher the better)
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reset : in std_logic; --
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ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
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ADC_in : in std_logic -- "analog" paddle input pin
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);
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end pwm_sdadc;
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-- Dummy implementation (no real A/D conversion performed)
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architecture rtl of pwm_sdadc is
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begin
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process (clk, ADC_in)
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begin
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if ADC_in = '1' then
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ADC_out <= (others => '1');
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else
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ADC_out <= (others => '0');
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end if;
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end process;
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end rtl;
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