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96 lines
2.8 KiB
Verilog
96 lines
2.8 KiB
Verilog
/* This file is part of JT51.
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JT51 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT51 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT51. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 27-10-2016
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*/
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`timescale 1ns / 1ps
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module jt51_pm(
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input [6:0] kc_I,
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input [5:0] kf_I,
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input [8:0] mod_I,
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input add,
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output reg [12:0] kcex
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);
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reg [9:0] lim;
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reg [13:0] kcex0, kcex1;
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reg [1:0] extra;
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reg [6:0] kcin;
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reg carry;
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always @(*) begin: kc_input_cleaner
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{ carry, kcin } = kc_I[1:0]==2'd3 ? { 1'b0, kc_I } + 8'd1 : {1'b0,kc_I};
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end
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always @(*) begin : addition
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lim = { 1'd0, mod_I } + { 4'd0, kf_I };
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case( kcin[3:0] )
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default:
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if( lim>=10'd448 ) extra = 2'd2;
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else if( lim>=10'd256 ) extra = 2'd1;
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else extra = 2'd0;
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4'd1,4'd5,4'd9,4'd13:
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if( lim>=10'd384 ) extra = 2'd2;
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else if( lim>=10'd192 ) extra = 2'd1;
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else extra = 2'd0;
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4'd2,4'd6,4'd10,4'd14:
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if( lim>=10'd512 ) extra = 2'd3;
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else if( lim>=10'd320 ) extra = 2'd2;
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else if( lim>=10'd128 ) extra = 2'd1;
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else extra = 2'd0;
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endcase
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kcex0 = {1'b0,kcin,kf_I} + { 6'd0, extra, 6'd0 } + { 5'd0, mod_I };
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kcex1 = kcex0[7:6]==2'd3 ? kcex0 + 14'd64 : kcex0;
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end
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reg signed [9:0] slim;
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reg [1:0] sextra;
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reg [13:0] skcex0, skcex1;
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always @(*) begin : subtraction
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slim = { 1'd0, mod_I } - { 4'd0, kf_I };
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case( kcin[3:0] )
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default:
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if( slim>=10'sd449 ) sextra = 2'd3;
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else if( slim>=10'sd257 ) sextra = 2'd2;
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else if( slim>=10'sd65 ) sextra = 2'd1;
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else sextra = 2'd0;
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4'd1,4'd5,4'd9,4'd13:
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if( slim>=10'sd321 ) sextra = 2'd2;
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else if( slim>=10'sd129 ) sextra = 2'd1;
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else sextra = 2'd0;
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4'd2,4'd6,4'd10,4'd14:
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if( slim>=10'sd385 ) sextra = 2'd2;
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else if( slim>=10'sd193 ) sextra = 2'd1;
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else sextra = 2'd0;
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endcase
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skcex0 = {1'b0,kcin,kf_I} - { 6'd0, sextra, 6'd0 } - { 5'd0, mod_I };
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skcex1 = skcex0[7:6]==2'd3 ? skcex0 - 14'd64 : skcex0;
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end
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always @(*) begin : mux
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if ( add )
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kcex = kcex1[13] | carry ? {3'd7, 4'd14, 6'd63} : kcex1[12:0];
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else
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kcex = carry ? {3'd7, 4'd14, 6'd63} : (skcex1[13] ? 13'd0 : skcex1[12:0]);
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end
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endmodule
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