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200 lines
6.8 KiB
Systemverilog
200 lines
6.8 KiB
Systemverilog
//============================================================================
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// Irem M72 for MiSTer FPGA - PAL address decoders
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//
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// Copyright (C) 2022 Martin Donlon
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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// http://wiki.pldarchive.co.uk/index.php?title=M72-R-3A
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import m72_pkg::*;
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module address_translator
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(
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input logic [19:0] A,
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input logic [15:0] data,
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input logic [1:0] bytesel,
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input logic rd,
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input logic wr,
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input board_cfg_t board_cfg,
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input logic DBEN,
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input logic M_IO,
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output logic ls245_en, // TODO this signal might be better named
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output [24:0] sdr_addr,
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output writable,
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output bg_a_memrq, // CHARA
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output bg_b_memrq, // CHARA
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output bg_palette_memrq, // CHARA_P
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output sprite_memrq, //
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output sprite_palette_memrq, // OBJ_P
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output sound_memrq,
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output sprite_dma,
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output [1:0] iset,
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output [15:0] iset_data,
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output snd_latch1_wr,
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output snd_latch2_wr
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);
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assign snd_latch1_wr = ~M_IO & wr & ( A[7:0] == 8'h00 );
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assign snd_latch2_wr = (board_cfg.m84) ? 1'b0 : ( ~M_IO & wr & ( A[7:0] == 8'hc0));
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always_comb begin
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case (board_cfg.memory_map)
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0: begin
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casex (A[19:16])
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4'b010x: begin ls245_en = DBEN & M_IO; writable = 1; sdr_addr = REGION_CPU_RAM.base_addr[24:0] | A[16:0]; end
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4'b00xx: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:0] | A[17:0]; end
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4'b1111: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:0] | A[17:0]; end
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default: begin ls245_en = 0; writable = 0; sdr_addr = 24'd0; end
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endcase
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end
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1: begin
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casex (A[19:16])
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4'b1010: begin ls245_en = DBEN & M_IO; writable = 1; sdr_addr = REGION_CPU_RAM.base_addr[24:0] | A[16:0]; end
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4'b0xxx: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:0] | A[18:0]; end
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4'b1111: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:0] | A[18:0]; end
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default: begin ls245_en = 0; writable = 0; sdr_addr = 24'd0; end
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endcase
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end
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2: begin
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casex (A[19:16])
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4'b100x: begin ls245_en = DBEN & M_IO; writable = 1; sdr_addr = REGION_CPU_RAM.base_addr[24:0] | A[16:0]; end
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4'b0xxx: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:0] | A[18:0]; end
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4'b1111: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:0] | A[18:0]; end
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default: begin ls245_en = 0; writable = 0; sdr_addr = 24'd0; end
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endcase
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end
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3,4: begin
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casex (A[19:16])
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4'b1110: begin ls245_en = DBEN & M_IO; writable = 1; sdr_addr = REGION_CPU_RAM.base_addr[24:0] | A[16:0]; end
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4'b0xxx: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:0] | A[18:0]; end
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4'b1111: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:0] | A[18:0]; end
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default: begin ls245_en = 0; writable = 0; sdr_addr = 24'd0; end
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endcase
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end
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default: begin
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ls245_en = 0;
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writable = 0;
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sdr_addr = 0;
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end
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endcase
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end
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always_comb begin
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bg_a_memrq = 0;
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bg_b_memrq = 0;
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bg_palette_memrq = 0;
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sprite_memrq = 0;
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sprite_palette_memrq = 0;
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sound_memrq = 0;
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case (board_cfg.memory_map)
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// M84 rtype2
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3: begin
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casex (A[19:12])
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// 0xc0xxx
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8'b1100_0000: sprite_memrq = 1;
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// 0xc8xxx
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8'b1100_1000: sprite_palette_memrq = 1;
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// 0xd8xxx
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8'b1101_1000: bg_palette_memrq = 1;
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// 0xd0000 - 0xd3fff
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8'b1101_00xx: bg_a_memrq = 1;
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// 0xd4000 - 0xd7fff
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8'b1101_01xx: bg_b_memrq = 1;
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default: begin end// nothing
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endcase
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end
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// M84 Hammerin' Harry
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4: begin
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casex (A[19:12])
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// 0xc0xxx
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8'b1100_0000: sprite_memrq = 1;
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// 0xa0xxx
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8'b1010_0000: sprite_palette_memrq = 1;
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// 0xa8xxx
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8'b1010_1000: bg_palette_memrq = 1;
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// 0xd0000 - 0xd3fff
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8'b1101_00xx: bg_a_memrq = 1;
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// 0xd4000 - 0xd7fff
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8'b1101_01xx: bg_b_memrq = 1;
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default: begin end// nothing
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endcase
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end
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// M72
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default: begin
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casex (A[19:12])
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// 0xc0xxx
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8'b1100_0000: sprite_memrq = 1;
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// 0xc8xxx
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8'b1100_1000: sprite_palette_memrq = 1;
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// 0xccxxx
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8'b1100_1100: bg_palette_memrq = 1;
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// 0xd0000 - 0xd3fff
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8'b1101_00xx: bg_a_memrq = 1;
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// 0xd8000 - 0xdbfff
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8'b1101_10xx: bg_b_memrq = 1;
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// 0xexxxx
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8'b1110_xxxx: sound_memrq = 1;
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default: begin end// nothing
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endcase
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end
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endcase
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end
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always_comb begin
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sprite_dma = 0;
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iset_data = 16'd0;
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iset = 2'b00;
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// M84
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if (board_cfg.m84) begin
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if (M_IO & wr) begin
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sprite_dma = A == 20'hbc000;
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if (A == 20'hb0000) begin
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iset = bytesel;
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iset_data = data;
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end else if (A == 20'hb0001) begin
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iset = 2'b10;
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iset_data = { data[7:0], 8'h00 };
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end
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end
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end else begin
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if (!M_IO & wr) begin
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sprite_dma = A == 8'h04;
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if (A == 8'h06) begin
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iset = 2'b01;
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iset_data = { 8'h00, data[7:0] };
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end else if (A == 8'h07) begin
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iset = 2'b10;
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iset_data = { data[7:0], 8'h00 };
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end
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end
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end
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end
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endmodule
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