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45 lines
1011 B
VHDL
45 lines
1011 B
VHDL
--
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-- GEN_CLK.vhd
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--
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-- GENERATOR of CLOCK.
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--
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-- Copyright (C)2001 SEILEBOST
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-- All rights reserved.
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--
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-- $Id: GEN_CLK.vhd, v0.42 2002/01/03 00:00:00 SEILEBOST $
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--
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-- Generate secondary CLK from CLK_MASTER
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-- CLK : Clock Master, 16 MHz
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-- CLK_16 : for the tone generator,
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-- CLK_256 : for the envelope generator
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity GEN_CLK is
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Port ( CLK : in std_logic;
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RST : in std_logic;
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CLK_16 : out std_logic;
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CLK_256 : out std_logic
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);
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end GEN_CLK;
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architecture Behavioral of GEN_CLK is
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SIGNAL COUNT : std_logic_vector(7 downto 0);
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begin
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PROCESS(CLK, RST)
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BEGIN
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if (RST = '1') then
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COUNT <= (OTHERS => '0');
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elsif (CLK'event and CLK = '1') then
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COUNT <= COUNT + 1;
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CLK_16 <= COUNT(3);
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CLK_256 <= COUNT(7);
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end if;
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END PROCESS;
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end Behavioral;
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