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48 lines
1.5 KiB
Systemverilog
48 lines
1.5 KiB
Systemverilog
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86. If not, see <http://www.gnu.org/licenses/>.
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task do_mul;
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output [31:0] out;
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input is_8_bit;
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input [15:0] a;
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input [15:0] b;
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input [15:0] flags_in;
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output [15:0] flags_out;
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input is_signed;
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begin
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flags_out = flags_in;
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flags_out[ZF_IDX] = 1'b0;
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out = 32'b0;
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if (!is_8_bit) begin
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if (is_signed)
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out[31:0] = {{16{a[15]}}, a} * {{16{b[15]}}, b};
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else
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out[31:0] = {16'b0, a} * {16'b0, b};
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flags_out[CF_IDX] = |out[31:16];
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flags_out[OF_IDX] = |out[31:16];
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end else begin
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if (is_signed)
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out = {16'b0, {{8{a[7]}}, a[7:0]} * {{8{b[7]}}, b[7:0]}};
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else
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out = {16'b0, {8'b0, a[7:0]} * {8'b0, b[7:0]}};
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flags_out[CF_IDX] = |out[15:8];
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flags_out[OF_IDX] = |out[15:8];
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end
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end
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endtask
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