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88 lines
2.1 KiB
VHDL
88 lines
2.1 KiB
VHDL
--
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-- 48K RAM comprised of three smaller 16K RAMs
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--
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-- (c) 2012 d18c7db(a)hotmail
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--
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-- This program is free software; you can redistribute it and/or modify it under
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-- the terms of the GNU General Public License version 3 or, at your option,
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-- any later version as published by the Free Software Foundation.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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--
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-- For full details, see the GNU General Public License at www.gnu.org/licenses
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--only 32k so we can use Internal BRAM
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity ram48k is
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port (
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clk : in std_logic;
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cs : in std_logic;
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oe : in std_logic;
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we : in std_logic;
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addr : in std_logic_vector(15 downto 0);
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di : in std_logic_vector( 7 downto 0);
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do : out std_logic_vector( 7 downto 0)
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);
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end;
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architecture RTL of ram48k is
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signal ro0 : std_logic_vector(7 downto 0);--, ro1, ro2
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-- signal cs0, cs1, cs2 : std_logic := '0';
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begin
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-- cs0 <= '1' when cs='1' and addr(15 downto 14)="00" else '0';
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-- cs1 <= '1' when cs='1' and addr(15 downto 14)="01" else '0';
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-- cs2 <= '1' when cs='1' and addr(15 downto 14)="10" else '0';
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do <=
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ro0 when oe='1' and cs='1' else -- and cs0='1' else
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-- ro1 when oe='1' and cs1='1' else
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-- ro2 when oe='1' and cs2='1' else
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(others=>'0');
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RAM_0000_3FFF : entity work.spram--32k
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generic map (
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widthad_a => 15,
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width_a => 8)
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port map (
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address => addr(14 downto 0),
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clock => clk,
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data => di,
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wren => we,
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q => ro0
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);
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--RAM_4000_7FFF : entity work.spram
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-- generic map (
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-- widthad_a => 14,
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-- width_a => 8)
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-- port map (
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-- address => addr(13 downto 0),
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-- clock => clk,
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-- data => di,
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-- wren => we,
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-- q => ro1
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-- );
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--RAM_8000_BFFF : entity work.spram
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-- generic map (
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-- widthad_a => 14,
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-- width_a => 8)
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-- port map (
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-- address => addr(13 downto 0),
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-- clock => clk,
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-- data => di,
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-- wren => we,
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-- q => ro2
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-- );
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end RTL;
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