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https://github.com/Gehstock/Mist_FPGA.git
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53 lines
1.6 KiB
Verilog
53 lines
1.6 KiB
Verilog
/*MIT License
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Copyright (c) 2019 Gregory Hogan (Soltan_G42)
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.*/
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`timescale 1 ps / 1 ps
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module blockade_lpf
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(
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input clk,
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input reset,
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input signed [15:0] in,
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output signed [15:0] out
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);
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reg [9:0] div = 64;
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reg signed [17:0] A2;
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reg signed [17:0] B2;
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reg signed [17:0] B1;
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wire signed [15:0] audio_post_lpf1;
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// Parameters calculated for a cut-off frequency of 723.43Hz
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always @ (*) begin
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A2 = -18'd32312;
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B1 = 18'd228;
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B2 = 18'd228;
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end
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iir_1st_order lpf6db(.clk(clk),
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.reset(reset),
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.div(div),
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.A2(A2),
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.B1(B1),
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.B2(B2),
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.in(in),
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.out(audio_post_lpf1));
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assign out = audio_post_lpf1;
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endmodule |