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77 lines
2.1 KiB
Verilog
77 lines
2.1 KiB
Verilog
/* This file is part of JT89.
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JT89 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT89 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT89. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: March, 8th 2017
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This work was originally based in the implementation found on the
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SMS core of MiST
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*/
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module jt89_noise(
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input clk,
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(* direct_enable = 1 *) input clk_en,
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input rst,
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input clr,
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input [2:0] ctrl3,
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input [3:0] vol,
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input [9:0] tone2,
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output [8:0] snd
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);
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reg [15:0] shift;
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reg [10:0] cnt;
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reg update;
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jt89_vol u_vol(
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.rst ( rst ),
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.clk ( clk ),
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.clk_en ( clk_en ),
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.din ( shift[0] ),
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.vol ( vol ),
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.snd ( snd )
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);
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always @(posedge clk)
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if( rst ) begin
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cnt <= 'd0;
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end else if( clk_en ) begin
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if( cnt==11'd1 ) begin
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case( ctrl3[1:0] )
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2'd0: cnt <= 11'h20; // clk_en already divides by 16
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2'd1: cnt <= 11'h40;
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2'd2: cnt <= 11'h80;
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2'd3: cnt <= (tone2 == 0) ? 11'h02 : {tone2, 1'b0};
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endcase
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end else begin
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cnt <= cnt-11'b1;
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end
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end
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wire fb = ctrl3[2]?(shift[0]^shift[3]):shift[0];
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always @(posedge clk)
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if( rst || clr )
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shift <= { 1'b1, 15'd0 };
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else if( clk_en ) begin
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if( cnt==1 ) begin
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shift <= (|shift == 1'b0) ? {1'b1, 15'd0 } : {fb, shift[15:1]};
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end
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end
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endmodule
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