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98 lines
2.1 KiB
Verilog
98 lines
2.1 KiB
Verilog
/* This file is part of JT51.
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JT51 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT51 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT51. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 27-10-2016
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*/
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`timescale 1ns / 1ps
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module jt51_lin2exp(
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input [15:0] lin,
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output reg [9:0] man,
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output reg [2:0] exp
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);
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always @(*) begin
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casez( lin[15:9] )
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// negative numbers
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7'b10?????: begin
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man = lin[15:6];
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exp = 3'd7;
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end
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7'b110????: begin
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man = lin[14:5];
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exp = 3'd6;
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end
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7'b1110???: begin
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man = lin[13:4];
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exp = 3'd5;
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end
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7'b11110??: begin
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man = lin[12:3];
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exp = 3'd4;
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end
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7'b111110?: begin
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man = lin[11:2];
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exp = 3'd3;
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end
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7'b1111110: begin
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man = lin[10:1];
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exp = 3'd2;
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end
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7'b1111111: begin
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man = lin[ 9:0];
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exp = 3'd1;
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end
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// positive numbers
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7'b01?????: begin
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man = lin[15:6];
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exp = 3'd7;
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end
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7'b001????: begin
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man = lin[14:5];
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exp = 3'd6;
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end
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7'b0001???: begin
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man = lin[13:4];
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exp = 3'd5;
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end
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7'b00001??: begin
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man = lin[12:3];
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exp = 3'd4;
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end
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7'b000001?: begin
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man = lin[11:2];
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exp = 3'd3;
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end
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7'b0000001: begin
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man = lin[10:1];
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exp = 3'd2;
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end
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7'b0000000: begin
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man = lin[ 9:0];
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exp = 3'd1;
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end
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default: begin
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man = lin[9:0];
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exp = 3'd1;
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end
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endcase
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end
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endmodule
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