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704 lines
15 KiB
C
704 lines
15 KiB
C
/* $Id: inlndos.h,v 1.2 1999/01/03 02:06:05 sybalsky Exp $ (C) Copyright Venue, All Rights Reserved */
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/************************************************************************/
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/* */
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/* (C) Copyright 1991, 1992 Venue. All Rights Reserved. */
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/* Manufactured in the United States of America. */
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/* */
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/************************************************************************/
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/************************************************************************/
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/* */
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/* I N L I N E P S 2 . H */
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/* */
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/* INLINE definitions for 386 machines, compiled with gcc. */
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/* */
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/* This file consists of 3 sections: */
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/* */
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/* inline static functions for use anywhere in Medley */
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/* (e.g., the byte-swapping functions) */
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/* */
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/* #defines and static inline functions for the dispatch */
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/* loop (e.g., IDIFFERENCE), relying on the register */
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/* conventions that hold in that part of the code */
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/* */
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/* #defines and static inline functions for other */
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/* specific files (e.g., the arithmetic functions, */
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/* free-variable lookup, etc.), relying on the register */
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/* conventions in the respective files. */
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/* */
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/* */
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/* */
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/* */
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/* */
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/* */
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/* */
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/* */
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/* */
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/* */
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/* R E G I S T E R C O N V E N T I O N S */
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/* */
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/* The following conventions hold in the dispatch loop, */
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/* and are set up by ... asm("...") decls in xc.c: */
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/* */
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/* esi pccache - the current PC */
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/* edi cspcache - the current lisp stack ptr. */
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/* ebx tscache - the top-of-stack item. */
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/* */
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/* */
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/* Register conventions within arithmetic functions in the files */
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/* arithops.c etc.: */
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/* */
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/* esi first argument to the function */
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/* edi second argument to the function */
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/* */
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/************************************************************************/
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/************************************************************************/
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/* */
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/* G E N E R A L - P U R P O S E I N L I N E F U N C T I O N S */
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/* */
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/* These functions don't rely on conventions. */
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/* */
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/************************************************************************/
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/************************************************************************/
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/* */
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/* */
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/* */
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/* */
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/* */
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/************************************************************************/
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/* undefine these macros so we use the 386i inline code */
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#undef Get_BYTE_PCMAC0
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#undef Get_BYTE_PCMAC1
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#undef Get_BYTE_PCMAC2
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#undef Get_BYTE_PCMAC3
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#define Get_BYTE_PCMAC0 Get_BYTE_PCMAC0fn(pccache)
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#define Get_BYTE_PCMAC1 Get_BYTE_PCMAC1fn(pccache)
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#define Get_BYTE_PCMAC2 Get_BYTE_PCMAC2fn(pccache)
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#define Get_BYTE_PCMAC3 Get_BYTE_PCMAC3fn(pccache)
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extern inline unsigned int Get_BYTE_PCMAC0fn (pccache)
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unsigned int pccache;
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{
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unsigned int word;
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asm("lea %0,-1[%1] \n\
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xor %0,3 \n\
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movzx %0,BYTE PTR [%0] \n\
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" : "=r" (word) : "r" (pccache) );
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return(word);
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}
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extern inline unsigned int Get_BYTE_PCMAC1fn (pccache)
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unsigned int pccache;
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{
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unsigned int word;
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asm("lea %0,[%1] \n\
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xor %0,3 \n\
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movzx %0,BYTE PTR [%0] \n\
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" : "=r" (word) : "r" (pccache) );
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return(word);
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}
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extern inline unsigned int Get_BYTE_PCMAC2fn (pccache)
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unsigned int pccache;
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{
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unsigned int word;
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asm("lea %0,1[%1] \n\
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xor %0,3 \n\
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movzx %0,BYTE PTR [%0] \n\
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" : "=r" (word) : "r" (pccache) );
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return(word);
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}
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extern inline unsigned int Get_BYTE_PCMAC3fn (pccache)
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unsigned int pccache;
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{
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unsigned int word;
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asm("lea %0,2[%1] \n\
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xor %0,3 \n\
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movzx %0,BYTE PTR [%0] \n\
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" : "=r" (word) : "r" (pccache) );
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return(word);
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}
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#undef Get_DLword_PCMAC0
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#undef Get_DLword_PCMAC1
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#undef Get_DLword_PCMAC2
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#undef Get_DLword_PCMAC3
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#define Get_DLword_PCMAC0 Get_DLword_PCMAC0fn(pccache)
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#define Get_DLword_PCMAC1 Get_DLword_PCMAC1fn(pccache)
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#define Get_DLword_PCMAC2 Get_DLword_PCMAC2fn(pccache)
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#define Get_DLword_PCMAC3 Get_DLword_PCMAC3fn(pccache)
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extern inline unsigned int Get_DLword_PCMAC0fn(pccache)
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unsigned int pccache;
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{
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unsigned int word asm("ax");
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asm("mov edx,%1 \n\
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xor dl,3 \n\
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movzx eax, byte ptr [edx] \n\
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lea edx,-1[%1] \n\
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xor dl,3 \n\
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mov ah, byte ptr [edx] \n\
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" : "=r" (word) : "r" (pccache) : "dx" );
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return(word);
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}
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extern inline unsigned int Get_DLword_PCMAC1fn(pccache)
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unsigned int pccache;
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{
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unsigned int word asm("ax");
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asm("lea edx,1[%1] \n\
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xor dl,3 \n\
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movzx eax, byte ptr [edx] \n\
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lea edx,[%1] \n\
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xor dl,3 \n\
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mov ah, byte ptr [edx] \n\
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" : "=r" (word) : "r" (pccache) : "dx" );
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return(word);
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}
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extern inline unsigned int Get_DLword_PCMAC2fn(pccache)
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unsigned int pccache;
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{
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unsigned int word asm("ax");
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asm("lea edx,2[%1] \n\
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xor dl,3 \n\
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movzx eax, byte ptr [edx] \n\
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lea edx,1[%1] \n\
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xor dl,3 \n\
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mov ah, byte ptr [edx] \n\
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" : "=r" (word) : "r" (pccache) : "dx" );
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return(word);
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}
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extern inline unsigned int Get_DLword_PCMAC3fn(pccache)
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unsigned int pccache;
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{
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unsigned int word asm("ax");
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asm("lea edx,3[%1] \n\
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xor dl,3 \n\
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movzx eax, byte ptr [edx] \n\
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lea edx,2[%1] \n\
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xor dl,3 \n\
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mov ah, byte ptr [edx] \n\
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" : "=r" (word) : "r" (pccache) : "dx" );
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return(word);
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}
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#undef Get_Pointer_PCMAC0
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#undef Get_Pointer_PCMAC1
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#undef Get_Pointer_PCMAC2
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#define Get_Pointer_PCMAC0 Get_Pointer_PCMAC0fn(pccache)
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#define Get_Pointer_PCMAC1 Get_Pointer_PCMAC1fn(pccache)
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#define Get_Pointer_PCMAC2 Get_Pointer_PCMAC2fn(pccache)
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extern inline const unsigned int Get_Pointer_PCMAC0fn(pccache)
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unsigned int pccache;
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{
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unsigned int word asm("ax");
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asm("lea edx,-1[%1] \n\
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xor dl,3 \n\
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movzx eax,byte ptr [edx] \n\
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shl eax,16 \n\
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lea edx,1[%1] \n\
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xor dl,3 \n\
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mov al,[edx] \n\
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lea edx,[%1] \n\
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xor dl,3 \n\
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mov ah,[edx] \n\
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" : "=r" (word) : "r" (pccache) : "dx" );
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return(word);
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}
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extern inline const unsigned int Get_Pointer_PCMAC1fn(pccache)
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unsigned int pccache;
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{
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unsigned int word asm("ax");
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asm("lea edx,[%1] \n\
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xor dl,3 \n\
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movzx eax,byte ptr [edx] \n\
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shl eax,16 \n\
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lea edx,2[%1] \n\
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xor dl,3 \n\
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mov al,[edx] \n\
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lea edx,1[%1] \n\
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xor dl,3 \n\
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mov ah,[edx] \n\
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" : "=r" (word) : "r" (pccache) : "dx" );
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return(word);
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}
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extern inline const unsigned int Get_Pointer_PCMAC2fn(pccache)
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unsigned int pccache;
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{
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unsigned int word asm("ax");
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asm("lea edx,1[%1] \n\
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xor dl,3 \n\
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movzx eax,byte ptr [edx] \n\
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shl eax,16 \n\
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lea edx,3[%1] \n\
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xor dl,3 \n\
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mov al,[edx] \n\
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lea edx,2[%1] \n\
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xor dl,3 \n\
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mov ah,[edx] \n\
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" : "=r" (word) : "r" (pccache) : "dx" );
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return(word);
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}
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#undef DIFFERENCE
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#undef IDIFFERENCE
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#define DIFFERENCE { \
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fast_op_difference(POP_TOS_1); \
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fast1_dispatcher(); \
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diff_err: \
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asm volatile("diff_err:"); \
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asm volatile("add bl,7"); \
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asm volatile("ror ebx,15"); \
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N_OP_POPPED_CALL_2(N_OP_difference, GET_POPPED); \
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}
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extern inline void fast_op_difference(LispPTR value)
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{
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asm volatile("\
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mov eax,%0 \n\
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rol ebx,15 \n\
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sub bl,7 \n\
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jne diff_err \n\
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rol eax,17 \n\
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sub al,7 \n\
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jne diff_err \n\
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sub eax,ebx \n\
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jo diff_err \n\
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ror eax,15 \n\
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or eax,917504 \n\
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mov ebx,eax \
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" : : "g" (value) : "ax" );
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}
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#define IDIFFERENCE { \
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fast_op_idifference(POP_TOS_1); \
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fast1_dispatcher(); \
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idiff_err: \
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asm volatile("idiff_err:"); \
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asm volatile("add bl,7"); \
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asm volatile("ror ebx,15"); \
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N_OP_POPPED_CALL_2(N_OP_idifference, GET_POPPED); \
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}
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extern inline void fast_op_idifference(LispPTR value)
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{
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asm volatile("\
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mov eax,%0 \n\
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rol ebx,15 \n\
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sub bl,7 \n\
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jne idiff_err \n\
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rol eax,17 \n\
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sub al,7 \n\
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jne idiff_err \n\
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sub eax,ebx \n\
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jo idiff_err \n\
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ror eax,15 \n\
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or eax,917504 \n\
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mov ebx,eax \
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" : : "g" (value) : "ax" );
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}
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#undef IDIFFERENCE_N
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#define IDIFFERENCE_N(n) { \
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fast_op_idifferencen(n); \
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fast2_dispatcher(); \
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idiffn_err: \
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asm("idiffn_err2:"); \
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asm volatile("add ebx,eax ; undo the sub"); \
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asm("idiffn_err:"); \
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asm volatile("add bl,7"); \
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asm volatile("ror ebx,15"); \
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N_OP_CALL_1d(N_OP_idifferencen, n); \
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}
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extern inline void fast_op_idifferencen(LispPTR value)
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{
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asm volatile("\
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mov eax,%0 \n\
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rol eax,15 \n\
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rol ebx,15 \n\
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sub bl,7 \n\
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jne idiffn_err \n\
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sub ebx,eax \n\
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jo idiffn_err2 \n\
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ror ebx,15 \n\
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or ebx,917504 \n\
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" : : "g" (value) : "ax" );
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}
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#undef PLUS2
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#undef IPLUS2
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#define PLUS2 { \
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fast_op_plus(POP_TOS_1); \
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fast1_dispatcher(); \
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plus_err: \
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asm volatile("plus_err:"); \
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asm volatile("add bl,7"); \
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asm volatile("ror ebx,15"); \
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N_OP_POPPED_CALL_2(N_OP_plus2, GET_POPPED); \
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}
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extern inline void fast_op_plus(LispPTR value)
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{
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asm volatile("\
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mov eax,%0 \n\
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rol ebx,15 \n\
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sub bl,7 \n\
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jne plus_err \n\
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rol eax,15 \n\
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sub al,7 \n\
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jne plus_err \n\
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add eax,ebx \n\
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jo plus_err \n\
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ror eax,15 \n\
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or eax,917504 \n\
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mov ebx,eax \n\
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" : : "g" (value) : "ax" );
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}
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#define IPLUS2 { \
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fast_op_iplus(POP_TOS_1); \
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fast1_dispatcher(); \
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iplus_err: \
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asm volatile("iplus_err:"); \
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asm volatile("add bl,7"); \
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asm volatile("ror ebx,15"); \
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N_OP_POPPED_CALL_2(N_OP_iplus2, GET_POPPED); \
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}
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extern inline void fast_op_iplus(LispPTR value)
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{
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asm volatile("\
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mov eax,%0 \n\
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rol ebx,15 \n\
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sub bl,7 \n\
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jne iplus_err \n\
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rol eax,15 \n\
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sub al,7 \n\
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jne iplus_err \n\
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add eax,ebx \n\
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jo iplus_err \n\
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ror eax,15 \n\
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or eax,917504 \n\
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mov ebx,eax \n\
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" : : "g" (value) : "ax" );
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}
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#undef IPLUS_N
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#define IPLUS_N(n) { \
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fast_op_iplusn(n); \
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fast2_dispatcher(); \
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iplusn_err: \
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asm("iplusn_err:"); \
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asm volatile("add bl,7"); \
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asm volatile("ror ebx,15"); \
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N_OP_CALL_1d(N_OP_iplusn, n); \
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}
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extern inline void fast_op_iplusn(LispPTR value)
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{
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asm volatile("\
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mov eax,%0 \n\
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rol eax,15 \n\
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rol ebx,15 \n\
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sub bl,7 \n\
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jne iplusn_err \n\
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add eax,ebx \n\
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jo iplusn_err \n\
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ror eax,15 \n\
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or eax,917504 \n\
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mov ebx,eax \n\
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" : : "g" (value) : "ax" );
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}
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#undef GREATERP
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#define GREATERP { \
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fast_op_greaterp(POP_TOS_1); \
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fast1_dispatcher(); \
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greaterp_err: \
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asm("greaterp_err:"); \
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N_OP_POPPED_CALL_2(N_OP_greaterp, GET_POPPED); \
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}
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extern inline void fast_op_greaterp(LispPTR value)
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{
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asm volatile("\
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mov eax,%0 \n\
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mov edx,ebx \n\
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rol edx,15 \n\
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sub dl,7 \n\
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jne greaterp_err \n\
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rol eax,15 \n\
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sub al,7 \n\
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jne greaterp_err \n\
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xor ebx,ebx \n\
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cmp eax,edx \n\
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jle greater_no \n\
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mov ebx,76 \n\
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greater_no: " : : "g" (value) );
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}
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#undef IGREATERP
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#define IGREATERP { \
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fast_op_igreaterp(POP_TOS_1); \
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fast1_dispatcher(); \
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igreaterp_err: \
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asm("igreaterp_err: "); \
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N_OP_POPPED_CALL_2(N_OP_igreaterp, GET_POPPED); \
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}
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extern inline void fast_op_igreaterp(LispPTR value)
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{
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asm volatile("\
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mov eax,%0 \n\
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mov edx,ebx \n\
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rol edx,15 \n\
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sub dl,7 \n\
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jne igreaterp_err \n\
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rol eax,15 \n\
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sub al,7 \n\
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jne igreaterp_err \n\
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xor ebx,ebx \n\
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cmp eax,edx \n\
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jle igreater_no \n\
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mov ebx,76 \n\
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igreater_no: " : : "g" (value) );
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}
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#undef LRSH8
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#define LRSH8 { \
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asm volatile("\
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mov eax,ebx \n\
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rol eax,16 \n\
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cmp ax,0eh \n\
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jne lrsh8_err \n\
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shr bx,8 \n\
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" : : : "ax" ); \
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fast1_dispatcher(); \
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lrsh8_err: \
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asm("lrsh8_err: "); \
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N_OP_CALL_1(N_OP_lrsh8); \
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}
|
|
|
|
#undef LRSH1
|
|
#define LRSH1 { \
|
|
asm volatile("\
|
|
mov eax,ebx \n\
|
|
rol eax,16 \n\
|
|
cmp ax,0eh \n\
|
|
jne lrsh1_err \n\
|
|
shr bx,1 \n\
|
|
" : : : "ax" ); \
|
|
fast1_dispatcher(); \
|
|
lrsh1_err: \
|
|
asm("lrsh1_err: "); \
|
|
N_OP_CALL_1(N_OP_lrsh1); \
|
|
}
|
|
|
|
#undef LLSH8
|
|
#define LLSH8 { \
|
|
asm volatile("\
|
|
mov eax,ebx \n\
|
|
rol eax,16 \n\
|
|
cmp ax,0eh \n\
|
|
jne llsh8_err \n\
|
|
or bh,bh \n\
|
|
jne llsh8_err \n\
|
|
shl bx,8 \n\
|
|
" : : : "ax" ); \
|
|
fast1_dispatcher(); \
|
|
llsh8_err: \
|
|
asm("llsh8_err: "); \
|
|
N_OP_CALL_1(N_OP_llsh8); \
|
|
}
|
|
|
|
#undef LLSH1
|
|
#define LLSH1 { \
|
|
asm volatile("\
|
|
mov eax,ebx \n\
|
|
rol eax,16 \n\
|
|
cmp ax,0eh \n\
|
|
jne llsh1_err \n\
|
|
test bh,80h \n\
|
|
jne llsh1_err \n\
|
|
shl bx,1 \n\
|
|
" : : : "ax" ); \
|
|
fast1_dispatcher(); \
|
|
llsh1_err: \
|
|
asm("llsh1_err: "); \
|
|
N_OP_CALL_1(N_OP_llsh1); \
|
|
}
|
|
|
|
|
|
#undef LOGOR
|
|
#define LOGOR { \
|
|
fast_op_logor(POP_TOS_1); \
|
|
fast1_dispatcher(); \
|
|
logor_err: \
|
|
asm("logor_err:"); \
|
|
asm volatile("ror ebx,15"); \
|
|
N_OP_POPPED_CALL_2(N_OP_logor, GET_POPPED); \
|
|
}
|
|
|
|
extern inline void fast_op_logor(LispPTR value)
|
|
{
|
|
asm volatile("\
|
|
mov eax,%0 \n\
|
|
rol ebx,15 \n\
|
|
cmp bl,7 \n\
|
|
jne logor_err \n\
|
|
rol eax,15 \n\
|
|
cmp al,7 \n\
|
|
jne logor_err \n\
|
|
or ebx,eax \n\
|
|
ror ebx,15 \n\
|
|
" : : "g" (value) : "ax" );
|
|
|
|
}
|
|
|
|
|
|
#undef LOGAND
|
|
#define LOGAND { \
|
|
fast_op_logand(POP_TOS_1); \
|
|
fast1_dispatcher(); \
|
|
logand_err: \
|
|
asm("logand_err: "); \
|
|
asm volatile("ror ebx,15"); \
|
|
N_OP_POPPED_CALL_2(N_OP_logand, GET_POPPED); \
|
|
}
|
|
|
|
extern inline void fast_op_logand(LispPTR value)
|
|
{
|
|
asm volatile("\
|
|
mov eax,%0 \n\
|
|
rol ebx,15 \n\
|
|
cmp bl,7 \n\
|
|
jne logand_err \n\
|
|
rol eax,15 \n\
|
|
cmp al,7 \n\
|
|
jne logand_err \n\
|
|
and ebx,eax \n\
|
|
ror ebx,15 \n\
|
|
" : : "g" (value) : "ax" );
|
|
|
|
}
|
|
|
|
|
|
#undef LOGXOR
|
|
#define LOGXOR { \
|
|
fast_op_logxor(POP_TOS_1); \
|
|
fast1_dispatcher(); \
|
|
logxor_err: \
|
|
asm("logxor_err:"); \
|
|
asm volatile("ror ebx,15"); \
|
|
N_OP_POPPED_CALL_2(N_OP_logxor, GET_POPPED); \
|
|
}
|
|
|
|
extern inline void fast_op_logxor(LispPTR value)
|
|
{
|
|
asm volatile("\
|
|
mov eax,%0 \n\
|
|
rol ebx,15 \n\
|
|
cmp bl,7 \n\
|
|
jne logxor_err \n\
|
|
rol eax,15 \n\
|
|
sub al,7 \n\
|
|
jne logxor_err \n\
|
|
xor ebx,eax \n\
|
|
ror ebx,15 \n\
|
|
" : : "g" (value) : "ax" );
|
|
|
|
}
|
|
|
|
|
|
|
|
#undef N_OP_ADDBASE
|
|
#define N_OP_ADDBASE { \
|
|
fast_op_addbase(POP_TOS_1); \
|
|
fast1_dispatcher(); \
|
|
addbase_err: \
|
|
asm("addbase_err: "); \
|
|
asm volatile("ror ebx,15"); \
|
|
N_OP_POPPED_CALL_2(N_OP_addbase, GET_POPPED); \
|
|
}
|
|
extern inline void fast_op_addbase(LispPTR value)
|
|
{
|
|
asm volatile("\
|
|
mov eax,%0 \n\
|
|
rol ebx,15 \n\
|
|
cmp bl,7 \n\
|
|
jne addbase_err \n\
|
|
sar ebx,15 \n\
|
|
and eax,0ffffffh \n\
|
|
add ebx,eax \n\
|
|
" : : "g" (value) : "ax" );
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#undef N_OP_LOLOC
|
|
#define N_OP_LOLOC { \
|
|
asm volatile(" \
|
|
and %0,0ffffh \n\
|
|
or %0,0e0000h" : "=r" (tscache) : "0" (tscache)); \
|
|
nextop1; }
|
|
|
|
#undef N_OP_HILOC
|
|
#define N_OP_HILOC { \
|
|
asm volatile(" \
|
|
shr %0,16 \n\
|
|
and %0,0ffffh \n\
|
|
or %0,0e0000h" : "=r" (tscache) : "0" (tscache)); \
|
|
nextop1; }
|
|
|
|
#undef N_OP_VAG2
|
|
#define N_OP_VAG2 \
|
|
{ \
|
|
asm(" sub edi,4"); \
|
|
asm(" mov eax,[edi]"); \
|
|
asm(" rol ebx,16"); \
|
|
asm(" mov bx,ax"); \
|
|
asm(" ror ebx,16"); \
|
|
nextop1; }
|
|
|