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Uploaded_11_11_2020

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MicroCoreLabs
2020-11-11 22:45:55 -08:00
parent a3f43cf1d5
commit 0d80a36b30
2 changed files with 744 additions and 744 deletions
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264
MCL86jr/FPGA/src4synth/MCL86jr.v
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@@ -46,57 +46,57 @@
module MCL86jr module MCL86jr
( (
input CORE_CLK, input CORE_CLK,
input CLK, input CLK,
input RESET, input RESET,
input READY, input READY,
input INTR, input INTR,
input NMI, input NMI,
output A19, output A19,
output A18, output A18,
output A17, output A17,
output A16, output A16,
output A15, output A15,
output A14, output A14,
output A13, output A13,
output A12, output A12,
output A11, output A11,
output A10, output A10,
output A9, output A9,
output A8, output A8,
inout AD7, inout AD7,
inout AD6, inout AD6,
inout AD5, inout AD5,
inout AD4, inout AD4,
inout AD3, inout AD3,
inout AD2, inout AD2,
inout AD1, inout AD1,
inout AD0, inout AD0,
output ALE, output ALE,
output INTA_n, output INTA_n,
output RD_n, output RD_n,
output WR_n, output WR_n,
output IOM, output IOM,
output DTR, output DTR,
output DEN, output DEN,
output SSO_n, output SSO_n,
output [18:0] SRAM_A, output [18:0] SRAM_A,
inout [7:0] SRAM_D, inout [7:0] SRAM_D,
output SRAM_CE_n, output SRAM_CE_n,
output SRAM_OE_n, output SRAM_OE_n,
output SRAM_WE_n, output SRAM_WE_n,
output [7:0] LED, output [7:0] LED,
output BUF1_OE_n, output BUF1_OE_n,
output BUF2_OE_n, output BUF2_OE_n,
output BUF2_DIR output BUF2_DIR
); );
@@ -154,8 +154,8 @@ wire [7:0] t_sram_d_out;
spartan6_pll SPARTAN6PLL spartan6_pll SPARTAN6PLL
( (
.CLK_IN1 (CORE_CLK), .CLK_IN1 (CORE_CLK),
.CLK_OUT1 (core_clk_int) .CLK_OUT1 (core_clk_int)
); );
@@ -226,35 +226,35 @@ begin : REGISTER_IOS
t_reset_d2 <= t_reset_d1; t_reset_d2 <= t_reset_d1;
t_reset_d3 <= t_reset_d2; t_reset_d3 <= t_reset_d2;
// Use either the PCjr board reset or an internal timer for a reset // Use either the PCjr board reset or an internal timer for a reset
if ( (t_reset_d3==1'b1 && t_reset_d2==1'b1) || (fpga_config_done==1'b0) ) if ( (t_reset_d3==1'b1 && t_reset_d2==1'b1) || (fpga_config_done==1'b0) )
begin begin
t_reset_d4 <= 1'b1; t_reset_d4 <= 1'b1;
led_int <= 8'b10000000; led_int <= 8'b10000000;
end end
else else
begin begin
t_reset_d4 <= t_reset_d3; t_reset_d4 <= t_reset_d3;
end end
prescaler <= prescaler + 1'b1; prescaler <= prescaler + 1'b1;
prescaler_d <= prescaler[21]; prescaler_d <= prescaler[21];
if (prescaler[26]==1'b1) fpga_config_done <= 1'b1; if (prescaler[26]==1'b1) fpga_config_done <= 1'b1;
// Blink the sweeping LEDs // Blink the sweeping LEDs
if (prescaler_d==1'b0 && prescaler[21]==1'b1) if (prescaler_d==1'b0 && prescaler[21]==1'b1)
begin begin
if (led_go_left==1'b0) if (led_go_left==1'b0)
led_int[7:0] <= {led_int[0] , led_int[7:1] }; led_int[7:0] <= {led_int[0] , led_int[7:1] };
else else
led_int[7:0] <= {led_int[6:0] , led_int[7] }; led_int[7:0] <= {led_int[6:0] , led_int[7] };
if (led_int[6]==1'b1) led_go_left <= 1'b0; if (led_int[6]==1'b1) led_go_left <= 1'b0;
if (led_int[1]==1'b1) led_go_left <= 1'b1; if (led_int[1]==1'b1) led_go_left <= 1'b1;
end end
@@ -266,51 +266,51 @@ end
// BIU Core // BIU Core
//------------------------------------------------------------------------ //------------------------------------------------------------------------
biu_min BIU_CORE biu_min BIU_CORE
( (
.CORE_CLK_INT (core_clk_int), .CORE_CLK_INT (core_clk_int),
.RESET_INT (t_reset_d4), .RESET_INT (t_reset_d4),
.CLK (CLK), .CLK (CLK),
.READY_IN (READY), .READY_IN (READY),
.NMI (NMI), .NMI (NMI),
.INTR (INTR), .INTR (INTR),
.INTA_n (INTA_n), .INTA_n (INTA_n),
.ALE (ALE), .ALE (ALE),
.RD_n (RD_n), .RD_n (RD_n),
.WR_n (WR_n), .WR_n (WR_n),
.SSO_n (SSO_n), .SSO_n (SSO_n),
.IOM (IOM), .IOM (IOM),
.DTR (DTR), .DTR (DTR),
.DEN (DEN), .DEN (DEN),
.AD_OE (t_biu_ad_oe), .AD_OE (t_biu_ad_oe),
.AD_OUT (t_biu_ad_out), .AD_OUT (t_biu_ad_out),
.AD_IN (t_biu_ad_in), .AD_IN (t_biu_ad_in),
.EU_BIU_COMMAND (t_eu_biu_command), .EU_BIU_COMMAND (t_eu_biu_command),
.EU_BIU_DATAOUT (t_eu_biu_dataout), .EU_BIU_DATAOUT (t_eu_biu_dataout),
.EU_REGISTER_R3 (t_eu_register_r3), .EU_REGISTER_R3 (t_eu_register_r3),
.EU_PREFIX_LOCK (t_eu_prefix_lock), .EU_PREFIX_LOCK (t_eu_prefix_lock),
.BIU_DONE (t_biu_done), .BIU_DONE (t_biu_done),
.BIU_CLK_COUNTER_ZERO (t_biu_clk_counter_zero), .BIU_CLK_COUNTER_ZERO (t_biu_clk_counter_zero),
.BIU_SEGMENT ( ), .BIU_SEGMENT ( ),
.BIU_NMI_CAUGHT (t_biu_nmi_caught), .BIU_NMI_CAUGHT (t_biu_nmi_caught),
.BIU_NMI_DEBOUNCE (t_biu_nmi_debounce), .BIU_NMI_DEBOUNCE (t_biu_nmi_debounce),
.BIU_INTR (t_biu_intr), .BIU_INTR (t_biu_intr),
.PFQ_TOP_BYTE (t_pfq_top_byte), .PFQ_TOP_BYTE (t_pfq_top_byte),
.PFQ_EMPTY (t_pfq_empty), .PFQ_EMPTY (t_pfq_empty),
.PFQ_ADDR_OUT (t_pfq_addr_out), .PFQ_ADDR_OUT (t_pfq_addr_out),
.BIU_REGISTER_ES (t_biu_register_es), .BIU_REGISTER_ES (t_biu_register_es),
.BIU_REGISTER_SS (t_biu_register_ss), .BIU_REGISTER_SS (t_biu_register_ss),
.BIU_REGISTER_CS (t_biu_register_cs), .BIU_REGISTER_CS (t_biu_register_cs),
.BIU_REGISTER_DS (t_biu_register_ds), .BIU_REGISTER_DS (t_biu_register_ds),
.BIU_REGISTER_RM (t_biu_register_rm), .BIU_REGISTER_RM (t_biu_register_rm),
.BIU_REGISTER_REG (t_biu_register_reg), .BIU_REGISTER_REG (t_biu_register_reg),
.BIU_RETURN_DATA (t_biu_return_data), .BIU_RETURN_DATA (t_biu_return_data),
.SRAM_A (SRAM_A), .SRAM_A (SRAM_A),
.SRAM_D_OE (t_sram_d_oe), .SRAM_D_OE (t_sram_d_oe),
.SRAM_D_OUT (t_sram_d_out), .SRAM_D_OUT (t_sram_d_out),
.SRAM_D_IN (SRAM_D), .SRAM_D_IN (SRAM_D),
.SRAM_OE_n (SRAM_OE_n), .SRAM_OE_n (SRAM_OE_n),
.SRAM_WE_n (SRAM_WE_n) .SRAM_WE_n (SRAM_WE_n)
); );
@@ -319,31 +319,31 @@ biu_min BIU_CORE
// EU Core // EU Core
//------------------------------------------------------------------------ //------------------------------------------------------------------------
mcl86_eu_core EU_CORE mcl86_eu_core EU_CORE
( (
.CORE_CLK_INT (core_clk_int), .CORE_CLK_INT (core_clk_int),
.RESET_INT (t_reset_d4), .RESET_INT (t_reset_d4),
.TEST_N_INT (1'b1), .TEST_N_INT (1'b1),
.EU_BIU_COMMAND (t_eu_biu_command), .EU_BIU_COMMAND (t_eu_biu_command),
.EU_BIU_DATAOUT (t_eu_biu_dataout), .EU_BIU_DATAOUT (t_eu_biu_dataout),
.EU_REGISTER_R3 (t_eu_register_r3), .EU_REGISTER_R3 (t_eu_register_r3),
.EU_PREFIX_LOCK (t_eu_prefix_lock), .EU_PREFIX_LOCK (t_eu_prefix_lock),
.EU_FLAG_I (t_eu_flag_i), .EU_FLAG_I (t_eu_flag_i),
.BIU_DONE (t_biu_done), .BIU_DONE (t_biu_done),
.BIU_CLK_COUNTER_ZERO (t_biu_clk_counter_zero), .BIU_CLK_COUNTER_ZERO (t_biu_clk_counter_zero),
.BIU_NMI_CAUGHT (t_biu_nmi_caught), .BIU_NMI_CAUGHT (t_biu_nmi_caught),
.BIU_NMI_DEBOUNCE (t_biu_nmi_debounce), .BIU_NMI_DEBOUNCE (t_biu_nmi_debounce),
.BIU_INTR (t_biu_intr), .BIU_INTR (t_biu_intr),
.PFQ_TOP_BYTE (t_pfq_top_byte), .PFQ_TOP_BYTE (t_pfq_top_byte),
.PFQ_EMPTY (t_pfq_empty), .PFQ_EMPTY (t_pfq_empty),
.PFQ_ADDR_OUT (t_pfq_addr_out), .PFQ_ADDR_OUT (t_pfq_addr_out),
.BIU_REGISTER_ES (t_biu_register_es), .BIU_REGISTER_ES (t_biu_register_es),
.BIU_REGISTER_SS (t_biu_register_ss), .BIU_REGISTER_SS (t_biu_register_ss),
.BIU_REGISTER_CS (t_biu_register_cs), .BIU_REGISTER_CS (t_biu_register_cs),
.BIU_REGISTER_DS (t_biu_register_ds), .BIU_REGISTER_DS (t_biu_register_ds),
.BIU_REGISTER_RM (t_biu_register_rm), .BIU_REGISTER_RM (t_biu_register_rm),
.BIU_REGISTER_REG (t_biu_register_reg), .BIU_REGISTER_REG (t_biu_register_reg),
.BIU_RETURN_DATA (t_biu_return_data) .BIU_RETURN_DATA (t_biu_return_data)
); );

950
MCL86jr/FPGA/src4synth/biu_min.v
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