Improvements to the SD Card and EMS drivers. (#31)
* Refactor SD driver the IO to XTMax. * Refactor the EMS driver to support 8MB.
This commit is contained in:
Matthieu Bucchianeri
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GitHub
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53caec7569
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422a4306f2
@@ -2,7 +2,8 @@
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//
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// File Name : XTMax.ino
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// Used on :
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// Author : Ted Fried, MicroCore Labs
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// Authors : Ted Fried, MicroCore Labs
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// Matthieu Bucchianeri
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// Creation : 9/7/2024
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//
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// Description:
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@@ -34,6 +35,10 @@
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// Revision 6 12/14/2024
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// - Made SD LPT base a # define
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//
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// Revision 7 01/12/2024
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// - Refactor SD card I/O
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// - Add support for 16-bit EMS page offsets.
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//
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//------------------------------------------------------------------------
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//
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// Copyright (c) 2024 Ted Fried
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@@ -152,7 +157,12 @@
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#define PSRAM_RESET_VALUE 0x01000000
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#define PSRAM_CLK_HIGH 0x02000000
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#define SD_LPT_BASE 0x378
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#define EMS_BASE_IO 0x260 // Must be a multiple of 8.
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#define EMS_BASE_MEM 0xD0000
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#define EMS_TOTAL_SIZE (8*1024*1024)
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#define SD_BASE 0x280 // Must be a multiple of 2.
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@@ -171,16 +181,10 @@ uint32_t databit_out = 0;
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uint8_t data_in = 0;
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uint8_t isa_data_out = 0;
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uint8_t lpt_data = 0;
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uint8_t lpt_status = 0x6F;
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uint8_t lpt_control = 0xEC;
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uint8_t nibble_in =0;
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uint8_t nibble_out =0;
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uint8_t read_byte =0;
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uint8_t reg_0x260 =0;
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uint8_t reg_0x261 =0;
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uint8_t reg_0x262 =0;
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uint8_t reg_0x263 =0;
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uint16_t ems_frame_pointer[4] = {0, 0, 0, 0};
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uint8_t spi_shift_out =0;
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uint8_t sd_spi_datain =0;
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uint32_t sd_spi_cs_n = 0x0;
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@@ -386,6 +390,9 @@ inline void PSRAM_Configure() {
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// --------------------------------------------------------------------------------------------------
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inline uint8_t PSRAM_Read(uint32_t address_in) {
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if (address_in >= EMS_TOTAL_SIZE) {
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return 0xff;
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}
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// Send Command = Quad Read = 0x0B
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//
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@@ -423,15 +430,17 @@ inline uint8_t PSRAM_Read(uint32_t address_in) {
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GPIO9_DR = PSRAM_RESET_VALUE; // Drive CLK=0 , CS_n=1
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GPIO9_GDIR = 0x3F000000; // Change Data[3:0] to outputs quickly
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return read_byte;
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}
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return read_byte;
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}
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// --------------------------------------------------------------------------------------------------
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// --------------------------------------------------------------------------------------------------
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inline uint8_t PSRAM_Write(uint32_t address_in , int8_t local_data) {
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inline void PSRAM_Write(uint32_t address_in , int8_t local_data) {
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if (address_in >= EMS_TOTAL_SIZE) {
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return;
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}
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// Send Command = Quad Write = 0x02
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//
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@@ -457,9 +466,7 @@ inline uint8_t PSRAM_Write(uint32_t address_in , int8_t local_data) {
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nibble_out = local_data; PSRAM_Write_Clk_Cycle();
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GPIO9_DR = PSRAM_RESET_VALUE; // Drive CLK=0 , CS_n=1
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return read_byte;
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}
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}
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// --------------------------------------------------------------------------------------------------
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@@ -489,14 +496,14 @@ inline void Mem_Read_Cycle() {
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isa_address = ADDRESS_DATA_GPIO6_UNSCRAMBLE;
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if ( (isa_address>=0xE0000) && (isa_address<0xF0000) ) { // Expanded RAM page frame
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if ( (isa_address>=EMS_BASE_MEM) && (isa_address<EMS_BASE_MEM+0x10000) ) { // Expanded RAM page frame
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page_base_address = (isa_address & 0xFC000);
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if (page_base_address == 0xEC000) { psram_address = (reg_0x263<<14) | (isa_address & 0x03FFF); }
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else if (page_base_address == 0xE8000) { psram_address = (reg_0x262<<14) | (isa_address & 0x03FFF); }
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else if (page_base_address == 0xE4000) { psram_address = (reg_0x261<<14) | (isa_address & 0x03FFF); }
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else if (page_base_address == 0xE0000) { psram_address = (reg_0x260<<14) | (isa_address & 0x03FFF); }
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if (page_base_address == (EMS_BASE_MEM | 0xC000)) { psram_address = (ems_frame_pointer[3]<<14) | (isa_address & 0x03FFF); }
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else if (page_base_address == (EMS_BASE_MEM | 0x8000)) { psram_address = (ems_frame_pointer[2]<<14) | (isa_address & 0x03FFF); }
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else if (page_base_address == (EMS_BASE_MEM | 0x4000)) { psram_address = (ems_frame_pointer[1]<<14) | (isa_address & 0x03FFF); }
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else if (page_base_address == (EMS_BASE_MEM | 0x0000)) { psram_address = (ems_frame_pointer[0]<<14) | (isa_address & 0x03FFF); }
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GPIO7_DR = MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_LOW + DATA_OE_n_LOW ; // Assert CHRDY_n=0 to begin wait states
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@@ -511,16 +518,15 @@ inline void Mem_Read_Cycle() {
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
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}
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/*
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XTMax_MEM_Response_Array
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- Array holds value 0,1,2
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0 = unitiailzed - add wait states and snoop
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1 = No wait states and no response
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2 = No wait states and yes respond
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*/
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/*
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XTMax_MEM_Response_Array
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- Array holds value 0,1,2
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0 = unitiailzed - add wait states and snoop
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1 = No wait states and no response
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2 = No wait states and yes respond
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*/
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else if (isa_address<0xA0000) { // "Conventional" RAM
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isa_data_out = Internal_RAM_Read();
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GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
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@@ -564,14 +570,14 @@ inline void Mem_Write_Cycle() {
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isa_address = ADDRESS_DATA_GPIO6_UNSCRAMBLE;
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if ( (isa_address>=0xE0000) && (isa_address<0xF0000) ) { // Expanded RAM page frame
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if ( (isa_address>=EMS_BASE_MEM) && (isa_address<EMS_BASE_MEM+0x10000) ) { // Expanded RAM page frame
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page_base_address = (isa_address & 0xFC000);
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if (page_base_address == 0xEC000) { psram_address = (reg_0x263<<14) | (isa_address & 0x03FFF); }
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else if (page_base_address == 0xE8000) { psram_address = (reg_0x262<<14) | (isa_address & 0x03FFF); }
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else if (page_base_address == 0xE4000) { psram_address = (reg_0x261<<14) | (isa_address & 0x03FFF); }
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else if (page_base_address == 0xE0000) { psram_address = (reg_0x260<<14) | (isa_address & 0x03FFF); }
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if (page_base_address == (EMS_BASE_MEM | 0xC000)) { psram_address = (ems_frame_pointer[3]<<14) | (isa_address & 0x03FFF); }
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else if (page_base_address == (EMS_BASE_MEM | 0x8000)) { psram_address = (ems_frame_pointer[2]<<14) | (isa_address & 0x03FFF); }
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else if (page_base_address == (EMS_BASE_MEM | 0x4000)) { psram_address = (ems_frame_pointer[1]<<14) | (isa_address & 0x03FFF); }
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else if (page_base_address == (EMS_BASE_MEM | 0x0000)) { psram_address = (ems_frame_pointer[0]<<14) | (isa_address & 0x03FFF); }
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GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_HIGH + CHRDY_OUT_LOW + trigger_out;
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_LOW + CHRDY_OE_n_LOW + DATA_OE_n_HIGH; // Steer data mux to Data[7:0] and Assert CHRDY_n=0 to begin wait states
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@@ -592,8 +598,7 @@ inline void Mem_Write_Cycle() {
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GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
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}
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else if (isa_address<0xA0000) { // XTMax stores the full 640 KB conventional memory
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GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_HIGH + CHRDY_OUT_LOW + trigger_out;
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_LOW + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
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@@ -620,13 +625,17 @@ inline void IO_Read_Cycle() {
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isa_address = 0xFFFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
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if ((isa_address&0x0FFC)==0x260 ) { // Location of 16 KB Expanded Memory page frame pointers
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if ((isa_address&0x0FF8)==EMS_BASE_IO ) { // Location of 16 KB Expanded Memory page frame pointers
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switch (isa_address) {
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case 0x260: isa_data_out = reg_0x260; break;
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case 0x261: isa_data_out = reg_0x261; break;
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case 0x262: isa_data_out = reg_0x262; break;
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case 0x263: isa_data_out = reg_0x263; break;
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case EMS_BASE_IO : isa_data_out = ems_frame_pointer[0]; break;
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case EMS_BASE_IO+1: isa_data_out = ems_frame_pointer[0] >> 8; break;
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case EMS_BASE_IO+2: isa_data_out = ems_frame_pointer[1]; break;
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case EMS_BASE_IO+3: isa_data_out = ems_frame_pointer[1] >> 8; break;
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case EMS_BASE_IO+4: isa_data_out = ems_frame_pointer[2]; break;
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case EMS_BASE_IO+5: isa_data_out = ems_frame_pointer[2] >> 8; break;
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case EMS_BASE_IO+6: isa_data_out = ems_frame_pointer[3]; break;
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case EMS_BASE_IO+7: isa_data_out = ems_frame_pointer[3] >> 8; break;
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}
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GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
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@@ -638,12 +647,12 @@ inline void IO_Read_Cycle() {
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}
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else if ((isa_address&0x0FFC)==SD_LPT_BASE ) { // Location of Parallel Port
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else if ((isa_address&0x0FFE)==SD_BASE ) { // Location of SD Card registers
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switch (isa_address) {
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case SD_LPT_BASE: sd_spi_dataout = 0xff; SD_SPI_Cycle(); isa_data_out = sd_spi_datain; break;
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}
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// Both registers serve the same function (to allow use of Word I/O)
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sd_spi_dataout = 0xff;
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SD_SPI_Cycle();
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isa_data_out = sd_spi_datain;
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GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_LOW;
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@@ -664,7 +673,7 @@ inline void IO_Write_Cycle() {
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isa_address = 0xFFFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
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if ((isa_address&0x0FFC)==0x260 ) { // Location of 16 KB Expanded Memory page frame pointers
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if ((isa_address&0x0FF8)==EMS_BASE_IO ) { // Location of 16 KB Expanded Memory page frame pointers
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GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_HIGH + CHRDY_OUT_LOW + trigger_out;
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_LOW + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
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@@ -676,10 +685,14 @@ inline void IO_Write_Cycle() {
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data_in = 0xFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
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switch (isa_address) {
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case 0x260: reg_0x260 = data_in; break;
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case 0x261: reg_0x261 = data_in; break;
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case 0x262: reg_0x262 = data_in; break;
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case 0x263: reg_0x263 = data_in; break;
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case EMS_BASE_IO : ems_frame_pointer[0] = (ems_frame_pointer[0] & 0xFF00) | data_in; break;
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case EMS_BASE_IO+1: ems_frame_pointer[0] = (ems_frame_pointer[0] & 0x00FF) | ((uint16_t)data_in << 8); break;
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case EMS_BASE_IO+2: ems_frame_pointer[1] = (ems_frame_pointer[1] & 0xFF00) | data_in; break;
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case EMS_BASE_IO+3: ems_frame_pointer[1] = (ems_frame_pointer[1] & 0x00FF) | ((uint16_t)data_in << 8); break;
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case EMS_BASE_IO+4: ems_frame_pointer[2] = (ems_frame_pointer[2] & 0xFF00) | data_in; break;
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case EMS_BASE_IO+5: ems_frame_pointer[2] = (ems_frame_pointer[2] & 0x00FF) | ((uint16_t)data_in << 8); break;
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case EMS_BASE_IO+6: ems_frame_pointer[3] = (ems_frame_pointer[3] & 0xFF00) | data_in; break;
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case EMS_BASE_IO+7: ems_frame_pointer[3] = (ems_frame_pointer[3] & 0x00FF) | ((uint16_t)data_in << 8); break;
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}
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GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
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@@ -687,7 +700,7 @@ inline void IO_Write_Cycle() {
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}
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else if ((isa_address&0x0FFC)==SD_LPT_BASE ) { // Location of Parallel Port
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else if ((isa_address&0x0FFC)==SD_BASE ) { // Location of SD Card registers
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GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_HIGH + CHRDY_OUT_LOW + trigger_out;
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_LOW + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
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@@ -696,8 +709,9 @@ inline void IO_Write_Cycle() {
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data_in = 0xFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
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switch (isa_address) {
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case SD_LPT_BASE : sd_spi_dataout = data_in; SD_SPI_Cycle(); break;
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case (SD_LPT_BASE+1): sd_spi_cs_n = data_in&0x1; break;
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case SD_BASE: // First two registers serve the same function (to allow use of Word I/O)
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case SD_BASE+1: sd_spi_dataout = data_in; SD_SPI_Cycle(); break;
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case SD_BASE+2: sd_spi_cs_n = data_in&0x1; break;
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}
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//gpio9_int = GPIO9_DR;
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@@ -708,10 +722,6 @@ inline void IO_Write_Cycle() {
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sd_pin_outputs = (sd_spi_cs_n<<17); // SD_CS_n - SD_CLK - SD_MOSI
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//trigger_out = ((lpt_data&0x1)<<28); // SD_MOSI
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//trigger_out = ((lpt_data&0x2)<<27); // SD_CLK
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//trigger_out = ((lpt_data&0x4)<<26); // SD_CS_n
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GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
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}
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