From ad5560bf41daefc4f658a3929a62f2d189404024 Mon Sep 17 00:00:00 2001
From: MicroCoreLabs <54004369+MicroCoreLabs@users.noreply.github.com>
Date: Wed, 11 Nov 2020 20:09:27 -0800
Subject: [PATCH] Uploaded_11_11_2020

---
 MCL86jr/FPGA/MCL86jr/MCL86jr.bld              |    44 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.cmd_log          |   676 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.gise             |   217 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.lso              |     1 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.ncd              |     3 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.ngc              |     3 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.ngd              |     3 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.ngr              |     3 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.pad              |   174 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.par              |   228 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.pcf              |   756 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.prj              |     5 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.ptwx             |   332 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.stx              |     0
 MCL86jr/FPGA/MCL86jr/MCL86jr.syr              |   944 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.twr              |   694 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.twx              |   348 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.ucf              |   178 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.ucf.bak          |   175 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.unroutes         |     9 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.ut               |    31 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.xise             |   386 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.xpi              |     3 +
 MCL86jr/FPGA/MCL86jr/MCL86jr.xst              |    53 +
 MCL86jr/FPGA/MCL86jr/MCL86jr_bitgen.xwbt      |     8 +
 MCL86jr/FPGA/MCL86jr/MCL86jr_envsettings.html |   568 +
 MCL86jr/FPGA/MCL86jr/MCL86jr_guide.ncd        |     3 +
 MCL86jr/FPGA/MCL86jr/MCL86jr_map.map          |   178 +
 MCL86jr/FPGA/MCL86jr/MCL86jr_map.mrp          |   329 +
 MCL86jr/FPGA/MCL86jr/MCL86jr_map.ncd          |     3 +
 MCL86jr/FPGA/MCL86jr/MCL86jr_map.ngm          |     3 +
 MCL86jr/FPGA/MCL86jr/MCL86jr_map.psr          |    62 +
 MCL86jr/FPGA/MCL86jr/MCL86jr_map.xrpt         |   789 +
 MCL86jr/FPGA/MCL86jr/MCL86jr_ngdbuild.xrpt    |   149 +
 MCL86jr/FPGA/MCL86jr/MCL86jr_pad.csv          |   175 +
 MCL86jr/FPGA/MCL86jr/MCL86jr_pad.txt          |   174 +
 MCL86jr/FPGA/MCL86jr/MCL86jr_par.xrpt         |  1566 +
 MCL86jr/FPGA/MCL86jr/MCL86jr_summary.html     |   502 +
 MCL86jr/FPGA/MCL86jr/MCL86jr_summary.xml      |    10 +
 MCL86jr/FPGA/MCL86jr/MCL86jr_usage.xml        |  2138 +
 MCL86jr/FPGA/MCL86jr/MCL86jr_xpa.log          |    65 +
 MCL86jr/FPGA/MCL86jr/MCL86jr_xst.xrpt         |   260 +
 MCL86jr/FPGA/MCL86jr/_impact.cmd              |   150 +
 MCL86jr/FPGA/MCL86jr/_impact.log              |   330 +
 MCL86jr/FPGA/MCL86jr/_ngo/netlist.lst         |     3 +
 MCL86jr/FPGA/MCL86jr/_xmsgs/bitgen.xmsgs      |    18 +
 MCL86jr/FPGA/MCL86jr/_xmsgs/map.xmsgs         |    39 +
 MCL86jr/FPGA/MCL86jr/_xmsgs/ngdbuild.xmsgs    |    13 +
 MCL86jr/FPGA/MCL86jr/_xmsgs/par.xmsgs         |    12 +
 MCL86jr/FPGA/MCL86jr/_xmsgs/pn_parser.xmsgs   |    21 +
 MCL86jr/FPGA/MCL86jr/_xmsgs/trce.xmsgs        |    18 +
 MCL86jr/FPGA/MCL86jr/_xmsgs/xst.xmsgs         |   186 +
 MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.asy   |    17 +
 MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.gise  |    52 +
 MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.mif   |  4096 +
 MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.ncf   |     0
 MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.ngc   |     3 +
 MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.v     |   176 +
 MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.veo   |    61 +
 MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.xco   |   108 +
 MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.xise  |    69 +
 .../EU4Kx32/blk_mem_gen_v7_3_readme.txt       |   213 +
 .../EU4Kx32/doc/blk_mem_gen_v7_3_vinfo.html   |   224 +
 .../EU4Kx32/doc/pg058-blk-mem-gen.pdf         |   Bin 0 -> 7207569 bytes
 .../EU4Kx32/example_design/EU4Kx32_exdes.ucf  |    57 +
 .../EU4Kx32/example_design/EU4Kx32_exdes.vhd  |   151 +
 .../EU4Kx32/example_design/EU4Kx32_exdes.xdc  |    54 +
 .../EU4Kx32/example_design/EU4Kx32_prod.vhd   |   260 +
 .../EU4Kx32/implement/implement.bat           |    48 +
 .../ipcore_dir/EU4Kx32/implement/implement.sh |    48 +
 .../EU4Kx32/implement/planAhead_ise.bat       |    55 +
 .../EU4Kx32/implement/planAhead_ise.sh        |    55 +
 .../EU4Kx32/implement/planAhead_ise.tcl       |    67 +
 .../ipcore_dir/EU4Kx32/implement/xst.prj      |     1 +
 .../ipcore_dir/EU4Kx32/implement/xst.scr      |    13 +
 .../EU4Kx32/simulation/EU4Kx32_synth.vhd      |   255 +
 .../EU4Kx32/simulation/EU4Kx32_tb.vhd         |   135 +
 .../EU4Kx32/simulation/addr_gen.vhd           |   117 +
 .../EU4Kx32/simulation/bmg_stim_gen.vhd       |   426 +
 .../EU4Kx32/simulation/bmg_tb_pkg.vhd         |   200 +
 .../EU4Kx32/simulation/functional/simcmds.tcl |    60 +
 .../simulation/functional/simulate_isim.bat   |    67 +
 .../simulation/functional/simulate_mti.bat    |     3 +
 .../simulation/functional/simulate_mti.do     |    74 +
 .../simulation/functional/simulate_mti.sh     |     3 +
 .../simulation/functional/simulate_ncsim.sh   |    69 +
 .../simulation/functional/simulate_vcs.sh     |    68 +
 .../simulation/functional/ucli_commands.key   |     4 +
 .../simulation/functional/vcs_session.tcl     |    80 +
 .../EU4Kx32/simulation/functional/wave_mti.do |    33 +
 .../simulation/functional/wave_ncsim.sv       |    18 +
 .../ipcore_dir/EU4Kx32/simulation/random.vhd  |   112 +
 .../EU4Kx32/simulation/timing/simcmds.tcl     |    60 +
 .../simulation/timing/simulate_isim.bat       |    63 +
 .../simulation/timing/simulate_mti.bat        |     3 +
 .../EU4Kx32/simulation/timing/simulate_mti.do |    73 +
 .../EU4Kx32/simulation/timing/simulate_mti.sh |     3 +
 .../simulation/timing/simulate_ncsim.sh       |    76 +
 .../EU4Kx32/simulation/timing/simulate_vcs.sh |    68 +
 .../simulation/timing/ucli_commands.key       |     4 +
 .../EU4Kx32/simulation/timing/vcs_session.tcl |    80 +
 .../EU4Kx32/simulation/timing/wave_mti.do     |    33 +
 .../EU4Kx32/simulation/timing/wave_ncsim.sv   |    17 +
 .../FPGA/MCL86jr/ipcore_dir/EU4Kx32_flist.txt |    55 +
 .../FPGA/MCL86jr/ipcore_dir/EU4Kx32_xmdf.tcl  |   243 +
 .../FPGA/MCL86jr/ipcore_dir/_xmsgs/cg.xmsgs   |    27 +
 .../MCL86jr/ipcore_dir/_xmsgs/pn_parser.xmsgs |    15 +
 MCL86jr/FPGA/MCL86jr/ipcore_dir/coregen.cgp   |     9 +
 MCL86jr/FPGA/MCL86jr/ipcore_dir/coregen.log   |    49 +
 .../FPGA/MCL86jr/ipcore_dir/edit_EU4Kx32.tcl  |    37 +
 .../MCL86jr/ipcore_dir/edit_spartan6_pll.tcl  |    37 +
 .../FPGA/MCL86jr/ipcore_dir/spartan6_pll.asy  |    13 +
 .../FPGA/MCL86jr/ipcore_dir/spartan6_pll.gise |    52 +
 .../FPGA/MCL86jr/ipcore_dir/spartan6_pll.ncf  |    59 +
 .../FPGA/MCL86jr/ipcore_dir/spartan6_pll.sym  |    15 +
 .../FPGA/MCL86jr/ipcore_dir/spartan6_pll.ucf  |    58 +
 .../FPGA/MCL86jr/ipcore_dir/spartan6_pll.v    |   145 +
 .../FPGA/MCL86jr/ipcore_dir/spartan6_pll.veo  |    75 +
 .../FPGA/MCL86jr/ipcore_dir/spartan6_pll.xco  |   269 +
 .../FPGA/MCL86jr/ipcore_dir/spartan6_pll.xdc  |    66 +
 .../FPGA/MCL86jr/ipcore_dir/spartan6_pll.xise |   403 +
 .../spartan6_pll/clk_wiz_v3_6_readme.txt      |   184 +
 .../spartan6_pll/doc/clk_wiz_v3_6_readme.txt  |   184 +
 .../spartan6_pll/doc/clk_wiz_v3_6_vinfo.html  |   195 +
 .../spartan6_pll/doc/pg065_clk_wiz.pdf        |   Bin 0 -> 42657 bytes
 .../example_design/spartan6_pll_exdes.ucf     |    59 +
 .../example_design/spartan6_pll_exdes.v       |   150 +
 .../example_design/spartan6_pll_exdes.xdc     |    68 +
 .../spartan6_pll/implement/implement.bat      |    90 +
 .../spartan6_pll/implement/implement.sh       |    91 +
 .../spartan6_pll/implement/planAhead_ise.bat  |    58 +
 .../spartan6_pll/implement/planAhead_ise.sh   |    59 +
 .../spartan6_pll/implement/planAhead_ise.tcl  |    78 +
 .../spartan6_pll/implement/planAhead_rdn.bat  |    58 +
 .../spartan6_pll/implement/planAhead_rdn.sh   |    57 +
 .../spartan6_pll/implement/planAhead_rdn.tcl  |    69 +
 .../ipcore_dir/spartan6_pll/implement/xst.prj |     2 +
 .../ipcore_dir/spartan6_pll/implement/xst.scr |     9 +
 .../simulation/functional/simcmds.tcl         |     8 +
 .../simulation/functional/simulate_isim.bat   |    59 +
 .../simulation/functional/simulate_isim.sh    |    61 +
 .../simulation/functional/simulate_mti.bat    |    61 +
 .../simulation/functional/simulate_mti.do     |    65 +
 .../simulation/functional/simulate_mti.sh     |    61 +
 .../simulation/functional/simulate_ncsim.sh   |    62 +
 .../simulation/functional/simulate_vcs.sh     |    72 +
 .../simulation/functional/ucli_commands.key   |     5 +
 .../simulation/functional/vcs_session.tcl     |    15 +
 .../simulation/functional/wave.do             |    57 +
 .../simulation/functional/wave.sv             |   111 +
 .../spartan6_pll/simulation/spartan6_pll_tb.v |   133 +
 .../simulation/timing/sdf_cmd_file            |     2 +
 .../simulation/timing/simcmds.tcl             |     9 +
 .../simulation/timing/simulate_isim.sh        |    62 +
 .../simulation/timing/simulate_mti.bat        |    59 +
 .../simulation/timing/simulate_mti.do         |    65 +
 .../simulation/timing/simulate_mti.sh         |    61 +
 .../simulation/timing/simulate_ncsim.sh       |    64 +
 .../simulation/timing/simulate_vcs.sh         |    72 +
 .../simulation/timing/spartan6_pll_tb.v       |   136 +
 .../simulation/timing/ucli_commands.key       |     5 +
 .../simulation/timing/vcs_session.tcl         |     1 +
 .../spartan6_pll/simulation/timing/wave.do    |    70 +
 .../MCL86jr/ipcore_dir/spartan6_pll_flist.txt |    55 +
 .../MCL86jr/ipcore_dir/spartan6_pll_xmdf.tcl  |   140 +
 MCL86jr/FPGA/MCL86jr/ipcore_dir/summary.log   |    18 +
 .../FPGA/MCL86jr/ipcore_dir/tmp/EU4Kx32.lso   |     1 +
 .../ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs     |    15 +
 .../MCL86jr/ipcore_dir/tmp/_xmsgs/xst.xmsgs   |   849 +
 .../tmp/customization_gui.0.0556430854162.out |   505 +
 .../tmp/customization_gui.0.136417835083.out  |   505 +
 .../tmp/customization_gui.0.273617099167.out  |   505 +
 .../tmp/customization_gui.0.453378507147.out  |   505 +
 .../tmp/customization_gui.0.496287952408.out  |   505 +
 .../tmp/customization_gui.0.507115344753.out  |   505 +
 .../tmp/customization_gui.0.736896934797.out  |   505 +
 .../FPGA/MCL86jr/iseconfig/MCL86jr.projectmgr |   109 +
 .../FPGA/MCL86jr/iseconfig/MCL86jr.xreport    |   215 +
 MCL86jr/FPGA/MCL86jr/mcl86jr.bgn              |   146 +
 MCL86jr/FPGA/MCL86jr/mcl86jr.bit              |   Bin 0 -> 340993 bytes
 MCL86jr/FPGA/MCL86jr/mcl86jr.drc              |    16 +
 MCL86jr/FPGA/MCL86jr/pa.fromHdl.tcl           |    24 +
 MCL86jr/FPGA/MCL86jr/pa.fromNetlist.tcl       |    12 +
 .../FPGA/MCL86jr/par_usage_statistics.html    |    33 +
 MCL86jr/FPGA/MCL86jr/planAhead.ngc2edif.log   |    67 +
 MCL86jr/FPGA/MCL86jr/planAhead_pid2800.debug  |    72 +
 MCL86jr/FPGA/MCL86jr/planAhead_pid6304.debug  |    74 +
 MCL86jr/FPGA/MCL86jr/planAhead_pid7676.debug  |    73 +
 .../MCL86jr.data/constrs_1/fileset.xml        |    21 +
 .../MCL86jr.data/sim_1/fileset.xml            |    13 +
 .../MCL86jr.data/sources_1/fileset.xml        |    44 +
 .../MCL86jr.data/wt/project.wpc               |     4 +
 .../MCL86jr.data/wt/webtalk_pa.xml            |    27 +
 .../FPGA/MCL86jr/planAhead_run_1/MCL86jr.ppr  |    27 +
 .../MCL86jr/planAhead_run_1/planAhead.jou     |    49 +
 .../MCL86jr/planAhead_run_1/planAhead.log     |   122 +
 .../MCL86jr/planAhead_run_1/planAhead_run.log |   113 +
 .../MCL86jr.data/cache/EU4Kx32_ngc_zx.edif    |  2660 +
 .../MCL86jr.data/cache/MCL86jr_ngc_zx.edif    | 29336 ++++++
 .../MCL86jr.data/constrs_1/fileset.xml        |    21 +
 .../MCL86jr.data/runs/impl_1.psg              |    20 +
 .../MCL86jr.data/runs/runs.xml                |     5 +
 .../MCL86jr.data/sim_1/fileset.xml            |    10 +
 .../MCL86jr.data/sources_1/fileset.xml        |    24 +
 .../MCL86jr.data/wt/java_command_handlers.wdf |     3 +
 .../MCL86jr.data/wt/project.wpc               |     4 +
 .../MCL86jr.data/wt/webtalk_pa.xml            |    29 +
 .../FPGA/MCL86jr/planAhead_run_2/MCL86jr.ppr  |    28 +
 .../MCL86jr/planAhead_run_2/planAhead.jou     |    10 +
 .../MCL86jr/planAhead_run_2/planAhead.log     |    95 +
 .../MCL86jr/planAhead_run_2/planAhead_run.log |    86 +
 .../MCL86jr.data/cache/EU4Kx32_ngc_zx.edif    |  2660 +
 .../MCL86jr.data/cache/MCL86jr_ngc_zx.edif    | 30706 +++++++
 .../MCL86jr.data/constrs_1/designprops.xml    |    11 +
 .../MCL86jr.data/constrs_1/fileset.xml        |    27 +
 .../MCL86jr.data/constrs_1/usercols.xml       |     4 +
 .../MCL86jr.data/runs/impl_1.psg              |    20 +
 .../MCL86jr.data/runs/runs.xml                |     5 +
 .../MCL86jr.data/sim_1/fileset.xml            |    10 +
 .../MCL86jr.data/sources_1/chipscope.xml      |     6 +
 .../MCL86jr.data/sources_1/fileset.xml        |    30 +
 .../MCL86jr.data/sources_1/ports.xml          |    87 +
 .../MCL86jr.data/wt/java_command_handlers.wdf |     3 +
 .../MCL86jr.data/wt/project.wpc               |     4 +
 .../MCL86jr.data/wt/webtalk_pa.xml            |    29 +
 .../FPGA/MCL86jr/planAhead_run_3/MCL86jr.ppr  |    28 +
 .../MCL86jr/planAhead_run_3/planAhead.jou     |    13 +
 .../MCL86jr/planAhead_run_3/planAhead.log     |    94 +
 .../MCL86jr/planAhead_run_3/planAhead_run.log |    85 +
 .../MCL86jr/usage_statistics_webtalk.html     |  2562 +
 MCL86jr/FPGA/MCL86jr/webtalk.log              |    16 +
 MCL86jr/FPGA/MCL86jr/webtalk_pn.xml           |    51 +
 MCL86jr/FPGA/MCL86jr/xlnx_auto_0_xdb/cst.xbcd |   Bin 0 -> 19842 bytes
 MCL86jr/FPGA/MCL86jr/xst/work/work.sdbl       |   Bin 0 -> 121498 bytes
 MCL86jr/FPGA/MCL86jr/xst/work/work.sdbx       |   Bin 0 -> 140 bytes
 MCL86jr/FPGA/MCL86jr_Impact.ipf               |   Bin 0 -> 44665 bytes
 MCL86jr/FPGA/Untitled.cfi                     |    11 +
 MCL86jr/FPGA/Untitled.mcs                     | 21313 +++++
 MCL86jr/FPGA/Untitled.prm                     |    17 +
 MCL86jr/FPGA/impact.xsl                       |    55 +
 MCL86jr/FPGA/impact_impact.xwbt               |     8 +
 .../FPGA/src4synth/MCL86_Microcode_Xilinx.coe |     2 +
 MCL86jr/FPGA/src4synth/MCL86jr.v              |   354 +
 MCL86jr/FPGA/src4synth/biu_min.v              |   924 +
 MCL86jr/FPGA/src4synth/eu.v                   |   492 +
 MCL86jr/FPGA/usage_statistics_webtalk.html    |    98 +
 MCL86jr/FPGA/webtalk.log                      |    16 +
 MCL86jr/FPGA/webtalk_impact.xml               |    61 +
 .../Fabrication_Products2/MCL86jr-B_Cu.gbr    |  8586 ++
 .../Fabrication_Products2/MCL86jr-B_Mask.gbr  |  6008 ++
 .../Fabrication_Products2/MCL86jr-B_Paste.gbr |  7251 ++
 .../Fabrication_Products2/MCL86jr-B_SilkS.gbr |  1780 +
 .../MCL86jr-Edge_Cuts.gbr                     |    23 +
 .../Fabrication_Products2/MCL86jr-F_Cu.gbr    | 14070 +++
 .../Fabrication_Products2/MCL86jr-F_Mask.gbr  |  6492 ++
 .../Fabrication_Products2/MCL86jr-F_Paste.gbr | 11762 +++
 .../Fabrication_Products2/MCL86jr-F_SilkS.gbr |   599 +
 .../Fabrication_Products2/MCL86jr-In1_Cu.gbr  |  7681 ++
 .../Fabrication_Products2/MCL86jr-In2_Cu.gbr  |  7482 ++
 .../MCL86jr-NPTH-drl_map.gbr                  |   107 +
 .../Fabrication_Products2/MCL86jr-NPTH.drl    |     7 +
 .../MCL86jr-PTH-drl_map.gbr                   |  1801 +
 .../Fabrication_Products2/MCL86jr-PTH.drl     |   215 +
 .../Fabrication_Products2/MCL86jr-bottom.pos  |    56 +
 .../Fabrication_Products2/MCL86jr-top.pos     |    20 +
 .../PCBA/Fabrication_Products2/MCL86jr.d356   |   574 +
 .../PCBA/Fabrication_Products2/MCL86jr.rpt    |  3090 +
 .../Fabrication_Products2/MCL86jr_BOM.txt     |    31 +
 MCL86jr/PCBA/MCL86jr                          |    15 +
 MCL86jr/PCBA/MCL86jr-cache.lib                |   520 +
 MCL86jr/PCBA/MCL86jr.kicad_pcb                |  6119 ++
 MCL86jr/PCBA/MCL86jr.kicad_pcb-bak            |  6119 ++
 MCL86jr/PCBA/MCL86jr.net                      |  1460 +
 MCL86jr/PCBA/MCL86jr.pro                      |   248 +
 MCL86jr/PCBA/MCL86jr.sch                      |    40 +
 MCL86jr/PCBA/MCL86jr.sch-bak                  |    40 +
 MCL86jr/PCBA/MCL86jr.xml                      |  1735 +
 MCL86jr/PCBA/Page1.sch                        |  1868 +
 MCL86jr/PCBA/Page1.sch-bak                    |  1868 +
 MCL86jr/PCBA/Page2.sch                        |   259 +
 MCL86jr/PCBA/Page2.sch-bak                    |   259 +
 MCL86jr/PCBA/Page3sch.sch                     |   893 +
 MCL86jr/PCBA/Page3sch.sch-bak                 |   893 +
 MCL86jr/PCBA/Page4.sch                        |   741 +
 MCL86jr/PCBA/Page4.sch-bak                    |   741 +
 MCL86jr/PCBA/Page5.sch                        |    16 +
 MCL86jr/PCBA/Page5.sch-bak                    |   211 +
 MCL86jr/PCBA/Page6.sch                        |    16 +
 MCL86jr/PCBA/Page6.sch-bak                    |    16 +
 MCL86jr/PCBA/file5F602590.sch                 |    27 +
 MCL86jr/PCBA/file5F602590.sch-bak             |    31 +
 MCL86jr/PCBA/file5F60942F.sch                 |    68 +
 MCL86jr/PCBA/fp-info-cache                    | 75328 ++++++++++++++++
 MCL86jr/PCBA/fp-lib-table                     |     6 +
 MCL86jr/PCBA/sym-lib-table                    |     5 +
 README.md                                     |     4 +
 296 files changed, 300672 insertions(+)
 create mode 100644 MCL86jr/FPGA/MCL86jr/MCL86jr.bld
 create mode 100644 MCL86jr/FPGA/MCL86jr/MCL86jr.cmd_log
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 create mode 100644 MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/sources_1/fileset.xml
 create mode 100644 MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/sources_1/ports.xml
 create mode 100644 MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/wt/java_command_handlers.wdf
 create mode 100644 MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/wt/project.wpc
 create mode 100644 MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/wt/webtalk_pa.xml
 create mode 100644 MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.ppr
 create mode 100644 MCL86jr/FPGA/MCL86jr/planAhead_run_3/planAhead.jou
 create mode 100644 MCL86jr/FPGA/MCL86jr/planAhead_run_3/planAhead.log
 create mode 100644 MCL86jr/FPGA/MCL86jr/planAhead_run_3/planAhead_run.log
 create mode 100644 MCL86jr/FPGA/MCL86jr/usage_statistics_webtalk.html
 create mode 100644 MCL86jr/FPGA/MCL86jr/webtalk.log
 create mode 100644 MCL86jr/FPGA/MCL86jr/webtalk_pn.xml
 create mode 100644 MCL86jr/FPGA/MCL86jr/xlnx_auto_0_xdb/cst.xbcd
 create mode 100644 MCL86jr/FPGA/MCL86jr/xst/work/work.sdbl
 create mode 100644 MCL86jr/FPGA/MCL86jr/xst/work/work.sdbx
 create mode 100644 MCL86jr/FPGA/MCL86jr_Impact.ipf
 create mode 100644 MCL86jr/FPGA/Untitled.cfi
 create mode 100644 MCL86jr/FPGA/Untitled.mcs
 create mode 100644 MCL86jr/FPGA/Untitled.prm
 create mode 100644 MCL86jr/FPGA/impact.xsl
 create mode 100644 MCL86jr/FPGA/impact_impact.xwbt
 create mode 100644 MCL86jr/FPGA/src4synth/MCL86_Microcode_Xilinx.coe
 create mode 100644 MCL86jr/FPGA/src4synth/MCL86jr.v
 create mode 100644 MCL86jr/FPGA/src4synth/biu_min.v
 create mode 100644 MCL86jr/FPGA/src4synth/eu.v
 create mode 100644 MCL86jr/FPGA/usage_statistics_webtalk.html
 create mode 100644 MCL86jr/FPGA/webtalk.log
 create mode 100644 MCL86jr/FPGA/webtalk_impact.xml
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr-B_Cu.gbr
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr-B_Mask.gbr
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr-B_Paste.gbr
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr-B_SilkS.gbr
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr-Edge_Cuts.gbr
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr-F_Cu.gbr
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr-F_Mask.gbr
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr-F_Paste.gbr
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr-F_SilkS.gbr
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr-In1_Cu.gbr
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr-In2_Cu.gbr
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr-NPTH-drl_map.gbr
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr-NPTH.drl
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr-PTH-drl_map.gbr
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr-PTH.drl
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr-bottom.pos
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr-top.pos
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr.d356
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr.rpt
 create mode 100644 MCL86jr/PCBA/Fabrication_Products2/MCL86jr_BOM.txt
 create mode 100644 MCL86jr/PCBA/MCL86jr
 create mode 100644 MCL86jr/PCBA/MCL86jr-cache.lib
 create mode 100644 MCL86jr/PCBA/MCL86jr.kicad_pcb
 create mode 100644 MCL86jr/PCBA/MCL86jr.kicad_pcb-bak
 create mode 100644 MCL86jr/PCBA/MCL86jr.net
 create mode 100644 MCL86jr/PCBA/MCL86jr.pro
 create mode 100644 MCL86jr/PCBA/MCL86jr.sch
 create mode 100644 MCL86jr/PCBA/MCL86jr.sch-bak
 create mode 100644 MCL86jr/PCBA/MCL86jr.xml
 create mode 100644 MCL86jr/PCBA/Page1.sch
 create mode 100644 MCL86jr/PCBA/Page1.sch-bak
 create mode 100644 MCL86jr/PCBA/Page2.sch
 create mode 100644 MCL86jr/PCBA/Page2.sch-bak
 create mode 100644 MCL86jr/PCBA/Page3sch.sch
 create mode 100644 MCL86jr/PCBA/Page3sch.sch-bak
 create mode 100644 MCL86jr/PCBA/Page4.sch
 create mode 100644 MCL86jr/PCBA/Page4.sch-bak
 create mode 100644 MCL86jr/PCBA/Page5.sch
 create mode 100644 MCL86jr/PCBA/Page5.sch-bak
 create mode 100644 MCL86jr/PCBA/Page6.sch
 create mode 100644 MCL86jr/PCBA/Page6.sch-bak
 create mode 100644 MCL86jr/PCBA/file5F602590.sch
 create mode 100644 MCL86jr/PCBA/file5F602590.sch-bak
 create mode 100644 MCL86jr/PCBA/file5F60942F.sch
 create mode 100644 MCL86jr/PCBA/fp-info-cache
 create mode 100644 MCL86jr/PCBA/fp-lib-table
 create mode 100644 MCL86jr/PCBA/sym-lib-table

diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.bld b/MCL86jr/FPGA/MCL86jr/MCL86jr.bld
new file mode 100644
index 0000000..2da5511
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.bld
@@ -0,0 +1,44 @@
+Release 14.7 ngdbuild P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
+-intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p
+xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd
+
+Reading NGO file "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ngc" ...
+Loading design module "ipcore_dir/EU4Kx32.ngc"...
+Gathering constraint information from source properties...
+Done.
+
+Annotating constraints to design from ucf file "MCL86jr.ucf" ...
+Resolving constraint associations...
+Checking Constraint Associations...
+INFO:ConstraintSystem:178 - TNM 'CORE_CLK', used in period specification
+   'TS_CORE_CLK', was traced into DCM_SP instance SPARTAN6PLL/dcm_sp_inst. The
+   following new TNM groups and period specifications were generated at the
+   DCM_SP output(s): 
+   CLKFX: <TIMESPEC TS_SPARTAN6PLL_clkfx = PERIOD "SPARTAN6PLL_clkfx"
+   TS_CORE_CLK / 2.2 HIGH 50%>
+
+Done...
+
+Checking expanded design ...
+
+Partition Implementation Status
+-------------------------------
+
+  No Partitions were found in this design.
+
+-------------------------------
+
+NGDBUILD Design Results Summary:
+  Number of errors:     0
+  Number of warnings:   0
+
+Total memory usage is 170808 kilobytes
+
+Writing NGD file "MCL86jr.ngd" ...
+Total REAL time to NGDBUILD completion:  4 sec
+Total CPU time to NGDBUILD completion:   4 sec
+
+Writing NGDBUILD log file "MCL86jr.bld"...
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.cmd_log b/MCL86jr/FPGA/MCL86jr/MCL86jr.cmd_log
new file mode 100644
index 0000000..fccb526
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.cmd_log
@@ -0,0 +1,676 @@
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-2 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-2 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-2 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-2 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-2 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
+xst -intstyle ise -ifn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xst" -ofn "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.syr" 
+ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc MCL86jr.ucf -p xc6slx9-tqg144-3 MCL86jr.ngc MCL86jr.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd MCL86jr.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf MCL86jr.ucf 
+bitgen -intstyle ise -f MCL86jr.ut MCL86jr.ncd 
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.gise b/MCL86jr/FPGA/MCL86jr/MCL86jr.gise
new file mode 100644
index 0000000..58adfcd
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.gise
@@ -0,0 +1,217 @@
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+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150596" xil_pn:in_ck="-7247114840459501862" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="787467277420992043" xil_pn:start_ts="1605150595">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="ipcore_dir/EU4Kx32.ngc"/>
+      <outfile xil_pn:name="ipcore_dir/EU4Kx32.v"/>
+      <outfile xil_pn:name="ipcore_dir/spartan6_pll.v"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150596" xil_pn:in_ck="656480033301313304" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1605150596">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150596" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1358955015879939485" xil_pn:start_ts="1605150596">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150596" xil_pn:in_ck="656480033301313304" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1605150596">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150596" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="6091208428188821685" xil_pn:start_ts="1605150596">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150615" xil_pn:in_ck="7485807331199273541" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2304791464621354458" xil_pn:start_ts="1605150596">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="OutputChanged"/>
+      <outfile xil_pn:name="MCL86jr.lso"/>
+      <outfile xil_pn:name="MCL86jr.ngc"/>
+      <outfile xil_pn:name="MCL86jr.ngr"/>
+      <outfile xil_pn:name="MCL86jr.prj"/>
+      <outfile xil_pn:name="MCL86jr.stx"/>
+      <outfile xil_pn:name="MCL86jr.syr"/>
+      <outfile xil_pn:name="MCL86jr.xst"/>
+      <outfile xil_pn:name="MCL86jr_xst.xrpt"/>
+      <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
+      <outfile xil_pn:name="webtalk_pn.xml"/>
+      <outfile xil_pn:name="xst"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150615" xil_pn:in_ck="5237154405922346467" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1262981232102443208" xil_pn:start_ts="1605150615">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150622" xil_pn:in_ck="-1301045618153758935" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-3050930112883171540" xil_pn:start_ts="1605150615">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="MCL86jr.bld"/>
+      <outfile xil_pn:name="MCL86jr.ngd"/>
+      <outfile xil_pn:name="MCL86jr_ngdbuild.xrpt"/>
+      <outfile xil_pn:name="_ngo"/>
+      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150658" xil_pn:in_ck="-6237160376423811521" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="5459139723028316866" xil_pn:start_ts="1605150622">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="MCL86jr.pcf"/>
+      <outfile xil_pn:name="MCL86jr_map.map"/>
+      <outfile xil_pn:name="MCL86jr_map.mrp"/>
+      <outfile xil_pn:name="MCL86jr_map.ncd"/>
+      <outfile xil_pn:name="MCL86jr_map.ngm"/>
+      <outfile xil_pn:name="MCL86jr_map.psr"/>
+      <outfile xil_pn:name="MCL86jr_map.xrpt"/>
+      <outfile xil_pn:name="MCL86jr_summary.xml"/>
+      <outfile xil_pn:name="MCL86jr_usage.xml"/>
+      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150702" xil_pn:in_ck="5563182848059918264" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1885771668075636388" xil_pn:start_ts="1605150658">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="MCL86jr.ncd"/>
+      <outfile xil_pn:name="MCL86jr.pad"/>
+      <outfile xil_pn:name="MCL86jr.par"/>
+      <outfile xil_pn:name="MCL86jr.ptwx"/>
+      <outfile xil_pn:name="MCL86jr.unroutes"/>
+      <outfile xil_pn:name="MCL86jr.xpi"/>
+      <outfile xil_pn:name="MCL86jr_pad.csv"/>
+      <outfile xil_pn:name="MCL86jr_pad.txt"/>
+      <outfile xil_pn:name="MCL86jr_par.xrpt"/>
+      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150730" xil_pn:in_ck="121150499032679689" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3552836582087367069" xil_pn:start_ts="1605150702">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="MCL86jr.ut"/>
+      <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
+      <outfile xil_pn:name="mcl86jr.bgn"/>
+      <outfile xil_pn:name="mcl86jr.bit"/>
+      <outfile xil_pn:name="mcl86jr.drc"/>
+      <outfile xil_pn:name="usage_statistics_webtalk.html"/>
+      <outfile xil_pn:name="webtalk.log"/>
+      <outfile xil_pn:name="webtalk_pn.xml"/>
+    </transform>
+    <transform xil_pn:end_ts="1605041197" xil_pn:in_ck="171691199137775411" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1605041194">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="InputChanged"/>
+      <outfile xil_pn:name="_impact.cmd"/>
+      <outfile xil_pn:name="_impact.log"/>
+    </transform>
+    <transform xil_pn:end_ts="1600579929" xil_pn:in_ck="121150499032679689" xil_pn:name="TRAN_XPower_spartan6" xil_pn:prop_ck="1949643303204221642" xil_pn:start_ts="1600579929">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="InputAdded"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="InputRemoved"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150702" xil_pn:in_ck="5538025637473800251" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1605150695">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="MCL86jr.twr"/>
+      <outfile xil_pn:name="MCL86jr.twx"/>
+      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
+    </transform>
+  </transforms>
+
+</generated_project>
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.lso b/MCL86jr/FPGA/MCL86jr/MCL86jr.lso
new file mode 100644
index 0000000..b8f99f5
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.lso
@@ -0,0 +1 @@
+work
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.ncd b/MCL86jr/FPGA/MCL86jr/MCL86jr.ncd
new file mode 100644
index 0000000..ae05415
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.ncd
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6
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new file mode 100644
index 0000000..bba216b
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diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.ngd b/MCL86jr/FPGA/MCL86jr/MCL86jr.ngd
new file mode 100644
index 0000000..64250cb
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.ngd
@@ -0,0 +1,3 @@
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diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.ngr b/MCL86jr/FPGA/MCL86jr/MCL86jr.ngr
new file mode 100644
index 0000000..513c346
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.ngr
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
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34c2;8o7c8=c;28?l45k3:1(;<k:30g?k05k3;07d<=b;29 34c2;8o7c8=c;08?l45i3:1(;<k:30g?k05k3907d<=9;29 34c2;8o7c8=c;68?l4503:1(;<k:30g?k05k3?07d<<7;29 34c2;8o7c8=c;48?l44>3:1(;<k:30g?k05k3=07d<<5;29 34c2;8o7c8=c;:8?l44<3:1(;<k:30g?k05k3307d<<3;29 34c2;8o7c8=c;c8?l44:3:1(;<k:30g?k05k3h07d<<1;29 34c2;8o7c8=c;a8?l4483:1(;<k:30g?k05k3n07d<=f;29 34c2;8o7c8=c;g8?l45?3:1(;<k:30g?k05k3l07d?k9;29 34c28n37c8=c;28?l7c?3:1(;<k:0f;?k05k3;07d?k6;29 34c28n37c8=c;08?l7c=3:1(;<k:0f;?k05k3907d?k4;29 34c28n37c8=c;68?l7c;3:1(;<k:0f;?k05k3?07d?j2;29 34c28n37c8=c;48?l7b93:1(;<k:0f;?k05k3=07d?j0;29 34c28n37c8=c;:8?l7cn3:1(;<k:0f;?k05k3307d?ke;29 34c28n37c8=c;c8?l7cl3:1(;<k:0f;?k05k3h07d?kc;29 34c28n37c8=c;a8?l7cj3:1(;<k:0f;?k05k3n07d?ka;29 34c28n37c8=c;g8?l7c:3:1(;<k:0f;?k05k3l07d?ja;29 34c28o27c8=c;28?l7b03:1(;<k:0g:?k05k3;07d?j7;29 34c28o27c8=c;08?l7b>3:1(;<k:0g:?k05k3907d?j5;29 34c28o27c8=c;68?l7b<3:1(;<k:0g:?k05k3?07d?i3;29 34c28o27c8=c;48?l7a:3:1(;<k:0g:?k05k3=07d?i1;29 34c28o27c8=c;:8?l7a83:1(;<k:0g:?k05k3307d?jf;29 34c28o27c8=c;c8?l7bm3:1(;<k:0g:?k05k3h07d?jd;29 34c28o27c8=c;a8?l7bk3:1(;<k:0g:?k05k3n07d?jb;29 34c28o27c8=c;g8?l7b;3:1(;<k:0g:?k05k3l07d<>d;29 34c2;;h7c8=c;28?l46j3:1(;<k:33`?k05k3;07d<>a;29 34c2;;h7c8=c;08?l4613:1(;<k:33`?k05k3907d<>8;29 34c2;;h7c8=c;68?l46?3:1(;<k:33`?k05k3?07d<=6;29 34c2;;h7c8=c;48?l45=3:1(;<k:33`?k05k3=07d<=4;29 34c2;;h7c8=c;:8?l45;3:1(;<k:33`?k05k3307d<=2;29 34c2;;h7c8=c;c8?l4593:1(;<k:33`?k05k3h07d<=0;29 34c2;;h7c8=c;a8?l46n3:1(;<k:33`?k05k3n07d<>e;29 34c2;;h7c8=c;g8?l46>3:1(;<k:33`?k05k3l07d<?c;29 34c2;:i7c8=c;28?l47i3:1(;<k:32a?k05k3;07d<?9;29 34c2;:i7c8=c;08?l4703:1(;<k:32a?k05k3907d<?7;29 34c2;:i7c8=c;68?l47>3:1(;<k:32a?k05k3?07d<>5;29 34c2;:i7c8=c;48?l46<3:1(;<k:32a?k05k3=07d<>3;29 34c2;:i7c8=c;:8?l46:3:1(;<k:32a?k05k3307d<>1;29 34c2;:i7c8=c;c8?l4683:1(;<k:32a?k05k3h07d<?f;29 34c2;:i7c8=c;a8?l47m3:1(;<k:32a?k05k3n07d<?d;29 34c2;:i7c8=c;g8?l47=3:1(;<k:32a?k05k3l07d<<f;29 34c2;9n7c8=c;28?l44l3:1(;<k:31f?k05k3;07d<<c;29 34c2;9n7c8=c;08?l44j3:1(;<k:31f?k05k3907d<<a;29 34c2;9n7c8=c;68?l4413:1(;<k:31f?k05k3?07d<;8;29 34c2;9n7c8=c;48?l43?3:1(;<k:31f?k05k3=07d<;6;29 34c2;9n7c8=c;:8?l43=3:1(;<k:31f?k05k3307d<;4;29 34c2;9n7c8=c;c8?l43;3:1(;<k:31f?k05k3h07d<;2;29 34c2;9n7c8=c;a8?l4393:1(;<k:31f?k05k3n07d<;0;29 34c2;9n7c8=c;g8?l4403:1(;<k:31f?k05k3l07d<81;29?l04l3:17d9>c;29?l7dm3:17d?lb;29?l7c83:17d?lf;29?l0593:17b:89;29 34c2==37c8=c;28?j20?3:1(;<k:55;?k05k3;07b:86;29 34c2==37c8=c;08?j20=3:1(;<k:55;?k05k3907b:84;29 34c2==37c8=c;68?j20;3:1(;<k:55;?k05k3?07b:72;29 34c2==37c8=c;48?j2?93:1(;<k:55;?k05k3=07b:70;29 34c2==37c8=c;:8?j20n3:1(;<k:55;?k05k3307b:8e;29 34c2==37c8=c;c8?j20l3:1(;<k:55;?k05k3h07b:8c;29 34c2==37c8=c;a8?j20j3:1(;<k:55;?k05k3n07b:8a;29 34c2==37c8=c;g8?j20:3:1(;<k:55;?k05k3l07b:7a;29 34c2=227c8=c;28?j2?03:1(;<k:5::?k05k3;07b:77;29 34c2=227c8=c;08?j2?>3:1(;<k:5::?k05k3907b:75;29 34c2=227c8=c;68?j2?<3:1(;<k:5::?k05k3?07b:63;29 34c2=227c8=c;48?j2>:3:1(;<k:5::?k05k3=07b:61;29 34c2=227c8=c;:8?j2>83:1(;<k:5::?k05k3307b:7f;29 34c2=227c8=c;c8?j2?m3:1(;<k:5::?k05k3h07b:7d;29 34c2=227c8=c;a8?j2?k3:1(;<k:5::?k05k3n07b:7b;29 34c2=227c8=c;g8?j2?;3:1(;<k:5::?k05k3l07b:nf;29 34c2=kn7c8=c;28?j2fl3:1(;<k:5cf?k05k3;07b:nc;29 34c2=kn7c8=c;08?j2fj3:1(;<k:5cf?k05k3907b:na;29 34c2=kn7c8=c;68?j2f13:1(;<k:5cf?k05k3?07b:m8;29 34c2=kn7c8=c;48?j2e?3:1(;<k:5cf?k05k3=07b:m6;29 34c2=kn7c8=c;:8?j2e=3:1(;<k:5cf?k05k3307b:m4;29 34c2=kn7c8=c;c8?j2e;3:1(;<k:5cf?k05k3h07b:m2;29 34c2=kn7c8=c;a8?j2e93:1(;<k:5cf?k05k3n07b:m0;29 34c2=kn7c8=c;g8?j2f03:1(;<k:5cf?k05k3l07b:n7;29?j2f>3:17b?k1;29?g15i3:1=7>50z&45`<0:81C;?84o72g>5<<uk=9;7>51;294~"09l0?o95G7348k1e42900qo?89d83>1<729q/;<k54cf8L2413E=957?t$7:a>7303tc99>4?::k131<722c=?54?::m572<722wi=>>9:186>5<7s-=:i7:me:J463=K?;31=v*98c8112=za;?86=44i37:>5<<a;=?6=44i71;>5<<g?9<6=44}cfb5?6=<3:1<v*81d87fa=O?;<0@:<6:0y'2=d=:<=0qd<:3;29?l40<3:17d8<8;29?j04?3:17pl>31594?3=83:p(:?j:5`f?M15>2F<>44>{%4;f?42?2wb>8=50;9j60?=831b>::50;9j26>=831d:>950;9~f457=3:197>50z&45`<3jl1C;?84L60:>4}#>1h1>894}h067?6=3`8>57>5;h040?6=3`<847>5;n403?6=3th:9ih50;794?6|,>;n69lj;I512>J0:00:w)87b;063>{n:<91<75f24;94?=n:>>1<75f62:94?=h>:=1<75rb07f4?6==3:1<v*81d87f`=O?;<0@:<6:0y'2=d=:<=0qd<:3;29?l4213:17d<84;29?l0403:17b8<7;29?xd6=l=1<7;50;2x 27b2=hn7E9=6:N46<<6s-<3n7<:7:j605=831b>8750;9j622=831b:>650;9l261=831vn<;j8;291?6=8r.<=h4;bd9K370<D>826<u+69`9601<u`8>?7>5;h06=?6=3`8<87>5;h40<?6=3f<8;7>5;|`21`?=83?1<7>t$63f>1db3A=9:6B82882!0?j38>;6sf24194?=n:<31<75f26694?=n>:21<75`62594?=zj8?nm7>55;294~"09l0?nh5G7348H24>28q/:5l52458yl42;3:17d<:9;29?l40<3:17d8<8;29?j04?3:17pl>5d`94?3=83:p(:?j:5`f?M15>2F<>44>{%4;f?42?2wb>8=50;9j60?=831b>::50;9j26>=831d:>950;9~f43bk3:197>50z&45`<3jl1C;?84L60:>4}#>1h1>894}h067?6=3`8>57>5;h040?6=3`<847>5;n403?6=3th:9hj50;794?6|,>;n69lj;I512>J0:00:w)87b;063>{n:<91<75f24;94?=n:>>1<75f62:94?=h>:=1<75rb07fa?6==3:1<v*81d87f`=O?;<0@:<6:0y'2=d=:<=0qd<:3;29?l4213:17d<84;29?l0403:17b8<7;29?xd6=l;1<7;50;2x 27b2=hn7E9=6:N46<<6s-<3n7<:7:j605=831b>8750;9j622=831b:>650;9l261=831vn<;j2;291?6=8r.<=h4;bd9K370<D>826<u+69`9601<u`8>?7>5;h06=?6=3`8<87>5;h40<?6=3f<8;7>5;|`21`5=83?1<7>t$63f>1db3A=9:6B82882!0?j38>;6sf24194?=n:<31<75f26694?=n>:21<75`62594?=zj8?n87>55;294~"09l0?nh5G7348H24>28q/:5l52458yl42;3:17d<:9;29?l40<3:17d8<8;29?j04?3:17pl>5d794?3=83:p(:?j:5`f?M15>2F<>44>{%4;f?42?2wb>8=50;9j60?=831b>::50;9j26>=831d:>950;9~f43b>3:197>50z&45`<3jl1C;?84L60:>4}#>1h1>894}h067?6=3`8>57>5;h040?6=3`<847>5;n403?6=3th:94j50;794?6|,>;n69lj;I512>J0:00:w)87b;063>{n:<91<75f24;94?=n:>>1<75f62:94?=h>:=1<75rb07:a?6==3:1<v*81d87f`=O?;<0@:<6:0y'2=d=:<=0qd<:3;29?l4213:17d<84;29?l0403:17b8<7;29?xd6=h?1<7;50;2x 27b2=hn7E9=6:N46<<6s-<3n7<:7:j605=831b>8750;9j622=831b:>650;9l261=831vn<;n6;291?6=8r.<=h4;bd9K370<D>826<u+69`9601<u`8>?7>5;h06=?6=3`8<87>5;h40<?6=3f<8;7>5;|`21d1=83?1<7>t$63f>1db3A=9:6B82882!0?j38>;6sf24194?=n:<31<75f26694?=n>:21<75`62594?=zj8?j47>55;294~"09l0?nh5G7348H24>28q/:5l52458yl42;3:17d<:9;29?l40<3:17d8<8;29?j04?3:17pl>5`;94?3=83:p(:?j:5`f?M15>2F<>44>{%4;f?42?2wb>8=50;9j60?=831b>::50;9j26>=831d:>950;9~f43fi3:197>50z&45`<3jl1C;?84L60:>4}#>1h1>894}h067?6=3`8>57>5;h040?6=3`<847>5;n403?6=3th:9ll50;794?6|,>;n69lj;I512>J0:00:w)87b;063>{n:<91<75f24;94?=n:>>1<75f62:94?=h>:=1<75rb07bg?6==3:1<v*81d87f`=O?;<0@:<6:0y'2=d=:<=0qd<:3;29?l4213:17d<84;29?l0403:17b8<7;29?xd6=0l1<7;50;2x 27b2=hn7E9=6:N46<<6s-<3n7<:7:j605=831b>8750;9j622=831b:>650;9l261=831vn<;n0;291?6=8r.<=h4;bd9K370<D>826<u+69`9601<u`8>?7>5;h06=?6=3`8<87>5;h40<?6=3f<8;7>5;|`21d7=83?1<7>t$63f>1db3A=9:6B82882!0?j38>;6sf24194?=n:<31<75f26694?=n>:21<75`62594?=zj8?j>7>55;294~"09l0?nh5G7348H24>28q/:5l52458yl42;3:17d<:9;29?l40<3:17d8<8;29?j04?3:17pl>5`194?3=83:p(:?j:5`f?M15>2F<>44>{%4;f?42?2wb>8=50;9j60?=831b>::50;9j26>=831d:>950;9~f43f<3:197>50z&45`<3jl1C;?84L60:>4}#>1h1>894}h067?6=3`8>57>5;h040?6=3`<847>5;n403?6=3th::=>50;794?6|,>;n69lj;I512>J0:00:w)87b;063>{n:<91<75f24;94?=n:>>1<75f62:94?=h>:=1<75rb0435?6==3:1<v*81d87f`=O?;<0@:<6:0y'2=d=:<=0qd<:3;29?l4213:17d<84;29?l0403:17b8<7;29?xd6>921<7;50;2x 27b2=hn7E9=6:N46<<6s-<3n7<:7:j605=831b>8750;9j622=831b:>650;9l261=831vn<8?9;291?6=8r.<=h4;bd9K370<D>826<u+69`9601<u`8>?7>5;h06=?6=3`8<87>5;h40<?6=3f<8;7>5;|`225g=83?1<7>t$63f>1db3A=9:6B82882!0?j38>;6sf24194?=n:<31<75f26694?=n>:21<75`62594?=zj8<;n7>55;294~"09l0?nh5G7348H24>28q/:5l52458yl42;3:17d<:9;29?l40<3:17d8<8;29?j04?3:17pl>61a94?3=83:p(:?j:5`f?M15>2F<>44>{%4;f?42?2wb>8=50;9j60?=831b>::50;9j26>=831d:>950;9~f407l3:197>50z&45`<3jl1C;?84L60:>4}#>1h1>894}h067?6=3`8>57>5;h040?6=3`<847>5;n403?6=3th::=k50;794?6|,>;n69lj;I512>J0:00:w)87b;063>{n:<91<75f24;94?=n:>>1<75f62:94?=h>:=1<75rb043b?6==3:1<v*81d87f`=O?;<0@:<6:0y'2=d=:<=0qd<:3;29?l4213:17d<84;29?l0403:17b8<7;29?xd6>981<7;50;2x 27b2=hn7E9=6:N46<<6s-<3n7<:7:j605=831b>8750;9j622=831b:>650;9l261=831vn<8?3;291?6=8r.<=h4;bd9K370<D>826<u+69`9601<u`8>?7>5;h06=?6=3`8<87>5;h40<?6=3f<8;7>5;|`2252=83?1<7>t$63f>1db3A=9:6B82882!0?j38>;6sf24194?=n:<31<75f26694?=n>:21<75`62594?=zj8<;97>55;294~"09l0?nh5G7348H24>28q/:5l52458yl42;3:17d<:9;29?l40<3:17d8<8;29?j04?3:17pl>61494?3=83:p(:?j:5`f?M15>2F<>44>{%4;f?42?2wb>8=50;9j60?=831b>::50;9j26>=831d:>950;9~f407?3:197>50z&45`<3jl1C;?84L60:>4}#>1h1>894}h067?6=3`8>57>5;h040?6=3`<847>5;n403?6=3th::9<50;794?6|,>;n69lj;I512>J0:00:w)87b;063>{n:<91<75f24;94?=n:>>1<75f62:94?=h>:=1<75rb0477?6==3:1<v*81d87f`=O?;<0@:<6:0y'2=d=:<=0qd<:3;29?l4213:17d<84;29?l0403:17b8<7;29?xd6>=k1<7;50;2x 27b2=hn7E9=6:N46<<6s-<3n7<:7:j605=831b>8750;9j622=831b:>650;9l261=831vn<8;b;291?6=8r.<=h4;bd9K370<D>826<u+69`9601<u`8>?7>5;h06=?6=3`8<87>5;h40<?6=3f<8;7>5;|`221e=83?1<7>t$63f>1db3A=9:6B82882!0?j38>;6sf24194?=n:<31<75f26694?=n>:21<75`62594?=zj8<?h7>55;294~"09l0?nh5G7348H24>28q/:5l52458yl42;3:17d<:9;29?l40<3:17d8<8;29?j04?3:17pl>65g94?3=83:p(:?j:5`f?M15>2F<>44>{%4;f?42?2wb>8=50;9j60?=831b>::50;9j26>=831d:>950;9~f403n3:197>50z&45`<3jl1C;?84L60:>4}#>1h1>894}h067?6=3`8>57>5;h040?6=3`<847>5;n403?6=3th::8>50;794?6|,>;n69lj;I512>J0:00:w)87b;063>{n:<91<75f24;94?=n:>>1<75f62:94?=h>:=1<75rb0465?6==3:1<v*81d87f`=O?;<0@:<6:0y'2=d=:<=0qd<:3;29?l4213:17d<84;29?l0403:17b8<7;29?xd6>=>1<7;50;2x 27b2=hn7E9=6:N46<<6s-<3n7<:7:j605=831b>8750;9j622=831b:>650;9l261=831vn<8;5;291?6=8r.<=h4;bd9K370<D>826<u+69`9601<u`8>?7>5;h06=?6=3`8<87>5;h40<?6=3f<8;7>5;|`2210=83?1<7>t$63f>1db3A=9:6B82882!0?j38>;6sf24194?=n:<31<75f26694?=n>:21<75`62594?=zj8<?;7>55;294~"09l0?nh5G7348H24>28q/:5l52458yl42;3:17d<:9;29?l40<3:17d8<8;29?j04?3:17pl>65:94?3=83:p(:?j:5`f?M15>2F<>44>{%4;f?42?2wb>8=50;9j60?=831b>::50;9j26>=831d:>950;9~f40313:197>50z&45`<3jl1C;?84L60:>4}#>1h1>894}h067?6=3`8>57>5;h040?6=3`<847>5;n403?6=3th:;?750;794?6|,>;n69lj;I512>J0:00:w)87b;063>{n:<91<75f24;94?=n:>>1<75f62:94?=h>:=1<75rb051e?6==3:1<v*81d87f`=O?;<0@:<6:0y'2=d=:<=0qd<:3;29?l4213:17d<84;29?l0403:17b8<7;29?xd6?:;1<7;50;2x 27b2=hn7E9=6:N46<<6s-<3n7<:7:j605=831b>8750;9j622=831b:>650;9l261=831vn<9<2;291?6=8r.<=h4;bd9K370<D>826<u+69`9601<u`8>?7>5;h06=?6=3`8<87>5;h40<?6=3f<8;7>5;|`2365=83?1<7>t$63f>1db3A=9:6B82882!0?j38>;6sf24194?=n:<31<75f26694?=n>:21<75`62594?=zj8=887>55;294~"09l0?nh5G7348H24>28q/:5l52458yl42;3:17d<:9;29?l40<3:17d8<8;29?j04?3:17pl>72794?3=83:p(:?j:5`f?M15>2F<>44>{%4;f?42?2wb>8=50;9j60?=831b>::50;9j26>=831d:>950;9~f414>3:197>50z&45`<3jl1C;?84L60:>4}#>1h1>894}h067?6=3`8>57>5;h040?6=3`<847>5;n403?6=3th:;>950;794?6|,>;n69lj;I512>J0:00:w)87b;063>{n:<91<75f24;94?=n:>>1<75f62:94?=h>:=1<75rb050<?6==3:1<v*81d87f`=O?;<0@:<6:0y'2=d=:<=0qd<:3;29?l4213:17d<84;29?l0403:17b8<7;29?xd6?;h1<7;50;2x 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3>>28h:m6`98982?xu6j821<7<t=0ag>1>034>j97:77:&5<<<6j8k0b;67:39~w4d6?3:1>v3>ce87<3=:<h?18584$7::>4d6i2d=454<;|q2f40=838p1<mk:5:6?82f=3>396*98882f4g<f?23695rs0`21?6=:r7:oi4;859>0d3=<1>0(;66:0`2e>h1010>7p}>b3694?4|58io697<;<6b1?2>;2.=444>b0c8j3>?2?1v<l=3;296~;6km0?5?524`790<4<,?226<l>a:l5<=<03ty:n?<50;0x94ec2=3:70:n5;6:5>"1000:n<o4n7:;>==z{8h9=7>52z?2ga<319168l;54828 3>>28h:m6`9898:?xu6j;:1<7<t=0ag>1>a34>j97:7f:&5<<<6j8k0b;67:`9~w4d6n3:1>v3>ce87<`=:<h?185k4$7::>4d6i2d=454m;|q2f4c=838p1<mk:5:g?82f=3>3h6*98882f4g<f?236n5rs0`2`?6=:r7:oi4;8b9>0d3=<1i0(;66:0`2e>h1010o7p}>b0a94?4|58io696m;<6b1?2?j2.=444>b0c8j3>?2l1v<l>4;296~;6km0?4>524`790=5<,?226<l>a:l5<=<a3ty:n?j50;0x94ec2=km70:n5;6bb>"1000:n?m4n7:;>5=z{8h9n7>52z?2ga<3im168l;54`f8 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3>>28h9o6`9898:?xu6j:81<7<t=0ag>1d334>j97:m4:&5<<<6j;i0b;67:`9~w4d493:1>v3>ce87f6=:<h?18o=4$7::>4d5k2d=454m;|q2f66=838p1<mk:5`1?82f=3>i>6*98882f7e<f?236n5rs0`1b?6=:r7:oi4;b09>0d3=<k;0(;66:0`1g>h1010o7p}>b3g94?4|58io69l?;<6b1?2e82.=444>b3a8j3>?2l1v<l=6;296~;6km0?m5524`790d><,?226<l=c:l5<=<a3ty:n?;50;0x94ec2=k<70:n5;6b3>{t9h2i6=4={<3``?7c927?m84>d09~w4g2<3:1>v3>a469261<5;>n68>n;|q27g<72;qU=>l4=0c4a?04?2wx=>o50;0xZ45f34;j;i49369~w45>2909wS?<9:?2e2e=>:=0q~?<8;296~X6;116=l9m:714?xu6;>0;6?uQ125894g0i3<8;6s|12494?4|V89=70?n788572=z{89>6=4={_301>;6i>21:>94}r300?6=:rT:?9521`54>3503ty:?>4?:3y]565<58k<:78<7:p564=838pR<==;<3b30<1;>1v<=k:181[74l27:m5856258yv74k3:1>vP>3b9>5d>22?9<7p}>a6094?4|58k3878<7:?20a<28h1/:5751`4a?k0?03i0q~?n7083>7}:9h286;=8;<37f?37i2.=444>a7`8j3>?2m1v<o80;296~;6i181:>94=06:>06f3-<357?n6c9m2=>=m2wx=l8i:18187f080=?:52155915g<,?226<o9b:l5<=<a3ty:m;k50;0x94g?83<8;63>44864d=#>131=l8m;o4;<?773ty:m;j50;0x94g0n3<8;63>42864d=#>131=l8m;o4;<?763ty:m;m50;0x94g0<3<8;63>40864d=#>131=l8m;o4;<?753ty:m;o50;0x94g0;3<8;63>3g864d=#>131=l8m;o4;<?743ty:n8=50;6x94d2;3<8;63>b469622<58h>:7;?c:?472<28j1v<l:4;290~;6j<>1:>94=0`63?40<27:n88551`892502<;87p}>9ec94?2|58k:?78<7:?2e76=:>>018:<:51b?87f:;0><n5+69;95<ba3g<347;4}r3:a5<72;q6=l?7:714?833;3>?=6*98882=a`<f?236=5rs0;ga?6=:r7:m<95625890242=9m7)879;3:`c=i>121=6s|18fg>5<5s4;j=;49369>115=<:n0(;66:0;gb>h101097p}>9ea94?4|58k:978<7:?606<3;j1/:57518fe?k0?0390q~?6dc83>7}:9h;?6;=8;<777?24j2.=444>9ed8j3>?2=1v<7k9;296~;6i881:>94=460>15>3-<357?6dg9m2=>=>2wx=4j8:18187f990=?:525519060<,?226<7kf:l5<=<03ty:5i850;0x94g7n3<8;63:428771=#>131=4ji;o4;<?><uz;2h84?:3y>5d6b2?9<70;;3;607>"1000:5ih4n7:;><=z{83o87>52z?2e5b=>:=018:<:511?!0?13;2hk5a69:9e>{t90n86=4={<3b4f<1;>1699=54238 3>>283oj6`9898a?xu61m81<7<t=0c3f?04?27>8>4;2g9'2=?=90nm7c878;a8yv7>l80;6?u21`2b>35034???7:=e:&5<<<61ml0b;67:e9~w4?c83:1>v3>a1;9261<5<>869<k;%4;=?7>lo1e:565e:p5<ea2909w0?n098572=:==918?l4$7::>4?cn2d=454i;|q2=fc=838p1<o?7;403>;2<:0?>l5+69;95<ba3g<347??;|q2=`>=838p1<o>f;403>;2<:0?8o5+69;95<ba3g<347?>;|q2=`1=838p1<o>e;403>;2<:0?8l5+69;95<ba3g<347?=;|q2=`0=838p1<o>d;403>;2<:0?845+69;95<ba3g<347?<;|q2=`3=838p1<o>c;403>;2<:0?8:5+69;95<ba3g<347?;;|q2=`2=838p1<o>b;403>;2<:0?8;5+69;95<ba3g<347?:;|q2=`5=838p1<o>a;403>;2<:0?885+69;95<ba3g<347?9;|q2=`4=838p1<o>9;403>;2<:0?895+69;95<ba3g<347?8;|q2=`7=838p1<o>1;403>;2<:0?8?5+69;95<ba3g<347?7;|q2=a>=838p1<o?6;403>;2<:0??55+69;95<ba3g<347?6;|q2=fb=838p1<o?5;403>;2<:0?>45+69;95<ba3g<347?n;|q2e76=838p1<o=0;403>;6i;819=l4}r3b16<72;q6=l;<:714?87f==09;95rs0`63?6=;r7:oi493e9>0d3=>:n01<l:7;403>{t9>n?6=4<{<34`1<5?=16=:j;:714?870l?0><l5rs05gb?6=<r7:;k>5625890b42;2970;k3;16g>;2;=0><l5+69;952bb3g<347>4}r34`a<72<q6=:ki:714?83c;38in63:d2801g=:=:;19=o4=610>06d3-<357?8dd9m2=>=92wx=:jl:187870ml0=?:525e196g?<5<n86>;8;<71b?37i2.=444>7eg8j3>?2;1v<9kb;290~;6?ln1:>94=4f0>7d?34?o?7=;c:?66a<28h1/:57516ff?k0?0390q~?8d`83>1}:9>oh6;=8;<7g7?4e<27>h>4<409>17d==9k0(;66:05ga>h1010?7p}>7e;94?2|58=nn78<7:?6`6<5i0169i=53268904>2<:j7)879;34``=i>12196s|16f;>5<1s4;<il49369>1a5=:0o018j<:206?81493?;m63834864f=:?:919=l4$7::>41cm2d=4549;|q23a1=83>p1<9j9;403>;2l:095<525e1970c<5<8=68>n;%4;=?70ll1e:5657:p2a?=839pR;j6;<3``?0b;27=hl49019'2=?=>m20b;67:19~w3b12908wS8k6:?2ga<1m816:i956128 3>>2?n37c878;38yv0c<3:1?vP9d59>5fb=>l:01;j::723?!0?13<o46`98981?xu1l;0;6>uQ6e0894ec2?nm708k3;434>"1000=h55a69:97>{t>m:1<7=t^7f3?87dl3<oi639d08545=#>131:i64n7:;>1=z{?in6=4<{_4`a>;6km0=hi526bd9256<,?226;j7;o4;<?3<uz<ho7>53z\5gf=:9jn1:im4=7ag>3673-<3578k8:l5<=<13ty=ol4?:2y]2fg<58io6;jm;<4`f?0782.=4449d99m2=>=?2wx>9j50;cxZ72c34;8j79>b:?204<09k16=9=570`894222>;i70?;7;52f>;6<k0<=o5215f934d<58>26:?m;<07a?0782wx=9m50;1xZ42d34;hh7?:6:?20a<1891v<:n:180[73i27:oi4>559>51d=>9:0q~?;8;297~X6<116=nj51418942>2?:;7p}>4783>6}Y9=<01<mk:071?873?3<;<6s|15694?5|V8>?70?ld;365>;6<<0=<=5rs061>5<4sW;?>63>ce8215=:9=91:=>4}r374?6=;rT:8=521bf951`<58>:6;>?;|q27`<72:qU=>k4=0ag>42b34;8j78?0:p5g322909w0?m5685<0=:9k?=6;>?;|q473<720q6=:k6:71;?870mh0=?55216ga>35?34;<in49399>52cc2?9370?8ed857==:9>om6;=7;<34b5<10<16;>956128yv7>nj0;6?u21`3;>71334???7890:&5<<<61oh0b;67:19~w4?ai3:1>v3>a059622<5<>86;;j;%4;=?7>nk1e:5651:p5<`>2909w0?n178131=:==91:8m4$7::>4?aj2d=454=;|q2=c>=838p1<o>5;040>;2<:0=9o5+69;95<`e3g<347=4}r3:b2<72;q6=l?;:357?833;3<>m6*98882=cd<f?23695rs0;e2?6=:r7:m<=5266890242??27)879;3:bg=i>12196s|18d6>5<5s4;j=?4=759>115=><20(;66:0;ef>h1010=7p}>9g194?4|58k:<7<84:?606<1=<1/:57518da?k0?03=0q~?6f383>7}:9h:m6?9;;<777?02;2.=444>9g`8j3>?211v<7i1;296~;6i9o1>::4=460>3353-<357?6fc9m2=>=12wx=4h?:18187f8m09;9525519207<,?226<7ib:l5<=<f3ty:5hh50;0x94g7k38<863:428515=#>131=4hm;o4;<?d<uz;2ih4?:3y>5d6e2;=?70;;3;47a>"1000:5kl4n7:;>f=z{83nh7>52z?2e5g=:>>018:<:76g?!0?13;2jo5a69:9`>{t90oh6=4={<3b4<<5?=1699=565a8 3>>283mn6`9898f?xu61lh1<7<t=0c3<?40<27>8>494`9'2=?=90li7c878;d8yv7>mh0;6?u21`24>71334???78;9:&5<<<61oh0b;67:028yv7f8=0;6?u21`3e>71334???7874:&5<<<61oh0b;67:038yv7f8:0;6?u21`3f>71334???7873:&5<<<61oh0b;67:008yv7f8;0;6?u21`3g>71334???7872:&5<<<61oh0b;67:018yv7f880;6?u21`3`>71334???7870:&5<<<61oh0b;67:068yv7f890;6?u21`3a>71334???788f:&5<<<61oh0b;67:078yv7>no0;6?u21`3b>71334???788b:&5<<<61oh0b;67:048yv7>nl0;6?u21`3:>71334???7880:&5<<<61oh0b;67:058yv7>nm0;6?u21`32>71334???7895:&5<<<61oh0b;67:0:8yv7>n=0;6?u21`25>71334???78:7:&5<<<61oh0b;67:0;8yv7>m00;6?u21`26>71334???78;8:&5<<<61oh0b;67:0c8yv70l<0;6?u25e19341<58=o:78?0:p5d46290hw0?8e8811<=:9>oj6?;6;<34ag<5=016=:kl:37:?870mm09945216gf>73>34;<ik4=589>52`72;?270?n238545=:?:?19=l4=614>06e34=8?7;>3:p52c?2909w0?8f18131=:=m91:5<4$7::>41b?2d=454?;|q23`0=838p1<9jf;040>;2l:0=4=5+69;952c03g<347?4}r34a0<72;q6=:kj:357?83c;3<<j6*988823`1<f?236?5rs05f0?6=:r7:;hj5266890b42?=i7)879;34a2=i>121?6s|16g0>5<5s4;<in4=759>1a5=>>:0(;66:05f3>h1010?7p}>7d094?4|58=nn7<84:?6`6<1><1/:57516g4?k0?03?0q~?8e083>7}:9>oj6?9;;<7g7?02?2.=444>7d58j3>?2?1v<9j0;296~;6?l31>::4=4f0>32?3-<357?8e69m2=>=?2wx9>=50;0xZ05434?8878?0:&5<<<2;;1e:5650:p166=838pR8=?;<705?0782.=444:339m2=>=92wx;><50;0x941c<3<84638328545=z{<8n6=4={_71a>;2:o0=<=5+69;9164<f?236?5rs40`>5<5sW?9o63:2e8545=#>1319><4n7:;>6=z{<8j6=4={_71e>;2:k0=<=5+69;9164<f?23695rs40;>5<5sW?9463:288545=#>1319><4n7:;>0=z{<8<6=4={_713>;0;80=<=5+69;9164<f?236;5rs617>5<5s4;<h949849>363=>9:0q~;=5;296~X2:<169?856128 3>>2<997c878;58yv43n3:18v382687g6=Y>j30R?:l;_07b>{t9k?26=46{<4ge?16j27=oo481c9>2fb=?8h01;mi:63a?80c93=:n639d4845g=:>m=1;<l4=7f0>27e34;i9l49019~yx{zHIIp8kj?:5d2aa3>1tJKNv>r@ARxyEF
\ No newline at end of file
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.pad b/MCL86jr/FPGA/MCL86jr/MCL86jr.pad
new file mode 100644
index 0000000..bef47af
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.pad
@@ -0,0 +1,174 @@
+Release 14.7 - par P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Wed Nov 11 19:11:33 2020
+
+
+# NOTE: This file is designed to be imported into a spreadsheet program
+# such as Microsoft Excel for viewing, printing and sorting. The |
+# character is used as the data field separator. This file is also designed
+# to support parsing.
+#
+INPUT FILE:       MCL86jr_map.ncd
+OUTPUT FILE:      MCL86jr.pad
+PART TYPE:        xc6slx9
+SPEED GRADE:      -3
+PACKAGE:          tqg144
+
+Pinout by Pin Number:
+
+-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
+Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
+P1|A13|IOB|IO_L83N_VREF_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
+P2|A16|IOB|IO_L83P_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
+P3|||GND||||||||||||
+P4|||VCCO_3|||3|||||3.30||||
+P5|A12|IOB|IO_L52N_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
+P6|A17|IOB|IO_L52P_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
+P7|A11|IOB|IO_L51N_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
+P8|A18|IOB|IO_L51P_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
+P9|A10|IOB|IO_L50N_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
+P10|A19|IOB|IO_L50P_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
+P11|A9|IOB|IO_L49N_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
+P12|SSO_n|IOB|IO_L49P_3|OUTPUT|PCI33_3|3||||||LOCATED|NO|NONE|
+P13|||GND||||||||||||
+P14|A8|IOB|IO_L44N_GCLK20_3|OUTPUT|PCI33_3|3||||||LOCATED|YES|NONE|
+P15||IOBM|IO_L44P_GCLK21_3|UNUSED||3|||||||||
+P16|BUF2_DIR|IOB|IO_L43N_GCLK22_IRDY2_3|OUTPUT|PCI33_3|3||||||LOCATED|NO|NONE|
+P17||IOBM|IO_L43P_GCLK23_3|UNUSED||3|||||||||
+P18|||VCCO_3|||3|||||3.30||||
+P19|||VCCINT||||||||1.2||||
+P20|||VCCAUX||||||||2.5||||
+P21|BUF2_OE_n|IOB|IO_L42N_GCLK24_3|OUTPUT|PCI33_3|3||||||LOCATED|NO|NONE|
+P22|AD7|IOB|IO_L42P_GCLK25_TRDY2_3|BIDIR|PCI33_3|3||||NONE||LOCATED|YES|NONE|
+P23|AD6|IOB|IO_L41N_GCLK26_3|BIDIR|PCI33_3|3||||NONE||LOCATED|YES|NONE|
+P24||IOBM|IO_L41P_GCLK27_3|UNUSED||3|||||||||
+P25|||GND||||||||||||
+P26|AD5|IOB|IO_L37N_3|BIDIR|PCI33_3|3||||NONE||LOCATED|YES|NONE|
+P27|AD4|IOB|IO_L37P_3|BIDIR|PCI33_3|3||||NONE||LOCATED|YES|NONE|
+P28|||VCCINT||||||||1.2||||
+P29||IOBS|IO_L36N_3|UNUSED||3|||||||||
+P30||IOBM|IO_L36P_3|UNUSED||3|||||||||
+P31|||VCCO_3|||3|||||3.30||||
+P32|AD3|IOB|IO_L2N_3|BIDIR|PCI33_3|3||||NONE||LOCATED|YES|NONE|
+P33|AD2|IOB|IO_L2P_3|BIDIR|PCI33_3|3||||NONE||LOCATED|YES|NONE|
+P34|AD1|IOB|IO_L1N_VREF_3|BIDIR|PCI33_3|3||||NONE||LOCATED|YES|NONE|
+P35|AD0|IOB|IO_L1P_3|BIDIR|PCI33_3|3||||NONE||LOCATED|YES|NONE|
+P36|||VCCAUX||||||||2.5||||
+P37|||PROGRAM_B_2||||||||||||
+P38||IOBS|IO_L65N_CSO_B_2|UNUSED||2|||||||||
+P39||IOBM|IO_L65P_INIT_B_2|UNUSED||2|||||||||
+P40||IOBS|IO_L64N_D9_2|UNUSED||2|||||||||
+P41|ALE|IOB|IO_L64P_D8_2|OUTPUT|PCI33_3|2||||||LOCATED|YES|NONE|
+P42|||VCCO_2|||2|||||3.30||||
+P43||IOBS|IO_L62N_D6_2|UNUSED||2|||||||||
+P44|NMI|IOB|IO_L62P_D5_2|INPUT|LVCMOS33|2|||PULLDOWN|NONE||LOCATED|YES|NONE|
+P45|INTR|IOB|IO_L49N_D4_2|INPUT|PCI33_3|2||||NONE||LOCATED|YES|NONE|
+P46|CLK|IOB|IO_L49P_D3_2|INPUT|PCI33_3|2||||NONE||LOCATED|YES|NONE|
+P47|RESET|IOB|IO_L48N_RDWR_B_VREF_2|INPUT|PCI33_3|2||||NONE||LOCATED|NO|NONE|
+P48|READY|IOB|IO_L48P_D7_2|INPUT|PCI33_3|2||||NONE||LOCATED|YES|NONE|
+P49|||GND||||||||||||
+P50|RD_n|IOB|IO_L31N_GCLK30_D15_2|OUTPUT|PCI33_3|2||||||LOCATED|YES|NONE|
+P51|WR_n|IOB|IO_L31P_GCLK31_D14_2|OUTPUT|PCI33_3|2||||||LOCATED|YES|NONE|
+P52|||VCCINT||||||||1.2||||
+P53|||VCCAUX||||||||2.5||||
+P54|||GND||||||||||||
+P55|IOM|IOB|IO_L30N_GCLK0_USERCCLK_2|OUTPUT|PCI33_3|2||||||LOCATED|YES|NONE|
+P56|DTR|IOB|IO_L30P_GCLK1_D13_2|OUTPUT|PCI33_3|2||||||LOCATED|YES|NONE|
+P57|DEN|IOB|IO_L14N_D12_2|OUTPUT|PCI33_3|2||||||LOCATED|YES|NONE|
+P58|INTA_n|IOB|IO_L14P_D11_2|OUTPUT|PCI33_3|2||||||LOCATED|YES|NONE|
+P59|BUF1_OE_n|IOB|IO_L13N_D10_2|OUTPUT|PCI33_3|2||||||LOCATED|NO|NONE|
+P60||IOBM|IO_L13P_M1_2|UNUSED||2|||||||||
+P61|SRAM_A<4>|IOB|IO_L12N_D2_MISO3_2|OUTPUT|PCI33_3|2||||||LOCATED|NO|NONE|
+P62|SRAM_A<5>|IOB|IO_L12P_D1_MISO2_2|OUTPUT|PCI33_3|2||||||LOCATED|NO|NONE|
+P63|||VCCO_2|||2|||||3.30||||
+P64||IOBS|IO_L3N_MOSI_CSI_B_MISO0_2|UNUSED||2|||||||||
+P65||IOBM|IO_L3P_D0_DIN_MISO_MISO1_2|UNUSED||2|||||||||
+P66|SRAM_A<6>|IOB|IO_L2N_CMPMOSI_2|OUTPUT|PCI33_3|2||||||LOCATED|NO|NONE|
+P67|SRAM_A<7>|IOB|IO_L2P_CMPCLK_2|OUTPUT|PCI33_3|2||||||LOCATED|NO|NONE|
+P68|||GND||||||||||||
+P69||IOBS|IO_L1N_M0_CMPMISO_2|UNUSED||2|||||||||
+P70||IOBM|IO_L1P_CCLK_2|UNUSED||2|||||||||
+P71|||DONE_2||||||||||||
+P72|||CMPCS_B_2||||||||||||
+P73|||SUSPEND||||||||||||
+P74|SRAM_A<12>|IOB|IO_L74N_DOUT_BUSY_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
+P75|SRAM_A<14>|IOB|IO_L74P_AWAKE_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
+P76|||VCCO_1|||1|||||3.30||||
+P77|||GND||||||||||||
+P78|SRAM_A<16>|IOB|IO_L47N_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
+P79|SRAM_A<17>|IOB|IO_L47P_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
+P80|SRAM_D<3>|IOB|IO_L46N_1|BIDIR|PCI33_3|1||||NONE||LOCATED|NO|NONE|
+P81|SRAM_D<4>|IOB|IO_L46P_1|BIDIR|PCI33_3|1||||NONE||LOCATED|NO|NONE|
+P82|SRAM_D<5>|IOB|IO_L45N_1|BIDIR|PCI33_3|1||||NONE||LOCATED|NO|NONE|
+P83|SRAM_D<6>|IOB|IO_L45P_1|BIDIR|PCI33_3|1||||NONE||LOCATED|NO|NONE|
+P84|CORE_CLK|IOB|IO_L43N_GCLK4_1|INPUT|PCI33_3|1||||NONE||LOCATED|NO|NONE|
+P85|SRAM_D<7>|IOB|IO_L43P_GCLK5_1|BIDIR|PCI33_3|1||||NONE||LOCATED|NO|NONE|
+P86|||VCCO_1|||1|||||3.30||||
+P87|SRAM_CE_n|IOB|IO_L42N_GCLK6_TRDY1_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
+P88|SRAM_A<10>|IOB|IO_L42P_GCLK7_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
+P89|||VCCINT||||||||1.2||||
+P90|||VCCAUX||||||||2.5||||
+P91|||GND||||||||||||
+P92|SRAM_OE_n|IOB|IO_L41N_GCLK8_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
+P93|SRAM_A<11>|IOB|IO_L41P_GCLK9_IRDY1_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
+P94|SRAM_A<9>|IOB|IO_L40N_GCLK10_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
+P95|SRAM_A<8>|IOB|IO_L40P_GCLK11_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
+P96|||GND||||||||||||
+P97|SRAM_A<13>|IOB|IO_L34N_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
+P98|SRAM_WE_n|IOB|IO_L34P_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
+P99|SRAM_A<18>|IOB|IO_L33N_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
+P100|SRAM_A<15>|IOB|IO_L33P_1|OUTPUT|PCI33_3|1||||||LOCATED|NO|NONE|
+P101||IOBS|IO_L32N_1|UNUSED||1|||||||||
+P102||IOBM|IO_L32P_1|UNUSED||1|||||||||
+P103|||VCCO_1|||1|||||3.30||||
+P104||IOBS|IO_L1N_VREF_1|UNUSED||1|||||||||
+P105||IOBM|IO_L1P_1|UNUSED||1|||||||||
+P106|||TDO||||||||||||
+P107|||TMS||||||||||||
+P108|||GND||||||||||||
+P109|||TCK||||||||||||
+P110|||TDI||||||||||||
+P111|LED<0>|IOB|IO_L66N_SCP0_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
+P112|LED<1>|IOB|IO_L66P_SCP1_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
+P113|||GND||||||||||||
+P114|LED<2>|IOB|IO_L65N_SCP2_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
+P115||IOBM|IO_L65P_SCP3_0|UNUSED||0|||||||||
+P116|LED<3>|IOB|IO_L64N_SCP4_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
+P117|SRAM_D<2>|IOB|IO_L64P_SCP5_0|BIDIR|PCI33_3|0||||NONE||LOCATED|NO|NONE|
+P118|SRAM_D<1>|IOB|IO_L63N_SCP6_0|BIDIR|PCI33_3|0||||NONE||LOCATED|NO|NONE|
+P119|SRAM_D<0>|IOB|IO_L63P_SCP7_0|BIDIR|PCI33_3|0||||NONE||LOCATED|NO|NONE|
+P120|LED<4>|IOB|IO_L62N_VREF_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
+P121|LED<5>|IOB|IO_L62P_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
+P122|||VCCO_0|||0|||||3.30||||
+P123|SRAM_A<3>|IOB|IO_L37N_GCLK12_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
+P124|SRAM_A<2>|IOB|IO_L37P_GCLK13_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
+P125|||VCCO_0|||0|||||3.30||||
+P126|SRAM_A<1>|IOB|IO_L36N_GCLK14_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
+P127|LED<6>|IOB|IO_L36P_GCLK15_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
+P128|||VCCINT||||||||1.2||||
+P129|||VCCAUX||||||||2.5||||
+P130|||GND||||||||||||
+P131|LED<7>|IOB|IO_L35N_GCLK16_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
+P132|SRAM_A<0>|IOB|IO_L35P_GCLK17_0|OUTPUT|PCI33_3|0||||||LOCATED|NO|NONE|
+P133||IOBS|IO_L34N_GCLK18_0|UNUSED||0|||||||||
+P134||IOBM|IO_L34P_GCLK19_0|UNUSED||0|||||||||
+P135|||VCCO_0|||0|||||3.30||||
+P136|||GND||||||||||||
+P137||IOBS|IO_L4N_0|UNUSED||0|||||||||
+P138||IOBM|IO_L4P_0|UNUSED||0|||||||||
+P139||IOBS|IO_L3N_0|UNUSED||0|||||||||
+P140||IOBM|IO_L3P_0|UNUSED||0|||||||||
+P141||IOBS|IO_L2N_0|UNUSED||0|||||||||
+P142|A14|IOB|IO_L2P_0|OUTPUT|PCI33_3|0||||||LOCATED|YES|NONE|
+P143|A15|IOB|IO_L1N_VREF_0|OUTPUT|PCI33_3|0||||||LOCATED|YES|NONE|
+P144||IOBM|IO_L1P_HSWAPEN_0|UNUSED||0|||||||||
+
+-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
+
+* Default value.
+** This default Pullup/Pulldown value can be overridden in Bitgen. 
+****** Special VCCO requirements may apply. Please consult the device 
+       family datasheet for specific guideline on VCCO requirements. 
+
+
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.par b/MCL86jr/FPGA/MCL86jr/MCL86jr.par
new file mode 100644
index 0000000..f27cf4c
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.par
@@ -0,0 +1,228 @@
+Release 14.7 par P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+MICROCORELABS::  Wed Nov 11 19:10:59 2020
+
+par -w -intstyle ise -ol high -xe n -mt off MCL86jr_map.ncd MCL86jr.ncd
+MCL86jr.pcf 
+
+
+Constraints file: MCL86jr.pcf.
+Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
+   "MCL86jr" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -3
+
+Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
+Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
+
+
+Device speed data version:  "PRODUCTION 1.23 2013-10-13".
+
+
+
+Device Utilization Summary:
+
+Slice Logic Utilization:
+  Number of Slice Registers:                   853 out of  11,440    7%
+    Number used as Flip Flops:                 853
+    Number used as Latches:                      0
+    Number used as Latch-thrus:                  0
+    Number used as AND/OR logics:                0
+  Number of Slice LUTs:                        959 out of   5,720   16%
+    Number used as logic:                      887 out of   5,720   15%
+      Number using O6 output only:             681
+      Number using O5 output only:              54
+      Number using O5 and O6:                  152
+      Number used as ROM:                        0
+    Number used as Memory:                      58 out of   1,440    4%
+      Number used as Dual Port RAM:              0
+      Number used as Single Port RAM:            0
+      Number used as Shift Register:            58
+        Number using O6 output only:             2
+        Number using O5 output only:             0
+        Number using O5 and O6:                 56
+    Number used exclusively as route-thrus:     14
+      Number with same-slice register load:      8
+      Number with same-slice carry load:         6
+      Number with other load:                    0
+
+Slice Logic Distribution:
+  Number of occupied Slices:                   381 out of   1,430   26%
+  Number of MUXCYs used:                       196 out of   2,860    6%
+  Number of LUT Flip Flop pairs used:        1,197
+    Number with an unused Flip Flop:           437 out of   1,197   36%
+    Number with an unused LUT:                 238 out of   1,197   19%
+    Number of fully used LUT-FF pairs:         522 out of   1,197   43%
+    Number of slice register sites lost
+      to control set restrictions:               0 out of  11,440    0%
+
+  A LUT Flip Flop pair for this architecture represents one LUT paired with
+  one Flip Flop within a slice.  A control set is a unique combination of
+  clock, reset, set, and enable signals for a registered element.
+  The Slice Logic Distribution report is not meaningful if the design is
+  over-mapped for a non-slice resource or if Placement fails.
+
+IO Utilization:
+  Number of bonded IOBs:                        75 out of     102   73%
+    Number of LOCed IOBs:                       75 out of      75  100%
+    IOB Flip Flops:                             39
+
+Specific Feature Utilization:
+  Number of RAMB16BWERs:                         7 out of      32   21%
+  Number of RAMB8BWERs:                          1 out of      64    1%
+  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3%
+    Number used as BUFIO2s:                      1
+    Number used as BUFIO2_2CLKs:                 0
+  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
+  Number of BUFG/BUFGMUXs:                       1 out of      16    6%
+    Number used as BUFGs:                        1
+    Number used as BUFGMUX:                      0
+  Number of DCM/DCM_CLKGENs:                     1 out of       4   25%
+    Number used as DCMs:                         1
+    Number used as DCM_CLKGENs:                  0
+  Number of ILOGIC2/ISERDES2s:                  12 out of     200    6%
+    Number used as ILOGIC2s:                    12
+    Number used as ISERDES2s:                    0
+  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
+  Number of OLOGIC2/OSERDES2s:                  27 out of     200   13%
+    Number used as OLOGIC2s:                    27
+    Number used as OSERDES2s:                    0
+  Number of BSCANs:                              0 out of       4    0%
+  Number of BUFHs:                               0 out of     128    0%
+  Number of BUFPLLs:                             0 out of       8    0%
+  Number of BUFPLL_MCBs:                         0 out of       4    0%
+  Number of DSP48A1s:                            0 out of      16    0%
+  Number of ICAPs:                               0 out of       1    0%
+  Number of MCBs:                                0 out of       2    0%
+  Number of PCILOGICSEs:                         0 out of       2    0%
+  Number of PLL_ADVs:                            0 out of       2    0%
+  Number of PMVs:                                0 out of       1    0%
+  Number of STARTUPs:                            0 out of       1    0%
+  Number of SUSPEND_SYNCs:                       0 out of       1    0%
+
+
+Overall effort level (-ol):   High 
+Router effort level (-rl):    High 
+
+WARNING:Timing:3402 - The Clock Modifying COMP, SPARTAN6PLL/dcm_sp_inst, has the attribute CLK_FEEDBACK set to NONE.  No phase relationship
+   exists between the input and output clocks of this Clock Modifying COMP. Data paths between these clock domains must be constrained using
+   FROM/TO constraints.
+Starting initial Timing Analysis.  REAL time: 4 secs 
+Finished initial Timing Analysis.  REAL time: 4 secs 
+
+Starting Router
+
+
+Phase  1  : 7181 unrouted;      REAL time: 4 secs 
+
+Phase  2  : 5599 unrouted;      REAL time: 5 secs 
+
+Phase  3  : 2119 unrouted;      REAL time: 8 secs 
+
+Phase  4  : 2185 unrouted; (Setup:587, Hold:47, Component Switching Limit:0)     REAL time: 9 secs 
+
+Updating file: MCL86jr.ncd with current fully routed design.
+
+Phase  5  : 0 unrouted; (Setup:6935, Hold:53, Component Switching Limit:0)     REAL time: 19 secs 
+
+Phase  6  : 0 unrouted; (Setup:769, Hold:53, Component Switching Limit:0)     REAL time: 23 secs 
+
+Updating file: MCL86jr.ncd with current fully routed design.
+
+Phase  7  : 0 unrouted; (Setup:769, Hold:53, Component Switching Limit:0)     REAL time: 32 secs 
+
+Phase  8  : 0 unrouted; (Setup:769, Hold:53, Component Switching Limit:0)     REAL time: 32 secs 
+
+Phase  9  : 0 unrouted; (Setup:769, Hold:53, Component Switching Limit:0)     REAL time: 32 secs 
+
+Phase 10  : 0 unrouted; (Setup:769, Hold:0, Component Switching Limit:0)     REAL time: 32 secs 
+
+Phase 11  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 33 secs 
+Total REAL time to Router completion: 33 secs 
+Total CPU time to Router completion: 33 secs 
+
+Partition Implementation Status
+-------------------------------
+
+  No Partitions were found in this design.
+
+-------------------------------
+
+Generating "PAR" statistics.
+
+**************************
+Generating Clock Report
+**************************
+
++---------------------+--------------+------+------+------------+-------------+
+|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
++---------------------+--------------+------+------+------------+-------------+
+|        core_clk_int |  BUFGMUX_X2Y3| No   |  321 |  0.601     |  1.669      |
++---------------------+--------------+------+------+------------+-------------+
+
+* Net Skew is the difference between the minimum and maximum routing
+only delays for the net. Note this is different from Clock Skew which
+is reported in TRCE timing report. Clock Skew is the difference between
+the minimum and maximum path delays which includes logic delays.
+
+* The fanout is the number of component pins not the individual BEL loads,
+for example SLICE loads not FF loads.
+
+Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
+
+Number of Timing Constraints that were not applied: 1
+
+Asterisk (*) preceding a constraint indicates it was not met.
+   This may be due to a setup or hold violation.
+
+----------------------------------------------------------------------------------------------------------
+  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
+                                            |             |    Slack   | Achievable | Errors |    Score   
+----------------------------------------------------------------------------------------------------------
+  TS_SPARTAN6PLL_clkfx = PERIOD TIMEGRP "SP | SETUP       |     0.299ns|     8.791ns|       0|           0
+  ARTAN6PLL_clkfx" TS_CORE_CLK / 2.2        | HOLD        |     0.367ns|            |       0|           0
+    HIGH 50%                                |             |            |            |        |            
+----------------------------------------------------------------------------------------------------------
+  TS_CORE_CLK = PERIOD TIMEGRP "CORE_CLK" 2 | MINLOWPULSE |    12.000ns|     8.000ns|       0|           0
+  0 ns HIGH 50%                             |             |            |            |        |            
+----------------------------------------------------------------------------------------------------------
+
+
+Derived Constraint Report
+Review Timing Report for more details on the following derived constraints.
+To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
+or "Run Timing Analysis" from Timing Analyzer (timingan).
+Derived Constraints for TS_CORE_CLK
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
+|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
+|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+|TS_CORE_CLK                    |     20.000ns|      8.000ns|     19.340ns|            0|            0|            0|       513828|
+| TS_SPARTAN6PLL_clkfx          |      9.091ns|      8.791ns|          N/A|            0|            0|       513828|            0|
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+
+All constraints were met.
+
+
+Generating Pad Report.
+
+All signals are completely routed.
+
+Total REAL time to PAR completion: 34 secs 
+Total CPU time to PAR completion: 34 secs 
+
+Peak Memory Usage:  421 MB
+
+Placer: Placement generated during map.
+Routing: Completed - No errors found.
+Timing: Completed - No errors found.
+
+Number of error messages: 0
+Number of warning messages: 1
+Number of info messages: 0
+
+Writing design to file MCL86jr.ncd
+
+
+
+PAR done!
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.pcf b/MCL86jr/FPGA/MCL86jr/MCL86jr.pcf
new file mode 100644
index 0000000..731e168
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.pcf
@@ -0,0 +1,756 @@
+//! **************************************************************************
+// Written by: Map P.20131013 on Wed Nov 11 19:10:56 2020
+//! **************************************************************************
+
+SCHEMATIC START;
+COMP "A8" LOCATE = SITE "P14" LEVEL 1;
+COMP "A9" LOCATE = SITE "P11" LEVEL 1;
+COMP "A10" LOCATE = SITE "P9" LEVEL 1;
+COMP "A11" LOCATE = SITE "P7" LEVEL 1;
+COMP "A12" LOCATE = SITE "P5" LEVEL 1;
+COMP "A13" LOCATE = SITE "P1" LEVEL 1;
+COMP "A14" LOCATE = SITE "P142" LEVEL 1;
+COMP "A15" LOCATE = SITE "P143" LEVEL 1;
+COMP "A16" LOCATE = SITE "P2" LEVEL 1;
+COMP "A17" LOCATE = SITE "P6" LEVEL 1;
+COMP "A18" LOCATE = SITE "P8" LEVEL 1;
+COMP "A19" LOCATE = SITE "P10" LEVEL 1;
+COMP "AD0" LOCATE = SITE "P35" LEVEL 1;
+COMP "AD1" LOCATE = SITE "P34" LEVEL 1;
+COMP "AD2" LOCATE = SITE "P33" LEVEL 1;
+COMP "AD3" LOCATE = SITE "P32" LEVEL 1;
+COMP "AD4" LOCATE = SITE "P27" LEVEL 1;
+COMP "AD5" LOCATE = SITE "P26" LEVEL 1;
+COMP "AD6" LOCATE = SITE "P23" LEVEL 1;
+COMP "AD7" LOCATE = SITE "P22" LEVEL 1;
+COMP "ALE" LOCATE = SITE "P41" LEVEL 1;
+COMP "DEN" LOCATE = SITE "P57" LEVEL 1;
+COMP "CLK" LOCATE = SITE "P46" LEVEL 1;
+COMP "DTR" LOCATE = SITE "P56" LEVEL 1;
+COMP "IOM" LOCATE = SITE "P55" LEVEL 1;
+COMP "NMI" LOCATE = SITE "P44" LEVEL 1;
+COMP "SRAM_A<0>" LOCATE = SITE "P132" LEVEL 1;
+COMP "SRAM_A<1>" LOCATE = SITE "P126" LEVEL 1;
+COMP "SRAM_A<2>" LOCATE = SITE "P124" LEVEL 1;
+COMP "SRAM_A<3>" LOCATE = SITE "P123" LEVEL 1;
+COMP "SRAM_A<4>" LOCATE = SITE "P61" LEVEL 1;
+COMP "SRAM_A<5>" LOCATE = SITE "P62" LEVEL 1;
+COMP "SRAM_A<6>" LOCATE = SITE "P66" LEVEL 1;
+COMP "SRAM_A<7>" LOCATE = SITE "P67" LEVEL 1;
+COMP "SRAM_A<8>" LOCATE = SITE "P95" LEVEL 1;
+COMP "SRAM_A<9>" LOCATE = SITE "P94" LEVEL 1;
+COMP "SRAM_D<0>" LOCATE = SITE "P119" LEVEL 1;
+COMP "SRAM_D<1>" LOCATE = SITE "P118" LEVEL 1;
+COMP "SRAM_D<2>" LOCATE = SITE "P117" LEVEL 1;
+COMP "SRAM_D<3>" LOCATE = SITE "P80" LEVEL 1;
+COMP "SRAM_D<4>" LOCATE = SITE "P81" LEVEL 1;
+COMP "SRAM_D<5>" LOCATE = SITE "P82" LEVEL 1;
+COMP "SRAM_D<6>" LOCATE = SITE "P83" LEVEL 1;
+COMP "SRAM_D<7>" LOCATE = SITE "P85" LEVEL 1;
+COMP "SRAM_CE_n" LOCATE = SITE "P87" LEVEL 1;
+COMP "SRAM_OE_n" LOCATE = SITE "P92" LEVEL 1;
+COMP "SRAM_WE_n" LOCATE = SITE "P98" LEVEL 1;
+COMP "INTR" LOCATE = SITE "P45" LEVEL 1;
+COMP "RD_n" LOCATE = SITE "P50" LEVEL 1;
+COMP "WR_n" LOCATE = SITE "P51" LEVEL 1;
+COMP "SRAM_A<10>" LOCATE = SITE "P88" LEVEL 1;
+COMP "SRAM_A<11>" LOCATE = SITE "P93" LEVEL 1;
+COMP "SRAM_A<12>" LOCATE = SITE "P74" LEVEL 1;
+COMP "SRAM_A<13>" LOCATE = SITE "P97" LEVEL 1;
+COMP "SRAM_A<14>" LOCATE = SITE "P75" LEVEL 1;
+COMP "SRAM_A<15>" LOCATE = SITE "P100" LEVEL 1;
+COMP "SRAM_A<16>" LOCATE = SITE "P78" LEVEL 1;
+COMP "SRAM_A<17>" LOCATE = SITE "P79" LEVEL 1;
+COMP "SRAM_A<18>" LOCATE = SITE "P99" LEVEL 1;
+COMP "READY" LOCATE = SITE "P48" LEVEL 1;
+COMP "RESET" LOCATE = SITE "P47" LEVEL 1;
+COMP "SSO_n" LOCATE = SITE "P12" LEVEL 1;
+COMP "LED<0>" LOCATE = SITE "P111" LEVEL 1;
+COMP "LED<1>" LOCATE = SITE "P112" LEVEL 1;
+COMP "LED<2>" LOCATE = SITE "P114" LEVEL 1;
+COMP "LED<3>" LOCATE = SITE "P116" LEVEL 1;
+COMP "LED<4>" LOCATE = SITE "P120" LEVEL 1;
+COMP "LED<5>" LOCATE = SITE "P121" LEVEL 1;
+COMP "LED<6>" LOCATE = SITE "P127" LEVEL 1;
+COMP "LED<7>" LOCATE = SITE "P131" LEVEL 1;
+COMP "INTA_n" LOCATE = SITE "P58" LEVEL 1;
+COMP "BUF1_OE_n" LOCATE = SITE "P59" LEVEL 1;
+COMP "BUF2_OE_n" LOCATE = SITE "P21" LEVEL 1;
+COMP "BUF2_DIR" LOCATE = SITE "P16" LEVEL 1;
+COMP "CORE_CLK" LOCATE = SITE "P84" LEVEL 1;
+PIN
+        EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>
+        = BEL
+        "EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram"
+        PINNAME CLKA;
+PIN
+        EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>
+        = BEL
+        "EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram"
+        PINNAME CLKA;
+PIN
+        EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>
+        = BEL
+        "EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram"
+        PINNAME CLKA;
+PIN
+        EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>
+        = BEL
+        "EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram"
+        PINNAME CLKA;
+PIN
+        EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>
+        = BEL
+        "EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram"
+        PINNAME CLKA;
+PIN
+        EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM9.ram_pins<26>
+        = BEL
+        "EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM9.ram"
+        PINNAME CLKAWRCLK;
+PIN
+        EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>
+        = BEL
+        "EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram"
+        PINNAME CLKA;
+PIN
+        EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>
+        = BEL
+        "EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram"
+        PINNAME CLKA;
+TIMEGRP SPARTAN6PLL_clkfx = BEL "t_biu_ad_out_d_0" BEL "t_biu_ad_out_d_1" BEL
+        "t_biu_ad_out_d_2" BEL "t_biu_ad_out_d_3" BEL "t_biu_ad_out_d_4" BEL
+        "t_biu_ad_out_d_5" BEL "t_biu_ad_out_d_6" BEL "t_biu_ad_out_d_7" BEL
+        "t_biu_ad_out_d_8" BEL "t_biu_ad_out_d_9" BEL "t_biu_ad_out_d_10" BEL
+        "t_biu_ad_out_d_11" BEL "t_biu_ad_out_d_12" BEL "t_biu_ad_out_d_13"
+        BEL "t_biu_ad_out_d_14" BEL "t_biu_ad_out_d_15" BEL
+        "t_biu_ad_out_d_16" BEL "t_biu_ad_out_d_17" BEL "t_biu_ad_out_d_18"
+        BEL "t_biu_ad_out_d_19" BEL "led_int_0" BEL "led_int_1" BEL
+        "led_int_2" BEL "led_int_3" BEL "led_int_4" BEL "led_int_5" BEL
+        "led_int_6" BEL "led_int_7" BEL "prescaler_d" BEL "t_reset_d3" BEL
+        "prescaler_0" BEL "prescaler_1" BEL "prescaler_2" BEL "prescaler_3"
+        BEL "prescaler_4" BEL "prescaler_5" BEL "prescaler_6" BEL
+        "prescaler_7" BEL "prescaler_8" BEL "prescaler_9" BEL "prescaler_10"
+        BEL "prescaler_11" BEL "prescaler_12" BEL "prescaler_13" BEL
+        "prescaler_14" BEL "prescaler_15" BEL "prescaler_16" BEL
+        "prescaler_17" BEL "prescaler_18" BEL "prescaler_19" BEL
+        "prescaler_20" BEL "prescaler_21" BEL "SPARTAN6PLL/clkout1_buf" BEL
+        "BIU_CORE/nmi_counter_25" BEL "BIU_CORE/nmi_counter_24" BEL
+        "BIU_CORE/nmi_counter_23" BEL "BIU_CORE/nmi_counter_22" BEL
+        "BIU_CORE/nmi_counter_21" BEL "BIU_CORE/nmi_counter_20" BEL
+        "BIU_CORE/nmi_counter_19" BEL "BIU_CORE/nmi_counter_18" BEL
+        "BIU_CORE/nmi_counter_17" BEL "BIU_CORE/nmi_counter_16" BEL
+        "BIU_CORE/nmi_counter_15" BEL "BIU_CORE/nmi_counter_14" BEL
+        "BIU_CORE/nmi_counter_13" BEL "BIU_CORE/nmi_counter_12" BEL
+        "BIU_CORE/nmi_counter_11" BEL "BIU_CORE/nmi_counter_10" BEL
+        "BIU_CORE/nmi_counter_9" BEL "BIU_CORE/nmi_counter_8" BEL
+        "BIU_CORE/nmi_counter_7" BEL "BIU_CORE/nmi_counter_6" BEL
+        "BIU_CORE/nmi_counter_5" BEL "BIU_CORE/nmi_counter_4" BEL
+        "BIU_CORE/nmi_counter_3" BEL "BIU_CORE/nmi_counter_2" BEL
+        "BIU_CORE/nmi_counter_1" BEL "BIU_CORE/nmi_counter_0" BEL
+        "BIU_CORE/pfq_addr_out_15" BEL "BIU_CORE/pfq_addr_out_14" BEL
+        "BIU_CORE/pfq_addr_out_13" BEL "BIU_CORE/pfq_addr_out_12" BEL
+        "BIU_CORE/pfq_addr_out_11" BEL "BIU_CORE/pfq_addr_out_10" BEL
+        "BIU_CORE/pfq_addr_out_9" BEL "BIU_CORE/pfq_addr_out_8" BEL
+        "BIU_CORE/pfq_addr_out_7" BEL "BIU_CORE/pfq_addr_out_6" BEL
+        "BIU_CORE/pfq_addr_out_5" BEL "BIU_CORE/pfq_addr_out_4" BEL
+        "BIU_CORE/pfq_addr_out_3" BEL "BIU_CORE/pfq_addr_out_2" BEL
+        "BIU_CORE/pfq_addr_out_1" BEL "BIU_CORE/pfq_addr_out_0" BEL
+        "BIU_CORE/pfq_addr_in_15" BEL "BIU_CORE/pfq_addr_in_14" BEL
+        "BIU_CORE/pfq_addr_in_13" BEL "BIU_CORE/pfq_addr_in_12" BEL
+        "BIU_CORE/pfq_addr_in_11" BEL "BIU_CORE/pfq_addr_in_10" BEL
+        "BIU_CORE/pfq_addr_in_9" BEL "BIU_CORE/pfq_addr_in_8" BEL
+        "BIU_CORE/pfq_addr_in_7" BEL "BIU_CORE/pfq_addr_in_6" BEL
+        "BIU_CORE/pfq_addr_in_5" BEL "BIU_CORE/pfq_addr_in_4" BEL
+        "BIU_CORE/pfq_addr_in_3" BEL "BIU_CORE/pfq_addr_in_2" BEL
+        "BIU_CORE/pfq_addr_in_1" BEL "BIU_CORE/pfq_addr_in_0" BEL
+        "BIU_CORE/clock_cycle_counter_12" BEL
+        "BIU_CORE/clock_cycle_counter_11" BEL
+        "BIU_CORE/clock_cycle_counter_10" BEL "BIU_CORE/clock_cycle_counter_9"
+        BEL "BIU_CORE/clock_cycle_counter_8" BEL
+        "BIU_CORE/clock_cycle_counter_7" BEL "BIU_CORE/clock_cycle_counter_6"
+        BEL "BIU_CORE/clock_cycle_counter_5" BEL
+        "BIU_CORE/clock_cycle_counter_4" BEL "BIU_CORE/clock_cycle_counter_3"
+        BEL "BIU_CORE/clock_cycle_counter_2" BEL
+        "BIU_CORE/clock_cycle_counter_1" BEL "BIU_CORE/clock_cycle_counter_0"
+        BEL "BIU_CORE/nmi_d5" BEL "BIU_CORE/s_bits_2" BEL "BIU_CORE/s_bits_1"
+        BEL "BIU_CORE/s_bits_0" BEL "BIU_CORE/ALE" BEL
+        "BIU_CORE/pfq_top_byte_int_d1_7" BEL "BIU_CORE/pfq_top_byte_int_d1_6"
+        BEL "BIU_CORE/pfq_top_byte_int_d1_5" BEL
+        "BIU_CORE/pfq_top_byte_int_d1_4" BEL "BIU_CORE/pfq_top_byte_int_d1_3"
+        BEL "BIU_CORE/pfq_top_byte_int_d1_2" BEL
+        "BIU_CORE/pfq_top_byte_int_d1_1" BEL "BIU_CORE/pfq_top_byte_int_d1_0"
+        BEL "BIU_CORE/nmi_d4" BEL "BIU_CORE/clk_d4" BEL
+        "BIU_CORE/pfq_addr_out_d1_15" BEL "BIU_CORE/pfq_addr_out_d1_14" BEL
+        "BIU_CORE/pfq_addr_out_d1_13" BEL "BIU_CORE/pfq_addr_out_d1_12" BEL
+        "BIU_CORE/pfq_addr_out_d1_11" BEL "BIU_CORE/pfq_addr_out_d1_10" BEL
+        "BIU_CORE/pfq_addr_out_d1_9" BEL "BIU_CORE/pfq_addr_out_d1_8" BEL
+        "BIU_CORE/pfq_addr_out_d1_7" BEL "BIU_CORE/pfq_addr_out_d1_6" BEL
+        "BIU_CORE/pfq_addr_out_d1_5" BEL "BIU_CORE/pfq_addr_out_d1_4" BEL
+        "BIU_CORE/pfq_addr_out_d1_3" BEL "BIU_CORE/pfq_addr_out_d1_2" BEL
+        "BIU_CORE/pfq_addr_out_d1_1" BEL "BIU_CORE/pfq_addr_out_d1_0" BEL
+        "BIU_CORE/intr_d3" BEL "BIU_CORE/nmi_d3" BEL "BIU_CORE/clk_d3" BEL
+        "BIU_CORE/pfq_entry2_7" BEL "BIU_CORE/pfq_entry2_6" BEL
+        "BIU_CORE/pfq_entry2_5" BEL "BIU_CORE/pfq_entry2_4" BEL
+        "BIU_CORE/pfq_entry2_3" BEL "BIU_CORE/pfq_entry2_2" BEL
+        "BIU_CORE/pfq_entry2_1" BEL "BIU_CORE/pfq_entry2_0" BEL
+        "BIU_CORE/pfq_entry1_7" BEL "BIU_CORE/pfq_entry1_6" BEL
+        "BIU_CORE/pfq_entry1_5" BEL "BIU_CORE/pfq_entry1_4" BEL
+        "BIU_CORE/pfq_entry1_3" BEL "BIU_CORE/pfq_entry1_2" BEL
+        "BIU_CORE/pfq_entry1_1" BEL "BIU_CORE/pfq_entry1_0" BEL
+        "BIU_CORE/pfq_entry3_7" BEL "BIU_CORE/pfq_entry3_6" BEL
+        "BIU_CORE/pfq_entry3_5" BEL "BIU_CORE/pfq_entry3_4" BEL
+        "BIU_CORE/pfq_entry3_3" BEL "BIU_CORE/pfq_entry3_2" BEL
+        "BIU_CORE/pfq_entry3_1" BEL "BIU_CORE/pfq_entry3_0" BEL
+        "BIU_CORE/pfq_entry0_7" BEL "BIU_CORE/pfq_entry0_6" BEL
+        "BIU_CORE/pfq_entry0_5" BEL "BIU_CORE/pfq_entry0_4" BEL
+        "BIU_CORE/pfq_entry0_3" BEL "BIU_CORE/pfq_entry0_2" BEL
+        "BIU_CORE/pfq_entry0_1" BEL "BIU_CORE/pfq_entry0_0" BEL
+        "BIU_CORE/INTA_n" BEL "BIU_CORE/DEN" BEL "BIU_CORE/RD_n" BEL
+        "BIU_CORE/WR_n" BEL "BIU_CORE/DTR" BEL "BIU_CORE/IOM" BEL
+        "BIU_CORE/intr_d2" BEL "BIU_CORE/clk_d2" BEL "BIU_CORE/SRAM_A_18" BEL
+        "BIU_CORE/SRAM_A_17" BEL "BIU_CORE/SRAM_A_16" BEL "BIU_CORE/SRAM_A_15"
+        BEL "BIU_CORE/SRAM_A_14" BEL "BIU_CORE/SRAM_A_13" BEL
+        "BIU_CORE/SRAM_A_12" BEL "BIU_CORE/SRAM_A_11" BEL "BIU_CORE/SRAM_A_10"
+        BEL "BIU_CORE/SRAM_A_9" BEL "BIU_CORE/SRAM_A_8" BEL
+        "BIU_CORE/SRAM_A_7" BEL "BIU_CORE/SRAM_A_6" BEL "BIU_CORE/SRAM_A_5"
+        BEL "BIU_CORE/SRAM_A_4" BEL "BIU_CORE/SRAM_A_3" BEL
+        "BIU_CORE/SRAM_A_2" BEL "BIU_CORE/SRAM_A_1" BEL "BIU_CORE/SRAM_A_0"
+        BEL "BIU_CORE/latched_data_in_7" BEL "BIU_CORE/latched_data_in_6" BEL
+        "BIU_CORE/latched_data_in_5" BEL "BIU_CORE/latched_data_in_4" BEL
+        "BIU_CORE/latched_data_in_3" BEL "BIU_CORE/latched_data_in_2" BEL
+        "BIU_CORE/latched_data_in_1" BEL "BIU_CORE/latched_data_in_0" BEL
+        "BIU_CORE/biu_return_data_int_7" BEL "BIU_CORE/biu_return_data_int_6"
+        BEL "BIU_CORE/biu_return_data_int_5" BEL
+        "BIU_CORE/biu_return_data_int_4" BEL "BIU_CORE/biu_return_data_int_3"
+        BEL "BIU_CORE/biu_return_data_int_2" BEL
+        "BIU_CORE/biu_return_data_int_1" BEL "BIU_CORE/biu_return_data_int_0"
+        BEL "BIU_CORE/addr_out_temp_19" BEL "BIU_CORE/addr_out_temp_18" BEL
+        "BIU_CORE/addr_out_temp_17" BEL "BIU_CORE/addr_out_temp_16" BEL
+        "BIU_CORE/addr_out_temp_15" BEL "BIU_CORE/addr_out_temp_14" BEL
+        "BIU_CORE/addr_out_temp_13" BEL "BIU_CORE/addr_out_temp_12" BEL
+        "BIU_CORE/addr_out_temp_11" BEL "BIU_CORE/addr_out_temp_10" BEL
+        "BIU_CORE/addr_out_temp_9" BEL "BIU_CORE/addr_out_temp_8" BEL
+        "BIU_CORE/addr_out_temp_7" BEL "BIU_CORE/addr_out_temp_6" BEL
+        "BIU_CORE/addr_out_temp_5" BEL "BIU_CORE/addr_out_temp_4" BEL
+        "BIU_CORE/addr_out_temp_3" BEL "BIU_CORE/addr_out_temp_2" BEL
+        "BIU_CORE/addr_out_temp_1" BEL "BIU_CORE/addr_out_temp_0" BEL
+        "BIU_CORE/AD_OUT_19" BEL "BIU_CORE/AD_OUT_18" BEL "BIU_CORE/AD_OUT_17"
+        BEL "BIU_CORE/AD_OUT_16" BEL "BIU_CORE/AD_OUT_15" BEL
+        "BIU_CORE/AD_OUT_14" BEL "BIU_CORE/AD_OUT_13" BEL "BIU_CORE/AD_OUT_12"
+        BEL "BIU_CORE/AD_OUT_11" BEL "BIU_CORE/AD_OUT_10" BEL
+        "BIU_CORE/AD_OUT_9" BEL "BIU_CORE/AD_OUT_8" BEL "BIU_CORE/AD_OUT_7"
+        BEL "BIU_CORE/AD_OUT_6" BEL "BIU_CORE/AD_OUT_5" BEL
+        "BIU_CORE/AD_OUT_4" BEL "BIU_CORE/AD_OUT_3" BEL "BIU_CORE/AD_OUT_2"
+        BEL "BIU_CORE/AD_OUT_1" BEL "BIU_CORE/AD_OUT_0" BEL
+        "BIU_CORE/SRAM_D_OUT_7" BEL "BIU_CORE/SRAM_D_OUT_6" BEL
+        "BIU_CORE/SRAM_D_OUT_5" BEL "BIU_CORE/SRAM_D_OUT_4" BEL
+        "BIU_CORE/SRAM_D_OUT_3" BEL "BIU_CORE/SRAM_D_OUT_2" BEL
+        "BIU_CORE/SRAM_D_OUT_1" BEL "BIU_CORE/SRAM_D_OUT_0" BEL
+        "BIU_CORE/mcl6_feature_1" BEL "BIU_CORE/mcl6_feature_0" BEL
+        "BIU_CORE/sram_select" BEL "BIU_CORE/SRAM_WE_n" BEL
+        "BIU_CORE/SRAM_OE_n" BEL "BIU_CORE/biu_state_7" BEL
+        "BIU_CORE/biu_state_6" BEL "BIU_CORE/biu_state_5" BEL
+        "BIU_CORE/biu_state_4" BEL "BIU_CORE/biu_state_3" BEL
+        "BIU_CORE/biu_state_2" BEL "BIU_CORE/biu_state_1" BEL
+        "BIU_CORE/biu_state_0" BEL "BIU_CORE/wr_n_int" BEL "BIU_CORE/rd_n_int"
+        BEL "BIU_CORE/den_int" BEL "BIU_CORE/inta_n_int" BEL "BIU_CORE/clk_d1"
+        BEL "BIU_CORE/dtr_int" BEL "BIU_CORE/SRAM_D_OE" BEL "BIU_CORE/AD_OE"
+        BEL "BIU_CORE/intr_d1" BEL "BIU_CORE/byte_num" BEL "BIU_CORE/ready_d1"
+        BEL "BIU_CORE/biu_done_int" BEL "BIU_CORE/eu_biu_req_d1" BEL
+        "BIU_CORE/biu_return_data_int_9" BEL "BIU_CORE/biu_return_data_int_10"
+        BEL "BIU_CORE/biu_return_data_int_8" BEL
+        "BIU_CORE/biu_return_data_int_12" BEL
+        "BIU_CORE/biu_return_data_int_13" BEL
+        "BIU_CORE/biu_return_data_int_11" BEL
+        "BIU_CORE/biu_return_data_int_15" BEL "BIU_CORE/pfq_write" BEL
+        "BIU_CORE/biu_return_data_int_14" BEL "BIU_CORE/nmi_d1" BEL
+        "BIU_CORE/eu_register_r3_d_15" BEL "BIU_CORE/eu_register_r3_d_14" BEL
+        "BIU_CORE/eu_register_r3_d_13" BEL "BIU_CORE/eu_register_r3_d_12" BEL
+        "BIU_CORE/eu_register_r3_d_11" BEL "BIU_CORE/eu_register_r3_d_10" BEL
+        "BIU_CORE/eu_register_r3_d_9" BEL "BIU_CORE/eu_register_r3_d_8" BEL
+        "BIU_CORE/eu_register_r3_d_7" BEL "BIU_CORE/eu_register_r3_d_6" BEL
+        "BIU_CORE/eu_register_r3_d_5" BEL "BIU_CORE/eu_register_r3_d_4" BEL
+        "BIU_CORE/eu_register_r3_d_3" BEL "BIU_CORE/eu_register_r3_d_2" BEL
+        "BIU_CORE/eu_register_r3_d_1" BEL "BIU_CORE/eu_register_r3_d_0" BEL
+        "BIU_CORE/biu_register_reg_15" BEL "BIU_CORE/biu_register_reg_14" BEL
+        "BIU_CORE/biu_register_reg_13" BEL "BIU_CORE/biu_register_reg_12" BEL
+        "BIU_CORE/biu_register_reg_11" BEL "BIU_CORE/biu_register_reg_10" BEL
+        "BIU_CORE/biu_register_reg_9" BEL "BIU_CORE/biu_register_reg_8" BEL
+        "BIU_CORE/biu_register_reg_7" BEL "BIU_CORE/biu_register_reg_6" BEL
+        "BIU_CORE/biu_register_reg_5" BEL "BIU_CORE/biu_register_reg_4" BEL
+        "BIU_CORE/biu_register_reg_3" BEL "BIU_CORE/biu_register_reg_2" BEL
+        "BIU_CORE/biu_register_reg_1" BEL "BIU_CORE/biu_register_reg_0" BEL
+        "BIU_CORE/biu_register_rm_15" BEL "BIU_CORE/biu_register_rm_14" BEL
+        "BIU_CORE/biu_register_rm_13" BEL "BIU_CORE/biu_register_rm_12" BEL
+        "BIU_CORE/biu_register_rm_11" BEL "BIU_CORE/biu_register_rm_10" BEL
+        "BIU_CORE/biu_register_rm_9" BEL "BIU_CORE/biu_register_rm_8" BEL
+        "BIU_CORE/biu_register_rm_7" BEL "BIU_CORE/biu_register_rm_6" BEL
+        "BIU_CORE/biu_register_rm_5" BEL "BIU_CORE/biu_register_rm_4" BEL
+        "BIU_CORE/biu_register_rm_3" BEL "BIU_CORE/biu_register_rm_2" BEL
+        "BIU_CORE/biu_register_rm_1" BEL "BIU_CORE/biu_register_rm_0" BEL
+        "BIU_CORE/biu_register_cs_15" BEL "BIU_CORE/biu_register_cs_14" BEL
+        "BIU_CORE/biu_register_cs_13" BEL "BIU_CORE/biu_register_cs_12" BEL
+        "BIU_CORE/biu_register_cs_11" BEL "BIU_CORE/biu_register_cs_10" BEL
+        "BIU_CORE/biu_register_cs_9" BEL "BIU_CORE/biu_register_cs_8" BEL
+        "BIU_CORE/biu_register_cs_7" BEL "BIU_CORE/biu_register_cs_6" BEL
+        "BIU_CORE/biu_register_cs_5" BEL "BIU_CORE/biu_register_cs_4" BEL
+        "BIU_CORE/biu_register_cs_3" BEL "BIU_CORE/biu_register_cs_2" BEL
+        "BIU_CORE/biu_register_cs_1" BEL "BIU_CORE/biu_register_cs_0" BEL
+        "BIU_CORE/biu_register_ds_15" BEL "BIU_CORE/biu_register_ds_14" BEL
+        "BIU_CORE/biu_register_ds_13" BEL "BIU_CORE/biu_register_ds_12" BEL
+        "BIU_CORE/biu_register_ds_11" BEL "BIU_CORE/biu_register_ds_10" BEL
+        "BIU_CORE/biu_register_ds_9" BEL "BIU_CORE/biu_register_ds_8" BEL
+        "BIU_CORE/biu_register_ds_7" BEL "BIU_CORE/biu_register_ds_6" BEL
+        "BIU_CORE/biu_register_ds_5" BEL "BIU_CORE/biu_register_ds_4" BEL
+        "BIU_CORE/biu_register_ds_3" BEL "BIU_CORE/biu_register_ds_2" BEL
+        "BIU_CORE/biu_register_ds_1" BEL "BIU_CORE/biu_register_ds_0" BEL
+        "BIU_CORE/biu_register_ss_15" BEL "BIU_CORE/biu_register_ss_14" BEL
+        "BIU_CORE/biu_register_ss_13" BEL "BIU_CORE/biu_register_ss_12" BEL
+        "BIU_CORE/biu_register_ss_11" BEL "BIU_CORE/biu_register_ss_10" BEL
+        "BIU_CORE/biu_register_ss_9" BEL "BIU_CORE/biu_register_ss_8" BEL
+        "BIU_CORE/biu_register_ss_7" BEL "BIU_CORE/biu_register_ss_6" BEL
+        "BIU_CORE/biu_register_ss_5" BEL "BIU_CORE/biu_register_ss_4" BEL
+        "BIU_CORE/biu_register_ss_3" BEL "BIU_CORE/biu_register_ss_2" BEL
+        "BIU_CORE/biu_register_ss_1" BEL "BIU_CORE/biu_register_ss_0" BEL
+        "BIU_CORE/biu_register_es_15" BEL "BIU_CORE/biu_register_es_14" BEL
+        "BIU_CORE/biu_register_es_13" BEL "BIU_CORE/biu_register_es_12" BEL
+        "BIU_CORE/biu_register_es_11" BEL "BIU_CORE/biu_register_es_10" BEL
+        "BIU_CORE/biu_register_es_9" BEL "BIU_CORE/biu_register_es_8" BEL
+        "BIU_CORE/biu_register_es_7" BEL "BIU_CORE/biu_register_es_6" BEL
+        "BIU_CORE/biu_register_es_5" BEL "BIU_CORE/biu_register_es_4" BEL
+        "BIU_CORE/biu_register_es_3" BEL "BIU_CORE/biu_register_es_2" BEL
+        "BIU_CORE/biu_register_es_1" BEL "BIU_CORE/biu_register_es_0" BEL
+        "BIU_CORE/ad_in_int_7" BEL "BIU_CORE/ad_in_int_6" BEL
+        "BIU_CORE/ad_in_int_5" BEL "BIU_CORE/ad_in_int_4" BEL
+        "BIU_CORE/ad_in_int_3" BEL "BIU_CORE/ad_in_int_2" BEL
+        "BIU_CORE/ad_in_int_1" BEL "BIU_CORE/ad_in_int_0" BEL
+        "EU_CORE/eu_register_r0_15" BEL "EU_CORE/eu_register_r0_14" BEL
+        "EU_CORE/eu_register_r0_13" BEL "EU_CORE/eu_register_r0_12" BEL
+        "EU_CORE/eu_register_r0_11" BEL "EU_CORE/eu_register_r0_10" BEL
+        "EU_CORE/eu_register_r0_9" BEL "EU_CORE/eu_register_r0_8" BEL
+        "EU_CORE/eu_register_r0_7" BEL "EU_CORE/eu_register_r0_6" BEL
+        "EU_CORE/eu_register_r0_5" BEL "EU_CORE/eu_register_r0_4" BEL
+        "EU_CORE/eu_register_r0_3" BEL "EU_CORE/eu_register_r0_2" BEL
+        "EU_CORE/eu_register_r0_1" BEL "EU_CORE/eu_register_r0_0" BEL
+        "EU_CORE/eu_alu_last_result_15" BEL "EU_CORE/eu_alu_last_result_14"
+        BEL "EU_CORE/eu_alu_last_result_13" BEL
+        "EU_CORE/eu_alu_last_result_12" BEL "EU_CORE/eu_alu_last_result_11"
+        BEL "EU_CORE/eu_alu_last_result_10" BEL "EU_CORE/eu_alu_last_result_9"
+        BEL "EU_CORE/eu_alu_last_result_8" BEL "EU_CORE/eu_alu_last_result_7"
+        BEL "EU_CORE/eu_alu_last_result_6" BEL "EU_CORE/eu_alu_last_result_5"
+        BEL "EU_CORE/eu_alu_last_result_4" BEL "EU_CORE/eu_alu_last_result_3"
+        BEL "EU_CORE/eu_alu_last_result_2" BEL "EU_CORE/eu_alu_last_result_1"
+        BEL "EU_CORE/eu_alu_last_result_0" BEL "EU_CORE/eu_rom_address_12" BEL
+        "EU_CORE/eu_rom_address_11" BEL "EU_CORE/eu_rom_address_10" BEL
+        "EU_CORE/eu_rom_address_9" BEL "EU_CORE/eu_rom_address_8" BEL
+        "EU_CORE/eu_rom_address_7" BEL "EU_CORE/eu_rom_address_6" BEL
+        "EU_CORE/eu_rom_address_5" BEL "EU_CORE/eu_rom_address_4" BEL
+        "EU_CORE/eu_rom_address_3" BEL "EU_CORE/eu_rom_address_2" BEL
+        "EU_CORE/eu_rom_address_1" BEL "EU_CORE/eu_rom_address_0" BEL
+        "EU_CORE/eu_calling_address_51" BEL "EU_CORE/eu_calling_address_50"
+        BEL "EU_CORE/eu_calling_address_49" BEL
+        "EU_CORE/eu_calling_address_48" BEL "EU_CORE/eu_calling_address_47"
+        BEL "EU_CORE/eu_calling_address_46" BEL
+        "EU_CORE/eu_calling_address_45" BEL "EU_CORE/eu_calling_address_44"
+        BEL "EU_CORE/eu_calling_address_43" BEL
+        "EU_CORE/eu_calling_address_42" BEL "EU_CORE/eu_calling_address_41"
+        BEL "EU_CORE/eu_calling_address_40" BEL
+        "EU_CORE/eu_calling_address_39" BEL "EU_CORE/eu_calling_address_38"
+        BEL "EU_CORE/eu_calling_address_37" BEL
+        "EU_CORE/eu_calling_address_36" BEL "EU_CORE/eu_calling_address_35"
+        BEL "EU_CORE/eu_calling_address_34" BEL
+        "EU_CORE/eu_calling_address_33" BEL "EU_CORE/eu_calling_address_32"
+        BEL "EU_CORE/eu_calling_address_31" BEL
+        "EU_CORE/eu_calling_address_30" BEL "EU_CORE/eu_calling_address_29"
+        BEL "EU_CORE/eu_calling_address_28" BEL
+        "EU_CORE/eu_calling_address_27" BEL "EU_CORE/eu_calling_address_26"
+        BEL "EU_CORE/eu_calling_address_25" BEL
+        "EU_CORE/eu_calling_address_24" BEL "EU_CORE/eu_calling_address_23"
+        BEL "EU_CORE/eu_calling_address_22" BEL
+        "EU_CORE/eu_calling_address_21" BEL "EU_CORE/eu_calling_address_20"
+        BEL "EU_CORE/eu_calling_address_19" BEL
+        "EU_CORE/eu_calling_address_18" BEL "EU_CORE/eu_calling_address_17"
+        BEL "EU_CORE/eu_calling_address_16" BEL
+        "EU_CORE/eu_calling_address_15" BEL "EU_CORE/eu_calling_address_14"
+        BEL "EU_CORE/eu_calling_address_13" BEL
+        "EU_CORE/eu_calling_address_12" BEL "EU_CORE/eu_calling_address_11"
+        BEL "EU_CORE/eu_calling_address_10" BEL "EU_CORE/eu_calling_address_9"
+        BEL "EU_CORE/eu_calling_address_8" BEL "EU_CORE/eu_calling_address_7"
+        BEL "EU_CORE/eu_calling_address_6" BEL "EU_CORE/eu_calling_address_5"
+        BEL "EU_CORE/eu_calling_address_4" BEL "EU_CORE/eu_calling_address_3"
+        BEL "EU_CORE/eu_calling_address_2" BEL "EU_CORE/eu_calling_address_1"
+        BEL "EU_CORE/eu_calling_address_0" BEL "EU_CORE/eu_add_overflow8" BEL
+        "EU_CORE/eu_add_overflow16" BEL "EU_CORE/eu_flag_t_d" BEL
+        "EU_CORE/eu_biu_dataout_15" BEL "EU_CORE/eu_biu_dataout_14" BEL
+        "EU_CORE/eu_biu_dataout_13" BEL "EU_CORE/eu_biu_dataout_12" BEL
+        "EU_CORE/eu_biu_dataout_11" BEL "EU_CORE/eu_biu_dataout_10" BEL
+        "EU_CORE/eu_biu_dataout_9" BEL "EU_CORE/eu_biu_dataout_8" BEL
+        "EU_CORE/eu_biu_dataout_7" BEL "EU_CORE/eu_biu_dataout_6" BEL
+        "EU_CORE/eu_biu_dataout_5" BEL "EU_CORE/eu_biu_dataout_4" BEL
+        "EU_CORE/eu_biu_dataout_3" BEL "EU_CORE/eu_biu_dataout_2" BEL
+        "EU_CORE/eu_biu_dataout_1" BEL "EU_CORE/eu_biu_dataout_0" BEL
+        "EU_CORE/eu_register_r3_15" BEL "EU_CORE/eu_register_r3_14" BEL
+        "EU_CORE/eu_register_r3_13" BEL "EU_CORE/eu_register_r3_12" BEL
+        "EU_CORE/eu_register_r3_11" BEL "EU_CORE/eu_register_r3_10" BEL
+        "EU_CORE/eu_register_r3_9" BEL "EU_CORE/eu_register_r3_8" BEL
+        "EU_CORE/eu_register_r3_7" BEL "EU_CORE/eu_register_r3_6" BEL
+        "EU_CORE/eu_register_r3_5" BEL "EU_CORE/eu_register_r3_4" BEL
+        "EU_CORE/eu_register_r3_3" BEL "EU_CORE/eu_register_r3_2" BEL
+        "EU_CORE/eu_register_r3_1" BEL "EU_CORE/eu_register_r3_0" BEL
+        "EU_CORE/eu_register_r2_15" BEL "EU_CORE/eu_register_r2_14" BEL
+        "EU_CORE/eu_register_r2_13" BEL "EU_CORE/eu_register_r2_12" BEL
+        "EU_CORE/eu_register_r2_11" BEL "EU_CORE/eu_register_r2_10" BEL
+        "EU_CORE/eu_register_r2_9" BEL "EU_CORE/eu_register_r2_8" BEL
+        "EU_CORE/eu_register_r2_7" BEL "EU_CORE/eu_register_r2_6" BEL
+        "EU_CORE/eu_register_r2_5" BEL "EU_CORE/eu_register_r2_4" BEL
+        "EU_CORE/eu_register_r2_3" BEL "EU_CORE/eu_register_r2_2" BEL
+        "EU_CORE/eu_register_r2_1" BEL "EU_CORE/eu_register_r2_0" BEL
+        "EU_CORE/eu_biu_command_15" BEL "EU_CORE/eu_biu_command_14" BEL
+        "EU_CORE/eu_biu_command_13" BEL "EU_CORE/eu_biu_command_12" BEL
+        "EU_CORE/eu_biu_command_11" BEL "EU_CORE/eu_biu_command_10" BEL
+        "EU_CORE/eu_biu_command_9" BEL "EU_CORE/eu_biu_command_8" BEL
+        "EU_CORE/eu_biu_command_7" BEL "EU_CORE/eu_biu_command_6" BEL
+        "EU_CORE/eu_biu_command_5" BEL "EU_CORE/eu_biu_command_4" BEL
+        "EU_CORE/eu_biu_command_3" BEL "EU_CORE/eu_biu_command_2" BEL
+        "EU_CORE/eu_biu_command_1" BEL "EU_CORE/eu_biu_command_0" BEL
+        "EU_CORE/eu_flags_15" BEL "EU_CORE/eu_flags_14" BEL
+        "EU_CORE/eu_flags_13" BEL "EU_CORE/eu_flags_12" BEL
+        "EU_CORE/eu_flags_11" BEL "EU_CORE/eu_flags_10" BEL
+        "EU_CORE/eu_flags_9" BEL "EU_CORE/eu_flags_8" BEL "EU_CORE/eu_flags_7"
+        BEL "EU_CORE/eu_flags_6" BEL "EU_CORE/eu_flags_5" BEL
+        "EU_CORE/eu_flags_4" BEL "EU_CORE/eu_flags_3" BEL "EU_CORE/eu_flags_2"
+        BEL "EU_CORE/eu_flags_1" BEL "EU_CORE/eu_flags_0" BEL
+        "EU_CORE/eu_register_r1_15" BEL "EU_CORE/eu_register_r1_14" BEL
+        "EU_CORE/eu_register_r1_13" BEL "EU_CORE/eu_register_r1_12" BEL
+        "EU_CORE/eu_register_r1_11" BEL "EU_CORE/eu_register_r1_10" BEL
+        "EU_CORE/eu_register_r1_9" BEL "EU_CORE/eu_register_r1_8" BEL
+        "EU_CORE/eu_register_r1_7" BEL "EU_CORE/eu_register_r1_6" BEL
+        "EU_CORE/eu_register_r1_5" BEL "EU_CORE/eu_register_r1_4" BEL
+        "EU_CORE/eu_register_r1_3" BEL "EU_CORE/eu_register_r1_2" BEL
+        "EU_CORE/eu_register_r1_1" BEL "EU_CORE/eu_register_r1_0" BEL
+        "EU_CORE/eu_register_si_15" BEL "EU_CORE/eu_register_si_14" BEL
+        "EU_CORE/eu_register_si_13" BEL "EU_CORE/eu_register_si_12" BEL
+        "EU_CORE/eu_register_si_11" BEL "EU_CORE/eu_register_si_10" BEL
+        "EU_CORE/eu_register_si_9" BEL "EU_CORE/eu_register_si_8" BEL
+        "EU_CORE/eu_register_si_7" BEL "EU_CORE/eu_register_si_6" BEL
+        "EU_CORE/eu_register_si_5" BEL "EU_CORE/eu_register_si_4" BEL
+        "EU_CORE/eu_register_si_3" BEL "EU_CORE/eu_register_si_2" BEL
+        "EU_CORE/eu_register_si_1" BEL "EU_CORE/eu_register_si_0" BEL
+        "EU_CORE/eu_register_bp_15" BEL "EU_CORE/eu_register_bp_14" BEL
+        "EU_CORE/eu_register_bp_13" BEL "EU_CORE/eu_register_bp_12" BEL
+        "EU_CORE/eu_register_bp_11" BEL "EU_CORE/eu_register_bp_10" BEL
+        "EU_CORE/eu_register_bp_9" BEL "EU_CORE/eu_register_bp_8" BEL
+        "EU_CORE/eu_register_bp_7" BEL "EU_CORE/eu_register_bp_6" BEL
+        "EU_CORE/eu_register_bp_5" BEL "EU_CORE/eu_register_bp_4" BEL
+        "EU_CORE/eu_register_bp_3" BEL "EU_CORE/eu_register_bp_2" BEL
+        "EU_CORE/eu_register_bp_1" BEL "EU_CORE/eu_register_bp_0" BEL
+        "EU_CORE/eu_register_di_15" BEL "EU_CORE/eu_register_di_14" BEL
+        "EU_CORE/eu_register_di_13" BEL "EU_CORE/eu_register_di_12" BEL
+        "EU_CORE/eu_register_di_11" BEL "EU_CORE/eu_register_di_10" BEL
+        "EU_CORE/eu_register_di_9" BEL "EU_CORE/eu_register_di_8" BEL
+        "EU_CORE/eu_register_di_7" BEL "EU_CORE/eu_register_di_6" BEL
+        "EU_CORE/eu_register_di_5" BEL "EU_CORE/eu_register_di_4" BEL
+        "EU_CORE/eu_register_di_3" BEL "EU_CORE/eu_register_di_2" BEL
+        "EU_CORE/eu_register_di_1" BEL "EU_CORE/eu_register_di_0" BEL
+        "EU_CORE/eu_register_sp_15" BEL "EU_CORE/eu_register_sp_14" BEL
+        "EU_CORE/eu_register_sp_13" BEL "EU_CORE/eu_register_sp_12" BEL
+        "EU_CORE/eu_register_sp_11" BEL "EU_CORE/eu_register_sp_10" BEL
+        "EU_CORE/eu_register_sp_9" BEL "EU_CORE/eu_register_sp_8" BEL
+        "EU_CORE/eu_register_sp_7" BEL "EU_CORE/eu_register_sp_6" BEL
+        "EU_CORE/eu_register_sp_5" BEL "EU_CORE/eu_register_sp_4" BEL
+        "EU_CORE/eu_register_sp_3" BEL "EU_CORE/eu_register_sp_2" BEL
+        "EU_CORE/eu_register_sp_1" BEL "EU_CORE/eu_register_sp_0" BEL
+        "EU_CORE/eu_register_dx_15" BEL "EU_CORE/eu_register_dx_14" BEL
+        "EU_CORE/eu_register_dx_13" BEL "EU_CORE/eu_register_dx_12" BEL
+        "EU_CORE/eu_register_dx_11" BEL "EU_CORE/eu_register_dx_10" BEL
+        "EU_CORE/eu_register_dx_9" BEL "EU_CORE/eu_register_dx_8" BEL
+        "EU_CORE/eu_register_dx_7" BEL "EU_CORE/eu_register_dx_6" BEL
+        "EU_CORE/eu_register_dx_5" BEL "EU_CORE/eu_register_dx_4" BEL
+        "EU_CORE/eu_register_dx_3" BEL "EU_CORE/eu_register_dx_2" BEL
+        "EU_CORE/eu_register_dx_1" BEL "EU_CORE/eu_register_dx_0" BEL
+        "EU_CORE/eu_register_cx_15" BEL "EU_CORE/eu_register_cx_14" BEL
+        "EU_CORE/eu_register_cx_13" BEL "EU_CORE/eu_register_cx_12" BEL
+        "EU_CORE/eu_register_cx_11" BEL "EU_CORE/eu_register_cx_10" BEL
+        "EU_CORE/eu_register_cx_9" BEL "EU_CORE/eu_register_cx_8" BEL
+        "EU_CORE/eu_register_cx_7" BEL "EU_CORE/eu_register_cx_6" BEL
+        "EU_CORE/eu_register_cx_5" BEL "EU_CORE/eu_register_cx_4" BEL
+        "EU_CORE/eu_register_cx_3" BEL "EU_CORE/eu_register_cx_2" BEL
+        "EU_CORE/eu_register_cx_1" BEL "EU_CORE/eu_register_cx_0" BEL
+        "EU_CORE/eu_register_bx_15" BEL "EU_CORE/eu_register_bx_14" BEL
+        "EU_CORE/eu_register_bx_13" BEL "EU_CORE/eu_register_bx_12" BEL
+        "EU_CORE/eu_register_bx_11" BEL "EU_CORE/eu_register_bx_10" BEL
+        "EU_CORE/eu_register_bx_9" BEL "EU_CORE/eu_register_bx_8" BEL
+        "EU_CORE/eu_register_bx_7" BEL "EU_CORE/eu_register_bx_6" BEL
+        "EU_CORE/eu_register_bx_5" BEL "EU_CORE/eu_register_bx_4" BEL
+        "EU_CORE/eu_register_bx_3" BEL "EU_CORE/eu_register_bx_2" BEL
+        "EU_CORE/eu_register_bx_1" BEL "EU_CORE/eu_register_bx_0" BEL
+        "EU_CORE/eu_register_ax_15" BEL "EU_CORE/eu_register_ax_14" BEL
+        "EU_CORE/eu_register_ax_13" BEL "EU_CORE/eu_register_ax_12" BEL
+        "EU_CORE/eu_register_ax_11" BEL "EU_CORE/eu_register_ax_10" BEL
+        "EU_CORE/eu_register_ax_9" BEL "EU_CORE/eu_register_ax_8" BEL
+        "EU_CORE/eu_register_ax_7" BEL "EU_CORE/eu_register_ax_6" BEL
+        "EU_CORE/eu_register_ax_5" BEL "EU_CORE/eu_register_ax_4" BEL
+        "EU_CORE/eu_register_ax_3" BEL "EU_CORE/eu_register_ax_2" BEL
+        "EU_CORE/eu_register_ax_1" BEL "EU_CORE/eu_register_ax_0" BEL
+        "EU_CORE/eu_add_aux_carry" BEL "EU_CORE/eu_add_carry8" BEL
+        "EU_CORE/eu_add_carry" BEL "EU_CORE/biu_done_d1" BEL
+        "EU_CORE/eu_stall_pipeline" BEL "t_reset_d4" BEL
+        "BIU_CORE/eu_biu_req_caught" BEL "BIU_CORE/nmi_caught" BEL
+        "EU_CORE/eu_tr_latched" BEL "EU_CORE/biu_done_caught" BEL
+        "BIU_CORE/BIU_INTR" BEL "BIU_CORE/ale_int" BEL "BIU_CORE/iom_int" BEL
+        "EU_CORE/intr_enable_delayed" BEL "BIU_CORE/nmi_d2" BEL "led_go_left"
+        BEL "BIU_CORE/word_cycle" BEL "Mshreg_t_biu_ad_oe_d2" BEL
+        "t_biu_ad_oe_d2" BEL "Mshreg_t_reset_d2" BEL "t_reset_d2" BEL
+        "BIU_CORE/Mshreg_biu_return_data_int_d2_15" BEL
+        "BIU_CORE/biu_return_data_int_d2_15" BEL
+        "BIU_CORE/Mshreg_biu_return_data_int_d2_14" BEL
+        "BIU_CORE/biu_return_data_int_d2_14" BEL
+        "BIU_CORE/Mshreg_biu_return_data_int_d2_13" BEL
+        "BIU_CORE/biu_return_data_int_d2_13" BEL
+        "BIU_CORE/Mshreg_biu_return_data_int_d2_12" BEL
+        "BIU_CORE/biu_return_data_int_d2_12" BEL
+        "BIU_CORE/Mshreg_biu_return_data_int_d2_11" BEL
+        "BIU_CORE/biu_return_data_int_d2_11" BEL
+        "BIU_CORE/Mshreg_biu_return_data_int_d2_10" BEL
+        "BIU_CORE/biu_return_data_int_d2_10" BEL
+        "BIU_CORE/Mshreg_biu_return_data_int_d2_9" BEL
+        "BIU_CORE/biu_return_data_int_d2_9" BEL
+        "BIU_CORE/Mshreg_biu_return_data_int_d2_8" BEL
+        "BIU_CORE/biu_return_data_int_d2_8" BEL
+        "BIU_CORE/Mshreg_biu_return_data_int_d2_7" BEL
+        "BIU_CORE/biu_return_data_int_d2_7" BEL
+        "BIU_CORE/Mshreg_biu_return_data_int_d2_6" BEL
+        "BIU_CORE/biu_return_data_int_d2_6" BEL
+        "BIU_CORE/Mshreg_biu_return_data_int_d2_3" BEL
+        "BIU_CORE/biu_return_data_int_d2_3" BEL
+        "BIU_CORE/Mshreg_biu_return_data_int_d2_5" BEL
+        "BIU_CORE/biu_return_data_int_d2_5" BEL
+        "BIU_CORE/Mshreg_biu_return_data_int_d2_4" BEL
+        "BIU_CORE/biu_return_data_int_d2_4" BEL
+        "BIU_CORE/Mshreg_biu_return_data_int_d2_2" BEL
+        "BIU_CORE/biu_return_data_int_d2_2" BEL
+        "BIU_CORE/Mshreg_biu_return_data_int_d2_1" BEL
+        "BIU_CORE/biu_return_data_int_d2_1" BEL
+        "BIU_CORE/Mshreg_biu_return_data_int_d2_0" BEL
+        "BIU_CORE/biu_return_data_int_d2_0" BEL
+        "BIU_CORE/Mshreg_biu_register_rm_d2_15" BEL
+        "BIU_CORE/biu_register_rm_d2_15" BEL
+        "BIU_CORE/Mshreg_biu_register_rm_d2_12" BEL
+        "BIU_CORE/biu_register_rm_d2_12" BEL
+        "BIU_CORE/Mshreg_biu_register_rm_d2_14" BEL
+        "BIU_CORE/biu_register_rm_d2_14" BEL
+        "BIU_CORE/Mshreg_biu_register_rm_d2_13" BEL
+        "BIU_CORE/biu_register_rm_d2_13" BEL
+        "BIU_CORE/Mshreg_biu_register_rm_d2_11" BEL
+        "BIU_CORE/biu_register_rm_d2_11" BEL
+        "BIU_CORE/Mshreg_biu_register_rm_d2_10" BEL
+        "BIU_CORE/biu_register_rm_d2_10" BEL
+        "BIU_CORE/Mshreg_biu_register_rm_d2_9" BEL
+        "BIU_CORE/biu_register_rm_d2_9" BEL
+        "BIU_CORE/Mshreg_biu_register_rm_d2_8" BEL
+        "BIU_CORE/biu_register_rm_d2_8" BEL
+        "BIU_CORE/Mshreg_biu_register_rm_d2_5" BEL
+        "BIU_CORE/biu_register_rm_d2_5" BEL
+        "BIU_CORE/Mshreg_biu_register_rm_d2_7" BEL
+        "BIU_CORE/biu_register_rm_d2_7" BEL
+        "BIU_CORE/Mshreg_biu_register_rm_d2_6" BEL
+        "BIU_CORE/biu_register_rm_d2_6" BEL
+        "BIU_CORE/Mshreg_biu_register_rm_d2_4" BEL
+        "BIU_CORE/biu_register_rm_d2_4" BEL
+        "BIU_CORE/Mshreg_biu_register_rm_d2_3" BEL
+        "BIU_CORE/biu_register_rm_d2_3" BEL
+        "BIU_CORE/Mshreg_biu_register_rm_d2_2" BEL
+        "BIU_CORE/biu_register_rm_d2_2" BEL
+        "BIU_CORE/Mshreg_biu_register_rm_d2_1" BEL
+        "BIU_CORE/biu_register_rm_d2_1" BEL
+        "BIU_CORE/Mshreg_biu_register_ds_d2_14" BEL
+        "BIU_CORE/biu_register_ds_d2_14" BEL
+        "BIU_CORE/Mshreg_biu_register_rm_d2_0" BEL
+        "BIU_CORE/biu_register_rm_d2_0" BEL
+        "BIU_CORE/Mshreg_biu_register_ds_d2_15" BEL
+        "BIU_CORE/biu_register_ds_d2_15" BEL
+        "BIU_CORE/Mshreg_biu_register_ds_d2_13" BEL
+        "BIU_CORE/biu_register_ds_d2_13" BEL
+        "BIU_CORE/Mshreg_biu_register_ds_d2_12" BEL
+        "BIU_CORE/biu_register_ds_d2_12" BEL
+        "BIU_CORE/Mshreg_biu_register_ds_d2_11" BEL
+        "BIU_CORE/biu_register_ds_d2_11" BEL
+        "BIU_CORE/Mshreg_biu_register_ds_d2_10" BEL
+        "BIU_CORE/biu_register_ds_d2_10" BEL
+        "BIU_CORE/Mshreg_biu_register_ds_d2_7" BEL
+        "BIU_CORE/biu_register_ds_d2_7" BEL
+        "BIU_CORE/Mshreg_biu_register_ds_d2_9" BEL
+        "BIU_CORE/biu_register_ds_d2_9" BEL
+        "BIU_CORE/Mshreg_biu_register_ds_d2_8" BEL
+        "BIU_CORE/biu_register_ds_d2_8" BEL
+        "BIU_CORE/Mshreg_biu_register_ds_d2_6" BEL
+        "BIU_CORE/biu_register_ds_d2_6" BEL
+        "BIU_CORE/Mshreg_biu_register_ds_d2_5" BEL
+        "BIU_CORE/biu_register_ds_d2_5" BEL
+        "BIU_CORE/Mshreg_biu_register_ds_d2_4" BEL
+        "BIU_CORE/biu_register_ds_d2_4" BEL
+        "BIU_CORE/Mshreg_biu_register_ds_d2_3" BEL
+        "BIU_CORE/biu_register_ds_d2_3" BEL
+        "BIU_CORE/Mshreg_biu_register_ds_d2_0" BEL
+        "BIU_CORE/biu_register_ds_d2_0" BEL
+        "BIU_CORE/Mshreg_biu_register_ds_d2_2" BEL
+        "BIU_CORE/biu_register_ds_d2_2" BEL
+        "BIU_CORE/Mshreg_biu_register_ds_d2_1" BEL
+        "BIU_CORE/biu_register_ds_d2_1" BEL
+        "BIU_CORE/Mshreg_biu_register_reg_d2_15" BEL
+        "BIU_CORE/biu_register_reg_d2_15" BEL
+        "BIU_CORE/Mshreg_biu_register_reg_d2_14" BEL
+        "BIU_CORE/biu_register_reg_d2_14" BEL
+        "BIU_CORE/Mshreg_biu_register_reg_d2_13" BEL
+        "BIU_CORE/biu_register_reg_d2_13" BEL
+        "BIU_CORE/Mshreg_biu_register_reg_d2_12" BEL
+        "BIU_CORE/biu_register_reg_d2_12" BEL
+        "BIU_CORE/Mshreg_biu_register_reg_d2_9" BEL
+        "BIU_CORE/biu_register_reg_d2_9" BEL
+        "BIU_CORE/Mshreg_biu_register_reg_d2_11" BEL
+        "BIU_CORE/biu_register_reg_d2_11" BEL
+        "BIU_CORE/Mshreg_biu_register_reg_d2_10" BEL
+        "BIU_CORE/biu_register_reg_d2_10" BEL
+        "BIU_CORE/Mshreg_biu_register_reg_d2_8" BEL
+        "BIU_CORE/biu_register_reg_d2_8" BEL
+        "BIU_CORE/Mshreg_biu_register_reg_d2_7" BEL
+        "BIU_CORE/biu_register_reg_d2_7" BEL
+        "BIU_CORE/Mshreg_biu_register_reg_d2_6" BEL
+        "BIU_CORE/biu_register_reg_d2_6" BEL
+        "BIU_CORE/Mshreg_biu_register_reg_d2_5" BEL
+        "BIU_CORE/biu_register_reg_d2_5" BEL
+        "BIU_CORE/Mshreg_biu_register_reg_d2_4" BEL
+        "BIU_CORE/biu_register_reg_d2_4" BEL
+        "BIU_CORE/Mshreg_biu_register_reg_d2_3" BEL
+        "BIU_CORE/biu_register_reg_d2_3" BEL
+        "BIU_CORE/Mshreg_biu_register_reg_d2_2" BEL
+        "BIU_CORE/biu_register_reg_d2_2" BEL
+        "BIU_CORE/Mshreg_biu_register_reg_d2_1" BEL
+        "BIU_CORE/biu_register_reg_d2_1" BEL
+        "BIU_CORE/Mshreg_biu_register_reg_d2_0" BEL
+        "BIU_CORE/biu_register_reg_d2_0" BEL
+        "BIU_CORE/Mshreg_biu_register_ss_d2_15" BEL
+        "BIU_CORE/biu_register_ss_d2_15" BEL
+        "BIU_CORE/Mshreg_biu_register_ss_d2_14" BEL
+        "BIU_CORE/biu_register_ss_d2_14" BEL
+        "BIU_CORE/Mshreg_biu_register_ss_d2_13" BEL
+        "BIU_CORE/biu_register_ss_d2_13" BEL
+        "BIU_CORE/Mshreg_biu_register_ss_d2_10" BEL
+        "BIU_CORE/biu_register_ss_d2_10" BEL
+        "BIU_CORE/Mshreg_biu_register_ss_d2_12" BEL
+        "BIU_CORE/biu_register_ss_d2_12" BEL
+        "BIU_CORE/Mshreg_biu_register_ss_d2_11" BEL
+        "BIU_CORE/biu_register_ss_d2_11" BEL
+        "BIU_CORE/Mshreg_biu_register_ss_d2_9" BEL
+        "BIU_CORE/biu_register_ss_d2_9" BEL
+        "BIU_CORE/Mshreg_biu_register_ss_d2_8" BEL
+        "BIU_CORE/biu_register_ss_d2_8" BEL
+        "BIU_CORE/Mshreg_biu_register_ss_d2_7" BEL
+        "BIU_CORE/biu_register_ss_d2_7" BEL
+        "BIU_CORE/Mshreg_biu_register_ss_d2_6" BEL
+        "BIU_CORE/biu_register_ss_d2_6" BEL
+        "BIU_CORE/Mshreg_biu_register_ss_d2_3" BEL
+        "BIU_CORE/biu_register_ss_d2_3" BEL
+        "BIU_CORE/Mshreg_biu_register_ss_d2_5" BEL
+        "BIU_CORE/biu_register_ss_d2_5" BEL
+        "BIU_CORE/Mshreg_biu_register_ss_d2_4" BEL
+        "BIU_CORE/biu_register_ss_d2_4" BEL
+        "BIU_CORE/Mshreg_biu_register_ss_d2_2" BEL
+        "BIU_CORE/biu_register_ss_d2_2" BEL
+        "BIU_CORE/Mshreg_biu_register_ss_d2_1" BEL
+        "BIU_CORE/biu_register_ss_d2_1" BEL
+        "BIU_CORE/Mshreg_biu_register_ss_d2_0" BEL
+        "BIU_CORE/biu_register_ss_d2_0" BEL
+        "BIU_CORE/Mshreg_biu_register_es_d2_15" BEL
+        "BIU_CORE/biu_register_es_d2_15" BEL
+        "BIU_CORE/Mshreg_biu_register_es_d2_12" BEL
+        "BIU_CORE/biu_register_es_d2_12" BEL
+        "BIU_CORE/Mshreg_biu_register_es_d2_14" BEL
+        "BIU_CORE/biu_register_es_d2_14" BEL
+        "BIU_CORE/Mshreg_biu_register_es_d2_13" BEL
+        "BIU_CORE/biu_register_es_d2_13" BEL
+        "BIU_CORE/Mshreg_biu_register_es_d2_11" BEL
+        "BIU_CORE/biu_register_es_d2_11" BEL
+        "BIU_CORE/Mshreg_biu_register_es_d2_10" BEL
+        "BIU_CORE/biu_register_es_d2_10" BEL
+        "BIU_CORE/Mshreg_biu_register_es_d2_9" BEL
+        "BIU_CORE/biu_register_es_d2_9" BEL
+        "BIU_CORE/Mshreg_biu_register_es_d2_8" BEL
+        "BIU_CORE/biu_register_es_d2_8" BEL
+        "BIU_CORE/Mshreg_biu_register_es_d2_5" BEL
+        "BIU_CORE/biu_register_es_d2_5" BEL
+        "BIU_CORE/Mshreg_biu_register_es_d2_7" BEL
+        "BIU_CORE/biu_register_es_d2_7" BEL
+        "BIU_CORE/Mshreg_biu_register_es_d2_6" BEL
+        "BIU_CORE/biu_register_es_d2_6" BEL
+        "BIU_CORE/Mshreg_biu_register_es_d2_4" BEL
+        "BIU_CORE/biu_register_es_d2_4" BEL
+        "BIU_CORE/Mshreg_biu_register_es_d2_3" BEL
+        "BIU_CORE/biu_register_es_d2_3" BEL
+        "BIU_CORE/Mshreg_biu_register_es_d2_2" BEL
+        "BIU_CORE/biu_register_es_d2_2" BEL
+        "BIU_CORE/Mshreg_biu_register_es_d2_1" BEL
+        "BIU_CORE/biu_register_es_d2_1" BEL
+        "BIU_CORE/Mshreg_biu_register_cs_d2_14" BEL
+        "BIU_CORE/biu_register_cs_d2_14" BEL
+        "BIU_CORE/Mshreg_biu_register_es_d2_0" BEL
+        "BIU_CORE/biu_register_es_d2_0" BEL
+        "BIU_CORE/Mshreg_biu_register_cs_d2_15" BEL
+        "BIU_CORE/biu_register_cs_d2_15" BEL
+        "BIU_CORE/Mshreg_biu_register_cs_d2_13" BEL
+        "BIU_CORE/biu_register_cs_d2_13" BEL
+        "BIU_CORE/Mshreg_biu_register_cs_d2_12" BEL
+        "BIU_CORE/biu_register_cs_d2_12" BEL
+        "BIU_CORE/Mshreg_biu_register_cs_d2_11" BEL
+        "BIU_CORE/biu_register_cs_d2_11" BEL
+        "BIU_CORE/Mshreg_biu_register_cs_d2_10" BEL
+        "BIU_CORE/biu_register_cs_d2_10" BEL
+        "BIU_CORE/Mshreg_biu_register_cs_d2_7" BEL
+        "BIU_CORE/biu_register_cs_d2_7" BEL
+        "BIU_CORE/Mshreg_biu_register_cs_d2_9" BEL
+        "BIU_CORE/biu_register_cs_d2_9" BEL
+        "BIU_CORE/Mshreg_biu_register_cs_d2_8" BEL
+        "BIU_CORE/biu_register_cs_d2_8" BEL
+        "BIU_CORE/Mshreg_biu_register_cs_d2_6" BEL
+        "BIU_CORE/biu_register_cs_d2_6" BEL
+        "BIU_CORE/Mshreg_biu_register_cs_d2_5" BEL
+        "BIU_CORE/biu_register_cs_d2_5" BEL
+        "BIU_CORE/Mshreg_biu_register_cs_d2_4" BEL
+        "BIU_CORE/biu_register_cs_d2_4" BEL
+        "BIU_CORE/Mshreg_biu_register_cs_d2_3" BEL
+        "BIU_CORE/biu_register_cs_d2_3" BEL
+        "BIU_CORE/Mshreg_biu_register_cs_d2_0" BEL
+        "BIU_CORE/biu_register_cs_d2_0" BEL
+        "BIU_CORE/Mshreg_biu_register_cs_d2_2" BEL
+        "BIU_CORE/biu_register_cs_d2_2" BEL
+        "BIU_CORE/Mshreg_biu_register_cs_d2_1" BEL
+        "BIU_CORE/biu_register_cs_d2_1" PIN
+        "EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>"
+        PIN
+        "EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>"
+        PIN
+        "EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>"
+        PIN
+        "EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>"
+        PIN
+        "EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>"
+        PIN
+        "EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM9.ram_pins<26>"
+        BEL
+        "EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/sel_pipe_0"
+        PIN
+        "EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>"
+        PIN
+        "EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram_pins<28>";
+PIN SP6_BUFIO_INSERT_ML_BUFIO2_0_pins<0> = BEL "SP6_BUFIO_INSERT_ML_BUFIO2_0"
+        PINNAME DIVCLK;
+PIN SPARTAN6PLL/dcm_sp_inst_pins<2> = BEL "SPARTAN6PLL/dcm_sp_inst" PINNAME
+        CLKIN;
+TIMEGRP CORE_CLK = PIN "SP6_BUFIO_INSERT_ML_BUFIO2_0_pins<0>" PIN
+        "SPARTAN6PLL/dcm_sp_inst_pins<2>";
+TS_CORE_CLK = PERIOD TIMEGRP "CORE_CLK" 20 ns HIGH 50%;
+TS_SPARTAN6PLL_clkfx = PERIOD TIMEGRP "SPARTAN6PLL_clkfx" TS_CORE_CLK / 2.2
+        HIGH 50%;
+SCHEMATIC END;
+
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.prj b/MCL86jr/FPGA/MCL86jr/MCL86jr.prj
new file mode 100644
index 0000000..9063bf2
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.prj
@@ -0,0 +1,5 @@
+verilog work "ipcore_dir/EU4Kx32.v"
+verilog work "ipcore_dir/spartan6_pll.v"
+verilog work "../src4synth/eu.v"
+verilog work "../src4synth/biu_min.v"
+verilog work "../src4synth/MCL86jr.v"
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.ptwx b/MCL86jr/FPGA/MCL86jr/MCL86jr.ptwx
new file mode 100644
index 0000000..1e01a45
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.ptwx
@@ -0,0 +1,332 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE twReport [
+<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
+					twDebug*, twFoot?, twClientInfo?)>
+<!ATTLIST twReport version CDATA "10,4">
+<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
+<!ELEMENT twExecVer (#PCDATA)>
+<!ELEMENT twCopyright (#PCDATA)>
+<!ELEMENT twCmdLine (#PCDATA)>
+<!ELEMENT twDesign (#PCDATA)>
+<!ELEMENT twPCF (#PCDATA)>
+<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
+<!ELEMENT twDevName (#PCDATA)>
+<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
+<!ELEMENT twSpeedGrade (#PCDATA)>
+<!ELEMENT twSpeedVer (#PCDATA)>
+<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
+<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
+<!ATTLIST twRptInfo twAdvRpt  (TRUE | FALSE) "FALSE">
+<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
+<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
+<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
+<!ELEMENT twItemLimit (#PCDATA)>
+<!ELEMENT twUnconst EMPTY>
+<!ELEMENT twUnconstLimit (#PCDATA)>
+<!ELEMENT twEnvVar EMPTY>
+<!ATTLIST twEnvVar name CDATA #REQUIRED>
+<!ATTLIST twEnvVar description CDATA #REQUIRED>
+<!ELEMENT twWarn (#PCDATA)>
+<!ELEMENT twInfo (#PCDATA)>
+<!ELEMENT twDebug (#PCDATA)>
+<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
+<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
+<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
+<!ELEMENT twProc (#PCDATA)>
+<!ELEMENT twTemp (#PCDATA)>
+<!ELEMENT twVolt (#PCDATA)>
+<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
+<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG |  twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
+<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
+<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)> 
+<!ELEMENT twCycles (twSigConn+)>
+<!ATTLIST twCycles twNum CDATA #REQUIRED>
+<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
+<!ELEMENT twSig (#PCDATA)>
+<!ELEMENT twDriver (#PCDATA)>
+<!ELEMENT twLoad (#PCDATA)> 
+<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* |  (twPathRpt*, twRacePathRpt?) |  twNetRpt* | twClkSkewLimit*))>
+<!ATTLIST twConst twConstType (NET | 
+							   NETDELAY | 
+							   NETSKEW | 
+							   PATH |
+							   DEFPERIOD |
+							   UNCONSTPATH |
+							   DEFPATH | 
+							   PATH2SETUP |
+							   UNCONSTPATH2SETUP | 
+							   PATHCLASS | 
+							   PATHDELAY | 
+							   PERIOD |
+							   FREQUENCY |
+							   PATHBLOCK |
+							   OFFSET |
+							   OFFSETIN |
+							   OFFSETINCLOCK | 
+							   UNCONSTOFFSETINCLOCK |
+							   OFFSETINDELAY |
+							   OFFSETINMOD |
+							   OFFSETOUT |
+							   OFFSETOUTCLOCK |
+							   UNCONSTOFFSETOUTCLOCK | 
+							   OFFSETOUTDELAY |
+							   OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED> 
+<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
+					   twEndPtCnt?,
+					   twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
+<!ELEMENT twConstName (#PCDATA)>
+<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
+<!ATTLIST twConstHead uID CDATA #IMPLIED>
+<!ELEMENT twItemCnt (#PCDATA)>
+<!ELEMENT twErrCnt (#PCDATA)>
+<!ELEMENT twErrCntEndPt (#PCDATA)>
+<!ELEMENT twErrCntSetup (#PCDATA)>
+<!ELEMENT twErrCntHold (#PCDATA)>
+<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
+<!ELEMENT twEndPtCnt (#PCDATA)>
+<!ELEMENT twPathErrCnt (#PCDATA)>
+<!ELEMENT twMinPer (#PCDATA) >
+<!ELEMENT twFootnote EMPTY>
+<!ATTLIST twFootnote number CDATA #REQUIRED>
+<!ELEMENT twMaxDel (#PCDATA)>
+<!ELEMENT twMaxFreq (#PCDATA)>
+<!ELEMENT twMinOff (#PCDATA)>
+<!ELEMENT twMaxOff (#PCDATA)>
+<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
+<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
+<!ELEMENT twTIGName (#PCDATA)>
+<!ELEMENT twInstantiated (#PCDATA)>
+<!ELEMENT twBlocked (#PCDATA)>
+<!ELEMENT twRacePathRpt (twRacePath+)>
+<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
+<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest,  (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
+<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
+						twSimpleMinPath CDATA #IMPLIED>
+<!ELEMENT twTotDel (#PCDATA)>
+<!ELEMENT twSrc (#PCDATA)>
+<!ATTLIST twSrc BELType CDATA #IMPLIED>
+<!ELEMENT twDest (#PCDATA)>
+<!ATTLIST twDest BELType CDATA #IMPLIED>
+<!ELEMENT twDel (#PCDATA)>
+<!ELEMENT twSUTime (#PCDATA)>
+<!ELEMENT twTotPathDel (#PCDATA)>
+<!ELEMENT twClkSkew (#PCDATA)>
+<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
+<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
+<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
+<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
+<!ELEMENT twSlack (#PCDATA)>
+<!ELEMENT twDelConst (#PCDATA)>
+<!ELEMENT tw2Phase EMPTY>
+<!ELEMENT twClkUncert (#PCDATA)>
+<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED  fInputJit CDATA #IMPLIED
+					  fDCMJit CDATA #IMPLIED
+					  fPhaseErr CDATA #IMPLIED
+					  sEqu CDATA #IMPLIED>
+<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
+<!ELEMENT twPathRptBanner (#PCDATA)>
+<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
+<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
+<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
+<!ELEMENT twOff (#PCDATA)>
+<!ELEMENT twGuaranteed EMPTY>
+<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
+<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
+<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
+<!ELEMENT twClkDel (#PCDATA)>
+<!ELEMENT twClkSrc (#PCDATA)>
+<!ELEMENT twClkDest (#PCDATA)>
+<!ELEMENT twGuarInSetup (#PCDATA)>
+<!ELEMENT twOffSrc (#PCDATA)>
+<!ELEMENT twOffDest (#PCDATA)>
+<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
+<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
+<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
+<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
+<!ELEMENT twDataDel (#PCDATA)>
+<!ELEMENT twDataSrc (#PCDATA)>
+<!ELEMENT twDataDest (#PCDATA)>
+<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
+<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
+<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
+<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
+<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
+<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
+<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
+<!ELEMENT twLogLvls (#PCDATA)>
+<!ELEMENT twSrcSite (#PCDATA)>
+<!ELEMENT twSrcClk (#PCDATA)>
+<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
+<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
+<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
+<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
+<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
+<!ELEMENT twDelInfo (#PCDATA)>
+<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
+<!ELEMENT twSite (#PCDATA)>
+<!ELEMENT twDelType (#PCDATA)>
+<!ELEMENT twFanCnt (#PCDATA)>
+<!ELEMENT twComp (#PCDATA)>
+<!ELEMENT twNet (#PCDATA)>
+<!ELEMENT twBEL (#PCDATA)>
+<!ELEMENT twLogDel (#PCDATA)>
+<!ELEMENT twRouteDel (#PCDATA)>
+<!ELEMENT twDestClk (#PCDATA)>
+<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
+<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
+<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
+<!ELEMENT twPctLog (#PCDATA)>
+<!ELEMENT twPctRoute (#PCDATA)>
+<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
+<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
+<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
+<!ELEMENT twTimeConst (#PCDATA)>
+<!ELEMENT twAbsSlack (#PCDATA)>
+<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
+<!ELEMENT twSkew (#PCDATA)>
+<!ELEMENT twDetNet (twNetDel*)>
+<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
+<!ELEMENT twNetDelInfo (#PCDATA)>
+<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
+<!ELEMENT twDetSkewNet (twNetSkew*)>
+<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
+<!ELEMENT twClkSkewLimit  EMPTY>
+<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED                      arrv1 CDATA #IMPLIED
+		         arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
+<!ELEMENT twConstRollupTable (twConstRollup*)>
+<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
+<!ELEMENT twConstRollup  EMPTY>
+<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED                      requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
+<!ATTLIST twConstRollup  actualRollup CDATA #IMPLIED                      errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED                      itemsRollup CDATA #IMPLIED>
+<!ELEMENT twConstList (twConstListItem)*>
+<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)> 
+<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
+<!ELEMENT twNotMet EMPTY>
+<!ELEMENT twReqVal (#PCDATA)>
+<!ELEMENT twActVal (#PCDATA)>
+<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
+<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
+<!ELEMENT twConstStats (twConstName)>
+<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
+<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
+<!ATTLIST twConstStats twActual CDATA #IMPLIED>
+<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
+<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
+<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
+<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
+<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
+<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
+<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
+<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED  slackIndex CDATA #IMPLIED>
+<!ELEMENT twConstData EMPTY>
+<!ATTLIST twConstData type CDATA #IMPLIED  units (MHz | ns) "ns" slack CDATA #IMPLIED
+					  best CDATA #IMPLIED requested CDATA #IMPLIED
+					  errors CDATA #IMPLIED
+					  score CDATA #IMPLIED>
+<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
+<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
+<!ELEMENT twTimeGrpName (#PCDATA)>
+<!ELEMENT twCompList (twCompName+)>
+<!ELEMENT twCompName (#PCDATA)>
+<!ELEMENT twSigList (twSigName+)>
+<!ELEMENT twSigName (#PCDATA)>
+<!ELEMENT twBELList (twBELName+)>
+<!ELEMENT twBELName (#PCDATA)>
+<!ELEMENT twBlockList (twBlockName+)>
+<!ELEMENT twBlockName (#PCDATA)>
+<!ELEMENT twMacList (twMacName+)>
+<!ELEMENT twMacName (#PCDATA)>
+<!ELEMENT twPinList (twPinName+)>
+<!ELEMENT twPinName (#PCDATA)>
+<!ELEMENT twUnmetConstCnt (#PCDATA)>
+<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
+<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
+<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
+<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
+<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
+<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)> 
+<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
+<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
+<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
+<!ELEMENT twSU2ClkTime (#PCDATA)>
+<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ELEMENT twH2ClkTime (#PCDATA)>
+<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
+<!ELEMENT twClk2Pad (twDest, twTime)>
+<!ELEMENT twTime (#PCDATA)>
+<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
+<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
+<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
+<!ELEMENT twClk2Out EMPTY>
+<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
+<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
+<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
+<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
+<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
+<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
+<!ELEMENT twRiseRise (#PCDATA)>
+<!ELEMENT twFallRise (#PCDATA)>
+<!ELEMENT twRiseFall (#PCDATA)>
+<!ELEMENT twFallFall (#PCDATA)>
+<!ELEMENT twPad2PadList (twPad2Pad+)>
+<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
+<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
+<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
+<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
+<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
+<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
+<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
+<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
+<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
+<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
+<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
+<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>       
+<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
+<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED  twHoldSlack CDATA #IMPLIED>
+<!ELEMENT twOffOutTblRow EMPTY>
+<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
+<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
+<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
+<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
+<!ELEMENT twNonDedClk (#PCDATA)>
+<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
+<!ELEMENT twScore (#PCDATA)>
+<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
+<!ELEMENT twPathCnt (#PCDATA)>
+<!ELEMENT twNetCnt (#PCDATA)>
+<!ELEMENT twConnCnt (#PCDATA)>
+<!ELEMENT twPct (#PCDATA)>
+<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
+<!ELEMENT twMaxCombDel (#PCDATA)>
+<!ELEMENT twMaxFromToDel (#PCDATA)>
+<!ELEMENT twMaxNetDel (#PCDATA)>
+<!ELEMENT twMaxNetSkew (#PCDATA)>
+<!ELEMENT twMaxInAfterClk (#PCDATA)>
+<!ELEMENT twMinInBeforeClk (#PCDATA)>
+<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
+<!ELEMENT twMinOutAfterClk (#PCDATA)>
+<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
+<!ELEMENT twTimestamp (#PCDATA)>
+<!ELEMENT twFootnoteExplanation EMPTY>
+<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
+<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
+<!ELEMENT twClientInfo (twClientName, twAttrList?)>
+<!ELEMENT twClientName (#PCDATA)>
+<!ELEMENT twAttrList (twAttrListItem)*>
+<!ELEMENT twAttrListItem (twName, twValue*)>
+<!ELEMENT twName (#PCDATA)>
+<!ELEMENT twValue (#PCDATA)>
+]>
+<twReport><twBody><twSumRpt><twConstRollupTable uID="1" anchorID="55"><twConstRollup name="TS_CORE_CLK" fullName="TS_CORE_CLK = PERIOD TIMEGRP &quot;CORE_CLK&quot; 20 ns HIGH 50%;" type="origin" depth="0" requirement="20.000" prefType="period" actual="8.000" actualRollup="19.340" errors="0" errorRollup="0" items="0" itemsRollup="513828"/><twConstRollup name="TS_SPARTAN6PLL_clkfx" fullName="TS_SPARTAN6PLL_clkfx = PERIOD TIMEGRP &quot;SPARTAN6PLL_clkfx&quot; TS_CORE_CLK / 2.2         HIGH 50%;" type="child" depth="1" requirement="9.091" prefType="period" actual="8.791" actualRollup="N/A" errors="0" errorRollup="0" items="513828" itemsRollup="0"/></twConstRollupTable><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SPARTAN6PLL_clkfx = PERIOD TIMEGRP &quot;SPARTAN6PLL_clkfx&quot; TS_CORE_CLK / 2.2         HIGH 50%</twConstName><twConstData type="SETUP" slack="0.299" best="8.791" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.367" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_CORE_CLK = PERIOD TIMEGRP &quot;CORE_CLK&quot; 20 ns HIGH 50%</twConstName><twConstData type="MINLOWPULSE" slack="12.000" best="8.000" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="56">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.stx b/MCL86jr/FPGA/MCL86jr/MCL86jr.stx
new file mode 100644
index 0000000..e69de29
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.syr b/MCL86jr/FPGA/MCL86jr/MCL86jr.syr
new file mode 100644
index 0000000..200dea4
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.syr
@@ -0,0 +1,944 @@
+Release 14.7 - xst P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+--> Parameter TMPDIR set to xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.09 secs
+ 
+--> Parameter xsthdpdir set to xst
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.09 secs
+ 
+--> Reading design: MCL86jr.prj
+
+TABLE OF CONTENTS
+  1) Synthesis Options Summary
+  2) HDL Parsing
+  3) HDL Elaboration
+  4) HDL Synthesis
+       4.1) HDL Synthesis Report
+  5) Advanced HDL Synthesis
+       5.1) Advanced HDL Synthesis Report
+  6) Low Level Synthesis
+  7) Partition Report
+  8) Design Summary
+       8.1) Primitive and Black Box Usage
+       8.2) Device utilization summary
+       8.3) Partition Resource Summary
+       8.4) Timing Report
+            8.4.1) Clock Information
+            8.4.2) Asynchronous Control Signals Information
+            8.4.3) Timing Summary
+            8.4.4) Timing Details
+            8.4.5) Cross Clock Domains Report
+
+
+=========================================================================
+*                      Synthesis Options Summary                        *
+=========================================================================
+---- Source Parameters
+Input File Name                    : "MCL86jr.prj"
+Ignore Synthesis Constraint File   : NO
+
+---- Target Parameters
+Output File Name                   : "MCL86jr"
+Output Format                      : NGC
+Target Device                      : xc6slx9-3-tqg144
+
+---- Source Options
+Top Module Name                    : MCL86jr
+Automatic FSM Extraction           : YES
+FSM Encoding Algorithm             : Auto
+Safe Implementation                : No
+FSM Style                          : LUT
+RAM Extraction                     : Yes
+RAM Style                          : Auto
+ROM Extraction                     : Yes
+Shift Register Extraction          : YES
+ROM Style                          : Auto
+Resource Sharing                   : YES
+Asynchronous To Synchronous        : NO
+Shift Register Minimum Size        : 2
+Use DSP Block                      : Auto
+Automatic Register Balancing       : No
+
+---- Target Options
+LUT Combining                      : Auto
+Reduce Control Sets                : Auto
+Add IO Buffers                     : YES
+Global Maximum Fanout              : 100000
+Add Generic Clock Buffer(BUFG)     : 16
+Register Duplication               : YES
+Optimize Instantiated Primitives   : NO
+Use Clock Enable                   : Auto
+Use Synchronous Set                : Auto
+Use Synchronous Reset              : Auto
+Pack IO Registers into IOBs        : Auto
+Equivalent register Removal        : YES
+
+---- General Options
+Optimization Goal                  : Speed
+Optimization Effort                : 1
+Power Reduction                    : NO
+Keep Hierarchy                     : No
+Netlist Hierarchy                  : As_Optimized
+RTL Output                         : Yes
+Global Optimization                : AllClockNets
+Read Cores                         : YES
+Write Timing Constraints           : NO
+Cross Clock Analysis               : NO
+Hierarchy Separator                : /
+Bus Delimiter                      : <>
+Case Specifier                     : Maintain
+Slice Utilization Ratio            : 100
+BRAM Utilization Ratio             : 100
+DSP48 Utilization Ratio            : 100
+Auto BRAM Packing                  : NO
+Slice Utilization Ratio Delta      : 5
+
+---- Other Options
+Cores Search Directories           : {"ipcore_dir"  }
+
+=========================================================================
+
+
+=========================================================================
+*                          HDL Parsing                                  *
+=========================================================================
+Analyzing Verilog file "C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\EU4Kx32.v" into library work
+Parsing module <EU4Kx32>.
+Analyzing Verilog file "C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\spartan6_pll.v" into library work
+Parsing module <spartan6_pll>.
+Analyzing Verilog file "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" into library work
+Parsing module <mcl86_eu_core>.
+Analyzing Verilog file "C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" into library work
+Parsing module <biu_min>.
+Analyzing Verilog file "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" into library work
+Parsing module <MCL86jr>.
+
+=========================================================================
+*                            HDL Elaboration                            *
+=========================================================================
+
+Elaborating module <MCL86jr>.
+
+Elaborating module <spartan6_pll>.
+
+Elaborating module <IBUFG>.
+
+Elaborating module <DCM_SP(CLKDV_DIVIDE=2.0,CLKFX_DIVIDE=5,CLKFX_MULTIPLY=11,CLKIN_DIVIDE_BY_2="FALSE",CLKIN_PERIOD=20.0,CLKOUT_PHASE_SHIFT="NONE",CLK_FEEDBACK="NONE",DESKEW_ADJUST="SYSTEM_SYNCHRONOUS",PHASE_SHIFT=0,STARTUP_WAIT="FALSE")>.
+WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\spartan6_pll.v" Line 111: Assignment to clk0 ignored, since the identifier is never used
+WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\spartan6_pll.v" Line 126: Assignment to locked_int ignored, since the identifier is never used
+WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\spartan6_pll.v" Line 127: Assignment to status_int ignored, since the identifier is never used
+
+Elaborating module <BUFG>.
+WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 182: Result of 32-bit expression is truncated to fit in 1-bit target.
+WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 183: Result of 32-bit expression is truncated to fit in 1-bit target.
+WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 184: Result of 32-bit expression is truncated to fit in 1-bit target.
+WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 185: Result of 32-bit expression is truncated to fit in 1-bit target.
+WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 186: Result of 32-bit expression is truncated to fit in 1-bit target.
+WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 187: Result of 32-bit expression is truncated to fit in 1-bit target.
+WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 188: Result of 32-bit expression is truncated to fit in 1-bit target.
+WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 189: Result of 32-bit expression is truncated to fit in 1-bit target.
+WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 213: Assignment to t_eu_flag_i_d ignored, since the identifier is never used
+
+Elaborating module <biu_min>.
+WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 231: Assignment to eu_qs_out ignored, since the identifier is never used
+WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 477: Result of 32-bit expression is truncated to fit in 13-bit target.
+WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 493: Result of 17-bit expression is truncated to fit in 16-bit target.
+WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 503: Result of 17-bit expression is truncated to fit in 16-bit target.
+WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 835: Result of 17-bit expression is truncated to fit in 16-bit target.
+WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 276: Assignment to ready_d3 ignored, since the identifier is never used
+
+Elaborating module <mcl86_eu_core>.
+
+Elaborating module <EU4Kx32>.
+WARNING:HDLCompiler:1499 - "C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\EU4Kx32.v" Line 39: Empty module <EU4Kx32> remains a black box.
+WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 264: Assignment to eu_prefix_repnz ignored, since the identifier is never used
+WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 265: Assignment to eu_prefix_rep ignored, since the identifier is never used
+WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 268: Assignment to eu_flag_o ignored, since the identifier is never used
+WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 269: Assignment to eu_flag_d ignored, since the identifier is never used
+WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 272: Assignment to eu_flag_s ignored, since the identifier is never used
+WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 273: Assignment to eu_flag_z ignored, since the identifier is never used
+WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 275: Assignment to eu_flag_a ignored, since the identifier is never used
+WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 276: Assignment to eu_nmi_pending ignored, since the identifier is never used
+WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 277: Assignment to eu_flag_p ignored, since the identifier is never used
+WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 278: Assignment to eu_flag_temp ignored, since the identifier is never used
+WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 279: Assignment to eu_flag_c ignored, since the identifier is never used
+WARNING:HDLCompiler:413 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 298: Result of 20-bit expression is truncated to fit in 16-bit target.
+WARNING:HDLCompiler:1127 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 338: Assignment to biu_done_d2 ignored, since the identifier is never used
+WARNING:HDLCompiler:634 - "C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 147: Net <system_signals[15]> does not have a driver.
+
+=========================================================================
+*                           HDL Synthesis                               *
+=========================================================================
+
+Synthesizing Unit <MCL86jr>.
+    Related source file is "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v".
+INFO:Xst:3210 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" line 269: Output port <BIU_SEGMENT> of the instance <BIU_CORE> is unconnected or connected to loadless signal.
+INFO:Xst:3210 - "C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" line 322: Output port <EU_FLAG_I> of the instance <EU_CORE> is unconnected or connected to loadless signal.
+    Found 1-bit register for signal <t_biu_ad_oe_d2>.
+    Found 20-bit register for signal <t_biu_ad_out_d>.
+    Found 1-bit register for signal <t_reset_d1>.
+    Found 1-bit register for signal <t_reset_d2>.
+    Found 1-bit register for signal <t_reset_d3>.
+    Found 1-bit register for signal <t_reset_d4>.
+    Found 8-bit register for signal <led_int>.
+    Found 27-bit register for signal <prescaler>.
+    Found 1-bit register for signal <prescaler_d>.
+    Found 1-bit register for signal <led_go_left>.
+    Found 1-bit register for signal <t_biu_ad_oe_d1>.
+    Found 27-bit adder for signal <prescaler[26]_GND_1_o_add_24_OUT> created at line 241.
+    Found 1-bit tristate buffer for signal <AD7> created at line 182
+    Found 1-bit tristate buffer for signal <AD6> created at line 183
+    Found 1-bit tristate buffer for signal <AD5> created at line 184
+    Found 1-bit tristate buffer for signal <AD4> created at line 185
+    Found 1-bit tristate buffer for signal <AD3> created at line 186
+    Found 1-bit tristate buffer for signal <AD2> created at line 187
+    Found 1-bit tristate buffer for signal <AD1> created at line 188
+    Found 1-bit tristate buffer for signal <AD0> created at line 189
+    Found 1-bit tristate buffer for signal <SRAM_D<7>> created at line 199
+    Found 1-bit tristate buffer for signal <SRAM_D<6>> created at line 199
+    Found 1-bit tristate buffer for signal <SRAM_D<5>> created at line 199
+    Found 1-bit tristate buffer for signal <SRAM_D<4>> created at line 199
+    Found 1-bit tristate buffer for signal <SRAM_D<3>> created at line 199
+    Found 1-bit tristate buffer for signal <SRAM_D<2>> created at line 199
+    Found 1-bit tristate buffer for signal <SRAM_D<1>> created at line 199
+    Found 1-bit tristate buffer for signal <SRAM_D<0>> created at line 199
+    Summary:
+	inferred   1 Adder/Subtractor(s).
+	inferred  63 D-type flip-flop(s).
+	inferred   1 Multiplexer(s).
+	inferred  16 Tristate(s).
+Unit <MCL86jr> synthesized.
+
+Synthesizing Unit <spartan6_pll>.
+    Related source file is "C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\spartan6_pll.v".
+    Summary:
+	no macro.
+Unit <spartan6_pll> synthesized.
+
+Synthesizing Unit <biu_min>.
+    Related source file is "C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v".
+WARNING:Xst:647 - Input <EU_BIU_COMMAND<3:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <EU_BIU_COMMAND<15:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <EU_PREFIX_LOCK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+    Found 1-bit register for signal <clk_d2>.
+    Found 1-bit register for signal <clk_d3>.
+    Found 1-bit register for signal <clk_d4>.
+    Found 1-bit register for signal <nmi_d1>.
+    Found 1-bit register for signal <nmi_d2>.
+    Found 1-bit register for signal <nmi_d3>.
+    Found 1-bit register for signal <nmi_d4>.
+    Found 1-bit register for signal <nmi_d5>.
+    Found 1-bit register for signal <nmi_caught>.
+    Found 16-bit register for signal <eu_register_r3_d>.
+    Found 1-bit register for signal <eu_biu_req_caught>.
+    Found 16-bit register for signal <biu_register_cs>.
+    Found 16-bit register for signal <biu_register_es>.
+    Found 16-bit register for signal <biu_register_ss>.
+    Found 16-bit register for signal <biu_register_ds>.
+    Found 16-bit register for signal <biu_register_rm>.
+    Found 16-bit register for signal <biu_register_reg>.
+    Found 13-bit register for signal <clock_cycle_counter>.
+    Found 16-bit register for signal <pfq_addr_out>.
+    Found 8-bit register for signal <pfq_entry0>.
+    Found 8-bit register for signal <pfq_entry1>.
+    Found 8-bit register for signal <pfq_entry2>.
+    Found 8-bit register for signal <pfq_entry3>.
+    Found 8-bit register for signal <biu_state>.
+    Found 1-bit register for signal <pfq_write>.
+    Found 16-bit register for signal <pfq_addr_in>.
+    Found 1-bit register for signal <biu_return_data_int<15>>.
+    Found 1-bit register for signal <biu_return_data_int<14>>.
+    Found 1-bit register for signal <biu_return_data_int<13>>.
+    Found 1-bit register for signal <biu_return_data_int<12>>.
+    Found 1-bit register for signal <biu_return_data_int<11>>.
+    Found 1-bit register for signal <biu_return_data_int<10>>.
+    Found 1-bit register for signal <biu_return_data_int<9>>.
+    Found 1-bit register for signal <biu_return_data_int<8>>.
+    Found 1-bit register for signal <biu_return_data_int<7>>.
+    Found 1-bit register for signal <biu_return_data_int<6>>.
+    Found 1-bit register for signal <biu_return_data_int<5>>.
+    Found 1-bit register for signal <biu_return_data_int<4>>.
+    Found 1-bit register for signal <biu_return_data_int<3>>.
+    Found 1-bit register for signal <biu_return_data_int<2>>.
+    Found 1-bit register for signal <biu_return_data_int<1>>.
+    Found 1-bit register for signal <biu_return_data_int<0>>.
+    Found 1-bit register for signal <biu_done_int>.
+    Found 1-bit register for signal <ready_d1>.
+    Found 1-bit register for signal <eu_biu_req_d1>.
+    Found 8-bit register for signal <latched_data_in>.
+    Found 1-bit register for signal <addr_out_temp<19>>.
+    Found 1-bit register for signal <addr_out_temp<18>>.
+    Found 1-bit register for signal <addr_out_temp<17>>.
+    Found 1-bit register for signal <addr_out_temp<16>>.
+    Found 1-bit register for signal <addr_out_temp<15>>.
+    Found 1-bit register for signal <addr_out_temp<14>>.
+    Found 1-bit register for signal <addr_out_temp<13>>.
+    Found 1-bit register for signal <addr_out_temp<12>>.
+    Found 1-bit register for signal <addr_out_temp<11>>.
+    Found 1-bit register for signal <addr_out_temp<10>>.
+    Found 1-bit register for signal <addr_out_temp<9>>.
+    Found 1-bit register for signal <addr_out_temp<8>>.
+    Found 1-bit register for signal <addr_out_temp<7>>.
+    Found 1-bit register for signal <addr_out_temp<6>>.
+    Found 1-bit register for signal <addr_out_temp<5>>.
+    Found 1-bit register for signal <addr_out_temp<4>>.
+    Found 1-bit register for signal <addr_out_temp<3>>.
+    Found 1-bit register for signal <addr_out_temp<2>>.
+    Found 1-bit register for signal <addr_out_temp<1>>.
+    Found 1-bit register for signal <addr_out_temp<0>>.
+    Found 3-bit register for signal <s_bits>.
+    Found 1-bit register for signal <AD_OUT<19>>.
+    Found 1-bit register for signal <AD_OUT<18>>.
+    Found 1-bit register for signal <AD_OUT<17>>.
+    Found 1-bit register for signal <AD_OUT<16>>.
+    Found 1-bit register for signal <AD_OUT<15>>.
+    Found 1-bit register for signal <AD_OUT<14>>.
+    Found 1-bit register for signal <AD_OUT<13>>.
+    Found 1-bit register for signal <AD_OUT<12>>.
+    Found 1-bit register for signal <AD_OUT<11>>.
+    Found 1-bit register for signal <AD_OUT<10>>.
+    Found 1-bit register for signal <AD_OUT<9>>.
+    Found 1-bit register for signal <AD_OUT<8>>.
+    Found 1-bit register for signal <AD_OUT<7>>.
+    Found 1-bit register for signal <AD_OUT<6>>.
+    Found 1-bit register for signal <AD_OUT<5>>.
+    Found 1-bit register for signal <AD_OUT<4>>.
+    Found 1-bit register for signal <AD_OUT<3>>.
+    Found 1-bit register for signal <AD_OUT<2>>.
+    Found 1-bit register for signal <AD_OUT<1>>.
+    Found 1-bit register for signal <AD_OUT<0>>.
+    Found 1-bit register for signal <word_cycle>.
+    Found 1-bit register for signal <byte_num>.
+    Found 8-bit register for signal <ad_in_int>.
+    Found 1-bit register for signal <BIU_INTR>.
+    Found 1-bit register for signal <intr_d1>.
+    Found 1-bit register for signal <intr_d2>.
+    Found 1-bit register for signal <intr_d3>.
+    Found 1-bit register for signal <AD_OE>.
+    Found 1-bit register for signal <RD_n>.
+    Found 1-bit register for signal <WR_n>.
+    Found 1-bit register for signal <IOM>.
+    Found 1-bit register for signal <DTR>.
+    Found 1-bit register for signal <DEN>.
+    Found 1-bit register for signal <INTA_n>.
+    Found 1-bit register for signal <inta_n_int>.
+    Found 1-bit register for signal <ale_int>.
+    Found 1-bit register for signal <rd_n_int>.
+    Found 1-bit register for signal <wr_n_int>.
+    Found 1-bit register for signal <iom_int>.
+    Found 1-bit register for signal <dtr_int>.
+    Found 1-bit register for signal <den_int>.
+    Found 1-bit register for signal <SRAM_OE_n>.
+    Found 1-bit register for signal <SRAM_WE_n>.
+    Found 1-bit register for signal <SRAM_D_OE>.
+    Found 16-bit register for signal <biu_register_es_d1>.
+    Found 16-bit register for signal <biu_register_ss_d1>.
+    Found 16-bit register for signal <biu_register_cs_d1>.
+    Found 16-bit register for signal <biu_register_ds_d1>.
+    Found 16-bit register for signal <biu_register_rm_d1>.
+    Found 16-bit register for signal <biu_register_reg_d1>.
+    Found 16-bit register for signal <biu_register_es_d2>.
+    Found 16-bit register for signal <biu_register_ss_d2>.
+    Found 16-bit register for signal <biu_register_cs_d2>.
+    Found 16-bit register for signal <biu_register_ds_d2>.
+    Found 16-bit register for signal <biu_register_rm_d2>.
+    Found 16-bit register for signal <biu_register_reg_d2>.
+    Found 8-bit register for signal <pfq_top_byte_int_d1>.
+    Found 16-bit register for signal <pfq_addr_out_d1>.
+    Found 16-bit register for signal <biu_return_data_int_d1>.
+    Found 16-bit register for signal <biu_return_data_int_d2>.
+    Found 26-bit register for signal <nmi_counter>.
+    Found 1-bit register for signal <ALE>.
+    Found 1-bit register for signal <sram_select>.
+    Found 8-bit register for signal <mcl6_feature>.
+    Found 1-bit register for signal <SRAM_A<18>>.
+    Found 1-bit register for signal <SRAM_A<17>>.
+    Found 1-bit register for signal <SRAM_A<16>>.
+    Found 1-bit register for signal <SRAM_A<15>>.
+    Found 1-bit register for signal <SRAM_A<14>>.
+    Found 1-bit register for signal <SRAM_A<13>>.
+    Found 1-bit register for signal <SRAM_A<12>>.
+    Found 1-bit register for signal <SRAM_A<11>>.
+    Found 1-bit register for signal <SRAM_A<10>>.
+    Found 1-bit register for signal <SRAM_A<9>>.
+    Found 1-bit register for signal <SRAM_A<8>>.
+    Found 1-bit register for signal <SRAM_A<7>>.
+    Found 1-bit register for signal <SRAM_A<6>>.
+    Found 1-bit register for signal <SRAM_A<5>>.
+    Found 1-bit register for signal <SRAM_A<4>>.
+    Found 1-bit register for signal <SRAM_A<3>>.
+    Found 1-bit register for signal <SRAM_A<2>>.
+    Found 1-bit register for signal <SRAM_A<1>>.
+    Found 1-bit register for signal <SRAM_A<0>>.
+    Found 8-bit register for signal <SRAM_D_OUT>.
+    Found 1-bit register for signal <clk_d1>.
+    Found 26-bit adder for signal <nmi_counter[25]_GND_22_o_add_44_OUT> created at line 402.
+    Found 16-bit adder for signal <pfq_addr_out[15]_GND_22_o_add_79_OUT> created at line 493.
+    Found 16-bit adder for signal <pfq_addr_in[15]_GND_22_o_add_85_OUT> created at line 503.
+    Found 8-bit adder for signal <biu_state[7]_GND_22_o_add_97_OUT> created at line 523.
+    Found 20-bit adder for signal <biu_register_cs[15]_GND_22_o_add_99_OUT> created at line 579.
+    Found 20-bit adder for signal <biu_muxed_segment[15]_GND_22_o_add_100_OUT> created at line 586.
+    Found 20-bit adder for signal <biu_register_ss[15]_GND_22_o_add_102_OUT> created at line 601.
+    Found 20-bit adder for signal <biu_register_cs[15]_GND_22_o_add_128_OUT> created at line 651.
+    Found 16-bit adder for signal <addr_out_temp[15]_GND_22_o_add_186_OUT> created at line 875.
+    Found 13-bit subtractor for signal <GND_22_o_GND_22_o_sub_73_OUT<12:0>> created at line 477.
+    Found 16-bit 4-to-1 multiplexer for signal <biu_muxed_segment> created at line 189.
+    Found 8-bit 4-to-1 multiplexer for signal <pfq_top_byte_int> created at line 196.
+    Found 1-bit comparator equal for signal <n0033> created at line 255
+    Found 2-bit comparator equal for signal <pfq_addr_in[1]_pfq_addr_out[1]_equal_33_o> created at line 256
+    Found 4-bit comparator greater for signal <GND_22_o_addr_out_temp[19]_LessThan_140_o> created at line 671
+    Found 4-bit comparator greater for signal <addr_out_temp[19]_PWR_6_o_LessThan_141_o> created at line 671
+    Summary:
+	inferred  10 Adder/Subtractor(s).
+	inferred 621 D-type flip-flop(s).
+	inferred   4 Comparator(s).
+	inferred 101 Multiplexer(s).
+Unit <biu_min> synthesized.
+
+Synthesizing Unit <mcl86_eu_core>.
+    Related source file is "C:\MCL\MCL86\MCL86jr\src4synth\eu.v".
+WARNING:Xst:653 - Signal <system_signals<15:14>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
+WARNING:Xst:653 - Signal <system_signals<10>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
+    Found 1-bit register for signal <eu_biu_req_d1>.
+    Found 1-bit register for signal <biu_done_caught>.
+    Found 1-bit register for signal <eu_flag_t_d>.
+    Found 1-bit register for signal <eu_tr_latched>.
+    Found 1-bit register for signal <eu_add_carry>.
+    Found 1-bit register for signal <eu_add_carry8>.
+    Found 1-bit register for signal <eu_add_aux_carry>.
+    Found 1-bit register for signal <eu_add_overflow16>.
+    Found 1-bit register for signal <eu_add_overflow8>.
+    Found 16-bit register for signal <eu_alu_last_result>.
+    Found 16-bit register for signal <eu_register_ax>.
+    Found 16-bit register for signal <eu_register_bx>.
+    Found 16-bit register for signal <eu_register_cx>.
+    Found 16-bit register for signal <eu_register_dx>.
+    Found 16-bit register for signal <eu_register_sp>.
+    Found 16-bit register for signal <eu_register_bp>.
+    Found 16-bit register for signal <eu_register_si>.
+    Found 16-bit register for signal <eu_register_di>.
+    Found 16-bit register for signal <eu_flags>.
+    Found 16-bit register for signal <eu_register_r0>.
+    Found 16-bit register for signal <eu_register_r1>.
+    Found 16-bit register for signal <eu_register_r2>.
+    Found 16-bit register for signal <eu_register_r3>.
+    Found 16-bit register for signal <eu_biu_command>.
+    Found 16-bit register for signal <eu_biu_dataout>.
+    Found 1-bit register for signal <eu_stall_pipeline>.
+    Found 13-bit register for signal <eu_rom_address>.
+    Found 52-bit register for signal <eu_calling_address>.
+    Found 1-bit register for signal <intr_enable_delayed>.
+    Found 1-bit register for signal <biu_done_d1>.
+    Found 13-bit adder for signal <eu_rom_address[12]_GND_23_o_add_186_OUT> created at line 483.
+    Found 16-bit 16-to-1 multiplexer for signal <eu_operand0> created at line 155.
+    Found 16-bit 16-to-1 multiplexer for signal <eu_operand1> created at line 156.
+    Found 20-bit 7-to-1 multiplexer for signal <n0455> created at line 298.
+    Summary:
+	inferred   1 Adder/Subtractor(s).
+	inferred 333 D-type flip-flop(s).
+	inferred  54 Multiplexer(s).
+Unit <mcl86_eu_core> synthesized.
+
+=========================================================================
+HDL Synthesis Report
+
+Macro Statistics
+# Adders/Subtractors                                   : 12
+ 13-bit adder                                          : 1
+ 13-bit subtractor                                     : 1
+ 16-bit adder                                          : 3
+ 20-bit adder                                          : 4
+ 26-bit adder                                          : 1
+ 27-bit adder                                          : 1
+ 8-bit adder                                           : 1
+# Registers                                            : 129
+ 1-bit register                                        : 68
+ 13-bit register                                       : 2
+ 16-bit register                                       : 41
+ 19-bit register                                       : 1
+ 20-bit register                                       : 3
+ 26-bit register                                       : 1
+ 27-bit register                                       : 1
+ 3-bit register                                        : 1
+ 52-bit register                                       : 1
+ 8-bit register                                        : 10
+# Comparators                                          : 4
+ 1-bit comparator equal                                : 1
+ 2-bit comparator equal                                : 1
+ 4-bit comparator greater                              : 2
+# Multiplexers                                         : 156
+ 1-bit 2-to-1 multiplexer                              : 118
+ 13-bit 2-to-1 multiplexer                             : 9
+ 16-bit 16-to-1 multiplexer                            : 2
+ 16-bit 2-to-1 multiplexer                             : 3
+ 16-bit 4-to-1 multiplexer                             : 1
+ 2-bit 2-to-1 multiplexer                              : 1
+ 20-bit 2-to-1 multiplexer                             : 3
+ 20-bit 7-to-1 multiplexer                             : 1
+ 26-bit 2-to-1 multiplexer                             : 1
+ 3-bit 2-to-1 multiplexer                              : 1
+ 52-bit 2-to-1 multiplexer                             : 1
+ 8-bit 2-to-1 multiplexer                              : 14
+ 8-bit 4-to-1 multiplexer                              : 1
+# Tristates                                            : 16
+ 1-bit tristate buffer                                 : 16
+# Xors                                                 : 20
+ 1-bit xor2                                            : 2
+ 1-bit xor3                                            : 16
+ 1-bit xor8                                            : 1
+ 16-bit xor2                                           : 1
+
+=========================================================================
+
+=========================================================================
+*                       Advanced HDL Synthesis                          *
+=========================================================================
+
+Reading core <ipcore_dir/EU4Kx32.ngc>.
+Loading core <EU4Kx32> for timing and area information for instance <EU4Kx32_i>.
+WARNING:Xst:2677 - Node <mcl6_feature_2> of sequential type is unconnected in block <BIU_CORE>.
+WARNING:Xst:2677 - Node <mcl6_feature_3> of sequential type is unconnected in block <BIU_CORE>.
+WARNING:Xst:2677 - Node <mcl6_feature_4> of sequential type is unconnected in block <BIU_CORE>.
+WARNING:Xst:2677 - Node <mcl6_feature_5> of sequential type is unconnected in block <BIU_CORE>.
+WARNING:Xst:2677 - Node <mcl6_feature_6> of sequential type is unconnected in block <BIU_CORE>.
+WARNING:Xst:2677 - Node <mcl6_feature_7> of sequential type is unconnected in block <BIU_CORE>.
+
+Synthesizing (advanced) Unit <MCL86jr>.
+The following registers are absorbed into counter <prescaler>: 1 register on signal <prescaler>.
+Unit <MCL86jr> synthesized (advanced).
+
+Synthesizing (advanced) Unit <biu_min>.
+The following registers are absorbed into counter <clock_cycle_counter>: 1 register on signal <clock_cycle_counter>.
+The following registers are absorbed into counter <pfq_addr_out>: 1 register on signal <pfq_addr_out>.
+The following registers are absorbed into counter <nmi_counter>: 1 register on signal <nmi_counter>.
+The following registers are absorbed into counter <pfq_addr_in>: 1 register on signal <pfq_addr_in>.
+Unit <biu_min> synthesized (advanced).
+WARNING:Xst:2677 - Node <mcl6_feature_2> of sequential type is unconnected in block <biu_min>.
+WARNING:Xst:2677 - Node <mcl6_feature_3> of sequential type is unconnected in block <biu_min>.
+WARNING:Xst:2677 - Node <mcl6_feature_4> of sequential type is unconnected in block <biu_min>.
+WARNING:Xst:2677 - Node <mcl6_feature_5> of sequential type is unconnected in block <biu_min>.
+WARNING:Xst:2677 - Node <mcl6_feature_6> of sequential type is unconnected in block <biu_min>.
+WARNING:Xst:2677 - Node <mcl6_feature_7> of sequential type is unconnected in block <biu_min>.
+
+=========================================================================
+Advanced HDL Synthesis Report
+
+Macro Statistics
+# Adders/Subtractors                                   : 7
+ 13-bit adder                                          : 1
+ 16-bit adder                                          : 1
+ 20-bit adder                                          : 4
+ 8-bit adder                                           : 1
+# Counters                                             : 5
+ 13-bit down counter                                   : 1
+ 16-bit up counter                                     : 2
+ 26-bit up counter                                     : 1
+ 27-bit up counter                                     : 1
+# Registers                                            : 913
+ Flip-Flops                                            : 913
+# Comparators                                          : 4
+ 1-bit comparator equal                                : 1
+ 2-bit comparator equal                                : 1
+ 4-bit comparator greater                              : 2
+# Multiplexers                                         : 209
+ 1-bit 16-to-1 multiplexer                             : 32
+ 1-bit 2-to-1 multiplexer                              : 131
+ 1-bit 4-to-1 multiplexer                              : 16
+ 13-bit 2-to-1 multiplexer                             : 7
+ 16-bit 2-to-1 multiplexer                             : 1
+ 2-bit 2-to-1 multiplexer                              : 1
+ 20-bit 2-to-1 multiplexer                             : 3
+ 20-bit 7-to-1 multiplexer                             : 1
+ 3-bit 2-to-1 multiplexer                              : 1
+ 52-bit 2-to-1 multiplexer                             : 1
+ 8-bit 2-to-1 multiplexer                              : 14
+ 8-bit 4-to-1 multiplexer                              : 1
+# Xors                                                 : 20
+ 1-bit xor2                                            : 2
+ 1-bit xor3                                            : 16
+ 1-bit xor8                                            : 1
+ 16-bit xor2                                           : 1
+
+=========================================================================
+
+=========================================================================
+*                         Low Level Synthesis                           *
+=========================================================================
+WARNING:Xst:2677 - Node <prescaler_22> of sequential type is unconnected in block <MCL86jr>.
+WARNING:Xst:2677 - Node <prescaler_23> of sequential type is unconnected in block <MCL86jr>.
+WARNING:Xst:2677 - Node <prescaler_24> of sequential type is unconnected in block <MCL86jr>.
+WARNING:Xst:2677 - Node <prescaler_25> of sequential type is unconnected in block <MCL86jr>.
+WARNING:Xst:2677 - Node <prescaler_26> of sequential type is unconnected in block <MCL86jr>.
+
+Optimizing unit <MCL86jr> ...
+
+Optimizing unit <biu_min> ...
+
+Optimizing unit <mcl86_eu_core> ...
+INFO:Xst:2261 - The FF/Latch <BIU_CORE/eu_biu_req_d1> in Unit <MCL86jr> is equivalent to the following FF/Latch, which will be removed : <EU_CORE/eu_biu_req_d1> 
+
+Mapping all equations...
+Building and optimizing final netlist ...
+Found area constraint ratio of 100 (+ 5) on block MCL86jr, actual ratio is 32.
+
+Final Macro Processing ...
+
+Processing Unit <MCL86jr> :
+	Found 2-bit shift register for signal <t_biu_ad_oe_d2>.
+	Found 2-bit shift register for signal <t_reset_d2>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_15>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_14>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_13>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_12>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_11>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_10>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_9>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_8>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_7>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_6>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_5>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_4>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_3>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_2>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_1>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_return_data_int_d2_0>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_15>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_14>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_13>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_12>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_11>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_10>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_9>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_8>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_7>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_6>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_5>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_4>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_3>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_2>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_1>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_rm_d2_0>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_15>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_14>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_13>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_12>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_11>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_10>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_9>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_8>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_7>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_6>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_5>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_4>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_3>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_2>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_1>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ds_d2_0>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_15>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_14>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_13>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_12>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_11>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_10>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_9>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_8>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_7>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_6>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_5>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_4>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_3>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_2>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_1>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_reg_d2_0>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_15>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_14>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_13>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_12>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_11>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_10>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_9>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_8>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_7>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_6>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_5>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_4>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_3>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_2>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_1>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_ss_d2_0>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_15>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_14>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_13>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_12>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_11>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_10>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_9>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_8>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_7>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_6>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_5>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_4>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_3>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_2>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_1>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_es_d2_0>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_15>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_14>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_13>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_12>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_11>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_10>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_9>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_8>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_7>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_6>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_5>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_4>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_3>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_2>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_1>.
+	Found 2-bit shift register for signal <BIU_CORE/biu_register_cs_d2_0>.
+Unit <MCL86jr> processed.
+
+=========================================================================
+Final Register Report
+
+Macro Statistics
+# Registers                                            : 777
+ Flip-Flops                                            : 777
+# Shift Registers                                      : 114
+ 2-bit shift register                                  : 114
+
+=========================================================================
+
+=========================================================================
+*                           Partition Report                            *
+=========================================================================
+
+Partition Implementation Status
+-------------------------------
+
+  No Partitions were found in this design.
+
+-------------------------------
+
+=========================================================================
+*                            Design Summary                             *
+=========================================================================
+
+Top Level Output File Name         : MCL86jr.ngc
+
+Primitive and Black Box Usage:
+------------------------------
+# BELS                             : 1407
+#      GND                         : 2
+#      INV                         : 15
+#      LUT1                        : 60
+#      LUT2                        : 87
+#      LUT3                        : 116
+#      LUT4                        : 73
+#      LUT5                        : 223
+#      LUT6                        : 384
+#      MUXCY                       : 175
+#      MUXF7                       : 59
+#      MUXF8                       : 25
+#      VCC                         : 2
+#      XORCY                       : 186
+# FlipFlops/Latches                : 892
+#      FD                          : 48
+#      FDE                         : 183
+#      FDR                         : 125
+#      FDRE                        : 503
+#      FDS                         : 13
+#      FDSE                        : 20
+# RAMS                             : 8
+#      RAMB16BWER                  : 7
+#      RAMB8BWER                   : 1
+# Shift Registers                  : 114
+#      SRLC16E                     : 114
+# Clock Buffers                    : 1
+#      BUFG                        : 1
+# IO Buffers                       : 75
+#      IBUF                        : 5
+#      IBUFG                       : 1
+#      IOBUF                       : 16
+#      OBUF                        : 53
+# DCMs                             : 1
+#      DCM_SP                      : 1
+
+Device utilization summary:
+---------------------------
+
+Selected Device : 6slx9tqg144-3 
+
+
+Slice Logic Utilization: 
+ Number of Slice Registers:             892  out of  11440     7%  
+ Number of Slice LUTs:                 1072  out of   5720    18%  
+    Number used as Logic:               958  out of   5720    16%  
+    Number used as Memory:              114  out of   1440     7%  
+       Number used as SRL:              114
+
+Slice Logic Distribution: 
+ Number of LUT Flip Flop pairs used:   1452
+   Number with an unused Flip Flop:     560  out of   1452    38%  
+   Number with an unused LUT:           380  out of   1452    26%  
+   Number of fully used LUT-FF pairs:   512  out of   1452    35%  
+   Number of unique control sets:        41
+
+IO Utilization: 
+ Number of IOs:                          75
+ Number of bonded IOBs:                  75  out of    102    73%  
+
+Specific Feature Utilization:
+ Number of Block RAM/FIFO:                8  out of     32    25%  
+    Number using Block RAM only:          8
+ Number of BUFG/BUFGCTRLs:                1  out of     16     6%  
+
+---------------------------
+Partition Resource Summary:
+---------------------------
+
+  No Partitions were found in this design.
+
+---------------------------
+
+
+=========================================================================
+Timing Report
+
+NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
+      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
+      GENERATED AFTER PLACE-and-ROUTE.
+
+Clock Information:
+------------------
+-----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------+-------+
+Clock Signal                       | Clock buffer(FF name)                                                                                                                      | Load  |
+-----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------+-------+
+CORE_CLK                           | DCM_SP:CLKFX                                                                                                                               | 1014  |
+EU_CORE/EU4Kx32_i/N1               | NONE(EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram)| 8     |
+-----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------+-------+
+INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
+
+Asynchronous Control Signals Information:
+----------------------------------------
+No asynchronous control signals found in this design
+
+Timing Summary:
+---------------
+Speed Grade: -3
+
+   Minimum period: 20.419ns (Maximum Frequency: 48.973MHz)
+   Minimum input arrival time before clock: 3.307ns
+   Maximum output required time after clock: 4.642ns
+   Maximum combinational path delay: No path found
+
+Timing Details:
+---------------
+All values displayed in nanoseconds (ns)
+
+=========================================================================
+Timing constraint: Default period analysis for Clock 'CORE_CLK'
+  Clock period: 20.419ns (frequency: 48.973MHz)
+  Total number of paths / destination ports: 513942 / 2565
+-------------------------------------------------------------------------
+Delay:               9.282ns (Levels of Logic = 9)
+  Source:            EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
+  Destination:       EU_CORE/eu_register_r0_15 (FF)
+  Source Clock:      CORE_CLK rising 2.2X
+  Destination Clock: CORE_CLK rising 2.2X
+
+  Data Path: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_register_r0_15
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     RAMB16BWER:CLKA->DOA7    1   1.850   0.684  U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<7>)
+     LUT3:I1->O           88   0.203   1.903  U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux141 (douta<21>)
+     end scope: 'EU_CORE/EU4Kx32_i:douta<21>'
+     LUT5:I3->O            1   0.203   0.000  EU_CORE/mux30_4 (EU_CORE/mux30_4)
+     MUXF7:I1->O           1   0.140   0.000  EU_CORE/mux30_3_f7 (EU_CORE/mux30_3_f7)
+     MUXF8:I1->O          10   0.152   1.085  EU_CORE/mux30_2_f8 (EU_CORE/eu_operand0<8>1)
+     LUT6:I3->O            2   0.205   0.617  EU_CORE/carry<7>1_SW0 (N146)
+     LUT5:I4->O            1   0.205   0.808  EU_CORE/carry<9>1_SW0 (N152)
+     LUT5:I2->O            5   0.205   0.715  EU_CORE/carry<11>1 (EU_CORE/carry<11>)
+     LUT6:I5->O           16   0.205   0.000  EU_CORE/Mmux_n045534 (EU_CORE/n0455<11>)
+     FDRE:D                    0.102          EU_CORE/eu_register_ax_11
+    ----------------------------------------
+    Total                      9.282ns (3.470ns logic, 5.812ns route)
+                                       (37.4% logic, 62.6% route)
+
+=========================================================================
+Timing constraint: Default OFFSET IN BEFORE for Clock 'CORE_CLK'
+  Total number of paths / destination ports: 37 / 37
+-------------------------------------------------------------------------
+Offset:              3.307ns (Levels of Logic = 3)
+  Source:            SRAM_D<1> (PAD)
+  Destination:       BIU_CORE/biu_return_data_int_9 (FF)
+  Destination Clock: CORE_CLK rising 2.2X
+
+  Data Path: SRAM_D<1> to BIU_CORE/biu_return_data_int_9
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     IOBUF:IO->O           3   1.222   0.995  SRAM_D_1_IOBUF (N103)
+     LUT5:I0->O            1   0.203   0.580  BIU_CORE/biu_state[7]_biu_return_data_int[15]_select_249_OUT<6>_SW1 (N215)
+     LUT5:I4->O            1   0.205   0.000  BIU_CORE/biu_state[7]_biu_return_data_int[15]_select_249_OUT<6> (BIU_CORE/biu_state[7]_biu_return_data_int[15]_select_249_OUT<9>)
+     FDR:D                     0.102          BIU_CORE/biu_return_data_int_9
+    ----------------------------------------
+    Total                      3.307ns (1.732ns logic, 1.575ns route)
+                                       (52.4% logic, 47.6% route)
+
+=========================================================================
+Timing constraint: Default OFFSET OUT AFTER for Clock 'CORE_CLK'
+  Total number of paths / destination ports: 82 / 66
+-------------------------------------------------------------------------
+Offset:              4.642ns (Levels of Logic = 2)
+  Source:            BIU_CORE/SRAM_D_OE (FF)
+  Destination:       SRAM_D<7> (PAD)
+  Source Clock:      CORE_CLK rising 2.2X
+
+  Data Path: BIU_CORE/SRAM_D_OE to SRAM_D<7>
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     FDR:C->Q              2   0.447   0.616  BIU_CORE/SRAM_D_OE (BIU_CORE/SRAM_D_OE)
+     INV:I->O              8   0.206   0.802  t_sram_d_oe_inv1_INV_0 (t_sram_d_oe_inv)
+     IOBUF:T->IO               2.571          SRAM_D_7_IOBUF (SRAM_D<7>)
+    ----------------------------------------
+    Total                      4.642ns (3.224ns logic, 1.418ns route)
+                                       (69.5% logic, 30.5% route)
+
+=========================================================================
+
+Cross Clock Domains Report:
+--------------------------
+
+Clock to Setup on destination clock CORE_CLK
+---------------+---------+---------+---------+---------+
+               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
+Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
+---------------+---------+---------+---------+---------+
+CORE_CLK       |    9.282|         |         |         |
+---------------+---------+---------+---------+---------+
+
+=========================================================================
+
+
+Total REAL time to Xst completion: 17.00 secs
+Total CPU time to Xst completion: 16.43 secs
+ 
+--> 
+
+Total memory usage is 268688 kilobytes
+
+Number of errors   :    0 (   0 filtered)
+Number of warnings :   55 (   0 filtered)
+Number of infos    :    4 (   0 filtered)
+
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.twr b/MCL86jr/FPGA/MCL86jr/MCL86jr.twr
new file mode 100644
index 0000000..8c66200
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.twr
@@ -0,0 +1,694 @@
+--------------------------------------------------------------------------------
+Release 14.7 Trace  (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3
+-n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf
+MCL86jr.ucf
+
+Design file:              MCL86jr.ncd
+Physical constraint file: MCL86jr.pcf
+Device,package,speed:     xc6slx9,tqg144,C,-3 (PRODUCTION 1.23 2013-10-13)
+Report level:             verbose report
+
+Environment Variable      Effect 
+--------------------      ------ 
+NONE                      No environment variables were set
+--------------------------------------------------------------------------------
+
+INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
+INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
+   option. All paths that are not constrained will be reported in the 
+   unconstrained paths section(s) of the report.
+INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
+   a 50 Ohm transmission line loading model.  For the details of this model, 
+   and for more information on accounting for different loading conditions, 
+   please see the device datasheet.
+
+================================================================================
+Timing constraint: TS_CORE_CLK = PERIOD TIMEGRP "CORE_CLK" 20 ns HIGH 50%;
+For more information, see Period Analysis in the Timing Closure User Guide (UG612).
+
+ 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
+ 0 timing errors detected. (0 component switching limit errors)
+ Minimum period is   8.000ns.
+--------------------------------------------------------------------------------
+
+Component Switching Limit Checks: TS_CORE_CLK = PERIOD TIMEGRP "CORE_CLK" 20 ns HIGH 50%;
+--------------------------------------------------------------------------------
+Slack: 6.421ns (period - min period limit)
+  Period: 9.091ns
+  Min period limit: 2.670ns (374.532MHz) (Tdcmper_CLKFX)
+  Physical resource: SPARTAN6PLL/dcm_sp_inst/CLKFX
+  Logical resource: SPARTAN6PLL/dcm_sp_inst/CLKFX
+  Location pin: DCM_X0Y1.CLKFX
+  Clock network: SPARTAN6PLL/clkfx
+--------------------------------------------------------------------------------
+Slack: 12.000ns (period - (min low pulse limit / (low pulse / period)))
+  Period: 20.000ns
+  Low pulse: 10.000ns
+  Low pulse limit: 4.000ns (Tdcmpw_CLKIN_50_100)
+  Physical resource: SPARTAN6PLL/dcm_sp_inst/CLKIN
+  Logical resource: SPARTAN6PLL/dcm_sp_inst/CLKIN
+  Location pin: DCM_X0Y1.CLKIN
+  Clock network: SPARTAN6PLL/dcm_sp_inst_ML_NEW_DIVCLK
+--------------------------------------------------------------------------------
+Slack: 12.000ns (period - (min high pulse limit / (high pulse / period)))
+  Period: 20.000ns
+  High pulse: 10.000ns
+  High pulse limit: 4.000ns (Tdcmpw_CLKIN_50_100)
+  Physical resource: SPARTAN6PLL/dcm_sp_inst/CLKIN
+  Logical resource: SPARTAN6PLL/dcm_sp_inst/CLKIN
+  Location pin: DCM_X0Y1.CLKIN
+  Clock network: SPARTAN6PLL/dcm_sp_inst_ML_NEW_DIVCLK
+--------------------------------------------------------------------------------
+
+================================================================================
+Timing constraint: TS_SPARTAN6PLL_clkfx = PERIOD TIMEGRP "SPARTAN6PLL_clkfx" 
+TS_CORE_CLK / 2.2         HIGH 50%;
+For more information, see Period Analysis in the Timing Closure User Guide (UG612).
+
+ 513828 paths analyzed, 3870 endpoints analyzed, 0 failing endpoints
+ 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
+ Minimum period is   8.791ns.
+--------------------------------------------------------------------------------
+
+Paths for end point EU_CORE/eu_flags_12 (SLICE_X15Y29.BX), 2245 paths
+--------------------------------------------------------------------------------
+Slack (setup path):     0.299ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
+  Destination:          EU_CORE/eu_flags_12 (FF)
+  Requirement:          9.090ns
+  Data Path Delay:      8.558ns (Levels of Logic = 6)
+  Clock Path Skew:      -0.007ns (0.243 - 0.250)
+  Source Clock:         core_clk_int rising at 0.000ns
+  Destination Clock:    core_clk_int rising at 9.090ns
+  Clock Uncertainty:    0.226ns
+
+  Clock Uncertainty:          0.226ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter (TSJ):  0.070ns
+    Total Input Jitter (TIJ):   0.000ns
+    Discrete Jitter (DJ):       0.381ns
+    Phase Error (PE):           0.000ns
+
+  Maximum Data Path at Slow Process Corner: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_flags_12
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    RAMB16_X1Y10.DOA5    Trcko_DOA             1.850   EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
+                                                       EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
+    SLICE_X17Y23.B3      net (fanout=1)        1.070   EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<5>
+    SLICE_X17Y23.B       Tilo                  0.259   EU_CORE/eu_register_r0<3>
+                                                       EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux111
+    SLICE_X12Y22.BX      net (fanout=18)       0.850   EU_CORE/eu_rom_data<19>
+    SLICE_X12Y22.BMUX    Tbxb                  0.157   EU_CORE/eu_biu_dataout<3>
+                                                       EU_CORE/mux14_2_f8
+    SLICE_X13Y25.D1      net (fanout=5)        0.878   EU_CORE/eu_operand1<8>
+    SLICE_X13Y25.D       Tilo                  0.259   EU_CORE/eu_register_r2<11>
+                                                       EU_CORE/carry<7>1_SW1
+    SLICE_X13Y25.C6      net (fanout=3)        0.132   N147
+    SLICE_X13Y25.C       Tilo                  0.259   EU_CORE/eu_register_r2<11>
+                                                       EU_CORE/carry<9>1_SW1
+    SLICE_X15Y24.C2      net (fanout=1)        0.804   N153
+    SLICE_X15Y24.C       Tilo                  0.259   EU_CORE/eu_alu_last_result<11>
+                                                       EU_CORE/carry<11>1
+    SLICE_X17Y30.A5      net (fanout=7)        0.811   EU_CORE/carry<11>
+    SLICE_X17Y30.A       Tilo                  0.259   EU_CORE/eu_register_r1<15>
+                                                       EU_CORE/Mmux_n045543
+    SLICE_X15Y29.BX      net (fanout=13)       0.648   EU_CORE/n0455<12>
+    SLICE_X15Y29.CLK     Tdick                 0.063   EU_CORE/eu_flags<14>
+                                                       EU_CORE/eu_flags_12
+    -------------------------------------------------  ---------------------------
+    Total                                      8.558ns (3.365ns logic, 5.193ns route)
+                                                       (39.3% logic, 60.7% route)
+
+--------------------------------------------------------------------------------
+Slack (setup path):     0.368ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
+  Destination:          EU_CORE/eu_flags_12 (FF)
+  Requirement:          9.090ns
+  Data Path Delay:      8.492ns (Levels of Logic = 6)
+  Clock Path Skew:      -0.004ns (0.243 - 0.247)
+  Source Clock:         core_clk_int rising at 0.000ns
+  Destination Clock:    core_clk_int rising at 9.090ns
+  Clock Uncertainty:    0.226ns
+
+  Clock Uncertainty:          0.226ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter (TSJ):  0.070ns
+    Total Input Jitter (TIJ):   0.000ns
+    Discrete Jitter (DJ):       0.381ns
+    Phase Error (PE):           0.000ns
+
+  Maximum Data Path at Slow Process Corner: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_flags_12
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    RAMB16_X1Y12.DOA2    Trcko_DOA             1.850   EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
+                                                       EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
+    SLICE_X13Y21.B3      net (fanout=2)        1.098   EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<2>
+    SLICE_X13Y21.B       Tilo                  0.259   BIU_CORE/pfq_addr_out_d1<15>
+                                                       EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux81
+    SLICE_X12Y22.D4      net (fanout=49)       0.520   EU_CORE/eu_rom_data<16>
+    SLICE_X12Y22.BMUX    Topdb                 0.393   EU_CORE/eu_biu_dataout<3>
+                                                       EU_CORE/mux14_6
+                                                       EU_CORE/mux14_4_f7
+                                                       EU_CORE/mux14_2_f8
+    SLICE_X13Y25.D1      net (fanout=5)        0.878   EU_CORE/eu_operand1<8>
+    SLICE_X13Y25.D       Tilo                  0.259   EU_CORE/eu_register_r2<11>
+                                                       EU_CORE/carry<7>1_SW1
+    SLICE_X13Y25.C6      net (fanout=3)        0.132   N147
+    SLICE_X13Y25.C       Tilo                  0.259   EU_CORE/eu_register_r2<11>
+                                                       EU_CORE/carry<9>1_SW1
+    SLICE_X15Y24.C2      net (fanout=1)        0.804   N153
+    SLICE_X15Y24.C       Tilo                  0.259   EU_CORE/eu_alu_last_result<11>
+                                                       EU_CORE/carry<11>1
+    SLICE_X17Y30.A5      net (fanout=7)        0.811   EU_CORE/carry<11>
+    SLICE_X17Y30.A       Tilo                  0.259   EU_CORE/eu_register_r1<15>
+                                                       EU_CORE/Mmux_n045543
+    SLICE_X15Y29.BX      net (fanout=13)       0.648   EU_CORE/n0455<12>
+    SLICE_X15Y29.CLK     Tdick                 0.063   EU_CORE/eu_flags<14>
+                                                       EU_CORE/eu_flags_12
+    -------------------------------------------------  ---------------------------
+    Total                                      8.492ns (3.601ns logic, 4.891ns route)
+                                                       (42.4% logic, 57.6% route)
+
+--------------------------------------------------------------------------------
+Slack (setup path):     0.375ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
+  Destination:          EU_CORE/eu_flags_12 (FF)
+  Requirement:          9.090ns
+  Data Path Delay:      8.485ns (Levels of Logic = 6)
+  Clock Path Skew:      -0.004ns (0.243 - 0.247)
+  Source Clock:         core_clk_int rising at 0.000ns
+  Destination Clock:    core_clk_int rising at 9.090ns
+  Clock Uncertainty:    0.226ns
+
+  Clock Uncertainty:          0.226ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter (TSJ):  0.070ns
+    Total Input Jitter (TIJ):   0.000ns
+    Discrete Jitter (DJ):       0.381ns
+    Phase Error (PE):           0.000ns
+
+  Maximum Data Path at Slow Process Corner: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_flags_12
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    RAMB16_X1Y12.DOA2    Trcko_DOA             1.850   EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
+                                                       EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
+    SLICE_X13Y21.B3      net (fanout=2)        1.098   EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<2>
+    SLICE_X13Y21.B       Tilo                  0.259   BIU_CORE/pfq_addr_out_d1<15>
+                                                       EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux81
+    SLICE_X12Y22.C4      net (fanout=49)       0.520   EU_CORE/eu_rom_data<16>
+    SLICE_X12Y22.BMUX    Topcb                 0.386   EU_CORE/eu_biu_dataout<3>
+                                                       EU_CORE/mux14_51
+                                                       EU_CORE/mux14_4_f7
+                                                       EU_CORE/mux14_2_f8
+    SLICE_X13Y25.D1      net (fanout=5)        0.878   EU_CORE/eu_operand1<8>
+    SLICE_X13Y25.D       Tilo                  0.259   EU_CORE/eu_register_r2<11>
+                                                       EU_CORE/carry<7>1_SW1
+    SLICE_X13Y25.C6      net (fanout=3)        0.132   N147
+    SLICE_X13Y25.C       Tilo                  0.259   EU_CORE/eu_register_r2<11>
+                                                       EU_CORE/carry<9>1_SW1
+    SLICE_X15Y24.C2      net (fanout=1)        0.804   N153
+    SLICE_X15Y24.C       Tilo                  0.259   EU_CORE/eu_alu_last_result<11>
+                                                       EU_CORE/carry<11>1
+    SLICE_X17Y30.A5      net (fanout=7)        0.811   EU_CORE/carry<11>
+    SLICE_X17Y30.A       Tilo                  0.259   EU_CORE/eu_register_r1<15>
+                                                       EU_CORE/Mmux_n045543
+    SLICE_X15Y29.BX      net (fanout=13)       0.648   EU_CORE/n0455<12>
+    SLICE_X15Y29.CLK     Tdick                 0.063   EU_CORE/eu_flags<14>
+                                                       EU_CORE/eu_flags_12
+    -------------------------------------------------  ---------------------------
+    Total                                      8.485ns (3.594ns logic, 4.891ns route)
+                                                       (42.4% logic, 57.6% route)
+
+--------------------------------------------------------------------------------
+
+Paths for end point EU_CORE/eu_alu_last_result_12 (SLICE_X18Y30.AX), 2245 paths
+--------------------------------------------------------------------------------
+Slack (setup path):     0.306ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
+  Destination:          EU_CORE/eu_alu_last_result_12 (FF)
+  Requirement:          9.090ns
+  Data Path Delay:      8.553ns (Levels of Logic = 6)
+  Clock Path Skew:      -0.005ns (0.245 - 0.250)
+  Source Clock:         core_clk_int rising at 0.000ns
+  Destination Clock:    core_clk_int rising at 9.090ns
+  Clock Uncertainty:    0.226ns
+
+  Clock Uncertainty:          0.226ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter (TSJ):  0.070ns
+    Total Input Jitter (TIJ):   0.000ns
+    Discrete Jitter (DJ):       0.381ns
+    Phase Error (PE):           0.000ns
+
+  Maximum Data Path at Slow Process Corner: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_alu_last_result_12
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    RAMB16_X1Y10.DOA5    Trcko_DOA             1.850   EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
+                                                       EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
+    SLICE_X17Y23.B3      net (fanout=1)        1.070   EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<5>
+    SLICE_X17Y23.B       Tilo                  0.259   EU_CORE/eu_register_r0<3>
+                                                       EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux111
+    SLICE_X12Y22.BX      net (fanout=18)       0.850   EU_CORE/eu_rom_data<19>
+    SLICE_X12Y22.BMUX    Tbxb                  0.157   EU_CORE/eu_biu_dataout<3>
+                                                       EU_CORE/mux14_2_f8
+    SLICE_X13Y25.D1      net (fanout=5)        0.878   EU_CORE/eu_operand1<8>
+    SLICE_X13Y25.D       Tilo                  0.259   EU_CORE/eu_register_r2<11>
+                                                       EU_CORE/carry<7>1_SW1
+    SLICE_X13Y25.C6      net (fanout=3)        0.132   N147
+    SLICE_X13Y25.C       Tilo                  0.259   EU_CORE/eu_register_r2<11>
+                                                       EU_CORE/carry<9>1_SW1
+    SLICE_X15Y24.C2      net (fanout=1)        0.804   N153
+    SLICE_X15Y24.C       Tilo                  0.259   EU_CORE/eu_alu_last_result<11>
+                                                       EU_CORE/carry<11>1
+    SLICE_X17Y30.A5      net (fanout=7)        0.811   EU_CORE/carry<11>
+    SLICE_X17Y30.A       Tilo                  0.259   EU_CORE/eu_register_r1<15>
+                                                       EU_CORE/Mmux_n045543
+    SLICE_X18Y30.AX      net (fanout=13)       0.570   EU_CORE/n0455<12>
+    SLICE_X18Y30.CLK     Tdick                 0.136   EU_CORE/eu_alu_last_result<15>
+                                                       EU_CORE/eu_alu_last_result_12
+    -------------------------------------------------  ---------------------------
+    Total                                      8.553ns (3.438ns logic, 5.115ns route)
+                                                       (40.2% logic, 59.8% route)
+
+--------------------------------------------------------------------------------
+Slack (setup path):     0.375ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
+  Destination:          EU_CORE/eu_alu_last_result_12 (FF)
+  Requirement:          9.090ns
+  Data Path Delay:      8.487ns (Levels of Logic = 6)
+  Clock Path Skew:      -0.002ns (0.245 - 0.247)
+  Source Clock:         core_clk_int rising at 0.000ns
+  Destination Clock:    core_clk_int rising at 9.090ns
+  Clock Uncertainty:    0.226ns
+
+  Clock Uncertainty:          0.226ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter (TSJ):  0.070ns
+    Total Input Jitter (TIJ):   0.000ns
+    Discrete Jitter (DJ):       0.381ns
+    Phase Error (PE):           0.000ns
+
+  Maximum Data Path at Slow Process Corner: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_alu_last_result_12
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    RAMB16_X1Y12.DOA2    Trcko_DOA             1.850   EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
+                                                       EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
+    SLICE_X13Y21.B3      net (fanout=2)        1.098   EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<2>
+    SLICE_X13Y21.B       Tilo                  0.259   BIU_CORE/pfq_addr_out_d1<15>
+                                                       EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux81
+    SLICE_X12Y22.D4      net (fanout=49)       0.520   EU_CORE/eu_rom_data<16>
+    SLICE_X12Y22.BMUX    Topdb                 0.393   EU_CORE/eu_biu_dataout<3>
+                                                       EU_CORE/mux14_6
+                                                       EU_CORE/mux14_4_f7
+                                                       EU_CORE/mux14_2_f8
+    SLICE_X13Y25.D1      net (fanout=5)        0.878   EU_CORE/eu_operand1<8>
+    SLICE_X13Y25.D       Tilo                  0.259   EU_CORE/eu_register_r2<11>
+                                                       EU_CORE/carry<7>1_SW1
+    SLICE_X13Y25.C6      net (fanout=3)        0.132   N147
+    SLICE_X13Y25.C       Tilo                  0.259   EU_CORE/eu_register_r2<11>
+                                                       EU_CORE/carry<9>1_SW1
+    SLICE_X15Y24.C2      net (fanout=1)        0.804   N153
+    SLICE_X15Y24.C       Tilo                  0.259   EU_CORE/eu_alu_last_result<11>
+                                                       EU_CORE/carry<11>1
+    SLICE_X17Y30.A5      net (fanout=7)        0.811   EU_CORE/carry<11>
+    SLICE_X17Y30.A       Tilo                  0.259   EU_CORE/eu_register_r1<15>
+                                                       EU_CORE/Mmux_n045543
+    SLICE_X18Y30.AX      net (fanout=13)       0.570   EU_CORE/n0455<12>
+    SLICE_X18Y30.CLK     Tdick                 0.136   EU_CORE/eu_alu_last_result<15>
+                                                       EU_CORE/eu_alu_last_result_12
+    -------------------------------------------------  ---------------------------
+    Total                                      8.487ns (3.674ns logic, 4.813ns route)
+                                                       (43.3% logic, 56.7% route)
+
+--------------------------------------------------------------------------------
+Slack (setup path):     0.382ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
+  Destination:          EU_CORE/eu_alu_last_result_12 (FF)
+  Requirement:          9.090ns
+  Data Path Delay:      8.480ns (Levels of Logic = 6)
+  Clock Path Skew:      -0.002ns (0.245 - 0.247)
+  Source Clock:         core_clk_int rising at 0.000ns
+  Destination Clock:    core_clk_int rising at 9.090ns
+  Clock Uncertainty:    0.226ns
+
+  Clock Uncertainty:          0.226ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter (TSJ):  0.070ns
+    Total Input Jitter (TIJ):   0.000ns
+    Discrete Jitter (DJ):       0.381ns
+    Phase Error (PE):           0.000ns
+
+  Maximum Data Path at Slow Process Corner: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_alu_last_result_12
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    RAMB16_X1Y12.DOA2    Trcko_DOA             1.850   EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
+                                                       EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
+    SLICE_X13Y21.B3      net (fanout=2)        1.098   EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<2>
+    SLICE_X13Y21.B       Tilo                  0.259   BIU_CORE/pfq_addr_out_d1<15>
+                                                       EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux81
+    SLICE_X12Y22.C4      net (fanout=49)       0.520   EU_CORE/eu_rom_data<16>
+    SLICE_X12Y22.BMUX    Topcb                 0.386   EU_CORE/eu_biu_dataout<3>
+                                                       EU_CORE/mux14_51
+                                                       EU_CORE/mux14_4_f7
+                                                       EU_CORE/mux14_2_f8
+    SLICE_X13Y25.D1      net (fanout=5)        0.878   EU_CORE/eu_operand1<8>
+    SLICE_X13Y25.D       Tilo                  0.259   EU_CORE/eu_register_r2<11>
+                                                       EU_CORE/carry<7>1_SW1
+    SLICE_X13Y25.C6      net (fanout=3)        0.132   N147
+    SLICE_X13Y25.C       Tilo                  0.259   EU_CORE/eu_register_r2<11>
+                                                       EU_CORE/carry<9>1_SW1
+    SLICE_X15Y24.C2      net (fanout=1)        0.804   N153
+    SLICE_X15Y24.C       Tilo                  0.259   EU_CORE/eu_alu_last_result<11>
+                                                       EU_CORE/carry<11>1
+    SLICE_X17Y30.A5      net (fanout=7)        0.811   EU_CORE/carry<11>
+    SLICE_X17Y30.A       Tilo                  0.259   EU_CORE/eu_register_r1<15>
+                                                       EU_CORE/Mmux_n045543
+    SLICE_X18Y30.AX      net (fanout=13)       0.570   EU_CORE/n0455<12>
+    SLICE_X18Y30.CLK     Tdick                 0.136   EU_CORE/eu_alu_last_result<15>
+                                                       EU_CORE/eu_alu_last_result_12
+    -------------------------------------------------  ---------------------------
+    Total                                      8.480ns (3.667ns logic, 4.813ns route)
+                                                       (43.2% logic, 56.8% route)
+
+--------------------------------------------------------------------------------
+
+Paths for end point EU_CORE/eu_register_di_12 (SLICE_X17Y27.CX), 2245 paths
+--------------------------------------------------------------------------------
+Slack (setup path):     0.316ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
+  Destination:          EU_CORE/eu_register_di_12 (FF)
+  Requirement:          9.090ns
+  Data Path Delay:      8.538ns (Levels of Logic = 6)
+  Clock Path Skew:      -0.010ns (0.240 - 0.250)
+  Source Clock:         core_clk_int rising at 0.000ns
+  Destination Clock:    core_clk_int rising at 9.090ns
+  Clock Uncertainty:    0.226ns
+
+  Clock Uncertainty:          0.226ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter (TSJ):  0.070ns
+    Total Input Jitter (TIJ):   0.000ns
+    Discrete Jitter (DJ):       0.381ns
+    Phase Error (PE):           0.000ns
+
+  Maximum Data Path at Slow Process Corner: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_register_di_12
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    RAMB16_X1Y10.DOA5    Trcko_DOA             1.850   EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
+                                                       EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
+    SLICE_X17Y23.B3      net (fanout=1)        1.070   EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<5>
+    SLICE_X17Y23.B       Tilo                  0.259   EU_CORE/eu_register_r0<3>
+                                                       EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux111
+    SLICE_X12Y22.BX      net (fanout=18)       0.850   EU_CORE/eu_rom_data<19>
+    SLICE_X12Y22.BMUX    Tbxb                  0.157   EU_CORE/eu_biu_dataout<3>
+                                                       EU_CORE/mux14_2_f8
+    SLICE_X13Y25.D1      net (fanout=5)        0.878   EU_CORE/eu_operand1<8>
+    SLICE_X13Y25.D       Tilo                  0.259   EU_CORE/eu_register_r2<11>
+                                                       EU_CORE/carry<7>1_SW1
+    SLICE_X13Y25.C6      net (fanout=3)        0.132   N147
+    SLICE_X13Y25.C       Tilo                  0.259   EU_CORE/eu_register_r2<11>
+                                                       EU_CORE/carry<9>1_SW1
+    SLICE_X15Y24.C2      net (fanout=1)        0.804   N153
+    SLICE_X15Y24.C       Tilo                  0.259   EU_CORE/eu_alu_last_result<11>
+                                                       EU_CORE/carry<11>1
+    SLICE_X17Y30.A5      net (fanout=7)        0.811   EU_CORE/carry<11>
+    SLICE_X17Y30.A       Tilo                  0.259   EU_CORE/eu_register_r1<15>
+                                                       EU_CORE/Mmux_n045543
+    SLICE_X17Y27.CX      net (fanout=13)       0.628   EU_CORE/n0455<12>
+    SLICE_X17Y27.CLK     Tdick                 0.063   EU_CORE/eu_register_di<12>
+                                                       EU_CORE/eu_register_di_12
+    -------------------------------------------------  ---------------------------
+    Total                                      8.538ns (3.365ns logic, 5.173ns route)
+                                                       (39.4% logic, 60.6% route)
+
+--------------------------------------------------------------------------------
+Slack (setup path):     0.385ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
+  Destination:          EU_CORE/eu_register_di_12 (FF)
+  Requirement:          9.090ns
+  Data Path Delay:      8.472ns (Levels of Logic = 6)
+  Clock Path Skew:      -0.007ns (0.240 - 0.247)
+  Source Clock:         core_clk_int rising at 0.000ns
+  Destination Clock:    core_clk_int rising at 9.090ns
+  Clock Uncertainty:    0.226ns
+
+  Clock Uncertainty:          0.226ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter (TSJ):  0.070ns
+    Total Input Jitter (TIJ):   0.000ns
+    Discrete Jitter (DJ):       0.381ns
+    Phase Error (PE):           0.000ns
+
+  Maximum Data Path at Slow Process Corner: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_register_di_12
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    RAMB16_X1Y12.DOA2    Trcko_DOA             1.850   EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
+                                                       EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
+    SLICE_X13Y21.B3      net (fanout=2)        1.098   EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<2>
+    SLICE_X13Y21.B       Tilo                  0.259   BIU_CORE/pfq_addr_out_d1<15>
+                                                       EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux81
+    SLICE_X12Y22.D4      net (fanout=49)       0.520   EU_CORE/eu_rom_data<16>
+    SLICE_X12Y22.BMUX    Topdb                 0.393   EU_CORE/eu_biu_dataout<3>
+                                                       EU_CORE/mux14_6
+                                                       EU_CORE/mux14_4_f7
+                                                       EU_CORE/mux14_2_f8
+    SLICE_X13Y25.D1      net (fanout=5)        0.878   EU_CORE/eu_operand1<8>
+    SLICE_X13Y25.D       Tilo                  0.259   EU_CORE/eu_register_r2<11>
+                                                       EU_CORE/carry<7>1_SW1
+    SLICE_X13Y25.C6      net (fanout=3)        0.132   N147
+    SLICE_X13Y25.C       Tilo                  0.259   EU_CORE/eu_register_r2<11>
+                                                       EU_CORE/carry<9>1_SW1
+    SLICE_X15Y24.C2      net (fanout=1)        0.804   N153
+    SLICE_X15Y24.C       Tilo                  0.259   EU_CORE/eu_alu_last_result<11>
+                                                       EU_CORE/carry<11>1
+    SLICE_X17Y30.A5      net (fanout=7)        0.811   EU_CORE/carry<11>
+    SLICE_X17Y30.A       Tilo                  0.259   EU_CORE/eu_register_r1<15>
+                                                       EU_CORE/Mmux_n045543
+    SLICE_X17Y27.CX      net (fanout=13)       0.628   EU_CORE/n0455<12>
+    SLICE_X17Y27.CLK     Tdick                 0.063   EU_CORE/eu_register_di<12>
+                                                       EU_CORE/eu_register_di_12
+    -------------------------------------------------  ---------------------------
+    Total                                      8.472ns (3.601ns logic, 4.871ns route)
+                                                       (42.5% logic, 57.5% route)
+
+--------------------------------------------------------------------------------
+Slack (setup path):     0.392ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram (RAM)
+  Destination:          EU_CORE/eu_register_di_12 (FF)
+  Requirement:          9.090ns
+  Data Path Delay:      8.465ns (Levels of Logic = 6)
+  Clock Path Skew:      -0.007ns (0.240 - 0.247)
+  Source Clock:         core_clk_int rising at 0.000ns
+  Destination Clock:    core_clk_int rising at 9.090ns
+  Clock Uncertainty:    0.226ns
+
+  Clock Uncertainty:          0.226ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter (TSJ):  0.070ns
+    Total Input Jitter (TIJ):   0.000ns
+    Discrete Jitter (DJ):       0.381ns
+    Phase Error (PE):           0.000ns
+
+  Maximum Data Path at Slow Process Corner: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram to EU_CORE/eu_register_di_12
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    RAMB16_X1Y12.DOA2    Trcko_DOA             1.850   EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
+                                                       EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram
+    SLICE_X13Y21.B3      net (fanout=2)        1.098   EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<2>
+    SLICE_X13Y21.B       Tilo                  0.259   BIU_CORE/pfq_addr_out_d1<15>
+                                                       EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux81
+    SLICE_X12Y22.C4      net (fanout=49)       0.520   EU_CORE/eu_rom_data<16>
+    SLICE_X12Y22.BMUX    Topcb                 0.386   EU_CORE/eu_biu_dataout<3>
+                                                       EU_CORE/mux14_51
+                                                       EU_CORE/mux14_4_f7
+                                                       EU_CORE/mux14_2_f8
+    SLICE_X13Y25.D1      net (fanout=5)        0.878   EU_CORE/eu_operand1<8>
+    SLICE_X13Y25.D       Tilo                  0.259   EU_CORE/eu_register_r2<11>
+                                                       EU_CORE/carry<7>1_SW1
+    SLICE_X13Y25.C6      net (fanout=3)        0.132   N147
+    SLICE_X13Y25.C       Tilo                  0.259   EU_CORE/eu_register_r2<11>
+                                                       EU_CORE/carry<9>1_SW1
+    SLICE_X15Y24.C2      net (fanout=1)        0.804   N153
+    SLICE_X15Y24.C       Tilo                  0.259   EU_CORE/eu_alu_last_result<11>
+                                                       EU_CORE/carry<11>1
+    SLICE_X17Y30.A5      net (fanout=7)        0.811   EU_CORE/carry<11>
+    SLICE_X17Y30.A       Tilo                  0.259   EU_CORE/eu_register_r1<15>
+                                                       EU_CORE/Mmux_n045543
+    SLICE_X17Y27.CX      net (fanout=13)       0.628   EU_CORE/n0455<12>
+    SLICE_X17Y27.CLK     Tdick                 0.063   EU_CORE/eu_register_di<12>
+                                                       EU_CORE/eu_register_di_12
+    -------------------------------------------------  ---------------------------
+    Total                                      8.465ns (3.594ns logic, 4.871ns route)
+                                                       (42.5% logic, 57.5% route)
+
+--------------------------------------------------------------------------------
+
+Hold Paths: TS_SPARTAN6PLL_clkfx = PERIOD TIMEGRP "SPARTAN6PLL_clkfx" TS_CORE_CLK / 2.2
+        HIGH 50%;
+--------------------------------------------------------------------------------
+
+Paths for end point BIU_CORE/Mshreg_biu_return_data_int_d2_2 (SLICE_X12Y35.BX), 1 path
+--------------------------------------------------------------------------------
+Slack (hold path):      0.367ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               BIU_CORE/biu_return_data_int_2 (FF)
+  Destination:          BIU_CORE/Mshreg_biu_return_data_int_d2_2 (FF)
+  Requirement:          0.000ns
+  Data Path Delay:      0.369ns (Levels of Logic = 0)
+  Clock Path Skew:      0.002ns (0.041 - 0.039)
+  Source Clock:         core_clk_int rising at 0.000ns
+  Destination Clock:    core_clk_int rising at 0.000ns
+  Clock Uncertainty:    0.000ns
+
+  Minimum Data Path at Fast Process Corner: BIU_CORE/biu_return_data_int_2 to BIU_CORE/Mshreg_biu_return_data_int_d2_2
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X13Y35.AQ      Tcko                  0.198   BIU_CORE/biu_return_data_int_5
+                                                       BIU_CORE/biu_return_data_int_2
+    SLICE_X12Y35.BX      net (fanout=2)        0.251   BIU_CORE/biu_return_data_int_2
+    SLICE_X12Y35.CLK     Tdh         (-Th)     0.080   BIU_CORE/biu_return_data_int_d2<5>
+                                                       BIU_CORE/Mshreg_biu_return_data_int_d2_2
+    -------------------------------------------------  ---------------------------
+    Total                                      0.369ns (0.118ns logic, 0.251ns route)
+                                                       (32.0% logic, 68.0% route)
+
+--------------------------------------------------------------------------------
+
+Paths for end point BIU_CORE/Mshreg_biu_register_reg_d2_11 (SLICE_X20Y29.BX), 1 path
+--------------------------------------------------------------------------------
+Slack (hold path):      0.371ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               BIU_CORE/biu_register_reg_11 (FF)
+  Destination:          BIU_CORE/Mshreg_biu_register_reg_d2_11 (FF)
+  Requirement:          0.000ns
+  Data Path Delay:      0.372ns (Levels of Logic = 0)
+  Clock Path Skew:      0.001ns (0.042 - 0.041)
+  Source Clock:         core_clk_int rising at 0.000ns
+  Destination Clock:    core_clk_int rising at 0.000ns
+  Clock Uncertainty:    0.000ns
+
+  Minimum Data Path at Fast Process Corner: BIU_CORE/biu_register_reg_11 to BIU_CORE/Mshreg_biu_register_reg_d2_11
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X20Y30.DQ      Tcko                  0.234   BIU_CORE/biu_register_reg<11>
+                                                       BIU_CORE/biu_register_reg_11
+    SLICE_X20Y29.BX      net (fanout=1)        0.218   BIU_CORE/biu_register_reg<11>
+    SLICE_X20Y29.CLK     Tdh         (-Th)     0.080   BIU_CORE/biu_register_reg_d2<12>
+                                                       BIU_CORE/Mshreg_biu_register_reg_d2_11
+    -------------------------------------------------  ---------------------------
+    Total                                      0.372ns (0.154ns logic, 0.218ns route)
+                                                       (41.4% logic, 58.6% route)
+
+--------------------------------------------------------------------------------
+
+Paths for end point BIU_CORE/Mshreg_biu_register_rm_d2_7 (SLICE_X0Y20.BI), 1 path
+--------------------------------------------------------------------------------
+Slack (hold path):      0.372ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               BIU_CORE/biu_register_rm_7 (FF)
+  Destination:          BIU_CORE/Mshreg_biu_register_rm_d2_7 (FF)
+  Requirement:          0.000ns
+  Data Path Delay:      0.376ns (Levels of Logic = 0)
+  Clock Path Skew:      0.004ns (0.038 - 0.034)
+  Source Clock:         core_clk_int rising at 0.000ns
+  Destination Clock:    core_clk_int rising at 0.000ns
+  Clock Uncertainty:    0.000ns
+
+  Minimum Data Path at Fast Process Corner: BIU_CORE/biu_register_rm_7 to BIU_CORE/Mshreg_biu_register_rm_d2_7
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X0Y21.DQ       Tcko                  0.234   BIU_CORE/biu_register_rm<7>
+                                                       BIU_CORE/biu_register_rm_7
+    SLICE_X0Y20.BI       net (fanout=1)        0.113   BIU_CORE/biu_register_rm<7>
+    SLICE_X0Y20.CLK      Tdh         (-Th)    -0.029   BIU_CORE/biu_register_rm_d2<4>
+                                                       BIU_CORE/Mshreg_biu_register_rm_d2_7
+    -------------------------------------------------  ---------------------------
+    Total                                      0.376ns (0.263ns logic, 0.113ns route)
+                                                       (69.9% logic, 30.1% route)
+
+--------------------------------------------------------------------------------
+
+Component Switching Limit Checks: TS_SPARTAN6PLL_clkfx = PERIOD TIMEGRP "SPARTAN6PLL_clkfx" TS_CORE_CLK / 2.2
+        HIGH 50%;
+--------------------------------------------------------------------------------
+Slack: 5.966ns (period - min period limit)
+  Period: 9.090ns
+  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
+  Physical resource: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA
+  Logical resource: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA
+  Location pin: RAMB16_X1Y14.CLKA
+  Clock network: core_clk_int
+--------------------------------------------------------------------------------
+Slack: 5.966ns (period - min period limit)
+  Period: 9.090ns
+  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
+  Physical resource: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA
+  Logical resource: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA
+  Location pin: RAMB16_X1Y10.CLKA
+  Clock network: core_clk_int
+--------------------------------------------------------------------------------
+Slack: 5.966ns (period - min period limit)
+  Period: 9.090ns
+  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
+  Physical resource: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA
+  Logical resource: EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA
+  Location pin: RAMB16_X0Y12.CLKA
+  Clock network: core_clk_int
+--------------------------------------------------------------------------------
+
+
+Derived Constraint Report
+Derived Constraints for TS_CORE_CLK
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
+|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
+|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+|TS_CORE_CLK                    |     20.000ns|      8.000ns|     19.340ns|            0|            0|            0|       513828|
+| TS_SPARTAN6PLL_clkfx          |      9.091ns|      8.791ns|          N/A|            0|            0|       513828|            0|
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+
+All constraints were met.
+
+
+Data Sheet report:
+-----------------
+All values displayed in nanoseconds (ns)
+
+Clock to Setup on destination clock CORE_CLK
+---------------+---------+---------+---------+---------+
+               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
+Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
+---------------+---------+---------+---------+---------+
+CORE_CLK       |    8.791|         |         |         |
+---------------+---------+---------+---------+---------+
+
+
+Timing summary:
+---------------
+
+Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)
+
+Constraints cover 513828 paths, 0 nets, and 5708 connections
+
+Design statistics:
+   Minimum period:   8.791ns{1}   (Maximum frequency: 113.753MHz)
+
+
+------------------------------------Footnotes-----------------------------------
+1)  The minimum period statistic assumes all single cycle delays.
+
+Analysis completed Wed Nov 11 19:11:41 2020 
+--------------------------------------------------------------------------------
+
+Trace Settings:
+-------------------------
+Trace Settings 
+
+Peak Memory Usage: 236 MB
+
+
+
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.twx b/MCL86jr/FPGA/MCL86jr/MCL86jr.twx
new file mode 100644
index 0000000..3b47ca2
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.twx
@@ -0,0 +1,348 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE twReport [
+<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
+					twDebug*, twFoot?, twClientInfo?)>
+<!ATTLIST twReport version CDATA "10,4">
+<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
+<!ELEMENT twExecVer (#PCDATA)>
+<!ELEMENT twCopyright (#PCDATA)>
+<!ELEMENT twCmdLine (#PCDATA)>
+<!ELEMENT twDesign (#PCDATA)>
+<!ELEMENT twPCF (#PCDATA)>
+<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
+<!ELEMENT twDevName (#PCDATA)>
+<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
+<!ELEMENT twSpeedGrade (#PCDATA)>
+<!ELEMENT twSpeedVer (#PCDATA)>
+<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
+<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
+<!ATTLIST twRptInfo twAdvRpt  (TRUE | FALSE) "FALSE">
+<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
+<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
+<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
+<!ELEMENT twItemLimit (#PCDATA)>
+<!ELEMENT twUnconst EMPTY>
+<!ELEMENT twUnconstLimit (#PCDATA)>
+<!ELEMENT twEnvVar EMPTY>
+<!ATTLIST twEnvVar name CDATA #REQUIRED>
+<!ATTLIST twEnvVar description CDATA #REQUIRED>
+<!ELEMENT twWarn (#PCDATA)>
+<!ELEMENT twInfo (#PCDATA)>
+<!ELEMENT twDebug (#PCDATA)>
+<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
+<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
+<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
+<!ELEMENT twProc (#PCDATA)>
+<!ELEMENT twTemp (#PCDATA)>
+<!ELEMENT twVolt (#PCDATA)>
+<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
+<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG |  twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
+<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
+<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)> 
+<!ELEMENT twCycles (twSigConn+)>
+<!ATTLIST twCycles twNum CDATA #REQUIRED>
+<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
+<!ELEMENT twSig (#PCDATA)>
+<!ELEMENT twDriver (#PCDATA)>
+<!ELEMENT twLoad (#PCDATA)> 
+<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* |  (twPathRpt*, twRacePathRpt?) |  twNetRpt* | twClkSkewLimit*))>
+<!ATTLIST twConst twConstType (NET | 
+							   NETDELAY | 
+							   NETSKEW | 
+							   PATH |
+							   DEFPERIOD |
+							   UNCONSTPATH |
+							   DEFPATH | 
+							   PATH2SETUP |
+							   UNCONSTPATH2SETUP | 
+							   PATHCLASS | 
+							   PATHDELAY | 
+							   PERIOD |
+							   FREQUENCY |
+							   PATHBLOCK |
+							   OFFSET |
+							   OFFSETIN |
+							   OFFSETINCLOCK | 
+							   UNCONSTOFFSETINCLOCK |
+							   OFFSETINDELAY |
+							   OFFSETINMOD |
+							   OFFSETOUT |
+							   OFFSETOUTCLOCK |
+							   UNCONSTOFFSETOUTCLOCK | 
+							   OFFSETOUTDELAY |
+							   OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED> 
+<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
+					   twEndPtCnt?,
+					   twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
+<!ELEMENT twConstName (#PCDATA)>
+<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
+<!ATTLIST twConstHead uID CDATA #IMPLIED>
+<!ELEMENT twItemCnt (#PCDATA)>
+<!ELEMENT twErrCnt (#PCDATA)>
+<!ELEMENT twErrCntEndPt (#PCDATA)>
+<!ELEMENT twErrCntSetup (#PCDATA)>
+<!ELEMENT twErrCntHold (#PCDATA)>
+<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
+<!ELEMENT twEndPtCnt (#PCDATA)>
+<!ELEMENT twPathErrCnt (#PCDATA)>
+<!ELEMENT twMinPer (#PCDATA) >
+<!ELEMENT twFootnote EMPTY>
+<!ATTLIST twFootnote number CDATA #REQUIRED>
+<!ELEMENT twMaxDel (#PCDATA)>
+<!ELEMENT twMaxFreq (#PCDATA)>
+<!ELEMENT twMinOff (#PCDATA)>
+<!ELEMENT twMaxOff (#PCDATA)>
+<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
+<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
+<!ELEMENT twTIGName (#PCDATA)>
+<!ELEMENT twInstantiated (#PCDATA)>
+<!ELEMENT twBlocked (#PCDATA)>
+<!ELEMENT twRacePathRpt (twRacePath+)>
+<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
+<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest,  (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
+<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
+						twSimpleMinPath CDATA #IMPLIED>
+<!ELEMENT twTotDel (#PCDATA)>
+<!ELEMENT twSrc (#PCDATA)>
+<!ATTLIST twSrc BELType CDATA #IMPLIED>
+<!ELEMENT twDest (#PCDATA)>
+<!ATTLIST twDest BELType CDATA #IMPLIED>
+<!ELEMENT twDel (#PCDATA)>
+<!ELEMENT twSUTime (#PCDATA)>
+<!ELEMENT twTotPathDel (#PCDATA)>
+<!ELEMENT twClkSkew (#PCDATA)>
+<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
+<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
+<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
+<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
+<!ELEMENT twSlack (#PCDATA)>
+<!ELEMENT twDelConst (#PCDATA)>
+<!ELEMENT tw2Phase EMPTY>
+<!ELEMENT twClkUncert (#PCDATA)>
+<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED  fInputJit CDATA #IMPLIED
+					  fDCMJit CDATA #IMPLIED
+					  fPhaseErr CDATA #IMPLIED
+					  sEqu CDATA #IMPLIED>
+<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
+<!ELEMENT twPathRptBanner (#PCDATA)>
+<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
+<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
+<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
+<!ELEMENT twOff (#PCDATA)>
+<!ELEMENT twGuaranteed EMPTY>
+<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
+<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
+<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
+<!ELEMENT twClkDel (#PCDATA)>
+<!ELEMENT twClkSrc (#PCDATA)>
+<!ELEMENT twClkDest (#PCDATA)>
+<!ELEMENT twGuarInSetup (#PCDATA)>
+<!ELEMENT twOffSrc (#PCDATA)>
+<!ELEMENT twOffDest (#PCDATA)>
+<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
+<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
+<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
+<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
+<!ELEMENT twDataDel (#PCDATA)>
+<!ELEMENT twDataSrc (#PCDATA)>
+<!ELEMENT twDataDest (#PCDATA)>
+<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
+<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
+<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
+<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
+<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
+<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
+<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
+<!ELEMENT twLogLvls (#PCDATA)>
+<!ELEMENT twSrcSite (#PCDATA)>
+<!ELEMENT twSrcClk (#PCDATA)>
+<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
+<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
+<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
+<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
+<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
+<!ELEMENT twDelInfo (#PCDATA)>
+<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
+<!ELEMENT twSite (#PCDATA)>
+<!ELEMENT twDelType (#PCDATA)>
+<!ELEMENT twFanCnt (#PCDATA)>
+<!ELEMENT twComp (#PCDATA)>
+<!ELEMENT twNet (#PCDATA)>
+<!ELEMENT twBEL (#PCDATA)>
+<!ELEMENT twLogDel (#PCDATA)>
+<!ELEMENT twRouteDel (#PCDATA)>
+<!ELEMENT twDestClk (#PCDATA)>
+<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
+<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
+<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
+<!ELEMENT twPctLog (#PCDATA)>
+<!ELEMENT twPctRoute (#PCDATA)>
+<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
+<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
+<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
+<!ELEMENT twTimeConst (#PCDATA)>
+<!ELEMENT twAbsSlack (#PCDATA)>
+<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
+<!ELEMENT twSkew (#PCDATA)>
+<!ELEMENT twDetNet (twNetDel*)>
+<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
+<!ELEMENT twNetDelInfo (#PCDATA)>
+<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
+<!ELEMENT twDetSkewNet (twNetSkew*)>
+<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
+<!ELEMENT twClkSkewLimit  EMPTY>
+<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED                      arrv1 CDATA #IMPLIED
+		         arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
+<!ELEMENT twConstRollupTable (twConstRollup*)>
+<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
+<!ELEMENT twConstRollup  EMPTY>
+<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED                      requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
+<!ATTLIST twConstRollup  actualRollup CDATA #IMPLIED                      errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED                      itemsRollup CDATA #IMPLIED>
+<!ELEMENT twConstList (twConstListItem)*>
+<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)> 
+<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
+<!ELEMENT twNotMet EMPTY>
+<!ELEMENT twReqVal (#PCDATA)>
+<!ELEMENT twActVal (#PCDATA)>
+<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
+<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
+<!ELEMENT twConstStats (twConstName)>
+<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
+<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
+<!ATTLIST twConstStats twActual CDATA #IMPLIED>
+<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
+<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
+<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
+<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
+<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
+<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
+<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
+<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED  slackIndex CDATA #IMPLIED>
+<!ELEMENT twConstData EMPTY>
+<!ATTLIST twConstData type CDATA #IMPLIED  units (MHz | ns) "ns" slack CDATA #IMPLIED
+					  best CDATA #IMPLIED requested CDATA #IMPLIED
+					  errors CDATA #IMPLIED
+					  score CDATA #IMPLIED>
+<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
+<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
+<!ELEMENT twTimeGrpName (#PCDATA)>
+<!ELEMENT twCompList (twCompName+)>
+<!ELEMENT twCompName (#PCDATA)>
+<!ELEMENT twSigList (twSigName+)>
+<!ELEMENT twSigName (#PCDATA)>
+<!ELEMENT twBELList (twBELName+)>
+<!ELEMENT twBELName (#PCDATA)>
+<!ELEMENT twBlockList (twBlockName+)>
+<!ELEMENT twBlockName (#PCDATA)>
+<!ELEMENT twMacList (twMacName+)>
+<!ELEMENT twMacName (#PCDATA)>
+<!ELEMENT twPinList (twPinName+)>
+<!ELEMENT twPinName (#PCDATA)>
+<!ELEMENT twUnmetConstCnt (#PCDATA)>
+<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
+<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
+<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
+<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
+<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
+<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)> 
+<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
+<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
+<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
+<!ELEMENT twSU2ClkTime (#PCDATA)>
+<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ELEMENT twH2ClkTime (#PCDATA)>
+<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
+<!ELEMENT twClk2Pad (twDest, twTime)>
+<!ELEMENT twTime (#PCDATA)>
+<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
+<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
+<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
+<!ELEMENT twClk2Out EMPTY>
+<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
+<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
+<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
+<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
+<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
+<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
+<!ELEMENT twRiseRise (#PCDATA)>
+<!ELEMENT twFallRise (#PCDATA)>
+<!ELEMENT twRiseFall (#PCDATA)>
+<!ELEMENT twFallFall (#PCDATA)>
+<!ELEMENT twPad2PadList (twPad2Pad+)>
+<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
+<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
+<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
+<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
+<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
+<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
+<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
+<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
+<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
+<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
+<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
+<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>       
+<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
+<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED  twHoldSlack CDATA #IMPLIED>
+<!ELEMENT twOffOutTblRow EMPTY>
+<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
+<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
+<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
+<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
+<!ELEMENT twNonDedClk (#PCDATA)>
+<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
+<!ELEMENT twScore (#PCDATA)>
+<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
+<!ELEMENT twPathCnt (#PCDATA)>
+<!ELEMENT twNetCnt (#PCDATA)>
+<!ELEMENT twConnCnt (#PCDATA)>
+<!ELEMENT twPct (#PCDATA)>
+<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
+<!ELEMENT twMaxCombDel (#PCDATA)>
+<!ELEMENT twMaxFromToDel (#PCDATA)>
+<!ELEMENT twMaxNetDel (#PCDATA)>
+<!ELEMENT twMaxNetSkew (#PCDATA)>
+<!ELEMENT twMaxInAfterClk (#PCDATA)>
+<!ELEMENT twMinInBeforeClk (#PCDATA)>
+<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
+<!ELEMENT twMinOutAfterClk (#PCDATA)>
+<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
+<!ELEMENT twTimestamp (#PCDATA)>
+<!ELEMENT twFootnoteExplanation EMPTY>
+<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
+<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
+<!ELEMENT twClientInfo (twClientName, twAttrList?)>
+<!ELEMENT twClientName (#PCDATA)>
+<!ELEMENT twAttrList (twAttrListItem)*>
+<!ELEMENT twAttrListItem (twName, twValue*)>
+<!ELEMENT twName (#PCDATA)>
+<!ELEMENT twValue (#PCDATA)>
+]>
+<twReport><twHead anchorID="1"><twExecVer>Release 14.7 Trace  (nt64)</twExecVer><twCopyright>Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3
+-n 3 -fastpaths -xml MCL86jr.twx MCL86jr.ncd -o MCL86jr.twr MCL86jr.pcf -ucf
+MCL86jr.ucf
+
+</twCmdLine><twDesign>MCL86jr.ncd</twDesign><twDesignPath>MCL86jr.ncd</twDesignPath><twPCF>MCL86jr.pcf</twPCF><twPcfPath>MCL86jr.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="tqg144"><twDevName>xc6slx9</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-3</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true"  dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="5" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="TIMESPEC TS_CORE_CLK = PERIOD &quot;CORE_CLK&quot; 20 ns HIGH 50 %;" ScopeName="">TS_CORE_CLK = PERIOD TIMEGRP &quot;CORE_CLK&quot; 20 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>8.000</twMinPer></twConstHead><twPinLimitRpt anchorID="6"><twPinLimitBanner>Component Switching Limit Checks: TS_CORE_CLK = PERIOD TIMEGRP &quot;CORE_CLK&quot; 20 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="7" type="MINPERIOD" name="Tdcmper_CLKFX" slack="6.421" period="9.091" constraintValue="9.091" deviceLimit="2.670" freqLimit="374.532" physResource="SPARTAN6PLL/dcm_sp_inst/CLKFX" logResource="SPARTAN6PLL/dcm_sp_inst/CLKFX" locationPin="DCM_X0Y1.CLKFX" clockNet="SPARTAN6PLL/clkfx"/><twPinLimit anchorID="8" type="MINLOWPULSE" name="Tdcmpw_CLKIN_50_100" slack="12.000" period="20.000" constraintValue="10.000" deviceLimit="4.000" physResource="SPARTAN6PLL/dcm_sp_inst/CLKIN" logResource="SPARTAN6PLL/dcm_sp_inst/CLKIN" locationPin="DCM_X0Y1.CLKIN" clockNet="SPARTAN6PLL/dcm_sp_inst_ML_NEW_DIVCLK"/><twPinLimit anchorID="9" type="MINHIGHPULSE" name="Tdcmpw_CLKIN_50_100" slack="12.000" period="20.000" constraintValue="10.000" deviceLimit="4.000" physResource="SPARTAN6PLL/dcm_sp_inst/CLKIN" logResource="SPARTAN6PLL/dcm_sp_inst/CLKIN" locationPin="DCM_X0Y1.CLKIN" clockNet="SPARTAN6PLL/dcm_sp_inst_ML_NEW_DIVCLK"/></twPinLimitRpt></twConst><twConst anchorID="10" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="TIMESPEC TS_CORE_CLK = PERIOD &quot;CORE_CLK&quot; 20 ns HIGH 50 %;" ScopeName="">TS_SPARTAN6PLL_clkfx = PERIOD TIMEGRP &quot;SPARTAN6PLL_clkfx&quot; TS_CORE_CLK / 2.2         HIGH 50%;</twConstName><twItemCnt>513828</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>3870</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>8.791</twMinPer></twConstHead><twPathRptBanner iPaths="2245" iCriticalPaths="0" sType="EndPoint">Paths for end point EU_CORE/eu_flags_12 (SLICE_X15Y29.BX), 2245 paths
+</twPathRptBanner><twPathRpt anchorID="11"><twConstPath anchorID="12" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.299</twSlack><twSrc BELType="RAM">EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twSrc><twDest BELType="FF">EU_CORE/eu_flags_12</twDest><twTotPathDel>8.558</twTotPathDel><twClkSkew dest = "0.243" src = "0.250">0.007</twClkSkew><twDelConst>9.090</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.381" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.226</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twSrc><twDest BELType='FF'>EU_CORE/eu_flags_12</twDest><twLogLvls>6</twLogLvls><twSrcSite>RAMB16_X1Y10.CLKA</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">core_clk_int</twSrcClk><twPathDel><twSite>RAMB16_X1Y10.DOA5</twSite><twDelType>Trcko_DOA</twDelType><twDelInfo twEdge="twRising">1.850</twDelInfo><twComp>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twComp><twBEL>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y23.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.070</twDelInfo><twComp>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta&lt;5&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y23.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r0&lt;3&gt;</twComp><twBEL>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux111</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y22.BX</twSite><twDelType>net</twDelType><twFanCnt>18</twFanCnt><twDelInfo twEdge="twRising">0.850</twDelInfo><twComp>EU_CORE/eu_rom_data&lt;19&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y22.BMUX</twSite><twDelType>Tbxb</twDelType><twDelInfo twEdge="twRising">0.157</twDelInfo><twComp>EU_CORE/eu_biu_dataout&lt;3&gt;</twComp><twBEL>EU_CORE/mux14_2_f8</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y25.D1</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.878</twDelInfo><twComp>EU_CORE/eu_operand1&lt;8&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y25.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r2&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;7&gt;1_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y25.C6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.132</twDelInfo><twComp>N147</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y25.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r2&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;9&gt;1_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y24.C2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.804</twDelInfo><twComp>N153</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y24.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_alu_last_result&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;11&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y30.A5</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.811</twDelInfo><twComp>EU_CORE/carry&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y30.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r1&lt;15&gt;</twComp><twBEL>EU_CORE/Mmux_n045543</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y29.BX</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twRising">0.648</twDelInfo><twComp>EU_CORE/n0455&lt;12&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y29.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.063</twDelInfo><twComp>EU_CORE/eu_flags&lt;14&gt;</twComp><twBEL>EU_CORE/eu_flags_12</twBEL></twPathDel><twLogDel>3.365</twLogDel><twRouteDel>5.193</twRouteDel><twTotDel>8.558</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="9.090">core_clk_int</twDestClk><twPctLog>39.3</twPctLog><twPctRoute>60.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="13"><twConstPath anchorID="14" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.368</twSlack><twSrc BELType="RAM">EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twSrc><twDest BELType="FF">EU_CORE/eu_flags_12</twDest><twTotPathDel>8.492</twTotPathDel><twClkSkew dest = "0.243" src = "0.247">0.004</twClkSkew><twDelConst>9.090</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.381" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.226</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twSrc><twDest BELType='FF'>EU_CORE/eu_flags_12</twDest><twLogLvls>6</twLogLvls><twSrcSite>RAMB16_X1Y12.CLKA</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">core_clk_int</twSrcClk><twPathDel><twSite>RAMB16_X1Y12.DOA2</twSite><twDelType>Trcko_DOA</twDelType><twDelInfo twEdge="twRising">1.850</twDelInfo><twComp>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twComp><twBEL>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y21.B3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.098</twDelInfo><twComp>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y21.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>BIU_CORE/pfq_addr_out_d1&lt;15&gt;</twComp><twBEL>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux81</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y22.D4</twSite><twDelType>net</twDelType><twFanCnt>49</twFanCnt><twDelInfo twEdge="twRising">0.520</twDelInfo><twComp>EU_CORE/eu_rom_data&lt;16&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y22.BMUX</twSite><twDelType>Topdb</twDelType><twDelInfo twEdge="twRising">0.393</twDelInfo><twComp>EU_CORE/eu_biu_dataout&lt;3&gt;</twComp><twBEL>EU_CORE/mux14_6</twBEL><twBEL>EU_CORE/mux14_4_f7</twBEL><twBEL>EU_CORE/mux14_2_f8</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y25.D1</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.878</twDelInfo><twComp>EU_CORE/eu_operand1&lt;8&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y25.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r2&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;7&gt;1_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y25.C6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.132</twDelInfo><twComp>N147</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y25.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r2&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;9&gt;1_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y24.C2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.804</twDelInfo><twComp>N153</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y24.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_alu_last_result&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;11&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y30.A5</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.811</twDelInfo><twComp>EU_CORE/carry&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y30.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r1&lt;15&gt;</twComp><twBEL>EU_CORE/Mmux_n045543</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y29.BX</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twRising">0.648</twDelInfo><twComp>EU_CORE/n0455&lt;12&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y29.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.063</twDelInfo><twComp>EU_CORE/eu_flags&lt;14&gt;</twComp><twBEL>EU_CORE/eu_flags_12</twBEL></twPathDel><twLogDel>3.601</twLogDel><twRouteDel>4.891</twRouteDel><twTotDel>8.492</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="9.090">core_clk_int</twDestClk><twPctLog>42.4</twPctLog><twPctRoute>57.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="15"><twConstPath anchorID="16" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.375</twSlack><twSrc BELType="RAM">EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twSrc><twDest BELType="FF">EU_CORE/eu_flags_12</twDest><twTotPathDel>8.485</twTotPathDel><twClkSkew dest = "0.243" src = "0.247">0.004</twClkSkew><twDelConst>9.090</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.381" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.226</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twSrc><twDest BELType='FF'>EU_CORE/eu_flags_12</twDest><twLogLvls>6</twLogLvls><twSrcSite>RAMB16_X1Y12.CLKA</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">core_clk_int</twSrcClk><twPathDel><twSite>RAMB16_X1Y12.DOA2</twSite><twDelType>Trcko_DOA</twDelType><twDelInfo twEdge="twRising">1.850</twDelInfo><twComp>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twComp><twBEL>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y21.B3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.098</twDelInfo><twComp>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y21.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>BIU_CORE/pfq_addr_out_d1&lt;15&gt;</twComp><twBEL>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux81</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y22.C4</twSite><twDelType>net</twDelType><twFanCnt>49</twFanCnt><twDelInfo twEdge="twRising">0.520</twDelInfo><twComp>EU_CORE/eu_rom_data&lt;16&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y22.BMUX</twSite><twDelType>Topcb</twDelType><twDelInfo twEdge="twRising">0.386</twDelInfo><twComp>EU_CORE/eu_biu_dataout&lt;3&gt;</twComp><twBEL>EU_CORE/mux14_51</twBEL><twBEL>EU_CORE/mux14_4_f7</twBEL><twBEL>EU_CORE/mux14_2_f8</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y25.D1</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.878</twDelInfo><twComp>EU_CORE/eu_operand1&lt;8&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y25.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r2&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;7&gt;1_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y25.C6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.132</twDelInfo><twComp>N147</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y25.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r2&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;9&gt;1_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y24.C2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.804</twDelInfo><twComp>N153</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y24.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_alu_last_result&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;11&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y30.A5</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.811</twDelInfo><twComp>EU_CORE/carry&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y30.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r1&lt;15&gt;</twComp><twBEL>EU_CORE/Mmux_n045543</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y29.BX</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twRising">0.648</twDelInfo><twComp>EU_CORE/n0455&lt;12&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y29.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.063</twDelInfo><twComp>EU_CORE/eu_flags&lt;14&gt;</twComp><twBEL>EU_CORE/eu_flags_12</twBEL></twPathDel><twLogDel>3.594</twLogDel><twRouteDel>4.891</twRouteDel><twTotDel>8.485</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="9.090">core_clk_int</twDestClk><twPctLog>42.4</twPctLog><twPctRoute>57.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="2245" iCriticalPaths="0" sType="EndPoint">Paths for end point EU_CORE/eu_alu_last_result_12 (SLICE_X18Y30.AX), 2245 paths
+</twPathRptBanner><twPathRpt anchorID="17"><twConstPath anchorID="18" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.306</twSlack><twSrc BELType="RAM">EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twSrc><twDest BELType="FF">EU_CORE/eu_alu_last_result_12</twDest><twTotPathDel>8.553</twTotPathDel><twClkSkew dest = "0.245" src = "0.250">0.005</twClkSkew><twDelConst>9.090</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.381" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.226</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twSrc><twDest BELType='FF'>EU_CORE/eu_alu_last_result_12</twDest><twLogLvls>6</twLogLvls><twSrcSite>RAMB16_X1Y10.CLKA</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">core_clk_int</twSrcClk><twPathDel><twSite>RAMB16_X1Y10.DOA5</twSite><twDelType>Trcko_DOA</twDelType><twDelInfo twEdge="twRising">1.850</twDelInfo><twComp>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twComp><twBEL>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y23.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.070</twDelInfo><twComp>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta&lt;5&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y23.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r0&lt;3&gt;</twComp><twBEL>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux111</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y22.BX</twSite><twDelType>net</twDelType><twFanCnt>18</twFanCnt><twDelInfo twEdge="twRising">0.850</twDelInfo><twComp>EU_CORE/eu_rom_data&lt;19&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y22.BMUX</twSite><twDelType>Tbxb</twDelType><twDelInfo twEdge="twRising">0.157</twDelInfo><twComp>EU_CORE/eu_biu_dataout&lt;3&gt;</twComp><twBEL>EU_CORE/mux14_2_f8</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y25.D1</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.878</twDelInfo><twComp>EU_CORE/eu_operand1&lt;8&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y25.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r2&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;7&gt;1_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y25.C6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.132</twDelInfo><twComp>N147</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y25.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r2&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;9&gt;1_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y24.C2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.804</twDelInfo><twComp>N153</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y24.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_alu_last_result&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;11&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y30.A5</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.811</twDelInfo><twComp>EU_CORE/carry&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y30.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r1&lt;15&gt;</twComp><twBEL>EU_CORE/Mmux_n045543</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y30.AX</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twRising">0.570</twDelInfo><twComp>EU_CORE/n0455&lt;12&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X18Y30.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.136</twDelInfo><twComp>EU_CORE/eu_alu_last_result&lt;15&gt;</twComp><twBEL>EU_CORE/eu_alu_last_result_12</twBEL></twPathDel><twLogDel>3.438</twLogDel><twRouteDel>5.115</twRouteDel><twTotDel>8.553</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="9.090">core_clk_int</twDestClk><twPctLog>40.2</twPctLog><twPctRoute>59.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="19"><twConstPath anchorID="20" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.375</twSlack><twSrc BELType="RAM">EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twSrc><twDest BELType="FF">EU_CORE/eu_alu_last_result_12</twDest><twTotPathDel>8.487</twTotPathDel><twClkSkew dest = "0.245" src = "0.247">0.002</twClkSkew><twDelConst>9.090</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.381" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.226</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twSrc><twDest BELType='FF'>EU_CORE/eu_alu_last_result_12</twDest><twLogLvls>6</twLogLvls><twSrcSite>RAMB16_X1Y12.CLKA</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">core_clk_int</twSrcClk><twPathDel><twSite>RAMB16_X1Y12.DOA2</twSite><twDelType>Trcko_DOA</twDelType><twDelInfo twEdge="twRising">1.850</twDelInfo><twComp>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twComp><twBEL>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y21.B3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.098</twDelInfo><twComp>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y21.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>BIU_CORE/pfq_addr_out_d1&lt;15&gt;</twComp><twBEL>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux81</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y22.D4</twSite><twDelType>net</twDelType><twFanCnt>49</twFanCnt><twDelInfo twEdge="twRising">0.520</twDelInfo><twComp>EU_CORE/eu_rom_data&lt;16&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y22.BMUX</twSite><twDelType>Topdb</twDelType><twDelInfo twEdge="twRising">0.393</twDelInfo><twComp>EU_CORE/eu_biu_dataout&lt;3&gt;</twComp><twBEL>EU_CORE/mux14_6</twBEL><twBEL>EU_CORE/mux14_4_f7</twBEL><twBEL>EU_CORE/mux14_2_f8</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y25.D1</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.878</twDelInfo><twComp>EU_CORE/eu_operand1&lt;8&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y25.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r2&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;7&gt;1_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y25.C6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.132</twDelInfo><twComp>N147</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y25.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r2&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;9&gt;1_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y24.C2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.804</twDelInfo><twComp>N153</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y24.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_alu_last_result&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;11&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y30.A5</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.811</twDelInfo><twComp>EU_CORE/carry&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y30.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r1&lt;15&gt;</twComp><twBEL>EU_CORE/Mmux_n045543</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y30.AX</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twRising">0.570</twDelInfo><twComp>EU_CORE/n0455&lt;12&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X18Y30.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.136</twDelInfo><twComp>EU_CORE/eu_alu_last_result&lt;15&gt;</twComp><twBEL>EU_CORE/eu_alu_last_result_12</twBEL></twPathDel><twLogDel>3.674</twLogDel><twRouteDel>4.813</twRouteDel><twTotDel>8.487</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="9.090">core_clk_int</twDestClk><twPctLog>43.3</twPctLog><twPctRoute>56.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="21"><twConstPath anchorID="22" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.382</twSlack><twSrc BELType="RAM">EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twSrc><twDest BELType="FF">EU_CORE/eu_alu_last_result_12</twDest><twTotPathDel>8.480</twTotPathDel><twClkSkew dest = "0.245" src = "0.247">0.002</twClkSkew><twDelConst>9.090</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.381" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.226</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twSrc><twDest BELType='FF'>EU_CORE/eu_alu_last_result_12</twDest><twLogLvls>6</twLogLvls><twSrcSite>RAMB16_X1Y12.CLKA</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">core_clk_int</twSrcClk><twPathDel><twSite>RAMB16_X1Y12.DOA2</twSite><twDelType>Trcko_DOA</twDelType><twDelInfo twEdge="twRising">1.850</twDelInfo><twComp>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twComp><twBEL>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y21.B3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.098</twDelInfo><twComp>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y21.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>BIU_CORE/pfq_addr_out_d1&lt;15&gt;</twComp><twBEL>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux81</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y22.C4</twSite><twDelType>net</twDelType><twFanCnt>49</twFanCnt><twDelInfo twEdge="twRising">0.520</twDelInfo><twComp>EU_CORE/eu_rom_data&lt;16&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y22.BMUX</twSite><twDelType>Topcb</twDelType><twDelInfo twEdge="twRising">0.386</twDelInfo><twComp>EU_CORE/eu_biu_dataout&lt;3&gt;</twComp><twBEL>EU_CORE/mux14_51</twBEL><twBEL>EU_CORE/mux14_4_f7</twBEL><twBEL>EU_CORE/mux14_2_f8</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y25.D1</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.878</twDelInfo><twComp>EU_CORE/eu_operand1&lt;8&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y25.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r2&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;7&gt;1_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y25.C6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.132</twDelInfo><twComp>N147</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y25.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r2&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;9&gt;1_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y24.C2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.804</twDelInfo><twComp>N153</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y24.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_alu_last_result&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;11&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y30.A5</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.811</twDelInfo><twComp>EU_CORE/carry&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y30.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r1&lt;15&gt;</twComp><twBEL>EU_CORE/Mmux_n045543</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y30.AX</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twRising">0.570</twDelInfo><twComp>EU_CORE/n0455&lt;12&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X18Y30.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.136</twDelInfo><twComp>EU_CORE/eu_alu_last_result&lt;15&gt;</twComp><twBEL>EU_CORE/eu_alu_last_result_12</twBEL></twPathDel><twLogDel>3.667</twLogDel><twRouteDel>4.813</twRouteDel><twTotDel>8.480</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="9.090">core_clk_int</twDestClk><twPctLog>43.2</twPctLog><twPctRoute>56.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="2245" iCriticalPaths="0" sType="EndPoint">Paths for end point EU_CORE/eu_register_di_12 (SLICE_X17Y27.CX), 2245 paths
+</twPathRptBanner><twPathRpt anchorID="23"><twConstPath anchorID="24" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.316</twSlack><twSrc BELType="RAM">EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twSrc><twDest BELType="FF">EU_CORE/eu_register_di_12</twDest><twTotPathDel>8.538</twTotPathDel><twClkSkew dest = "0.240" src = "0.250">0.010</twClkSkew><twDelConst>9.090</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.381" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.226</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twSrc><twDest BELType='FF'>EU_CORE/eu_register_di_12</twDest><twLogLvls>6</twLogLvls><twSrcSite>RAMB16_X1Y10.CLKA</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">core_clk_int</twSrcClk><twPathDel><twSite>RAMB16_X1Y10.DOA5</twSite><twDelType>Trcko_DOA</twDelType><twDelInfo twEdge="twRising">1.850</twDelInfo><twComp>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twComp><twBEL>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y23.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.070</twDelInfo><twComp>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta&lt;5&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y23.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r0&lt;3&gt;</twComp><twBEL>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux111</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y22.BX</twSite><twDelType>net</twDelType><twFanCnt>18</twFanCnt><twDelInfo twEdge="twRising">0.850</twDelInfo><twComp>EU_CORE/eu_rom_data&lt;19&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y22.BMUX</twSite><twDelType>Tbxb</twDelType><twDelInfo twEdge="twRising">0.157</twDelInfo><twComp>EU_CORE/eu_biu_dataout&lt;3&gt;</twComp><twBEL>EU_CORE/mux14_2_f8</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y25.D1</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.878</twDelInfo><twComp>EU_CORE/eu_operand1&lt;8&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y25.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r2&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;7&gt;1_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y25.C6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.132</twDelInfo><twComp>N147</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y25.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r2&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;9&gt;1_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y24.C2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.804</twDelInfo><twComp>N153</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y24.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_alu_last_result&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;11&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y30.A5</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.811</twDelInfo><twComp>EU_CORE/carry&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y30.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r1&lt;15&gt;</twComp><twBEL>EU_CORE/Mmux_n045543</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y27.CX</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twRising">0.628</twDelInfo><twComp>EU_CORE/n0455&lt;12&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y27.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.063</twDelInfo><twComp>EU_CORE/eu_register_di&lt;12&gt;</twComp><twBEL>EU_CORE/eu_register_di_12</twBEL></twPathDel><twLogDel>3.365</twLogDel><twRouteDel>5.173</twRouteDel><twTotDel>8.538</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="9.090">core_clk_int</twDestClk><twPctLog>39.4</twPctLog><twPctRoute>60.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="25"><twConstPath anchorID="26" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.385</twSlack><twSrc BELType="RAM">EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twSrc><twDest BELType="FF">EU_CORE/eu_register_di_12</twDest><twTotPathDel>8.472</twTotPathDel><twClkSkew dest = "0.240" src = "0.247">0.007</twClkSkew><twDelConst>9.090</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.381" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.226</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twSrc><twDest BELType='FF'>EU_CORE/eu_register_di_12</twDest><twLogLvls>6</twLogLvls><twSrcSite>RAMB16_X1Y12.CLKA</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">core_clk_int</twSrcClk><twPathDel><twSite>RAMB16_X1Y12.DOA2</twSite><twDelType>Trcko_DOA</twDelType><twDelInfo twEdge="twRising">1.850</twDelInfo><twComp>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twComp><twBEL>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y21.B3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.098</twDelInfo><twComp>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y21.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>BIU_CORE/pfq_addr_out_d1&lt;15&gt;</twComp><twBEL>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux81</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y22.D4</twSite><twDelType>net</twDelType><twFanCnt>49</twFanCnt><twDelInfo twEdge="twRising">0.520</twDelInfo><twComp>EU_CORE/eu_rom_data&lt;16&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y22.BMUX</twSite><twDelType>Topdb</twDelType><twDelInfo twEdge="twRising">0.393</twDelInfo><twComp>EU_CORE/eu_biu_dataout&lt;3&gt;</twComp><twBEL>EU_CORE/mux14_6</twBEL><twBEL>EU_CORE/mux14_4_f7</twBEL><twBEL>EU_CORE/mux14_2_f8</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y25.D1</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.878</twDelInfo><twComp>EU_CORE/eu_operand1&lt;8&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y25.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r2&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;7&gt;1_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y25.C6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.132</twDelInfo><twComp>N147</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y25.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r2&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;9&gt;1_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y24.C2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.804</twDelInfo><twComp>N153</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y24.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_alu_last_result&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;11&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y30.A5</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.811</twDelInfo><twComp>EU_CORE/carry&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y30.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r1&lt;15&gt;</twComp><twBEL>EU_CORE/Mmux_n045543</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y27.CX</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twRising">0.628</twDelInfo><twComp>EU_CORE/n0455&lt;12&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y27.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.063</twDelInfo><twComp>EU_CORE/eu_register_di&lt;12&gt;</twComp><twBEL>EU_CORE/eu_register_di_12</twBEL></twPathDel><twLogDel>3.601</twLogDel><twRouteDel>4.871</twRouteDel><twTotDel>8.472</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="9.090">core_clk_int</twDestClk><twPctLog>42.5</twPctLog><twPctRoute>57.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="27"><twConstPath anchorID="28" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.392</twSlack><twSrc BELType="RAM">EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twSrc><twDest BELType="FF">EU_CORE/eu_register_di_12</twDest><twTotPathDel>8.465</twTotPathDel><twClkSkew dest = "0.240" src = "0.247">0.007</twClkSkew><twDelConst>9.090</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.381" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.226</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twSrc><twDest BELType='FF'>EU_CORE/eu_register_di_12</twDest><twLogLvls>6</twLogLvls><twSrcSite>RAMB16_X1Y12.CLKA</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">core_clk_int</twSrcClk><twPathDel><twSite>RAMB16_X1Y12.DOA2</twSite><twDelType>Trcko_DOA</twDelType><twDelInfo twEdge="twRising">1.850</twDelInfo><twComp>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twComp><twBEL>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y21.B3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.098</twDelInfo><twComp>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y21.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>BIU_CORE/pfq_addr_out_d1&lt;15&gt;</twComp><twBEL>EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux81</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y22.C4</twSite><twDelType>net</twDelType><twFanCnt>49</twFanCnt><twDelInfo twEdge="twRising">0.520</twDelInfo><twComp>EU_CORE/eu_rom_data&lt;16&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y22.BMUX</twSite><twDelType>Topcb</twDelType><twDelInfo twEdge="twRising">0.386</twDelInfo><twComp>EU_CORE/eu_biu_dataout&lt;3&gt;</twComp><twBEL>EU_CORE/mux14_51</twBEL><twBEL>EU_CORE/mux14_4_f7</twBEL><twBEL>EU_CORE/mux14_2_f8</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y25.D1</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.878</twDelInfo><twComp>EU_CORE/eu_operand1&lt;8&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y25.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r2&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;7&gt;1_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y25.C6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.132</twDelInfo><twComp>N147</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y25.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r2&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;9&gt;1_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y24.C2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.804</twDelInfo><twComp>N153</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y24.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_alu_last_result&lt;11&gt;</twComp><twBEL>EU_CORE/carry&lt;11&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y30.A5</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.811</twDelInfo><twComp>EU_CORE/carry&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y30.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>EU_CORE/eu_register_r1&lt;15&gt;</twComp><twBEL>EU_CORE/Mmux_n045543</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y27.CX</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twRising">0.628</twDelInfo><twComp>EU_CORE/n0455&lt;12&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X17Y27.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.063</twDelInfo><twComp>EU_CORE/eu_register_di&lt;12&gt;</twComp><twBEL>EU_CORE/eu_register_di_12</twBEL></twPathDel><twLogDel>3.594</twLogDel><twRouteDel>4.871</twRouteDel><twTotDel>8.465</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="9.090">core_clk_int</twDestClk><twPctLog>42.5</twPctLog><twPctRoute>57.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_SPARTAN6PLL_clkfx = PERIOD TIMEGRP &quot;SPARTAN6PLL_clkfx&quot; TS_CORE_CLK / 2.2
+        HIGH 50%;
+</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point BIU_CORE/Mshreg_biu_return_data_int_d2_2 (SLICE_X12Y35.BX), 1 path
+</twPathRptBanner><twPathRpt anchorID="29"><twConstPath anchorID="30" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.367</twSlack><twSrc BELType="FF">BIU_CORE/biu_return_data_int_2</twSrc><twDest BELType="FF">BIU_CORE/Mshreg_biu_return_data_int_d2_2</twDest><twTotPathDel>0.369</twTotPathDel><twClkSkew dest = "0.041" src = "0.039">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>BIU_CORE/biu_return_data_int_2</twSrc><twDest BELType='FF'>BIU_CORE/Mshreg_biu_return_data_int_d2_2</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X13Y35.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">core_clk_int</twSrcClk><twPathDel><twSite>SLICE_X13Y35.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>BIU_CORE/biu_return_data_int_5</twComp><twBEL>BIU_CORE/biu_return_data_int_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y35.BX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.251</twDelInfo><twComp>BIU_CORE/biu_return_data_int_2</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X12Y35.CLK</twSite><twDelType>Tdh</twDelType><twDelInfo twEdge="twFalling">-0.080</twDelInfo><twComp>BIU_CORE/biu_return_data_int_d2&lt;5&gt;</twComp><twBEL>BIU_CORE/Mshreg_biu_return_data_int_d2_2</twBEL></twPathDel><twLogDel>0.118</twLogDel><twRouteDel>0.251</twRouteDel><twTotDel>0.369</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="0.000">core_clk_int</twDestClk><twPctLog>32.0</twPctLog><twPctRoute>68.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point BIU_CORE/Mshreg_biu_register_reg_d2_11 (SLICE_X20Y29.BX), 1 path
+</twPathRptBanner><twPathRpt anchorID="31"><twConstPath anchorID="32" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.371</twSlack><twSrc BELType="FF">BIU_CORE/biu_register_reg_11</twSrc><twDest BELType="FF">BIU_CORE/Mshreg_biu_register_reg_d2_11</twDest><twTotPathDel>0.372</twTotPathDel><twClkSkew dest = "0.042" src = "0.041">-0.001</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>BIU_CORE/biu_register_reg_11</twSrc><twDest BELType='FF'>BIU_CORE/Mshreg_biu_register_reg_d2_11</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X20Y30.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">core_clk_int</twSrcClk><twPathDel><twSite>SLICE_X20Y30.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.234</twDelInfo><twComp>BIU_CORE/biu_register_reg&lt;11&gt;</twComp><twBEL>BIU_CORE/biu_register_reg_11</twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y29.BX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.218</twDelInfo><twComp>BIU_CORE/biu_register_reg&lt;11&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X20Y29.CLK</twSite><twDelType>Tdh</twDelType><twDelInfo twEdge="twFalling">-0.080</twDelInfo><twComp>BIU_CORE/biu_register_reg_d2&lt;12&gt;</twComp><twBEL>BIU_CORE/Mshreg_biu_register_reg_d2_11</twBEL></twPathDel><twLogDel>0.154</twLogDel><twRouteDel>0.218</twRouteDel><twTotDel>0.372</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="0.000">core_clk_int</twDestClk><twPctLog>41.4</twPctLog><twPctRoute>58.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point BIU_CORE/Mshreg_biu_register_rm_d2_7 (SLICE_X0Y20.BI), 1 path
+</twPathRptBanner><twPathRpt anchorID="33"><twConstPath anchorID="34" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.372</twSlack><twSrc BELType="FF">BIU_CORE/biu_register_rm_7</twSrc><twDest BELType="FF">BIU_CORE/Mshreg_biu_register_rm_d2_7</twDest><twTotPathDel>0.376</twTotPathDel><twClkSkew dest = "0.038" src = "0.034">-0.004</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>BIU_CORE/biu_register_rm_7</twSrc><twDest BELType='FF'>BIU_CORE/Mshreg_biu_register_rm_d2_7</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X0Y21.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">core_clk_int</twSrcClk><twPathDel><twSite>SLICE_X0Y21.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.234</twDelInfo><twComp>BIU_CORE/biu_register_rm&lt;7&gt;</twComp><twBEL>BIU_CORE/biu_register_rm_7</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y20.BI</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.113</twDelInfo><twComp>BIU_CORE/biu_register_rm&lt;7&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X0Y20.CLK</twSite><twDelType>Tdh</twDelType><twDelInfo twEdge="twFalling">0.029</twDelInfo><twComp>BIU_CORE/biu_register_rm_d2&lt;4&gt;</twComp><twBEL>BIU_CORE/Mshreg_biu_register_rm_d2_7</twBEL></twPathDel><twLogDel>0.263</twLogDel><twRouteDel>0.113</twRouteDel><twTotDel>0.376</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="0.000">core_clk_int</twDestClk><twPctLog>69.9</twPctLog><twPctRoute>30.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="35"><twPinLimitBanner>Component Switching Limit Checks: TS_SPARTAN6PLL_clkfx = PERIOD TIMEGRP &quot;SPARTAN6PLL_clkfx&quot; TS_CORE_CLK / 2.2
+        HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="36" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="5.966" period="9.090" constraintValue="9.090" deviceLimit="3.124" freqLimit="320.102" physResource="EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA" logResource="EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA" locationPin="RAMB16_X1Y14.CLKA" clockNet="core_clk_int"/><twPinLimit anchorID="37" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="5.966" period="9.090" constraintValue="9.090" deviceLimit="3.124" freqLimit="320.102" physResource="EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA" logResource="EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA" locationPin="RAMB16_X1Y10.CLKA" clockNet="core_clk_int"/><twPinLimit anchorID="38" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="5.966" period="9.090" constraintValue="9.090" deviceLimit="3.124" freqLimit="320.102" physResource="EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA" logResource="EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA" locationPin="RAMB16_X0Y12.CLKA" clockNet="core_clk_int"/></twPinLimitRpt></twConst><twConstRollupTable uID="1" anchorID="39"><twConstRollup name="TS_CORE_CLK" fullName="TS_CORE_CLK = PERIOD TIMEGRP &quot;CORE_CLK&quot; 20 ns HIGH 50%;" type="origin" depth="0" requirement="20.000" prefType="period" actual="8.000" actualRollup="19.340" errors="0" errorRollup="0" items="0" itemsRollup="513828"/><twConstRollup name="TS_SPARTAN6PLL_clkfx" fullName="TS_SPARTAN6PLL_clkfx = PERIOD TIMEGRP &quot;SPARTAN6PLL_clkfx&quot; TS_CORE_CLK / 2.2         HIGH 50%;" type="child" depth="1" requirement="9.091" prefType="period" actual="8.791" actualRollup="N/A" errors="0" errorRollup="0" items="513828" itemsRollup="0"/></twConstRollupTable><twUnmetConstCnt anchorID="40">0</twUnmetConstCnt><twDataSheet anchorID="41" twNameLen="15"><twClk2SUList anchorID="42" twDestWidth="8"><twDest>CORE_CLK</twDest><twClk2SU><twSrc>CORE_CLK</twSrc><twRiseRise>8.791</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="43"><twErrCnt>0</twErrCnt><twScore>0</twScore><twSetupScore>0</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>513828</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>5708</twConnCnt></twConstCov><twStats anchorID="44"><twMinPer>8.791</twMinPer><twFootnote number="1" /><twMaxFreq>113.753</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation  number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Wed Nov 11 19:11:41 2020 </twTimestamp></twFoot><twClientInfo anchorID="45"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
+
+Peak Memory Usage: 236 MB
+</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.ucf b/MCL86jr/FPGA/MCL86jr/MCL86jr.ucf
new file mode 100644
index 0000000..61c0ad9
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.ucf
@@ -0,0 +1,178 @@
+
+#Created by Constraints Editor (xc6slx9-tqg144-2) - 2016/06/18
+NET "CORE_CLK" TNM_NET = "CORE_CLK";
+TIMESPEC TS_CORE_CLK = PERIOD "CORE_CLK" 20 ns HIGH 50 %;
+
+
+NET "CORE_CLK" IOSTANDARD = PCI33_3;
+NET "A8" IOSTANDARD = PCI33_3;
+NET "A9" IOSTANDARD = PCI33_3;
+NET "A10" IOSTANDARD = PCI33_3;
+NET "A11" IOSTANDARD = PCI33_3;
+NET "A12" IOSTANDARD = PCI33_3;
+NET "A13" IOSTANDARD = PCI33_3;
+NET "A14" IOSTANDARD = PCI33_3;
+NET "A15" IOSTANDARD = PCI33_3;
+NET "A16" IOSTANDARD = PCI33_3;
+NET "A17" IOSTANDARD = PCI33_3;
+NET "A18" IOSTANDARD = PCI33_3;
+NET "A19" IOSTANDARD = PCI33_3;
+NET "AD0" IOSTANDARD = PCI33_3;
+NET "AD1" IOSTANDARD = PCI33_3;
+NET "AD2" IOSTANDARD = PCI33_3;
+NET "AD3" IOSTANDARD = PCI33_3;
+NET "AD4" IOSTANDARD = PCI33_3;
+NET "AD5" IOSTANDARD = PCI33_3;
+NET "AD6" IOSTANDARD = PCI33_3;
+NET "AD7" IOSTANDARD = PCI33_3;
+NET "CLK" IOSTANDARD = PCI33_3;
+NET "INTR" IOSTANDARD = PCI33_3;
+NET "NMI" IOSTANDARD = LVCMOS33;
+NET "READY" IOSTANDARD = PCI33_3;
+NET "RESET" IOSTANDARD = PCI33_3;
+NET "ALE" IOSTANDARD = PCI33_3;
+NET "INTA_n" IOSTANDARD = PCI33_3;
+NET "RD_n" IOSTANDARD = PCI33_3;
+NET "DEN" IOSTANDARD = PCI33_3;
+NET "WR_n" IOSTANDARD = PCI33_3;
+NET "DTR" IOSTANDARD = PCI33_3;
+NET "IOM" IOSTANDARD = PCI33_3;
+
+NET "SRAM_A[18]" IOSTANDARD = PCI33_3;
+NET "SRAM_A[17]" IOSTANDARD = PCI33_3;
+NET "SRAM_A[16]" IOSTANDARD = PCI33_3;
+NET "SRAM_A[15]" IOSTANDARD = PCI33_3;
+NET "SRAM_A[14]" IOSTANDARD = PCI33_3;
+NET "SRAM_A[13]" IOSTANDARD = PCI33_3;
+NET "SRAM_A[12]" IOSTANDARD = PCI33_3;
+NET "SRAM_A[11]" IOSTANDARD = PCI33_3;
+NET "SRAM_A[10]" IOSTANDARD = PCI33_3;
+NET "SRAM_A[9]" IOSTANDARD = PCI33_3;
+NET "SRAM_A[8]" IOSTANDARD = PCI33_3;
+NET "SRAM_A[7]" IOSTANDARD = PCI33_3;
+NET "SRAM_A[6]" IOSTANDARD = PCI33_3;
+NET "SRAM_A[5]" IOSTANDARD = PCI33_3;
+NET "SRAM_A[4]" IOSTANDARD = PCI33_3;
+NET "SRAM_A[3]" IOSTANDARD = PCI33_3;
+NET "SRAM_A[2]" IOSTANDARD = PCI33_3;
+NET "SRAM_A[1]" IOSTANDARD = PCI33_3;
+NET "SRAM_A[0]" IOSTANDARD = PCI33_3;
+NET "SRAM_CE_n" IOSTANDARD = PCI33_3;
+NET "SRAM_OE_n" IOSTANDARD = PCI33_3;
+NET "SRAM_WE_n" IOSTANDARD = PCI33_3;
+NET "SRAM_D[7]" IOSTANDARD = PCI33_3;
+NET "SRAM_D[6]" IOSTANDARD = PCI33_3;
+NET "SRAM_D[5]" IOSTANDARD = PCI33_3;
+NET "SRAM_D[4]" IOSTANDARD = PCI33_3;
+NET "SRAM_D[3]" IOSTANDARD = PCI33_3;
+NET "SRAM_D[2]" IOSTANDARD = PCI33_3;
+NET "SRAM_D[1]" IOSTANDARD = PCI33_3;
+NET "SRAM_D[0]" IOSTANDARD = PCI33_3;
+
+NET "LED[7]" IOSTANDARD = PCI33_3;
+NET "LED[6]" IOSTANDARD = PCI33_3;
+NET "LED[5]" IOSTANDARD = PCI33_3;
+NET "LED[4]" IOSTANDARD = PCI33_3;
+NET "LED[3]" IOSTANDARD = PCI33_3;
+NET "LED[2]" IOSTANDARD = PCI33_3;
+NET "LED[1]" IOSTANDARD = PCI33_3;
+NET "LED[0]" IOSTANDARD = PCI33_3;
+
+NET "BUF1_OE_n" IOSTANDARD = PCI33_3;
+NET "BUF2_OE_n" IOSTANDARD = PCI33_3;
+NET "BUF2_DIR" IOSTANDARD = PCI33_3;
+NET "SSO_n" IOSTANDARD = PCI33_3;
+
+
+
+
+
+
+NET "A8" LOC = P14;
+NET "A9" LOC = P11;
+NET "A10" LOC = P9;
+NET "A11" LOC = P7;
+NET "A12" LOC = P5;
+NET "A13" LOC = P1;
+NET "A14" LOC = P142;
+NET "A15" LOC = P143;
+NET "A16" LOC = P2;
+NET "A17" LOC = P6;
+NET "A18" LOC = P8;
+NET "A19" LOC = P10;
+NET "AD0" LOC = P35;
+NET "AD1" LOC = P34;
+NET "AD2" LOC = P33;
+NET "AD3" LOC = P32;
+NET "AD4" LOC = P27;
+NET "AD5" LOC = P26;
+NET "AD6" LOC = P23;
+NET "AD7" LOC = P22;
+NET "CLK" LOC = P46;
+NET "INTR" LOC = P45;
+NET "NMI" LOC = P44;
+NET "READY" LOC = P48;
+NET "RESET" LOC = P47;
+NET "ALE" LOC = P41;
+NET "INTA_n" LOC = P58;
+NET "RD_n" LOC = P50;
+NET "WR_n" LOC = P51;
+NET "IOM" LOC = P55;
+NET "DTR" LOC = P56;
+NET "DEN" LOC = P57;
+
+NET "SRAM_A[18]" LOC = P99;
+NET "SRAM_A[17]" LOC = P79;
+NET "SRAM_A[16]" LOC = P78;
+NET "SRAM_A[15]" LOC = P100;
+NET "SRAM_A[14]" LOC = P75;
+NET "SRAM_A[13]" LOC = P97;
+NET "SRAM_A[12]" LOC = P74;
+NET "SRAM_A[11]" LOC = P93;
+NET "SRAM_A[10]" LOC = P88;
+NET "SRAM_A[9]" LOC = P94;
+NET "SRAM_A[8]" LOC = P95;
+NET "SRAM_A[7]" LOC = P67;
+NET "SRAM_A[6]" LOC = P66;
+NET "SRAM_A[5]" LOC = P62;
+NET "SRAM_A[4]" LOC = P61;
+NET "SRAM_A[3]" LOC = P123;
+NET "SRAM_A[2]" LOC = P124;
+NET "SRAM_A[1]" LOC = P126;
+NET "SRAM_A[0]" LOC = P132;
+
+NET "SRAM_CE_n" LOC = P87;
+NET "SRAM_OE_n" LOC = P92;
+NET "SRAM_WE_n" LOC = P98;
+
+NET "SRAM_D[7]" LOC = P85;
+NET "SRAM_D[6]" LOC = P83;
+NET "SRAM_D[5]" LOC = P82;
+NET "SRAM_D[4]" LOC = P81;
+NET "SRAM_D[3]" LOC = P80;
+NET "SRAM_D[2]" LOC = P117;
+NET "SRAM_D[1]" LOC = P118;
+NET "SRAM_D[0]" LOC = P119;
+
+NET "LED[7]" LOC = P131;
+NET "LED[6]" LOC = P127;
+NET "LED[5]" LOC = P121;
+NET "LED[4]" LOC = P120;
+NET "LED[3]" LOC = P116;
+NET "LED[2]" LOC = P114;
+NET "LED[1]" LOC = P112;
+NET "LED[0]" LOC = P111;
+
+
+NET "CORE_CLK" LOC = P84;
+
+
+NET "BUF1_OE_n" LOC = P59;
+NET "BUF2_OE_n" LOC = P21;
+NET "BUF2_DIR" LOC = P16;
+NET "SSO_n" LOC = P12;
+
+
+# PlanAhead Generated IO constraints 
+
+NET "NMI" PULLDOWN;
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.ucf.bak b/MCL86jr/FPGA/MCL86jr/MCL86jr.ucf.bak
new file mode 100644
index 0000000..12003f9
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.ucf.bak
@@ -0,0 +1,175 @@
+
+#Created by Constraints Editor (xc6slx9-tqg144-2) - 2016/06/18
+NET "CORE_CLK" TNM_NET = "CORE_CLK";
+TIMESPEC TS_CORE_CLK = PERIOD "CORE_CLK" 20 ns HIGH 50 %;
+
+# PlanAhead Generated IO constraints 
+
+NET "CORE_CLK" IOSTANDARD = PCI33_3;
+NET "A8" IOSTANDARD = PCI33_3;  
+NET "A9" IOSTANDARD = PCI33_3;  
+NET "A10" IOSTANDARD = PCI33_3; 
+NET "A11" IOSTANDARD = PCI33_3 ;
+NET "A12" IOSTANDARD = PCI33_3 ;
+NET "A13" IOSTANDARD = PCI33_3 ;
+NET "A14" IOSTANDARD = PCI33_3 ;
+NET "A15" IOSTANDARD = PCI33_3 ;
+NET "A16" IOSTANDARD = PCI33_3 ; 
+NET "A17" IOSTANDARD = PCI33_3 ; 
+NET "A18" IOSTANDARD = PCI33_3 ; 
+NET "A19" IOSTANDARD = PCI33_3 ; 
+NET "AD0" IOSTANDARD = PCI33_3 ;
+NET "AD1" IOSTANDARD = PCI33_3 ;
+NET "AD2" IOSTANDARD = PCI33_3 ;
+NET "AD3" IOSTANDARD = PCI33_3 ;
+NET "AD4" IOSTANDARD = PCI33_3 ;
+NET "AD5" IOSTANDARD = PCI33_3 ;
+NET "AD6" IOSTANDARD = PCI33_3 ;
+NET "AD7" IOSTANDARD = PCI33_3 ;
+NET "CLK" IOSTANDARD = PCI33_3 ;
+NET "INTR" IOSTANDARD = PCI33_3 ;   
+NET "NMI" IOSTANDARD = PCI33_3 ;  
+NET "READY" IOSTANDARD = PCI33_3 ;
+NET "RESET" IOSTANDARD = PCI33_3 ;
+NET "ALE"  IOSTANDARD = PCI33_3 ;
+NET "INTA_n"  IOSTANDARD = PCI33_3 ;
+NET "RD_n"  IOSTANDARD = PCI33_3 ;
+NET "DEN" IOSTANDARD = PCI33_3 ; 
+NET "WR_n" IOSTANDARD = PCI33_3 ;
+NET "DTR" IOSTANDARD = PCI33_3 ; 
+NET "IOM" IOSTANDARD = PCI33_3 ; 
+
+NET "SRAM_A[18]"     IOSTANDARD = PCI33_3 ;
+NET "SRAM_A[17]"     IOSTANDARD = PCI33_3 ;
+NET "SRAM_A[16]"     IOSTANDARD = PCI33_3 ;
+NET "SRAM_A[15]"     IOSTANDARD = PCI33_3 ;
+NET "SRAM_A[14]"     IOSTANDARD = PCI33_3 ;
+NET "SRAM_A[13]"     IOSTANDARD = PCI33_3 ;
+NET "SRAM_A[12]"     IOSTANDARD = PCI33_3 ;
+NET "SRAM_A[11]"     IOSTANDARD = PCI33_3 ;
+NET "SRAM_A[10]"     IOSTANDARD = PCI33_3 ;
+NET "SRAM_A[9]"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_A[8]"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_A[7]"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_A[6]"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_A[5]"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_A[4]"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_A[3]"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_A[2]"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_A[1]"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_A[0]"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_CE_n"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_OE_n"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_WE_n"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_D[7]"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_D[6]"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_D[5]"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_D[4]"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_D[3]"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_D[2]"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_D[1]"      IOSTANDARD = PCI33_3 ;
+NET "SRAM_D[0]"      IOSTANDARD = PCI33_3 ;
+
+NET "LED[7]"      IOSTANDARD = PCI33_3 ;
+NET "LED[6]"      IOSTANDARD = PCI33_3 ;
+NET "LED[5]"      IOSTANDARD = PCI33_3 ;
+NET "LED[4]"      IOSTANDARD = PCI33_3 ;
+NET "LED[3]"      IOSTANDARD = PCI33_3 ;
+NET "LED[2]"      IOSTANDARD = PCI33_3 ;
+NET "LED[1]"      IOSTANDARD = PCI33_3 ;
+NET "LED[0]"      IOSTANDARD = PCI33_3 ;
+
+NET "BUF1_OE_n"      IOSTANDARD = PCI33_3 ;
+NET "BUF2_OE_n"      IOSTANDARD = PCI33_3 ;
+NET "BUF2_DIR"      IOSTANDARD = PCI33_3 ;
+NET "SSO_n"      IOSTANDARD = PCI33_3 ;
+
+
+
+
+
+
+NET "A8"   LOC = P14    ;
+NET "A9"   LOC = P11    ;
+NET "A10"  LOC = P9    ;
+NET "A11"  LOC = P7    ;
+NET "A12"  LOC = P5    ;
+NET "A13"  LOC = P1    ;
+NET "A14"  LOC = P143    ;
+NET "A15"  LOC = P144    ;
+NET "A16"  LOC = P2    ;
+NET "A17"  LOC = P6    ;
+NET "A18"  LOC = P8    ;
+NET "A19"  LOC = P10    ;
+NET "AD0"  LOC = P35    ;
+NET "AD1"  LOC = P34    ;
+NET "AD2"  LOC = P33    ;
+NET "AD3"  LOC = P32    ;
+NET "AD4"  LOC = P27    ;
+NET "AD5"  LOC = P26    ;
+NET "AD6"  LOC = P23    ;
+NET "AD7"  LOC = P22    ;
+NET "CLK"  LOC = P46;
+NET "INTR"   LOC = P45  ;
+NET "NMI"    LOC = P44  ;
+NET "READY"  LOC = P48  ;
+NET "RESET"  LOC = P47  ;
+NET "ALE"     LOC = P41   ;
+NET "INTA_n"  LOC = P58   ;
+NET "RD_n"    LOC = P50   ;
+NET "WR_n"    LOC = P51   ;
+NET "IOM"     LOC = P55   ;
+NET "DTR"     LOC = P56   ;
+NET "DEN"     LOC = P57   ;
+
+NET "SRAM_A[18]"     LOC = P99   ;
+NET "SRAM_A[17]"     LOC = P79   ;
+NET "SRAM_A[16]"     LOC = P78   ;
+NET "SRAM_A[15]"     LOC = P100   ;
+NET "SRAM_A[14]"     LOC = P75   ;
+NET "SRAM_A[13]"     LOC = P97   ;
+NET "SRAM_A[12]"     LOC = P74   ;
+NET "SRAM_A[11]"     LOC = P93   ;
+NET "SRAM_A[10]"     LOC = P88   ;
+NET "SRAM_A[9]"     LOC = P94   ;
+NET "SRAM_A[8]"     LOC = P95   ;
+NET "SRAM_A[7]"     LOC = P67   ;
+NET "SRAM_A[6]"     LOC = P66   ;
+NET "SRAM_A[5]"     LOC = P62   ;
+NET "SRAM_A[4]"     LOC = P61   ;
+NET "SRAM_A[3]"     LOC = P123   ;
+NET "SRAM_A[2]"     LOC = P124   ;
+NET "SRAM_A[1]"     LOC = P126   ;
+NET "SRAM_A[0]"     LOC = P132   ;
+
+NET "SRAM_CE_n"     LOC = P87  ;
+NET "SRAM_OE_n"     LOC = P92  ;
+NET "SRAM_WE_n"     LOC = P98  ;
+
+NET "SRAM_D[7]"     LOC = P85  ;
+NET "SRAM_D[6]"     LOC = P83  ;
+NET "SRAM_D[5]"     LOC = P82  ;
+NET "SRAM_D[4]"     LOC = P81  ;
+NET "SRAM_D[3]"     LOC = P80   ;
+NET "SRAM_D[2]"     LOC = P117   ;
+NET "SRAM_D[1]"     LOC = P118   ;
+NET "SRAM_D[0]"     LOC = P119   ;
+
+NET "LED[7]"        LOC = P131   ;
+NET "LED[6]"        LOC = P127   ;
+NET "LED[5]"        LOC = P121   ;
+NET "LED[4]"        LOC = P120   ;
+NET "LED[3]"        LOC = P116   ;
+NET "LED[2]"        LOC = P114   ;
+NET "LED[1]"        LOC = P112   ;
+NET "LED[0]"        LOC = P111   ;
+
+
+NET "CORE_CLK"     LOC = P84  ;
+
+
+NET "BUF1_OE_n"   LOC = P59  ;
+NET "BUF2_OE_n"   LOC = P21  ;
+NET "BUF2_DIR"    LOC = P16  ;
+NET "SSO_n"         LOC = P12  ;
+
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.unroutes b/MCL86jr/FPGA/MCL86jr/MCL86jr.unroutes
new file mode 100644
index 0000000..b30f415
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.unroutes
@@ -0,0 +1,9 @@
+Release 14.7 - par P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Wed Nov 11 19:11:34 2020
+
+All signals are completely routed.
+
+
+
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.ut b/MCL86jr/FPGA/MCL86jr/MCL86jr.ut
new file mode 100644
index 0000000..b72fd8a
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.ut
@@ -0,0 +1,31 @@
+-g INIT_9K:Yes
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:10
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:Yes
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.xise b/MCL86jr/FPGA/MCL86jr/MCL86jr.xise
new file mode 100644
index 0000000..c9ba1e0
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.xise
@@ -0,0 +1,386 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="../src4synth/biu_min.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+    </file>
+    <file xil_pn:name="../src4synth/MCL86jr.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+    </file>
+    <file xil_pn:name="../src4synth/eu.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+    </file>
+    <file xil_pn:name="ipcore_dir/EU4Kx32.xco" xil_pn:type="FILE_COREGEN">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="MCL86jr.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="ipcore_dir/spartan6_pll.xco" xil_pn:type="FILE_COREGEN">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+    </file>
+    <file xil_pn:name="ipcore_dir/EU4Kx32.xise" xil_pn:type="FILE_COREGENISE">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="ipcore_dir/spartan6_pll.xise" xil_pn:type="FILE_COREGENISE">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="10" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|MCL86jr" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../src4synth/MCL86jr.v" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MCL86jr" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="-g INIT_9K:Yes" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="MCL86jr" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MCL86jr_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="MCL86jr_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MCL86jr_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MCL86jr_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="MCL86jr" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-09-12T20:32:34" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="0F0A51A7D06B470287A989EDCA362445" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.xpi b/MCL86jr/FPGA/MCL86jr/MCL86jr.xpi
new file mode 100644
index 0000000..a50c444
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.xpi
@@ -0,0 +1,3 @@
+PROGRAM=PAR
+STATE=ROUTED
+TIMESPECS_MET=YES
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr.xst b/MCL86jr/FPGA/MCL86jr/MCL86jr.xst
new file mode 100644
index 0000000..6ad3867
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr.xst
@@ -0,0 +1,53 @@
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn MCL86jr.prj
+-ofn MCL86jr
+-ofmt NGC
+-p xc6slx9-3-tqg144
+-top MCL86jr
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-sd {"ipcore_dir"  }
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr_bitgen.xwbt b/MCL86jr/FPGA/MCL86jr/MCL86jr_bitgen.xwbt
new file mode 100644
index 0000000..cf4eabf
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr_bitgen.xwbt
@@ -0,0 +1,8 @@
+INTSTYLE=ise
+INFILE=C:\MCL\MCL86\MCL86jr\MCL86jr\MCL86jr.ncd
+OUTFILE=C:\MCL\MCL86\MCL86jr\MCL86jr\MCL86jr.bit
+FAMILY=Spartan6
+PART=xc6slx9-3tqg144
+WORKINGDIR=C:\MCL\MCL86\MCL86jr\MCL86jr
+LICENSE=WebPack
+USER_INFO=174191283_174191284_0_212
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr_envsettings.html b/MCL86jr/FPGA/MCL86jr/MCL86jr_envsettings.html
new file mode 100644
index 0000000..836058a
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr_envsettings.html
@@ -0,0 +1,568 @@
+<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<center><big><big><b>System Settings</b></big></big></center><br>
+<A NAME="Environment Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Environment Variable</b></td>
+<td><b>xst</b></td>
+<td><b>ngdbuild</b></td>
+<td><b>map</b></td>
+<td><b>par</b></td>
+</tr>
+<tr>
+<td>PATHEXT</td>
+<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
+<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
+<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
+<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
+</tr>
+<tr>
+<td>Path</td>
+<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\Program Files (x86)\SemanticDesigns\DMS\Executables;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Intel\WiFi\bin\;<br>C:\Program Files\Common Files\Intel\WirelessCommon\;<br>C:\altera_lite\15.1\modelsim_ase\win32aloem;<br>C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem</td>
+<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\Program Files (x86)\SemanticDesigns\DMS\Executables;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Intel\WiFi\bin\;<br>C:\Program Files\Common Files\Intel\WirelessCommon\;<br>C:\altera_lite\15.1\modelsim_ase\win32aloem;<br>C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem</td>
+<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\Program Files (x86)\SemanticDesigns\DMS\Executables;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Intel\WiFi\bin\;<br>C:\Program Files\Common Files\Intel\WirelessCommon\;<br>C:\altera_lite\15.1\modelsim_ase\win32aloem;<br>C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem</td>
+<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\Program Files (x86)\SemanticDesigns\DMS\Executables;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Intel\WiFi\bin\;<br>C:\Program Files\Common Files\Intel\WirelessCommon\;<br>C:\altera_lite\15.1\modelsim_ase\win32aloem;<br>C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem</td>
+</tr>
+<tr>
+<td>XILINX</td>
+<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
+<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
+<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
+<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
+</tr>
+<tr>
+<td>XILINX_DSP</td>
+<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
+<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
+<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
+<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
+</tr>
+<tr>
+<td>XILINX_EDK</td>
+<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
+<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
+<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
+<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
+</tr>
+<tr>
+<td>XILINX_PLANAHEAD</td>
+<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
+<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
+<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
+<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
+</tr>
+</TABLE>
+<A NAME="Synthesis Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td>-ifn</td>
+<td>&nbsp;</td>
+<td>MCL86jr.prj</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-ofn</td>
+<td>&nbsp;</td>
+<td>MCL86jr</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-ofmt</td>
+<td>&nbsp;</td>
+<td>NGC</td>
+<td>NGC</td>
+</tr>
+<tr>
+<td>-p</td>
+<td>&nbsp;</td>
+<td>xc6slx9-3-tqg144</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-top</td>
+<td>&nbsp;</td>
+<td>MCL86jr</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-opt_mode</td>
+<td>Optimization Goal</td>
+<td>Speed</td>
+<td>Speed</td>
+</tr>
+<tr>
+<td>-opt_level</td>
+<td>Optimization Effort</td>
+<td>1</td>
+<td>1</td>
+</tr>
+<tr>
+<td>-power</td>
+<td>Power Reduction</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-iuc</td>
+<td>Use synthesis Constraints File</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-keep_hierarchy</td>
+<td>Keep Hierarchy</td>
+<td>No</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-netlist_hierarchy</td>
+<td>Netlist Hierarchy</td>
+<td>As_Optimized</td>
+<td>As_Optimized</td>
+</tr>
+<tr>
+<td>-rtlview</td>
+<td>Generate RTL Schematic</td>
+<td>Yes</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-glob_opt</td>
+<td>Global Optimization Goal</td>
+<td>AllClockNets</td>
+<td>AllClockNets</td>
+</tr>
+<tr>
+<td>-read_cores</td>
+<td>Read Cores</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-sd</td>
+<td>Cores Search Directories</td>
+<td>{&quot;ipcore_dir&quot;  }</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-write_timing_constraints</td>
+<td>Write Timing Constraints</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-cross_clock_analysis</td>
+<td>Cross Clock Analysis</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-bus_delimiter</td>
+<td>Bus Delimiter</td>
+<td>&lt;&gt;</td>
+<td>&lt;&gt;</td>
+</tr>
+<tr>
+<td>-slice_utilization_ratio</td>
+<td>Slice Utilization Ratio</td>
+<td>100</td>
+<td>100</td>
+</tr>
+<tr>
+<td>-bram_utilization_ratio</td>
+<td>BRAM Utilization Ratio</td>
+<td>100</td>
+<td>100</td>
+</tr>
+<tr>
+<td>-dsp_utilization_ratio</td>
+<td>DSP Utilization Ratio</td>
+<td>100</td>
+<td>100</td>
+</tr>
+<tr>
+<td>-reduce_control_sets</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-fsm_extract</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-fsm_encoding</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-safe_implementation</td>
+<td>&nbsp;</td>
+<td>No</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-fsm_style</td>
+<td>&nbsp;</td>
+<td>LUT</td>
+<td>LUT</td>
+</tr>
+<tr>
+<td>-ram_extract</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-ram_style</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-rom_extract</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-shreg_extract</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-rom_style</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-auto_bram_packing</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-resource_sharing</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-async_to_sync</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-use_dsp48</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-iobuf</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-max_fanout</td>
+<td>&nbsp;</td>
+<td>100000</td>
+<td>100000</td>
+</tr>
+<tr>
+<td>-bufg</td>
+<td>&nbsp;</td>
+<td>16</td>
+<td>16</td>
+</tr>
+<tr>
+<td>-register_duplication</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-register_balancing</td>
+<td>&nbsp;</td>
+<td>No</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-optimize_primitives</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-use_clock_enable</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-use_sync_set</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-use_sync_reset</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-iob</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-equivalent_register_removal</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-slice_utilization_ratio_maxmargin</td>
+<td>&nbsp;</td>
+<td>5</td>
+<td>0</td>
+</tr>
+</TABLE>
+<A NAME="Translation Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td>-intstyle</td>
+<td>&nbsp;</td>
+<td>ise</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-dd</td>
+<td>&nbsp;</td>
+<td>_ngo</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-p</td>
+<td>&nbsp;</td>
+<td>xc6slx9-tqg144-3</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-sd</td>
+<td>Macro Search Path</td>
+<td>ipcore_dir</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-uc</td>
+<td>&nbsp;</td>
+<td>MCL86jr.ucf</td>
+<td>None</td>
+</tr>
+</TABLE>
+<A NAME="Map Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td>-ol</td>
+<td>Place & Route Effort Level (Overall)</td>
+<td>high</td>
+<td>high</td>
+</tr>
+<tr>
+<td>-xe</td>
+<td>Placer Extra Effort Map</td>
+<td>NORMAL</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-xt</td>
+<td>Extra Cost Tables</td>
+<td>0</td>
+<td>0</td>
+</tr>
+<tr>
+<td>-ir</td>
+<td>Use RLOC Constraints</td>
+<td>OFF</td>
+<td>OFF</td>
+</tr>
+<tr>
+<td>-t</td>
+<td>Starting Placer Cost Table (1-100) Map</td>
+<td>2</td>
+<td>0</td>
+</tr>
+<tr>
+<td>-r</td>
+<td>Register Ordering</td>
+<td>4</td>
+<td>4</td>
+</tr>
+<tr>
+<td>-register_duplication</td>
+<td>Register Duplication Map</td>
+<td>TRUE</td>
+<td>FALSE</td>
+</tr>
+<tr>
+<td>-intstyle</td>
+<td>&nbsp;</td>
+<td>ise</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-lc</td>
+<td>LUT Combining</td>
+<td>off</td>
+<td>off</td>
+</tr>
+<tr>
+<td>-o</td>
+<td>&nbsp;</td>
+<td>MCL86jr_map.ncd</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-w</td>
+<td>&nbsp;</td>
+<td>true</td>
+<td>false</td>
+</tr>
+<tr>
+<td>-pr</td>
+<td>Pack I/O Registers/Latches into IOBs</td>
+<td>b</td>
+<td>off</td>
+</tr>
+<tr>
+<td>-p</td>
+<td>&nbsp;</td>
+<td>xc6slx9-tqg144-3</td>
+<td>None</td>
+</tr>
+</TABLE>
+<A NAME="Place and Route Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td>-xe</td>
+<td>&nbsp;</td>
+<td>n</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-intstyle</td>
+<td>&nbsp;</td>
+<td>ise</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-mt</td>
+<td>Enable Multi-Threading</td>
+<td>off</td>
+<td>off</td>
+</tr>
+<tr>
+<td>-ol</td>
+<td>Place & Route Effort Level (Overall)</td>
+<td>high</td>
+<td>std</td>
+</tr>
+<tr>
+<td>-w</td>
+<td>&nbsp;</td>
+<td>true</td>
+<td>false</td>
+</tr>
+</TABLE>
+<A NAME="Operating System Information"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Operating System Information</b></td>
+<td><b>xst</b></td>
+<td><b>ngdbuild</b></td>
+<td><b>map</b></td>
+<td><b>par</b></td>
+</tr>
+<tr>
+<td>CPU Architecture/Speed</td>
+<td>Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz/2492 MHz</td>
+<td>Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz/2492 MHz</td>
+<td>Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz/2492 MHz</td>
+<td>Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz/2492 MHz</td>
+</tr>
+<tr>
+<td>Host</td>
+<td>MicroCoreLabs</td>
+<td>MicroCoreLabs</td>
+<td>MicroCoreLabs</td>
+<td>MicroCoreLabs</td>
+</tr>
+<tr>
+<td>OS Name</td>
+<td>Microsoft Windows 7 , 64-bit</td>
+<td>Microsoft Windows 7 , 64-bit</td>
+<td>Microsoft Windows 7 , 64-bit</td>
+<td>Microsoft Windows 7 , 64-bit</td>
+</tr>
+<tr>
+<td>OS Release</td>
+<td>Service Pack 1  (build 7601)</td>
+<td>Service Pack 1  (build 7601)</td>
+<td>Service Pack 1  (build 7601)</td>
+<td>Service Pack 1  (build 7601)</td>
+</tr>
+</TABLE>
+</BODY> </HTML>
\ No newline at end of file
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr_guide.ncd b/MCL86jr/FPGA/MCL86jr/MCL86jr_guide.ncd
new file mode 100644
index 0000000..ae05415
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr_guide.ncd
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6
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   1272     7e0eNrVlzlynDcQhS/jA2BvAJM4dKDAOgLW0FWKVbq7v26K5SpzRqlpBm8e/sbS6BX8w5frHz+++3Jud933Ib21uHuIu/aQUgJkAjrMAUFeDPMNCqOHUloP4hdQLlALMJgny/dQHd9qRjocW43J2hkQTFGobDovk1dEuprClR62O0BEupuyCxxBeiZb3cCmN3PQnbfHwH4xpAPM1GMMscfEfjGN1mP2FdBvOQrQNrCRFs+KkjNQCrBcj1KRymSeLKSVG8V6V49tIB2eySOw6UgKkynjzh6nZzgl9LiwS9yO4U4s24Vztx55HGccnXIwcTwLuIlN74k9uViAtIGpDGny+s1LBXRKZNMU2T7l6AGckgoaJMkXqFFhdq7rew6n9BzT7Tk1hol5WV2Wi7SeK2tzSwwbN8/Du55XYt4quecdkG7dZV+kp7LiDIUDXGGru1Ivjg2KG74XjyuA00sOsKLfZDCsbgKibCsjxkolaErzXmEBeLC0zbJ2di8jKQy+zVCBKr1scYCuPYReubd1cX4DGEJcykDWbyUBnCbuxi6+VGAzrzjpIugi6lWpBLUM3WBMYLbbZRGdsqIDcK1cDqqOYXWEcvU+9Rrk9hoz3wgOYI/OTh4gNWr2SHNkWRnx8ce/0+pqVhHEFRuGFjNAsMfZiIC5cHQo2LXi6Dxu7XniwDIvZj4FvRshLuewO9H+cXekbE8YDEI8jZF7mp6AmInhXMSMXi2tQcxsXJS2uQ1B8fi4hIhPyMZeNHlKVGniQiWzohRWCCnehcTpksg0SQsrZTVknmo+tJe1sPrmlrIn0oMucs1eF0glf1Q8RRQnC1AAu+RGyjj8Hl0mPZxms8MkkTwimx3Zx73ITfI/CvEWG1rFiztSxPmJvOwp4U905PrZkTy5acpQi9LVLPAbSEVTAdvnsjZZUAeAzrkdbD8aXpjUrDwrk9dg8nYKGThBs0BT67aMmUjuIhmrrUqYXiqLBFJVtH5K4VpS5iDyAgLR2BJSWiqaSuO+MgTrLioL4Yfg4ngij4hyTK6OydUbnEwM4ulaKIRVYgSoJ5VQ7pU5QCofTXzUwlqJuUYYpFI4G5MSzthrEinq6JS0iGTKbCpRQXPWe0KD1OIGa37cuOrGapDutZxq8aJwFo1U6lBz6Umc6pJIjxkfZUNlqS8/undpdk4v3QfqkE/1dkYIhGrmKxbLBN+L/SlhctoLYek75hcyQq668EJYux/1yZFJhXg1nICdqPky45PbUWKZR7uktfXoHR7gWvQLOkeSQQDXii8a1kzHMTy4O91FmLlBTAZHnEYtxZkVlWj954xW9YzUs1nFbt9ncX2ykPv85htdd49ijDQL8fEFRm58/7KpivH7t+3G4y++SXf6SyK7x4/XQv8rYfiVMD5+/FCVyb03ldXfiy6ptWlRtp8qnD+BwsEUrho/6Ha71oEzYr80ktsED9PTnmpff2ov/4n2r4XpV8L8K2F5N0r86cW3jHW0NO/2Inepdk9tUT6BJ9O70lZhPL70nkenD3TQp0qnT6B0flfaKmLkReMjj1XPM/G50u0TKF3elbYKnmkNPk92LhTpp0rLJ1Ba3pW2jlOY4nlpAulFeIRPoHR9V9o6pPDI8TUMa2jPlZ6fQOn2rrR2dK//Z9HLAo3WvWhc4xMo7U1psecAcGCTB4CfNDC/aNN+lReBsn6qX/5njYC/33//8/vX2Z17fF3d+cc3bXaOn2AjOgFPPv21PmBkvZP79lqDZv/2NlMa9Y1iLOtLxVjV54AxexQYW/o0MHb0gaCseHvFKYvai41l7cjGRPuysabd2djUHm1sW6dWyltY+5bRYN3L6FsPM1qskxlt1i6MTmsaRre1DqPXGohSDWGqtNFktdposYpttFrdNjqtOBrdViKNXiuUSjWdKZdGk9Uko8Uqk9Fq9cnosCpldFspMHqtICgd3sqC0fj22lVaLAONVstDo8Oy0eiynDR6397BUP4T0/A3Gi0JjGZLBaNiCWG0WVo8iKO/AV3t5bg=
\ No newline at end of file
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr_map.map b/MCL86jr/FPGA/MCL86jr/MCL86jr_map.map
new file mode 100644
index 0000000..6a41c38
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr_map.map
@@ -0,0 +1,178 @@
+Release 14.7 Map P.20131013 (nt64)
+Xilinx Map Application Log File for Design 'MCL86jr'
+
+Design Information
+------------------
+Command Line   : map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol
+high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir
+off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+Target Device  : xc6slx9
+Target Package : tqg144
+Target Speed   : -3
+Mapper Version : spartan6 -- $Revision: 1.55 $
+Mapped Date    : Wed Nov 11 19:10:23 2020
+
+Mapping design into LUTs...
+Running directed packing...
+Running delay-based LUT packing...
+Updating timing models...
+WARNING:Timing:3402 - The Clock Modifying COMP, SPARTAN6PLL/dcm_sp_inst, has the attribute CLK_FEEDBACK set to NONE.  No phase relationship
+   exists between the input and output clocks of this Clock Modifying COMP. Data paths between these clock domains must be constrained using
+   FROM/TO constraints.
+INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
+   (.mrp).
+Running timing-driven placement...
+Total REAL time at the beginning of Placer: 6 secs 
+Total CPU  time at the beginning of Placer: 5 secs 
+
+Phase 1.1  Initial Placement Analysis
+Phase 1.1  Initial Placement Analysis (Checksum:7c03570a) REAL time: 6 secs 
+
+Phase 2.7  Design Feasibility Check
+Phase 2.7  Design Feasibility Check (Checksum:7c03570a) REAL time: 7 secs 
+
+Phase 3.31  Local Placement Optimization
+Phase 3.31  Local Placement Optimization (Checksum:7c03570a) REAL time: 7 secs 
+
+Phase 4.2  Initial Placement for Architecture Specific Features
+
+Phase 4.2  Initial Placement for Architecture Specific Features
+(Checksum:1a11c56) REAL time: 9 secs 
+
+Phase 5.36  Local Placement Optimization
+Phase 5.36  Local Placement Optimization (Checksum:1a11c56) REAL time: 9 secs 
+
+Phase 6.30  Global Clock Region Assignment
+Phase 6.30  Global Clock Region Assignment (Checksum:1a11c56) REAL time: 9 secs 
+
+Phase 7.3  Local Placement Optimization
+Phase 7.3  Local Placement Optimization (Checksum:1a11c56) REAL time: 9 secs 
+
+Phase 8.5  Local Placement Optimization
+Phase 8.5  Local Placement Optimization (Checksum:1a11c56) REAL time: 9 secs 
+
+Phase 9.8  Global Placement
+............................
+......................
+......................................................................................
+...........................................................................................................................................................................................
+.................................
+Phase 9.8  Global Placement (Checksum:eb9fb3e1) REAL time: 17 secs 
+
+Phase 10.5  Local Placement Optimization
+Phase 10.5  Local Placement Optimization (Checksum:eb9fb3e1) REAL time: 17 secs 
+
+Phase 11.18  Placement Optimization
+Phase 11.18  Placement Optimization (Checksum:7cbfab27) REAL time: 28 secs 
+
+Phase 12.5  Local Placement Optimization
+Phase 12.5  Local Placement Optimization (Checksum:7cbfab27) REAL time: 28 secs 
+
+Phase 13.34  Placement Validation
+Phase 13.34  Placement Validation (Checksum:20017819) REAL time: 28 secs 
+
+Total REAL time to Placer completion: 28 secs 
+Total CPU  time to Placer completion: 28 secs 
+Running physical synthesis...
+
+Physical synthesis completed.
+Running post-placement packing...
+Writing output files...
+WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
+   (RAMB8BWER).  9K Block RAM initialization data, both user defined and
+   default, may be incorrect and should not be used.  For more information,
+   please reference Xilinx Answer Record 39999.
+
+Design Summary
+--------------
+
+Design Summary:
+Number of errors:      0
+Number of warnings:    2
+Slice Logic Utilization:
+  Number of Slice Registers:                   853 out of  11,440    7%
+    Number used as Flip Flops:                 853
+    Number used as Latches:                      0
+    Number used as Latch-thrus:                  0
+    Number used as AND/OR logics:                0
+  Number of Slice LUTs:                        959 out of   5,720   16%
+    Number used as logic:                      887 out of   5,720   15%
+      Number using O6 output only:             681
+      Number using O5 output only:              54
+      Number using O5 and O6:                  152
+      Number used as ROM:                        0
+    Number used as Memory:                      58 out of   1,440    4%
+      Number used as Dual Port RAM:              0
+      Number used as Single Port RAM:            0
+      Number used as Shift Register:            58
+        Number using O6 output only:             2
+        Number using O5 output only:             0
+        Number using O5 and O6:                 56
+    Number used exclusively as route-thrus:     14
+      Number with same-slice register load:      8
+      Number with same-slice carry load:         6
+      Number with other load:                    0
+
+Slice Logic Distribution:
+  Number of occupied Slices:                   381 out of   1,430   26%
+  Number of MUXCYs used:                       196 out of   2,860    6%
+  Number of LUT Flip Flop pairs used:        1,197
+    Number with an unused Flip Flop:           437 out of   1,197   36%
+    Number with an unused LUT:                 238 out of   1,197   19%
+    Number of fully used LUT-FF pairs:         522 out of   1,197   43%
+    Number of unique control sets:              40
+    Number of slice register sites lost
+      to control set restrictions:              41 out of  11,440    1%
+
+  A LUT Flip Flop pair for this architecture represents one LUT paired with
+  one Flip Flop within a slice.  A control set is a unique combination of
+  clock, reset, set, and enable signals for a registered element.
+  The Slice Logic Distribution report is not meaningful if the design is
+  over-mapped for a non-slice resource or if Placement fails.
+
+IO Utilization:
+  Number of bonded IOBs:                        75 out of     102   73%
+    Number of LOCed IOBs:                       75 out of      75  100%
+    IOB Flip Flops:                             39
+
+Specific Feature Utilization:
+  Number of RAMB16BWERs:                         7 out of      32   21%
+  Number of RAMB8BWERs:                          1 out of      64    1%
+  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3%
+    Number used as BUFIO2s:                      1
+    Number used as BUFIO2_2CLKs:                 0
+  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
+  Number of BUFG/BUFGMUXs:                       1 out of      16    6%
+    Number used as BUFGs:                        1
+    Number used as BUFGMUX:                      0
+  Number of DCM/DCM_CLKGENs:                     1 out of       4   25%
+    Number used as DCMs:                         1
+    Number used as DCM_CLKGENs:                  0
+  Number of ILOGIC2/ISERDES2s:                  12 out of     200    6%
+    Number used as ILOGIC2s:                    12
+    Number used as ISERDES2s:                    0
+  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
+  Number of OLOGIC2/OSERDES2s:                  27 out of     200   13%
+    Number used as OLOGIC2s:                    27
+    Number used as OSERDES2s:                    0
+  Number of BSCANs:                              0 out of       4    0%
+  Number of BUFHs:                               0 out of     128    0%
+  Number of BUFPLLs:                             0 out of       8    0%
+  Number of BUFPLL_MCBs:                         0 out of       4    0%
+  Number of DSP48A1s:                            0 out of      16    0%
+  Number of ICAPs:                               0 out of       1    0%
+  Number of MCBs:                                0 out of       2    0%
+  Number of PCILOGICSEs:                         0 out of       2    0%
+  Number of PLL_ADVs:                            0 out of       2    0%
+  Number of PMVs:                                0 out of       1    0%
+  Number of STARTUPs:                            0 out of       1    0%
+  Number of SUSPEND_SYNCs:                       0 out of       1    0%
+
+Average Fanout of Non-Clock Nets:                4.04
+
+Peak Memory Usage:  441 MB
+Total REAL time to MAP completion:  33 secs 
+Total CPU time to MAP completion:   32 secs 
+
+Mapping completed.
+See MAP report file "MCL86jr_map.mrp" for details.
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr_map.mrp b/MCL86jr/FPGA/MCL86jr/MCL86jr_map.mrp
new file mode 100644
index 0000000..b736129
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr_map.mrp
@@ -0,0 +1,329 @@
+Release 14.7 Map P.20131013 (nt64)
+Xilinx Mapping Report File for Design 'MCL86jr'
+
+Design Information
+------------------
+Command Line   : map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol
+high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir
+off -pr b -lc off -power off -o MCL86jr_map.ncd MCL86jr.ngd MCL86jr.pcf 
+Target Device  : xc6slx9
+Target Package : tqg144
+Target Speed   : -3
+Mapper Version : spartan6 -- $Revision: 1.55 $
+Mapped Date    : Wed Nov 11 19:10:23 2020
+
+Design Summary
+--------------
+Number of errors:      0
+Number of warnings:    2
+Slice Logic Utilization:
+  Number of Slice Registers:                   853 out of  11,440    7%
+    Number used as Flip Flops:                 853
+    Number used as Latches:                      0
+    Number used as Latch-thrus:                  0
+    Number used as AND/OR logics:                0
+  Number of Slice LUTs:                        959 out of   5,720   16%
+    Number used as logic:                      887 out of   5,720   15%
+      Number using O6 output only:             681
+      Number using O5 output only:              54
+      Number using O5 and O6:                  152
+      Number used as ROM:                        0
+    Number used as Memory:                      58 out of   1,440    4%
+      Number used as Dual Port RAM:              0
+      Number used as Single Port RAM:            0
+      Number used as Shift Register:            58
+        Number using O6 output only:             2
+        Number using O5 output only:             0
+        Number using O5 and O6:                 56
+    Number used exclusively as route-thrus:     14
+      Number with same-slice register load:      8
+      Number with same-slice carry load:         6
+      Number with other load:                    0
+
+Slice Logic Distribution:
+  Number of occupied Slices:                   381 out of   1,430   26%
+  Number of MUXCYs used:                       196 out of   2,860    6%
+  Number of LUT Flip Flop pairs used:        1,197
+    Number with an unused Flip Flop:           437 out of   1,197   36%
+    Number with an unused LUT:                 238 out of   1,197   19%
+    Number of fully used LUT-FF pairs:         522 out of   1,197   43%
+    Number of unique control sets:              40
+    Number of slice register sites lost
+      to control set restrictions:              41 out of  11,440    1%
+
+  A LUT Flip Flop pair for this architecture represents one LUT paired with
+  one Flip Flop within a slice.  A control set is a unique combination of
+  clock, reset, set, and enable signals for a registered element.
+  The Slice Logic Distribution report is not meaningful if the design is
+  over-mapped for a non-slice resource or if Placement fails.
+
+IO Utilization:
+  Number of bonded IOBs:                        75 out of     102   73%
+    Number of LOCed IOBs:                       75 out of      75  100%
+    IOB Flip Flops:                             39
+
+Specific Feature Utilization:
+  Number of RAMB16BWERs:                         7 out of      32   21%
+  Number of RAMB8BWERs:                          1 out of      64    1%
+  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3%
+    Number used as BUFIO2s:                      1
+    Number used as BUFIO2_2CLKs:                 0
+  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
+  Number of BUFG/BUFGMUXs:                       1 out of      16    6%
+    Number used as BUFGs:                        1
+    Number used as BUFGMUX:                      0
+  Number of DCM/DCM_CLKGENs:                     1 out of       4   25%
+    Number used as DCMs:                         1
+    Number used as DCM_CLKGENs:                  0
+  Number of ILOGIC2/ISERDES2s:                  12 out of     200    6%
+    Number used as ILOGIC2s:                    12
+    Number used as ISERDES2s:                    0
+  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
+  Number of OLOGIC2/OSERDES2s:                  27 out of     200   13%
+    Number used as OLOGIC2s:                    27
+    Number used as OSERDES2s:                    0
+  Number of BSCANs:                              0 out of       4    0%
+  Number of BUFHs:                               0 out of     128    0%
+  Number of BUFPLLs:                             0 out of       8    0%
+  Number of BUFPLL_MCBs:                         0 out of       4    0%
+  Number of DSP48A1s:                            0 out of      16    0%
+  Number of ICAPs:                               0 out of       1    0%
+  Number of MCBs:                                0 out of       2    0%
+  Number of PCILOGICSEs:                         0 out of       2    0%
+  Number of PLL_ADVs:                            0 out of       2    0%
+  Number of PMVs:                                0 out of       1    0%
+  Number of STARTUPs:                            0 out of       1    0%
+  Number of SUSPEND_SYNCs:                       0 out of       1    0%
+
+Average Fanout of Non-Clock Nets:                4.04
+
+Peak Memory Usage:  441 MB
+Total REAL time to MAP completion:  33 secs 
+Total CPU time to MAP completion:   32 secs 
+
+Table of Contents
+-----------------
+Section 1 - Errors
+Section 2 - Warnings
+Section 3 - Informational
+Section 4 - Removed Logic Summary
+Section 5 - Removed Logic
+Section 6 - IOB Properties
+Section 7 - RPMs
+Section 8 - Guide Report
+Section 9 - Area Group and Partition Summary
+Section 10 - Timing Report
+Section 11 - Configuration String Information
+Section 12 - Control Set Information
+Section 13 - Utilization by Hierarchy
+
+Section 1 - Errors
+------------------
+
+Section 2 - Warnings
+--------------------
+WARNING:Timing:3402 - The Clock Modifying COMP, SPARTAN6PLL/dcm_sp_inst, has the attribute CLK_FEEDBACK set to NONE.  No phase relationship
+   exists between the input and output clocks of this Clock Modifying COMP. Data paths between these clock domains must be constrained using
+   FROM/TO constraints.
+WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
+   (RAMB8BWER).  9K Block RAM initialization data, both user defined and
+   default, may be incorrect and should not be used.  For more information,
+   please reference Xilinx Answer Record 39999.
+
+Section 3 - Informational
+-------------------------
+INFO:LIT:243 - Logical network EU_CORE/EU4Kx32_i/douta<31> has no load.
+INFO:MapLib:562 - No environment variables are currently set.
+INFO:LIT:244 - All of the single ended outputs in this design are using slew
+   rate limited output drivers. The delay on speed critical single ended outputs
+   can be dramatically reduced by designating them as fast outputs.
+INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
+   0.000 to 85.000 Celsius)
+INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
+   1.260 Volts)
+INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
+   (.mrp).
+INFO:Pack:1650 - Map created a placed design.
+INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance
+   with the CLKFX and CLKFX180 outputs of the DCM comp SPARTAN6PLL/dcm_sp_inst,
+   consult the device Data Sheet.
+
+Section 4 - Removed Logic Summary
+---------------------------------
+   1 block(s) removed
+   4 block(s) optimized away
+   3 signal(s) removed
+
+Section 5 - Removed Logic
+-------------------------
+
+The trimmed logic report below shows the logic removed from your design due to
+sourceless or loadless signals, and VCC or ground connections.  If the removal
+of a signal or symbol results in the subsequent removal of an additional signal
+or symbol, the message explaining that second removal will be indented.  This
+indentation will be repeated as a chain of related logic is removed.
+
+To quickly locate the original cause for the removal of a chain of logic, look
+above the place where that logic is listed in the trimming report, then locate
+the lines that are least indented (begin at the leftmost edge).
+
+The signal "EU_CORE/EU4Kx32_i/douta<31>" is sourceless and has been removed.
+The signal
+"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.
+cstr/ramloop[7].ram.ram_douta<8>" is sourceless and has been removed.
+ Sourceless block
+"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.
+cstr/has_mux_a.A/Mmux_dout_mux251" (ROM) removed.
+The signal
+"EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.
+cstr/ramloop[6].ram.ram_douta<8>" is sourceless and has been removed.
+
+Optimized Block(s):
+TYPE 		BLOCK
+GND 		EU_CORE/EU4Kx32_i/XST_GND
+VCC 		EU_CORE/EU4Kx32_i/XST_VCC
+GND 		XST_GND
+VCC 		XST_VCC
+
+To enable printing of redundant blocks removed and signals merged, set the
+detailed map report option and rerun map.
+
+Section 6 - IOB Properties
+--------------------------
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+| IOB Name                           | Type             | Direction | IO Standard          | Diff  | Drive    | Slew | Reg (s)      | Resistor | IOB      |
+|                                    |                  |           |                      | Term  | Strength | Rate |              |          | Delay    |
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+| A8                                 | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
+| A9                                 | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
+| A10                                | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
+| A11                                | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
+| A12                                | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
+| A13                                | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
+| A14                                | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
+| A15                                | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
+| A16                                | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
+| A17                                | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
+| A18                                | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
+| A19                                | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
+| AD0                                | IOB              | BIDIR     | PCI33_3              |       |          |      | IFF          |          |          |
+|                                    |                  |           |                      |       |          |      | OFF          |          |          |
+| AD1                                | IOB              | BIDIR     | PCI33_3              |       |          |      | IFF          |          |          |
+|                                    |                  |           |                      |       |          |      | OFF          |          |          |
+| AD2                                | IOB              | BIDIR     | PCI33_3              |       |          |      | IFF          |          |          |
+|                                    |                  |           |                      |       |          |      | OFF          |          |          |
+| AD3                                | IOB              | BIDIR     | PCI33_3              |       |          |      | IFF          |          |          |
+|                                    |                  |           |                      |       |          |      | OFF          |          |          |
+| AD4                                | IOB              | BIDIR     | PCI33_3              |       |          |      | IFF          |          |          |
+|                                    |                  |           |                      |       |          |      | OFF          |          |          |
+| AD5                                | IOB              | BIDIR     | PCI33_3              |       |          |      | IFF          |          |          |
+|                                    |                  |           |                      |       |          |      | OFF          |          |          |
+| AD6                                | IOB              | BIDIR     | PCI33_3              |       |          |      | IFF          |          |          |
+|                                    |                  |           |                      |       |          |      | OFF          |          |          |
+| AD7                                | IOB              | BIDIR     | PCI33_3              |       |          |      | IFF          |          |          |
+|                                    |                  |           |                      |       |          |      | OFF          |          |          |
+| ALE                                | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
+| BUF1_OE_n                          | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| BUF2_DIR                           | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| BUF2_OE_n                          | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| CLK                                | IOB              | INPUT     | PCI33_3              |       |          |      | IFF          |          |          |
+| CORE_CLK                           | IOB              | INPUT     | PCI33_3              |       |          |      |              |          |          |
+| DEN                                | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
+| DTR                                | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
+| INTA_n                             | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
+| INTR                               | IOB              | INPUT     | PCI33_3              |       |          |      | IFF          |          |          |
+| IOM                                | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
+| LED<0>                             | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| LED<1>                             | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| LED<2>                             | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| LED<3>                             | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| LED<4>                             | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| LED<5>                             | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| LED<6>                             | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| LED<7>                             | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| NMI                                | IOB              | INPUT     | LVCMOS33             |       |          |      | IFF          | PULLDOWN |          |
+| RD_n                               | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
+| READY                              | IOB              | INPUT     | PCI33_3              |       |          |      | IFF          |          |          |
+| RESET                              | IOB              | INPUT     | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<0>                          | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<1>                          | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<2>                          | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<3>                          | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<4>                          | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<5>                          | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<6>                          | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<7>                          | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<8>                          | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<9>                          | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<10>                         | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<11>                         | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<12>                         | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<13>                         | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<14>                         | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<15>                         | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<16>                         | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<17>                         | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_A<18>                         | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_CE_n                          | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_D<0>                          | IOB              | BIDIR     | PCI33_3              |       |          |      |              |          |          |
+| SRAM_D<1>                          | IOB              | BIDIR     | PCI33_3              |       |          |      |              |          |          |
+| SRAM_D<2>                          | IOB              | BIDIR     | PCI33_3              |       |          |      |              |          |          |
+| SRAM_D<3>                          | IOB              | BIDIR     | PCI33_3              |       |          |      |              |          |          |
+| SRAM_D<4>                          | IOB              | BIDIR     | PCI33_3              |       |          |      |              |          |          |
+| SRAM_D<5>                          | IOB              | BIDIR     | PCI33_3              |       |          |      |              |          |          |
+| SRAM_D<6>                          | IOB              | BIDIR     | PCI33_3              |       |          |      |              |          |          |
+| SRAM_D<7>                          | IOB              | BIDIR     | PCI33_3              |       |          |      |              |          |          |
+| SRAM_OE_n                          | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SRAM_WE_n                          | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| SSO_n                              | IOB              | OUTPUT    | PCI33_3              |       |          |      |              |          |          |
+| WR_n                               | IOB              | OUTPUT    | PCI33_3              |       |          |      | OFF          |          |          |
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+Section 7 - RPMs
+----------------
+
+Section 8 - Guide Report
+------------------------
+Guide not run on this design.
+
+Section 9 - Area Group and Partition Summary
+--------------------------------------------
+
+Partition Implementation Status
+-------------------------------
+
+  No Partitions were found in this design.
+
+-------------------------------
+
+Area Group Information
+----------------------
+
+  No area groups were found in this design.
+
+----------------------
+
+Section 10 - Timing Report
+--------------------------
+A logic-level (pre-route) timing report can be generated by using Xilinx static
+timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
+mapped NCD and PCF files. Please note that this timing report will be generated
+using estimated delay information. For accurate numbers, please generate a
+timing report with the post Place and Route NCD file.
+
+For more information about the Timing Analyzer, consult the Xilinx Timing
+Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
+Command Line Tools User Guide "TRACE" chapter.
+
+Section 11 - Configuration String Details
+-----------------------------------------
+Use the "-detail" map option to print out Configuration Strings
+
+Section 12 - Control Set Information
+------------------------------------
+Use the "-detail" map option to print out Control Set Information.
+
+Section 13 - Utilization by Hierarchy
+-------------------------------------
+Use the "-detail" map option to print out the Utilization by Hierarchy section.
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr_map.ncd b/MCL86jr/FPGA/MCL86jr/MCL86jr_map.ncd
new file mode 100644
index 0000000..f585e9f
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr_map.ncd
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6
+###3604:XlxV32DM    3fc7     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TeaBbTY7zJOHqcoZi147UH2NjYNdAo+dzuC5/nIhslzAdKkuOIdXAcd2WXmJLfVQ9vMfJMkJnjXvxz8olSCoBM883qce6vwI+PGc44hr5ywUpUXhpY1J/5gJ3GAQBSVe7gGnZD1ZHQRXxHwnBI/g1jVedgDbOYvZeUlZpQuBKB76qBwZ4TwvclsY/HOKi8L0t0gzcA/LyEkjZphQj7fQjjHW3WNY5DFMOXhFDl6Wx9D54DU9eBJwXHeAqyninBQGJKDprSuYhkJ9LBp0h2PS4TDKTbEOvKkG4Hl4E70KeB74khlncs9jkecxZad3eh64gteuUbTKYTvi/V44l3seXZ7HoOdB7yL75vt6bvkUtK2g1dxNSJrejHnbV8iNO7CJO13DmPQQwMVSBT8het4eaJytUqJK1LSVqFWzp47orWmLOjcUcvBbDaS6NKSO4UrPtqkWtKl4oUThA2rHW9SJ89sWKChHCYQnpZuXUhy82ahFgDmzpfKxhfg+l6TMZ1v1kBvy2EFbZTY0BsbQ8Y6OjP4+aPzqiMBRy0Exd3WMgFitihjnOi6aH4ZcDxlyle2DX9ozBiNriYfsOShPL17MFsHuP5i8BNAX9x+PVU2rmta3yfnqkwsF6QgDCZg2tajX6rx7p8w8JwLBCwMTW+eV2Xqjm1MR+Vt9GPQyAkJr9B7Kb3akZrt7h67fcEMTJdsApnO75VawKSsKc5MkNOVjn8w37uWx4GUyYd6HQohD8Yb1ep0cNwE6AmC5/uAbKHiJ78IS31uVvdC+KoM7VWODEl+89xudcC/xLSrxJbij1ld+k3ded80lnYsS30UlvkUlvlMlvgtLfH32qDFYGWVpkgWU+DpnNyMf9iTjmA7dMqvEc1DDOlKJ6Fb5VOCTlZHsUhmIhQOMJLAocovspKKbkMqdcTfE2N7jzjrlycwRJPdkRYMBF8p6DmcE4xf1XplJZIb9fMWUF3HRHxko/VdN3eDyxtG/P3OcavSKhXP//swRjV6xcFzfkYcaWaq3fUe+jcVZ4lB3ipuq9qToDtZrmFfBKratyHraGnXRcZF10/meEt3E3Lmx7TTHJNpgWR1asn+yIst4Ih7WoN+MN9etCysu3aNIKrBmoXIScg+lTf1B06Y8mTblybQZnsyqfmNVP+WeHXm/qtR9DkMqx99eQEgYqowcIP4xoTPUwxnSrzwFFdNJqMf/TWzVb0BATUgj0q/60CLUSrxqScj7zeg3o9+MfjP67eG27eG27Zv67XLgyhr/96xRjrvKXQTij01B5eRY/Gtln/ArhhvcECyXSvxtUePktaGIO33FiH+5jVX/om1KofiOLbFjWQgFuAMWTPzW5XkjiqAf3dA5uQdY1s8/X0TrRq0/zvP7V9dLLQRhhu2RgtoMajOo+W2+vwWylTSawka+R+M8vvWx0atErwVhV91fmVme4rgIXEFetzLZq+vVPj4JEVa6ZP6Bkt9McudvLx6ZVxjJU0qI924yEWl6Q4O4Ma5CCs93V6b2zKD1+I5b6gp3hz2NFAcjiG5G+xem+ZuqxNyMZkzb3b9rfwE0sxvNU+F6Brd9+Mp4FYxmUM4RSFsLrWb81OVlpekIFKW1C32l51uRT7jKMJmTLx5iEA6O70hXwGaQuH425AZYb/wpaesqwIPdwrhpcf/NE2/yi6BuJxKdKHgt+lMDocIcKVR+i1LgMj486Vv875FnfLviT5LD6xM8/PTOUb32P+zqHpZ4D0v8VrYVkUmtmwx2pqbQunxbazhrHoDE8xwByE8Nb1Y00eOKxxlR8da+Acg1R5XpFYO949nDp49Ybo0E75GU92tnJHibflH0IUs0q35UgdOz/fqBQpXETDQeUmNecuopx/Ymj9t36reAGEHmpVFS3MuWu16H/Pbb/6BiEnKlyeCFcp1tLpHpPL9cvkW1DOpK7aJEllWfbf1yGYso73JYAHDuH9psPluc13f7XKQfWD60P1OvMUsl7fKlveYoC1bJrrYvvSeXvrQ5dYqTS+/JRci7j1jg7ypqoYiSj5C4iI23iI2feqmeVY8PbS3wd612FAQzo1D7h3Z52UlXlO1n3NVFdzV+A8D/uUThDZ97IN1aD3nf+FNtypd////a3n/Rju8/YURBbw0tsNYPZf2pfr2FFf27C3EU39p1FVtImOr53YU1R5111FTjTs+WyX8u4uux/ALF/3Xlf1K0FVM=###6424:XlxV32DM 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\ No newline at end of file
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr_map.ngm b/MCL86jr/FPGA/MCL86jr/MCL86jr_map.ngm
new file mode 100644
index 0000000..e5e6f95
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr_map.ngm
@@ -0,0 +1,3 @@
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diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr_map.psr b/MCL86jr/FPGA/MCL86jr/MCL86jr_map.psr
new file mode 100644
index 0000000..a156fb6
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr_map.psr
@@ -0,0 +1,62 @@
+Release 14.7 Physical Synthesis Report P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
+
+TABLE OF CONTENTS
+  1) Physical Synthesis Options Summary
+  2) Optimizations statistics and details
+
+
+=========================================================================
+*                 Physical Synthesis Options Summary                    *
+=========================================================================
+---- Options
+Global Optimization                 : OFF
+    Retiming                        : OFF
+    Equivalent Register Removal     : OFF
+Timing-Driven Packing and Placement : ON
+    Logic Optimization              : OFF
+    Register Duplication            : ON
+
+---- Intelligent clock gating       : OFF
+
+---- Target Parameters
+Target Device                       : 6slx9tqg144-3
+
+=========================================================================
+
+
+=========================================================================
+*                        Optimizations                                  *
+=========================================================================
+---- Statistics
+   Number of LUTs added by Replication                       | 19              
+
+   Overall change in number of design objects                | +19              
+
+
+---- Details
+
+New or modified components                             | Optimization             | Objective           
+-------------------------------------------------------|--------------------------|----------------------
+EU_CORE/EU4Kx32_i/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux131_REPLICA_14| Replication              | Fanout Optimization
+EU_CORE/Mmux_n045543_REPLICA_16                        | Replication              | Fanout Optimization
+EU_CORE/Mmux_n045572_REPLICA_15                        | Replication              | Fanout Optimization
+EU_CORE/carry<9>1_REPLICA_17                           | Replication              | Fanout Optimization
+EU_CORE/eu_rom_data<16>_REPLICA_10                     | Replication              | Fanout Optimization
+EU_CORE/eu_rom_data<17>_REPLICA_5                      | Replication              | Fanout Optimization
+EU_CORE/eu_rom_data<17>_REPLICA_6                      | Replication              | Fanout Optimization
+EU_CORE/eu_rom_data<17>_REPLICA_7                      | Replication              | Fanout Optimization
+EU_CORE/eu_rom_data<17>_REPLICA_8                      | Replication              | Fanout Optimization
+EU_CORE/eu_rom_data<17>_REPLICA_9                      | Replication              | Fanout Optimization
+EU_CORE/eu_rom_data<19>1_REPLICA_18                    | Replication              | Fanout Optimization
+EU_CORE/eu_rom_data<20>_REPLICA_0                      | Replication              | Fanout Optimization
+EU_CORE/eu_rom_data<20>_REPLICA_1                      | Replication              | Fanout Optimization
+EU_CORE/eu_rom_data<20>_REPLICA_2                      | Replication              | Fanout Optimization
+EU_CORE/eu_rom_data<20>_REPLICA_3                      | Replication              | Fanout Optimization
+EU_CORE/eu_rom_data<21>_REPLICA_4                      | Replication              | Fanout Optimization
+EU_CORE/eu_rom_data<22>_REPLICA_11                     | Replication              | Fanout Optimization
+EU_CORE/eu_rom_data<22>_REPLICA_12                     | Replication              | Fanout Optimization
+EU_CORE/eu_rom_data<22>_REPLICA_13                     | Replication              | Fanout Optimization
+
+   Flops added for Enable Generation                       
+-------------------------
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr_map.xrpt b/MCL86jr/FPGA/MCL86jr/MCL86jr_map.xrpt
new file mode 100644
index 0000000..573c231
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr_map.xrpt
@@ -0,0 +1,789 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="nt64" product="ISE" version="14.7">
+
+  <!--The data in this file is primarily intended for consumption by Xilinx tools.
+    The structure and the elements are likely to change over the next few releases.
+    This means code written to parse this file will need to be revisited each subsequent release.-->
+
+  <application stringID="Map" timeStamp="Wed Nov 11 19:10:57 2020">
+    <section stringID="User_Env">
+      <table stringID="User_EnvVar">
+        <column stringID="variable"/>
+        <column stringID="value"/>
+        <row stringID="row" value="0">
+          <item stringID="variable" value="Path"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ProgramData\Oracle\Java\javapath;C:\Program Files (x86)\SemanticDesigns\DMS\Executables;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\Intel\WiFi\bin\;C:\Program Files\Common Files\Intel\WirelessCommon\;C:\altera_lite\15.1\modelsim_ase\win32aloem;C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem"/>
+        </row>
+        <row stringID="row" value="1">
+          <item stringID="variable" value="PATHEXT"/>
+          <item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
+        </row>
+        <row stringID="row" value="2">
+          <item stringID="variable" value="XILINX"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\"/>
+        </row>
+        <row stringID="row" value="3">
+          <item stringID="variable" value="XILINX_DSP"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE"/>
+        </row>
+        <row stringID="row" value="4">
+          <item stringID="variable" value="XILINX_EDK"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\EDK"/>
+        </row>
+        <row stringID="row" value="5">
+          <item stringID="variable" value="XILINX_PLANAHEAD"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\PlanAhead"/>
+        </row>
+      </table>
+      <item stringID="User_EnvOs" value="OS Information">
+        <item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
+        <item stringID="User_EnvOsrelease" value="Service Pack 1  (build 7601)"/>
+      </item>
+      <item stringID="User_EnvHost" value="MicroCoreLabs"/>
+      <table stringID="User_EnvCpu">
+        <column stringID="arch"/>
+        <column stringID="speed"/>
+        <row stringID="row" value="0">
+          <item stringID="arch" value="Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz"/>
+          <item stringID="speed" value="2492 MHz"/>
+        </row>
+      </table>
+    </section>
+    <section stringID="MAP_OPTION_SUMMARY">
+      <item DEFAULT="high" label="-ol" stringID="MAP_EFFORTLEVEL" value="high"/>
+      <item DEFAULT="" label="-xe" stringID="MAP_EXTRAEFFORTLEVEL" value="NORMAL"/>
+      <item DEFAULT="0" label="-xt" stringID="MAP_EXTRA_COST_TABLE" value="0"/>
+      <item DEFAULT="OFF" label="-ir" stringID="MAP_IGNORERLOCS" value="OFF"/>
+      <item DEFAULT="OFF" stringID="MAP_LUTCOMPRESSIONMODE" value="OFF"/>
+      <item DEFAULT="0" label="-t" stringID="MAP_PLACERCOSTTABLE" value="2"/>
+      <item DEFAULT="4" label="-r" stringID="MAP_REGORDERING" value="4"/>
+      <item DEFAULT="FALSE" stringID="MAP_REPLICATELUTS" value="TRUE"/>
+      <item DEFAULT="FALSE" label="-register_duplication" stringID="MAP_REPLICATEREGISTERS" value="TRUE"/>
+      <item DEFAULT="None" label="-intstyle" stringID="MAP_INTSTYLE" value="ise"/>
+      <item DEFAULT="off" label="-lc" stringID="MAP_LUT_COMBINING" value="off"/>
+      <item DEFAULT="None" label="-o" stringID="MAP_OUTFILE" value="MCL86jr_map.ncd"/>
+      <item DEFAULT="false" label="-w" stringID="MAP_OVERWRITE_OUTPUT" value="true"/>
+      <item DEFAULT="off" label="-pr" stringID="MAP_PACK_INTERNAL" value="b"/>
+      <item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc6slx9-tqg144-3"/>
+    </section>
+    <task stringID="MAP_PACK_REPORT">
+      <item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="853">
+        <item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="853"/>
+        <item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
+      </item>
+      <item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="932">
+        <item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="54"/>
+        <item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="662"/>
+        <item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="152"/>
+        <item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_DPRAM_O5ONLY" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_SPRAM_O5ONLY" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="2"/>
+        <item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="56"/>
+        <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="6"/>
+        <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="6"/>
+        <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
+      </item>
+      <item AVAILABLE="102" dataType="int" stringID="MAP_AGG_BONDED_IO" value="75"/>
+      <item AVAILABLE="98" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
+      <item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="39"/>
+      <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
+      <item AVAILABLE="49" dataType="int" stringID="MAP_NUM_IOBM" value="0"/>
+      <item AVAILABLE="51" dataType="int" stringID="MAP_NUM_BONDED_IOBM" value="0"/>
+      <item AVAILABLE="49" dataType="int" stringID="MAP_NUM_IOBS" value="0"/>
+      <item AVAILABLE="51" dataType="int" stringID="MAP_NUM_BONDED_IOBS" value="0"/>
+      <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IPAD" value="0"/>
+      <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_IPAD" value="0"/>
+      <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_OPAD" value="0"/>
+      <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/>
+      <section stringID="MAP_DESIGN_INFORMATION">
+        <item stringID="MAP_PART" value="6slx9tqg144-3"/>
+        <item stringID="MAP_DEVICE" value="xc6slx9"/>
+        <item stringID="MAP_ARCHITECTURE" value="spartan6"/>
+        <item stringID="MAP_PACKAGE" value="tqg144"/>
+        <item stringID="MAP_SPEED" value="-3"/>
+      </section>
+      <section stringID="MAP_DESIGN_SUMMARY">
+        <item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
+        <item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_WARNINGS" value="2"/>
+        <item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="451876"/>
+        <item stringID="MAP_TOTAL_REAL_TIME" value="33 secs "/>
+        <item stringID="MAP_TOTAL_CPU_TIME" value="32 secs "/>
+      </section>
+      <section stringID="MAP_SLICE_REPORTING">
+        <item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="853">
+          <item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="853"/>
+          <item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
+        </item>
+        <item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="959">
+          <item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="54"/>
+          <item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="681"/>
+          <item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="152"/>
+          <item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_DPRAM_O5ONLY" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_SPRAM_O5ONLY" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="2"/>
+          <item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="56"/>
+          <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="6"/>
+          <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="8"/>
+          <item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="8"/>
+          <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="6"/>
+          <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
+        </item>
+        <item AVAILABLE="1430" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="381">
+          <item AVAILABLE="355" dataType="int" stringID="MAP_NUM_SLICEL" value="83"/>
+          <item AVAILABLE="360" dataType="int" stringID="MAP_NUM_SLICEM" value="15"/>
+          <item AVAILABLE="715" dataType="int" stringID="MAP_NUM_SLICEX" value="283"/>
+        </item>
+        <item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1197">
+          <item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="437"/>
+          <item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="238"/>
+          <item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="522"/>
+        </item>
+      </section>
+      <section stringID="MAP_IOB_REPORTING">
+        <item AVAILABLE="102" dataType="int" stringID="MAP_AGG_BONDED_IO" value="75"/>
+        <item AVAILABLE="98" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
+        <item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="39"/>
+        <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
+        <item AVAILABLE="49" dataType="int" stringID="MAP_NUM_IOBM" value="0"/>
+        <item AVAILABLE="51" dataType="int" stringID="MAP_NUM_BONDED_IOBM" value="0"/>
+        <item AVAILABLE="49" dataType="int" stringID="MAP_NUM_IOBS" value="0"/>
+        <item AVAILABLE="51" dataType="int" stringID="MAP_NUM_BONDED_IOBS" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IPAD" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_IPAD" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_OPAD" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/>
+      </section>
+      <section stringID="MAP_HARD_IP_REPORTING"/>
+      <section stringID="MAP_RAM_FIFO_DATA">
+        <item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="7"/>
+        <item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="1"/>
+      </section>
+      <section stringID="MAP_IP_DATA">
+        <item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
+        <item AVAILABLE="128" dataType="int" stringID="MAP_NUM_BUFH" value="0"/>
+        <item AVAILABLE="8" dataType="int" stringID="MAP_NUM_BUFPLL" value="0"/>
+        <item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BUFPLL_MCB" value="0"/>
+        <item AVAILABLE="16" dataType="int" stringID="MAP_NUM_DSP48A1" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_GTPA1_DUAL" value="0"/>
+        <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_ICAP" value="0"/>
+        <item AVAILABLE="2" dataType="int" stringID="MAP_NUM_MCB" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_PCIE_A1" value="0"/>
+        <item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PCILOGICSE" value="0"/>
+        <item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PLL_ADV" value="0"/>
+        <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_PMV" value="0"/>
+        <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_STARTUP" value="0"/>
+        <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
+      </section>
+      <section stringID="MAP_BUFG_DATA">
+        <item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="1"/>
+        <item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
+        <item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
+      </section>
+      <section stringID="MAP_MACRO_RPM_REPORTING">
+        <item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
+        <item dataType="int" stringID="MAP_RPMS" value="0"/>
+      </section>
+      <section stringID="MAP_IOB_PROPERTIES">
+        <table stringID="MAP_IOB_TABLE">
+          <column label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME"/>
+          <column stringID="Type"/>
+          <column stringID="Direction"/>
+          <column label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD"/>
+          <column label="Diff&#xA;Term" stringID="DIFF_TERM"/>
+          <column label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH"/>
+          <column label="Slew&#xA;Rate" stringID="SLEW_RATE"/>
+          <column label="Reg&#xA;(s)" stringID="REGS"/>
+          <column stringID="Resistor"/>
+          <column label="IOB&#xA;Delay" stringID="IOB_DELAY"/>
+          <row stringID="row" value="1">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="A8"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="OFF"/>
+          </row>
+          <row stringID="row" value="2">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="A9"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="OFF"/>
+          </row>
+          <row stringID="row" value="3">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="A10"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="OFF"/>
+          </row>
+          <row stringID="row" value="4">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="A11"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="OFF"/>
+          </row>
+          <row stringID="row" value="5">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="A12"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="OFF"/>
+          </row>
+          <row stringID="row" value="6">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="A13"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="OFF"/>
+          </row>
+          <row stringID="row" value="7">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="A14"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="OFF"/>
+          </row>
+          <row stringID="row" value="8">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="A15"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="OFF"/>
+          </row>
+          <row stringID="row" value="9">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="A16"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="OFF"/>
+          </row>
+          <row stringID="row" value="10">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="A17"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="OFF"/>
+          </row>
+          <row stringID="row" value="11">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="A18"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="OFF"/>
+          </row>
+          <row stringID="row" value="12">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="A19"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="OFF"/>
+          </row>
+          <row stringID="row" value="13">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="AD0"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="BIDIR"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="IFF OFF"/>
+          </row>
+          <row stringID="row" value="14">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="AD1"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="BIDIR"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="IFF OFF"/>
+          </row>
+          <row stringID="row" value="15">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="AD2"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="BIDIR"/>
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+            <item label="Reg&#xA;(s)" stringID="REGS" value="IFF OFF"/>
+          </row>
+          <row stringID="row" value="16">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="AD3"/>
+            <item stringID="Type" value="IOB"/>
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+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="IFF OFF"/>
+          </row>
+          <row stringID="row" value="17">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="AD4"/>
+            <item stringID="Type" value="IOB"/>
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+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="IFF OFF"/>
+          </row>
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+            <item stringID="Type" value="IOB"/>
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+          </row>
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+            <item stringID="Type" value="IOB"/>
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+            <item label="Reg&#xA;(s)" stringID="REGS" value="IFF OFF"/>
+          </row>
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+            <item stringID="Type" value="IOB"/>
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+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="BUF1_OE_n"/>
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+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="BUF2_DIR"/>
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+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="BUF2_OE_n"/>
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+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="CLK"/>
+            <item stringID="Type" value="IOB"/>
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+          </row>
+          <row stringID="row" value="26">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="CORE_CLK"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="INPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="27">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="DEN"/>
+            <item stringID="Type" value="IOB"/>
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+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
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+          </row>
+          <row stringID="row" value="28">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="DTR"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
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+          </row>
+          <row stringID="row" value="29">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="INTA_n"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
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+            <item label="Reg&#xA;(s)" stringID="REGS" value="OFF"/>
+          </row>
+          <row stringID="row" value="30">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="INTR"/>
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+          </row>
+          <row stringID="row" value="31">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="IOM"/>
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+          </row>
+          <row stringID="row" value="32">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="LED&lt;0>"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="33">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="LED&lt;1>"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="34">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="LED&lt;2>"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
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+          </row>
+          <row stringID="row" value="35">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="LED&lt;3>"/>
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+          <row stringID="row" value="36">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="LED&lt;4>"/>
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+          <row stringID="row" value="37">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="LED&lt;5>"/>
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+          </row>
+          <row stringID="row" value="38">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="LED&lt;6>"/>
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+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="39">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="LED&lt;7>"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
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+          </row>
+          <row stringID="row" value="40">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="NMI"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="INPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="IFF"/>
+            <item stringID="Resistor" value="PULLDOWN"/>
+          </row>
+          <row stringID="row" value="41">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RD_n"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="OFF"/>
+          </row>
+          <row stringID="row" value="42">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="READY"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="INPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="IFF"/>
+          </row>
+          <row stringID="row" value="43">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RESET"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="INPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="44">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_A&lt;0>"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="45">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_A&lt;1>"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="46">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_A&lt;2>"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="47">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_A&lt;3>"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="48">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_A&lt;4>"/>
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+          <row stringID="row" value="49">
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+          <row stringID="row" value="50">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_A&lt;6>"/>
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+          <row stringID="row" value="51">
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+          <row stringID="row" value="52">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_A&lt;8>"/>
+            <item stringID="Type" value="IOB"/>
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+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
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+          <row stringID="row" value="53">
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+          <row stringID="row" value="54">
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+          <row stringID="row" value="55">
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+          <row stringID="row" value="56">
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+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
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+          <row stringID="row" value="57">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_A&lt;13>"/>
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+          <row stringID="row" value="58">
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+          <row stringID="row" value="59">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_A&lt;15>"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="60">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_A&lt;16>"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="61">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_A&lt;17>"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
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+          <row stringID="row" value="62">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_A&lt;18>"/>
+            <item stringID="Type" value="IOB"/>
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+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="63">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_CE_n"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
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+          <row stringID="row" value="64">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_D&lt;0>"/>
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+            <item stringID="Direction" value="BIDIR"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="65">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_D&lt;1>"/>
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+            <item stringID="Direction" value="BIDIR"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="66">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_D&lt;2>"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="BIDIR"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="67">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_D&lt;3>"/>
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+            <item stringID="Direction" value="BIDIR"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
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+          <row stringID="row" value="68">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_D&lt;4>"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="BIDIR"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="69">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_D&lt;5>"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="BIDIR"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="70">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_D&lt;6>"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="BIDIR"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
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+          <row stringID="row" value="71">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_D&lt;7>"/>
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+          <row stringID="row" value="72">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_OE_n"/>
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+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
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+          <row stringID="row" value="73">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SRAM_WE_n"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="74">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SSO_n"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+          </row>
+          <row stringID="row" value="75">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="WR_n"/>
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+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="PCI33_3"/>
+            <item label="Reg&#xA;(s)" stringID="REGS" value="OFF"/>
+          </row>
+        </table>
+      </section>
+      <section stringID="MAP_RPM_MACROS">
+        <section stringID="MAP_SHAPE_SECTION">
+          <item dataType="int" stringID="MAP_NUM_SHAPE" value="11"/>
+        </section>
+      </section>
+      <section stringID="MAP_GUIDE_REPORT"/>
+      <section stringID="MAP_AREA_GROUPS_PARTITIONS"/>
+      <section stringID="MAP_TIMING_REPORT"/>
+      <section stringID="MAP_CONFIGURATION_STRING_DETAILS"/>
+      <section stringID="MAP_GENERAL_CONFIG_DATA">
+        <item stringID="MAP_CLKDV_DIVIDE" value="2.0"/>
+        <item stringID="MAP_CLKIN_DIVIDE_BY_2" value="FALSE"/>
+        <item stringID="MAP_CLKOUT_PHASE_SHIFT" value="NONE"/>
+        <item stringID="MAP_CLK_FEEDBACK" value="NONE"/>
+        <item stringID="MAP_DESKEW_ADJUST" value="5"/>
+        <item stringID="MAP_DFS_FREQUENCY_MODE" value="LOW"/>
+        <item stringID="MAP_DLL_FREQUENCY_MODE" value="LOW"/>
+        <item stringID="MAP_DSS_MODE" value="NONE"/>
+        <item stringID="MAP_DUTY_CYCLE_CORRECTION" value="TRUE"/>
+        <item stringID="MAP_STARTUP_WAIT" value="FALSE"/>
+        <item stringID="MAP_VERY_HIGH_FREQUENCY" value="FALSE"/>
+        <item stringID="MAP_CLKFX_DIVIDE" value="5"/>
+        <item stringID="MAP_CLKFX_MULTIPLY" value="11"/>
+        <item stringID="MAP_CLKIN_PERIOD" value="20.000000"/>
+        <item stringID="MAP_PHASE_SHIFT" value="0"/>
+      </section>
+      <section stringID="MAP_CONTROL_SET_INFORMATION">
+        <item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="40"/>
+        <tree stringID="MAP_CONTROL_SET_HIERARCHY">
+          <property stringID="MAP_CLOCK_SIGNAL"/>
+          <property stringID="MAP_RESET_SIGNAL"/>
+          <property stringID="MAP_SET_SIGNAL"/>
+          <property stringID="MAP_ENABLE_SIGNAL"/>
+          <property label="Slice&#xA;Load Count" stringID="MAP_SLICE_LOAD_COUNT"/>
+          <property label="Bel&#xA;Load Count" stringID="MAP_BEL_LOAD_COUNT"/>
+        </tree>
+      </section>
+    </task>
+    <section stringID="MAP_RAM_FIFO_DATA">
+      <item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="7"/>
+      <item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="1"/>
+    </section>
+    <section stringID="MAP_IP_DATA">
+      <item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
+      <item AVAILABLE="128" dataType="int" stringID="MAP_NUM_BUFH" value="0"/>
+      <item AVAILABLE="8" dataType="int" stringID="MAP_NUM_BUFPLL" value="0"/>
+      <item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BUFPLL_MCB" value="0"/>
+      <item AVAILABLE="16" dataType="int" stringID="MAP_NUM_DSP48A1" value="0"/>
+      <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_GTPA1_DUAL" value="0"/>
+      <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_ICAP" value="0"/>
+      <item AVAILABLE="2" dataType="int" stringID="MAP_NUM_MCB" value="0"/>
+      <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_PCIE_A1" value="0"/>
+      <item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PCILOGICSE" value="0"/>
+      <item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PLL_ADV" value="0"/>
+      <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_PMV" value="0"/>
+      <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_STARTUP" value="0"/>
+      <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
+    </section>
+    <section stringID="MAP_BUFG_DATA">
+      <item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="1"/>
+      <item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
+      <item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
+      <item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
+      <item dataType="int" stringID="MAP_RPMS" value="0"/>
+      <item stringID="MAP_CLKDV_DIVIDE" value="2.0"/>
+      <item stringID="MAP_CLKIN_DIVIDE_BY_2" value="FALSE"/>
+      <item stringID="MAP_CLKOUT_PHASE_SHIFT" value="NONE"/>
+      <item stringID="MAP_CLK_FEEDBACK" value="NONE"/>
+      <item stringID="MAP_DESKEW_ADJUST" value="5"/>
+      <item stringID="MAP_DFS_FREQUENCY_MODE" value="LOW"/>
+      <item stringID="MAP_DLL_FREQUENCY_MODE" value="LOW"/>
+      <item stringID="MAP_DSS_MODE" value="NONE"/>
+      <item stringID="MAP_DUTY_CYCLE_CORRECTION" value="TRUE"/>
+      <item stringID="MAP_STARTUP_WAIT" value="FALSE"/>
+      <item stringID="MAP_VERY_HIGH_FREQUENCY" value="FALSE"/>
+      <item stringID="MAP_CLKFX_DIVIDE" value="5"/>
+      <item stringID="MAP_CLKFX_MULTIPLY" value="11"/>
+      <item stringID="MAP_CLKIN_PERIOD" value="20.000000"/>
+      <item stringID="MAP_PHASE_SHIFT" value="0"/>
+    </section>
+  </application>
+
+</document>
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr_ngdbuild.xrpt b/MCL86jr/FPGA/MCL86jr/MCL86jr_ngdbuild.xrpt
new file mode 100644
index 0000000..09e046f
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr_ngdbuild.xrpt
@@ -0,0 +1,149 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="nt64" product="ISE" version="14.7">
+
+  <!--The data in this file is primarily intended for consumption by Xilinx tools.
+    The structure and the elements are likely to change over the next few releases.
+    This means code written to parse this file will need to be revisited each subsequent release.-->
+
+  <application stringID="NgdBuild" timeStamp="Wed Nov 11 19:10:20 2020">
+    <section stringID="User_Env">
+      <table stringID="User_EnvVar">
+        <column stringID="variable"/>
+        <column stringID="value"/>
+        <row stringID="row" value="0">
+          <item stringID="variable" value="Path"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ProgramData\Oracle\Java\javapath;C:\Program Files (x86)\SemanticDesigns\DMS\Executables;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\Intel\WiFi\bin\;C:\Program Files\Common Files\Intel\WirelessCommon\;C:\altera_lite\15.1\modelsim_ase\win32aloem;C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem"/>
+        </row>
+        <row stringID="row" value="1">
+          <item stringID="variable" value="PATHEXT"/>
+          <item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
+        </row>
+        <row stringID="row" value="2">
+          <item stringID="variable" value="XILINX"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\"/>
+        </row>
+        <row stringID="row" value="3">
+          <item stringID="variable" value="XILINX_DSP"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE"/>
+        </row>
+        <row stringID="row" value="4">
+          <item stringID="variable" value="XILINX_EDK"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\EDK"/>
+        </row>
+        <row stringID="row" value="5">
+          <item stringID="variable" value="XILINX_PLANAHEAD"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\PlanAhead"/>
+        </row>
+      </table>
+      <item stringID="User_EnvOs" value="OS Information">
+        <item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
+        <item stringID="User_EnvOsrelease" value="Service Pack 1  (build 7601)"/>
+      </item>
+      <item stringID="User_EnvHost" value="MicroCoreLabs"/>
+      <table stringID="User_EnvCpu">
+        <column stringID="arch"/>
+        <column stringID="speed"/>
+        <row stringID="row" value="0">
+          <item stringID="arch" value="Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz"/>
+          <item stringID="speed" value="2492 MHz"/>
+        </row>
+      </table>
+    </section>
+    <task stringID="NGDBUILD_OPTION_SUMMARY">
+      <section stringID="NGDBUILD_OPTION_SUMMARY">
+        <item DEFAULT="None" label="-intstyle" stringID="NGDBUILD_intstyle" value="ise"/>
+        <item DEFAULT="None" label="-dd" stringID="NGDBUILD_output_dir" value="_ngo"/>
+        <item DEFAULT="None" label="-p" stringID="NGDBUILD_partname" value="xc6slx9-tqg144-3"/>
+        <item DEFAULT="None" label="-sd" stringID="NGDBUILD_search_path" value="ipcore_dir"/>
+        <item DEFAULT="None" label="-uc" stringID="NGDBUILD_ucf_file" value="MCL86jr.ucf"/>
+      </section>
+    </task>
+    <task stringID="NGDBUILD_REPORT">
+      <section stringID="NGDBUILD_DESIGN_SUMMARY">
+        <item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
+        <item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="0"/>
+        <item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="1"/>
+      </section>
+      <section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
+        <item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_DCM_SP" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_FD" value="48"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_FDE" value="183"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_FDR" value="125"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="503"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_FDS" value="13"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="20"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_GND" value="2"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="5"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_INV" value="15"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_IOBUF" value="16"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="60"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="87"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="116"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="73"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="223"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="384"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="175"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="59"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_MUXF8" value="25"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="53"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_RAMB16BWER" value="7"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_RAMB8BWER" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="114"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_VCC" value="2"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="186"/>
+      </section>
+      <section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
+        <item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_DCM_SP" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_FD" value="48"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_FDE" value="183"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_FDR" value="125"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="503"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_FDS" value="13"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="20"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_GND" value="2"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="21"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_INV" value="15"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="60"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="87"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="116"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="73"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="223"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="384"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="175"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="59"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_MUXF8" value="25"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="53"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="16"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_PULLDOWN" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_RAMB16BWER" value="7"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_RAMB8BWER" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="114"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_VCC" value="2"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="186"/>
+      </section>
+      <section stringID="NGDBUILD_CORE_SUMMARY">
+        <item COUNT="1" stringID="NGDBUILD_CORE" value="blk_mem_gen_v7_3, Xilinx CORE Generator 14.7"/>
+        <section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
+          <section stringID="NGDBUILD_CORE_INSTANCES">
+            <scope stringID="NGDBUILD_CORE_INSTANCE" value="EU4Kx32">
+              <item stringID="NGDBUILD_CORE_INFO" type="blk_mem_gen_v7_3" value="EU4Kx32"/>
+              <item c_addra_width="12" c_addrb_width="12" c_algorithm="1" c_axi_id_width="4" c_axi_slave_type="0" c_axi_type="1" c_byte_size="9" c_common_clk="0" c_default_data="0" c_disable_warn_bhv_coll="0" c_disable_warn_bhv_range="0" c_elaboration_dir="masked_value" c_enable_32bit_address="0" c_family="spartan6" c_has_axi_id="0" c_has_ena="0" c_has_enb="0" c_has_injecterr="0" c_has_mem_output_regs_a="0" c_has_mem_output_regs_b="0" c_has_mux_output_regs_a="0" c_has_mux_output_regs_b="0" c_has_regcea="0" c_has_regceb="0" c_has_rsta="0" c_has_rstb="0" c_has_softecc_input_regs_a="0" c_has_softecc_output_regs_b="0" c_init_file="BlankString" c_init_file_name="fname.mif" c_inita_val="0" c_initb_val="0" c_interface_type="0" c_load_init_file="1" c_mem_type="3" c_mux_pipeline_stages="0" c_prim_type="1" c_read_depth_a="4096" c_read_depth_b="4096" c_read_width_a="32" c_read_width_b="32" c_rst_priority_a="CE" c_rst_priority_b="CE" c_rst_type="SYNC" c_rstram_a="0" c_rstram_b="0" c_sim_collision_check="ALL" c_use_bram_block="0" c_use_byte_wea="0" c_use_byte_web="0" c_use_default_data="0" c_use_ecc="0" c_use_softecc="0" c_wea_width="1" c_web_width="1" c_write_depth_a="4096" c_write_depth_b="4096" c_write_mode_a="WRITE_FIRST" c_write_mode_b="WRITE_FIRST" c_write_width_a="32" c_write_width_b="32" c_xdevicefamily="spartan6" stringID="NGDBUILD_CORE_PARAMETERS" value="EU4Kx32"/>
+            </scope>
+            <scope stringID="NGDBUILD_CORE_INSTANCE" value="spartan6_pll">
+              <item stringID="NGDBUILD_CORE_INFO" type="clk_wiz_v3_6" value="spartan6_pll"/>
+              <item clkin1_period="20.0" clkin2_period="20.0" clock_mgr_type="AUTO" component_name="spartan6_pll" feedback_source="FDBK_AUTO" feedback_type="SINGLE" manual_override="false" num_out_clk="1" primtype_sel="DCM_SP" stringID="NGDBUILD_CORE_PARAMETERS" use_clk_valid="false" use_dyn_phase_shift="false" use_dyn_reconfig="false" use_freeze="false" use_inclk_stopped="false" use_inclk_switchover="false" use_locked="false" use_max_i_jitter="false" use_min_o_jitter="false" use_phase_alignment="false" use_power_down="false" use_reset="false" use_status="false" value="spartan6_pll"/>
+            </scope>
+          </section>
+        </section>
+      </section>
+    </task>
+  </application>
+
+</document>
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr_pad.csv b/MCL86jr/FPGA/MCL86jr/MCL86jr_pad.csv
new file mode 100644
index 0000000..d22333e
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr_pad.csv
@@ -0,0 +1,175 @@
+#Release 14.7 - par P.20131013 (nt64)
+#Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+#Wed Nov 11 19:11:33 2020
+
+#
+## NOTE: This file is designed to be imported into a spreadsheet program
+# such as Microsoft Excel for viewing, printing and sorting. The |
+# character is used as the data field separator. This file is also designed
+# to support parsing.
+#
+#INPUT FILE:       MCL86jr_map.ncd
+#OUTPUT FILE:      MCL86jr_pad.csv
+#PART TYPE:        xc6slx9
+#SPEED GRADE:      -3
+#PACKAGE:          tqg144
+#
+# Pinout by Pin Number:
+# 
+# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
+Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity,
+P1,A13,IOB,IO_L83N_VREF_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
+P2,A16,IOB,IO_L83P_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
+P3,,,GND,,,,,,,,,,,,
+P4,,,VCCO_3,,,3,,,,,3.30,,,,
+P5,A12,IOB,IO_L52N_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
+P6,A17,IOB,IO_L52P_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
+P7,A11,IOB,IO_L51N_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
+P8,A18,IOB,IO_L51P_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
+P9,A10,IOB,IO_L50N_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
+P10,A19,IOB,IO_L50P_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
+P11,A9,IOB,IO_L49N_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
+P12,SSO_n,IOB,IO_L49P_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,NO,NONE,
+P13,,,GND,,,,,,,,,,,,
+P14,A8,IOB,IO_L44N_GCLK20_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,YES,NONE,
+P15,,IOBM,IO_L44P_GCLK21_3,UNUSED,,3,,,,,,,,,
+P16,BUF2_DIR,IOB,IO_L43N_GCLK22_IRDY2_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,NO,NONE,
+P17,,IOBM,IO_L43P_GCLK23_3,UNUSED,,3,,,,,,,,,
+P18,,,VCCO_3,,,3,,,,,3.30,,,,
+P19,,,VCCINT,,,,,,,,1.2,,,,
+P20,,,VCCAUX,,,,,,,,2.5,,,,
+P21,BUF2_OE_n,IOB,IO_L42N_GCLK24_3,OUTPUT,PCI33_3,3,,,,,,LOCATED,NO,NONE,
+P22,AD7,IOB,IO_L42P_GCLK25_TRDY2_3,BIDIR,PCI33_3,3,,,,NONE,,LOCATED,YES,NONE,
+P23,AD6,IOB,IO_L41N_GCLK26_3,BIDIR,PCI33_3,3,,,,NONE,,LOCATED,YES,NONE,
+P24,,IOBM,IO_L41P_GCLK27_3,UNUSED,,3,,,,,,,,,
+P25,,,GND,,,,,,,,,,,,
+P26,AD5,IOB,IO_L37N_3,BIDIR,PCI33_3,3,,,,NONE,,LOCATED,YES,NONE,
+P27,AD4,IOB,IO_L37P_3,BIDIR,PCI33_3,3,,,,NONE,,LOCATED,YES,NONE,
+P28,,,VCCINT,,,,,,,,1.2,,,,
+P29,,IOBS,IO_L36N_3,UNUSED,,3,,,,,,,,,
+P30,,IOBM,IO_L36P_3,UNUSED,,3,,,,,,,,,
+P31,,,VCCO_3,,,3,,,,,3.30,,,,
+P32,AD3,IOB,IO_L2N_3,BIDIR,PCI33_3,3,,,,NONE,,LOCATED,YES,NONE,
+P33,AD2,IOB,IO_L2P_3,BIDIR,PCI33_3,3,,,,NONE,,LOCATED,YES,NONE,
+P34,AD1,IOB,IO_L1N_VREF_3,BIDIR,PCI33_3,3,,,,NONE,,LOCATED,YES,NONE,
+P35,AD0,IOB,IO_L1P_3,BIDIR,PCI33_3,3,,,,NONE,,LOCATED,YES,NONE,
+P36,,,VCCAUX,,,,,,,,2.5,,,,
+P37,,,PROGRAM_B_2,,,,,,,,,,,,
+P38,,IOBS,IO_L65N_CSO_B_2,UNUSED,,2,,,,,,,,,
+P39,,IOBM,IO_L65P_INIT_B_2,UNUSED,,2,,,,,,,,,
+P40,,IOBS,IO_L64N_D9_2,UNUSED,,2,,,,,,,,,
+P41,ALE,IOB,IO_L64P_D8_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,YES,NONE,
+P42,,,VCCO_2,,,2,,,,,3.30,,,,
+P43,,IOBS,IO_L62N_D6_2,UNUSED,,2,,,,,,,,,
+P44,NMI,IOB,IO_L62P_D5_2,INPUT,LVCMOS33,2,,,PULLDOWN,NONE,,LOCATED,YES,NONE,
+P45,INTR,IOB,IO_L49N_D4_2,INPUT,PCI33_3,2,,,,NONE,,LOCATED,YES,NONE,
+P46,CLK,IOB,IO_L49P_D3_2,INPUT,PCI33_3,2,,,,NONE,,LOCATED,YES,NONE,
+P47,RESET,IOB,IO_L48N_RDWR_B_VREF_2,INPUT,PCI33_3,2,,,,NONE,,LOCATED,NO,NONE,
+P48,READY,IOB,IO_L48P_D7_2,INPUT,PCI33_3,2,,,,NONE,,LOCATED,YES,NONE,
+P49,,,GND,,,,,,,,,,,,
+P50,RD_n,IOB,IO_L31N_GCLK30_D15_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,YES,NONE,
+P51,WR_n,IOB,IO_L31P_GCLK31_D14_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,YES,NONE,
+P52,,,VCCINT,,,,,,,,1.2,,,,
+P53,,,VCCAUX,,,,,,,,2.5,,,,
+P54,,,GND,,,,,,,,,,,,
+P55,IOM,IOB,IO_L30N_GCLK0_USERCCLK_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,YES,NONE,
+P56,DTR,IOB,IO_L30P_GCLK1_D13_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,YES,NONE,
+P57,DEN,IOB,IO_L14N_D12_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,YES,NONE,
+P58,INTA_n,IOB,IO_L14P_D11_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,YES,NONE,
+P59,BUF1_OE_n,IOB,IO_L13N_D10_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,NO,NONE,
+P60,,IOBM,IO_L13P_M1_2,UNUSED,,2,,,,,,,,,
+P61,SRAM_A<4>,IOB,IO_L12N_D2_MISO3_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,NO,NONE,
+P62,SRAM_A<5>,IOB,IO_L12P_D1_MISO2_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,NO,NONE,
+P63,,,VCCO_2,,,2,,,,,3.30,,,,
+P64,,IOBS,IO_L3N_MOSI_CSI_B_MISO0_2,UNUSED,,2,,,,,,,,,
+P65,,IOBM,IO_L3P_D0_DIN_MISO_MISO1_2,UNUSED,,2,,,,,,,,,
+P66,SRAM_A<6>,IOB,IO_L2N_CMPMOSI_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,NO,NONE,
+P67,SRAM_A<7>,IOB,IO_L2P_CMPCLK_2,OUTPUT,PCI33_3,2,,,,,,LOCATED,NO,NONE,
+P68,,,GND,,,,,,,,,,,,
+P69,,IOBS,IO_L1N_M0_CMPMISO_2,UNUSED,,2,,,,,,,,,
+P70,,IOBM,IO_L1P_CCLK_2,UNUSED,,2,,,,,,,,,
+P71,,,DONE_2,,,,,,,,,,,,
+P72,,,CMPCS_B_2,,,,,,,,,,,,
+P73,,,SUSPEND,,,,,,,,,,,,
+P74,SRAM_A<12>,IOB,IO_L74N_DOUT_BUSY_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
+P75,SRAM_A<14>,IOB,IO_L74P_AWAKE_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
+P76,,,VCCO_1,,,1,,,,,3.30,,,,
+P77,,,GND,,,,,,,,,,,,
+P78,SRAM_A<16>,IOB,IO_L47N_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
+P79,SRAM_A<17>,IOB,IO_L47P_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
+P80,SRAM_D<3>,IOB,IO_L46N_1,BIDIR,PCI33_3,1,,,,NONE,,LOCATED,NO,NONE,
+P81,SRAM_D<4>,IOB,IO_L46P_1,BIDIR,PCI33_3,1,,,,NONE,,LOCATED,NO,NONE,
+P82,SRAM_D<5>,IOB,IO_L45N_1,BIDIR,PCI33_3,1,,,,NONE,,LOCATED,NO,NONE,
+P83,SRAM_D<6>,IOB,IO_L45P_1,BIDIR,PCI33_3,1,,,,NONE,,LOCATED,NO,NONE,
+P84,CORE_CLK,IOB,IO_L43N_GCLK4_1,INPUT,PCI33_3,1,,,,NONE,,LOCATED,NO,NONE,
+P85,SRAM_D<7>,IOB,IO_L43P_GCLK5_1,BIDIR,PCI33_3,1,,,,NONE,,LOCATED,NO,NONE,
+P86,,,VCCO_1,,,1,,,,,3.30,,,,
+P87,SRAM_CE_n,IOB,IO_L42N_GCLK6_TRDY1_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
+P88,SRAM_A<10>,IOB,IO_L42P_GCLK7_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
+P89,,,VCCINT,,,,,,,,1.2,,,,
+P90,,,VCCAUX,,,,,,,,2.5,,,,
+P91,,,GND,,,,,,,,,,,,
+P92,SRAM_OE_n,IOB,IO_L41N_GCLK8_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
+P93,SRAM_A<11>,IOB,IO_L41P_GCLK9_IRDY1_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
+P94,SRAM_A<9>,IOB,IO_L40N_GCLK10_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
+P95,SRAM_A<8>,IOB,IO_L40P_GCLK11_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
+P96,,,GND,,,,,,,,,,,,
+P97,SRAM_A<13>,IOB,IO_L34N_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
+P98,SRAM_WE_n,IOB,IO_L34P_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
+P99,SRAM_A<18>,IOB,IO_L33N_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
+P100,SRAM_A<15>,IOB,IO_L33P_1,OUTPUT,PCI33_3,1,,,,,,LOCATED,NO,NONE,
+P101,,IOBS,IO_L32N_1,UNUSED,,1,,,,,,,,,
+P102,,IOBM,IO_L32P_1,UNUSED,,1,,,,,,,,,
+P103,,,VCCO_1,,,1,,,,,3.30,,,,
+P104,,IOBS,IO_L1N_VREF_1,UNUSED,,1,,,,,,,,,
+P105,,IOBM,IO_L1P_1,UNUSED,,1,,,,,,,,,
+P106,,,TDO,,,,,,,,,,,,
+P107,,,TMS,,,,,,,,,,,,
+P108,,,GND,,,,,,,,,,,,
+P109,,,TCK,,,,,,,,,,,,
+P110,,,TDI,,,,,,,,,,,,
+P111,LED<0>,IOB,IO_L66N_SCP0_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
+P112,LED<1>,IOB,IO_L66P_SCP1_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
+P113,,,GND,,,,,,,,,,,,
+P114,LED<2>,IOB,IO_L65N_SCP2_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
+P115,,IOBM,IO_L65P_SCP3_0,UNUSED,,0,,,,,,,,,
+P116,LED<3>,IOB,IO_L64N_SCP4_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
+P117,SRAM_D<2>,IOB,IO_L64P_SCP5_0,BIDIR,PCI33_3,0,,,,NONE,,LOCATED,NO,NONE,
+P118,SRAM_D<1>,IOB,IO_L63N_SCP6_0,BIDIR,PCI33_3,0,,,,NONE,,LOCATED,NO,NONE,
+P119,SRAM_D<0>,IOB,IO_L63P_SCP7_0,BIDIR,PCI33_3,0,,,,NONE,,LOCATED,NO,NONE,
+P120,LED<4>,IOB,IO_L62N_VREF_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
+P121,LED<5>,IOB,IO_L62P_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
+P122,,,VCCO_0,,,0,,,,,3.30,,,,
+P123,SRAM_A<3>,IOB,IO_L37N_GCLK12_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
+P124,SRAM_A<2>,IOB,IO_L37P_GCLK13_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
+P125,,,VCCO_0,,,0,,,,,3.30,,,,
+P126,SRAM_A<1>,IOB,IO_L36N_GCLK14_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
+P127,LED<6>,IOB,IO_L36P_GCLK15_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
+P128,,,VCCINT,,,,,,,,1.2,,,,
+P129,,,VCCAUX,,,,,,,,2.5,,,,
+P130,,,GND,,,,,,,,,,,,
+P131,LED<7>,IOB,IO_L35N_GCLK16_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
+P132,SRAM_A<0>,IOB,IO_L35P_GCLK17_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,NO,NONE,
+P133,,IOBS,IO_L34N_GCLK18_0,UNUSED,,0,,,,,,,,,
+P134,,IOBM,IO_L34P_GCLK19_0,UNUSED,,0,,,,,,,,,
+P135,,,VCCO_0,,,0,,,,,3.30,,,,
+P136,,,GND,,,,,,,,,,,,
+P137,,IOBS,IO_L4N_0,UNUSED,,0,,,,,,,,,
+P138,,IOBM,IO_L4P_0,UNUSED,,0,,,,,,,,,
+P139,,IOBS,IO_L3N_0,UNUSED,,0,,,,,,,,,
+P140,,IOBM,IO_L3P_0,UNUSED,,0,,,,,,,,,
+P141,,IOBS,IO_L2N_0,UNUSED,,0,,,,,,,,,
+P142,A14,IOB,IO_L2P_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,YES,NONE,
+P143,A15,IOB,IO_L1N_VREF_0,OUTPUT,PCI33_3,0,,,,,,LOCATED,YES,NONE,
+P144,,IOBM,IO_L1P_HSWAPEN_0,UNUSED,,0,,,,,,,,,
+
+# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
+# 
+#* Default value.
+#** This default Pullup/Pulldown value can be overridden in Bitgen. 
+#****** Special VCCO requirements may apply. Please consult the device 
+#       family datasheet for specific guideline on VCCO requirements. 
+#
+#
+#
\ No newline at end of file
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr_pad.txt b/MCL86jr/FPGA/MCL86jr/MCL86jr_pad.txt
new file mode 100644
index 0000000..211fb4e
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr_pad.txt
@@ -0,0 +1,174 @@
+Release 14.7 - par P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Wed Nov 11 19:11:33 2020
+
+
+INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process.  These formats are:
+1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
+2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
+3. The <design name>.pad file designed for parsing by customers.  It uses the "|" as a data field separator.
+
+INPUT FILE:       MCL86jr_map.ncd
+OUTPUT FILE:      MCL86jr_pad.txt
+PART TYPE:        xc6slx9
+SPEED GRADE:      -3
+PACKAGE:          tqg144
+
+Pinout by Pin Number:
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+|Pin Number|Signal Name|Pin Usage|Pin Name                  |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+|P1        |A13        |IOB      |IO_L83N_VREF_3            |OUTPUT   |PCI33_3    |3             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P2        |A16        |IOB      |IO_L83P_3                 |OUTPUT   |PCI33_3    |3             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P3        |           |         |GND                       |         |           |              |          |         |           |         |       |          |           |                |
+|P4        |           |         |VCCO_3                    |         |           |3             |          |         |           |         |3.30   |          |           |                |
+|P5        |A12        |IOB      |IO_L52N_3                 |OUTPUT   |PCI33_3    |3             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P6        |A17        |IOB      |IO_L52P_3                 |OUTPUT   |PCI33_3    |3             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P7        |A11        |IOB      |IO_L51N_3                 |OUTPUT   |PCI33_3    |3             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P8        |A18        |IOB      |IO_L51P_3                 |OUTPUT   |PCI33_3    |3             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P9        |A10        |IOB      |IO_L50N_3                 |OUTPUT   |PCI33_3    |3             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P10       |A19        |IOB      |IO_L50P_3                 |OUTPUT   |PCI33_3    |3             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P11       |A9         |IOB      |IO_L49N_3                 |OUTPUT   |PCI33_3    |3             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P12       |SSO_n      |IOB      |IO_L49P_3                 |OUTPUT   |PCI33_3    |3             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P13       |           |         |GND                       |         |           |              |          |         |           |         |       |          |           |                |
+|P14       |A8         |IOB      |IO_L44N_GCLK20_3          |OUTPUT   |PCI33_3    |3             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P15       |           |IOBM     |IO_L44P_GCLK21_3          |UNUSED   |           |3             |          |         |           |         |       |          |           |                |
+|P16       |BUF2_DIR   |IOB      |IO_L43N_GCLK22_IRDY2_3    |OUTPUT   |PCI33_3    |3             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P17       |           |IOBM     |IO_L43P_GCLK23_3          |UNUSED   |           |3             |          |         |           |         |       |          |           |                |
+|P18       |           |         |VCCO_3                    |         |           |3             |          |         |           |         |3.30   |          |           |                |
+|P19       |           |         |VCCINT                    |         |           |              |          |         |           |         |1.2    |          |           |                |
+|P20       |           |         |VCCAUX                    |         |           |              |          |         |           |         |2.5    |          |           |                |
+|P21       |BUF2_OE_n  |IOB      |IO_L42N_GCLK24_3          |OUTPUT   |PCI33_3    |3             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P22       |AD7        |IOB      |IO_L42P_GCLK25_TRDY2_3    |BIDIR    |PCI33_3    |3             |          |         |           |NONE     |       |LOCATED   |YES        |NONE            |
+|P23       |AD6        |IOB      |IO_L41N_GCLK26_3          |BIDIR    |PCI33_3    |3             |          |         |           |NONE     |       |LOCATED   |YES        |NONE            |
+|P24       |           |IOBM     |IO_L41P_GCLK27_3          |UNUSED   |           |3             |          |         |           |         |       |          |           |                |
+|P25       |           |         |GND                       |         |           |              |          |         |           |         |       |          |           |                |
+|P26       |AD5        |IOB      |IO_L37N_3                 |BIDIR    |PCI33_3    |3             |          |         |           |NONE     |       |LOCATED   |YES        |NONE            |
+|P27       |AD4        |IOB      |IO_L37P_3                 |BIDIR    |PCI33_3    |3             |          |         |           |NONE     |       |LOCATED   |YES        |NONE            |
+|P28       |           |         |VCCINT                    |         |           |              |          |         |           |         |1.2    |          |           |                |
+|P29       |           |IOBS     |IO_L36N_3                 |UNUSED   |           |3             |          |         |           |         |       |          |           |                |
+|P30       |           |IOBM     |IO_L36P_3                 |UNUSED   |           |3             |          |         |           |         |       |          |           |                |
+|P31       |           |         |VCCO_3                    |         |           |3             |          |         |           |         |3.30   |          |           |                |
+|P32       |AD3        |IOB      |IO_L2N_3                  |BIDIR    |PCI33_3    |3             |          |         |           |NONE     |       |LOCATED   |YES        |NONE            |
+|P33       |AD2        |IOB      |IO_L2P_3                  |BIDIR    |PCI33_3    |3             |          |         |           |NONE     |       |LOCATED   |YES        |NONE            |
+|P34       |AD1        |IOB      |IO_L1N_VREF_3             |BIDIR    |PCI33_3    |3             |          |         |           |NONE     |       |LOCATED   |YES        |NONE            |
+|P35       |AD0        |IOB      |IO_L1P_3                  |BIDIR    |PCI33_3    |3             |          |         |           |NONE     |       |LOCATED   |YES        |NONE            |
+|P36       |           |         |VCCAUX                    |         |           |              |          |         |           |         |2.5    |          |           |                |
+|P37       |           |         |PROGRAM_B_2               |         |           |              |          |         |           |         |       |          |           |                |
+|P38       |           |IOBS     |IO_L65N_CSO_B_2           |UNUSED   |           |2             |          |         |           |         |       |          |           |                |
+|P39       |           |IOBM     |IO_L65P_INIT_B_2          |UNUSED   |           |2             |          |         |           |         |       |          |           |                |
+|P40       |           |IOBS     |IO_L64N_D9_2              |UNUSED   |           |2             |          |         |           |         |       |          |           |                |
+|P41       |ALE        |IOB      |IO_L64P_D8_2              |OUTPUT   |PCI33_3    |2             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P42       |           |         |VCCO_2                    |         |           |2             |          |         |           |         |3.30   |          |           |                |
+|P43       |           |IOBS     |IO_L62N_D6_2              |UNUSED   |           |2             |          |         |           |         |       |          |           |                |
+|P44       |NMI        |IOB      |IO_L62P_D5_2              |INPUT    |LVCMOS33   |2             |          |         |PULLDOWN   |NONE     |       |LOCATED   |YES        |NONE            |
+|P45       |INTR       |IOB      |IO_L49N_D4_2              |INPUT    |PCI33_3    |2             |          |         |           |NONE     |       |LOCATED   |YES        |NONE            |
+|P46       |CLK        |IOB      |IO_L49P_D3_2              |INPUT    |PCI33_3    |2             |          |         |           |NONE     |       |LOCATED   |YES        |NONE            |
+|P47       |RESET      |IOB      |IO_L48N_RDWR_B_VREF_2     |INPUT    |PCI33_3    |2             |          |         |           |NONE     |       |LOCATED   |NO         |NONE            |
+|P48       |READY      |IOB      |IO_L48P_D7_2              |INPUT    |PCI33_3    |2             |          |         |           |NONE     |       |LOCATED   |YES        |NONE            |
+|P49       |           |         |GND                       |         |           |              |          |         |           |         |       |          |           |                |
+|P50       |RD_n       |IOB      |IO_L31N_GCLK30_D15_2      |OUTPUT   |PCI33_3    |2             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P51       |WR_n       |IOB      |IO_L31P_GCLK31_D14_2      |OUTPUT   |PCI33_3    |2             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P52       |           |         |VCCINT                    |         |           |              |          |         |           |         |1.2    |          |           |                |
+|P53       |           |         |VCCAUX                    |         |           |              |          |         |           |         |2.5    |          |           |                |
+|P54       |           |         |GND                       |         |           |              |          |         |           |         |       |          |           |                |
+|P55       |IOM        |IOB      |IO_L30N_GCLK0_USERCCLK_2  |OUTPUT   |PCI33_3    |2             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P56       |DTR        |IOB      |IO_L30P_GCLK1_D13_2       |OUTPUT   |PCI33_3    |2             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P57       |DEN        |IOB      |IO_L14N_D12_2             |OUTPUT   |PCI33_3    |2             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P58       |INTA_n     |IOB      |IO_L14P_D11_2             |OUTPUT   |PCI33_3    |2             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P59       |BUF1_OE_n  |IOB      |IO_L13N_D10_2             |OUTPUT   |PCI33_3    |2             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P60       |           |IOBM     |IO_L13P_M1_2              |UNUSED   |           |2             |          |         |           |         |       |          |           |                |
+|P61       |SRAM_A<4>  |IOB      |IO_L12N_D2_MISO3_2        |OUTPUT   |PCI33_3    |2             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P62       |SRAM_A<5>  |IOB      |IO_L12P_D1_MISO2_2        |OUTPUT   |PCI33_3    |2             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P63       |           |         |VCCO_2                    |         |           |2             |          |         |           |         |3.30   |          |           |                |
+|P64       |           |IOBS     |IO_L3N_MOSI_CSI_B_MISO0_2 |UNUSED   |           |2             |          |         |           |         |       |          |           |                |
+|P65       |           |IOBM     |IO_L3P_D0_DIN_MISO_MISO1_2|UNUSED   |           |2             |          |         |           |         |       |          |           |                |
+|P66       |SRAM_A<6>  |IOB      |IO_L2N_CMPMOSI_2          |OUTPUT   |PCI33_3    |2             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P67       |SRAM_A<7>  |IOB      |IO_L2P_CMPCLK_2           |OUTPUT   |PCI33_3    |2             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P68       |           |         |GND                       |         |           |              |          |         |           |         |       |          |           |                |
+|P69       |           |IOBS     |IO_L1N_M0_CMPMISO_2       |UNUSED   |           |2             |          |         |           |         |       |          |           |                |
+|P70       |           |IOBM     |IO_L1P_CCLK_2             |UNUSED   |           |2             |          |         |           |         |       |          |           |                |
+|P71       |           |         |DONE_2                    |         |           |              |          |         |           |         |       |          |           |                |
+|P72       |           |         |CMPCS_B_2                 |         |           |              |          |         |           |         |       |          |           |                |
+|P73       |           |         |SUSPEND                   |         |           |              |          |         |           |         |       |          |           |                |
+|P74       |SRAM_A<12> |IOB      |IO_L74N_DOUT_BUSY_1       |OUTPUT   |PCI33_3    |1             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P75       |SRAM_A<14> |IOB      |IO_L74P_AWAKE_1           |OUTPUT   |PCI33_3    |1             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P76       |           |         |VCCO_1                    |         |           |1             |          |         |           |         |3.30   |          |           |                |
+|P77       |           |         |GND                       |         |           |              |          |         |           |         |       |          |           |                |
+|P78       |SRAM_A<16> |IOB      |IO_L47N_1                 |OUTPUT   |PCI33_3    |1             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P79       |SRAM_A<17> |IOB      |IO_L47P_1                 |OUTPUT   |PCI33_3    |1             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P80       |SRAM_D<3>  |IOB      |IO_L46N_1                 |BIDIR    |PCI33_3    |1             |          |         |           |NONE     |       |LOCATED   |NO         |NONE            |
+|P81       |SRAM_D<4>  |IOB      |IO_L46P_1                 |BIDIR    |PCI33_3    |1             |          |         |           |NONE     |       |LOCATED   |NO         |NONE            |
+|P82       |SRAM_D<5>  |IOB      |IO_L45N_1                 |BIDIR    |PCI33_3    |1             |          |         |           |NONE     |       |LOCATED   |NO         |NONE            |
+|P83       |SRAM_D<6>  |IOB      |IO_L45P_1                 |BIDIR    |PCI33_3    |1             |          |         |           |NONE     |       |LOCATED   |NO         |NONE            |
+|P84       |CORE_CLK   |IOB      |IO_L43N_GCLK4_1           |INPUT    |PCI33_3    |1             |          |         |           |NONE     |       |LOCATED   |NO         |NONE            |
+|P85       |SRAM_D<7>  |IOB      |IO_L43P_GCLK5_1           |BIDIR    |PCI33_3    |1             |          |         |           |NONE     |       |LOCATED   |NO         |NONE            |
+|P86       |           |         |VCCO_1                    |         |           |1             |          |         |           |         |3.30   |          |           |                |
+|P87       |SRAM_CE_n  |IOB      |IO_L42N_GCLK6_TRDY1_1     |OUTPUT   |PCI33_3    |1             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P88       |SRAM_A<10> |IOB      |IO_L42P_GCLK7_1           |OUTPUT   |PCI33_3    |1             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P89       |           |         |VCCINT                    |         |           |              |          |         |           |         |1.2    |          |           |                |
+|P90       |           |         |VCCAUX                    |         |           |              |          |         |           |         |2.5    |          |           |                |
+|P91       |           |         |GND                       |         |           |              |          |         |           |         |       |          |           |                |
+|P92       |SRAM_OE_n  |IOB      |IO_L41N_GCLK8_1           |OUTPUT   |PCI33_3    |1             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P93       |SRAM_A<11> |IOB      |IO_L41P_GCLK9_IRDY1_1     |OUTPUT   |PCI33_3    |1             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P94       |SRAM_A<9>  |IOB      |IO_L40N_GCLK10_1          |OUTPUT   |PCI33_3    |1             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P95       |SRAM_A<8>  |IOB      |IO_L40P_GCLK11_1          |OUTPUT   |PCI33_3    |1             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P96       |           |         |GND                       |         |           |              |          |         |           |         |       |          |           |                |
+|P97       |SRAM_A<13> |IOB      |IO_L34N_1                 |OUTPUT   |PCI33_3    |1             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P98       |SRAM_WE_n  |IOB      |IO_L34P_1                 |OUTPUT   |PCI33_3    |1             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P99       |SRAM_A<18> |IOB      |IO_L33N_1                 |OUTPUT   |PCI33_3    |1             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P100      |SRAM_A<15> |IOB      |IO_L33P_1                 |OUTPUT   |PCI33_3    |1             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P101      |           |IOBS     |IO_L32N_1                 |UNUSED   |           |1             |          |         |           |         |       |          |           |                |
+|P102      |           |IOBM     |IO_L32P_1                 |UNUSED   |           |1             |          |         |           |         |       |          |           |                |
+|P103      |           |         |VCCO_1                    |         |           |1             |          |         |           |         |3.30   |          |           |                |
+|P104      |           |IOBS     |IO_L1N_VREF_1             |UNUSED   |           |1             |          |         |           |         |       |          |           |                |
+|P105      |           |IOBM     |IO_L1P_1                  |UNUSED   |           |1             |          |         |           |         |       |          |           |                |
+|P106      |           |         |TDO                       |         |           |              |          |         |           |         |       |          |           |                |
+|P107      |           |         |TMS                       |         |           |              |          |         |           |         |       |          |           |                |
+|P108      |           |         |GND                       |         |           |              |          |         |           |         |       |          |           |                |
+|P109      |           |         |TCK                       |         |           |              |          |         |           |         |       |          |           |                |
+|P110      |           |         |TDI                       |         |           |              |          |         |           |         |       |          |           |                |
+|P111      |LED<0>     |IOB      |IO_L66N_SCP0_0            |OUTPUT   |PCI33_3    |0             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P112      |LED<1>     |IOB      |IO_L66P_SCP1_0            |OUTPUT   |PCI33_3    |0             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P113      |           |         |GND                       |         |           |              |          |         |           |         |       |          |           |                |
+|P114      |LED<2>     |IOB      |IO_L65N_SCP2_0            |OUTPUT   |PCI33_3    |0             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P115      |           |IOBM     |IO_L65P_SCP3_0            |UNUSED   |           |0             |          |         |           |         |       |          |           |                |
+|P116      |LED<3>     |IOB      |IO_L64N_SCP4_0            |OUTPUT   |PCI33_3    |0             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P117      |SRAM_D<2>  |IOB      |IO_L64P_SCP5_0            |BIDIR    |PCI33_3    |0             |          |         |           |NONE     |       |LOCATED   |NO         |NONE            |
+|P118      |SRAM_D<1>  |IOB      |IO_L63N_SCP6_0            |BIDIR    |PCI33_3    |0             |          |         |           |NONE     |       |LOCATED   |NO         |NONE            |
+|P119      |SRAM_D<0>  |IOB      |IO_L63P_SCP7_0            |BIDIR    |PCI33_3    |0             |          |         |           |NONE     |       |LOCATED   |NO         |NONE            |
+|P120      |LED<4>     |IOB      |IO_L62N_VREF_0            |OUTPUT   |PCI33_3    |0             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P121      |LED<5>     |IOB      |IO_L62P_0                 |OUTPUT   |PCI33_3    |0             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P122      |           |         |VCCO_0                    |         |           |0             |          |         |           |         |3.30   |          |           |                |
+|P123      |SRAM_A<3>  |IOB      |IO_L37N_GCLK12_0          |OUTPUT   |PCI33_3    |0             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P124      |SRAM_A<2>  |IOB      |IO_L37P_GCLK13_0          |OUTPUT   |PCI33_3    |0             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P125      |           |         |VCCO_0                    |         |           |0             |          |         |           |         |3.30   |          |           |                |
+|P126      |SRAM_A<1>  |IOB      |IO_L36N_GCLK14_0          |OUTPUT   |PCI33_3    |0             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P127      |LED<6>     |IOB      |IO_L36P_GCLK15_0          |OUTPUT   |PCI33_3    |0             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P128      |           |         |VCCINT                    |         |           |              |          |         |           |         |1.2    |          |           |                |
+|P129      |           |         |VCCAUX                    |         |           |              |          |         |           |         |2.5    |          |           |                |
+|P130      |           |         |GND                       |         |           |              |          |         |           |         |       |          |           |                |
+|P131      |LED<7>     |IOB      |IO_L35N_GCLK16_0          |OUTPUT   |PCI33_3    |0             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P132      |SRAM_A<0>  |IOB      |IO_L35P_GCLK17_0          |OUTPUT   |PCI33_3    |0             |          |         |           |         |       |LOCATED   |NO         |NONE            |
+|P133      |           |IOBS     |IO_L34N_GCLK18_0          |UNUSED   |           |0             |          |         |           |         |       |          |           |                |
+|P134      |           |IOBM     |IO_L34P_GCLK19_0          |UNUSED   |           |0             |          |         |           |         |       |          |           |                |
+|P135      |           |         |VCCO_0                    |         |           |0             |          |         |           |         |3.30   |          |           |                |
+|P136      |           |         |GND                       |         |           |              |          |         |           |         |       |          |           |                |
+|P137      |           |IOBS     |IO_L4N_0                  |UNUSED   |           |0             |          |         |           |         |       |          |           |                |
+|P138      |           |IOBM     |IO_L4P_0                  |UNUSED   |           |0             |          |         |           |         |       |          |           |                |
+|P139      |           |IOBS     |IO_L3N_0                  |UNUSED   |           |0             |          |         |           |         |       |          |           |                |
+|P140      |           |IOBM     |IO_L3P_0                  |UNUSED   |           |0             |          |         |           |         |       |          |           |                |
+|P141      |           |IOBS     |IO_L2N_0                  |UNUSED   |           |0             |          |         |           |         |       |          |           |                |
+|P142      |A14        |IOB      |IO_L2P_0                  |OUTPUT   |PCI33_3    |0             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P143      |A15        |IOB      |IO_L1N_VREF_0             |OUTPUT   |PCI33_3    |0             |          |         |           |         |       |LOCATED   |YES        |NONE            |
+|P144      |           |IOBM     |IO_L1P_HSWAPEN_0          |UNUSED   |           |0             |          |         |           |         |       |          |           |                |
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+* Default value.
+** This default Pullup/Pulldown value can be overridden in Bitgen. 
+****** Special VCCO requirements may apply. Please consult the device 
+       family datasheet for specific guideline on VCCO requirements. 
+
+
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr_par.xrpt b/MCL86jr/FPGA/MCL86jr/MCL86jr_par.xrpt
new file mode 100644
index 0000000..cbc1c2e
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr_par.xrpt
@@ -0,0 +1,1566 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="nt64" product="ISE" version="14.7">
+
+  <!--The data in this file is primarily intended for consumption by Xilinx tools.
+    The structure and the elements are likely to change over the next few releases.
+    This means code written to parse this file will need to be revisited each subsequent release.-->
+
+  <application stringID="par" timeStamp="Wed Nov 11 19:11:03 2020">
+    <section stringID="User_Env">
+      <table stringID="User_EnvVar">
+        <column stringID="variable"/>
+        <column stringID="value"/>
+        <row stringID="row" value="0">
+          <item stringID="variable" value="Path"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ProgramData\Oracle\Java\javapath;C:\Program Files (x86)\SemanticDesigns\DMS\Executables;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\Intel\WiFi\bin\;C:\Program Files\Common Files\Intel\WirelessCommon\;C:\altera_lite\15.1\modelsim_ase\win32aloem;C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem"/>
+        </row>
+        <row stringID="row" value="1">
+          <item stringID="variable" value="PATHEXT"/>
+          <item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
+        </row>
+        <row stringID="row" value="2">
+          <item stringID="variable" value="XILINX"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\"/>
+        </row>
+        <row stringID="row" value="3">
+          <item stringID="variable" value="XILINX_DSP"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE"/>
+        </row>
+        <row stringID="row" value="4">
+          <item stringID="variable" value="XILINX_EDK"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\EDK"/>
+        </row>
+        <row stringID="row" value="5">
+          <item stringID="variable" value="XILINX_PLANAHEAD"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\PlanAhead"/>
+        </row>
+      </table>
+      <item stringID="User_EnvOs" value="OS Information">
+        <item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
+        <item stringID="User_EnvOsrelease" value="Service Pack 1  (build 7601)"/>
+      </item>
+      <item stringID="User_EnvHost" value="MicroCoreLabs"/>
+      <table stringID="User_EnvCpu">
+        <column stringID="arch"/>
+        <column stringID="speed"/>
+        <row stringID="row" value="0">
+          <item stringID="arch" value="Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz"/>
+          <item stringID="speed" value="2492 MHz"/>
+        </row>
+      </table>
+    </section>
+    <task stringID="PAR_OPTION_SUMMARY">
+      <section stringID="PAR_OPTION_SUMMARY">
+        <item DEFAULT="None" label="-xe" stringID="PAR_EXTRA_EFFORTLEVEL" value="n"/>
+        <item DEFAULT="" label="-intstyle" stringID="PAR_INTSTYLE" value="ise"/>
+        <item DEFAULT="off" label="-mt" stringID="PAR_MULTI_THREADING" value="off"/>
+        <item DEFAULT="std" label="-ol" stringID="PAR_OVERALL_EFFORTLEVEL" value="high"/>
+        <item DEFAULT="false" label="-w" stringID="PAR_OVERWRITE_OUTPUT" value="true"/>
+      </section>
+    </task>
+    <task stringID="PAR_PAR">
+      <section stringID="PAR_DESIGN_SUMMARY">
+        <item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="33 secs "/>
+        <item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="33 secs "/>
+        <item dataType="int" stringID="PAR_UNROUTES" value="0"/>
+        <item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
+        <item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="34 secs "/>
+        <item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="34 secs "/>
+      </section>
+    </task>
+    <task stringID="PAR_par">
+      <section stringID="PAR_DLY_CLK_REPORT"/>
+      <section stringID="PAR_CLOCK_REPORT">
+        <table stringID="PAR_CLOCK_TABLE">
+          <column label="Clock Net" stringID="CLOCK_NET"/>
+          <column label="Routed" stringID="ROUTED"/>
+          <column label="Resource" stringID="RESOURCE"/>
+          <column label="Locked" stringID="LOCKED"/>
+          <column label="Fanout" stringID="FANOUT"/>
+          <column label="Net Skew(ns)" stringID="NET_SKEW"/>
+          <column label="Max Delay(ns)" stringID="MAX_DELAY"/>
+          <row stringID="row" value="1">
+            <item label="Clock Net" stringID="CLOCK_NET" value="core_clk_int"/>
+            <item label="Routed" stringID="ROUTED" value="ROUTED"/>
+            <item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y3"/>
+            <item label="Locked" stringID="LOCKED" value="No"/>
+            <item dataType="float" label="Fanout" stringID="FANOUT" value="321.000000"/>
+            <item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.601000"/>
+            <item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.669000"/>
+          </row>
+        </table>
+      </section>
+      <section stringID="PAR_PAD_PIN_REPORT">
+        <table stringID="PAR_PINOUT_BY_PIN_NUMBER">
+          <column label="Pin&#xA;Number" sort="smart" stringID="Pin_Number"/>
+          <column label="Signal&#xA;Name" stringID="Signal_Name"/>
+          <column label="Pin&#xA;Usage" stringID="Pin_Usage"/>
+          <column label="Pin&#xA;Name" sort="smart" stringID="Pin_Name"/>
+          <column stringID="Direction"/>
+          <column label="IO&#xA;Standard" sort="smart" stringID="IO_Standard"/>
+          <column label="IO Bank&#xA;Number" stringID="IO_Bank_Number"/>
+          <column label="Drive&#xA;(mA)" stringID="Drive"/>
+          <column label="Slew&#xA;Rate" stringID="Slew_Rate"/>
+          <column label="Termination" stringID="Termination"/>
+          <column label="IOB&#xA;Delay" stringID="IOB_Delay"/>
+          <column label="Voltage" stringID="Voltage"/>
+          <column label="Constraint" stringID="Constraint"/>
+          <column label="IO&#xA;Register" stringID="IO_Register"/>
+          <column label="Signal&#xA;Integrity" stringID="Signal_Integrity"/>
+          <row stringID="row" value="1">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P1"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="A13"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L83N_VREF_3"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="2">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P2"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="A16"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L83P_3"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="3">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P3"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="4">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P4"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Voltage" stringID="Voltage" value="3.30"/>
+          </row>
+          <row stringID="row" value="5">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P5"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="A12"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L52N_3"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="6">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P6"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="A17"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L52P_3"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="7">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P7"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="A11"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L51N_3"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="8">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P8"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="A18"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L51P_3"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="9">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P9"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="A10"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L50N_3"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="10">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P10"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="A19"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L50P_3"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="11">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P11"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="A9"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L49N_3"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="12">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P12"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="SSO_n"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L49P_3"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="13">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P13"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="14">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P14"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="A8"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L44N_GCLK20_3"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="15">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P15"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L44P_GCLK21_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="16">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P16"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="BUF2_DIR"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L43N_GCLK22_IRDY2_3"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="17">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P17"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L43P_GCLK23_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="18">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P18"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Voltage" stringID="Voltage" value="3.30"/>
+          </row>
+          <row stringID="row" value="19">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P19"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCINT"/>
+            <item label="Voltage" stringID="Voltage" value="1.2"/>
+          </row>
+          <row stringID="row" value="20">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P20"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCAUX"/>
+            <item label="Voltage" stringID="Voltage" value="2.5"/>
+          </row>
+          <row stringID="row" value="21">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P21"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="BUF2_OE_n"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L42N_GCLK24_3"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="22">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P22"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="AD7"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L42P_GCLK25_TRDY2_3"/>
+            <item stringID="Direction" value="BIDIR"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="IOB&#xA;Delay" stringID="IOB_Delay" value="NONE"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="23">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P23"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="AD6"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L41N_GCLK26_3"/>
+            <item stringID="Direction" value="BIDIR"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="IOB&#xA;Delay" stringID="IOB_Delay" value="NONE"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="24">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P24"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L41P_GCLK27_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="25">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P25"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="26">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P26"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="AD5"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L37N_3"/>
+            <item stringID="Direction" value="BIDIR"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="IOB&#xA;Delay" stringID="IOB_Delay" value="NONE"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="27">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P27"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="AD4"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L37P_3"/>
+            <item stringID="Direction" value="BIDIR"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="IOB&#xA;Delay" stringID="IOB_Delay" value="NONE"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="28">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P28"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCINT"/>
+            <item label="Voltage" stringID="Voltage" value="1.2"/>
+          </row>
+          <row stringID="row" value="29">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P29"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L36N_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="30">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P30"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L36P_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="31">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P31"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Voltage" stringID="Voltage" value="3.30"/>
+          </row>
+          <row stringID="row" value="32">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P32"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="AD3"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L2N_3"/>
+            <item stringID="Direction" value="BIDIR"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="IOB&#xA;Delay" stringID="IOB_Delay" value="NONE"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="33">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P33"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="AD2"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L2P_3"/>
+            <item stringID="Direction" value="BIDIR"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="IOB&#xA;Delay" stringID="IOB_Delay" value="NONE"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="34">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P34"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="AD1"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L1N_VREF_3"/>
+            <item stringID="Direction" value="BIDIR"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="IOB&#xA;Delay" stringID="IOB_Delay" value="NONE"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="35">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P35"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="AD0"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L1P_3"/>
+            <item stringID="Direction" value="BIDIR"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="IOB&#xA;Delay" stringID="IOB_Delay" value="NONE"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="36">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P36"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCAUX"/>
+            <item label="Voltage" stringID="Voltage" value="2.5"/>
+          </row>
+          <row stringID="row" value="37">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P37"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="PROGRAM_B_2"/>
+          </row>
+          <row stringID="row" value="38">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P38"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L65N_CSO_B_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="39">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P39"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L65P_INIT_B_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="40">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P40"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L64N_D9_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="41">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P41"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="ALE"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L64P_D8_2"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="42">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P42"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_2"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+            <item label="Voltage" stringID="Voltage" value="3.30"/>
+          </row>
+          <row stringID="row" value="43">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P43"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L62N_D6_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="44">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P44"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="NMI"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L62P_D5_2"/>
+            <item stringID="Direction" value="INPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS33"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+            <item label="Termination" stringID="Termination" value="PULLDOWN"/>
+            <item label="IOB&#xA;Delay" stringID="IOB_Delay" value="NONE"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="45">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P45"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="INTR"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L49N_D4_2"/>
+            <item stringID="Direction" value="INPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
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+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="46">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P46"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="CLK"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L49P_D3_2"/>
+            <item stringID="Direction" value="INPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
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+          <row stringID="row" value="47">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P47"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="RESET"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L48N_RDWR_B_VREF_2"/>
+            <item stringID="Direction" value="INPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
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+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
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+          <row stringID="row" value="48">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P48"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="READY"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L48P_D7_2"/>
+            <item stringID="Direction" value="INPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
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+          <row stringID="row" value="49">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P49"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="50">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P50"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="RD_n"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L31N_GCLK30_D15_2"/>
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+          <row stringID="row" value="51">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P51"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="WR_n"/>
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+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L31P_GCLK31_D14_2"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
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+          </row>
+          <row stringID="row" value="52">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P52"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCINT"/>
+            <item label="Voltage" stringID="Voltage" value="1.2"/>
+          </row>
+          <row stringID="row" value="53">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P53"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCAUX"/>
+            <item label="Voltage" stringID="Voltage" value="2.5"/>
+          </row>
+          <row stringID="row" value="54">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P54"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="55">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P55"/>
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+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L30N_GCLK0_USERCCLK_2"/>
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+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
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+          </row>
+          <row stringID="row" value="56">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P56"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="DTR"/>
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+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L30P_GCLK1_D13_2"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
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+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
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+          </row>
+          <row stringID="row" value="57">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P57"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="DEN"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L14N_D12_2"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
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+          <row stringID="row" value="58">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P58"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="INTA_n"/>
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+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L14P_D11_2"/>
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+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
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+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
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+          <row stringID="row" value="59">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P59"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="BUF1_OE_n"/>
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+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L13N_D10_2"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
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+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="60">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P60"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L13P_M1_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="61">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P61"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="SRAM_A&lt;4>"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L12N_D2_MISO3_2"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
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+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
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+          </row>
+          <row stringID="row" value="62">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P62"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="SRAM_A&lt;5>"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L12P_D1_MISO2_2"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="63">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P63"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_2"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+            <item label="Voltage" stringID="Voltage" value="3.30"/>
+          </row>
+          <row stringID="row" value="64">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P64"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L3N_MOSI_CSI_B_MISO0_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="65">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P65"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L3P_D0_DIN_MISO_MISO1_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="66">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P66"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="SRAM_A&lt;6>"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L2N_CMPMOSI_2"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
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+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
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+          </row>
+          <row stringID="row" value="67">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P67"/>
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+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L2P_CMPCLK_2"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
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+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="68">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P68"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="69">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P69"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L1N_M0_CMPMISO_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="70">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P70"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L1P_CCLK_2"/>
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+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="71">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P71"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="DONE_2"/>
+          </row>
+          <row stringID="row" value="72">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P72"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="CMPCS_B_2"/>
+          </row>
+          <row stringID="row" value="73">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P73"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="SUSPEND"/>
+          </row>
+          <row stringID="row" value="74">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P74"/>
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+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L74N_DOUT_BUSY_1"/>
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+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
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+          <row stringID="row" value="75">
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+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L74P_AWAKE_1"/>
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+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
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+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
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+          </row>
+          <row stringID="row" value="76">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P76"/>
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+            <item label="Voltage" stringID="Voltage" value="3.30"/>
+          </row>
+          <row stringID="row" value="77">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P77"/>
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+          <row stringID="row" value="78">
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+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L47N_1"/>
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+          <row stringID="row" value="79">
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+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L47P_1"/>
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+          </row>
+          <row stringID="row" value="80">
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+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L46N_1"/>
+            <item stringID="Direction" value="BIDIR"/>
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+          <row stringID="row" value="81">
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+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L46P_1"/>
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+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
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+          </row>
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+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L63P_SCP7_0"/>
+            <item stringID="Direction" value="BIDIR"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="IOB&#xA;Delay" stringID="IOB_Delay" value="NONE"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="120">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P120"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="LED&lt;4>"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L62N_VREF_0"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="121">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P121"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="LED&lt;5>"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L62P_0"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="122">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P122"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_0"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="Voltage" stringID="Voltage" value="3.30"/>
+          </row>
+          <row stringID="row" value="123">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P123"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="SRAM_A&lt;3>"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L37N_GCLK12_0"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="124">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P124"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="SRAM_A&lt;2>"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L37P_GCLK13_0"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="125">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P125"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_0"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="Voltage" stringID="Voltage" value="3.30"/>
+          </row>
+          <row stringID="row" value="126">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P126"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="SRAM_A&lt;1>"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L36N_GCLK14_0"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="127">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P127"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="LED&lt;6>"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L36P_GCLK15_0"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="128">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P128"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCINT"/>
+            <item label="Voltage" stringID="Voltage" value="1.2"/>
+          </row>
+          <row stringID="row" value="129">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P129"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCAUX"/>
+            <item label="Voltage" stringID="Voltage" value="2.5"/>
+          </row>
+          <row stringID="row" value="130">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P130"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="131">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P131"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="LED&lt;7>"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L35N_GCLK16_0"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="132">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P132"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="SRAM_A&lt;0>"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L35P_GCLK17_0"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="133">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P133"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L34N_GCLK18_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="134">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P134"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L34P_GCLK19_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="135">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P135"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_0"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="Voltage" stringID="Voltage" value="3.30"/>
+          </row>
+          <row stringID="row" value="136">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P136"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="137">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P137"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L4N_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="138">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P138"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L4P_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="139">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P139"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L3N_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="140">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P140"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L3P_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="141">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P141"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L2N_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="142">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P142"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="A14"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L2P_0"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="143">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P143"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="A15"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L1N_VREF_0"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="PCI33_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="144">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P144"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L1P_HSWAPEN_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+        </table>
+        <table stringID="PAR_PSEUDO_LOGIC">
+          <column label="Signal&#xA;Name" stringID="Signal_Name"/>
+          <column stringID="Type"/>
+          <column stringID="Site"/>
+        </table>
+      </section>
+      <section stringID="PAR_UNROUTES_REPORT">
+        <item dataType="int" stringID="PAR_UNROUTED_NETS" value="0"/>
+        <item dataType="int" stringID="PAR_TOTAL_SOURCELESS_NETS" value="0"/>
+        <item dataType="int" stringID="PAR_TOTAL_LOADLESS_NETS" value="0"/>
+      </section>
+    </task>
+  </application>
+
+  <application stringID="Par" timeStamp="Wed Nov 11 19:11:03 2020">
+    <section stringID="User_Env">
+      <table stringID="User_EnvVar">
+        <column stringID="variable"/>
+        <column stringID="value"/>
+        <row stringID="row" value="0">
+          <item stringID="variable" value="Path"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ProgramData\Oracle\Java\javapath;C:\Program Files (x86)\SemanticDesigns\DMS\Executables;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\Intel\WiFi\bin\;C:\Program Files\Common Files\Intel\WirelessCommon\;C:\altera_lite\15.1\modelsim_ase\win32aloem;C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem"/>
+        </row>
+        <row stringID="row" value="1">
+          <item stringID="variable" value="PATHEXT"/>
+          <item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
+        </row>
+        <row stringID="row" value="2">
+          <item stringID="variable" value="XILINX"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\"/>
+        </row>
+        <row stringID="row" value="3">
+          <item stringID="variable" value="XILINX_DSP"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE"/>
+        </row>
+        <row stringID="row" value="4">
+          <item stringID="variable" value="XILINX_EDK"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\EDK"/>
+        </row>
+        <row stringID="row" value="5">
+          <item stringID="variable" value="XILINX_PLANAHEAD"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\PlanAhead"/>
+        </row>
+      </table>
+      <item stringID="User_EnvOs" value="OS Information">
+        <item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
+        <item stringID="User_EnvOsrelease" value="Service Pack 1  (build 7601)"/>
+      </item>
+      <item stringID="User_EnvHost" value="MicroCoreLabs"/>
+      <table stringID="User_EnvCpu">
+        <column stringID="arch"/>
+        <column stringID="speed"/>
+        <row stringID="row" value="0">
+          <item stringID="arch" value="Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz"/>
+          <item stringID="speed" value="2492 MHz"/>
+        </row>
+      </table>
+    </section>
+    <task label="Device Utilization Summary" stringID="PAR_DEVICE_UTLIZATION">
+      <section stringID="PAR_SLICE_REPORTING">
+        <item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="PAR_SLICE_REGISTERS" value="853">
+          <item dataType="int" stringID="PAR_NUM_SLICE_FF" value="853"/>
+          <item dataType="int" stringID="PAR_NUM_SLICE_LATCH" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_SLICE_LATCHTHRU" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_SLICE_LATCHLOGIC" value="0"/>
+        </item>
+        <item AVAILABLE="5720" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="959">
+          <item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="54"/>
+          <item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="681"/>
+          <item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="152"/>
+          <item dataType="int" stringID="PAR_NUM_ROM_O5ONLY" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_ROM_O6ONLY" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_ROM_O5ANDO6" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_DPRAM_O5ONLY" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_DPRAM_O6ONLY" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_DPRAM_O5ANDO6" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_SPRAM_O5ONLY" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_SPRAM_O6ONLY" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_SPRAM_O5ANDO6" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_SRL_O5ONLY" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_SRL_O6ONLY" value="2"/>
+          <item dataType="int" stringID="PAR_NUM_SRL_O5ANDO6" value="56"/>
+          <item dataType="int" stringID="PAR_NUM_LUT_RT_EXO6" value="6"/>
+          <item dataType="int" stringID="PAR_NUM_LUT_RT_EXO5" value="8"/>
+          <item dataType="int" stringID="PAR_NUM_LUT_RT_O5ANDO6" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_FLOP" value="8"/>
+          <item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="6"/>
+          <item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
+        </item>
+        <item AVAILABLE="1430" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="381">
+          <item AVAILABLE="355" dataType="int" stringID="PAR_NUM_SLICEL" value="83"/>
+          <item AVAILABLE="360" dataType="int" stringID="PAR_NUM_SLICEM" value="15"/>
+          <item AVAILABLE="715" dataType="int" stringID="PAR_NUM_SLICEX" value="283"/>
+        </item>
+        <item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="1197">
+          <item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="437"/>
+          <item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="238"/>
+          <item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="522"/>
+        </item>
+      </section>
+      <section stringID="PAR_IOB_REPORTING">
+        <item AVAILABLE="102" dataType="int" stringID="PAR_AGG_BONDED_IO" value="75"/>
+        <item AVAILABLE="98" dataType="int" stringID="PAR_AGG_UNBONDED_IO" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="PAR_NUM_IOB_FF" value="39"/>
+        <item AVAILABLE="0" dataType="int" stringID="PAR_NUM_IOB_LATCH" value="0"/>
+        <item AVAILABLE="49" dataType="int" stringID="PAR_NUM_IOBM" value="0"/>
+        <item AVAILABLE="51" dataType="int" stringID="PAR_NUM_BONDED_IOBM" value="0"/>
+        <item AVAILABLE="49" dataType="int" stringID="PAR_NUM_IOBS" value="0"/>
+        <item AVAILABLE="51" dataType="int" stringID="PAR_NUM_BONDED_IOBS" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="PAR_NUM_IPAD" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="PAR_NUM_BONDED_IPAD" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="PAR_NUM_BONDED_OPAD" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="PAR_NUM_OPAD" value="0"/>
+      </section>
+      <section stringID="PAR_HARD_IP_REPORTING"/>
+      <section stringID="PAR_RAM_FIFO_DATA">
+        <item AVAILABLE="32" dataType="int" stringID="PAR_NUM_RAMB16BWER" value="7"/>
+        <item AVAILABLE="64" dataType="int" stringID="PAR_NUM_RAMB8BWER" value="1"/>
+      </section>
+      <section stringID="PAR_IP_DATA">
+        <item AVAILABLE="4" dataType="int" stringID="PAR_NUM_BSCAN" value="0"/>
+        <item AVAILABLE="128" dataType="int" stringID="PAR_NUM_BUFH" value="0"/>
+        <item AVAILABLE="8" dataType="int" stringID="PAR_NUM_BUFPLL" value="0"/>
+        <item AVAILABLE="4" dataType="int" stringID="PAR_NUM_BUFPLL_MCB" value="0"/>
+        <item AVAILABLE="16" dataType="int" stringID="PAR_NUM_DSP48A1" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="PAR_NUM_GTPA1_DUAL" value="0"/>
+        <item AVAILABLE="1" dataType="int" stringID="PAR_NUM_ICAP" value="0"/>
+        <item AVAILABLE="2" dataType="int" stringID="PAR_NUM_MCB" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="PAR_NUM_PCIE_A1" value="0"/>
+        <item AVAILABLE="2" dataType="int" stringID="PAR_NUM_PCILOGICSE" value="0"/>
+        <item AVAILABLE="2" dataType="int" stringID="PAR_NUM_PLL_ADV" value="0"/>
+        <item AVAILABLE="1" dataType="int" stringID="PAR_NUM_PMV" value="0"/>
+        <item AVAILABLE="1" dataType="int" stringID="PAR_NUM_STARTUP" value="0"/>
+        <item AVAILABLE="1" dataType="int" stringID="PAR_NUM_SUSPEND_SYNC" value="0"/>
+      </section>
+      <section stringID="PAR_BUFG_DATA">
+        <item dataType="int" stringID="PAR_NUM_BUFG" value="1"/>
+        <item dataType="int" stringID="PAR_NUM_BUFGMUX" value="0"/>
+        <item dataType="int" stringID="PAR_AVAILABLE" value="16"/>
+      </section>
+    </task>
+  </application>
+
+</document>
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr_summary.html b/MCL86jr/FPGA/MCL86jr/MCL86jr_summary.html
new file mode 100644
index 0000000..19b9fee
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr_summary.html
@@ -0,0 +1,502 @@
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>MCL86jr Project Status (11/11/2020 - 19:12:10)</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>MCL86jr.xise</TD>
+<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
+<TD> No Errors </TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>MCL86jr</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>Programming File Generated</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc6slx9-3tqg144</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>
+No Errors</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD ALIGN=LEFT><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/*.xmsgs?&DataKey=Warning'>60 Warnings (0 new)</A></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+<A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.unroutes'>All Signals Completely Routed</A></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD>
+<A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
+<TD>
+<A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr_envsettings.html'>
+System Settings</A>
+</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD>0 &nbsp;<A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
+</TR>
+</TABLE>
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
+<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
+<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
+<TD ALIGN=RIGHT>853</TD>
+<TD ALIGN=RIGHT>11,440</TD>
+<TD ALIGN=RIGHT>7%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
+<TD ALIGN=RIGHT>853</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latch-thrus</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as AND/OR logics</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
+<TD ALIGN=RIGHT>959</TD>
+<TD ALIGN=RIGHT>5,720</TD>
+<TD ALIGN=RIGHT>16%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
+<TD ALIGN=RIGHT>887</TD>
+<TD ALIGN=RIGHT>5,720</TD>
+<TD ALIGN=RIGHT>15%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
+<TD ALIGN=RIGHT>681</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
+<TD ALIGN=RIGHT>54</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
+<TD ALIGN=RIGHT>152</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as ROM</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Memory</TD>
+<TD ALIGN=RIGHT>58</TD>
+<TD ALIGN=RIGHT>1,440</TD>
+<TD ALIGN=RIGHT>4%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Dual Port RAM</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Single Port RAM</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Shift Register</TD>
+<TD ALIGN=RIGHT>58</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
+<TD ALIGN=RIGHT>56</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD>
+<TD ALIGN=RIGHT>14</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
+<TD ALIGN=RIGHT>8</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice carry load</TD>
+<TD ALIGN=RIGHT>6</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with other load</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
+<TD ALIGN=RIGHT>381</TD>
+<TD ALIGN=RIGHT>1,430</TD>
+<TD ALIGN=RIGHT>26%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MUXCYs used</TD>
+<TD ALIGN=RIGHT>196</TD>
+<TD ALIGN=RIGHT>2,860</TD>
+<TD ALIGN=RIGHT>6%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
+<TD ALIGN=RIGHT>1,197</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
+<TD ALIGN=RIGHT>437</TD>
+<TD ALIGN=RIGHT>1,197</TD>
+<TD ALIGN=RIGHT>36%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
+<TD ALIGN=RIGHT>238</TD>
+<TD ALIGN=RIGHT>1,197</TD>
+<TD ALIGN=RIGHT>19%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
+<TD ALIGN=RIGHT>522</TD>
+<TD ALIGN=RIGHT>1,197</TD>
+<TD ALIGN=RIGHT>43%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
+<TD ALIGN=RIGHT>40</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
+<TD ALIGN=RIGHT>41</TD>
+<TD ALIGN=RIGHT>11,440</TD>
+<TD ALIGN=RIGHT>1%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
+<TD ALIGN=RIGHT>75</TD>
+<TD ALIGN=RIGHT>102</TD>
+<TD ALIGN=RIGHT>73%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of LOCed IOBs</TD>
+<TD ALIGN=RIGHT>75</TD>
+<TD ALIGN=RIGHT>75</TD>
+<TD ALIGN=RIGHT>100%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;IOB Flip Flops</TD>
+<TD ALIGN=RIGHT>39</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
+<TD ALIGN=RIGHT>7</TD>
+<TD ALIGN=RIGHT>32</TD>
+<TD ALIGN=RIGHT>21%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>64</TD>
+<TD ALIGN=RIGHT>1%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>32</TD>
+<TD ALIGN=RIGHT>3%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFIO2s</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFIO2_2CLKs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>32</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>16</TD>
+<TD ALIGN=RIGHT>6%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGMUX</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>4</TD>
+<TD ALIGN=RIGHT>25%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as DCMs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as DCM_CLKGENs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
+<TD ALIGN=RIGHT>12</TD>
+<TD ALIGN=RIGHT>200</TD>
+<TD ALIGN=RIGHT>6%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as ILOGIC2s</TD>
+<TD ALIGN=RIGHT>12</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as ISERDES2s</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>200</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
+<TD ALIGN=RIGHT>27</TD>
+<TD ALIGN=RIGHT>200</TD>
+<TD ALIGN=RIGHT>13%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as OLOGIC2s</TD>
+<TD ALIGN=RIGHT>27</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as OSERDES2s</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>4</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>128</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>8</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>4</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>16</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
+<TD ALIGN=RIGHT>4.04</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+</TABLE>
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
+<TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0)</TD>
+<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
+<TD COLSPAN='2'><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
+<A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.unroutes'>All Signals Completely Routed</A></TD>
+<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
+<TD COLSPAN='2'><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
+<TD>
+<A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
+<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TABLE>
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Nov 11 19:10:14 2020</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/xst.xmsgs?&DataKey=Warning'>55 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/xst.xmsgs?&DataKey=Info'>4 Infos (2 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Nov 11 19:10:21 2020</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/ngdbuild.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Nov 11 19:10:57 2020</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/map.xmsgs?&DataKey=Warning'>2 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (0 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Nov 11 19:11:34 2020</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/par.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Nov 11 19:11:41 2020</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/trce.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed Nov 11 19:11:55 2020</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\_xmsgs/bitgen.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\MCL86jr_map.psr'>Physical Synthesis Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Nov 11 19:10:57 2020</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Nov 11 19:11:55 2020</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/MCL/MCL86/MCL86jr/MCL86jr\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Nov 11 19:12:10 2020</TD></TR>
+</TABLE>
+
+
+<br><center><b>Date Generated:</b> 11/11/2020 - 19:12:11</center>
+</BODY></HTML>
\ No newline at end of file
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr_summary.xml b/MCL86jr/FPGA/MCL86jr/MCL86jr_summary.xml
new file mode 100644
index 0000000..836fc8c
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr_summary.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<DesignSummary rev="208">
+<CmdHistory>
+</CmdHistory>
+</DesignSummary>
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr_usage.xml b/MCL86jr/FPGA/MCL86jr/MCL86jr_usage.xml
new file mode 100644
index 0000000..d130bdb
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr_usage.xml
@@ -0,0 +1,2138 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<DeviceUsageSummary rev="208">
+<DesignStatistics TimeStamp="Wed Nov 11 19:11:54 2020"><group name="NetStatistics">
+<item name="NumNets_Active" rev="208">
+<attrib name="value" value="1664"/></item>
+<item name="NumNets_Gnd" rev="208">
+<attrib name="value" value="1"/></item>
+<item name="NumNets_Vcc" rev="208">
+<attrib name="value" value="1"/></item>
+<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="208">
+<attrib name="value" value="107"/></item>
+<item name="NumNodesOfType_Active_BOUNCEIN" rev="208">
+<attrib name="value" value="218"/></item>
+<item name="NumNodesOfType_Active_BUFGOUT" rev="208">
+<attrib name="value" value="1"/></item>
+<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="208">
+<attrib name="value" value="8"/></item>
+<item name="NumNodesOfType_Active_BUFIOINP" rev="208">
+<attrib name="value" value="1"/></item>
+<item name="NumNodesOfType_Active_CLKPIN" rev="208">
+<attrib name="value" value="301"/></item>
+<item name="NumNodesOfType_Active_CLKPINFEED" rev="208">
+<attrib name="value" value="12"/></item>
+<item name="NumNodesOfType_Active_CNTRLPIN" rev="208">
+<attrib name="value" value="454"/></item>
+<item name="NumNodesOfType_Active_DOUBLE" rev="208">
+<attrib name="value" value="3302"/></item>
+<item name="NumNodesOfType_Active_GENERIC" rev="208">
+<attrib name="value" value="126"/></item>
+<item name="NumNodesOfType_Active_GLOBAL" rev="208">
+<attrib name="value" value="84"/></item>
+<item name="NumNodesOfType_Active_INPUT" rev="208">
+<attrib name="value" value="202"/></item>
+<item name="NumNodesOfType_Active_IOBIN2OUT" rev="208">
+<attrib name="value" value="115"/></item>
+<item name="NumNodesOfType_Active_IOBOUTPUT" rev="208">
+<attrib name="value" value="103"/></item>
+<item name="NumNodesOfType_Active_LUTINPUT" rev="208">
+<attrib name="value" value="4151"/></item>
+<item name="NumNodesOfType_Active_OUTBOUND" rev="208">
+<attrib name="value" value="1588"/></item>
+<item name="NumNodesOfType_Active_OUTPUT" rev="208">
+<attrib name="value" value="1565"/></item>
+<item name="NumNodesOfType_Active_PADINPUT" rev="208">
+<attrib name="value" value="82"/></item>
+<item name="NumNodesOfType_Active_PADOUTPUT" rev="208">
+<attrib name="value" value="22"/></item>
+<item name="NumNodesOfType_Active_PINBOUNCE" rev="208">
+<attrib name="value" value="1388"/></item>
+<item name="NumNodesOfType_Active_PINFEED" rev="208">
+<attrib name="value" value="4915"/></item>
+<item name="NumNodesOfType_Active_PINFEED2" rev="208">
+<attrib name="value" value="31"/></item>
+<item name="NumNodesOfType_Active_QUAD" rev="208">
+<attrib name="value" value="2838"/></item>
+<item name="NumNodesOfType_Active_REGINPUT" rev="208">
+<attrib name="value" value="595"/></item>
+<item name="NumNodesOfType_Active_SINGLE" rev="208">
+<attrib name="value" value="3576"/></item>
+<item name="NumNodesOfType_Gnd_BOUNCEIN" rev="208">
+<attrib name="value" value="127"/></item>
+<item name="NumNodesOfType_Gnd_CLKPIN" rev="208">
+<attrib name="value" value="1"/></item>
+<item name="NumNodesOfType_Gnd_CNTRLPIN" rev="208">
+<attrib name="value" value="3"/></item>
+<item name="NumNodesOfType_Gnd_DOUBLE" rev="208">
+<attrib name="value" value="23"/></item>
+<item name="NumNodesOfType_Gnd_GENERIC" rev="208">
+<attrib name="value" value="3"/></item>
+<item name="NumNodesOfType_Gnd_HGNDOUT" rev="208">
+<attrib name="value" value="48"/></item>
+<item name="NumNodesOfType_Gnd_INPUT" rev="208">
+<attrib name="value" value="779"/></item>
+<item name="NumNodesOfType_Gnd_IOBIN2OUT" rev="208">
+<attrib name="value" value="3"/></item>
+<item name="NumNodesOfType_Gnd_IOBOUTPUT" rev="208">
+<attrib name="value" value="3"/></item>
+<item name="NumNodesOfType_Gnd_LUTINPUT" rev="208">
+<attrib name="value" value="232"/></item>
+<item name="NumNodesOfType_Gnd_OUTBOUND" rev="208">
+<attrib name="value" value="50"/></item>
+<item name="NumNodesOfType_Gnd_OUTPUT" rev="208">
+<attrib name="value" value="57"/></item>
+<item name="NumNodesOfType_Gnd_PADINPUT" rev="208">
+<attrib name="value" value="3"/></item>
+<item name="NumNodesOfType_Gnd_PINBOUNCE" rev="208">
+<attrib name="value" value="202"/></item>
+<item name="NumNodesOfType_Gnd_PINFEED" rev="208">
+<attrib name="value" value="937"/></item>
+<item name="NumNodesOfType_Gnd_REGINPUT" rev="208">
+<attrib name="value" value="3"/></item>
+<item name="NumNodesOfType_Gnd_SINGLE" rev="208">
+<attrib name="value" value="50"/></item>
+<item name="NumNodesOfType_Vcc_CNTRLPIN" rev="208">
+<attrib name="value" value="1"/></item>
+<item name="NumNodesOfType_Vcc_HVCCOUT" rev="208">
+<attrib name="value" value="106"/></item>
+<item name="NumNodesOfType_Vcc_INPUT" rev="208">
+<attrib name="value" value="4"/></item>
+<item name="NumNodesOfType_Vcc_KVCCOUT" rev="208">
+<attrib name="value" value="15"/></item>
+<item name="NumNodesOfType_Vcc_LUTINPUT" rev="208">
+<attrib name="value" value="334"/></item>
+<item name="NumNodesOfType_Vcc_PINBOUNCE" rev="208">
+<attrib name="value" value="1"/></item>
+<item name="NumNodesOfType_Vcc_PINFEED" rev="208">
+<attrib name="value" value="338"/></item>
+</group>
+<group name="SiteStatistics">
+<item name="BUFG-BUFGMUX" rev="208">
+<attrib name="value" value="1"/></item>
+<item name="IOB-IOBM" rev="208">
+<attrib name="value" value="36"/></item>
+<item name="IOB-IOBS" rev="208">
+<attrib name="value" value="39"/></item>
+<item name="SLICEL-SLICEM" rev="208">
+<attrib name="value" value="41"/></item>
+<item name="SLICEX-SLICEL" rev="208">
+<attrib name="value" value="53"/></item>
+<item name="SLICEX-SLICEM" rev="208">
+<attrib name="value" value="57"/></item>
+</group>
+<group name="MiscellaneousStatistics">
+<item name="AGG_BONDED_IO" rev="207">
+<attrib name="value" value="75"/></item>
+<item name="AGG_IO" rev="207">
+<attrib name="value" value="75"/></item>
+<item name="AGG_LOCED_IO" rev="207">
+<attrib name="value" value="75"/></item>
+<item name="AGG_SLICE" rev="207">
+<attrib name="value" value="381"/></item>
+<item name="NUM_BONDED_IOB" rev="207">
+<attrib name="value" value="75"/></item>
+<item name="NUM_BSFULL" rev="207">
+<attrib name="value" value="522"/></item>
+<item name="NUM_BSLUTONLY" rev="207">
+<attrib name="value" value="437"/></item>
+<item name="NUM_BSREGONLY" rev="207">
+<attrib name="value" value="238"/></item>
+<item name="NUM_BSUSED" rev="207">
+<attrib name="value" value="1197"/></item>
+<item name="NUM_BUFG" rev="207">
+<attrib name="value" value="1"/></item>
+<item name="NUM_BUFIO2" rev="207">
+<attrib name="value" value="1"/></item>
+<item name="NUM_DCM" rev="207">
+<attrib name="value" value="1"/></item>
+<item name="NUM_ILOGIC2" rev="207">
+<attrib name="value" value="12"/></item>
+<item name="NUM_IOB_FF" rev="207">
+<attrib name="value" value="39"/></item>
+<item name="NUM_LOCED_IOB" rev="207">
+<attrib name="value" value="75"/></item>
+<item name="NUM_LOGIC_O5ANDO6" rev="207">
+<attrib name="value" value="152"/></item>
+<item name="NUM_LOGIC_O5ONLY" rev="207">
+<attrib name="value" value="54"/></item>
+<item name="NUM_LOGIC_O6ONLY" rev="207">
+<attrib name="value" value="681"/></item>
+<item name="NUM_LUT_RT_DRIVES_CARRY4" rev="207">
+<attrib name="value" value="6"/></item>
+<item name="NUM_LUT_RT_DRIVES_FLOP" rev="207">
+<attrib name="value" value="8"/></item>
+<item name="NUM_LUT_RT_EXO5" rev="207">
+<attrib name="value" value="8"/></item>
+<item name="NUM_LUT_RT_EXO6" rev="207">
+<attrib name="value" value="6"/></item>
+<item name="NUM_LUT_RT_O5" rev="207">
+<attrib name="value" value="12"/></item>
+<item name="NUM_LUT_RT_O6" rev="207">
+<attrib name="value" value="54"/></item>
+<item name="NUM_OLOGIC2" rev="207">
+<attrib name="value" value="27"/></item>
+<item name="NUM_RAMB16BWER" rev="207">
+<attrib name="value" value="7"/></item>
+<item name="NUM_RAMB8BWER" rev="207">
+<attrib name="value" value="1"/></item>
+<item name="NUM_SLICEL" rev="207">
+<attrib name="value" value="83"/></item>
+<item name="NUM_SLICEM" rev="207">
+<attrib name="value" value="15"/></item>
+<item name="NUM_SLICEX" rev="207">
+<attrib name="value" value="283"/></item>
+<item name="NUM_SLICE_CARRY4" rev="207">
+<attrib name="value" value="49"/></item>
+<item name="NUM_SLICE_CONTROLSET" rev="207">
+<attrib name="value" value="40"/></item>
+<item name="NUM_SLICE_CYINIT" rev="207">
+<attrib name="value" value="1240"/></item>
+<item name="NUM_SLICE_F7MUX" rev="207">
+<attrib name="value" value="59"/></item>
+<item name="NUM_SLICE_F8MUX" rev="207">
+<attrib name="value" value="25"/></item>
+<item name="NUM_SLICE_FF" rev="207">
+<attrib name="value" value="853"/></item>
+<item name="NUM_SLICE_UNUSEDCTRL" rev="207">
+<attrib name="value" value="107"/></item>
+<item name="NUM_SRL_O5ANDO6" rev="207">
+<attrib name="value" value="56"/></item>
+<item name="NUM_SRL_O6ONLY" rev="207">
+<attrib name="value" value="2"/></item>
+<item name="NUM_UNUSABLE_FF_BELS" rev="207">
+<attrib name="value" value="41"/></item>
+<item name="Xilinx Core blk_mem_gen_v7_3, Xilinx CORE Generator 14.7" rev="207">
+<attrib name="value" value="1"/></item>
+</group>
+</DesignStatistics>
+<DeviceUsage TimeStamp="Wed Nov 11 19:11:54 2020"><group name="SiteSummary">
+<item name="BUFG" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
+<item name="BUFG_BUFG" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
+<item name="BUFIO2" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
+<item name="BUFIO2_BUFIO2" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
+<item name="CARRY4" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="49"/></item>
+<item name="DCM" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
+<item name="DCM_DCM" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
+<item name="FF_SR" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="96"/></item>
+<item name="HARD0" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="19"/></item>
+<item name="ILOGIC2" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="12"/></item>
+<item name="ILOGIC2_IFF" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="12"/></item>
+<item name="IOB" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="75"/></item>
+<item name="IOB_IMUX" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="22"/></item>
+<item name="IOB_INBUF" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="22"/></item>
+<item name="IOB_OUTBUF" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="69"/></item>
+<item name="LUT5" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="226"/></item>
+<item name="LUT6" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="893"/></item>
+<item name="LUT_OR_MEM5" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="56"/></item>
+<item name="LUT_OR_MEM6" rev="208">
+<attrib name="total" value="1000000"/><attrib name="used" value="58"/></item>
+<item name="OLOGIC2" rev="208">
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+</ReportPinData>
+<CmdHistory>
+</CmdHistory>
+</DeviceUsageSummary>
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr_xpa.log b/MCL86jr/FPGA/MCL86jr/MCL86jr_xpa.log
new file mode 100644
index 0000000..e3dfbfb
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr_xpa.log
@@ -0,0 +1,65 @@
+Creating log file C:\MCL\MCL86\MCL86jr\MCL86jr\MCL86jr_xpa.log.
+Loading device for application Rf_Device from file '6slx9.nph' in environment
+C:\Xilinx\14.7\ISE_DS\ISE\.
+   "MCL86jr" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -3
+
+INFO:Power:1693 - 
+   --------------------------------------------------------------
+                         The power estimate will be calculated using PRODUCTION
+   data.
+   --------------------------------------------------------------
+
+Design load 20% complete
Design load 25% complete
Design load 30% complete
Design load 60% complete
Design load 95% complete
Design load 100% complete
Running Vector-less Activity Propagation
+........
+Finished Running Vector-less Activity Propagation
+Finished Running Vector-less Activity Propagation 0 secs 
+
+Design 'MCL86jr.ncd' and constraints 'MCL86jr.pcf' opened successfully
+
+
+Updating power analysis...
+WARNING:Power:91 - Can't change frequency of net BIU_CORE/RESET_INT_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0848_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0852_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0856_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0860_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0864_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0866_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0869_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0873_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0877_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0881_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0885_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0888_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0896_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0904_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net BIU_CORE/_n0909_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net BIU_CORE/biu_state[7]_GND_10_o_equal_153_o to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net BIU_CORE/biu_state[7]_GND_10_o_equal_155_o to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1079_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1083_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1087_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1091_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1095_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1099_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1103_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1107_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1111_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1115_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1119_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1123_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1127_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1131_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1135_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1156<0>2 to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/_n1156_inv to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/eu_stall_pipeline_eu_opcode_type[2]_AND_112_o to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net EU_CORE/eu_stall_pipeline_eu_opcode_type[2]_AND_114_o to 1.00Mhz.
+WARNING:Power:91 - Can't change frequency of net X245_DIR_OBUF to 1.00Mhz.
+WARNING:Power:90 - Can't change activity rate of net t_reset_d4 to 1.0% of CORE_CLK_BUFGP.
+WARNING:Power:91 - Can't change frequency of net t_reset_d4/t_reset_d4_rstpot to 1.00Mhz.
+Running Vector-less Activity Propagation
+........
+Finished Running Vector-less Activity Propagation
+Finished Running Vector-less Activity Propagation 0 secs 
+Update Power Analysis is complete.
diff --git a/MCL86jr/FPGA/MCL86jr/MCL86jr_xst.xrpt b/MCL86jr/FPGA/MCL86jr/MCL86jr_xst.xrpt
new file mode 100644
index 0000000..7e4e1a5
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/MCL86jr_xst.xrpt
@@ -0,0 +1,260 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="nt64" product="ISE" version="14.7">
+
+  <!--The data in this file is primarily intended for consumption by Xilinx tools.
+    The structure and the elements are likely to change over the next few releases.
+    This means code written to parse this file will need to be revisited each subsequent release.-->
+
+  <application stringID="Xst" timeStamp="Wed Nov 11 19:09:58 2020">
+    <section stringID="User_Env">
+      <table stringID="User_EnvVar">
+        <column stringID="variable"/>
+        <column stringID="value"/>
+        <row stringID="row" value="0">
+          <item stringID="variable" value="Path"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ProgramData\Oracle\Java\javapath;C:\Program Files (x86)\SemanticDesigns\DMS\Executables;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\Intel\WiFi\bin\;C:\Program Files\Common Files\Intel\WirelessCommon\;C:\altera_lite\15.1\modelsim_ase\win32aloem;C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem"/>
+        </row>
+        <row stringID="row" value="1">
+          <item stringID="variable" value="PATHEXT"/>
+          <item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
+        </row>
+        <row stringID="row" value="2">
+          <item stringID="variable" value="XILINX"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\"/>
+        </row>
+        <row stringID="row" value="3">
+          <item stringID="variable" value="XILINX_DSP"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE"/>
+        </row>
+        <row stringID="row" value="4">
+          <item stringID="variable" value="XILINX_EDK"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\EDK"/>
+        </row>
+        <row stringID="row" value="5">
+          <item stringID="variable" value="XILINX_PLANAHEAD"/>
+          <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\PlanAhead"/>
+        </row>
+      </table>
+      <item stringID="User_EnvOs" value="OS Information">
+        <item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
+        <item stringID="User_EnvOsrelease" value="Service Pack 1  (build 7601)"/>
+      </item>
+      <item stringID="User_EnvHost" value="MicroCoreLabs"/>
+      <table stringID="User_EnvCpu">
+        <column stringID="arch"/>
+        <column stringID="speed"/>
+        <row stringID="row" value="0">
+          <item stringID="arch" value="Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz"/>
+          <item stringID="speed" value="2492 MHz"/>
+        </row>
+      </table>
+    </section>
+    <section stringID="XST_OPTION_SUMMARY">
+      <item DEFAULT="" label="-ifn" stringID="XST_IFN" value="MCL86jr.prj"/>
+      <item DEFAULT="" label="-ofn" stringID="XST_OFN" value="MCL86jr"/>
+      <item DEFAULT="NGC" label="-ofmt" stringID="XST_OFMT" value="NGC"/>
+      <item DEFAULT="" label="-p" stringID="XST_P" value="xc6slx9-3-tqg144"/>
+      <item DEFAULT="" label="-top" stringID="XST_TOP" value="MCL86jr"/>
+      <item DEFAULT="Speed" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
+      <item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
+      <item DEFAULT="No" label="-power" stringID="XST_POWER" value="NO"/>
+      <item DEFAULT="No" label="-iuc" stringID="XST_IUC" value="NO"/>
+      <item DEFAULT="No" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="No"/>
+      <item DEFAULT="As_Optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
+      <item DEFAULT="No" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/>
+      <item DEFAULT="AllClockNets" label="-glob_opt" stringID="XST_GLOBOPT" value="AllClockNets"/>
+      <item DEFAULT="Yes" label="-read_cores" stringID="XST_READCORES" value="YES"/>
+      <item DEFAULT="" label="-sd" stringID="XST_SD" value="{&quot;ipcore_dir&quot;  }"/>
+      <item DEFAULT="No" label="-write_timing_constraints" stringID="XST_WRITETIMINGCONSTRAINTS" value="NO"/>
+      <item DEFAULT="No" label="-cross_clock_analysis" stringID="XST_CROSSCLOCKANALYSIS" value="NO"/>
+      <item DEFAULT="/" stringID="XST_HIERARCHYSEPARATOR" value="/"/>
+      <item DEFAULT="&lt;>" label="-bus_delimiter" stringID="XST_BUSDELIMITER" value="&lt;>"/>
+      <item DEFAULT="Maintain" stringID="XST_CASE" value="Maintain"/>
+      <item DEFAULT="100" label="-slice_utilization_ratio" stringID="XST_SLICEUTILIZATIONRATIO" value="100"/>
+      <item DEFAULT="100" label="-bram_utilization_ratio" stringID="XST_BRAMUTILIZATIONRATIO" value="100"/>
+      <item DEFAULT="100" label="-dsp_utilization_ratio" stringID="XST_DSPUTILIZATIONRATIO" value="100"/>
+      <item DEFAULT="Auto" stringID="XST_LC" value="Auto"/>
+      <item DEFAULT="Auto" label="-reduce_control_sets" stringID="XST_REDUCECONTROLSETS" value="Auto"/>
+      <item DEFAULT="Yes" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
+      <item DEFAULT="Auto" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Auto"/>
+      <item DEFAULT="No" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
+      <item DEFAULT="LUT" label="-fsm_style" stringID="XST_FSMSTYLE" value="LUT"/>
+      <item DEFAULT="Yes" label="-ram_extract" stringID="XST_RAMEXTRACT" value="Yes"/>
+      <item DEFAULT="Auto" label="-ram_style" stringID="XST_RAMSTYLE" value="Auto"/>
+      <item DEFAULT="Yes" label="-rom_extract" stringID="XST_ROMEXTRACT" value="Yes"/>
+      <item DEFAULT="Yes" label="-shreg_extract" stringID="XST_SHREGEXTRACT" value="YES"/>
+      <item DEFAULT="Auto" label="-rom_style" stringID="XST_ROMSTYLE" value="Auto"/>
+      <item DEFAULT="No" label="-auto_bram_packing" stringID="XST_AUTOBRAMPACKING" value="NO"/>
+      <item DEFAULT="Yes" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
+      <item DEFAULT="No" label="-async_to_sync" stringID="XST_ASYNCTOSYNC" value="NO"/>
+      <item DEFAULT="2" stringID="XST_SHREGMINSIZE" value="2"/>
+      <item DEFAULT="Auto" label="-use_dsp48" stringID="XST_USEDSP48" value="Auto"/>
+      <item DEFAULT="Yes" label="-iobuf" stringID="XST_IOBUF" value="YES"/>
+      <item DEFAULT="100000" label="-max_fanout" stringID="XST_MAXFANOUT" value="100000"/>
+      <item DEFAULT="16" label="-bufg" stringID="XST_BUFG" value="16"/>
+      <item DEFAULT="Yes" label="-register_duplication" stringID="XST_REGISTERDUPLICATION" value="YES"/>
+      <item DEFAULT="No" label="-register_balancing" stringID="XST_REGISTERBALANCING" value="No"/>
+      <item DEFAULT="No" label="-optimize_primitives" stringID="XST_OPTIMIZEPRIMITIVES" value="NO"/>
+      <item DEFAULT="Auto" label="-use_clock_enable" stringID="XST_USECLOCKENABLE" value="Auto"/>
+      <item DEFAULT="Auto" label="-use_sync_set" stringID="XST_USESYNCSET" value="Auto"/>
+      <item DEFAULT="Auto" label="-use_sync_reset" stringID="XST_USESYNCRESET" value="Auto"/>
+      <item DEFAULT="Auto" label="-iob" stringID="XST_IOB" value="Auto"/>
+      <item DEFAULT="Yes" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
+      <item DEFAULT="0" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
+    </section>
+    <section stringID="XST_UNISIM_SUMMARY">
+      <item dataType="int" stringID="XST_NUM_BUFG" value="1"/>
+      <item dataType="int" stringID="XST_NUM_IBUFG" value="1"/>
+    </section>
+    <section stringID="XST_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="12">
+        <item dataType="int" stringID="XST_16BIT_ADDER" value="3"/>
+        <item dataType="int" stringID="XST_8BIT_ADDER" value="1"/>
+      </item>
+      <item dataType="int" stringID="XST_REGISTERS" value="129">
+        <item dataType="int" stringID="XST_1BIT_REGISTER" value="68"/>
+        <item dataType="int" stringID="XST_16BIT_REGISTER" value="41"/>
+        <item dataType="int" stringID="XST_19BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_8BIT_REGISTER" value="10"/>
+      </item>
+      <item dataType="int" stringID="XST_COMPARATORS" value="4">
+        <item dataType="int" stringID="XST_1BIT_COMPARATOR_EQUAL" value="1"/>
+        <item dataType="int" stringID="XST_2BIT_COMPARATOR_EQUAL" value="1"/>
+        <item dataType="int" stringID="XST_4BIT_COMPARATOR_GREATER" value="2"/>
+      </item>
+      <item dataType="int" stringID="XST_MULTIPLEXERS" value="156">
+        <item dataType="int" stringID="XST_1BIT_2TO1_MULTIPLEXER" value="118"/>
+        <item dataType="int" stringID="XST_16BIT_2TO1_MULTIPLEXER" value="3"/>
+        <item dataType="int" stringID="XST_16BIT_4TO1_MULTIPLEXER" value="1"/>
+        <item dataType="int" stringID="XST_2BIT_2TO1_MULTIPLEXER" value="1"/>
+        <item dataType="int" stringID="XST_3BIT_2TO1_MULTIPLEXER" value="1"/>
+        <item dataType="int" stringID="XST_8BIT_2TO1_MULTIPLEXER" value="14"/>
+        <item dataType="int" stringID="XST_8BIT_4TO1_MULTIPLEXER" value="1"/>
+      </item>
+      <item dataType="int" stringID="XST_TRISTATES" value="16">
+        <item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="16"/>
+      </item>
+      <item dataType="int" stringID="XST_XORS" value="20">
+        <item dataType="int" stringID="XST_1BIT_XOR2" value="2"/>
+        <item dataType="int" stringID="XST_1BIT_XOR3" value="16"/>
+      </item>
+    </section>
+    <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="7">
+        <item dataType="int" stringID="XST_16BIT_ADDER" value="1"/>
+        <item dataType="int" stringID="XST_8BIT_ADDER" value="1"/>
+      </item>
+      <item dataType="int" stringID="XST_COUNTERS" value="5"></item>
+      <item dataType="int" stringID="XST_REGISTERS" value="913">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="913"/>
+      </item>
+      <item dataType="int" stringID="XST_COMPARATORS" value="4">
+        <item dataType="int" stringID="XST_1BIT_COMPARATOR_EQUAL" value="1"/>
+        <item dataType="int" stringID="XST_2BIT_COMPARATOR_EQUAL" value="1"/>
+        <item dataType="int" stringID="XST_4BIT_COMPARATOR_GREATER" value="2"/>
+      </item>
+      <item dataType="int" stringID="XST_MULTIPLEXERS" value="209">
+        <item dataType="int" stringID="XST_1BIT_2TO1_MULTIPLEXER" value="131"/>
+        <item dataType="int" stringID="XST_1BIT_4TO1_MULTIPLEXER" value="16"/>
+        <item dataType="int" stringID="XST_16BIT_2TO1_MULTIPLEXER" value="1"/>
+        <item dataType="int" stringID="XST_2BIT_2TO1_MULTIPLEXER" value="1"/>
+        <item dataType="int" stringID="XST_3BIT_2TO1_MULTIPLEXER" value="1"/>
+        <item dataType="int" stringID="XST_8BIT_2TO1_MULTIPLEXER" value="14"/>
+        <item dataType="int" stringID="XST_8BIT_4TO1_MULTIPLEXER" value="1"/>
+      </item>
+      <item dataType="int" stringID="XST_XORS" value="20">
+        <item dataType="int" stringID="XST_1BIT_XOR2" value="2"/>
+        <item dataType="int" stringID="XST_1BIT_XOR3" value="16"/>
+      </item>
+    </section>
+    <section stringID="XST_FINAL_REGISTER_REPORT">
+      <item dataType="int" stringID="XST_REGISTERS" value="777">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="777"/>
+      </item>
+      <item dataType="int" stringID="XST_SHIFT_REGISTERS" value="114">
+        <item dataType="int" stringID="XST_2BIT_SHIFT_REGISTER" value="114"/>
+      </item>
+    </section>
+    <section stringID="XST_PARTITION_REPORT">
+      <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
+        <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+      </section>
+    </section>
+    <section stringID="XST_DESIGN_SUMMARY">
+      <section stringID="XST_">
+        <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="MCL86jr.ngc"/>
+      </section>
+      <section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
+        <item dataType="int" stringID="XST_BELS" value="1407">
+          <item dataType="int" stringID="XST_GND" value="2"/>
+          <item dataType="int" stringID="XST_INV" value="15"/>
+          <item dataType="int" stringID="XST_LUT1" value="60"/>
+          <item dataType="int" stringID="XST_LUT2" value="87"/>
+          <item dataType="int" stringID="XST_LUT3" value="116"/>
+          <item dataType="int" stringID="XST_LUT4" value="73"/>
+          <item dataType="int" stringID="XST_LUT5" value="223"/>
+          <item dataType="int" stringID="XST_LUT6" value="384"/>
+          <item dataType="int" stringID="XST_MUXCY" value="175"/>
+          <item dataType="int" stringID="XST_MUXF7" value="59"/>
+          <item dataType="int" stringID="XST_MUXF8" value="25"/>
+          <item dataType="int" stringID="XST_VCC" value="2"/>
+          <item dataType="int" stringID="XST_XORCY" value="186"/>
+        </item>
+        <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="892">
+          <item dataType="int" stringID="XST_FD" value="48"/>
+          <item dataType="int" stringID="XST_FDE" value="183"/>
+          <item dataType="int" stringID="XST_FDR" value="125"/>
+          <item dataType="int" stringID="XST_FDRE" value="503"/>
+          <item dataType="int" stringID="XST_FDS" value="13"/>
+          <item dataType="int" stringID="XST_FDSE" value="20"/>
+        </item>
+        <item dataType="int" stringID="XST_RAMS" value="8">
+          <item dataType="int" stringID="XST_RAMB16BWER" value="7"/>
+        </item>
+        <item dataType="int" stringID="XST_SHIFT_REGISTERS" value="114">
+          <item dataType="int" stringID="XST_SRLC16E" value="114"/>
+        </item>
+        <item dataType="int" stringID="XST_CLOCK_BUFFERS" value="1">
+          <item dataType="int" label="-bufg" stringID="XST_BUFG" value="1"/>
+        </item>
+        <item dataType="int" stringID="XST_IO_BUFFERS" value="75">
+          <item dataType="int" stringID="XST_IBUF" value="5"/>
+          <item dataType="int" stringID="XST_IBUFG" value="1"/>
+          <item dataType="int" label="-iobuf" stringID="XST_IOBUF" value="16"/>
+          <item dataType="int" stringID="XST_OBUF" value="53"/>
+        </item>
+        <item dataType="int" stringID="XST_DCMS" value="1">
+          <item dataType="int" stringID="XST_DCMSP" value="1"/>
+        </item>
+      </section>
+    </section>
+    <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
+      <item stringID="XST_SELECTED_DEVICE" value="6slx9tqg144-3"/>
+      <item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="892"/>
+      <item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="1072"/>
+      <item AVAILABLE="5720" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="958"/>
+      <item AVAILABLE="1440" dataType="int" stringID="XST_NUMBER_USED_AS_MEMORY" value="114"/>
+      <item dataType="int" stringID="XST_NUMBER_USED_AS_SRL" value="114"/>
+      <item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="1452"/>
+      <item AVAILABLE="1452" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="560"/>
+      <item AVAILABLE="1452" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="380"/>
+      <item AVAILABLE="1452" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="512"/>
+      <item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="41"/>
+      <item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="75"/>
+      <item AVAILABLE="102" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="75"/>
+      <item AVAILABLE="32" dataType="int" label="Number of Block RAM/FIFO" stringID="XST_NUMBER_OF_BLOCK_RAMFIFO" value="8"/>
+      <item dataType="int" label="Number using Block RAM only" stringID="XST_NUMBER_USING_BLOCK_RAM_ONLY" value="8"/>
+      <item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="1"/>
+    </section>
+    <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
+      <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+    </section>
+    <section stringID="XST_ERRORS_STATISTICS">
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="55"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="4"/>
+    </section>
+  </application>
+
+</document>
diff --git a/MCL86jr/FPGA/MCL86jr/_impact.cmd b/MCL86jr/FPGA/MCL86jr/_impact.cmd
new file mode 100644
index 0000000..95df623
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/_impact.cmd
@@ -0,0 +1,150 @@
+setMode -bs
+setMode -ss
+setMode -sm
+setMode -hw140
+setMode -spi
+setMode -acecf
+setMode -acempm
+setMode -pff
+loadProjectFile -file "C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
+setMode -ss
+setMode -sm
+setMode -hw140
+setMode -spi
+setMode -acecf
+setMode -acempm
+setMode -pff
+setMode -bs
+setMode -pff
+setMode -pff
+setMode -pff
+setMode -pff
+setMode -pff
+setCurrentDesign -version 0
+setMode -pff
+setCurrentDeviceChain -index 0
+setMode -bs
+setMode -bs
+setMode -bs
+setMode -bs
+setCable -port auto
+Identify -inferir 
+identifyMPM 
+assignFile -p 1 -file "C:/MCL/MCL86/MCL86jr/MCL86jr/mcl86jr.bit"
+Program -p 1 
+attachflash -position 1 -spi "W25Q128FV"
+assignfiletoattachedflash -position 1 -file "C:/MCL/MCL86/MCL86jr/Untitled.mcs"
+setMode -bs
+deleteDevice -position 1
+setMode -bs
+setMode -ss
+setMode -sm
+setMode -hw140
+setMode -spi
+setMode -acecf
+setMode -acempm
+setMode -pff
+loadProjectFile -file "C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
+setMode -ss
+setMode -sm
+setMode -hw140
+setMode -spi
+setMode -acecf
+setMode -acempm
+setMode -pff
+setMode -bs
+setMode -pff
+setMode -pff
+setMode -pff
+setMode -pff
+setMode -pff
+setCurrentDesign -version 0
+setMode -pff
+setCurrentDeviceChain -index 0
+setSubmode -pffspi
+setMode -pff
+setMode -bs
+setMode -pff
+setSubmode -pffspi
+setSubmode -pffspi
+setMode -bs
+setMode -bs
+setMode -bs
+setMode -pff
+setSubmode -pffspi
+setSubmode -pffspi
+setMode -pff
+setSubmode -pffspi
+generate
+setCurrentDesign -version 0
+setMode -bs
+setMode -bs
+setMode -bs
+setMode -pff
+setSubmode -pffspi
+setSubmode -pffspi
+setMode -bs
+setMode -bs
+setMode -bs
+setMode -pff
+setSubmode -pffspi
+setSubmode -pffspi
+setMode -bs
+setMode -bs
+setMode -bs
+setCable -port auto
+Identify -inferir 
+identifyMPM 
+attachflash -position 1 -spi "W25Q128FV"
+assignfiletoattachedflash -position 1 -file "C:/MCL/MCL86/MCL86jr/Untitled.mcs"
+setMode -bs
+setMode -bs
+setMode -ss
+setMode -sm
+setMode -hw140
+setMode -spi
+setMode -acecf
+setMode -acempm
+setMode -pff
+setMode -bs
+saveProjectFile -file "C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
+Program -p 1 -dataWidth 1 -spionly -e -v -loadfpga 
+setMode -bs
+setMode -bs
+setMode -ss
+setMode -sm
+setMode -hw140
+setMode -spi
+setMode -acecf
+setMode -acempm
+setMode -pff
+setMode -bs
+saveProjectFile -file "C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
+setMode -bs
+setMode -bs
+setMode -ss
+setMode -sm
+setMode -hw140
+setMode -spi
+setMode -acecf
+setMode -acempm
+setMode -pff
+setMode -bs
+saveProjectFile -file "C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
+setMode -bs
+setMode -pff
+setMode -bs
+deleteDevice -position 1
+setMode -bs
+setMode -ss
+setMode -sm
+setMode -hw140
+setMode -spi
+setMode -acecf
+setMode -acempm
+setMode -pff
+deletePromDevice -position 1
+setCurrentDesign -version 0
+deleteDevice -position 1
+deleteDesign -version 0
+setCurrentDesign -version -1
diff --git a/MCL86jr/FPGA/MCL86jr/_impact.log b/MCL86jr/FPGA/MCL86jr/_impact.log
new file mode 100644
index 0000000..b7aed7c
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/_impact.log
@@ -0,0 +1,330 @@
+iMPACT Version: 14.7
+
+iMPACT log file Started on Sat Nov 07 21:58:06 2020
+
+Welcome to iMPACT
+iMPACT Version: 14.7
+// *** BATCH CMD : setMode -bs
+// *** BATCH CMD : setMode -ss
+// *** BATCH CMD : setMode -sm
+// *** BATCH CMD : setMode -hw140
+// *** BATCH CMD : setMode -spi
+// *** BATCH CMD : setMode -acecf
+// *** BATCH CMD : setMode -acempm
+// *** BATCH CMD : setMode -pff
+// *** BATCH CMD : loadProjectFile -file"C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
+'1': Loading file 'C:\MCL\MCL86\MCL86jr\MCL86jr\mcl86jr.bit' ...
+INFO:iMPACT - Elapsed time =      0 sec.
+done.
+INFO:iMPACT:501 - '1': Added Device xc6slx9 successfully.
+----------------------------------------------------------------------
+'1': Added Device 16M successfully.
+----------------------------------------------------------------------
+Active mode is BS
+// *** BATCH CMD : setMode -ss
+// *** BATCH CMD : setMode -sm
+// *** BATCH CMD : setMode -hw140
+// *** BATCH CMD : setMode -spi
+// *** BATCH CMD : setMode -acecf
+// *** BATCH CMD : setMode -acempm
+// *** BATCH CMD : setMode -pff
+// *** BATCH CMD : setMode -bs
+// *** BATCH CMD : setMode -pff
+// *** BATCH CMD : setCurrentDesign -version 0
+// *** BATCH CMD : setMode -pff
+// *** BATCH CMD : setCurrentDeviceChain -index 0
+// *** BATCH CMD : setMode -bs
+GUI --- Auto connect to cable...
+// *** BATCH CMD : setCable -port auto
+AutoDetecting cable. Please wait.
+*** WARNING ***: When port is set to auto detect mode, cable speed is set todefault 6 MHz regardless of explicit arguments supplied for setting the baudrates
+PROGRESS_START - Starting Operation.
+Connecting to cable (Usb Port - USB21).
+Checking cable driver.
+ Driver file xusb_xp2.sys found.
+ Driver version: src=2301, dest=2301.
+ Driver windrvr6.sys version = 10.2.1.0. WinDriver v10.21 Jungo (c) 1997 - 2010 Build Date: Aug 31 2010 x86_64 64bit SYS14:14:44, version = 1021.
+ Cable PID = 0008.
+ Max current requested during enumeration is 300 mA.
+Type = 0x0005.
+write (count, cmdBuffer, dataBuffer) failed C0000004.
+ Cable Type = 3, Revision = 0.
+ Setting cable speed to 6 MHz.
+Cable connection established.
+Firmware version = 2301.
+File version of C:/Xilinx/14.7/ISE_DS/ISE/data/xusb_xp2.hex = 2401.
+Firmware hex file version = 2401.
+Downloading C:/Xilinx/14.7/ISE_DS/ISE/data/xusb_xp2.hex.
+Downloaded firmware version = 2401.
+PLD file version = 200Dh.
+ PLD version = 200Dh.
+PROGRESS_END - End Operation.
+Elapsed time =      1 sec.
+Type = 0x0005.
+ESN option: 0000149BE10901.
+Attempting to identify devices in the boundary-scan chain configuration...
+INFO:iMPACT - Current time: 11/7/2020 9:58:25 PM
+// *** BATCH CMD : Identify -inferir 
+PROGRESS_START - Starting Operation.
+Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc6slx9, Version : 2
+INFO:iMPACT:1777 - 
+   Reading C:/Xilinx/14.7/ISE_DS/ISE/spartan6/data/xc6slx9.bsd...
+INFO:iMPACT:501 - '1': Added Device xc6slx9 successfully.
+----------------------------------------------------------------------
+done.
+PROGRESS_END - End Operation.
+Elapsed time =      0 sec.
+// *** BATCH CMD : identifyMPM 
+// *** BATCH CMD : assignFile -p 1 -file"C:/MCL/MCL86/MCL86jr/MCL86jr/mcl86jr.bit"
+'1': Loading file 'C:/MCL/MCL86/MCL86jr/MCL86jr/mcl86jr.bit' ...
+done.
+INFO:iMPACT:2257 - Startup Clock has been changed to 'JtagClk' in the bitstream   stored in memory,
+   but the original bitstream file remains unchanged.
+UserID read from the bitstream file = 0xFFFFFFFF.
+Data width read from the bitstream file = 1.
+INFO:iMPACT:501 - '1': Added Device xc6slx9 successfully.
+----------------------------------------------------------------------
+INFO:iMPACT - Current time: 11/7/2020 9:59:04 PM
+// *** BATCH CMD : Program -p 1 
+Maximum TCK operating frequency for this device chain: 25000000.
+Validating chain...
+Boundary-scan chain validated successfully.
+'1': Programming device...
+PROGRESS_START - Starting Operation.
+ LCK_cycle = NoWait.
+LCK cycle: NoWait
+done.
+'1': Reading status register contents...
+[0] CRC ERROR                                                              :        0
+[1] IDCODE ERROR                                                           :        0
+[2] DCM LOCK STATUS                                                        :        1
+[3] GTS_CFG_B STATUS                                                       :        1
+[4] GWE STATUS                                                             :        1
+[5] GHIGH STATUS                                                           :        1
+[6] DECRYPTION ERROR                                                       :        0
+[7] DECRYPTOR ENABLE                                                       :        0
+[8] HSWAPEN PIN                                                            :        1
+[9] MODE PIN M[0]                                                          :        1
+[10] MODE PIN M[1]                                                         :        1
+[11] RESERVED                                                              :        0
+[12] INIT_B PIN                                                            :        1
+[13] DONE PIN                                                              :        1
+[14] SUSPEND STATUS                                                        :        0
+[15] FALLBACK STATUS                                                       :        0
+INFO:iMPACT:2219 - Status register values:
+INFO:iMPACT - 0011 1100 1110 1100 
+INFO:iMPACT:579 - '1': Completed downloading bit file to device.
+INFO:iMPACT:188 - '1': Programming completed successfully.
+ LCK_cycle = NoWait.
+LCK cycle: NoWait
+INFO:iMPACT - '1': Checking done pin....done.
+'1': Programmed successfully.
+PROGRESS_END - End Operation.
+Elapsed time =      1 sec.
+Selected part: W25Q128FV
+// *** BATCH CMD : attachflash -position 1 -spi "W25Q128FV"
+Unprotect sectors: FALSE
+// *** BATCH CMD : assignfiletoattachedflash -position 1 -file"C:/MCL/MCL86/MCL86jr/Untitled.mcs"
+// *** BATCH CMD : setMode -bs
+// *** BATCH CMD : deleteDevice -position 1
+// *** BATCH CMD : setMode -bs
+// *** BATCH CMD : setMode -ss
+// *** BATCH CMD : setMode -sm
+// *** BATCH CMD : setMode -hw140
+// *** BATCH CMD : setMode -spi
+// *** BATCH CMD : setMode -acecf
+// *** BATCH CMD : setMode -acempm
+// *** BATCH CMD : setMode -pff
+// *** BATCH CMD : loadProjectFile -file"C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
+'1': Loading file 'C:\MCL\MCL86\MCL86jr\MCL86jr\mcl86jr.bit' ...
+INFO:iMPACT - Elapsed time =      0 sec.
+done.
+INFO:iMPACT:501 - '1': Added Device xc6slx9 successfully.
+----------------------------------------------------------------------
+'1': Added Device 16M successfully.
+----------------------------------------------------------------------
+Active mode is BS
+// *** BATCH CMD : setMode -ss
+// *** BATCH CMD : setMode -sm
+// *** BATCH CMD : setMode -hw140
+// *** BATCH CMD : setMode -spi
+// *** BATCH CMD : setMode -acecf
+// *** BATCH CMD : setMode -acempm
+// *** BATCH CMD : setMode -pff
+// *** BATCH CMD : setMode -bs
+// *** BATCH CMD : setMode -pff
+// *** BATCH CMD : setCurrentDesign -version 0
+// *** BATCH CMD : setMode -pff
+// *** BATCH CMD : setCurrentDeviceChain -index 0
+// *** BATCH CMD : setSubmode -pffspi
+// *** BATCH CMD : setMode -pff
+------------------------  GUI: Wizard Data Report  ---------------------------
+      Compression : false
+      Fill Value : FF
+      Output Format : mcs
+      Swap Bits : false
+      LoadDirection : UP
+      PROM Basename : Untitled
+      File Location : C:\MCL\MCL86\MCL86jr/
+      Auto Select : false
+      Number of Revisions : 1
+      Number of PROMs : 1
+      PROM Name : 16M   PROM Size : 16777216 bits
+        ------ Revision: 0 '0', 1 device(s) chain -----
+        Device 0, pn=xc6slx9   fn=mcl86jr.bit
+-------------------------- END of Report ----------------------------
+// *** BATCH CMD : setMode -bs
+// *** BATCH CMD : setMode -pff
+// *** BATCH CMD : setSubmode -pffspi
+// *** BATCH CMD : setMode -bs
+// *** BATCH CMD : setMode -pff
+// *** BATCH CMD : setSubmode -pffspi
+INFO:iMPACT - Current time: 11/7/2020 10:00:53 PM
+// *** BATCH CMD : setMode -pff
+// *** BATCH CMD : setSubmode -pffspi
+Total configuration bit size = 2727072  bits.
+Total configuration byte size = 340884 bytes.
+// *** BATCH CMD : generate
+0x53394 (340884) bytes loaded up from 0x0
+Using user-specified prom size of 16384K
+Writing file "C:\MCL\MCL86\MCL86jr\Untitled.mcs".
+Writing file "C:\MCL\MCL86\MCL86jr\Untitled.prm".
+Writing file "C:\MCL\MCL86\MCL86jr\Untitled.cfi".
+// *** BATCH CMD : setCurrentDesign -version 0
+// *** BATCH CMD : setMode -bs
+// *** BATCH CMD : setMode -pff
+// *** BATCH CMD : setSubmode -pffspi
+// *** BATCH CMD : setMode -bs
+// *** BATCH CMD : setMode -pff
+// *** BATCH CMD : setSubmode -pffspi
+// *** BATCH CMD : setMode -bs
+GUI --- Auto connect to cable...
+// *** BATCH CMD : setCable -port auto
+AutoDetecting cable. Please wait.
+*** WARNING ***: When port is set to auto detect mode, cable speed is set todefault 6 MHz regardless of explicit arguments supplied for setting the baudrates
+PROGRESS_START - Starting Operation.
+Connecting to cable (Usb Port - USB21).
+Checking cable driver.
+ Driver file xusb_xp2.sys found.
+ Driver version: src=2301, dest=2301.
+ Driver windrvr6.sys version = 10.2.1.0. WinDriver v10.21 Jungo (c) 1997 - 2010 Build Date: Aug 31 2010 x86_64 64bit SYS14:14:44, version = 1021.
+ Cable PID = 0008.
+ Max current requested during enumeration is 300 mA.
+Type = 0x0005.
+ Cable Type = 3, Revision = 0.
+ Setting cable speed to 6 MHz.
+Cable connection established.
+Firmware version = 2401.
+File version of C:/Xilinx/14.7/ISE_DS/ISE/data/xusb_xp2.hex = 2401.
+Firmware hex file version = 2401.
+PLD file version = 200Dh.
+ PLD version = 200Dh.
+PROGRESS_END - End Operation.
+Elapsed time =      1 sec.
+Type = 0x0005.
+ESN option: 0000149BE10901.
+Attempting to identify devices in the boundary-scan chain configuration...
+INFO:iMPACT - Current time: 11/7/2020 10:01:13 PM
+// *** BATCH CMD : Identify -inferir 
+PROGRESS_START - Starting Operation.
+Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc6slx9, Version : 2
+INFO:iMPACT:1777 - 
+   Reading C:/Xilinx/14.7/ISE_DS/ISE/spartan6/data/xc6slx9.bsd...
+INFO:iMPACT:501 - '1': Added Device xc6slx9 successfully.
+----------------------------------------------------------------------
+done.
+PROGRESS_END - End Operation.
+Elapsed time =      0 sec.
+// *** BATCH CMD : identifyMPM 
+Selected part: W25Q128FV
+// *** BATCH CMD : attachflash -position 1 -spi "W25Q128FV"
+Unprotect sectors: FALSE
+// *** BATCH CMD : assignfiletoattachedflash -position 1 -file"C:/MCL/MCL86/MCL86jr/Untitled.mcs"
+// *** BATCH CMD : setMode -bs
+// *** BATCH CMD : setMode -ss
+// *** BATCH CMD : setMode -sm
+// *** BATCH CMD : setMode -hw140
+// *** BATCH CMD : setMode -spi
+// *** BATCH CMD : setMode -acecf
+// *** BATCH CMD : setMode -acempm
+// *** BATCH CMD : setMode -pff
+// *** BATCH CMD : setMode -bs
+// *** BATCH CMD : saveProjectFile -file"C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
+INFO:iMPACT - Current time: 11/7/2020 10:01:48 PM
+// *** BATCH CMD : Program -p 1 -dataWidth 1 -spionly -e -v -loadfpga 
+Maximum TCK operating frequency for this device chain: 25000000.
+Validating chain...
+Boundary-scan chain validated successfully.
+'1': SPI access core not detected. SPI access core will be downloaded to thedevice to enable operations.
+INFO:iMPACT - Downloading core file   C:/Xilinx/14.7/ISE_DS/ISE/spartan6/data/xc6slx9_spi.cor.
+PROGRESS_START - Starting Operation.
+'1': Downloading core...
+ LCK_cycle = NoWait.
+LCK cycle: NoWait
+done.
+'1': Reading status register contents...
+INFO:iMPACT:2219 - Status register values:
+INFO:iMPACT - 0011 1100 1110 1100 
+INFO:iMPACT:2492 - '1': Completed downloading core to device.
+'1': IDCODE is 'ef4018' (in hex).
+'1': ID Check passed.
+'1': IDCODE is 'ef4018' (in hex).
+'1': ID Check passed.
+'1': Erasing Device.
+'1': Using Bulk Erase.
+'1': Erasing non-volatile quad-enable bit...
+'1': Programming Flash.
+'1': Reading device contents...
+done.
+'1': Verification completed.
+'1':Programming in x1 mode.
+W25Q128FV Status Register Contents = 0x0200.
+STATUS REGISTER PROTECT 0                         :         0
+SECTOR PROTECT                                    :         0
+TOP/BOTTOM PROTECT                                :         0
+BLOCK PROTECT BIT 2                               :         0
+BLOCK PROTECT BIT 1                               :         0
+BLOCK PROTECT BIT 0                               :         0
+'1': Configuration data download to FPGA was not successful. DONE did not gohigh, please check your configuration setup and mode settings.
+INFO:iMPACT - '1': Flash was not programmed successfully.
+PROGRESS_END - End Operation.
+Elapsed time =    141 sec.
+// *** BATCH CMD : setMode -bs
+// *** BATCH CMD : setMode -ss
+// *** BATCH CMD : setMode -sm
+// *** BATCH CMD : setMode -hw140
+// *** BATCH CMD : setMode -spi
+// *** BATCH CMD : setMode -acecf
+// *** BATCH CMD : setMode -acempm
+// *** BATCH CMD : setMode -pff
+// *** BATCH CMD : setMode -bs
+// *** BATCH CMD : saveProjectFile -file"C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
+// *** BATCH CMD : setMode -bs
+// *** BATCH CMD : setMode -ss
+// *** BATCH CMD : setMode -sm
+// *** BATCH CMD : setMode -hw140
+// *** BATCH CMD : setMode -spi
+// *** BATCH CMD : setMode -acecf
+// *** BATCH CMD : setMode -acempm
+// *** BATCH CMD : setMode -pff
+// *** BATCH CMD : setMode -bs
+// *** BATCH CMD : saveProjectFile -file"C:\MCL\MCL86\MCL86jr\MCL86jr_Impact.ipf"
+// *** BATCH CMD : setMode -bs
+// *** BATCH CMD : setMode -pff
+INFO:iMPACT - Launching WebTalk, please refer to the webtalk log at   C:\MCL\MCL86\MCL86jr/webtalk.log for details.
+INFO:iMPACT - Running wbtc successfully.
+// *** BATCH CMD : setMode -bs
+// *** BATCH CMD : deleteDevice -position 1
+// *** BATCH CMD : setMode -bs
+// *** BATCH CMD : setMode -ss
+// *** BATCH CMD : setMode -sm
+// *** BATCH CMD : setMode -hw140
+// *** BATCH CMD : setMode -spi
+// *** BATCH CMD : setMode -acecf
+// *** BATCH CMD : setMode -acempm
+// *** BATCH CMD : setMode -pff
+// *** BATCH CMD : deletePromDevice -position 1
+// *** BATCH CMD : setCurrentDesign -version 0
+// *** BATCH CMD : deleteDevice -position 1
+// *** BATCH CMD : deleteDesign -version 0
+// *** BATCH CMD : setCurrentDesign -version -1
diff --git a/MCL86jr/FPGA/MCL86jr/_ngo/netlist.lst b/MCL86jr/FPGA/MCL86jr/_ngo/netlist.lst
new file mode 100644
index 0000000..054369a
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/_ngo/netlist.lst
@@ -0,0 +1,3 @@
+C:\MCL\MCL86\MCL86jr\MCL86jr\MCL86jr.ngc 1605150614
+ipcore_dir/EU4Kx32.ngc 1599965148
+OK
diff --git a/MCL86jr/FPGA/MCL86jr/_xmsgs/bitgen.xmsgs b/MCL86jr/FPGA/MCL86jr/_xmsgs/bitgen.xmsgs
new file mode 100644
index 0000000..7506831
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/_xmsgs/bitgen.xmsgs
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="Bitgen" num="341" delta="old" >This design is using one or more 9K Block RAMs (RAMB8BWER).  9K Block RAM initialization data, both user defined and default, requires a special bit stream format.  For more information, please reference Xilinx Answer Record 39999.
+</msg>
+
+<msg type="info" file="PhysDesignRules" num="1861" delta="old" >To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp <arg fmt="%s" index="1">SPARTAN6PLL/dcm_sp_inst</arg>, consult the device Data Sheet.
+</msg>
+
+<msg type="warning" file="PhysDesignRules" num="2410" delta="old" >This design is using one or more 9K Block RAMs (RAMB8BWER).  9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used.  For more information, please reference Xilinx Answer Record 39999.
+</msg>
+
+</messages>
+
diff --git a/MCL86jr/FPGA/MCL86jr/_xmsgs/map.xmsgs b/MCL86jr/FPGA/MCL86jr/_xmsgs/map.xmsgs
new file mode 100644
index 0000000..778412d
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/_xmsgs/map.xmsgs
@@ -0,0 +1,39 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">EU_CORE/EU4Kx32_i/douta&lt;31&gt;</arg> has no load.
+</msg>
+
+<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
+</msg>
+
+<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
+</msg>
+
+<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
+</msg>
+
+<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
+</msg>
+
+<msg type="warning" file="Timing" num="3402" delta="old" >The Clock Modifying COMP, <arg fmt="%s" index="1">SPARTAN6PLL/dcm_sp_inst</arg>, has the attribute CLK_FEEDBACK set to NONE.  No phase relationship exists between the input and output clocks of this Clock Modifying COMP. Data paths between these clock domains must be constrained using FROM/TO constraints.
+</msg>
+
+<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
+</msg>
+
+<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
+</msg>
+
+<msg type="info" file="PhysDesignRules" num="1861" delta="old" >To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp <arg fmt="%s" index="1">SPARTAN6PLL/dcm_sp_inst</arg>, consult the device Data Sheet.
+</msg>
+
+<msg type="warning" file="PhysDesignRules" num="2410" delta="old" >This design is using one or more 9K Block RAMs (RAMB8BWER).  9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used.  For more information, please reference Xilinx Answer Record 39999.
+</msg>
+
+</messages>
+
diff --git a/MCL86jr/FPGA/MCL86jr/_xmsgs/ngdbuild.xmsgs b/MCL86jr/FPGA/MCL86jr/_xmsgs/ngdbuild.xmsgs
new file mode 100644
index 0000000..0a35564
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/_xmsgs/ngdbuild.xmsgs
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">CORE_CLK</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_CORE_CLK</arg>&apos;, was traced into <arg fmt="%s" index="4">DCM_SP</arg> instance <arg fmt="%s" index="5">SPARTAN6PLL/dcm_sp_inst</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">DCM_SP</arg> output(s): 
+<arg fmt="%s" index="7">CLKFX</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_SPARTAN6PLL_clkfx = PERIOD &quot;SPARTAN6PLL_clkfx&quot; TS_CORE_CLK / 2.2 HIGH 50%&gt;</arg>
+</msg>
+
+</messages>
+
diff --git a/MCL86jr/FPGA/MCL86jr/_xmsgs/par.xmsgs b/MCL86jr/FPGA/MCL86jr/_xmsgs/par.xmsgs
new file mode 100644
index 0000000..4121289
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/_xmsgs/par.xmsgs
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="Timing" num="3402" delta="old" >The Clock Modifying COMP, <arg fmt="%s" index="1">SPARTAN6PLL/dcm_sp_inst</arg>, has the attribute CLK_FEEDBACK set to NONE.  No phase relationship exists between the input and output clocks of this Clock Modifying COMP. Data paths between these clock domains must be constrained using FROM/TO constraints.
+</msg>
+
+</messages>
+
diff --git a/MCL86jr/FPGA/MCL86jr/_xmsgs/pn_parser.xmsgs b/MCL86jr/FPGA/MCL86jr/_xmsgs/pn_parser.xmsgs
new file mode 100644
index 0000000..1d1294c
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/_xmsgs/pn_parser.xmsgs
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated   -->
+<!--     by the Xilinx ISE software.  Any direct editing or        -->
+<!--     changes made to this file may result in unpredictable     -->
+<!--     behavior or data corruption.  It is strongly advised that -->
+<!--     users do not edit the contents of this file.              -->
+<!--                                                               -->
+<!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.    -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/MCL/MCL86/MCL86jr/src4synth/MCL86jr.v&quot; into library work</arg>
+</msg>
+
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/MCL/MCL86/MCL86jr/src4synth/biu_min.v&quot; into library work</arg>
+</msg>
+
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/MCL/MCL86/MCL86jr/src4synth/eu.v&quot; into library work</arg>
+</msg>
+
+</messages>
+
diff --git a/MCL86jr/FPGA/MCL86jr/_xmsgs/trce.xmsgs b/MCL86jr/FPGA/MCL86jr/_xmsgs/trce.xmsgs
new file mode 100644
index 0000000..f104f37
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/_xmsgs/trce.xmsgs
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="Timing" num="3402" delta="old" >The Clock Modifying COMP, <arg fmt="%s" index="1">SPARTAN6PLL/dcm_sp_inst</arg>, has the attribute CLK_FEEDBACK set to NONE.  No phase relationship exists between the input and output clocks of this Clock Modifying COMP. Data paths between these clock domains must be constrained using FROM/TO constraints.
+</msg>
+
+<msg type="info" file="Timing" num="3412" delta="old" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
+
+<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
+
+<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
+
+</messages>
+
diff --git a/MCL86jr/FPGA/MCL86jr/_xmsgs/xst.xmsgs b/MCL86jr/FPGA/MCL86jr/_xmsgs/xst.xmsgs
new file mode 100644
index 0000000..cec9e99
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/_xmsgs/xst.xmsgs
@@ -0,0 +1,186 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\spartan6_pll.v" Line 111: Assignment to <arg fmt="%s" index="1">clk0</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\spartan6_pll.v" Line 126: Assignment to <arg fmt="%s" index="1">locked_int</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\spartan6_pll.v" Line 127: Assignment to <arg fmt="%s" index="1">status_int</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 182: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">1</arg>-bit target.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 183: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">1</arg>-bit target.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 184: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">1</arg>-bit target.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 185: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">1</arg>-bit target.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 186: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">1</arg>-bit target.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 187: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">1</arg>-bit target.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 188: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">1</arg>-bit target.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 189: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">1</arg>-bit target.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v" Line 213: Assignment to <arg fmt="%s" index="1">t_eu_flag_i_d</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 231: Assignment to <arg fmt="%s" index="1">eu_qs_out</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 477: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">13</arg>-bit target.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 493: Result of <arg fmt="%d" index="1">17</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">16</arg>-bit target.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 503: Result of <arg fmt="%d" index="1">17</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">16</arg>-bit target.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 835: Result of <arg fmt="%d" index="1">17</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">16</arg>-bit target.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\biu_min.v" Line 276: Assignment to <arg fmt="%s" index="1">ready_d3</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1499" delta="old" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\EU4Kx32.v" Line 39: Empty module &lt;<arg fmt="%s" index="1">EU4Kx32</arg>&gt; remains a black box.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 264: Assignment to <arg fmt="%s" index="1">eu_prefix_repnz</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 265: Assignment to <arg fmt="%s" index="1">eu_prefix_rep</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 268: Assignment to <arg fmt="%s" index="1">eu_flag_o</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 269: Assignment to <arg fmt="%s" index="1">eu_flag_d</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 272: Assignment to <arg fmt="%s" index="1">eu_flag_s</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 273: Assignment to <arg fmt="%s" index="1">eu_flag_z</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 275: Assignment to <arg fmt="%s" index="1">eu_flag_a</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 276: Assignment to <arg fmt="%s" index="1">eu_nmi_pending</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 277: Assignment to <arg fmt="%s" index="1">eu_flag_p</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 278: Assignment to <arg fmt="%s" index="1">eu_flag_temp</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 279: Assignment to <arg fmt="%s" index="1">eu_flag_c</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="413" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 298: Result of <arg fmt="%d" index="1">20</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">16</arg>-bit target.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 338: Assignment to <arg fmt="%s" index="1">biu_done_d2</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="old" >"C:\MCL\MCL86\MCL86jr\src4synth\eu.v" Line 147: Net &lt;<arg fmt="%s" index="1">system_signals[15]</arg>&gt; does not have a driver.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v</arg>&quot; line <arg fmt="%s" index="2">269</arg>: Output port &lt;<arg fmt="%s" index="3">BIU_SEGMENT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">BIU_CORE</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v</arg>&quot; line <arg fmt="%s" index="2">322</arg>: Output port &lt;<arg fmt="%s" index="3">EU_FLAG_I</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">EU_CORE</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">EU_BIU_COMMAND&lt;3:2&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">EU_BIU_COMMAND&lt;15:15&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">EU_PREFIX_LOCK</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">system_signals&lt;15:14&gt;</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">system_signals&lt;10&gt;</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">mcl6_feature_2</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">BIU_CORE</arg>&gt;.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">mcl6_feature_3</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">BIU_CORE</arg>&gt;.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">mcl6_feature_4</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">BIU_CORE</arg>&gt;.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">mcl6_feature_5</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">BIU_CORE</arg>&gt;.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">mcl6_feature_6</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">BIU_CORE</arg>&gt;.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">mcl6_feature_7</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">BIU_CORE</arg>&gt;.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">mcl6_feature_2</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">biu_min</arg>&gt;.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">mcl6_feature_3</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">biu_min</arg>&gt;.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">mcl6_feature_4</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">biu_min</arg>&gt;.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">mcl6_feature_5</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">biu_min</arg>&gt;.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">mcl6_feature_6</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">biu_min</arg>&gt;.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">mcl6_feature_7</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">biu_min</arg>&gt;.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">prescaler_22</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">MCL86jr</arg>&gt;.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">prescaler_23</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">MCL86jr</arg>&gt;.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">prescaler_24</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">MCL86jr</arg>&gt;.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">prescaler_25</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">MCL86jr</arg>&gt;.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">prescaler_26</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">MCL86jr</arg>&gt;.
+</msg>
+
+<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">BIU_CORE/eu_biu_req_d1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">MCL86jr</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;EU_CORE/eu_biu_req_d1&gt; </arg>
+</msg>
+
+<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
+</msg>
+
+</messages>
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.asy b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.asy
new file mode 100644
index 0000000..9c4bfc2
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.asy
@@ -0,0 +1,17 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 EU4Kx32
+RECTANGLE Normal 32 32 544 1376
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName addra[11:0]
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName clka
+PINATTR Polarity IN
+LINE Wide 576 80 544 80
+PIN 576 80 RIGHT 36
+PINATTR PinName douta[31:0]
+PINATTR Polarity OUT
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.gise b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.gise
new file mode 100644
index 0000000..a2a9f84
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.gise
@@ -0,0 +1,52 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="EU4Kx32.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="EU4Kx32.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="EU4Kx32.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema">
+    <transform xil_pn:end_ts="1599968965" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1599968965">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150596" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3493971842567525973" xil_pn:start_ts="1605150596">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150596" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="2061036881009002330" xil_pn:start_ts="1605150596">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150596" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1605150596">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150596" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1277724965906371437" xil_pn:start_ts="1605150596">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+  </transforms>
+
+</generated_project>
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.mif b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.mif
new file mode 100644
index 0000000..0684ca9
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.mif
@@ -0,0 +1,4096 @@
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diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.ncf b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.ncf
new file mode 100644
index 0000000..e69de29
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.ngc b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.ngc
new file mode 100644
index 0000000..29c6f18
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.ngc
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\ No newline at end of file
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.v b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.v
new file mode 100644
index 0000000..cd46d58
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.v
@@ -0,0 +1,176 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
+*                                                                              *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
+*                                                                              *
+*     (c) Copyright 1995-2020 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// You must compile the wrapper file EU4Kx32.v when simulating
+// the core, EU4Kx32. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+`timescale 1ns/1ps
+
+module EU4Kx32(
+  clka,
+  addra,
+  douta
+);
+
+input clka;
+input [11 : 0] addra;
+output [31 : 0] douta;
+
+// synthesis translate_off
+
+  BLK_MEM_GEN_V7_3 #(
+    .C_ADDRA_WIDTH(12),
+    .C_ADDRB_WIDTH(12),
+    .C_ALGORITHM(1),
+    .C_AXI_ID_WIDTH(4),
+    .C_AXI_SLAVE_TYPE(0),
+    .C_AXI_TYPE(1),
+    .C_BYTE_SIZE(9),
+    .C_COMMON_CLK(0),
+    .C_DEFAULT_DATA("0"),
+    .C_DISABLE_WARN_BHV_COLL(0),
+    .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_ENABLE_32BIT_ADDRESS(0),
+    .C_FAMILY("spartan6"),
+    .C_HAS_AXI_ID(0),
+    .C_HAS_ENA(0),
+    .C_HAS_ENB(0),
+    .C_HAS_INJECTERR(0),
+    .C_HAS_MEM_OUTPUT_REGS_A(0),
+    .C_HAS_MEM_OUTPUT_REGS_B(0),
+    .C_HAS_MUX_OUTPUT_REGS_A(0),
+    .C_HAS_MUX_OUTPUT_REGS_B(0),
+    .C_HAS_REGCEA(0),
+    .C_HAS_REGCEB(0),
+    .C_HAS_RSTA(0),
+    .C_HAS_RSTB(0),
+    .C_HAS_SOFTECC_INPUT_REGS_A(0),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
+    .C_INIT_FILE("BlankString"),
+    .C_INIT_FILE_NAME("EU4Kx32.mif"),
+    .C_INITA_VAL("0"),
+    .C_INITB_VAL("0"),
+    .C_INTERFACE_TYPE(0),
+    .C_LOAD_INIT_FILE(1),
+    .C_MEM_TYPE(3),
+    .C_MUX_PIPELINE_STAGES(0),
+    .C_PRIM_TYPE(1),
+    .C_READ_DEPTH_A(4096),
+    .C_READ_DEPTH_B(4096),
+    .C_READ_WIDTH_A(32),
+    .C_READ_WIDTH_B(32),
+    .C_RST_PRIORITY_A("CE"),
+    .C_RST_PRIORITY_B("CE"),
+    .C_RST_TYPE("SYNC"),
+    .C_RSTRAM_A(0),
+    .C_RSTRAM_B(0),
+    .C_SIM_COLLISION_CHECK("ALL"),
+    .C_USE_BRAM_BLOCK(0),
+    .C_USE_BYTE_WEA(0),
+    .C_USE_BYTE_WEB(0),
+    .C_USE_DEFAULT_DATA(0),
+    .C_USE_ECC(0),
+    .C_USE_SOFTECC(0),
+    .C_WEA_WIDTH(1),
+    .C_WEB_WIDTH(1),
+    .C_WRITE_DEPTH_A(4096),
+    .C_WRITE_DEPTH_B(4096),
+    .C_WRITE_MODE_A("WRITE_FIRST"),
+    .C_WRITE_MODE_B("WRITE_FIRST"),
+    .C_WRITE_WIDTH_A(32),
+    .C_WRITE_WIDTH_B(32),
+    .C_XDEVICEFAMILY("spartan6")
+  )
+  inst (
+    .CLKA(clka),
+    .ADDRA(addra),
+    .DOUTA(douta),
+    .RSTA(),
+    .ENA(),
+    .REGCEA(),
+    .WEA(),
+    .DINA(),
+    .CLKB(),
+    .RSTB(),
+    .ENB(),
+    .REGCEB(),
+    .WEB(),
+    .ADDRB(),
+    .DINB(),
+    .DOUTB(),
+    .INJECTSBITERR(),
+    .INJECTDBITERR(),
+    .SBITERR(),
+    .DBITERR(),
+    .RDADDRECC(),
+    .S_ACLK(),
+    .S_ARESETN(),
+    .S_AXI_AWID(),
+    .S_AXI_AWADDR(),
+    .S_AXI_AWLEN(),
+    .S_AXI_AWSIZE(),
+    .S_AXI_AWBURST(),
+    .S_AXI_AWVALID(),
+    .S_AXI_AWREADY(),
+    .S_AXI_WDATA(),
+    .S_AXI_WSTRB(),
+    .S_AXI_WLAST(),
+    .S_AXI_WVALID(),
+    .S_AXI_WREADY(),
+    .S_AXI_BID(),
+    .S_AXI_BRESP(),
+    .S_AXI_BVALID(),
+    .S_AXI_BREADY(),
+    .S_AXI_ARID(),
+    .S_AXI_ARADDR(),
+    .S_AXI_ARLEN(),
+    .S_AXI_ARSIZE(),
+    .S_AXI_ARBURST(),
+    .S_AXI_ARVALID(),
+    .S_AXI_ARREADY(),
+    .S_AXI_RID(),
+    .S_AXI_RDATA(),
+    .S_AXI_RRESP(),
+    .S_AXI_RLAST(),
+    .S_AXI_RVALID(),
+    .S_AXI_RREADY(),
+    .S_AXI_INJECTSBITERR(),
+    .S_AXI_INJECTDBITERR(),
+    .S_AXI_SBITERR(),
+    .S_AXI_DBITERR(),
+    .S_AXI_RDADDRECC()
+  );
+
+// synthesis translate_on
+
+endmodule
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.veo b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.veo
new file mode 100644
index 0000000..48832f8
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.veo
@@ -0,0 +1,61 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
+*                                                                              *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
+*                                                                              *
+*     (c) Copyright 1995-2020 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+
+/*******************************************************************************
+*     Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.3       *
+*                                                                              *
+*     The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port     *
+*     Block Memory and Single Port Block Memory LogiCOREs, but is not a        *
+*     direct drop-in replacement.  It should be used in all new Xilinx         *
+*     designs. The core supports RAM and ROM functions over a wide range of    *
+*     widths and depths. Use this core to generate block memories with         *
+*     symmetric or asymmetric read and write port widths, as well as cores     *
+*     which can perform simultaneous write operations to separate              *
+*     locations, and simultaneous read operations from the same location.      *
+*     For more information on differences in interface and feature support     *
+*     between this core and the Dual Port Block Memory and Single Port         *
+*     Block Memory LogiCOREs, please consult the data sheet.                   *
+*******************************************************************************/
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+EU4Kx32 your_instance_name (
+  .clka(clka), // input clka
+  .addra(addra), // input [11 : 0] addra
+  .douta(douta) // output [31 : 0] douta
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file EU4Kx32.v when simulating
+// the core, EU4Kx32. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.xco b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.xco
new file mode 100644
index 0000000..14399de
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.xco
@@ -0,0 +1,108 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Sun Sep 13 03:44:44 2020
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:blk_mem_gen:7.3
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
+# END Select
+# BEGIN Parameters
+CSET additional_inputs_for_power_estimation=false
+CSET algorithm=Minimum_Area
+CSET assume_synchronous_clk=false
+CSET axi_id_width=4
+CSET axi_slave_type=Memory_Slave
+CSET axi_type=AXI4_Full
+CSET byte_size=9
+CSET coe_file=C:\MCL\MCL86\MCL86jr\src4synth\MCL86_Microcode_Xilinx.coe
+CSET collision_warnings=ALL
+CSET component_name=EU4Kx32
+CSET disable_collision_warnings=false
+CSET disable_out_of_range_warnings=false
+CSET ecc=false
+CSET ecctype=No_ECC
+CSET enable_32bit_address=false
+CSET enable_a=Always_Enabled
+CSET enable_b=Always_Enabled
+CSET error_injection_type=Single_Bit_Error_Injection
+CSET fill_remaining_memory_locations=false
+CSET interface_type=Native
+CSET load_init_file=true
+CSET mem_file=no_Mem_file_loaded
+CSET memory_type=Single_Port_ROM
+CSET operating_mode_a=WRITE_FIRST
+CSET operating_mode_b=WRITE_FIRST
+CSET output_reset_value_a=0
+CSET output_reset_value_b=0
+CSET pipeline_stages=0
+CSET port_a_clock=100
+CSET port_a_enable_rate=100
+CSET port_a_write_rate=0
+CSET port_b_clock=0
+CSET port_b_enable_rate=0
+CSET port_b_write_rate=0
+CSET primitive=8kx2
+CSET read_width_a=32
+CSET read_width_b=32
+CSET register_porta_input_of_softecc=false
+CSET register_porta_output_of_memory_core=false
+CSET register_porta_output_of_memory_primitives=false
+CSET register_portb_output_of_memory_core=false
+CSET register_portb_output_of_memory_primitives=false
+CSET register_portb_output_of_softecc=false
+CSET remaining_memory_locations=0
+CSET reset_memory_latch_a=false
+CSET reset_memory_latch_b=false
+CSET reset_priority_a=CE
+CSET reset_priority_b=CE
+CSET reset_type=SYNC
+CSET softecc=false
+CSET use_axi_id=false
+CSET use_bram_block=Stand_Alone
+CSET use_byte_write_enable=false
+CSET use_error_injection_pins=false
+CSET use_regcea_pin=false
+CSET use_regceb_pin=false
+CSET use_rsta_pin=false
+CSET use_rstb_pin=false
+CSET write_depth_a=4096
+CSET write_width_a=32
+CSET write_width_b=32
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-19T16:22:25Z
+# END Extra information
+GENERATE
+# CRC: e19ac0b2
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.xise b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.xise
new file mode 100644
index 0000000..79a245a
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32.xise
@@ -0,0 +1,69 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="EU4Kx32.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|EU4Kx32" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="EU4Kx32.ngc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/EU4Kx32" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="EU4Kx32" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-09-12T20:46:10" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B4491F8D5FD346FAADBE82E21925FDE4" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/blk_mem_gen_v7_3_readme.txt b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/blk_mem_gen_v7_3_readme.txt
new file mode 100644
index 0000000..80625fa
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/blk_mem_gen_v7_3_readme.txt
@@ -0,0 +1,213 @@
+                Core name: Xilinx LogiCORE Block Memory Generator
+                Version: 7.3 Rev 1
+                Release: ISE 14.4 / Vivado 2012.4
+                Release Date: October 16, 2012
+
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURES HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.3 
+solution. For the latest core updates, see the product page at:
+ 
+ http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
+
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+  Zynq-7000 devices
+  All Virtex-6 devices
+  All Spartan-6 devices
+  All Virtex-5 devices
+  All Spartan-3 devices
+  All Virtex-4 devices
+  
+
+  2.2 Vivado 
+  All 7 Series devices
+  Zynq-7000 devices
+
+................................................................................
+
+3. NEW FEATURES HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+
+  3.2 Vivado
+  
+    - 2012.4 software support
+
+
+................................................................................
+
+
+4. RESOLVED ISSUES
+
+
+The following issues are resolved in Block Memory Generator v7.3: 
+  
+  4.1 ISE 
+  
+
+  4.2 Vivado
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+
+    The following are known issues for v7.3 of this core at time of release:
+  
+    1. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
+  
+    3. Core does not generate for large memories. Depending on the
+       machine the ISE CORE Generator software runs on, the maximum size of the memory that
+       can be generated will vary.  For example, a Dual Pentium-4 server 
+       with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
+      - CR 415768
+      - AR 24034
+    
+
+  5.2 Vivado 
+
+    The following are known issues for v7.3 of this core at time of release:
+     
+  The most recent information, including known issues, workarounds, and resolutions for 
+  this version is provided in the IP Release Notes User Guide located at
+    
+         www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/16/2012  Xilinx, Inc.  7.3 Rev 1    ISE 14.4 and Vivado 2012.4 support;
+10/16/2012  Xilinx, Inc.  7.3          ISE 14.3 and Vivado 2012.3 support;
+07/25/2012  Xilinx, Inc.  7.2          ISE 14.2 and Vivado 2012.2 support;
+04/24/2012  Xilinx, Inc.  7.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+01/18/2011  Xilinx, Inc.  6.3          ISE 13.4 support;Artix7L*, AArtix-7* device support 
+06/22/2011  Xilinx, Inc.  6.2          ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
+03/01/2011  Xilinx, Inc.  6.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
+09/21/2010  Xilinx, Inc.  4.3          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  4.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  4.1          ISE 12.1 support
+03/09/2010  Xilinx, Inc.  3.3 rev 2    Fix for V6 Memory collision issue 
+12/02/2009  Xilinx, Inc.  3.3 rev 1    ISE 11.4 support; Spartan-6 Low Power
+                                       Device support; Automotive Spartan 3A
+                                       DSP device support
+09/16/2009  Xilinx, Inc.  3.3          Revised to v3.3
+06/24/2009  Xilinx, Inc.  3.2          Revised to v3.2
+04/24/2009  Xilinx, Inc.  3.1          Revised to v3.1
+09/19/2008  Xilinx, Inc.  2.8          Revised to v2.8
+03/24/2008  Xilinx, Inc.  2.7          10.1 support; Revised to v2.7
+10/03/2007  Xilinx, Inc.  2.6          Revised to v2.6
+07/2007     Xilinx, Inc.  2.5          Revised to v2.5
+04/2007     Xilinx, Inc.  2.4          Revised to v2.4 rev 1
+02/2007     Xilinx, Inc.  2.4          Revised to v2.4
+11/2006     Xilinx, Inc.  2.3          Revised to v2.3
+09/2006     Xilinx, Inc.  2.2          Revised to v2.2
+06/2006     Xilinx, Inc.  2.1          Revised to v2.1
+01/2006     Xilinx, Inc.  1.1          Initial release
+================================================================================
+
+8. Legal Disclaimer
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/doc/blk_mem_gen_v7_3_vinfo.html b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/doc/blk_mem_gen_v7_3_vinfo.html
new file mode 100644
index 0000000..01edd02
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/doc/blk_mem_gen_v7_3_vinfo.html
@@ -0,0 +1,224 @@
+<HTML>
+<HEAD>
+<TITLE>blk_mem_gen_v7_3_vinfo</TITLE>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
+</HEAD>
+<BODY>
+<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
+                Core name: Xilinx LogiCORE Block Memory Generator
+                Version: 7.3 Rev 1
+                Release: ISE 14.4 / Vivado 2012.4
+                Release Date: October 16, 2012
+
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURES HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
+
+For system requirements:
+
+   <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
+
+This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.3 
+solution. For the latest core updates, see the product page at:
+ 
+ <A HREF="http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm">www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm</A>
+
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+  Zynq-7000 devices
+  All Virtex-6 devices
+  All Spartan-6 devices
+  All Virtex-5 devices
+  All Spartan-3 devices
+  All Virtex-4 devices
+  
+
+  2.2 Vivado 
+  All 7 Series devices
+  Zynq-7000 devices
+
+................................................................................
+
+3. NEW FEATURES HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+
+  3.2 Vivado
+  
+    - 2012.4 software support
+
+
+................................................................................
+
+
+4. RESOLVED ISSUES
+
+
+The following issues are resolved in Block Memory Generator v7.3: 
+  
+  4.1 ISE 
+  
+
+  4.2 Vivado
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+
+    The following are known issues for v7.3 of this core at time of release:
+  
+    1. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
+  
+    3. Core does not generate for large memories. Depending on the
+       machine the ISE CORE Generator software runs on, the maximum size of the memory that
+       can be generated will vary.  For example, a Dual Pentium-4 server 
+       with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
+      - CR 415768
+      - AR 24034
+    
+
+  5.2 Vivado 
+
+    The following are known issues for v7.3 of this core at time of release:
+     
+  The most recent information, including known issues, workarounds, and resolutions for 
+  this version is provided in the IP Release Notes User Guide located at
+    
+         <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/16/2012  Xilinx, Inc.  7.3 Rev 1    ISE 14.4 and Vivado 2012.4 support;
+10/16/2012  Xilinx, Inc.  7.3          ISE 14.3 and Vivado 2012.3 support;
+07/25/2012  Xilinx, Inc.  7.2          ISE 14.2 and Vivado 2012.2 support;
+04/24/2012  Xilinx, Inc.  7.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+01/18/2011  Xilinx, Inc.  6.3          ISE 13.4 support;Artix7L*, AArtix-7* device support 
+06/22/2011  Xilinx, Inc.  6.2          ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
+03/01/2011  Xilinx, Inc.  6.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
+09/21/2010  Xilinx, Inc.  4.3          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  4.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  4.1          ISE 12.1 support
+03/09/2010  Xilinx, Inc.  3.3 rev 2    Fix for V6 Memory collision issue 
+12/02/2009  Xilinx, Inc.  3.3 rev 1    ISE 11.4 support; Spartan-6 Low Power
+                                       Device support; Automotive Spartan 3A
+                                       DSP device support
+09/16/2009  Xilinx, Inc.  3.3          Revised to v3.3
+06/24/2009  Xilinx, Inc.  3.2          Revised to v3.2
+04/24/2009  Xilinx, Inc.  3.1          Revised to v3.1
+09/19/2008  Xilinx, Inc.  2.8          Revised to v2.8
+03/24/2008  Xilinx, Inc.  2.7          10.1 support; Revised to v2.7
+10/03/2007  Xilinx, Inc.  2.6          Revised to v2.6
+07/2007     Xilinx, Inc.  2.5          Revised to v2.5
+04/2007     Xilinx, Inc.  2.4          Revised to v2.4 rev 1
+02/2007     Xilinx, Inc.  2.4          Revised to v2.4
+11/2006     Xilinx, Inc.  2.3          Revised to v2.3
+09/2006     Xilinx, Inc.  2.2          Revised to v2.2
+06/2006     Xilinx, Inc.  2.1          Revised to v2.1
+01/2006     Xilinx, Inc.  1.1          Initial release
+================================================================================
+
+8. Legal Disclaimer
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
+</FONT>
+</PRE>
+</BODY>
+</HTML>
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/doc/pg058-blk-mem-gen.pdf b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/doc/pg058-blk-mem-gen.pdf
new file mode 100644
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diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/example_design/EU4Kx32_exdes.ucf b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/example_design/EU4Kx32_exdes.ucf
new file mode 100644
index 0000000..9b76567
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/example_design/EU4Kx32_exdes.ucf
@@ -0,0 +1,57 @@
+################################################################################
+#
+# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Tx Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+NET "CLKA"  TNM_NET     = "CLKA";
+
+TIMESPEC "TS_CLKA"      = PERIOD "CLKA"  25 MHZ;
+
+################################################################################
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/example_design/EU4Kx32_exdes.vhd b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/example_design/EU4Kx32_exdes.vhd
new file mode 100644
index 0000000..5c5d0fb
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/example_design/EU4Kx32_exdes.vhd
@@ -0,0 +1,151 @@
+ 
+ 
+ 
+
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7.1 Core - Top-level core wrapper
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: EU4Kx32_exdes.vhd
+--
+-- Description:
+--   This is the actual BMG core wrapper.
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: August 31, 2005 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY UNISIM;
+USE UNISIM.VCOMPONENTS.ALL;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+ENTITY EU4Kx32_exdes IS
+  PORT (
+      --Inputs - Port A
+    ADDRA          : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+  
+    DOUTA          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    CLKA       : IN STD_LOGIC
+
+
+  );
+
+END EU4Kx32_exdes;
+
+
+ARCHITECTURE xilinx OF EU4Kx32_exdes IS
+
+  COMPONENT BUFG IS
+  PORT (
+     I      : IN STD_ULOGIC;
+     O      : OUT STD_ULOGIC
+  );
+  END COMPONENT;
+
+  COMPONENT EU4Kx32 IS
+  PORT (
+      --Port A
+    ADDRA      : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+  
+    DOUTA      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+    CLKA       : IN STD_LOGIC
+
+
+
+  );
+  END COMPONENT;
+
+  SIGNAL CLKA_buf     : STD_LOGIC;
+  SIGNAL CLKB_buf     : STD_LOGIC;
+  SIGNAL S_ACLK_buf   : STD_LOGIC;
+
+BEGIN
+
+  bufg_A : BUFG
+    PORT MAP (
+     I => CLKA,
+     O => CLKA_buf
+     );
+
+
+
+  bmg0 : EU4Kx32
+    PORT MAP (
+      --Port A
+      ADDRA      => ADDRA,
+  
+      DOUTA      => DOUTA,
+
+      CLKA       => CLKA_buf
+
+
+    );
+
+END xilinx;
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/example_design/EU4Kx32_exdes.xdc b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/example_design/EU4Kx32_exdes.xdc
new file mode 100644
index 0000000..3dc2b0f
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/example_design/EU4Kx32_exdes.xdc
@@ -0,0 +1,54 @@
+################################################################################
+#
+# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ]
+################################################################################
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/example_design/EU4Kx32_prod.vhd b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/example_design/EU4Kx32_prod.vhd
new file mode 100644
index 0000000..304732e
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/example_design/EU4Kx32_prod.vhd
@@ -0,0 +1,260 @@
+ 
+ 
+ 
+
+
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7.1 Core - Top-level wrapper
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--------------------------------------------------------------------------------
+--
+-- Filename: EU4Kx32_prod.vhd
+--
+-- Description:
+--   This is the top-level BMG wrapper (over BMG core).
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: August 31, 2005 - First Release
+--------------------------------------------------------------------------------
+--
+-- Configured Core Parameter Values:
+-- (Refer to the SIM Parameters table in the datasheet for more information on
+-- the these parameters.)
+--    C_FAMILY                    :  spartan6 
+--    C_XDEVICEFAMILY             :  spartan6 
+--    C_INTERFACE_TYPE            :  0 
+--    C_ENABLE_32BIT_ADDRESS      :  0 
+--    C_AXI_TYPE                  :  1 
+--    C_AXI_SLAVE_TYPE            :  0 
+--    C_AXI_ID_WIDTH              :  4 
+--    C_MEM_TYPE                  :  3 
+--    C_BYTE_SIZE                 :  9 
+--    C_ALGORITHM                 :  1 
+--    C_PRIM_TYPE                 :  1 
+--    C_LOAD_INIT_FILE            :  1 
+--    C_INIT_FILE_NAME            :  EU4Kx32.mif 
+--    C_USE_DEFAULT_DATA          :  0 
+--    C_DEFAULT_DATA              :  0 
+--    C_RST_TYPE                  :  SYNC 
+--    C_HAS_RSTA                  :  0 
+--    C_RST_PRIORITY_A            :  CE 
+--    C_RSTRAM_A                  :  0 
+--    C_INITA_VAL                 :  0 
+--    C_HAS_ENA                   :  0 
+--    C_HAS_REGCEA                :  0 
+--    C_USE_BYTE_WEA              :  0 
+--    C_WEA_WIDTH                 :  1 
+--    C_WRITE_MODE_A              :  WRITE_FIRST 
+--    C_WRITE_WIDTH_A             :  32 
+--    C_READ_WIDTH_A              :  32 
+--    C_WRITE_DEPTH_A             :  4096 
+--    C_READ_DEPTH_A              :  4096 
+--    C_ADDRA_WIDTH               :  12 
+--    C_HAS_RSTB                  :  0 
+--    C_RST_PRIORITY_B            :  CE 
+--    C_RSTRAM_B                  :  0 
+--    C_INITB_VAL                 :  0 
+--    C_HAS_ENB                   :  0 
+--    C_HAS_REGCEB                :  0 
+--    C_USE_BYTE_WEB              :  0 
+--    C_WEB_WIDTH                 :  1 
+--    C_WRITE_MODE_B              :  WRITE_FIRST 
+--    C_WRITE_WIDTH_B             :  32 
+--    C_READ_WIDTH_B              :  32 
+--    C_WRITE_DEPTH_B             :  4096 
+--    C_READ_DEPTH_B              :  4096 
+--    C_ADDRB_WIDTH               :  12 
+--    C_HAS_MEM_OUTPUT_REGS_A     :  0 
+--    C_HAS_MEM_OUTPUT_REGS_B     :  0 
+--    C_HAS_MUX_OUTPUT_REGS_A     :  0 
+--    C_HAS_MUX_OUTPUT_REGS_B     :  0 
+--    C_HAS_SOFTECC_INPUT_REGS_A  :  0 
+--    C_HAS_SOFTECC_OUTPUT_REGS_B :  0 
+--    C_MUX_PIPELINE_STAGES       :  0 
+--    C_USE_ECC                   :  0 
+--    C_USE_SOFTECC               :  0 
+--    C_HAS_INJECTERR             :  0 
+--    C_SIM_COLLISION_CHECK       :  ALL 
+--    C_COMMON_CLK                :  0 
+--    C_DISABLE_WARN_BHV_COLL     :  0 
+--    C_DISABLE_WARN_BHV_RANGE    :  0 
+
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY UNISIM;
+USE UNISIM.VCOMPONENTS.ALL;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+ENTITY EU4Kx32_prod IS
+  PORT (
+    --Port A
+    CLKA       : IN STD_LOGIC;
+    RSTA       : IN STD_LOGIC;  --opt port
+    ENA        : IN STD_LOGIC;  --optional port
+    REGCEA     : IN STD_LOGIC;  --optional port
+    WEA        : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ADDRA      : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+    DINA       : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    DOUTA      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+    --Port B
+    CLKB       : IN STD_LOGIC;
+    RSTB       : IN STD_LOGIC;  --opt port
+    ENB        : IN STD_LOGIC;  --optional port
+    REGCEB     : IN STD_LOGIC;  --optional port
+    WEB        : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ADDRB      : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+    DINB       : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    DOUTB      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+    --ECC
+    INJECTSBITERR  : IN STD_LOGIC; --optional port
+    INJECTDBITERR  : IN STD_LOGIC; --optional port
+    SBITERR        : OUT STD_LOGIC; --optional port
+    DBITERR        : OUT STD_LOGIC; --optional port
+    RDADDRECC      : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --optional port
+ -- AXI BMG Input and Output Port Declarations
+
+    -- AXI Global Signals
+    S_ACLK                         : IN  STD_LOGIC;
+    S_AXI_AWID                     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+    S_AXI_AWADDR                   : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXI_AWLEN                    : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    S_AXI_AWSIZE                   : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
+    S_AXI_AWBURST                  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_AWVALID                  : IN  STD_LOGIC;
+    S_AXI_AWREADY                  : OUT STD_LOGIC;
+    S_AXI_WDATA                    : IN  STD_LOGIC_VECTOR(31  DOWNTO 0);
+    S_AXI_WSTRB                    : IN  STD_LOGIC_VECTOR(0  DOWNTO 0);
+    S_AXI_WLAST                    : IN  STD_LOGIC;
+    S_AXI_WVALID                   : IN  STD_LOGIC;
+    S_AXI_WREADY                   : OUT STD_LOGIC;
+    S_AXI_BID                      : OUT STD_LOGIC_VECTOR(3  DOWNTO 0):= (OTHERS => '0');
+    S_AXI_BRESP                    : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_BVALID                   : OUT STD_LOGIC;
+    S_AXI_BREADY                   : IN  STD_LOGIC;
+
+    -- AXI Full/Lite Slave Read (Write side)
+    S_AXI_ARID                     : IN  STD_LOGIC_VECTOR(3  DOWNTO 0);
+    S_AXI_ARADDR                   : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXI_ARLEN                    : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    S_AXI_ARSIZE                   : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
+    S_AXI_ARBURST                  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_ARVALID                  : IN  STD_LOGIC;
+    S_AXI_ARREADY                  : OUT STD_LOGIC;
+    S_AXI_RID                      : OUT STD_LOGIC_VECTOR(3  DOWNTO 0):= (OTHERS => '0');
+    S_AXI_RDATA                    : OUT STD_LOGIC_VECTOR(31  DOWNTO 0);
+    S_AXI_RRESP                    : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_RLAST                    : OUT STD_LOGIC;
+    S_AXI_RVALID                   : OUT STD_LOGIC;
+    S_AXI_RREADY                   : IN  STD_LOGIC;
+
+    -- AXI Full/Lite Sideband Signals
+    S_AXI_INJECTSBITERR            : IN  STD_LOGIC;
+    S_AXI_INJECTDBITERR            : IN  STD_LOGIC;
+    S_AXI_SBITERR                  : OUT STD_LOGIC;
+    S_AXI_DBITERR                  : OUT STD_LOGIC;
+    S_AXI_RDADDRECC                : OUT STD_LOGIC_VECTOR(11  DOWNTO 0);
+    S_ARESETN                      : IN  STD_LOGIC
+
+
+  );
+
+END EU4Kx32_prod;
+
+
+ARCHITECTURE xilinx OF EU4Kx32_prod IS
+
+  COMPONENT EU4Kx32_exdes IS
+  PORT (
+      --Port A
+    ADDRA          : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+  
+    DOUTA          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+    CLKA       : IN STD_LOGIC
+
+
+
+
+  );
+  END COMPONENT;
+
+BEGIN
+
+  bmg0 : EU4Kx32_exdes
+    PORT MAP (
+      --Port A
+      ADDRA      => ADDRA,
+  
+      DOUTA      => DOUTA,
+
+      CLKA       => CLKA
+
+
+
+      );
+END xilinx;
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/implement.bat b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/implement.bat
new file mode 100644
index 0000000..b670304
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/implement.bat
@@ -0,0 +1,48 @@
+
+ 
+ 
+ 
+
+
+
+
+rem Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+rem Synthesize the VHDL Wrapper Files
+
+
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+copy EU4Kx32_exdes.ngc .\results\
+
+
+rem Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+copy ..\..\EU4Kx32.ngc results\
+
+
+rem  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\EU4Kx32_exdes.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -p xc6slx9-tqg144-2 EU4Kx32_exdes
+
+echo 'Running map'
+map EU4Kx32_exdes -o mapped.ncd  -pr i
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level Verilog model'
+netgen -ofmt verilog -sim -tm EU4Kx32_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/implement.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/implement.sh
new file mode 100644
index 0000000..29451fd
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/implement.sh
@@ -0,0 +1,48 @@
+
+ 
+ 
+ 
+
+
+
+
+#!/bin/sh
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+#Synthesize the Wrapper Files
+
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+cp EU4Kx32_exdes.ngc ./results/
+
+
+# Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+cp ../../EU4Kx32.ngc results/
+
+#  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/EU4Kx32_exdes.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -p xc6slx9-tqg144-2 EU4Kx32_exdes
+
+echo 'Running map'
+map EU4Kx32_exdes -o mapped.ncd -pr i
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level Verilog model'
+netgen -ofmt verilog -sim -tm EU4Kx32_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/planAhead_ise.bat b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/planAhead_ise.bat
new file mode 100644
index 0000000..332c312
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/planAhead_ise.bat
@@ -0,0 +1,55 @@
+#!/bin/sh
+rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+rem 
+rem This file contains confidential and proprietary information
+rem of Xilinx, Inc. and is protected under U.S. and
+rem international copyright and other intellectual property
+rem laws.
+rem 
+rem DISCLAIMER
+rem This disclaimer is not a license and does not grant any
+rem rights to the materials distributed herewith. Except as
+rem otherwise provided in a valid license issued to you by
+rem Xilinx, and to the maximum extent permitted by applicable
+rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+rem (2) Xilinx shall not be liable (whether in contract or tort,
+rem including negligence, or under any other theory of
+rem liability) for any loss or damage of any kind or nature
+rem related to, arising under or in connection with these
+rem materials, including for any direct, or any indirect,
+rem special, incidental, or consequential loss or damage
+rem (including loss of data, profits, goodwill, or any type of
+rem loss or damage suffered as a result of any action brought
+rem by a third party) even if such damage or loss was
+rem reasonably foreseeable or Xilinx had been advised of the
+rem possibility of the same.
+rem 
+rem CRITICAL APPLICATIONS
+rem Xilinx products are not designed or intended to be fail-
+rem safe, or for use in any application requiring fail-safe
+rem performance, such as life-support or safety devices or
+rem systems, Class III medical devices, nuclear facilities,
+rem applications related to the deployment of airbags, or any
+rem other applications that could lead to death, personal
+rem injury, or severe property or environmental damage
+rem (individually and collectively, "Critical
+rem Applications"). Customer assumes the sole risk and
+rem liability of any use of Xilinx products in Critical
+rem Applications, subject only to applicable laws and
+rem regulations governing limitations on product liability.
+rem 
+rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+rem PART OF THIS FILE AT ALL TIMES.
+
+rem -----------------------------------------------------------------------------
+rem  Script to synthesize and implement the Coregen FIFO Generator
+rem -----------------------------------------------------------------------------
+rmdir /S /Q results
+mkdir results
+cd results
+copy ..\..\..\EU4Kx32.ngc .
+planAhead -mode batch -source ..\planAhead_ise.tcl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/planAhead_ise.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/planAhead_ise.sh
new file mode 100644
index 0000000..9d992ce
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/planAhead_ise.sh
@@ -0,0 +1,55 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+#-----------------------------------------------------------------------------
+#  Script to synthesize and implement the Coregen FIFO Generator
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+cp ../../../EU4Kx32.ngc .
+planAhead -mode batch -source ../planAhead_ise.tcl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/planAhead_ise.tcl b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/planAhead_ise.tcl
new file mode 100644
index 0000000..291a264
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/planAhead_ise.tcl
@@ -0,0 +1,67 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+set device xc6slx9tqg144-2
+set projName EU4Kx32
+set design EU4Kx32
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module EU4Kx32_exdes
+add_files -norecurse {../../example_design/EU4Kx32_exdes.vhd}
+add_files -norecurse {./EU4Kx32.ngc}
+import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/EU4Kx32_exdes.xdc}
+set_property top EU4Kx32_exdes [get_property srcset [current_run]]
+synth_design
+opt_design 
+place_design 
+route_design 
+write_sdf -rename_top_module EU4Kx32_exdes -file routed.sdf 
+write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module EU4Kx32_exdes routed.v
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file report.drc
+write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/xst.prj b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/xst.prj
new file mode 100644
index 0000000..2c02a6f
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/xst.prj
@@ -0,0 +1 @@
+work ../example_design/EU4Kx32_exdes.vhd
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/xst.scr b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/xst.scr
new file mode 100644
index 0000000..e765e47
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/implement/xst.scr
@@ -0,0 +1,13 @@
+run
+-ifmt VHDL
+-ent EU4Kx32_exdes
+-p xc6slx9-tqg144-2
+-ifn xst.prj
+-write_timing_constraints No
+-iobuf YES
+-max_fanout 100
+-ofn EU4Kx32_exdes 
+-ofmt NGC
+-bus_delimiter ()
+-hierarchy_separator /
+-case Maintain
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/EU4Kx32_synth.vhd b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/EU4Kx32_synth.vhd
new file mode 100644
index 0000000..3ba4ef9
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/EU4Kx32_synth.vhd
@@ -0,0 +1,255 @@
+ 
+ 
+ 
+
+
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: EU4Kx32_synth.vhd
+--
+-- Description:
+--  Synthesizable Testbench
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+LIBRARY STD;
+USE STD.TEXTIO.ALL;
+
+--LIBRARY unisim;
+--USE unisim.vcomponents.ALL;
+
+LIBRARY work;
+USE work.ALL;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY EU4Kx32_synth IS
+GENERIC ( 
+   C_ROM_SYNTH : INTEGER := 1
+   );
+PORT(
+	CLK_IN     : IN  STD_LOGIC;
+    RESET_IN   : IN  STD_LOGIC;
+    STATUS     : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0')   --ERROR STATUS OUT OF FPGA
+    );
+END ENTITY;
+
+ARCHITECTURE EU4Kx32_synth_ARCH OF EU4Kx32_synth IS
+
+
+COMPONENT EU4Kx32_exdes 
+  PORT (
+      --Inputs - Port A
+    ADDRA          : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+    DOUTA          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    CLKA       : IN STD_LOGIC
+
+
+  );
+
+END COMPONENT;
+
+
+  SIGNAL CLKA: STD_LOGIC := '0';
+  SIGNAL RSTA: STD_LOGIC := '0';
+  SIGNAL ADDRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL ADDRA_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL CHECKER_EN : STD_LOGIC:='0';
+  SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
+  SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
+  SIGNAL clk_in_i: STD_LOGIC;
+ 
+  SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
+  SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
+  SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
+
+  SIGNAL ITER_R0 : STD_LOGIC := '0';
+  SIGNAL ITER_R1 : STD_LOGIC := '0';
+  SIGNAL ITER_R2 : STD_LOGIC := '0';
+
+  SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+
+  BEGIN
+
+--  clk_buf: bufg
+--    PORT map(
+--      i => CLK_IN,
+--      o => clk_in_i
+--    );
+   clk_in_i <= CLK_IN;
+   CLKA <= clk_in_i;
+
+   RSTA <= RESET_SYNC_R3 AFTER 50 ns;
+
+
+   PROCESS(clk_in_i)
+   BEGIN
+      IF(RISING_EDGE(clk_in_i)) THEN
+		 RESET_SYNC_R1 <= RESET_IN;
+		 RESET_SYNC_R2 <= RESET_SYNC_R1;
+		 RESET_SYNC_R3 <= RESET_SYNC_R2;
+	  END IF;
+   END PROCESS;
+
+
+PROCESS(CLKA)
+BEGIN
+  IF(RISING_EDGE(CLKA)) THEN
+    IF(RESET_SYNC_R3='1') THEN
+        ISSUE_FLAG_STATUS<= (OTHERS => '0'); 
+	  ELSE
+        ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
+   END IF;
+  END IF;
+END PROCESS;
+
+STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
+
+
+
+
+
+ BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
+    GENERIC MAP(  C_ROM_SYNTH => C_ROM_SYNTH
+              )
+
+     PORT MAP(
+                CLK => clk_in_i,
+            	RST => RSTA,
+                ADDRA  => ADDRA,
+				DATA_IN => DOUTA,
+				STATUS => ISSUE_FLAG(0)
+             );
+
+      PROCESS(CLKA)
+      BEGIN
+        IF(RISING_EDGE(CLKA)) THEN
+		  IF(RESET_SYNC_R3='1') THEN
+			STATUS(8) <= '0';
+			iter_r2 <= '0';
+			iter_r1 <= '0';
+			iter_r0 <= '0';
+		  ELSE
+			STATUS(8) <= iter_r2;
+			iter_r2 <= iter_r1;
+			iter_r1 <= iter_r0;
+			iter_r0 <= STIMULUS_FLOW(8);
+	      END IF;
+	    END IF;
+      END PROCESS;
+
+      PROCESS(CLKA)
+      BEGIN
+        IF(RISING_EDGE(CLKA)) THEN
+		  IF(RESET_SYNC_R3='1') THEN
+		      STIMULUS_FLOW <= (OTHERS => '0'); 
+           ELSIF(ADDRA(0)='1') THEN
+		      STIMULUS_FLOW <= STIMULUS_FLOW+1;
+         END IF;
+	    END IF;
+      END PROCESS;
+
+
+      PROCESS(CLKA)
+      BEGIN
+        IF(RISING_EDGE(CLKA)) THEN
+		  IF(RESET_SYNC_R3='1') THEN
+          
+
+           ELSE
+
+         END IF;
+	    END IF;
+      END PROCESS;
+
+
+      PROCESS(CLKA)
+      BEGIN
+        IF(RISING_EDGE(CLKA)) THEN
+		  IF(RESET_SYNC_R3='1') THEN
+            ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
+          ELSE
+            ADDRA_R <= ADDRA AFTER 50 ns;
+          END IF;
+	    END IF;
+      END PROCESS;
+
+
+    BMG_PORT: EU4Kx32_exdes PORT MAP ( 
+      --Port A
+      ADDRA      => ADDRA_R,
+      DOUTA      => DOUTA,
+      CLKA       => CLKA
+
+    );
+END ARCHITECTURE;
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/EU4Kx32_tb.vhd b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/EU4Kx32_tb.vhd
new file mode 100644
index 0000000..6a8b67f
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/EU4Kx32_tb.vhd
@@ -0,0 +1,135 @@
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+-- Filename: EU4Kx32_tb.vhd
+-- Description:
+--  Testbench Top
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.ALL;
+
+ENTITY EU4Kx32_tb IS
+END ENTITY;
+
+
+ARCHITECTURE EU4Kx32_tb_ARCH OF EU4Kx32_tb IS
+ SIGNAL  STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
+ SIGNAL  CLK :  STD_LOGIC := '1';
+ SIGNAL  RESET : STD_LOGIC;
+ 
+ BEGIN
+
+  
+ CLK_GEN: PROCESS BEGIN
+     CLK <= NOT CLK;
+     WAIT FOR 100 NS;
+     CLK <= NOT CLK; 
+     WAIT FOR 100 NS;
+  END PROCESS;
+  
+  RST_GEN: PROCESS BEGIN
+    RESET <= '1';
+    WAIT FOR 1000 NS;
+    RESET <= '0';
+    WAIT;
+  END PROCESS;
+
+  
+--STOP_SIM: PROCESS BEGIN
+-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
+--   ASSERT FALSE
+--     REPORT "END SIMULATION TIME REACHED"
+--     SEVERITY FAILURE;
+--END PROCESS;
+--
+PROCESS BEGIN
+  WAIT UNTIL STATUS(8)='1';
+  IF( STATUS(7 downto 0)/="0") THEN
+    ASSERT false
+     REPORT "Test Completed Successfully"
+	 SEVERITY NOTE;
+     REPORT "Simulation Failed"
+	 SEVERITY FAILURE;
+  ELSE
+   ASSERT false
+     REPORT "TEST PASS"
+     SEVERITY NOTE;
+     REPORT "Test Completed Successfully"
+	 SEVERITY FAILURE;
+  END IF;
+  
+END PROCESS;	 
+  
+  EU4Kx32_synth_inst:ENTITY work.EU4Kx32_synth
+  GENERIC MAP (C_ROM_SYNTH => 0)
+  PORT MAP(
+           CLK_IN   => CLK,
+     	   RESET_IN => RESET,
+           STATUS   => STATUS
+	  );
+
+END ARCHITECTURE;
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/addr_gen.vhd b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/addr_gen.vhd
new file mode 100644
index 0000000..62706ca
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/addr_gen.vhd
@@ -0,0 +1,117 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Address Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: addr_gen.vhd
+--
+-- Description:
+--   Address Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.ALL;
+
+ENTITY ADDR_GEN IS
+  GENERIC ( C_MAX_DEPTH : INTEGER :=  1024 ;
+            RST_VALUE  : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
+            RST_INC  : INTEGER := 0);
+  PORT (
+        CLK         : IN STD_LOGIC;
+        RST         : IN STD_LOGIC;
+        EN          : IN STD_LOGIC;
+        LOAD        :IN STD_LOGIC;
+        LOAD_VALUE  : IN STD_LOGIC_VECTOR (31 DOWNTO 0)  := (OTHERS => '0');
+        ADDR_OUT    : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)   --OUTPUT VECTOR           
+  );
+END ADDR_GEN;
+
+ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
+   SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
+BEGIN
+   ADDR_OUT <= ADDR_TEMP;
+   PROCESS(CLK)
+   BEGIN
+      IF(RISING_EDGE(CLK)) THEN
+         IF(RST='1') THEN
+    	    ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); 
+         ELSE
+            IF(EN='1') THEN
+               IF(LOAD='1') THEN
+	              ADDR_TEMP <=LOAD_VALUE;
+	           ELSE
+	              IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
+         	         ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
+	              ELSE
+	                 ADDR_TEMP <= ADDR_TEMP + '1';
+	              END IF;
+	           END IF;
+	        END IF;
+         END IF;
+      END IF;
+   END PROCESS;
+END ARCHITECTURE;
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/bmg_stim_gen.vhd b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/bmg_stim_gen.vhd
new file mode 100644
index 0000000..4276410
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/bmg_stim_gen.vhd
@@ -0,0 +1,426 @@
+ 
+ 
+    --------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_stim_gen.vhd
+--
+-- Description:
+--  Stimulus Generation For SROM
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+ LIBRARY work;
+USE work.ALL;
+USE work.BMG_TB_PKG.ALL;
+
+
+ENTITY REGISTER_LOGIC_SROM IS
+  PORT(
+    Q   : OUT STD_LOGIC;
+    CLK   : IN STD_LOGIC;
+    RST : IN STD_LOGIC;
+    D   : IN STD_LOGIC
+    );
+END REGISTER_LOGIC_SROM;
+
+ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
+   SIGNAL Q_O : STD_LOGIC :='0';
+BEGIN
+  Q <= Q_O;
+FF_BEH: PROCESS(CLK)
+BEGIN
+   IF(RISING_EDGE(CLK)) THEN
+      IF(RST /= '0' ) THEN
+	Q_O <= '0';
+     ELSE
+        Q_O <= D;
+      END IF;
+    END IF;
+  END PROCESS;
+END REGISTER_ARCH;
+
+LIBRARY STD;
+USE STD.TEXTIO.ALL;
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+--USE IEEE.NUMERIC_STD.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+ LIBRARY work;
+USE work.ALL;
+USE work.BMG_TB_PKG.ALL;
+
+
+ENTITY BMG_STIM_GEN IS
+      GENERIC ( C_ROM_SYNTH : INTEGER := 0
+      );
+      PORT (
+            CLK : IN STD_LOGIC;
+            RST : IN STD_LOGIC;
+            ADDRA: OUT  STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0'); 
+            DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0);   --OUTPUT VECTOR         
+            STATUS : OUT STD_LOGIC:= '0'
+    	  );
+END BMG_STIM_GEN;
+
+
+ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
+
+    FUNCTION hex_to_std_logic_vector(
+    hex_str       : STRING;
+    return_width  : INTEGER)
+  RETURN STD_LOGIC_VECTOR IS
+    VARIABLE tmp        : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
+                                           DOWNTO 0);
+
+  BEGIN
+    tmp := (OTHERS => '0');
+    FOR i IN 1 TO hex_str'LENGTH LOOP
+      CASE hex_str((hex_str'LENGTH+1)-i) IS
+        WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
+        WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
+        WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
+        WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
+        WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
+        WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
+        WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
+        WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
+        WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
+        WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
+        WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
+        WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
+        WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
+        WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
+        WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
+        WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
+        WHEN OTHERS  =>  tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
+      END CASE;
+    END LOOP;
+    RETURN tmp(return_width-1 DOWNTO 0);
+  END hex_to_std_logic_vector;
+
+CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
+SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+SIGNAL DO_READ : STD_LOGIC := '0';
+SIGNAL CHECK_DATA : STD_LOGIC := '0';
+SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
+SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
+SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
+CONSTANT DEFAULT_DATA  : STD_LOGIC_VECTOR(31 DOWNTO 0):= hex_to_std_logic_vector("0",32);
+
+BEGIN
+
+
+SYNTH_COE:  IF(C_ROM_SYNTH =0 ) GENERATE
+
+type mem_type is array (4095 downto 0) of std_logic_vector(31 downto 0);
+
+  FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
+    VARIABLE temp_return : STD_LOGIC;
+  BEGIN
+    IF (input = '0') THEN
+      temp_return := '0';
+    ELSE
+      temp_return := '1';
+    END IF;
+    RETURN temp_return;
+  END bit_to_sl;
+
+     function char_to_std_logic (
+      char : in character)
+      return std_logic is
+
+      variable data : std_logic;
+
+   begin
+      if char = '0' then
+         data := '0';
+
+      elsif char = '1' then
+         data := '1';
+
+      elsif char = 'X' then
+         data := 'X';
+
+      else
+         assert false
+            report "character which is not '0', '1' or 'X'."
+            severity warning;
+
+         data := 'U';
+      end if;
+
+      return data;
+
+   end char_to_std_logic;
+
+impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
+                       C_LOAD_INIT_FILE : INTEGER ;
+					   C_INIT_FILE_NAME : STRING ;
+                       DEFAULT_DATA   :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+                       width : INTEGER;
+                       depth         : INTEGER)
+  RETURN mem_type IS
+  VARIABLE init_return   : mem_type := (OTHERS => (OTHERS => '0'));
+  FILE     init_file     : TEXT;
+  VARIABLE mem_vector    : BIT_VECTOR(width-1 DOWNTO 0);
+  VARIABLE bitline     : LINE;
+  variable bitsgood    : boolean := true;
+  variable bitchar     : character;
+  VARIABLE i             : INTEGER;
+  VARIABLE j             : INTEGER;
+  BEGIN
+
+    --Display output message indicating that the behavioral model is being
+    --initialized
+    ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
+
+    -- Setup the default data
+    -- Default data is with respect to write_port_A and may be wider
+    -- or narrower than init_return width.  The following loops map
+    -- default data into the memory
+    IF (C_USE_DEFAULT_DATA=1) THEN
+      FOR i IN 0 TO depth-1 LOOP
+          init_return(i) := DEFAULT_DATA;
+        END LOOP;
+    END IF;
+
+    -- Read in the .mif file
+    -- The init data is formatted with respect to write port A dimensions.
+    -- The init_return vector is formatted with respect to minimum width and
+    -- maximum depth; the following loops map the .mif file into the memory
+    IF (C_LOAD_INIT_FILE=1) THEN
+      file_open(init_file, C_INIT_FILE_NAME, read_mode);
+      i := 0;
+      WHILE (i < depth AND NOT endfile(init_file)) LOOP
+        mem_vector := (OTHERS => '0');
+        readline(init_file, bitline);
+--        read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
+
+        FOR j IN 0 TO width-1 LOOP
+		  read(bitline,bitchar,bitsgood);
+          init_return(i)(width-1-j) := char_to_std_logic(bitchar);
+        END LOOP;
+        i := i + 1;
+    END LOOP;
+      file_close(init_file);
+    END IF;
+    RETURN init_return;
+
+  END FUNCTION;
+
+
+  --***************************************************************
+  -- convert bit to STD_LOGIC
+  --***************************************************************
+
+constant c_init : mem_type := init_memory(0,
+                                          1,
+										  "EU4Kx32.mif",
+                                           DEFAULT_DATA,
+                                          32,
+                                          4096);
+
+
+constant rom : mem_type := c_init;
+BEGIN
+
+ EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
+
+  CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
+    GENERIC MAP( C_MAX_DEPTH =>4096 )
+
+     PORT MAP(
+        CLK => CLK,
+     	RST => RST,
+   	    EN  => CHECK_DATA_2R,
+        LOAD => '0',
+     	LOAD_VALUE => ZERO,
+    	ADDR_OUT => CHECK_READ_ADDR
+       );
+ 
+
+  PROCESS(CLK)
+   BEGIN
+     IF(RISING_EDGE(CLK)) THEN
+       IF(CHECK_DATA_2R ='1') THEN
+    	 IF(EXPECTED_DATA = DATA_IN) THEN
+	        STATUS<='0';
+    	 ELSE
+	        STATUS <= '1';
+     	 END IF;
+       END IF;
+	 END IF;
+  END PROCESS;
+END GENERATE; 
+-- Simulatable ROM 
+
+--Synthesizable ROM
+SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
+  PROCESS(CLK)
+  BEGIN
+     IF(RISING_EDGE(CLK)) THEN
+	   IF(CHECK_DATA_2R='1') THEN
+		 IF(DATA_IN=DEFAULT_DATA) THEN
+		   STATUS <= '0';
+	     ELSE
+		   STATUS <= '1';
+		 END IF;
+	   END IF;
+	 END IF;
+  END PROCESS;
+
+END GENERATE;
+
+
+    READ_ADDR_INT(11 DOWNTO 0) <= READ_ADDR(11 DOWNTO 0);
+    ADDRA <= READ_ADDR_INT ;
+
+   CHECK_DATA <= DO_READ;
+
+
+
+
+  RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
+    GENERIC MAP( C_MAX_DEPTH => 4096 )
+
+     PORT MAP(
+        CLK => CLK,
+     	RST => RST,
+   	    EN  => DO_READ,
+        LOAD => '0',
+     	LOAD_VALUE => ZERO,
+    	ADDR_OUT => READ_ADDR
+       );
+
+RD_PROCESS: PROCESS (CLK)
+       BEGIN
+     IF (RISING_EDGE(CLK)) THEN
+          IF(RST='1') THEN
+    	     DO_READ <= '0';
+		  ELSE
+             DO_READ <= '1';
+	    END IF;
+	 END IF;
+END PROCESS;
+
+  BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
+  BEGIN
+    DFF_RIGHT: IF I=0 GENERATE
+     BEGIN
+     SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
+        PORT MAP(
+                 Q  => DO_READ_REG(0),
+                 CLK =>CLK,
+                 RST=>RST,
+                 D  =>DO_READ
+                );
+     END GENERATE DFF_RIGHT;
+    DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
+     BEGIN
+       SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
+         PORT MAP(
+                 Q  => DO_READ_REG(I),
+                 CLK =>CLK,
+                 RST=>RST,
+                 D  =>DO_READ_REG(I-1)
+                );
+      END GENERATE DFF_OTHERS;
+   END GENERATE BEGIN_SHIFT_REG;
+
+
+CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
+        PORT MAP(
+                 Q  => CHECK_DATA_2R,
+                 CLK =>CLK,
+                 RST=>RST,
+                 D  =>CHECK_DATA_R
+                );
+
+CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
+        PORT MAP(
+                 Q  => CHECK_DATA_R,
+                 CLK =>CLK,
+                 RST=>RST,
+                 D  =>CHECK_DATA
+                );
+
+
+
+
+
+
+END ARCHITECTURE;
+
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/bmg_tb_pkg.vhd b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/bmg_tb_pkg.vhd
new file mode 100644
index 0000000..4928909
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/bmg_tb_pkg.vhd
@@ -0,0 +1,200 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Testbench Package 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_tb_pkg.vhd
+--
+-- Description:
+--   BMG Testbench Package files
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+PACKAGE BMG_TB_PKG IS
+
+ FUNCTION DIVROUNDUP (
+    DATA_VALUE : INTEGER;
+    DIVISOR : INTEGER)
+ RETURN INTEGER;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+    CONDITION : BOOLEAN;
+    TRUE_CASE : STD_LOGIC_VECTOR;
+    FALSE_CASE : STD_LOGIC_VECTOR)
+  RETURN STD_LOGIC_VECTOR;
+ ------------------------ 
+ FUNCTION IF_THEN_ELSE (
+   CONDITION : BOOLEAN;
+   TRUE_CASE : STRING;
+   FALSE_CASE :STRING)
+ RETURN STRING;
+ ------------------------ 
+ FUNCTION IF_THEN_ELSE (
+   CONDITION : BOOLEAN;
+   TRUE_CASE : STD_LOGIC;
+   FALSE_CASE :STD_LOGIC)
+ RETURN STD_LOGIC;
+ ------------------------ 
+ FUNCTION IF_THEN_ELSE (
+   CONDITION : BOOLEAN;
+   TRUE_CASE : INTEGER;
+   FALSE_CASE : INTEGER)
+ RETURN INTEGER;
+ ------------------------ 
+ FUNCTION LOG2ROUNDUP (
+      DATA_VALUE : INTEGER)
+ RETURN INTEGER; 
+
+END BMG_TB_PKG;
+
+PACKAGE BODY BMG_TB_PKG IS
+
+ FUNCTION DIVROUNDUP (
+    DATA_VALUE : INTEGER;
+    DIVISOR : INTEGER)
+  RETURN INTEGER IS
+    VARIABLE DIV                   : INTEGER;
+  BEGIN
+    DIV   := DATA_VALUE/DIVISOR;
+    IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
+      DIV := DIV+1;
+    END IF;
+    RETURN DIV;
+  END DIVROUNDUP;
+  ---------------------------------
+    FUNCTION IF_THEN_ELSE (
+    CONDITION : BOOLEAN;
+    TRUE_CASE : STD_LOGIC_VECTOR;
+    FALSE_CASE : STD_LOGIC_VECTOR)
+    RETURN STD_LOGIC_VECTOR IS
+    BEGIN
+       IF NOT CONDITION THEN
+          RETURN FALSE_CASE;
+       ELSE
+          RETURN TRUE_CASE;
+      END IF;
+   END IF_THEN_ELSE;
+  ---------------------------------
+    FUNCTION IF_THEN_ELSE (
+    CONDITION : BOOLEAN;
+    TRUE_CASE : STD_LOGIC;
+    FALSE_CASE : STD_LOGIC)
+    RETURN STD_LOGIC IS
+    BEGIN
+       IF NOT CONDITION THEN
+          RETURN FALSE_CASE;
+       ELSE
+          RETURN TRUE_CASE;
+      END IF;
+   END IF_THEN_ELSE;
+  ---------------------------------
+  FUNCTION IF_THEN_ELSE (
+    CONDITION : BOOLEAN;
+    TRUE_CASE : INTEGER;
+    FALSE_CASE : INTEGER)
+  RETURN INTEGER IS
+    VARIABLE RETVAL : INTEGER := 0;
+  BEGIN
+    IF CONDITION=FALSE THEN
+      RETVAL:=FALSE_CASE;
+    ELSE
+      RETVAL:=TRUE_CASE;
+    END IF;
+    RETURN RETVAL;
+  END IF_THEN_ELSE;
+  ---------------------------------
+  FUNCTION IF_THEN_ELSE (
+    CONDITION : BOOLEAN;
+    TRUE_CASE : STRING;
+    FALSE_CASE : STRING)
+  RETURN STRING IS
+    BEGIN
+     IF NOT CONDITION THEN
+        RETURN FALSE_CASE;
+     ELSE
+        RETURN TRUE_CASE;
+     END IF;
+ END IF_THEN_ELSE;
+  ------------------------------- 
+  FUNCTION LOG2ROUNDUP (
+      DATA_VALUE : INTEGER)
+    RETURN INTEGER IS
+      VARIABLE WIDTH       : INTEGER := 0;
+      VARIABLE CNT         : INTEGER := 1;
+    BEGIN
+      IF (DATA_VALUE <= 1) THEN
+        WIDTH   := 1;
+      ELSE
+        WHILE (CNT < DATA_VALUE) LOOP
+          WIDTH := WIDTH + 1;
+          CNT   := CNT *2;
+        END LOOP;
+      END IF;
+      RETURN WIDTH;
+    END LOG2ROUNDUP;
+
+END BMG_TB_PKG;
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simcmds.tcl b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simcmds.tcl
new file mode 100644
index 0000000..be965c8
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simcmds.tcl
@@ -0,0 +1,60 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+ 
+ 
+ 
+
+
+
+
+wcfg new
+isim set radix hex
+wave add /EU4Kx32_tb/status
+      wave add  /EU4Kx32_tb/EU4Kx32_synth_inst/BMG_PORT/CLKA
+      wave add  /EU4Kx32_tb/EU4Kx32_synth_inst/BMG_PORT/ADDRA
+      wave add  /EU4Kx32_tb/EU4Kx32_synth_inst/BMG_PORT/DOUTA
+run all
+quit
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simulate_isim.bat b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simulate_isim.bat
new file mode 100644
index 0000000..954fe2d
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simulate_isim.bat
@@ -0,0 +1,67 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+:: 
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+:: 
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+:: 
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+:: 
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+::--------------------------------------------------------------------------------
+
+cp ..\..\..\EU4Kx32.mif .
+
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogcomp -work work ..\..\..\EU4Kx32.v 
+vhpcomp -work work ..\..\example_design\EU4Kx32_exdes.vhd
+
+echo "Compiling Test Bench Files"
+
+vhpcomp -work work    ..\bmg_tb_pkg.vhd
+vhpcomp -work work    ..\addr_gen.vhd
+vhpcomp -work work    ..\bmg_stim_gen.vhd
+vhpcomp -work work    ..\EU4Kx32_synth.vhd 
+vhpcomp -work work    ..\EU4Kx32_tb.vhd
+
+
+vlogcomp -work work $XILINX\verilog\src\glbl.v
+fuse work.EU4Kx32_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o EU4Kx32_tb.exe
+
+.\EU4Kx32_tb.exe -gui -tclbatch simcmds.tcl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simulate_mti.bat b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simulate_mti.bat
new file mode 100644
index 0000000..5964f52
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simulate_mti.bat
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simulate_mti.do b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simulate_mti.do
new file mode 100644
index 0000000..9e601f9
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simulate_mti.do
@@ -0,0 +1,74 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+cp ../../../EU4Kx32.mif .
+ vlib work 
+vmap work work
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlog -work work ../../../EU4Kx32.v 
+vcom -work work ../../example_design/EU4Kx32_exdes.vhd
+
+echo "Compiling Test Bench Files"
+
+vcom -work work    ../bmg_tb_pkg.vhd
+vcom -work work    ../addr_gen.vhd
+vcom -work work    ../bmg_stim_gen.vhd
+vcom -work work    ../EU4Kx32_synth.vhd 
+vcom -work work    ../EU4Kx32_tb.vhd
+
+
+vlog -work work $env(XILINX)/verilog/src/glbl.v
+vsim  -novopt -t ps -L XilinxCoreLib_ver -L unisims_ver glbl work.EU4Kx32_tb
+
+#Disabled waveform to save the disk space
+add log -r /*
+#Ignore integer warnings at time 0
+set StdArithNoWarnings 1
+run 0
+set StdArithNoWarnings 0
+
+run -all
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simulate_mti.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simulate_mti.sh
new file mode 100644
index 0000000..5964f52
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simulate_mti.sh
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simulate_ncsim.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simulate_ncsim.sh
new file mode 100644
index 0000000..fef6bb8
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simulate_ncsim.sh
@@ -0,0 +1,69 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+cp ../../../EU4Kx32.mif .
+
+
+mkdir work
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+ncvlog -work work ../../../EU4Kx32.v 
+ncvhdl -v93 -work work ../../example_design/EU4Kx32_exdes.vhd
+
+echo "Compiling Test Bench Files"
+
+ncvhdl -v93 -work work    ../bmg_tb_pkg.vhd
+ncvhdl -v93 -work work    ../addr_gen.vhd
+ncvhdl -v93 -work work    ../bmg_stim_gen.vhd
+ncvhdl -v93 -work work    ../EU4Kx32_synth.vhd 
+ncvhdl -v93 -work work    ../EU4Kx32_tb.vhd
+
+echo "Elaborating Design"
+ncvlog -work work $XILINX/verilog/src/glbl.v
+ncelab -access +rwc glbl work.EU4Kx32_tb
+
+echo "Simulating Design"
+ncsim -gui -input @"simvision -input wave_ncsim.sv" work.EU4Kx32_tb
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simulate_vcs.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simulate_vcs.sh
new file mode 100644
index 0000000..2a14348
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/simulate_vcs.sh
@@ -0,0 +1,68 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+#!/bin/sh
+cp ../../../EU4Kx32.mif .
+rm -rf simv* csrc DVEfiles AN.DB
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogan +v2k  ../../../EU4Kx32.v
+vhdlan  ../../example_design/EU4Kx32_exdes.vhd
+
+echo "Compiling Test Bench Files"
+vhdlan    ../bmg_tb_pkg.vhd
+vhdlan    ../addr_gen.vhd
+vhdlan    ../bmg_stim_gen.vhd
+vhdlan    ../EU4Kx32_synth.vhd 
+vhdlan    ../EU4Kx32_tb.vhd
+
+echo "Elaborating Design"
+vlogan +v2k $XILINX/verilog/src/glbl.v
+vcs +vcs+lic+wait -debug EU4Kx32_tb glbl
+
+echo "Simulating Design"
+./simv -ucli -i ucli_commands.key
+dve -session vcs_session.tcl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/ucli_commands.key b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/ucli_commands.key
new file mode 100644
index 0000000..a9767bd
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/ucli_commands.key
@@ -0,0 +1,4 @@
+dump -file bmg_vcs.vpd -type VPD
+dump -add EU4Kx32_tb
+run 
+quit
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/vcs_session.tcl b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/vcs_session.tcl
new file mode 100644
index 0000000..31390dc
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/vcs_session.tcl
@@ -0,0 +1,80 @@
+
+ 
+ 
+ 
+
+
+
+
+#--------------------------------------------------------------------------------
+#--
+#--  BMG core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: vcs_session.tcl
+#
+# Description:
+#   This is the VCS wave form file.
+#
+#--------------------------------------------------------------------------------
+if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {
+	gui_open_db -design V1 -file bmg_vcs.vpd -nosource
+}
+gui_set_precision 1ps
+gui_set_time_units 1ps
+
+gui_open_window Wave
+gui_sg_create EU4Kx32_Group
+gui_list_add_group -id Wave.1 {EU4Kx32_Group}
+
+      gui_sg_addsignal -group EU4Kx32_Group  /EU4Kx32_tb/status
+      gui_sg_addsignal -group EU4Kx32_Group  /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/CLKA
+      gui_sg_addsignal -group EU4Kx32_Group  /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/ADDRA
+      gui_sg_addsignal -group EU4Kx32_Group  /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/DOUTA
+
+gui_zoom -window Wave.1 -full
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/wave_mti.do b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/wave_mti.do
new file mode 100644
index 0000000..e8668d2
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/wave_mti.do
@@ -0,0 +1,33 @@
+
+ 
+ 
+ 
+
+
+
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+
+      add wave -noupdate /EU4Kx32_tb/status
+      add wave -noupdate /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/CLKA
+      add wave -noupdate /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/ADDRA
+      add wave -noupdate /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/DOUTA
+
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 197
+configure wave -valuecolwidth 106
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {9464063 ps}
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/wave_ncsim.sv b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/wave_ncsim.sv
new file mode 100644
index 0000000..10a90bd
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/functional/wave_ncsim.sv
@@ -0,0 +1,18 @@
+
+
+ 
+ 
+ 
+
+
+
+
+window new WaveWindow  -name  "Waves for BMG Example Design"
+waveform  using  "Waves for BMG Example Design"
+
+      waveform add -signals /EU4Kx32_tb/status
+      waveform add -signals /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/CLKA
+      waveform add -signals /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/ADDRA
+      waveform add -signals /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/DOUTA
+
+console submit -using simulator -wait no "run"
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/random.vhd b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/random.vhd
new file mode 100644
index 0000000..b0d417c
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/random.vhd
@@ -0,0 +1,112 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Random Number Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: random.vhd
+--
+-- Description:
+--   Random Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+
+
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+ENTITY RANDOM IS
+  GENERIC ( WIDTH : INTEGER :=  32;
+ 	        SEED  : INTEGER :=2 
+  );
+        
+  PORT (
+     CLK        : IN STD_LOGIC;
+     RST        : IN STD_LOGIC;
+     EN         : IN STD_LOGIC;
+     RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)   --OUTPUT VECTOR           
+  );
+END RANDOM;
+
+ARCHITECTURE BEHAVIORAL OF RANDOM IS
+BEGIN
+  PROCESS(CLK)
+    VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
+    VARIABLE TEMP      : STD_LOGIC := '0';
+  BEGIN
+    IF(RISING_EDGE(CLK)) THEN
+       IF(RST='1') THEN
+          RAND_TEMP  := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
+	   ELSE
+          IF(EN = '1') THEN
+             TEMP                        := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
+             RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
+             RAND_TEMP(0)                := TEMP;
+          END IF;
+       END IF;
+    END IF;
+    RANDOM_NUM <= RAND_TEMP;
+  END PROCESS;
+END ARCHITECTURE;
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simcmds.tcl b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simcmds.tcl
new file mode 100644
index 0000000..be965c8
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simcmds.tcl
@@ -0,0 +1,60 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+ 
+ 
+ 
+
+
+
+
+wcfg new
+isim set radix hex
+wave add /EU4Kx32_tb/status
+      wave add  /EU4Kx32_tb/EU4Kx32_synth_inst/BMG_PORT/CLKA
+      wave add  /EU4Kx32_tb/EU4Kx32_synth_inst/BMG_PORT/ADDRA
+      wave add  /EU4Kx32_tb/EU4Kx32_synth_inst/BMG_PORT/DOUTA
+run all
+quit
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simulate_isim.bat b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simulate_isim.bat
new file mode 100644
index 0000000..ab80687
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simulate_isim.bat
@@ -0,0 +1,63 @@
+:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+:: 
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+:: 
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+:: 
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+:: 
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+::--------------------------------------------------------------------------------
+
+cp ..\..\..\EU4Kx32.mif .
+
+
+vlogcomp -work work ..\..\implement\results\routed.v
+
+echo "Compiling Test Bench Files"
+
+vhpcomp -work work    ..\bmg_tb_pkg.vhd
+vhpcomp -work work    ..\addr_gen.vhd
+vhpcomp -work work    ..\bmg_stim_gen.vhd
+vhpcomp -work work    ..\EU4Kx32_synth.vhd 
+vhpcomp -work work    ..\EU4Kx32_tb.vhd
+
+    fuse -L simprims_ver work.EU4Kx32_tb work.glbl -o EU4Kx32_tb.exe
+
+.\EU4Kx32_tb.exe -sdftyp /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port=..\..\implement\results\routed.sdf -gui -tclbatch simcmds.tcl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simulate_mti.bat b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simulate_mti.bat
new file mode 100644
index 0000000..5964f52
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simulate_mti.bat
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simulate_mti.do b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simulate_mti.do
new file mode 100644
index 0000000..d7fc5db
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simulate_mti.do
@@ -0,0 +1,73 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+set work work
+#--------------------------------------------------------------------------------
+cp ../../../EU4Kx32.mif .
+
+vlib work
+vmap work work
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlog -work work ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+
+vcom -work work    ../bmg_tb_pkg.vhd
+vcom -work work    ../addr_gen.vhd
+vcom -work work    ../bmg_stim_gen.vhd
+vcom -work work    ../EU4Kx32_synth.vhd 
+vcom -work work    ../EU4Kx32_tb.vhd
+
+    vsim -novopt -t ps  -L simprims_ver +transport_int_delays -sdftyp /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port=../../implement/results/routed.sdf $work.EU4Kx32_tb $work.glbl -novopt
+
+#Disabled waveform to save the disk space
+add log -r /*
+#Ignore integer warnings at time 0
+set StdArithNoWarnings 1
+run 0
+set StdArithNoWarnings 0
+
+run -all
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simulate_mti.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simulate_mti.sh
new file mode 100644
index 0000000..5964f52
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simulate_mti.sh
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simulate_ncsim.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simulate_ncsim.sh
new file mode 100644
index 0000000..5443851
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simulate_ncsim.sh
@@ -0,0 +1,76 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+set work work
+#--------------------------------------------------------------------------------
+cp ../../../EU4Kx32.mif .
+mkdir work
+
+
+ncvlog -work work ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+
+ncvhdl -v93 -work work    ../bmg_tb_pkg.vhd
+ncvhdl -v93 -work work    ../addr_gen.vhd
+ncvhdl -v93 -work work    ../bmg_stim_gen.vhd
+ncvhdl -v93 -work work    ../EU4Kx32_synth.vhd 
+ncvhdl -v93 -work work    ../EU4Kx32_tb.vhd
+
+echo "Compiling SDF file"
+ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X
+
+echo "Generating SDF command file"
+echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd
+echo 'SCOPE = :EU4Kx32_synth_inst:BMG_PORT,' >> sdf.cmd
+echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd
+
+
+echo "Elaborating Design"
+ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd $work.EU4Kx32_tb
+
+echo "Simulating Design"
+ncsim -gui -input @"simvision -input wave_ncsim.sv" $work.EU4Kx32_tb
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simulate_vcs.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simulate_vcs.sh
new file mode 100644
index 0000000..025a7e4
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/simulate_vcs.sh
@@ -0,0 +1,68 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+#!/bin/sh
+cp ../../../EU4Kx32.mif .
+
+rm -rf simv* csrc DVEfiles AN.DB
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogan +v2k  ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+vhdlan    ../bmg_tb_pkg.vhd
+vhdlan    ../addr_gen.vhd
+vhdlan    ../bmg_stim_gen.vhd
+vhdlan    ../EU4Kx32_synth.vhd 
+vhdlan    ../EU4Kx32_tb.vhd
+
+
+echo "Elaborating Design"
+vcs +neg_tchk +vcs+lic+wait -debug EU4Kx32_tb glbl
+
+echo "Simulating Design"
+./simv -ucli -i ucli_commands.key
+dve -session vcs_session.tcl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/ucli_commands.key b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/ucli_commands.key
new file mode 100644
index 0000000..a9767bd
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/ucli_commands.key
@@ -0,0 +1,4 @@
+dump -file bmg_vcs.vpd -type VPD
+dump -add EU4Kx32_tb
+run 
+quit
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/vcs_session.tcl b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/vcs_session.tcl
new file mode 100644
index 0000000..e50fac1
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/vcs_session.tcl
@@ -0,0 +1,80 @@
+ 
+ 
+ 
+
+
+
+
+#--------------------------------------------------------------------------------
+#--
+#-- BMG Generator v8.4 Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: vcs_session.tcl
+#
+# Description:
+#   This is the VCS wave form file.
+#
+#--------------------------------------------------------------------------------
+
+if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {
+	gui_open_db -design V1 -file bmg_vcs.vpd -nosource
+}
+gui_set_precision 1ps
+gui_set_time_units 1ps
+
+gui_open_window Wave
+gui_sg_create EU4Kx32_Group
+gui_list_add_group -id Wave.1 {EU4Kx32_Group}
+
+      gui_sg_addsignal -group EU4Kx32_Group  /EU4Kx32_tb/status
+      gui_sg_addsignal -group EU4Kx32_Group  /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/CLKA
+      gui_sg_addsignal -group EU4Kx32_Group  /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/ADDRA
+      gui_sg_addsignal -group EU4Kx32_Group  /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/DOUTA
+
+gui_zoom -window Wave.1 -full
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/wave_mti.do b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/wave_mti.do
new file mode 100644
index 0000000..ffbb777
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/wave_mti.do
@@ -0,0 +1,33 @@
+
+ 
+ 
+ 
+
+
+
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+
+
+      add wave -noupdate /EU4Kx32_tb/status
+      add wave -noupdate /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/CLKA
+      add wave -noupdate /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/ADDRA
+      add wave -noupdate /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/DOUTA
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {9464063 ps}
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/wave_ncsim.sv b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/wave_ncsim.sv
new file mode 100644
index 0000000..ecd3cbe
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32/simulation/timing/wave_ncsim.sv
@@ -0,0 +1,17 @@
+
+ 
+ 
+ 
+
+
+
+
+window new WaveWindow  -name  "Waves for BMG Example Design"
+waveform  using  "Waves for BMG Example Design"
+
+
+      waveform add -signals /EU4Kx32_tb/status
+      waveform add -signals /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/CLKA
+      waveform add -signals /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/ADDRA
+      waveform add -signals /EU4Kx32_tb/EU4Kx32_synth_inst/bmg_port/DOUTA
+console submit -using simulator -wait no "run"
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32_flist.txt b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32_flist.txt
new file mode 100644
index 0000000..8bc492e
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32_flist.txt
@@ -0,0 +1,55 @@
+# Output products list for <EU4Kx32>
+EU4Kx32.asy
+EU4Kx32.gise
+EU4Kx32.mif
+EU4Kx32.ngc
+EU4Kx32.v
+EU4Kx32.veo
+EU4Kx32.xco
+EU4Kx32.xise
+EU4Kx32\blk_mem_gen_v7_3_readme.txt
+EU4Kx32\doc\blk_mem_gen_v7_3_vinfo.html
+EU4Kx32\doc\pg058-blk-mem-gen.pdf
+EU4Kx32\example_design\EU4Kx32_exdes.ucf
+EU4Kx32\example_design\EU4Kx32_exdes.vhd
+EU4Kx32\example_design\EU4Kx32_exdes.xdc
+EU4Kx32\example_design\EU4Kx32_prod.vhd
+EU4Kx32\implement\implement.bat
+EU4Kx32\implement\implement.sh
+EU4Kx32\implement\planAhead_ise.bat
+EU4Kx32\implement\planAhead_ise.sh
+EU4Kx32\implement\planAhead_ise.tcl
+EU4Kx32\implement\xst.prj
+EU4Kx32\implement\xst.scr
+EU4Kx32\simulation\EU4Kx32_synth.vhd
+EU4Kx32\simulation\EU4Kx32_tb.vhd
+EU4Kx32\simulation\addr_gen.vhd
+EU4Kx32\simulation\bmg_stim_gen.vhd
+EU4Kx32\simulation\bmg_tb_pkg.vhd
+EU4Kx32\simulation\functional\simcmds.tcl
+EU4Kx32\simulation\functional\simulate_isim.bat
+EU4Kx32\simulation\functional\simulate_mti.bat
+EU4Kx32\simulation\functional\simulate_mti.do
+EU4Kx32\simulation\functional\simulate_mti.sh
+EU4Kx32\simulation\functional\simulate_ncsim.sh
+EU4Kx32\simulation\functional\simulate_vcs.sh
+EU4Kx32\simulation\functional\ucli_commands.key
+EU4Kx32\simulation\functional\vcs_session.tcl
+EU4Kx32\simulation\functional\wave_mti.do
+EU4Kx32\simulation\functional\wave_ncsim.sv
+EU4Kx32\simulation\random.vhd
+EU4Kx32\simulation\timing\simcmds.tcl
+EU4Kx32\simulation\timing\simulate_isim.bat
+EU4Kx32\simulation\timing\simulate_mti.bat
+EU4Kx32\simulation\timing\simulate_mti.do
+EU4Kx32\simulation\timing\simulate_mti.sh
+EU4Kx32\simulation\timing\simulate_ncsim.sh
+EU4Kx32\simulation\timing\simulate_vcs.sh
+EU4Kx32\simulation\timing\ucli_commands.key
+EU4Kx32\simulation\timing\vcs_session.tcl
+EU4Kx32\simulation\timing\wave_mti.do
+EU4Kx32\simulation\timing\wave_ncsim.sv
+EU4Kx32_flist.txt
+EU4Kx32_xmdf.tcl
+_xmsgs\pn_parser.xmsgs
+summary.log
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32_xmdf.tcl b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32_xmdf.tcl
new file mode 100644
index 0000000..d18b7f7
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/EU4Kx32_xmdf.tcl
@@ -0,0 +1,243 @@
+# The package naming convention is <core_name>_xmdf
+package provide EU4Kx32_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::EU4Kx32_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::EU4Kx32_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name EU4Kx32
+}
+# ::EU4Kx32_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::EU4Kx32_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/blk_mem_gen_v7_3_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/doc/blk_mem_gen_v7_3_vinfo.html
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/doc/pg058-blk-mem-gen.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/example_design/EU4Kx32_exdes.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/example_design/EU4Kx32_exdes.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/example_design/EU4Kx32_exdes.xdc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/example_design/EU4Kx32_prod.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/implement/implement.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/implement/implement.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/implement/planAhead_ise.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/implement/planAhead_ise.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/implement/planAhead_ise.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/implement/xst.prj
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/implement/xst.scr
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/EU4Kx32_synth.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/EU4Kx32_tb.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/addr_gen.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/bmg_stim_gen.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/bmg_tb_pkg.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/functional/simcmds.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/functional/simulate_isim.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/functional/simulate_mti.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/functional/simulate_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/functional/simulate_mti.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/functional/simulate_ncsim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/functional/simulate_vcs.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/functional/ucli_commands.key
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/functional/vcs_session.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/functional/wave_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/functional/wave_ncsim.sv
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/random.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/timing/simcmds.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/timing/simulate_isim.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/timing/simulate_mti.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/timing/simulate_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/timing/simulate_mti.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/timing/simulate_ncsim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/timing/simulate_vcs.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/timing/ucli_commands.key
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/timing/vcs_session.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/timing/wave_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32/simulation/timing/wave_ncsim.sv
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32.mif
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path EU4Kx32_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path summary.log
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module EU4Kx32
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/_xmsgs/cg.xmsgs b/MCL86jr/FPGA/MCL86jr/ipcore_dir/_xmsgs/cg.xmsgs
new file mode 100644
index 0000000..d9add21
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/_xmsgs/cg.xmsgs
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="sim" num="172" delta="old" >Generating IP...
+</msg>
+
+<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;spartan6_pll&apos; already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+
+<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;spartan6_pll&apos; already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+
+<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Component clk_wiz_v3_6 does not have a valid model name for Verilog synthesis</arg>
+</msg>
+
+<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
+</msg>
+
+<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
+</msg>
+
+</messages>
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/_xmsgs/pn_parser.xmsgs b/MCL86jr/FPGA/MCL86jr/ipcore_dir/_xmsgs/pn_parser.xmsgs
new file mode 100644
index 0000000..b579295
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/_xmsgs/pn_parser.xmsgs
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated   -->
+<!--     by the Xilinx ISE software.  Any direct editing or        -->
+<!--     changes made to this file may result in unpredictable     -->
+<!--     behavior or data corruption.  It is strongly advised that -->
+<!--     users do not edit the contents of this file.              -->
+<!--                                                               -->
+<!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.    -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/spartan6_pll.v&quot; into library work</arg>
+</msg>
+
+</messages>
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/coregen.cgp b/MCL86jr/FPGA/MCL86jr/ipcore_dir/coregen.cgp
new file mode 100644
index 0000000..0b14935
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/coregen.cgp
@@ -0,0 +1,9 @@
+SET busformat = BusFormatAngleBracketNotRipped
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET package = tqg144
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/coregen.log b/MCL86jr/FPGA/MCL86jr/ipcore_dir/coregen.log
new file mode 100644
index 0000000..3c0d0bd
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/coregen.log
@@ -0,0 +1,49 @@
+INFO:sim:172 - Generating IP...
+Applying current project options...
+Finished applying current project options.
+WARNING:sim - A core named 'spartan6_pll' already exists in the project. Output
+   products for this core may be overwritten.
+Resolving generics for 'spartan6_pll'...
+WARNING:sim - A core named 'spartan6_pll' already exists in the project. Output
+   products for this core may be overwritten.
+Applying external generics to 'spartan6_pll'...
+Delivering associated files for 'spartan6_pll'...
+WARNING:sim - Component clk_wiz_v3_6 does not have a valid model name for
+   Verilog synthesis
+Delivering EJava files for 'spartan6_pll'...
+Delivered 3 files into directory
+C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/spartan6_pll
+Delivered 1 file into directory
+C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/spartan6_pll
+Generating ASY schematic symbol...
+Loading device for application Rf_Device from file '6slx9.nph' in environment
+C:\Xilinx\14.7\ISE_DS\ISE\.
+INFO:sim:949 - Finished generation of ASY schematic symbol.
+Generating SYM schematic symbol for 'spartan6_pll'...
+Generating ISE project...
+XCO file found: spartan6_pll.xco
+XMDF file found: spartan6_pll_xmdf.tcl
+Adding C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/spartan6_pll.asy -view
+all -origin_type imported
+Adding C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/spartan6_pll.ucf -view
+all -origin_type created
+Adding C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/spartan6_pll.v -view all
+-origin_type created
+INFO:HDLCompiler:1845 - Analyzing Verilog file
+   "C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/spartan6_pll.v" into library
+   work
+INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
+Adding C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/spartan6_pll.veo -view
+all -origin_type imported
+INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
+   Please set the new top explicitly by running the "project set top" command.
+   To re-calculate the new top automatically, set the "Auto Implementation Top"
+   property to true.
+Top level has been set to "/spartan6_pll"
+Generating README file...
+Generating FLIST file...
+INFO:sim:948 - Finished FLIST file generation.
+Launching README viewer...
+Moving files to output directory...
+Finished moving files to output directory
+Wrote CGP file for project 'spartan6_pll'.
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/edit_EU4Kx32.tcl b/MCL86jr/FPGA/MCL86jr/ipcore_dir/edit_EU4Kx32.tcl
new file mode 100644
index 0000000..a04a184
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/edit_EU4Kx32.tcl
@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator edit command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_edit "EU4Kx32" xc6slx9-3tqg144 Verilog ]
+
+if { $result == 0 } {
+   puts "Core Generator edit command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator edit command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator edit cancelled."
+}
+exit $result
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/edit_spartan6_pll.tcl b/MCL86jr/FPGA/MCL86jr/ipcore_dir/edit_spartan6_pll.tcl
new file mode 100644
index 0000000..0f5f5ec
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/edit_spartan6_pll.tcl
@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator edit command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_edit "spartan6_pll" xc6slx9-3tqg144 Verilog ]
+
+if { $result == 0 } {
+   puts "Core Generator edit command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator edit command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator edit cancelled."
+}
+exit $result
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.asy b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.asy
new file mode 100644
index 0000000..bd66909
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.asy
@@ -0,0 +1,13 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 spartan6_pll
+RECTANGLE Normal 32 32 576 1088
+LINE Normal 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName clk_in1
+PINATTR Polarity IN
+LINE Normal 608 80 576 80
+PIN 608 80 RIGHT 36
+PINATTR PinName clk_out1
+PINATTR Polarity OUT
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.gise b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.gise
new file mode 100644
index 0000000..df46c5d
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.gise
@@ -0,0 +1,52 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="spartan6_pll.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="spartan6_pll.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="spartan6_pll.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema">
+    <transform xil_pn:end_ts="1602182150" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1602182150">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150596" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4305212012872205941" xil_pn:start_ts="1605150596">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150596" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7868220677234866683" xil_pn:start_ts="1605150596">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150596" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1605150596">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1605150596" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6141970609282747533" xil_pn:start_ts="1605150596">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+  </transforms>
+
+</generated_project>
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.ncf b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.ncf
new file mode 100644
index 0000000..17ad990
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.ncf
@@ -0,0 +1,59 @@
+# file: spartan6_pll.ucf
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
+
+
+# FALSE PATH constraints 
+
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.sym b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.sym
new file mode 100644
index 0000000..a5f5394
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.sym
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="spartan6_pll">
+    <symboltype>BLOCK</symboltype>
+    <timestamp>2020-11-11T5:58:57</timestamp>
+    <pin polarity="Input" x="0" y="80" name="clk_in1" />
+    <pin polarity="Output" x="608" y="80" name="clk_out1" />
+    <graph>
+        <text style="fontsize:40;fontname:Arial" x="32" y="32">spartan6_pll</text>
+        <rect width="544" x="32" y="32" height="1056" />
+        <line x2="32" y1="80" y2="80" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin clk_in1" />
+        <line x2="576" y1="80" y2="80" x1="608" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="80" type="pin clk_out1" />
+    </graph>
+</symbol>
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.ucf b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.ucf
new file mode 100644
index 0000000..3a96e2e
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.ucf
@@ -0,0 +1,58 @@
+# file: spartan6_pll.ucf
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
+
+
+# FALSE PATH constraints 
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.v b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.v
new file mode 100644
index 0000000..6c01182
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.v
@@ -0,0 +1,145 @@
+// file: spartan6_pll.v
+// 
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+// "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+//----------------------------------------------------------------------------
+// CLK_OUT1___110.000______0.000______50.0______381.818____150.000
+//
+//----------------------------------------------------------------------------
+// "Input Clock   Freq (MHz)    Input Jitter (UI)"
+//----------------------------------------------------------------------------
+// __primary__________50.000____________0.010
+
+`timescale 1ps/1ps
+
+(* CORE_GENERATION_INFO = "spartan6_pll,clk_wiz_v3_6,{component_name=spartan6_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
+module spartan6_pll
+ (// Clock in ports
+  input         CLK_IN1,
+  // Clock out ports
+  output        CLK_OUT1
+ );
+
+  // Input buffering
+  //------------------------------------
+  IBUFG clkin1_buf
+   (.O (clkin1),
+    .I (CLK_IN1));
+
+
+  // Clocking primitive
+  //------------------------------------
+
+  // Instantiation of the DCM primitive
+  //    * Unused inputs are tied off
+  //    * Unused outputs are labeled unused
+  wire        psdone_unused;
+  wire        locked_int;
+  wire [7:0]  status_int;
+  wire clkfb;
+  wire clk0;
+  wire clkfx;
+
+  DCM_SP
+  #(.CLKDV_DIVIDE          (2.000),
+    .CLKFX_DIVIDE          (5),
+    .CLKFX_MULTIPLY        (11),
+    .CLKIN_DIVIDE_BY_2     ("FALSE"),
+    .CLKIN_PERIOD          (20.0),
+    .CLKOUT_PHASE_SHIFT    ("NONE"),
+    .CLK_FEEDBACK          ("NONE"),
+    .DESKEW_ADJUST         ("SYSTEM_SYNCHRONOUS"),
+    .PHASE_SHIFT           (0),
+    .STARTUP_WAIT          ("FALSE"))
+  dcm_sp_inst
+    // Input clock
+   (.CLKIN                 (clkin1),
+    .CLKFB                 (clkfb),
+    // Output clocks
+    .CLK0                  (clk0),
+    .CLK90                 (),
+    .CLK180                (),
+    .CLK270                (),
+    .CLK2X                 (),
+    .CLK2X180              (),
+    .CLKFX                 (clkfx),
+    .CLKFX180              (),
+    .CLKDV                 (),
+    // Ports for dynamic phase shift
+    .PSCLK                 (1'b0),
+    .PSEN                  (1'b0),
+    .PSINCDEC              (1'b0),
+    .PSDONE                (),
+    // Other control and status signals
+    .LOCKED                (locked_int),
+    .STATUS                (status_int),
+    .RST                   (1'b0),
+    // Unused pin- tie low
+    .DSSEN                 (1'b0));
+
+
+  // Output buffering
+  //-----------------------------------
+  // no phase alignment active, connect to ground
+  assign clkfb = 1'b0;
+
+  BUFG clkout1_buf
+   (.O   (CLK_OUT1),
+    .I   (clkfx));
+
+
+
+
+endmodule
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.veo b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.veo
new file mode 100644
index 0000000..9d7fb90
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.veo
@@ -0,0 +1,75 @@
+// 
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+// "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+//----------------------------------------------------------------------------
+// CLK_OUT1___110.000______0.000______50.0______381.818____150.000
+//
+//----------------------------------------------------------------------------
+// "Input Clock   Freq (MHz)    Input Jitter (UI)"
+//----------------------------------------------------------------------------
+// __primary__________50.000____________0.010
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+
+  spartan6_pll instance_name
+   (// Clock in ports
+    .CLK_IN1(CLK_IN1),      // IN
+    // Clock out ports
+    .CLK_OUT1(CLK_OUT1));    // OUT
+// INST_TAG_END ------ End INSTANTIATION Template ---------
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.xco b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.xco
new file mode 100644
index 0000000..22d2ef5
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.xco
@@ -0,0 +1,269 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Wed Nov 11 05:58:38 2020
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:clk_wiz:3.6
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
+# END Select
+# BEGIN Parameters
+CSET calc_done=DONE
+CSET clk_in_sel_port=CLK_IN_SEL
+CSET clk_out1_port=CLK_OUT1
+CSET clk_out1_use_fine_ps_gui=false
+CSET clk_out2_port=CLK_OUT2
+CSET clk_out2_use_fine_ps_gui=false
+CSET clk_out3_port=CLK_OUT3
+CSET clk_out3_use_fine_ps_gui=false
+CSET clk_out4_port=CLK_OUT4
+CSET clk_out4_use_fine_ps_gui=false
+CSET clk_out5_port=CLK_OUT5
+CSET clk_out5_use_fine_ps_gui=false
+CSET clk_out6_port=CLK_OUT6
+CSET clk_out6_use_fine_ps_gui=false
+CSET clk_out7_port=CLK_OUT7
+CSET clk_out7_use_fine_ps_gui=false
+CSET clk_valid_port=CLK_VALID
+CSET clkfb_in_n_port=CLKFB_IN_N
+CSET clkfb_in_p_port=CLKFB_IN_P
+CSET clkfb_in_port=CLKFB_IN
+CSET clkfb_in_signaling=SINGLE
+CSET clkfb_out_n_port=CLKFB_OUT_N
+CSET clkfb_out_p_port=CLKFB_OUT_P
+CSET clkfb_out_port=CLKFB_OUT
+CSET clkfb_stopped_port=CLKFB_STOPPED
+CSET clkin1_jitter_ps=200.0
+CSET clkin1_ui_jitter=0.010
+CSET clkin2_jitter_ps=100.0
+CSET clkin2_ui_jitter=0.010
+CSET clkout1_drives=BUFG
+CSET clkout1_requested_duty_cycle=50.000
+CSET clkout1_requested_out_freq=110.000
+CSET clkout1_requested_phase=0.000
+CSET clkout2_drives=BUFG
+CSET clkout2_requested_duty_cycle=50.000
+CSET clkout2_requested_out_freq=100.000
+CSET clkout2_requested_phase=0.000
+CSET clkout2_used=false
+CSET clkout3_drives=BUFG
+CSET clkout3_requested_duty_cycle=50.000
+CSET clkout3_requested_out_freq=100.000
+CSET clkout3_requested_phase=0.000
+CSET clkout3_used=false
+CSET clkout4_drives=BUFG
+CSET clkout4_requested_duty_cycle=50.000
+CSET clkout4_requested_out_freq=100.000
+CSET clkout4_requested_phase=0.000
+CSET clkout4_used=false
+CSET clkout5_drives=BUFG
+CSET clkout5_requested_duty_cycle=50.000
+CSET clkout5_requested_out_freq=100.000
+CSET clkout5_requested_phase=0.000
+CSET clkout5_used=false
+CSET clkout6_drives=BUFG
+CSET clkout6_requested_duty_cycle=50.000
+CSET clkout6_requested_out_freq=100.000
+CSET clkout6_requested_phase=0.000
+CSET clkout6_used=false
+CSET clkout7_drives=BUFG
+CSET clkout7_requested_duty_cycle=50.000
+CSET clkout7_requested_out_freq=100.000
+CSET clkout7_requested_phase=0.000
+CSET clkout7_used=false
+CSET clock_mgr_type=AUTO
+CSET component_name=spartan6_pll
+CSET daddr_port=DADDR
+CSET dclk_port=DCLK
+CSET dcm_clk_feedback=NONE
+CSET dcm_clk_out1_port=CLKFX
+CSET dcm_clk_out2_port=CLKFX
+CSET dcm_clk_out3_port=CLK0
+CSET dcm_clk_out4_port=CLK0
+CSET dcm_clk_out5_port=CLK0
+CSET dcm_clk_out6_port=CLK0
+CSET dcm_clkdv_divide=2.0
+CSET dcm_clkfx_divide=5
+CSET dcm_clkfx_multiply=11
+CSET dcm_clkgen_clk_out1_port=CLKFX
+CSET dcm_clkgen_clk_out2_port=CLKFX
+CSET dcm_clkgen_clk_out3_port=CLKFX
+CSET dcm_clkgen_clkfx_divide=1
+CSET dcm_clkgen_clkfx_md_max=0.000
+CSET dcm_clkgen_clkfx_multiply=4
+CSET dcm_clkgen_clkfxdv_divide=2
+CSET dcm_clkgen_clkin_period=10.000
+CSET dcm_clkgen_notes=None
+CSET dcm_clkgen_spread_spectrum=NONE
+CSET dcm_clkgen_startup_wait=false
+CSET dcm_clkin_divide_by_2=false
+CSET dcm_clkin_period=20.000
+CSET dcm_clkout_phase_shift=NONE
+CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
+CSET dcm_notes=None
+CSET dcm_phase_shift=0
+CSET dcm_pll_cascade=NONE
+CSET dcm_startup_wait=false
+CSET den_port=DEN
+CSET din_port=DIN
+CSET dout_port=DOUT
+CSET drdy_port=DRDY
+CSET dwe_port=DWE
+CSET feedback_source=FDBK_AUTO
+CSET in_freq_units=Units_MHz
+CSET in_jitter_units=Units_UI
+CSET input_clk_stopped_port=INPUT_CLK_STOPPED
+CSET jitter_options=UI
+CSET jitter_sel=No_Jitter
+CSET locked_port=LOCKED
+CSET mmcm_bandwidth=OPTIMIZED
+CSET mmcm_clkfbout_mult_f=4.000
+CSET mmcm_clkfbout_phase=0.000
+CSET mmcm_clkfbout_use_fine_ps=false
+CSET mmcm_clkin1_period=10.000
+CSET mmcm_clkin2_period=10.000
+CSET mmcm_clkout0_divide_f=4.000
+CSET mmcm_clkout0_duty_cycle=0.500
+CSET mmcm_clkout0_phase=0.000
+CSET mmcm_clkout0_use_fine_ps=false
+CSET mmcm_clkout1_divide=1
+CSET mmcm_clkout1_duty_cycle=0.500
+CSET mmcm_clkout1_phase=0.000
+CSET mmcm_clkout1_use_fine_ps=false
+CSET mmcm_clkout2_divide=1
+CSET mmcm_clkout2_duty_cycle=0.500
+CSET mmcm_clkout2_phase=0.000
+CSET mmcm_clkout2_use_fine_ps=false
+CSET mmcm_clkout3_divide=1
+CSET mmcm_clkout3_duty_cycle=0.500
+CSET mmcm_clkout3_phase=0.000
+CSET mmcm_clkout3_use_fine_ps=false
+CSET mmcm_clkout4_cascade=false
+CSET mmcm_clkout4_divide=1
+CSET mmcm_clkout4_duty_cycle=0.500
+CSET mmcm_clkout4_phase=0.000
+CSET mmcm_clkout4_use_fine_ps=false
+CSET mmcm_clkout5_divide=1
+CSET mmcm_clkout5_duty_cycle=0.500
+CSET mmcm_clkout5_phase=0.000
+CSET mmcm_clkout5_use_fine_ps=false
+CSET mmcm_clkout6_divide=1
+CSET mmcm_clkout6_duty_cycle=0.500
+CSET mmcm_clkout6_phase=0.000
+CSET mmcm_clkout6_use_fine_ps=false
+CSET mmcm_clock_hold=false
+CSET mmcm_compensation=ZHOLD
+CSET mmcm_divclk_divide=1
+CSET mmcm_notes=None
+CSET mmcm_ref_jitter1=0.010
+CSET mmcm_ref_jitter2=0.010
+CSET mmcm_startup_wait=false
+CSET num_out_clks=1
+CSET override_dcm=false
+CSET override_dcm_clkgen=false
+CSET override_mmcm=false
+CSET override_pll=false
+CSET platform=nt64
+CSET pll_bandwidth=OPTIMIZED
+CSET pll_clk_feedback=CLKFBOUT
+CSET pll_clkfbout_mult=8
+CSET pll_clkfbout_phase=0.000
+CSET pll_clkin_period=20.0
+CSET pll_clkout0_divide=128
+CSET pll_clkout0_duty_cycle=0.500
+CSET pll_clkout0_phase=0.000
+CSET pll_clkout1_divide=40
+CSET pll_clkout1_duty_cycle=0.500
+CSET pll_clkout1_phase=0.000
+CSET pll_clkout2_divide=1
+CSET pll_clkout2_duty_cycle=0.500
+CSET pll_clkout2_phase=0.000
+CSET pll_clkout3_divide=1
+CSET pll_clkout3_duty_cycle=0.500
+CSET pll_clkout3_phase=0.000
+CSET pll_clkout4_divide=1
+CSET pll_clkout4_duty_cycle=0.500
+CSET pll_clkout4_phase=0.000
+CSET pll_clkout5_divide=1
+CSET pll_clkout5_duty_cycle=0.500
+CSET pll_clkout5_phase=0.000
+CSET pll_compensation=INTERNAL
+CSET pll_divclk_divide=1
+CSET pll_notes=None
+CSET pll_ref_jitter=0.010
+CSET power_down_port=POWER_DOWN
+CSET prim_in_freq=50.000
+CSET prim_in_jitter=0.010
+CSET prim_source=Single_ended_clock_capable_pin
+CSET primary_port=CLK_IN1
+CSET primitive=MMCM
+CSET primtype_sel=PLL_BASE
+CSET psclk_port=PSCLK
+CSET psdone_port=PSDONE
+CSET psen_port=PSEN
+CSET psincdec_port=PSINCDEC
+CSET relative_inclk=REL_PRIMARY
+CSET reset_port=RESET
+CSET secondary_in_freq=100.000
+CSET secondary_in_jitter=0.010
+CSET secondary_port=CLK_IN2
+CSET secondary_source=Single_ended_clock_capable_pin
+CSET ss_mod_freq=250
+CSET ss_mode=CENTER_HIGH
+CSET status_port=STATUS
+CSET summary_strings=empty
+CSET use_clk_valid=false
+CSET use_clkfb_stopped=false
+CSET use_dyn_phase_shift=false
+CSET use_dyn_reconfig=false
+CSET use_freeze=false
+CSET use_freq_synth=true
+CSET use_inclk_stopped=false
+CSET use_inclk_switchover=false
+CSET use_locked=false
+CSET use_max_i_jitter=false
+CSET use_min_o_jitter=false
+CSET use_min_power=false
+CSET use_phase_alignment=false
+CSET use_power_down=false
+CSET use_reset=false
+CSET use_spread_spectrum=false
+CSET use_spread_spectrum_1=false
+CSET use_status=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-05-10T12:44:55Z
+# END Extra information
+GENERATE
+# CRC: ba056c03
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.xdc b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.xdc
new file mode 100644
index 0000000..a73ee7a
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.xdc
@@ -0,0 +1,66 @@
+# file: spartan6_pll.xdc
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1]
+set_propagated_clock CLK_IN1
+set_input_jitter CLK_IN1 0.2
+
+
+# Derived clock periods. These are commented out because they are 
+#   automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you 
+#   can copy them into your module level timing checks
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.xise b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.xise
new file mode 100644
index 0000000..af5f247
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll.xise
@@ -0,0 +1,403 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="spartan6_pll.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+    </file>
+    <file xil_pn:name="spartan6_pll.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|spartan6_pll" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="spartan6_pll.v" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spartan6_pll" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="spartan6_pll" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spartan6_pll_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spartan6_pll_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spartan6_pll_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spartan6_pll_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="spartan6_pll" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-11-10T21:58:59" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6B9D9C2E7E2049FA973835E0BADD6A15" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings>
+    <binding xil_pn:location="/spartan6_pll" xil_pn:name="spartan6_pll.ucf"/>
+  </bindings>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/clk_wiz_v3_6_readme.txt b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/clk_wiz_v3_6_readme.txt
new file mode 100644
index 0000000..91dcdd0
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/clk_wiz_v3_6_readme.txt
@@ -0,0 +1,184 @@
+CHANGE LOG for LogiCORE Clocking Wizard V3.6 
+
+                    Release Date: June 19, 2013
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+   http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+3. NEW FEATURE HISTORY 
+
+
+  3.1 ISE 
+  
+    - Spread Spectrum support for 7 series MMCME2
+
+    - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+      Resolved issue with example design becoming core top in planAhead
+
+      Resolved issue with Virtex6 MMCM instantiation for VHDL project
+      Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+06/19/2013  Xilinx, Inc.  3.6(Rev3)    ISE 14.6 support
+10/16/2012  Xilinx, Inc.  3.6(Rev2)    ISE 14.3 support
+07/25/2012  Xilinx, Inc.  3.6          ISE 14.2 support
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/doc/clk_wiz_v3_6_readme.txt b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/doc/clk_wiz_v3_6_readme.txt
new file mode 100644
index 0000000..91dcdd0
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/doc/clk_wiz_v3_6_readme.txt
@@ -0,0 +1,184 @@
+CHANGE LOG for LogiCORE Clocking Wizard V3.6 
+
+                    Release Date: June 19, 2013
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+   http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+3. NEW FEATURE HISTORY 
+
+
+  3.1 ISE 
+  
+    - Spread Spectrum support for 7 series MMCME2
+
+    - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+      Resolved issue with example design becoming core top in planAhead
+
+      Resolved issue with Virtex6 MMCM instantiation for VHDL project
+      Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+06/19/2013  Xilinx, Inc.  3.6(Rev3)    ISE 14.6 support
+10/16/2012  Xilinx, Inc.  3.6(Rev2)    ISE 14.3 support
+07/25/2012  Xilinx, Inc.  3.6          ISE 14.2 support
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/doc/clk_wiz_v3_6_vinfo.html b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/doc/clk_wiz_v3_6_vinfo.html
new file mode 100644
index 0000000..d6deba0
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/doc/clk_wiz_v3_6_vinfo.html
@@ -0,0 +1,195 @@
+<HTML>
+<HEAD>
+<TITLE>clk_wiz_v3_6_vinfo</TITLE>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
+</HEAD>
+<BODY>
+<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
+CHANGE LOG for LogiCORE Clocking Wizard V3.6 
+
+                    Release Date: June 19, 2013
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
+
+For system requirements:
+
+   <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+   <A HREF="http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/">www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/</A>
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+3. NEW FEATURE HISTORY 
+
+
+  3.1 ISE 
+  
+    - Spread Spectrum support for 7 series MMCME2
+
+    - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+      Resolved issue with example design becoming core top in planAhead
+
+      Resolved issue with Virtex6 MMCM instantiation for VHDL project
+      Please refer to AR 50719 - <A HREF="http://www.xilinx.com/support/answers/50719.htm">www.xilinx.com/support/answers/50719.htm</A>
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+06/19/2013  Xilinx, Inc.  3.6(Rev3)    ISE 14.6 support
+10/16/2012  Xilinx, Inc.  3.6(Rev2)    ISE 14.3 support
+07/25/2012  Xilinx, Inc.  3.6          ISE 14.2 support
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
+</FONT>
+</PRE>
+</BODY>
+</HTML>
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/doc/pg065_clk_wiz.pdf b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/doc/pg065_clk_wiz.pdf
new file mode 100644
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diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/example_design/spartan6_pll_exdes.ucf b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/example_design/spartan6_pll_exdes.ucf
new file mode 100644
index 0000000..e788969
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/example_design/spartan6_pll_exdes.ucf
@@ -0,0 +1,59 @@
+# file: spartan6_pll_exdes.ucf
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
+
+
+# FALSE PATH constraints 
+PIN "COUNTER_RESET" TIG;
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/example_design/spartan6_pll_exdes.v b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/example_design/spartan6_pll_exdes.v
new file mode 100644
index 0000000..3a7eb00
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/example_design/spartan6_pll_exdes.v
@@ -0,0 +1,150 @@
+// file: spartan6_pll_exdes.v
+// 
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+
+//----------------------------------------------------------------------------
+// Clocking wizard example design
+//----------------------------------------------------------------------------
+// This example design instantiates the created clocking network, where each
+//   output clock drives a counter. The high bit of each counter is ported.
+//----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+module spartan6_pll_exdes 
+ #( 
+  parameter TCQ = 100
+  )
+ (// Clock in ports
+  input         CLK_IN1,
+  // Reset that only drives logic in example design
+  input         COUNTER_RESET,
+  output [1:1]  CLK_OUT,
+  // High bits of counters driven by clocks
+  output        COUNT
+ );
+
+  // Parameters for the counters
+  //-------------------------------
+  // Counter width
+  localparam    C_W       = 16;
+  // Create reset for the counters
+  wire          reset_int = COUNTER_RESET;
+
+   reg rst_sync;
+   reg rst_sync_int;
+   reg rst_sync_int1;
+   reg rst_sync_int2;
+
+
+
+  // Declare the clocks and counter
+  wire           clk_int;
+  wire           clk_n;
+  wire           clk;
+  reg  [C_W-1:0] counter;
+
+  // Instantiation of the clocking network
+  //--------------------------------------
+  spartan6_pll clknetwork
+   (// Clock in ports
+    .CLK_IN1            (CLK_IN1),
+    // Clock out ports
+    .CLK_OUT1           (clk_int));
+
+  assign clk_n = ~clk;
+
+  ODDR2 clkout_oddr
+   (.Q  (CLK_OUT[1]),
+    .C0 (clk),
+    .C1 (clk_n),
+    .CE (1'b1),
+    .D0 (1'b1),
+    .D1 (1'b0),
+    .R  (1'b0),
+    .S  (1'b0));
+
+  // Connect the output clocks to the design
+  //-----------------------------------------
+  assign clk = clk_int;
+
+
+  // Reset synchronizer
+  //-----------------------------------
+    always @(posedge reset_int or posedge clk) begin
+       if (reset_int) begin
+            rst_sync <= 1'b1;
+            rst_sync_int <= 1'b1;
+            rst_sync_int1 <= 1'b1;
+            rst_sync_int2 <= 1'b1;
+       end
+       else begin
+            rst_sync <= 1'b0;
+            rst_sync_int <= rst_sync;     
+            rst_sync_int1 <= rst_sync_int; 
+            rst_sync_int2 <= rst_sync_int1;
+       end
+    end
+
+
+  // Output clock sampling
+  //-----------------------------------
+  always @(posedge clk or posedge rst_sync_int2) begin
+    if (rst_sync_int2) begin
+      counter <= #TCQ { C_W { 1'b 0 } };
+    end else begin
+      counter <= #TCQ counter + 1'b 1;
+    end
+  end
+
+  // alias the high bit to the output
+  assign COUNT = counter[C_W-1];
+
+
+
+endmodule
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/example_design/spartan6_pll_exdes.xdc b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/example_design/spartan6_pll_exdes.xdc
new file mode 100644
index 0000000..037e7da
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/example_design/spartan6_pll_exdes.xdc
@@ -0,0 +1,68 @@
+# file: spartan6_pll_exdes.xdc
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1]
+set_propagated_clock CLK_IN1
+set_input_jitter CLK_IN1 0.2
+
+# FALSE PATH constraint added on COUNTER_RESET 
+set_false_path -from [get_ports "COUNTER_RESET"]
+
+# Derived clock periods. These are commented out because they are 
+#   automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you 
+#   can copy them into your module level timing checks
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/implement.bat b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/implement.bat
new file mode 100644
index 0000000..cde0a90
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/implement.bat
@@ -0,0 +1,90 @@
+REM file: implement.bat
+REM 
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM 
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM 
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM 
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM 
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM 
+
+REM -----------------------------------------------------------------------------
+REM  Script to synthesize and implement the RTL provided for the clocking wizard
+REM -----------------------------------------------------------------------------
+
+REM Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+REM Copy unisim_comp.v file to results directory
+copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\
+
+REM Synthesize the Verilog Wrapper Files
+echo 'Synthesizing Clocking Wizard design with XST'
+xst -ifn xst.scr
+move spartan6_pll_exdes.ngc results\
+
+REM  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\spartan6_pll_exdes.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -uc spartan6_pll_exdes.ucf spartan6_pll_exdes
+
+echo 'Running map'
+map -timing -pr b spartan6_pll_exdes -o mapped.ncd
+
+echo 'Running par'
+par -w mapped.ncd routed mapped.pcf
+
+echo 'Running trce'
+trce -e 10 routed -o routed mapped.pcf
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level model for the clocking wizard example design'
+netgen -ofmt verilog -sim -sdf_anno false -tm spartan6_pll_exdes -w routed.ncd routed.v
+cd ..
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/implement.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/implement.sh
new file mode 100644
index 0000000..c4c6790
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/implement.sh
@@ -0,0 +1,91 @@
+#!/bin/sh
+# file: implement.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the clocking wizard
+#-----------------------------------------------------------------------------
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+# Copy unisim_comp.v file to results directory
+cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
+
+# Synthesize the Verilog Wrapper Files
+echo 'Synthesizing Clocking Wizard design with XST'
+xst -ifn xst.scr
+mv spartan6_pll_exdes.ngc results/
+
+#  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/spartan6_pll_exdes.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -uc spartan6_pll_exdes.ucf spartan6_pll_exdes
+
+echo 'Running map'
+map -timing spartan6_pll_exdes -o mapped.ncd
+
+echo 'Running par'
+par -w mapped.ncd routed mapped.pcf
+
+echo 'Running trce'
+trce -e 10 routed -o routed mapped.pcf
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level model for the clocking wizard example design'
+netgen -ofmt verilog -sim -sdf_anno false -tm spartan6_pll_exdes -w routed.ncd routed.v
+
+cd ..
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/planAhead_ise.bat b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/planAhead_ise.bat
new file mode 100644
index 0000000..8ac7718
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/planAhead_ise.bat
@@ -0,0 +1,58 @@
+REM file: planAhead_ise.bat
+REM 
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM 
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM 
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM 
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM 
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM 
+
+REM-----------------------------------------------------------------------------
+REM Script to synthesize and implement the RTL provided for the clocking wizard
+REM-----------------------------------------------------------------------------
+
+del \f results
+mkdir results
+cd results
+
+planAhead -mode batch -source ..\planAhead_ise.tcl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/planAhead_ise.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/planAhead_ise.sh
new file mode 100644
index 0000000..6c8c837
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/planAhead_ise.sh
@@ -0,0 +1,59 @@
+#!/bin/sh
+# file: planAhead_ise.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the clocking wizard
+#-----------------------------------------------------------------------------
+
+rm -rf results
+mkdir results
+cd results
+
+planAhead -mode batch -source ../planAhead_ise.tcl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/planAhead_ise.tcl b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/planAhead_ise.tcl
new file mode 100644
index 0000000..12ec751
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/planAhead_ise.tcl
@@ -0,0 +1,78 @@
+# file: planAhead_ise.tcl
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+set projDir [file dirname [info script]]
+set projName spartan6_pll
+set topName spartan6_pll_exdes
+set device xc6slx9tqg144-3
+
+create_project $projName $projDir/results/$projName -part $device
+
+set_property design_mode RTL [get_filesets sources_1]
+
+## Source files
+#set verilogSources [glob $srcDir/*.v]
+import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/spartan6_pll_exdes.v
+import_files -fileset [get_filesets sources_1] -force -norecurse ../../../spartan6_pll.v
+
+
+#UCF file
+import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/spartan6_pll_exdes.ucf
+
+set_property top $topName [get_property srcset [current_run]]
+
+launch_runs -runs synth_1
+wait_on_run synth_1
+
+set_property add_step Bitgen [get_runs impl_1]
+launch_runs -runs impl_1
+wait_on_run impl_1
+
+
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/planAhead_rdn.bat b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/planAhead_rdn.bat
new file mode 100644
index 0000000..42273f5
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/planAhead_rdn.bat
@@ -0,0 +1,58 @@
+REM file: planAhead_rdn.sh
+REM 
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM 
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM 
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM 
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM 
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM 
+
+REM-----------------------------------------------------------------------------
+REM Script to synthesize and implement the RTL provided for the XADC wizard
+REM-----------------------------------------------------------------------------
+
+del \f results
+mkdir results
+cd results
+
+planAhead -mode batch -source ..\planAhead_rdn.tcl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/planAhead_rdn.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/planAhead_rdn.sh
new file mode 100644
index 0000000..f4c1472
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/planAhead_rdn.sh
@@ -0,0 +1,57 @@
+#!/bin/sh
+# file: planAhead_rdn.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the XADC wizard
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+planAhead -mode batch -source ../planAhead_rdn.tcl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/planAhead_rdn.tcl b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/planAhead_rdn.tcl
new file mode 100644
index 0000000..d3d5a12
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/planAhead_rdn.tcl
@@ -0,0 +1,69 @@
+# file : planAhead_rdn.tcl
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+set device xc6slx9tqg144-3
+set projName spartan6_pll
+set design spartan6_pll
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module spartan6_pll_exdes
+set_property top spartan6_pll_exdes [get_property srcset [current_run]]
+add_files -norecurse {../../../spartan6_pll.v}
+add_files -norecurse {../../example_design/spartan6_pll_exdes.v}
+import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/spartan6_pll_exdes.xdc}
+synth_design
+opt_design 
+place_design 
+route_design 
+write_sdf -rename_top_module spartan6_pll_exdes -file routed.sdf 
+write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module spartan6_pll_exdes -file routed.v
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file report.drc
+write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/xst.prj b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/xst.prj
new file mode 100644
index 0000000..7f15d91
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/xst.prj
@@ -0,0 +1,2 @@
+verilog work ../../spartan6_pll.v
+verilog work ../example_design/spartan6_pll_exdes.v
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/xst.scr b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/xst.scr
new file mode 100644
index 0000000..59ebfa7
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/implement/xst.scr
@@ -0,0 +1,9 @@
+run
+-ifmt MIXED
+-top spartan6_pll_exdes
+-p xc6slx9-tqg144-3
+-ifn xst.prj
+-ofn spartan6_pll_exdes
+-keep_hierarchy soft 
+-equivalent_register_removal no 
+-max_fanout 65535
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simcmds.tcl b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simcmds.tcl
new file mode 100644
index 0000000..cdf8da7
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simcmds.tcl
@@ -0,0 +1,8 @@
+# file: simcmds.tcl
+
+# create the simulation script
+vcd dumpfile isim.vcd
+vcd dumpvars -m /spartan6_pll_tb -l 0
+wave add /
+run 50000ns
+quit
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_isim.bat b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_isim.bat
new file mode 100644
index 0000000..78a157f
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_isim.bat
@@ -0,0 +1,59 @@
+REM file: simulate_isim.bat
+REM  
+REM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM  
+REM  This file contains confidential and proprietary information
+REM  of Xilinx, Inc. and is protected under U.S. and
+REM  international copyright and other intellectual property
+REM  laws.
+REM  
+REM  DISCLAIMER
+REM  This disclaimer is not a license and does not grant any
+REM  rights to the materials distributed herewith. Except as
+REM  otherwise provided in a valid license issued to you by
+REM  Xilinx, and to the maximum extent permitted by applicable
+REM  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM  (2) Xilinx shall not be liable (whether in contract or tort,
+REM  including negligence, or under any other theory of
+REM  liability) for any loss or damage of any kind or nature
+REM  related to, arising under or in connection with these
+REM  materials, including for any direct, or any indirect,
+REM  special, incidental, or consequential loss or damage
+REM  (including loss of data, profits, goodwill, or any type of
+REM  loss or damage suffered as a result of any action brought
+REM  by a third party) even if such damage or loss was
+REM  reasonably foreseeable or Xilinx had been advised of the
+REM  possibility of the same.
+REM  
+REM  CRITICAL APPLICATIONS
+REM  Xilinx products are not designed or intended to be fail-
+REM  safe, or for use in any application requiring fail-safe
+REM  performance, such as life-support or safety devices or
+REM  systems, Class III medical devices, nuclear facilities,
+REM  applications related to the deployment of airbags, or any
+REM  other applications that could lead to death, personal
+REM  injury, or severe property or environmental damage
+REM  (individually and collectively, "Critical
+REM  Applications"). Customer assumes the sole risk and
+REM  liability of any use of Xilinx products in Critical
+REM  Applications, subject only to applicable laws and
+REM  regulations governing limitations on product liability.
+REM  
+REM  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM  PART OF THIS FILE AT ALL TIMES.
+REM  
+
+vlogcomp -work work %XILINX%\verilog\src\glbl.v
+vlogcomp -work work ..\..\..\spartan6_pll.v
+vlogcomp -work work ..\..\example_design\spartan6_pll_exdes.v
+vlogcomp -work work ..\spartan6_pll_tb.v
+
+REM compile the project
+fuse work.spartan6_pll_tb work.glbl -L unisims_ver -o spartan6_pll_isim.exe
+
+REM run the simulation script
+.\spartan6_pll_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_isim.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_isim.sh
new file mode 100644
index 0000000..c890b54
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_isim.sh
@@ -0,0 +1,61 @@
+# file: simulate_isim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# nt64
+# create the project
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -work work ../../../spartan6_pll.v
+vlogcomp -work work ../../example_design/spartan6_pll_exdes.v
+vlogcomp -work work ../spartan6_pll_tb.v
+
+# compile the project
+fuse work.spartan6_pll_tb work.glbl -L unisims_ver -o spartan6_pll_isim.exe
+
+# run the simulation script
+./spartan6_pll_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_mti.bat b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_mti.bat
new file mode 100644
index 0000000..eb14f17
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_mti.bat
@@ -0,0 +1,61 @@
+REM file: simulate_mti.bat
+REM  
+REM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM  
+REM  This file contains confidential and proprietary information
+REM  of Xilinx, Inc. and is protected under U.S. and
+REM  international copyright and other intellectual property
+REM  laws.
+REM  
+REM  DISCLAIMER
+REM  This disclaimer is not a license and does not grant any
+REM  rights to the materials distributed herewith. Except as
+REM  otherwise provided in a valid license issued to you by
+REM  Xilinx, and to the maximum extent permitted by applicable
+REM  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM  (2) Xilinx shall not be liable (whether in contract or tort,
+REM  including negligence, or under any other theory of
+REM  liability) for any loss or damage of any kind or nature
+REM  related to, arising under or in connection with these
+REM  materials, including for any direct, or any indirect,
+REM  special, incidental, or consequential loss or damage
+REM  (including loss of data, profits, goodwill, or any type of
+REM  loss or damage suffered as a result of any action brought
+REM  by a third party) even if such damage or loss was
+REM  reasonably foreseeable or Xilinx had been advised of the
+REM  possibility of the same.
+REM  
+REM  CRITICAL APPLICATIONS
+REM  Xilinx products are not designed or intended to be fail-
+REM  safe, or for use in any application requiring fail-safe
+REM  performance, such as life-support or safety devices or
+REM  systems, Class III medical devices, nuclear facilities,
+REM  applications related to the deployment of airbags, or any
+REM  other applications that could lead to death, personal
+REM  injury, or severe property or environmental damage
+REM  (individually and collectively, "Critical
+REM  Applications"). Customer assumes the sole risk and
+REM  liability of any use of Xilinx products in Critical
+REM  Applications, subject only to applicable laws and
+REM  regulations governing limitations on product liability.
+REM  
+REM  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM  PART OF THIS FILE AT ALL TIMES.
+REM  
+
+REM set up the working directory
+vlib work
+
+REM compile all of the files
+vlog -work work %XILINX%\verilog\src\glbl.v
+vlog -work work ..\..\..\spartan6_pll.v
+vlog -work work ..\..\example_design\spartan6_pll_exdes.v
+vlog -work work ..\spartan6_pll_tb.v
+
+REM run the simulation
+vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.spartan6_pll_tb work.glbl
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_mti.do b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_mti.do
new file mode 100644
index 0000000..179ea4e
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_mti.do
@@ -0,0 +1,65 @@
+# file: simulate_mti.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $env(XILINX)/verilog/src/glbl.v
+vlog -work work ../../../spartan6_pll.v
+vlog -work work ../../example_design/spartan6_pll_exdes.v
+vlog -work work ../spartan6_pll_tb.v
+
+# run the simulation
+vsim  -t ps -voptargs="+acc" -L unisims_ver work.spartan6_pll_tb work.glbl
+do wave.do
+log spartan6_pll_tb/dut/counter
+log -r /*
+run 50000ns
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_mti.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_mti.sh
new file mode 100644
index 0000000..3e9a9d7
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_mti.sh
@@ -0,0 +1,61 @@
+#/bin/sh
+# file: simulate_mti.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $XILINX/verilog/src/glbl.v
+vlog -work work ../../../spartan6_pll.v
+vlog -work work ../../example_design/spartan6_pll_exdes.v
+vlog -work work ../spartan6_pll_tb.v
+
+# run the simulation
+vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.spartan6_pll_tb work.glbl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_ncsim.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_ncsim.sh
new file mode 100644
index 0000000..62f3e24
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_ncsim.sh
@@ -0,0 +1,62 @@
+#/bin/sh
+# file: simulate_ncsim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+mkdir work
+
+# compile all of the files
+ncvlog -work work ${XILINX}/verilog/src/glbl.v
+ncvlog -work work ../../../spartan6_pll.v
+ncvlog -work work ../../example_design/spartan6_pll_exdes.v
+ncvlog -work work ../spartan6_pll_tb.v
+
+# elaborate and run the simulation
+ncelab -work work -access +wc work.spartan6_pll_tb work.glbl
+ncsim -input  "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.spartan6_pll_tb
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_vcs.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_vcs.sh
new file mode 100644
index 0000000..fbe63f8
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/simulate_vcs.sh
@@ -0,0 +1,72 @@
+#!/bin/sh
+# file: simulate_vcs.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# remove old files
+rm -rf simv* csrc DVEfiles AN.DB
+
+# compile all of the files
+# Note that -sverilog is not strictly required- You can
+#   remove the -sverilog if you change the type of the
+#   localparam for the periods in the testbench file to 
+#   [63:0] from time
+vlogan -sverilog \
+      ${XILINX}/verilog/src/glbl.v \
+      ../../../spartan6_pll.v \
+      ../../example_design/spartan6_pll_exdes.v \
+      ../spartan6_pll_tb.v
+
+# prepare the simulation 
+vcs +vcs+lic+wait -debug spartan6_pll_tb glbl
+
+# run the simulation
+./simv -ucli -i ucli_commands.key
+
+# launch the viewer
+dve -vpd vcdplus.vpd -session vcs_session.tcl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/ucli_commands.key b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/ucli_commands.key
new file mode 100644
index 0000000..b30f25d
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/ucli_commands.key
@@ -0,0 +1,5 @@
+call {$vcdpluson}
+call {$vcdplusmemon(spartan6_pll_tb.dut.counter)}
+run
+call {$vcdplusclose}
+quit
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/vcs_session.tcl b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/vcs_session.tcl
new file mode 100644
index 0000000..ca06641
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/vcs_session.tcl
@@ -0,0 +1,15 @@
+gui_open_window Wave
+gui_sg_create spartan6_pll_group
+gui_list_add_group -id Wave.1 {spartan6_pll_group}
+gui_sg_addsignal -group spartan6_pll_group {spartan6_pll_tb.test_phase}
+gui_set_radix -radix {ascii} -signals {spartan6_pll_tb.test_phase}
+gui_sg_addsignal -group spartan6_pll_group {{Input_clocks}} -divider
+gui_sg_addsignal -group spartan6_pll_group {spartan6_pll_tb.CLK_IN1}
+gui_sg_addsignal -group spartan6_pll_group {{Output_clocks}} -divider
+gui_sg_addsignal -group spartan6_pll_group {spartan6_pll_tb.dut.clk}
+gui_list_expand -id Wave.1 spartan6_pll_tb.dut.clk
+gui_sg_addsignal -group spartan6_pll_group {{Counters}} -divider
+gui_sg_addsignal -group spartan6_pll_group {spartan6_pll_tb.COUNT}
+gui_sg_addsignal -group spartan6_pll_group {spartan6_pll_tb.dut.counter}
+gui_list_expand -id Wave.1 spartan6_pll_tb.dut.counter
+gui_zoom -window Wave.1 -full
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/wave.do b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/wave.do
new file mode 100644
index 0000000..02ec307
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/wave.do
@@ -0,0 +1,57 @@
+# file: wave.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+add wave -noupdate -format Literal -radix ascii /spartan6_pll_tb/test_phase
+add wave -noupdate -divider {Input clocks}
+add wave -noupdate -format Logic /spartan6_pll_tb/CLK_IN1
+add wave -noupdate -divider {Output clocks}
+add wave -noupdate -format Logic /spartan6_pll_tb/dut/clk
+add wave -noupdate -divider Counters
+add wave -noupdate -format Literal -radix hexadecimal /spartan6_pll_tb/COUNT
+add wave -noupdate -format Literal -radix hexadecimal /spartan6_pll_tb/dut/counter
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/wave.sv b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/wave.sv
new file mode 100644
index 0000000..29c7d73
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/functional/wave.sv
@@ -0,0 +1,111 @@
+# file: wave.sv
+# 
+# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# Get the windows set up
+#
+if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} {
+    window geometry "Design Browser 1" 1054x819+536+322
+}
+window target "Design Browser 1" on
+browser using {Design Browser 1}
+browser set \
+    -scope nc::spartan6_pll_tb
+browser yview see nc::spartan6_pll_tb
+browser timecontrol set -lock 0
+
+if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} {
+    window geometry "Waveform 1" 1010x600+0+541
+}
+window target "Waveform 1" on
+waveform using {Waveform 1}
+waveform sidebar visibility partial
+waveform set \
+    -primarycursor TimeA \
+    -signalnames name \
+    -signalwidth 175 \
+    -units ns \
+    -valuewidth 75
+cursor set -using TimeA -time 0
+waveform baseline set -time 0
+waveform xview limits 0 20000n
+
+#
+# Define signal groups
+#
+catch {group new -name {Output clocks} -overlay 0}
+catch {group new -name {Status/control} -overlay 0}
+catch {group new -name {Counters} -overlay 0}
+
+set id [waveform add -signals [list {nc::spartan6_pll_tb.CLK_IN1}]]
+
+group using {Output clocks}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+    {spartan6_pll_tb.dut.clk} \
+
+group using {Counters}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+    {spartan6_pll_tb.dut.counter} \
+
+
+set id [waveform add -signals [list {nc::spartan6_pll_tb.COUNT} ]]
+
+set id [waveform add -signals [list {nc::spartan6_pll_tb.test_phase} ]]
+waveform format $id -radix %a
+
+set groupId [waveform add -groups {{Input clocks}}]
+set groupId [waveform add -groups {{Output clocks}}]
+set groupId [waveform add -groups {{Status/control}}]
+set groupId [waveform add -groups {{Counters}}]
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/spartan6_pll_tb.v b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/spartan6_pll_tb.v
new file mode 100644
index 0000000..9e5235e
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/spartan6_pll_tb.v
@@ -0,0 +1,133 @@
+// file: spartan6_pll_tb.v
+// 
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+
+//----------------------------------------------------------------------------
+// Clocking wizard demonstration testbench
+//----------------------------------------------------------------------------
+// This demonstration testbench instantiates the example design for the 
+//   clocking wizard. Input clocks are toggled, which cause the clocking
+//   network to lock and the counters to increment.
+//----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+`define wait_lock @(posedge dut.clknetwork.dcm_sp_inst.LOCKED)
+
+module spartan6_pll_tb ();
+
+  // Clock to Q delay of 100ps
+  localparam  TCQ              = 100;
+
+
+  // timescale is 1ps/1ps
+  localparam  ONE_NS      = 1000;
+  localparam  PHASE_ERR_MARGIN   = 100; // 100ps
+  // how many cycles to run
+  localparam  COUNT_PHASE = 1024;
+  // we'll be using the period in many locations
+  localparam time PER1    = 20.0*ONE_NS;
+  localparam time PER1_1  = PER1/2;
+  localparam time PER1_2  = PER1 - PER1/2;
+
+  // Declare the input clock signals
+  reg         CLK_IN1     = 1;
+
+  // The high bit of the sampling counter
+  wire        COUNT;
+  reg         COUNTER_RESET = 0;
+wire [1:1] CLK_OUT;
+//Freq Check using the M & D values setting and actual Frequency generated
+
+
+  // Input clock generation
+  //------------------------------------
+  always begin
+    CLK_IN1 = #PER1_1 ~CLK_IN1;
+    CLK_IN1 = #PER1_2 ~CLK_IN1;
+  end
+
+  // Test sequence
+  reg [15*8-1:0] test_phase = "";
+  initial begin
+    // Set up any display statements using time to be readable
+    $timeformat(-12, 2, "ps", 10);
+    COUNTER_RESET = 0;
+    test_phase = "wait lock";
+    `wait_lock;
+    #(PER1*6);
+    COUNTER_RESET = 1;
+    #(PER1*20)
+    COUNTER_RESET = 0;
+
+    test_phase = "counting";
+    #(PER1*COUNT_PHASE);
+
+    $display("SIMULATION PASSED");
+    $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
+    $finish;
+  end
+
+  // Instantiation of the example design containing the clock
+  //    network and sampling counters
+  //---------------------------------------------------------
+  spartan6_pll_exdes 
+  #(
+    .TCQ (TCQ)
+   ) dut
+   (// Clock in ports
+    .CLK_IN1            (CLK_IN1),
+    // Reset for logic in example design
+    .COUNTER_RESET      (COUNTER_RESET),
+    .CLK_OUT            (CLK_OUT),
+    // High bits of the counters
+    .COUNT              (COUNT));
+
+// Freq Check 
+
+endmodule
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/sdf_cmd_file b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/sdf_cmd_file
new file mode 100644
index 0000000..5166ae5
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/sdf_cmd_file
@@ -0,0 +1,2 @@
+COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X",
+SCOPE = spartan6_pll_tb.dut;
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simcmds.tcl b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simcmds.tcl
new file mode 100644
index 0000000..6bf6dcf
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simcmds.tcl
@@ -0,0 +1,9 @@
+# file: simcmds.tcl
+
+# create the simulation script
+vcd dumpfile isim.vcd
+vcd dumpvars -m /spartan6_pll_tb -l 0
+wave add /
+run 50000ns
+quit
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simulate_isim.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simulate_isim.sh
new file mode 100644
index 0000000..18f30b1
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simulate_isim.sh
@@ -0,0 +1,62 @@
+# file: simulate_isim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# create the project
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -work work ../../implement/results/routed.v
+vlogcomp -work work spartan6_pll_tb.v
+
+# compile the project
+fuse work.spartan6_pll_tb work.glbl -L secureip -L simprims_ver -o spartan6_pll_isim.exe
+
+# run the simulation script
+./spartan6_pll_isim.exe -tclbatch simcmds.tcl -sdfmax /spartan6_pll_tb/dut=../../implement/results/routed.sdf
+
+# run the simulation script
+#./spartan6_pll_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simulate_mti.bat b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simulate_mti.bat
new file mode 100644
index 0000000..4efe882
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simulate_mti.bat
@@ -0,0 +1,59 @@
+REM file: simulate_mti.bat
+REM  
+REM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM  
+REM  This file contains confidential and proprietary information
+REM  of Xilinx, Inc. and is protected under U.S. and
+REM  international copyright and other intellectual property
+REM  laws.
+REM  
+REM  DISCLAIMER
+REM  This disclaimer is not a license and does not grant any
+REM  rights to the materials distributed herewith. Except as
+REM  otherwise provided in a valid license issued to you by
+REM  Xilinx, and to the maximum extent permitted by applicable
+REM  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM  (2) Xilinx shall not be liable (whether in contract or tort,
+REM  including negligence, or under any other theory of
+REM  liability) for any loss or damage of any kind or nature
+REM  related to, arising under or in connection with these
+REM  materials, including for any direct, or any indirect,
+REM  special, incidental, or consequential loss or damage
+REM  (including loss of data, profits, goodwill, or any type of
+REM  loss or damage suffered as a result of any action brought
+REM  by a third party) even if such damage or loss was
+REM  reasonably foreseeable or Xilinx had been advised of the
+REM  possibility of the same.
+REM  
+REM  CRITICAL APPLICATIONS
+REM  Xilinx products are not designed or intended to be fail-
+REM  safe, or for use in any application requiring fail-safe
+REM  performance, such as life-support or safety devices or
+REM  systems, Class III medical devices, nuclear facilities,
+REM  applications related to the deployment of airbags, or any
+REM  other applications that could lead to death, personal
+REM  injury, or severe property or environmental damage
+REM  (individually and collectively, "Critical
+REM  Applications"). Customer assumes the sole risk and
+REM  liability of any use of Xilinx products in Critical
+REM  Applications, subject only to applicable laws and
+REM  regulations governing limitations on product liability.
+REM  
+REM  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM  PART OF THIS FILE AT ALL TIMES.
+REM  
+# set up the working directory
+set work work
+vlib work
+
+REM compile all of the files
+vlog -work work %XILINX%\verilog\src\glbl.v
+vlog -work work ..\..\implement\results\routed.v
+vlog -work work spartan6_pll_tb.v
+
+REM run the simulation
+vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax spartan6_pll_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.spartan6_pll_tb work.glbl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simulate_mti.do b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simulate_mti.do
new file mode 100644
index 0000000..8919a7c
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simulate_mti.do
@@ -0,0 +1,65 @@
+# file: simulate_mti.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $env(XILINX)/verilog/src/glbl.v
+vlog -work work ../../implement/results/routed.v
+vlog -work work spartan6_pll_tb.v
+
+# run the simulation
+vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax spartan6_pll_tb/dut=../../implement/results/routed.sdf +no_notifier work.spartan6_pll_tb work.glbl
+#do wave.do
+#log -r /*
+run 50000ns
+
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simulate_mti.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simulate_mti.sh
new file mode 100644
index 0000000..9c6e43c
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simulate_mti.sh
@@ -0,0 +1,61 @@
+#/bin/sh
+# file: simulate_mti.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $XILINX/verilog/src/glbl.v
+vlog -work work ../../implement/results/routed.v
+vlog -work work spartan6_pll_tb.v
+
+# run the simulation
+vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax spartan6_pll_tb/dut=../../implement/results/routed.sdf +no_notifier work.spartan6_pll_tb work.glbl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simulate_ncsim.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simulate_ncsim.sh
new file mode 100644
index 0000000..c2c5765
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simulate_ncsim.sh
@@ -0,0 +1,64 @@
+#!/bin/sh
+# file: simulate_ncsim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+mkdir work
+
+# compile all of the files
+ncvlog -work work ${XILINX}/verilog/src/glbl.v
+ncvlog -work work ../../implement/results/routed.v
+ncvlog -work work spartan6_pll_tb.v
+
+# elaborate and run the simulation
+ncsdfc ../../implement/results/routed.sdf
+
+ncelab -work work -access +wc -pulse_r 10 -nonotifier work.spartan6_pll_tb work.glbl -sdf_cmd_file sdf_cmd_file
+ncsim -input  "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.spartan6_pll_tb
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simulate_vcs.sh b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simulate_vcs.sh
new file mode 100644
index 0000000..25b1512
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/simulate_vcs.sh
@@ -0,0 +1,72 @@
+#!/bin/sh
+# file: simulate_vcs.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# remove old files
+rm -rf simv* csrc DVEfiles AN.DB
+
+# compile all of the files
+# Note that -sverilog is not strictly required- You can
+#   remove the -sverilog if you change the type of the
+#   localparam for the periods in the testbench file to 
+#   [63:0] from time
+  vlogan -sverilog \
+           spartan6_pll_tb.v \
+           ../../implement/results/routed.v
+
+
+# prepare the simulation
+vcs -sdf max:spartan6_pll_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \
+        +libext+.v -debug spartan6_pll_tb.v ../../implement/results/routed.v
+
+# run the simulation
+./simv -ucli -i ucli_commands.key
+
+# launch the viewer
+#dve -vpd vcdplus.vpd -session vcs_session.tcl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/spartan6_pll_tb.v b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/spartan6_pll_tb.v
new file mode 100644
index 0000000..13e6e9c
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/spartan6_pll_tb.v
@@ -0,0 +1,136 @@
+// file: spartan6_pll_tb.v
+// 
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+
+//----------------------------------------------------------------------------
+// Clocking wizard demonstration testbench
+//----------------------------------------------------------------------------
+// This demonstration testbench instantiates the example design for the 
+//   clocking wizard. Input clocks are toggled, which cause the clocking
+//   network to lock and the counters to increment.
+//----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+
+module spartan6_pll_tb ();
+
+  // Clock to Q delay of 100ps
+  localparam  TCQ              = 100;
+
+
+  // timescale is 1ps/1ps
+  localparam  ONE_NS      = 1000;
+  localparam  PHASE_ERR_MARGIN   = 100; // 100ps
+  // how many cycles to run
+  localparam  COUNT_PHASE = 1024;
+  // we'll be using the period in many locations
+  localparam time PER1    = 20.0*ONE_NS;
+  localparam time PER1_1  = PER1/2;
+  localparam time PER1_2  = PER1 - PER1/2;
+
+  // Declare the input clock signals
+  reg         CLK_IN1     = 1;
+
+  // The high bit of the sampling counter
+  wire        COUNT;
+  reg         COUNTER_RESET = 0;
+wire [1:1] CLK_OUT;
+//Freq Check using the M & D values setting and actual Frequency generated 
+
+  reg [13:0]  timeout_counter = 14'b00000000000000;
+
+  // Input clock generation
+  //------------------------------------
+  always begin
+    CLK_IN1 = #PER1_1 ~CLK_IN1;
+    CLK_IN1 = #PER1_2 ~CLK_IN1;
+  end
+
+  // Test sequence
+  reg [15*8-1:0] test_phase = "";
+  initial begin
+    // Set up any display statements using time to be readable
+    $timeformat(-12, 2, "ps", 10);
+    $display ("Timing checks are not valid");
+    COUNTER_RESET = 0;
+    test_phase = "wait lock";
+    #(PER1*50);
+    #(PER1*6);
+    COUNTER_RESET = 1;
+    #(PER1*19.5)
+    COUNTER_RESET = 0;
+    #(PER1*1)
+    $display ("Timing checks are valid");
+    test_phase = "counting";
+    #(PER1*COUNT_PHASE);
+
+    $display("SIMULATION PASSED");
+    $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
+    $finish;
+  end
+
+
+
+  // Instantiation of the example design containing the clock
+  //    network and sampling counters
+  //---------------------------------------------------------
+  spartan6_pll_exdes 
+    dut
+   (// Clock in ports
+    .CLK_IN1            (CLK_IN1),
+    // Reset for logic in example design
+    .COUNTER_RESET      (COUNTER_RESET),
+    .CLK_OUT            (CLK_OUT),
+    // High bits of the counters
+    .COUNT              (COUNT));
+
+
+// Freq Check 
+
+endmodule
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/ucli_commands.key b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/ucli_commands.key
new file mode 100644
index 0000000..0548d17
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/ucli_commands.key
@@ -0,0 +1,5 @@
+
+call {$vcdpluson}
+run 50000ns
+call {$vcdplusclose}
+quit
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/vcs_session.tcl b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/vcs_session.tcl
new file mode 100644
index 0000000..1438f6b
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/vcs_session.tcl
@@ -0,0 +1 @@
+gui_open_window Wave
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/wave.do b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/wave.do
new file mode 100644
index 0000000..d864e9c
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll/simulation/timing/wave.do
@@ -0,0 +1,70 @@
+# file: wave.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /spartan6_pll_tb/CLK_IN1
+add wave -noupdate /spartan6_pll_tb/COUNT
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {3223025 ps} 0}
+configure wave -namecolwidth 238
+configure wave -valuecolwidth 107
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {74848022 ps}
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll_flist.txt b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll_flist.txt
new file mode 100644
index 0000000..d320adc
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll_flist.txt
@@ -0,0 +1,55 @@
+# Output products list for <spartan6_pll>
+_xmsgs\pn_parser.xmsgs
+spartan6_pll.asy
+spartan6_pll.gise
+spartan6_pll.sym
+spartan6_pll.ucf
+spartan6_pll.v
+spartan6_pll.veo
+spartan6_pll.xco
+spartan6_pll.xdc
+spartan6_pll.xise
+spartan6_pll\clk_wiz_v3_6_readme.txt
+spartan6_pll\doc\clk_wiz_v3_6_readme.txt
+spartan6_pll\doc\clk_wiz_v3_6_vinfo.html
+spartan6_pll\doc\pg065_clk_wiz.pdf
+spartan6_pll\example_design\spartan6_pll_exdes.ucf
+spartan6_pll\example_design\spartan6_pll_exdes.v
+spartan6_pll\example_design\spartan6_pll_exdes.xdc
+spartan6_pll\implement\implement.bat
+spartan6_pll\implement\implement.sh
+spartan6_pll\implement\planAhead_ise.bat
+spartan6_pll\implement\planAhead_ise.sh
+spartan6_pll\implement\planAhead_ise.tcl
+spartan6_pll\implement\planAhead_rdn.bat
+spartan6_pll\implement\planAhead_rdn.sh
+spartan6_pll\implement\planAhead_rdn.tcl
+spartan6_pll\implement\xst.prj
+spartan6_pll\implement\xst.scr
+spartan6_pll\simulation\functional\simcmds.tcl
+spartan6_pll\simulation\functional\simulate_isim.bat
+spartan6_pll\simulation\functional\simulate_isim.sh
+spartan6_pll\simulation\functional\simulate_mti.bat
+spartan6_pll\simulation\functional\simulate_mti.do
+spartan6_pll\simulation\functional\simulate_mti.sh
+spartan6_pll\simulation\functional\simulate_ncsim.sh
+spartan6_pll\simulation\functional\simulate_vcs.sh
+spartan6_pll\simulation\functional\ucli_commands.key
+spartan6_pll\simulation\functional\vcs_session.tcl
+spartan6_pll\simulation\functional\wave.do
+spartan6_pll\simulation\functional\wave.sv
+spartan6_pll\simulation\spartan6_pll_tb.v
+spartan6_pll\simulation\timing\sdf_cmd_file
+spartan6_pll\simulation\timing\simcmds.tcl
+spartan6_pll\simulation\timing\simulate_isim.sh
+spartan6_pll\simulation\timing\simulate_mti.bat
+spartan6_pll\simulation\timing\simulate_mti.do
+spartan6_pll\simulation\timing\simulate_mti.sh
+spartan6_pll\simulation\timing\simulate_ncsim.sh
+spartan6_pll\simulation\timing\simulate_vcs.sh
+spartan6_pll\simulation\timing\spartan6_pll_tb.v
+spartan6_pll\simulation\timing\ucli_commands.key
+spartan6_pll\simulation\timing\vcs_session.tcl
+spartan6_pll\simulation\timing\wave.do
+spartan6_pll_flist.txt
+spartan6_pll_xmdf.tcl
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll_xmdf.tcl b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll_xmdf.tcl
new file mode 100644
index 0000000..50e2085
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/spartan6_pll_xmdf.tcl
@@ -0,0 +1,140 @@
+# The package naming convention is <core_name>_xmdf
+package provide spartan6_pll_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::spartan6_pll_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::spartan6_pll_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name spartan6_pll
+}
+# ::spartan6_pll_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::spartan6_pll_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll/clk_wiz_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll/doc/clk_wiz_ds709.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll/doc/clk_wiz_gsg521.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll/implement/implement.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll/implement/implement.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll/implement/xst.prj
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll/implement/xst.scr
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll/simulation/spartan6_pll_tb.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll/simulation/functional/simcmds.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll/simulation/functional/simulate_isim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll/simulation/functional/simulate_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll/simulation/functional/simulate_ncsim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll/simulation/functional/simulate_vcs.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll/simulation/functional/ucli_commands.key
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll/simulation/functional/vcs_session.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll/simulation/functional/wave.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll/simulation/functional/wave.sv
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll.ejp
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spartan6_pll_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module spartan6_pll
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/summary.log b/MCL86jr/FPGA/MCL86jr/ipcore_dir/summary.log
new file mode 100644
index 0000000..f64e212
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/summary.log
@@ -0,0 +1,18 @@
+
+User Configuration
+-------------------------------------
+Algorithm				:	Minimum_Area
+Memory Type				:	Single_Port_ROM
+Port A Read Width		:	32
+Memory Depth			:	4096
+--------------------------------------------------------------
+
+Block RAM resource(s) (9K BRAMs)		: 1
+Block RAM resource(s) (18K BRAMs)		: 7
+--------------------------------------------------------------
+Clock A Frequency		:  100
+Port A Enable Rate		:  100
+Port A Write Rate		:  0
+----------------------------------------------------------
+Estimated Power for IP : 8.267622 mW
+----------------------------------------------------------
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/EU4Kx32.lso b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/EU4Kx32.lso
new file mode 100644
index 0000000..b8f99f5
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/EU4Kx32.lso
@@ -0,0 +1 @@
+work
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs
new file mode 100644
index 0000000..b579295
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated   -->
+<!--     by the Xilinx ISE software.  Any direct editing or        -->
+<!--     changes made to this file may result in unpredictable     -->
+<!--     behavior or data corruption.  It is strongly advised that -->
+<!--     users do not edit the contents of this file.              -->
+<!--                                                               -->
+<!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.    -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/spartan6_pll.v&quot; into library work</arg>
+</msg>
+
+</messages>
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/_xmsgs/xst.xmsgs b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/_xmsgs/xst.xmsgs
new file mode 100644
index 0000000..951ac45
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/_xmsgs/xst.xmsgs
@@ -0,0 +1,849 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="UtilitiesC" num="159" delta="old" >Message file &quot;<arg fmt="%s" index="1">usenglish/ip.msg</arg>&quot; wasn&apos;t found.
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">2</arg>x<arg fmt="%d" index="5">4096</arg> 	u:<arg fmt="%d" index="6">2</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">2</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">4</arg>x<arg fmt="%d" index="5">4096</arg> 	u:<arg fmt="%d" index="6">4</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">2</arg>: (<arg fmt="%d" index="2">6</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">4</arg>x<arg fmt="%d" index="5">4096</arg> 	u:<arg fmt="%d" index="6">4</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">3</arg>: (<arg fmt="%d" index="2">10</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">4</arg>x<arg fmt="%d" index="5">4096</arg> 	u:<arg fmt="%d" index="6">4</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">4</arg>: (<arg fmt="%d" index="2">14</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">9</arg>x<arg fmt="%d" index="5">2048</arg> 	u:<arg fmt="%d" index="6">9</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">5</arg>: (<arg fmt="%d" index="2">14</arg>,<arg fmt="%d" index="3">2048</arg>) 	: <arg fmt="%d" index="4">9</arg>x<arg fmt="%d" index="5">2048</arg> 	u:<arg fmt="%d" index="6">9</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">6</arg>: (<arg fmt="%d" index="2">23</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">9</arg>x<arg fmt="%d" index="5">2048</arg> 	u:<arg fmt="%d" index="6">9</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">7</arg>: (<arg fmt="%d" index="2">23</arg>,<arg fmt="%d" index="3">2048</arg>) 	: <arg fmt="%d" index="4">9</arg>x<arg fmt="%d" index="5">2048</arg> 	u:<arg fmt="%d" index="6">9</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">2</arg>x<arg fmt="%d" index="5">4096</arg> 	u:<arg fmt="%d" index="6">2</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">2</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">4</arg>x<arg fmt="%d" index="5">4096</arg> 	u:<arg fmt="%d" index="6">4</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">2</arg>: (<arg fmt="%d" index="2">6</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">4</arg>x<arg fmt="%d" index="5">4096</arg> 	u:<arg fmt="%d" index="6">4</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">3</arg>: (<arg fmt="%d" index="2">10</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">4</arg>x<arg fmt="%d" index="5">4096</arg> 	u:<arg fmt="%d" index="6">4</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">4</arg>: (<arg fmt="%d" index="2">14</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">9</arg>x<arg fmt="%d" index="5">2048</arg> 	u:<arg fmt="%d" index="6">9</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">5</arg>: (<arg fmt="%d" index="2">14</arg>,<arg fmt="%d" index="3">2048</arg>) 	: <arg fmt="%d" index="4">9</arg>x<arg fmt="%d" index="5">2048</arg> 	u:<arg fmt="%d" index="6">9</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">6</arg>: (<arg fmt="%d" index="2">23</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">9</arg>x<arg fmt="%d" index="5">2048</arg> 	u:<arg fmt="%d" index="6">9</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">7</arg>: (<arg fmt="%d" index="2">23</arg>,<arg fmt="%d" index="3">2048</arg>) 	: <arg fmt="%d" index="4">9</arg>x<arg fmt="%d" index="5">2048</arg> 	u:<arg fmt="%d" index="6">9</arg>
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="321" delta="new" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_input_block.vhd" Line 691: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="321" delta="new" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_input_block.vhd" Line 707: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="746" delta="old" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_prim_width.vhd" Line 978: Range is empty (null range)
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="220" delta="old" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_prim_width.vhd" Line 978: Assignment ignored
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="746" delta="old" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_prim_width.vhd" Line 979: Range is empty (null range)
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="220" delta="old" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_prim_width.vhd" Line 979: Assignment ignored
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%s" index="1">$Id: get_init_bmg_v7_3.c,v 1.3 2011/07/25 06:20:41 Exp $</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" >Reading MIF file at <arg fmt="%s" index="1">C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/EU4Kx32.mif</arg>
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_prim_wrapper_s6_init.vhd" Line 464: Net &lt;<arg fmt="%s" index="1">pad_addr_b13[12]</arg>&gt; does not have a driver.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_prim_wrapper_s6_init.vhd" Line 473: Net &lt;<arg fmt="%s" index="1">pad_din_b16[15]</arg>&gt; does not have a driver.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_prim_wrapper_s6_init.vhd" Line 476: Net &lt;<arg fmt="%s" index="1">pad_dinp_b2[1]</arg>&gt; does not have a driver.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_prim_wrapper_s6_init.vhd" Line 531: Net &lt;<arg fmt="%s" index="1">doutb_i[1]</arg>&gt; does not have a driver.
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%s" index="1">$Id: get_init_bmg_v7_3.c,v 1.3 2011/07/25 06:20:41 Exp $</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" >Reading MIF file at <arg fmt="%s" index="1">C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/EU4Kx32.mif</arg>
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_prim_wrapper_s6_init.vhd" Line 493: Net &lt;<arg fmt="%s" index="1">pad_addr_b14[13]</arg>&gt; does not have a driver.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_prim_wrapper_s6_init.vhd" Line 502: Net &lt;<arg fmt="%s" index="1">pad_din_b32[31]</arg>&gt; does not have a driver.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_prim_wrapper_s6_init.vhd" Line 505: Net &lt;<arg fmt="%s" index="1">pad_dinp_b4[3]</arg>&gt; does not have a driver.
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%s" index="1">$Id: get_init_bmg_v7_3.c,v 1.3 2011/07/25 06:20:41 Exp $</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" >Reading MIF file at <arg fmt="%s" index="1">C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/EU4Kx32.mif</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%s" index="1">$Id: get_init_bmg_v7_3.c,v 1.3 2011/07/25 06:20:41 Exp $</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" >Reading MIF file at <arg fmt="%s" index="1">C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/EU4Kx32.mif</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" >Reading MIF file at <arg fmt="%s" index="1">C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/EU4Kx32.mif</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%s" index="1">$Id: get_init_bmg_v7_3.c,v 1.3 2011/07/25 06:20:41 Exp $</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" >Reading MIF file at <arg fmt="%s" index="1">C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/EU4Kx32.mif</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" >Reading MIF file at <arg fmt="%s" index="1">C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/EU4Kx32.mif</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%s" index="1">$Id: get_init_bmg_v7_3.c,v 1.3 2011/07/25 06:20:41 Exp $</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" >Reading MIF file at <arg fmt="%s" index="1">C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/EU4Kx32.mif</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" >Reading MIF file at <arg fmt="%s" index="1">C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/EU4Kx32.mif</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%s" index="1">$Id: get_init_bmg_v7_3.c,v 1.3 2011/07/25 06:20:41 Exp $</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" >Reading MIF file at <arg fmt="%s" index="1">C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/EU4Kx32.mif</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" >Reading MIF file at <arg fmt="%s" index="1">C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/EU4Kx32.mif</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%s" index="1">$Id: get_init_bmg_v7_3.c,v 1.3 2011/07/25 06:20:41 Exp $</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" >Reading MIF file at <arg fmt="%s" index="1">C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/EU4Kx32.mif</arg>
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="321" delta="new" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd" Line 1546: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="321" delta="new" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd" Line 1559: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="321" delta="new" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_mux.vhd" Line 459: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="321" delta="new" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_mux.vhd" Line 470: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="321" delta="new" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_mux.vhd" Line 472: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="321" delta="new" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_mux.vhd" Line 872: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd" Line 447: Net &lt;<arg fmt="%s" index="1">sbiterr_array[31]</arg>&gt; does not have a driver.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd" Line 448: Net &lt;<arg fmt="%s" index="1">dbiterr_array[31]</arg>&gt; does not have a driver.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\EU4Kx32.vhd</arg>&quot; line <arg fmt="%s" index="2">147</arg>: Output port &lt;<arg fmt="%s" index="3">doutb</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\EU4Kx32.vhd</arg>&quot; line <arg fmt="%s" index="2">147</arg>: Output port &lt;<arg fmt="%s" index="3">rdaddrecc</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\EU4Kx32.vhd</arg>&quot; line <arg fmt="%s" index="2">147</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\EU4Kx32.vhd</arg>&quot; line <arg fmt="%s" index="2">147</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bresp</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\EU4Kx32.vhd</arg>&quot; line <arg fmt="%s" index="2">147</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\EU4Kx32.vhd</arg>&quot; line <arg fmt="%s" index="2">147</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rdata</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\EU4Kx32.vhd</arg>&quot; line <arg fmt="%s" index="2">147</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rresp</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\EU4Kx32.vhd</arg>&quot; line <arg fmt="%s" index="2">147</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rdaddrecc</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\EU4Kx32.vhd</arg>&quot; line <arg fmt="%s" index="2">147</arg>: Output port &lt;<arg fmt="%s" index="3">sbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\EU4Kx32.vhd</arg>&quot; line <arg fmt="%s" index="2">147</arg>: Output port &lt;<arg fmt="%s" index="3">dbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\EU4Kx32.vhd</arg>&quot; line <arg fmt="%s" index="2">147</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_awready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\EU4Kx32.vhd</arg>&quot; line <arg fmt="%s" index="2">147</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_wready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\EU4Kx32.vhd</arg>&quot; line <arg fmt="%s" index="2">147</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bvalid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\EU4Kx32.vhd</arg>&quot; line <arg fmt="%s" index="2">147</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_arready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\EU4Kx32.vhd</arg>&quot; line <arg fmt="%s" index="2">147</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rlast</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\EU4Kx32.vhd</arg>&quot; line <arg fmt="%s" index="2">147</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rvalid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\EU4Kx32.vhd</arg>&quot; line <arg fmt="%s" index="2">147</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_sbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\EU4Kx32.vhd</arg>&quot; line <arg fmt="%s" index="2">147</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_dbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWID</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWADDR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWLEN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWSIZE</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWBURST</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_WDATA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_WSTRB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARID</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARADDR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARLEN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARSIZE</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARBURST</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AClk</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_ARESETN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWVALID</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_WLAST</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_WVALID</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_BREADY</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARVALID</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_RREADY</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="old" >Signal &apos;<arg fmt="%s" index="1">S_AXI_BID</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_v7_3_xst</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_BRESP</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="old" >Signal &apos;<arg fmt="%s" index="1">S_AXI_RID</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_v7_3_xst</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RDATA</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RRESP</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RDADDRECC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_AWREADY</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_WREADY</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_BVALID</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_ARREADY</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RLAST</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RVALID</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DINA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ADDRB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DINB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RSTA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ENA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">CLKB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RSTB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ENB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">INJECTDBITERR_I</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">INJECTSBITERR_I</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1342</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[0].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1342</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[0].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1342</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[1].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1342</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[1].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1342</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[2].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1342</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[2].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1342</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[3].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1342</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[3].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1342</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[4].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1342</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[4].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1342</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[5].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1342</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[5].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1342</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[6].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1342</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[6].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1342</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[7].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1342</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[7].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1606</arg>: Output port &lt;<arg fmt="%s" index="3">RDADDRECC</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">has_mux_a.A</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1606</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">has_mux_a.A</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1606</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">has_mux_a.A</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1750</arg>: Output port &lt;<arg fmt="%s" index="3">RDADDRECC</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">has_mux_b.B</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1750</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">has_mux_b.B</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\MCL\MCL86\MCL86jr\MCL86jr\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v7_3\blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1750</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">has_mux_b.B</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">RDADDRECC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">sbiterr_array</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_generic_cstr</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00000000000000000000000000000000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">dbiterr_array</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_generic_cstr</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00000000000000000000000000000000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ADDRB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DINB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ENB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">pad_addr_b13</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">pad_din_b16</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_1</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000000000000000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">pad_dinp_b2</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_1</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">doutb_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_1</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ADDRB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DINB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ENB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">pad_addr_b14</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">pad_din_b32</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_2</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00000000000000000000000000000000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">pad_dinp_b4</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_2</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">doutb_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_2</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ADDRB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DINB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ENB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">pad_addr_b14</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">pad_din_b32</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_3</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00000000000000000000000000000000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">pad_dinp_b4</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_3</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">doutb_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_3</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ADDRB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DINB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ENB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">pad_addr_b14</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">pad_din_b32</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_4</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00000000000000000000000000000000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">pad_dinp_b4</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_4</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">doutb_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_4</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ADDRB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DINB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ENB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">pad_addr_b14</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">pad_din_b32</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_5</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00000000000000000000000000000000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">pad_dinp_b4</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_5</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">doutb_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_5</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">000000000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ADDRB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DINB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ENB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">pad_addr_b14</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">pad_din_b32</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_6</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00000000000000000000000000000000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">pad_dinp_b4</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_6</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">doutb_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_6</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">000000000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ADDRB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DINB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ENB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">pad_addr_b14</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">pad_din_b32</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_7</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00000000000000000000000000000000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">pad_dinp_b4</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_7</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">doutb_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_7</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">000000000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ADDRB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DINB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ENB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">pad_addr_b14</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">pad_din_b32</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_8</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00000000000000000000000000000000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">pad_dinp_b4</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_8</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">doutb_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_init_8</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">000000000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">MUX_RST</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">MUX_REGCE</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">ADDR_IN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">SBITERRIN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DBITERRIN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">MEM_LAT_RST</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">MEM_REG_RST</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">MEM_REGCE</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">WE</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DOUTB_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RDADDRECC_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">CLKB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">SBITERR_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DBITERR_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">RDADDRECC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">has_mux_b.B/sel_pipe_0</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">blk_mem_gen_generic_cstr</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
+</msg>
+
+<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
+</msg>
+
+</messages>
+
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.0556430854162.out b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.0556430854162.out
new file mode 100644
index 0000000..156d885
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.0556430854162.out
@@ -0,0 +1,505 @@
+SET_FLAG DEBUG FALSE
+SET_FLAG MODE BATCH
+SET_FLAG STANDALONE_MODE FALSE
+SET_PREFERENCE devicefamily spartan6
+SET_PREFERENCE device xc6slx9
+SET_PREFERENCE speedgrade -3
+SET_PREFERENCE package tqg144
+SET_PREFERENCE verilogsim true
+SET_PREFERENCE vhdlsim false
+SET_PREFERENCE simulationfiles Behavioral
+SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
+SET_PREFERENCE outputdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/
+SET_PREFERENCE workingdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/
+SET_PREFERENCE subworkingdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/
+SET_PREFERENCE transientdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/_dbg/
+SET_PREFERENCE designentry Verilog
+SET_PREFERENCE flowvendor Other
+SET_PREFERENCE addpads false
+SET_PREFERENCE projectname coregen
+SET_PREFERENCE formalverification false
+SET_PREFERENCE asysymbol false
+SET_PREFERENCE implementationfiletype Ngc
+SET_PREFERENCE foundationsym false
+SET_PREFERENCE createndf false
+SET_PREFERENCE removerpms false
+SET_PARAMETER Component_Name spartan6_pll
+SET_PARAMETER Use_Freq_Synth true
+SET_PARAMETER Use_Phase_Alignment false
+SET_PARAMETER Use_Min_Power false
+SET_PARAMETER Use_Dyn_Phase_Shift false
+SET_PARAMETER Use_Dyn_Reconfig false
+SET_PARAMETER Jitter_Sel No_Jitter
+SET_PARAMETER Use_Spread_Spectrum false
+SET_PARAMETER Use_Spread_Spectrum_1 false
+SET_PARAMETER Prim_In_Freq 50.000
+SET_PARAMETER In_Freq_Units Units_MHz
+SET_PARAMETER In_Jitter_Units Units_UI
+SET_PARAMETER Relative_Inclk REL_PRIMARY
+SET_PARAMETER Secondary_In_Freq 100.000
+SET_PARAMETER Jitter_Options UI
+SET_PARAMETER Clkin1_UI_Jitter 0.010
+SET_PARAMETER Clkin2_UI_Jitter 0.010
+SET_PARAMETER Prim_In_Jitter 0.010
+SET_PARAMETER Secondary_In_Jitter 0.010
+SET_PARAMETER Clkin1_Jitter_Ps 200.0
+SET_PARAMETER Clkin2_Jitter_Ps 100.0
+SET_PARAMETER Clkout2_Used false
+SET_PARAMETER Clkout3_Used false
+SET_PARAMETER Clkout4_Used false
+SET_PARAMETER Clkout5_Used false
+SET_PARAMETER Clkout6_Used false
+SET_PARAMETER Clkout7_Used false
+SET_PARAMETER Num_Out_Clks 1
+SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
+SET_PARAMETER primary_port CLK_IN1
+SET_PARAMETER CLK_OUT1_port CLK_OUT1
+SET_PARAMETER CLK_OUT2_port CLK_OUT2
+SET_PARAMETER CLK_OUT3_port CLK_OUT3
+SET_PARAMETER CLK_OUT4_port CLK_OUT4
+SET_PARAMETER CLK_OUT5_port CLK_OUT5
+SET_PARAMETER CLK_OUT6_port CLK_OUT6
+SET_PARAMETER CLK_OUT7_port CLK_OUT7
+SET_PARAMETER DADDR_port DADDR
+SET_PARAMETER DCLK_port DCLK
+SET_PARAMETER DRDY_port DRDY
+SET_PARAMETER DWE_port DWE
+SET_PARAMETER DIN_port DIN
+SET_PARAMETER DOUT_port DOUT
+SET_PARAMETER DEN_port DEN
+SET_PARAMETER PSCLK_port PSCLK
+SET_PARAMETER PSEN_port PSEN
+SET_PARAMETER PSINCDEC_port PSINCDEC
+SET_PARAMETER PSDONE_port PSDONE
+SET_PARAMETER Clkout1_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout1_Requested_Phase 0.000
+SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout2_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout2_Requested_Phase 0.000
+SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout3_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout3_Requested_Phase 0.000
+SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout4_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout4_Requested_Phase 0.000
+SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout5_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout5_Requested_Phase 0.000
+SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout6_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout6_Requested_Phase 0.000
+SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout7_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout7_Requested_Phase 0.000
+SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.000
+SET_PARAMETER Use_Max_I_Jitter false
+SET_PARAMETER Use_Min_O_Jitter false
+SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
+SET_PARAMETER Use_Inclk_Switchover false
+SET_PARAMETER secondary_port CLK_IN2
+SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
+SET_PARAMETER Clkout1_Drives BUFG
+SET_PARAMETER Clkout2_Drives BUFG
+SET_PARAMETER Clkout3_Drives BUFG
+SET_PARAMETER Clkout4_Drives BUFG
+SET_PARAMETER Clkout5_Drives BUFG
+SET_PARAMETER Clkout6_Drives BUFG
+SET_PARAMETER Clkout7_Drives BUFG
+SET_PARAMETER Feedback_Source FDBK_AUTO
+SET_PARAMETER Clkfb_In_Signaling SINGLE
+SET_PARAMETER CLKFB_IN_port CLKFB_IN
+SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
+SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
+SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
+SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
+SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
+SET_PARAMETER Platform nt64
+SET_PARAMETER Summary_Strings empty
+SET_PARAMETER Use_Locked false
+SET_PARAMETER calc_done DONE
+SET_PARAMETER Use_Reset false
+SET_PARAMETER Use_Power_Down false
+SET_PARAMETER Use_Status false
+SET_PARAMETER Use_Freeze false
+SET_PARAMETER Use_Clk_Valid false
+SET_PARAMETER Use_Inclk_Stopped false
+SET_PARAMETER Use_Clkfb_Stopped false
+SET_PARAMETER RESET_port RESET
+SET_PARAMETER LOCKED_port LOCKED
+SET_PARAMETER Power_Down_port POWER_DOWN
+SET_PARAMETER CLK_VALID_port CLK_VALID
+SET_PARAMETER STATUS_port STATUS
+SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
+SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
+SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
+SET_PARAMETER Override_Mmcm false
+SET_PARAMETER Mmcm_Notes None
+SET_PARAMETER Mmcm_Divclk_Divide 1
+SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
+SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
+SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
+SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkin1_Period 10.000
+SET_PARAMETER Mmcm_Clkin2_Period 10.000
+SET_PARAMETER Mmcm_Clkout4_Cascade false
+SET_PARAMETER Mmcm_Clock_Hold false
+SET_PARAMETER Mmcm_Compensation ZHOLD
+SET_PARAMETER Mmcm_Ref_Jitter1 0.010
+SET_PARAMETER Mmcm_Ref_Jitter2 0.010
+SET_PARAMETER Mmcm_Startup_Wait false
+SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
+SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout0_Phase 0.000
+SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout1_Divide 1
+SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout1_Phase 0.000
+SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout2_Divide 1
+SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout2_Phase 0.000
+SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout3_Divide 1
+SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout3_Phase 0.000
+SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout4_Divide 1
+SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout4_Phase 0.000
+SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout5_Divide 1
+SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout5_Phase 0.000
+SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout6_Divide 1
+SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout6_Phase 0.000
+SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
+SET_PARAMETER Override_Dcm false
+SET_PARAMETER Dcm_Notes None
+SET_PARAMETER Dcm_Clkdv_Divide 2.0
+SET_PARAMETER Dcm_Clkfx_Divide 1
+SET_PARAMETER Dcm_Clkfx_Multiply 2
+SET_PARAMETER Dcm_Clkin_Divide_By_2 false
+SET_PARAMETER Dcm_Clkin_Period 20.000
+SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
+SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
+SET_PARAMETER Dcm_Phase_Shift 0
+SET_PARAMETER Dcm_Clk_Feedback NONE
+SET_PARAMETER Dcm_Startup_Wait false
+SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
+SET_PARAMETER Dcm_Clk_Out2_Port CLKFX
+SET_PARAMETER Dcm_Clk_Out3_Port CLK0
+SET_PARAMETER Dcm_Clk_Out4_Port CLK0
+SET_PARAMETER Dcm_Clk_Out5_Port CLK0
+SET_PARAMETER Dcm_Clk_Out6_Port CLK0
+SET_PARAMETER Override_Dcm_Clkgen false
+SET_PARAMETER Dcm_Clkgen_Notes None
+SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 1
+SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 4
+SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
+SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
+SET_PARAMETER Dcm_Clkgen_Startup_Wait false
+SET_PARAMETER Dcm_Clkgen_Clkin_Period 10.000
+SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
+SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
+SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
+SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX
+SET_PARAMETER Override_Pll false
+SET_PARAMETER Pll_Notes None
+SET_PARAMETER Pll_Bandwidth OPTIMIZED
+SET_PARAMETER Pll_Clkfbout_Mult 15
+SET_PARAMETER Pll_Clkfbout_Phase 0.000
+SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
+SET_PARAMETER Pll_Divclk_Divide 1
+SET_PARAMETER Pll_Clkin_Period 20.000
+SET_PARAMETER Pll_Compensation INTERNAL
+SET_PARAMETER Pll_Ref_Jitter 0.010
+SET_PARAMETER Pll_Clkout0_Divide 7
+SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout0_Phase 0.000
+SET_PARAMETER Pll_Clkout1_Divide 40
+SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout1_Phase 0.000
+SET_PARAMETER Pll_Clkout2_Divide 1
+SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout2_Phase 0.000
+SET_PARAMETER Pll_Clkout3_Divide 1
+SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout3_Phase 0.000
+SET_PARAMETER Pll_Clkout4_Divide 1
+SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout4_Phase 0.000
+SET_PARAMETER Pll_Clkout5_Divide 1
+SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout5_Phase 0.000
+SET_PARAMETER dcm_pll_cascade NONE
+SET_PARAMETER clock_mgr_type AUTO
+SET_PARAMETER primtype_sel PLL_BASE
+SET_PARAMETER primitive MMCM
+SET_PARAMETER SS_Mode CENTER_HIGH
+SET_PARAMETER SS_Mod_Freq 250
+SET_SIM_PARAMETER c_clkout2_used 0
+SET_SIM_PARAMETER c_clkout3_used 0
+SET_SIM_PARAMETER c_clkout4_used 0
+SET_SIM_PARAMETER c_clkout5_used 0
+SET_SIM_PARAMETER c_clkout6_used 0
+SET_SIM_PARAMETER c_clkout7_used 0
+SET_SIM_PARAMETER c_use_clkout1_bar 0
+SET_SIM_PARAMETER c_use_clkout2_bar 0
+SET_SIM_PARAMETER c_use_clkout3_bar 0
+SET_SIM_PARAMETER c_use_clkout4_bar 0
+SET_SIM_PARAMETER c_component_name spartan6_pll
+SET_SIM_PARAMETER c_platform nt64
+SET_SIM_PARAMETER c_use_freq_synth 1
+SET_SIM_PARAMETER c_use_phase_alignment 0
+SET_SIM_PARAMETER c_prim_in_jitter 0.010
+SET_SIM_PARAMETER c_secondary_in_jitter 0.010
+SET_SIM_PARAMETER c_jitter_sel No_Jitter
+SET_SIM_PARAMETER c_use_min_power 0
+SET_SIM_PARAMETER c_use_min_o_jitter 0
+SET_SIM_PARAMETER c_use_max_i_jitter 0
+SET_SIM_PARAMETER c_use_dyn_phase_shift 0
+SET_SIM_PARAMETER c_use_inclk_switchover 0
+SET_SIM_PARAMETER c_use_dyn_reconfig 0
+SET_SIM_PARAMETER c_use_spread_spectrum 0
+SET_SIM_PARAMETER c_use_spread_spectrum_1 0
+SET_SIM_PARAMETER c_primtype_sel DCM_SP
+SET_SIM_PARAMETER c_use_clk_valid 0
+SET_SIM_PARAMETER c_prim_in_freq 50.000
+SET_SIM_PARAMETER c_in_freq_units Units_MHz
+SET_SIM_PARAMETER c_secondary_in_freq 100.000
+SET_SIM_PARAMETER c_feedback_source FDBK_AUTO
+SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
+SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
+SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
+SET_SIM_PARAMETER c_use_reset 0
+SET_SIM_PARAMETER c_use_locked 0
+SET_SIM_PARAMETER c_use_inclk_stopped 0
+SET_SIM_PARAMETER c_use_clkfb_stopped 0
+SET_SIM_PARAMETER c_use_power_down 0
+SET_SIM_PARAMETER c_use_status 0
+SET_SIM_PARAMETER c_use_freeze 0
+SET_SIM_PARAMETER c_num_out_clks 1
+SET_SIM_PARAMETER c_clkout1_drives BUFG
+SET_SIM_PARAMETER c_clkout2_drives BUFG
+SET_SIM_PARAMETER c_clkout3_drives BUFG
+SET_SIM_PARAMETER c_clkout4_drives BUFG
+SET_SIM_PARAMETER c_clkout5_drives BUFG
+SET_SIM_PARAMETER c_clkout6_drives BUFG
+SET_SIM_PARAMETER c_clkout7_drives BUFG
+SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock   Freq (MHz)    Input Jitter (UI)"
+SET_SIM_PARAMETER c_inclk_sum_row1 __primary__________50.000____________0.010
+SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock 
+SET_SIM_PARAMETER c_outclk_sum_row0a "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+SET_SIM_PARAMETER c_outclk_sum_row0b "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1___100.000______0.000______50.0______400.000____150.000
+SET_SIM_PARAMETER c_outclk_sum_row2 no_CLK_OUT2_output
+SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output 
+SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
+SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
+SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
+SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output 
+SET_SIM_PARAMETER c_clkout1_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout2_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout3_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout4_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout5_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout6_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout7_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout2_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout3_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout4_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout1_out_freq 100.000
+SET_SIM_PARAMETER c_clkout2_out_freq N/A
+SET_SIM_PARAMETER c_clkout3_out_freq N/A
+SET_SIM_PARAMETER c_clkout4_out_freq N/A
+SET_SIM_PARAMETER c_clkout5_out_freq N/A
+SET_SIM_PARAMETER c_clkout6_out_freq N/A
+SET_SIM_PARAMETER c_clkout7_out_freq N/A
+SET_SIM_PARAMETER c_clkout1_phase 0.000
+SET_SIM_PARAMETER c_clkout2_phase N/A
+SET_SIM_PARAMETER c_clkout3_phase N/A
+SET_SIM_PARAMETER c_clkout4_phase N/A
+SET_SIM_PARAMETER c_clkout5_phase N/A
+SET_SIM_PARAMETER c_clkout6_phase N/A
+SET_SIM_PARAMETER c_clkout7_phase N/A
+SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
+SET_SIM_PARAMETER c_clkout2_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout3_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
+SET_SIM_PARAMETER c_mmcm_notes None
+SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
+SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
+SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
+SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
+SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
+SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
+SET_SIM_PARAMETER c_mmcm_divclk_divide 1
+SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
+SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
+SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
+SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
+SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
+SET_SIM_PARAMETER c_pll_notes None
+SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
+SET_SIM_PARAMETER c_pll_clkfbout_mult 15
+SET_SIM_PARAMETER c_pll_clkin_period 20.000
+SET_SIM_PARAMETER c_pll_compensation INTERNAL
+SET_SIM_PARAMETER c_pll_divclk_divide 1
+SET_SIM_PARAMETER c_pll_ref_jitter 0.010
+SET_SIM_PARAMETER c_pll_clkout0_divide 7
+SET_SIM_PARAMETER c_pll_clkout1_divide 40
+SET_SIM_PARAMETER c_pll_clkout2_divide 1
+SET_SIM_PARAMETER c_pll_clkout3_divide 1
+SET_SIM_PARAMETER c_pll_clkout4_divide 1
+SET_SIM_PARAMETER c_pll_clkout5_divide 1
+SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout2_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
+SET_SIM_PARAMETER c_dcm_notes None
+SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
+SET_SIM_PARAMETER c_dcm_clkfx_divide 1
+SET_SIM_PARAMETER c_dcm_clkfx_multiply 2
+SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
+SET_SIM_PARAMETER c_dcm_clkin_period 20.0
+SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
+SET_SIM_PARAMETER c_dcm_clk_feedback NONE
+SET_SIM_PARAMETER c_dcm_clk_feedback_port NONE
+SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
+SET_SIM_PARAMETER c_dcm_phase_shift 0
+SET_SIM_PARAMETER c_dcm_startup_wait FALSE
+SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
+SET_SIM_PARAMETER c_dcm_clk_out2_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out3_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
+SET_SIM_PARAMETER c_dcm_clkgen_notes None
+SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 1
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 4
+SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 20.0
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
+SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
+SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port NONE
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE
+SET_SIM_PARAMETER c_clock_mgr_type AUTO
+SET_SIM_PARAMETER c_override_mmcm 0
+SET_SIM_PARAMETER c_override_pll 0
+SET_SIM_PARAMETER c_override_dcm 0
+SET_SIM_PARAMETER c_override_dcm_clkgen 0
+SET_SIM_PARAMETER c_dcm_pll_cascade NONE
+SET_SIM_PARAMETER c_primary_port CLK_IN1
+SET_SIM_PARAMETER c_secondary_port CLK_IN2
+SET_SIM_PARAMETER c_clk_out1_port CLK_OUT1
+SET_SIM_PARAMETER c_clk_out2_port CLK_OUT2
+SET_SIM_PARAMETER c_clk_out3_port CLK_OUT3
+SET_SIM_PARAMETER c_clk_out4_port CLK_OUT4
+SET_SIM_PARAMETER c_clk_out5_port CLK_OUT5
+SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
+SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
+SET_SIM_PARAMETER c_reset_port RESET
+SET_SIM_PARAMETER c_locked_port LOCKED
+SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
+SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
+SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
+SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
+SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
+SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
+SET_SIM_PARAMETER c_power_down_port POWER_DOWN
+SET_SIM_PARAMETER c_daddr_port DADDR
+SET_SIM_PARAMETER c_dclk_port DCLK
+SET_SIM_PARAMETER c_drdy_port DRDY
+SET_SIM_PARAMETER c_dwe_port DWE
+SET_SIM_PARAMETER c_din_port DIN
+SET_SIM_PARAMETER c_dout_port DOUT
+SET_SIM_PARAMETER c_den_port DEN
+SET_SIM_PARAMETER c_psclk_port PSCLK
+SET_SIM_PARAMETER c_psen_port PSEN
+SET_SIM_PARAMETER c_psincdec_port PSINCDEC
+SET_SIM_PARAMETER c_psdone_port PSDONE
+SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
+SET_SIM_PARAMETER c_status_port STATUS
+SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
+SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
+SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
+SET_SIM_PARAMETER c_clkin1_jitter_ps 200.0
+SET_SIM_PARAMETER c_clkin2_jitter_ps 100.0
+SET_SIM_PARAMETER c_primitive MMCM
+SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
+SET_SIM_PARAMETER c_ss_mod_period 4000
+SET_CORE_NAME Clocking Wizard
+SET_CORE_VERSION 3.6
+SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
+SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
+SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
+SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
+SET_CORE_DATASHEET C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.136417835083.out b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.136417835083.out
new file mode 100644
index 0000000..a997e23
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.136417835083.out
@@ -0,0 +1,505 @@
+SET_FLAG DEBUG FALSE
+SET_FLAG MODE BATCH
+SET_FLAG STANDALONE_MODE FALSE
+SET_PREFERENCE devicefamily spartan6
+SET_PREFERENCE device xc6slx9
+SET_PREFERENCE speedgrade -3
+SET_PREFERENCE package tqg144
+SET_PREFERENCE verilogsim true
+SET_PREFERENCE vhdlsim false
+SET_PREFERENCE simulationfiles Behavioral
+SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
+SET_PREFERENCE outputdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/
+SET_PREFERENCE workingdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/
+SET_PREFERENCE subworkingdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/
+SET_PREFERENCE transientdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/_dbg/
+SET_PREFERENCE designentry Verilog
+SET_PREFERENCE flowvendor Other
+SET_PREFERENCE addpads false
+SET_PREFERENCE projectname coregen
+SET_PREFERENCE formalverification false
+SET_PREFERENCE asysymbol false
+SET_PREFERENCE implementationfiletype Ngc
+SET_PREFERENCE foundationsym false
+SET_PREFERENCE createndf false
+SET_PREFERENCE removerpms false
+SET_PARAMETER Component_Name spartan6_pll
+SET_PARAMETER Use_Freq_Synth true
+SET_PARAMETER Use_Phase_Alignment false
+SET_PARAMETER Use_Min_Power false
+SET_PARAMETER Use_Dyn_Phase_Shift false
+SET_PARAMETER Use_Dyn_Reconfig false
+SET_PARAMETER Jitter_Sel No_Jitter
+SET_PARAMETER Use_Spread_Spectrum false
+SET_PARAMETER Use_Spread_Spectrum_1 false
+SET_PARAMETER Prim_In_Freq 50.000
+SET_PARAMETER In_Freq_Units Units_MHz
+SET_PARAMETER In_Jitter_Units Units_UI
+SET_PARAMETER Relative_Inclk REL_PRIMARY
+SET_PARAMETER Secondary_In_Freq 100.000
+SET_PARAMETER Jitter_Options UI
+SET_PARAMETER Clkin1_UI_Jitter 0.010
+SET_PARAMETER Clkin2_UI_Jitter 0.010
+SET_PARAMETER Prim_In_Jitter 0.010
+SET_PARAMETER Secondary_In_Jitter 0.010
+SET_PARAMETER Clkin1_Jitter_Ps 200.0
+SET_PARAMETER Clkin2_Jitter_Ps 100.0
+SET_PARAMETER Clkout2_Used false
+SET_PARAMETER Clkout3_Used false
+SET_PARAMETER Clkout4_Used false
+SET_PARAMETER Clkout5_Used false
+SET_PARAMETER Clkout6_Used false
+SET_PARAMETER Clkout7_Used false
+SET_PARAMETER Num_Out_Clks 1
+SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
+SET_PARAMETER primary_port CLK_IN1
+SET_PARAMETER CLK_OUT1_port CLK_OUT1
+SET_PARAMETER CLK_OUT2_port CLK_OUT2
+SET_PARAMETER CLK_OUT3_port CLK_OUT3
+SET_PARAMETER CLK_OUT4_port CLK_OUT4
+SET_PARAMETER CLK_OUT5_port CLK_OUT5
+SET_PARAMETER CLK_OUT6_port CLK_OUT6
+SET_PARAMETER CLK_OUT7_port CLK_OUT7
+SET_PARAMETER DADDR_port DADDR
+SET_PARAMETER DCLK_port DCLK
+SET_PARAMETER DRDY_port DRDY
+SET_PARAMETER DWE_port DWE
+SET_PARAMETER DIN_port DIN
+SET_PARAMETER DOUT_port DOUT
+SET_PARAMETER DEN_port DEN
+SET_PARAMETER PSCLK_port PSCLK
+SET_PARAMETER PSEN_port PSEN
+SET_PARAMETER PSINCDEC_port PSINCDEC
+SET_PARAMETER PSDONE_port PSDONE
+SET_PARAMETER Clkout1_Requested_Out_Freq 110.000
+SET_PARAMETER Clkout1_Requested_Phase 0.000
+SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout2_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout2_Requested_Phase 0.000
+SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout3_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout3_Requested_Phase 0.000
+SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout4_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout4_Requested_Phase 0.000
+SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout5_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout5_Requested_Phase 0.000
+SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout6_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout6_Requested_Phase 0.000
+SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout7_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout7_Requested_Phase 0.000
+SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.000
+SET_PARAMETER Use_Max_I_Jitter false
+SET_PARAMETER Use_Min_O_Jitter false
+SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
+SET_PARAMETER Use_Inclk_Switchover false
+SET_PARAMETER secondary_port CLK_IN2
+SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
+SET_PARAMETER Clkout1_Drives BUFG
+SET_PARAMETER Clkout2_Drives BUFG
+SET_PARAMETER Clkout3_Drives BUFG
+SET_PARAMETER Clkout4_Drives BUFG
+SET_PARAMETER Clkout5_Drives BUFG
+SET_PARAMETER Clkout6_Drives BUFG
+SET_PARAMETER Clkout7_Drives BUFG
+SET_PARAMETER Feedback_Source FDBK_AUTO
+SET_PARAMETER Clkfb_In_Signaling SINGLE
+SET_PARAMETER CLKFB_IN_port CLKFB_IN
+SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
+SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
+SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
+SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
+SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
+SET_PARAMETER Platform nt64
+SET_PARAMETER Summary_Strings empty
+SET_PARAMETER Use_Locked false
+SET_PARAMETER calc_done DONE
+SET_PARAMETER Use_Reset false
+SET_PARAMETER Use_Power_Down false
+SET_PARAMETER Use_Status false
+SET_PARAMETER Use_Freeze false
+SET_PARAMETER Use_Clk_Valid false
+SET_PARAMETER Use_Inclk_Stopped false
+SET_PARAMETER Use_Clkfb_Stopped false
+SET_PARAMETER RESET_port RESET
+SET_PARAMETER LOCKED_port LOCKED
+SET_PARAMETER Power_Down_port POWER_DOWN
+SET_PARAMETER CLK_VALID_port CLK_VALID
+SET_PARAMETER STATUS_port STATUS
+SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
+SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
+SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
+SET_PARAMETER Override_Mmcm false
+SET_PARAMETER Mmcm_Notes None
+SET_PARAMETER Mmcm_Divclk_Divide 1
+SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
+SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
+SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
+SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkin1_Period 10.000
+SET_PARAMETER Mmcm_Clkin2_Period 10.000
+SET_PARAMETER Mmcm_Clkout4_Cascade false
+SET_PARAMETER Mmcm_Clock_Hold false
+SET_PARAMETER Mmcm_Compensation ZHOLD
+SET_PARAMETER Mmcm_Ref_Jitter1 0.010
+SET_PARAMETER Mmcm_Ref_Jitter2 0.010
+SET_PARAMETER Mmcm_Startup_Wait false
+SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
+SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout0_Phase 0.000
+SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout1_Divide 1
+SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout1_Phase 0.000
+SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout2_Divide 1
+SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout2_Phase 0.000
+SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout3_Divide 1
+SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout3_Phase 0.000
+SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout4_Divide 1
+SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout4_Phase 0.000
+SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout5_Divide 1
+SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout5_Phase 0.000
+SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout6_Divide 1
+SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout6_Phase 0.000
+SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
+SET_PARAMETER Override_Dcm false
+SET_PARAMETER Dcm_Notes None
+SET_PARAMETER Dcm_Clkdv_Divide 2.0
+SET_PARAMETER Dcm_Clkfx_Divide 5
+SET_PARAMETER Dcm_Clkfx_Multiply 11
+SET_PARAMETER Dcm_Clkin_Divide_By_2 false
+SET_PARAMETER Dcm_Clkin_Period 20.000
+SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
+SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
+SET_PARAMETER Dcm_Phase_Shift 0
+SET_PARAMETER Dcm_Clk_Feedback NONE
+SET_PARAMETER Dcm_Startup_Wait false
+SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
+SET_PARAMETER Dcm_Clk_Out2_Port CLKFX
+SET_PARAMETER Dcm_Clk_Out3_Port CLK0
+SET_PARAMETER Dcm_Clk_Out4_Port CLK0
+SET_PARAMETER Dcm_Clk_Out5_Port CLK0
+SET_PARAMETER Dcm_Clk_Out6_Port CLK0
+SET_PARAMETER Override_Dcm_Clkgen false
+SET_PARAMETER Dcm_Clkgen_Notes None
+SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 1
+SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 4
+SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
+SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
+SET_PARAMETER Dcm_Clkgen_Startup_Wait false
+SET_PARAMETER Dcm_Clkgen_Clkin_Period 10.000
+SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
+SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
+SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
+SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX
+SET_PARAMETER Override_Pll false
+SET_PARAMETER Pll_Notes None
+SET_PARAMETER Pll_Bandwidth OPTIMIZED
+SET_PARAMETER Pll_Clkfbout_Mult 8
+SET_PARAMETER Pll_Clkfbout_Phase 0.000
+SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
+SET_PARAMETER Pll_Divclk_Divide 1
+SET_PARAMETER Pll_Clkin_Period 20.0
+SET_PARAMETER Pll_Compensation INTERNAL
+SET_PARAMETER Pll_Ref_Jitter 0.010
+SET_PARAMETER Pll_Clkout0_Divide 128
+SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout0_Phase 0.000
+SET_PARAMETER Pll_Clkout1_Divide 40
+SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout1_Phase 0.000
+SET_PARAMETER Pll_Clkout2_Divide 1
+SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout2_Phase 0.000
+SET_PARAMETER Pll_Clkout3_Divide 1
+SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout3_Phase 0.000
+SET_PARAMETER Pll_Clkout4_Divide 1
+SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout4_Phase 0.000
+SET_PARAMETER Pll_Clkout5_Divide 1
+SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout5_Phase 0.000
+SET_PARAMETER dcm_pll_cascade NONE
+SET_PARAMETER clock_mgr_type AUTO
+SET_PARAMETER primtype_sel PLL_BASE
+SET_PARAMETER primitive MMCM
+SET_PARAMETER SS_Mode CENTER_HIGH
+SET_PARAMETER SS_Mod_Freq 250
+SET_SIM_PARAMETER c_clkout2_used 0
+SET_SIM_PARAMETER c_clkout3_used 0
+SET_SIM_PARAMETER c_clkout4_used 0
+SET_SIM_PARAMETER c_clkout5_used 0
+SET_SIM_PARAMETER c_clkout6_used 0
+SET_SIM_PARAMETER c_clkout7_used 0
+SET_SIM_PARAMETER c_use_clkout1_bar 0
+SET_SIM_PARAMETER c_use_clkout2_bar 0
+SET_SIM_PARAMETER c_use_clkout3_bar 0
+SET_SIM_PARAMETER c_use_clkout4_bar 0
+SET_SIM_PARAMETER c_component_name spartan6_pll
+SET_SIM_PARAMETER c_platform nt64
+SET_SIM_PARAMETER c_use_freq_synth 1
+SET_SIM_PARAMETER c_use_phase_alignment 0
+SET_SIM_PARAMETER c_prim_in_jitter 0.010
+SET_SIM_PARAMETER c_secondary_in_jitter 0.010
+SET_SIM_PARAMETER c_jitter_sel No_Jitter
+SET_SIM_PARAMETER c_use_min_power 0
+SET_SIM_PARAMETER c_use_min_o_jitter 0
+SET_SIM_PARAMETER c_use_max_i_jitter 0
+SET_SIM_PARAMETER c_use_dyn_phase_shift 0
+SET_SIM_PARAMETER c_use_inclk_switchover 0
+SET_SIM_PARAMETER c_use_dyn_reconfig 0
+SET_SIM_PARAMETER c_use_spread_spectrum 0
+SET_SIM_PARAMETER c_use_spread_spectrum_1 0
+SET_SIM_PARAMETER c_primtype_sel DCM_SP
+SET_SIM_PARAMETER c_use_clk_valid 0
+SET_SIM_PARAMETER c_prim_in_freq 50.000
+SET_SIM_PARAMETER c_in_freq_units Units_MHz
+SET_SIM_PARAMETER c_secondary_in_freq 100.000
+SET_SIM_PARAMETER c_feedback_source FDBK_AUTO
+SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
+SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
+SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
+SET_SIM_PARAMETER c_use_reset 0
+SET_SIM_PARAMETER c_use_locked 0
+SET_SIM_PARAMETER c_use_inclk_stopped 0
+SET_SIM_PARAMETER c_use_clkfb_stopped 0
+SET_SIM_PARAMETER c_use_power_down 0
+SET_SIM_PARAMETER c_use_status 0
+SET_SIM_PARAMETER c_use_freeze 0
+SET_SIM_PARAMETER c_num_out_clks 1
+SET_SIM_PARAMETER c_clkout1_drives BUFG
+SET_SIM_PARAMETER c_clkout2_drives BUFG
+SET_SIM_PARAMETER c_clkout3_drives BUFG
+SET_SIM_PARAMETER c_clkout4_drives BUFG
+SET_SIM_PARAMETER c_clkout5_drives BUFG
+SET_SIM_PARAMETER c_clkout6_drives BUFG
+SET_SIM_PARAMETER c_clkout7_drives BUFG
+SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock   Freq (MHz)    Input Jitter (UI)"
+SET_SIM_PARAMETER c_inclk_sum_row1 __primary__________50.000____________0.010
+SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock 
+SET_SIM_PARAMETER c_outclk_sum_row0a "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+SET_SIM_PARAMETER c_outclk_sum_row0b "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1___110.000______0.000______50.0______381.818____150.000
+SET_SIM_PARAMETER c_outclk_sum_row2 no_CLK_OUT2_output
+SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output 
+SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
+SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
+SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
+SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output 
+SET_SIM_PARAMETER c_clkout1_requested_out_freq 110.000
+SET_SIM_PARAMETER c_clkout2_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout3_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout4_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout5_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout6_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout7_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout2_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout3_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout4_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout1_out_freq 110.000
+SET_SIM_PARAMETER c_clkout2_out_freq N/A
+SET_SIM_PARAMETER c_clkout3_out_freq N/A
+SET_SIM_PARAMETER c_clkout4_out_freq N/A
+SET_SIM_PARAMETER c_clkout5_out_freq N/A
+SET_SIM_PARAMETER c_clkout6_out_freq N/A
+SET_SIM_PARAMETER c_clkout7_out_freq N/A
+SET_SIM_PARAMETER c_clkout1_phase 0.000
+SET_SIM_PARAMETER c_clkout2_phase N/A
+SET_SIM_PARAMETER c_clkout3_phase N/A
+SET_SIM_PARAMETER c_clkout4_phase N/A
+SET_SIM_PARAMETER c_clkout5_phase N/A
+SET_SIM_PARAMETER c_clkout6_phase N/A
+SET_SIM_PARAMETER c_clkout7_phase N/A
+SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
+SET_SIM_PARAMETER c_clkout2_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout3_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
+SET_SIM_PARAMETER c_mmcm_notes None
+SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
+SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
+SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
+SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
+SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
+SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
+SET_SIM_PARAMETER c_mmcm_divclk_divide 1
+SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
+SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
+SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
+SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
+SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
+SET_SIM_PARAMETER c_pll_notes None
+SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
+SET_SIM_PARAMETER c_pll_clkfbout_mult 8
+SET_SIM_PARAMETER c_pll_clkin_period 20.0
+SET_SIM_PARAMETER c_pll_compensation INTERNAL
+SET_SIM_PARAMETER c_pll_divclk_divide 1
+SET_SIM_PARAMETER c_pll_ref_jitter 0.010
+SET_SIM_PARAMETER c_pll_clkout0_divide 128
+SET_SIM_PARAMETER c_pll_clkout1_divide 40
+SET_SIM_PARAMETER c_pll_clkout2_divide 1
+SET_SIM_PARAMETER c_pll_clkout3_divide 1
+SET_SIM_PARAMETER c_pll_clkout4_divide 1
+SET_SIM_PARAMETER c_pll_clkout5_divide 1
+SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout2_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
+SET_SIM_PARAMETER c_dcm_notes None
+SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
+SET_SIM_PARAMETER c_dcm_clkfx_divide 5
+SET_SIM_PARAMETER c_dcm_clkfx_multiply 11
+SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
+SET_SIM_PARAMETER c_dcm_clkin_period 20.0
+SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
+SET_SIM_PARAMETER c_dcm_clk_feedback NONE
+SET_SIM_PARAMETER c_dcm_clk_feedback_port NONE
+SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
+SET_SIM_PARAMETER c_dcm_phase_shift 0
+SET_SIM_PARAMETER c_dcm_startup_wait FALSE
+SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
+SET_SIM_PARAMETER c_dcm_clk_out2_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out3_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
+SET_SIM_PARAMETER c_dcm_clkgen_notes None
+SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 1
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 4
+SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 20.0
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
+SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
+SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port NONE
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE
+SET_SIM_PARAMETER c_clock_mgr_type AUTO
+SET_SIM_PARAMETER c_override_mmcm 0
+SET_SIM_PARAMETER c_override_pll 0
+SET_SIM_PARAMETER c_override_dcm 0
+SET_SIM_PARAMETER c_override_dcm_clkgen 0
+SET_SIM_PARAMETER c_dcm_pll_cascade NONE
+SET_SIM_PARAMETER c_primary_port CLK_IN1
+SET_SIM_PARAMETER c_secondary_port CLK_IN2
+SET_SIM_PARAMETER c_clk_out1_port CLK_OUT1
+SET_SIM_PARAMETER c_clk_out2_port CLK_OUT2
+SET_SIM_PARAMETER c_clk_out3_port CLK_OUT3
+SET_SIM_PARAMETER c_clk_out4_port CLK_OUT4
+SET_SIM_PARAMETER c_clk_out5_port CLK_OUT5
+SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
+SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
+SET_SIM_PARAMETER c_reset_port RESET
+SET_SIM_PARAMETER c_locked_port LOCKED
+SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
+SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
+SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
+SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
+SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
+SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
+SET_SIM_PARAMETER c_power_down_port POWER_DOWN
+SET_SIM_PARAMETER c_daddr_port DADDR
+SET_SIM_PARAMETER c_dclk_port DCLK
+SET_SIM_PARAMETER c_drdy_port DRDY
+SET_SIM_PARAMETER c_dwe_port DWE
+SET_SIM_PARAMETER c_din_port DIN
+SET_SIM_PARAMETER c_dout_port DOUT
+SET_SIM_PARAMETER c_den_port DEN
+SET_SIM_PARAMETER c_psclk_port PSCLK
+SET_SIM_PARAMETER c_psen_port PSEN
+SET_SIM_PARAMETER c_psincdec_port PSINCDEC
+SET_SIM_PARAMETER c_psdone_port PSDONE
+SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
+SET_SIM_PARAMETER c_status_port STATUS
+SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
+SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
+SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
+SET_SIM_PARAMETER c_clkin1_jitter_ps 200.0
+SET_SIM_PARAMETER c_clkin2_jitter_ps 100.0
+SET_SIM_PARAMETER c_primitive MMCM
+SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
+SET_SIM_PARAMETER c_ss_mod_period 4000
+SET_CORE_NAME Clocking Wizard
+SET_CORE_VERSION 3.6
+SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
+SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
+SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
+SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
+SET_CORE_DATASHEET C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.273617099167.out b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.273617099167.out
new file mode 100644
index 0000000..fc712d9
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.273617099167.out
@@ -0,0 +1,505 @@
+SET_FLAG DEBUG FALSE
+SET_FLAG MODE BATCH
+SET_FLAG STANDALONE_MODE FALSE
+SET_PREFERENCE devicefamily spartan6
+SET_PREFERENCE device xc6slx9
+SET_PREFERENCE speedgrade -3
+SET_PREFERENCE package tqg144
+SET_PREFERENCE verilogsim true
+SET_PREFERENCE vhdlsim false
+SET_PREFERENCE simulationfiles Behavioral
+SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
+SET_PREFERENCE outputdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/
+SET_PREFERENCE workingdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/
+SET_PREFERENCE subworkingdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/
+SET_PREFERENCE transientdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/_dbg/
+SET_PREFERENCE designentry Verilog
+SET_PREFERENCE flowvendor Other
+SET_PREFERENCE addpads false
+SET_PREFERENCE projectname coregen
+SET_PREFERENCE formalverification false
+SET_PREFERENCE asysymbol false
+SET_PREFERENCE implementationfiletype Ngc
+SET_PREFERENCE foundationsym false
+SET_PREFERENCE createndf false
+SET_PREFERENCE removerpms false
+SET_PARAMETER Component_Name spartan6_pll
+SET_PARAMETER Use_Freq_Synth true
+SET_PARAMETER Use_Phase_Alignment false
+SET_PARAMETER Use_Min_Power false
+SET_PARAMETER Use_Dyn_Phase_Shift false
+SET_PARAMETER Use_Dyn_Reconfig false
+SET_PARAMETER Jitter_Sel No_Jitter
+SET_PARAMETER Use_Spread_Spectrum false
+SET_PARAMETER Use_Spread_Spectrum_1 false
+SET_PARAMETER Prim_In_Freq 50.000
+SET_PARAMETER In_Freq_Units Units_MHz
+SET_PARAMETER In_Jitter_Units Units_UI
+SET_PARAMETER Relative_Inclk REL_PRIMARY
+SET_PARAMETER Secondary_In_Freq 100.000
+SET_PARAMETER Jitter_Options UI
+SET_PARAMETER Clkin1_UI_Jitter 0.010
+SET_PARAMETER Clkin2_UI_Jitter 0.010
+SET_PARAMETER Prim_In_Jitter 0.010
+SET_PARAMETER Secondary_In_Jitter 0.010
+SET_PARAMETER Clkin1_Jitter_Ps 200.0
+SET_PARAMETER Clkin2_Jitter_Ps 100.0
+SET_PARAMETER Clkout2_Used false
+SET_PARAMETER Clkout3_Used false
+SET_PARAMETER Clkout4_Used false
+SET_PARAMETER Clkout5_Used false
+SET_PARAMETER Clkout6_Used false
+SET_PARAMETER Clkout7_Used false
+SET_PARAMETER Num_Out_Clks 1
+SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
+SET_PARAMETER primary_port CLK_IN1
+SET_PARAMETER CLK_OUT1_port CLK_OUT1
+SET_PARAMETER CLK_OUT2_port CLK_OUT2
+SET_PARAMETER CLK_OUT3_port CLK_OUT3
+SET_PARAMETER CLK_OUT4_port CLK_OUT4
+SET_PARAMETER CLK_OUT5_port CLK_OUT5
+SET_PARAMETER CLK_OUT6_port CLK_OUT6
+SET_PARAMETER CLK_OUT7_port CLK_OUT7
+SET_PARAMETER DADDR_port DADDR
+SET_PARAMETER DCLK_port DCLK
+SET_PARAMETER DRDY_port DRDY
+SET_PARAMETER DWE_port DWE
+SET_PARAMETER DIN_port DIN
+SET_PARAMETER DOUT_port DOUT
+SET_PARAMETER DEN_port DEN
+SET_PARAMETER PSCLK_port PSCLK
+SET_PARAMETER PSEN_port PSEN
+SET_PARAMETER PSINCDEC_port PSINCDEC
+SET_PARAMETER PSDONE_port PSDONE
+SET_PARAMETER Clkout1_Requested_Out_Freq 105.000
+SET_PARAMETER Clkout1_Requested_Phase 0.000
+SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout2_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout2_Requested_Phase 0.000
+SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout3_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout3_Requested_Phase 0.000
+SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout4_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout4_Requested_Phase 0.000
+SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout5_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout5_Requested_Phase 0.000
+SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout6_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout6_Requested_Phase 0.000
+SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout7_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout7_Requested_Phase 0.000
+SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.000
+SET_PARAMETER Use_Max_I_Jitter false
+SET_PARAMETER Use_Min_O_Jitter false
+SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
+SET_PARAMETER Use_Inclk_Switchover false
+SET_PARAMETER secondary_port CLK_IN2
+SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
+SET_PARAMETER Clkout1_Drives BUFG
+SET_PARAMETER Clkout2_Drives BUFG
+SET_PARAMETER Clkout3_Drives BUFG
+SET_PARAMETER Clkout4_Drives BUFG
+SET_PARAMETER Clkout5_Drives BUFG
+SET_PARAMETER Clkout6_Drives BUFG
+SET_PARAMETER Clkout7_Drives BUFG
+SET_PARAMETER Feedback_Source FDBK_AUTO
+SET_PARAMETER Clkfb_In_Signaling SINGLE
+SET_PARAMETER CLKFB_IN_port CLKFB_IN
+SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
+SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
+SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
+SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
+SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
+SET_PARAMETER Platform nt64
+SET_PARAMETER Summary_Strings empty
+SET_PARAMETER Use_Locked false
+SET_PARAMETER calc_done DONE
+SET_PARAMETER Use_Reset false
+SET_PARAMETER Use_Power_Down false
+SET_PARAMETER Use_Status false
+SET_PARAMETER Use_Freeze false
+SET_PARAMETER Use_Clk_Valid false
+SET_PARAMETER Use_Inclk_Stopped false
+SET_PARAMETER Use_Clkfb_Stopped false
+SET_PARAMETER RESET_port RESET
+SET_PARAMETER LOCKED_port LOCKED
+SET_PARAMETER Power_Down_port POWER_DOWN
+SET_PARAMETER CLK_VALID_port CLK_VALID
+SET_PARAMETER STATUS_port STATUS
+SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
+SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
+SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
+SET_PARAMETER Override_Mmcm false
+SET_PARAMETER Mmcm_Notes None
+SET_PARAMETER Mmcm_Divclk_Divide 1
+SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
+SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
+SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
+SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkin1_Period 10.000
+SET_PARAMETER Mmcm_Clkin2_Period 10.000
+SET_PARAMETER Mmcm_Clkout4_Cascade false
+SET_PARAMETER Mmcm_Clock_Hold false
+SET_PARAMETER Mmcm_Compensation ZHOLD
+SET_PARAMETER Mmcm_Ref_Jitter1 0.010
+SET_PARAMETER Mmcm_Ref_Jitter2 0.010
+SET_PARAMETER Mmcm_Startup_Wait false
+SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
+SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout0_Phase 0.000
+SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout1_Divide 1
+SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout1_Phase 0.000
+SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout2_Divide 1
+SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout2_Phase 0.000
+SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout3_Divide 1
+SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout3_Phase 0.000
+SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout4_Divide 1
+SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout4_Phase 0.000
+SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout5_Divide 1
+SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout5_Phase 0.000
+SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout6_Divide 1
+SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout6_Phase 0.000
+SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
+SET_PARAMETER Override_Dcm false
+SET_PARAMETER Dcm_Notes None
+SET_PARAMETER Dcm_Clkdv_Divide 2.0
+SET_PARAMETER Dcm_Clkfx_Divide 10
+SET_PARAMETER Dcm_Clkfx_Multiply 21
+SET_PARAMETER Dcm_Clkin_Divide_By_2 false
+SET_PARAMETER Dcm_Clkin_Period 20.000
+SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
+SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
+SET_PARAMETER Dcm_Phase_Shift 0
+SET_PARAMETER Dcm_Clk_Feedback NONE
+SET_PARAMETER Dcm_Startup_Wait false
+SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
+SET_PARAMETER Dcm_Clk_Out2_Port CLKFX
+SET_PARAMETER Dcm_Clk_Out3_Port CLK0
+SET_PARAMETER Dcm_Clk_Out4_Port CLK0
+SET_PARAMETER Dcm_Clk_Out5_Port CLK0
+SET_PARAMETER Dcm_Clk_Out6_Port CLK0
+SET_PARAMETER Override_Dcm_Clkgen false
+SET_PARAMETER Dcm_Clkgen_Notes None
+SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 1
+SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 4
+SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
+SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
+SET_PARAMETER Dcm_Clkgen_Startup_Wait false
+SET_PARAMETER Dcm_Clkgen_Clkin_Period 10.000
+SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
+SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
+SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
+SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX
+SET_PARAMETER Override_Pll false
+SET_PARAMETER Pll_Notes None
+SET_PARAMETER Pll_Bandwidth OPTIMIZED
+SET_PARAMETER Pll_Clkfbout_Mult 8
+SET_PARAMETER Pll_Clkfbout_Phase 0.000
+SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
+SET_PARAMETER Pll_Divclk_Divide 1
+SET_PARAMETER Pll_Clkin_Period 20.0
+SET_PARAMETER Pll_Compensation INTERNAL
+SET_PARAMETER Pll_Ref_Jitter 0.010
+SET_PARAMETER Pll_Clkout0_Divide 4
+SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout0_Phase 0.000
+SET_PARAMETER Pll_Clkout1_Divide 40
+SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout1_Phase 0.000
+SET_PARAMETER Pll_Clkout2_Divide 1
+SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout2_Phase 0.000
+SET_PARAMETER Pll_Clkout3_Divide 1
+SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout3_Phase 0.000
+SET_PARAMETER Pll_Clkout4_Divide 1
+SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout4_Phase 0.000
+SET_PARAMETER Pll_Clkout5_Divide 1
+SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout5_Phase 0.000
+SET_PARAMETER dcm_pll_cascade NONE
+SET_PARAMETER clock_mgr_type AUTO
+SET_PARAMETER primtype_sel PLL_BASE
+SET_PARAMETER primitive MMCM
+SET_PARAMETER SS_Mode CENTER_HIGH
+SET_PARAMETER SS_Mod_Freq 250
+SET_SIM_PARAMETER c_clkout2_used 0
+SET_SIM_PARAMETER c_clkout3_used 0
+SET_SIM_PARAMETER c_clkout4_used 0
+SET_SIM_PARAMETER c_clkout5_used 0
+SET_SIM_PARAMETER c_clkout6_used 0
+SET_SIM_PARAMETER c_clkout7_used 0
+SET_SIM_PARAMETER c_use_clkout1_bar 0
+SET_SIM_PARAMETER c_use_clkout2_bar 0
+SET_SIM_PARAMETER c_use_clkout3_bar 0
+SET_SIM_PARAMETER c_use_clkout4_bar 0
+SET_SIM_PARAMETER c_component_name spartan6_pll
+SET_SIM_PARAMETER c_platform nt64
+SET_SIM_PARAMETER c_use_freq_synth 1
+SET_SIM_PARAMETER c_use_phase_alignment 0
+SET_SIM_PARAMETER c_prim_in_jitter 0.010
+SET_SIM_PARAMETER c_secondary_in_jitter 0.010
+SET_SIM_PARAMETER c_jitter_sel No_Jitter
+SET_SIM_PARAMETER c_use_min_power 0
+SET_SIM_PARAMETER c_use_min_o_jitter 0
+SET_SIM_PARAMETER c_use_max_i_jitter 0
+SET_SIM_PARAMETER c_use_dyn_phase_shift 0
+SET_SIM_PARAMETER c_use_inclk_switchover 0
+SET_SIM_PARAMETER c_use_dyn_reconfig 0
+SET_SIM_PARAMETER c_use_spread_spectrum 0
+SET_SIM_PARAMETER c_use_spread_spectrum_1 0
+SET_SIM_PARAMETER c_primtype_sel DCM_SP
+SET_SIM_PARAMETER c_use_clk_valid 0
+SET_SIM_PARAMETER c_prim_in_freq 50.000
+SET_SIM_PARAMETER c_in_freq_units Units_MHz
+SET_SIM_PARAMETER c_secondary_in_freq 100.000
+SET_SIM_PARAMETER c_feedback_source FDBK_AUTO
+SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
+SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
+SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
+SET_SIM_PARAMETER c_use_reset 0
+SET_SIM_PARAMETER c_use_locked 0
+SET_SIM_PARAMETER c_use_inclk_stopped 0
+SET_SIM_PARAMETER c_use_clkfb_stopped 0
+SET_SIM_PARAMETER c_use_power_down 0
+SET_SIM_PARAMETER c_use_status 0
+SET_SIM_PARAMETER c_use_freeze 0
+SET_SIM_PARAMETER c_num_out_clks 1
+SET_SIM_PARAMETER c_clkout1_drives BUFG
+SET_SIM_PARAMETER c_clkout2_drives BUFG
+SET_SIM_PARAMETER c_clkout3_drives BUFG
+SET_SIM_PARAMETER c_clkout4_drives BUFG
+SET_SIM_PARAMETER c_clkout5_drives BUFG
+SET_SIM_PARAMETER c_clkout6_drives BUFG
+SET_SIM_PARAMETER c_clkout7_drives BUFG
+SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock   Freq (MHz)    Input Jitter (UI)"
+SET_SIM_PARAMETER c_inclk_sum_row1 __primary__________50.000____________0.010
+SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock 
+SET_SIM_PARAMETER c_outclk_sum_row0a "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+SET_SIM_PARAMETER c_outclk_sum_row0b "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1___105.000______0.000______50.0______390.476____150.000
+SET_SIM_PARAMETER c_outclk_sum_row2 no_CLK_OUT2_output
+SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output 
+SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
+SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
+SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
+SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output 
+SET_SIM_PARAMETER c_clkout1_requested_out_freq 105.000
+SET_SIM_PARAMETER c_clkout2_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout3_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout4_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout5_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout6_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout7_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout2_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout3_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout4_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout1_out_freq 105.000
+SET_SIM_PARAMETER c_clkout2_out_freq N/A
+SET_SIM_PARAMETER c_clkout3_out_freq N/A
+SET_SIM_PARAMETER c_clkout4_out_freq N/A
+SET_SIM_PARAMETER c_clkout5_out_freq N/A
+SET_SIM_PARAMETER c_clkout6_out_freq N/A
+SET_SIM_PARAMETER c_clkout7_out_freq N/A
+SET_SIM_PARAMETER c_clkout1_phase 0.000
+SET_SIM_PARAMETER c_clkout2_phase N/A
+SET_SIM_PARAMETER c_clkout3_phase N/A
+SET_SIM_PARAMETER c_clkout4_phase N/A
+SET_SIM_PARAMETER c_clkout5_phase N/A
+SET_SIM_PARAMETER c_clkout6_phase N/A
+SET_SIM_PARAMETER c_clkout7_phase N/A
+SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
+SET_SIM_PARAMETER c_clkout2_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout3_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
+SET_SIM_PARAMETER c_mmcm_notes None
+SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
+SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
+SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
+SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
+SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
+SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
+SET_SIM_PARAMETER c_mmcm_divclk_divide 1
+SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
+SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
+SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
+SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
+SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
+SET_SIM_PARAMETER c_pll_notes None
+SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
+SET_SIM_PARAMETER c_pll_clkfbout_mult 8
+SET_SIM_PARAMETER c_pll_clkin_period 20.0
+SET_SIM_PARAMETER c_pll_compensation INTERNAL
+SET_SIM_PARAMETER c_pll_divclk_divide 1
+SET_SIM_PARAMETER c_pll_ref_jitter 0.010
+SET_SIM_PARAMETER c_pll_clkout0_divide 4
+SET_SIM_PARAMETER c_pll_clkout1_divide 40
+SET_SIM_PARAMETER c_pll_clkout2_divide 1
+SET_SIM_PARAMETER c_pll_clkout3_divide 1
+SET_SIM_PARAMETER c_pll_clkout4_divide 1
+SET_SIM_PARAMETER c_pll_clkout5_divide 1
+SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout2_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
+SET_SIM_PARAMETER c_dcm_notes None
+SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
+SET_SIM_PARAMETER c_dcm_clkfx_divide 10
+SET_SIM_PARAMETER c_dcm_clkfx_multiply 21
+SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
+SET_SIM_PARAMETER c_dcm_clkin_period 20.0
+SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
+SET_SIM_PARAMETER c_dcm_clk_feedback NONE
+SET_SIM_PARAMETER c_dcm_clk_feedback_port NONE
+SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
+SET_SIM_PARAMETER c_dcm_phase_shift 0
+SET_SIM_PARAMETER c_dcm_startup_wait FALSE
+SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
+SET_SIM_PARAMETER c_dcm_clk_out2_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out3_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
+SET_SIM_PARAMETER c_dcm_clkgen_notes None
+SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 1
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 4
+SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 20.0
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
+SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
+SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port NONE
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE
+SET_SIM_PARAMETER c_clock_mgr_type AUTO
+SET_SIM_PARAMETER c_override_mmcm 0
+SET_SIM_PARAMETER c_override_pll 0
+SET_SIM_PARAMETER c_override_dcm 0
+SET_SIM_PARAMETER c_override_dcm_clkgen 0
+SET_SIM_PARAMETER c_dcm_pll_cascade NONE
+SET_SIM_PARAMETER c_primary_port CLK_IN1
+SET_SIM_PARAMETER c_secondary_port CLK_IN2
+SET_SIM_PARAMETER c_clk_out1_port CLK_OUT1
+SET_SIM_PARAMETER c_clk_out2_port CLK_OUT2
+SET_SIM_PARAMETER c_clk_out3_port CLK_OUT3
+SET_SIM_PARAMETER c_clk_out4_port CLK_OUT4
+SET_SIM_PARAMETER c_clk_out5_port CLK_OUT5
+SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
+SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
+SET_SIM_PARAMETER c_reset_port RESET
+SET_SIM_PARAMETER c_locked_port LOCKED
+SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
+SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
+SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
+SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
+SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
+SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
+SET_SIM_PARAMETER c_power_down_port POWER_DOWN
+SET_SIM_PARAMETER c_daddr_port DADDR
+SET_SIM_PARAMETER c_dclk_port DCLK
+SET_SIM_PARAMETER c_drdy_port DRDY
+SET_SIM_PARAMETER c_dwe_port DWE
+SET_SIM_PARAMETER c_din_port DIN
+SET_SIM_PARAMETER c_dout_port DOUT
+SET_SIM_PARAMETER c_den_port DEN
+SET_SIM_PARAMETER c_psclk_port PSCLK
+SET_SIM_PARAMETER c_psen_port PSEN
+SET_SIM_PARAMETER c_psincdec_port PSINCDEC
+SET_SIM_PARAMETER c_psdone_port PSDONE
+SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
+SET_SIM_PARAMETER c_status_port STATUS
+SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
+SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
+SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
+SET_SIM_PARAMETER c_clkin1_jitter_ps 200.0
+SET_SIM_PARAMETER c_clkin2_jitter_ps 100.0
+SET_SIM_PARAMETER c_primitive MMCM
+SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
+SET_SIM_PARAMETER c_ss_mod_period 4000
+SET_CORE_NAME Clocking Wizard
+SET_CORE_VERSION 3.6
+SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
+SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
+SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
+SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
+SET_CORE_DATASHEET C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.453378507147.out b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.453378507147.out
new file mode 100644
index 0000000..16c0a9b
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.453378507147.out
@@ -0,0 +1,505 @@
+SET_FLAG DEBUG FALSE
+SET_FLAG MODE BATCH
+SET_FLAG STANDALONE_MODE FALSE
+SET_PREFERENCE devicefamily spartan6
+SET_PREFERENCE device xc6slx9
+SET_PREFERENCE speedgrade -3
+SET_PREFERENCE package tqg144
+SET_PREFERENCE verilogsim true
+SET_PREFERENCE vhdlsim false
+SET_PREFERENCE simulationfiles Behavioral
+SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
+SET_PREFERENCE outputdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/
+SET_PREFERENCE workingdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/
+SET_PREFERENCE subworkingdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/
+SET_PREFERENCE transientdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/_dbg/
+SET_PREFERENCE designentry Verilog
+SET_PREFERENCE flowvendor Other
+SET_PREFERENCE addpads false
+SET_PREFERENCE projectname coregen
+SET_PREFERENCE formalverification false
+SET_PREFERENCE asysymbol false
+SET_PREFERENCE implementationfiletype Ngc
+SET_PREFERENCE foundationsym false
+SET_PREFERENCE createndf false
+SET_PREFERENCE removerpms false
+SET_PARAMETER Component_Name spartan6_pll
+SET_PARAMETER Use_Freq_Synth true
+SET_PARAMETER Use_Phase_Alignment false
+SET_PARAMETER Use_Min_Power false
+SET_PARAMETER Use_Dyn_Phase_Shift false
+SET_PARAMETER Use_Dyn_Reconfig false
+SET_PARAMETER Jitter_Sel No_Jitter
+SET_PARAMETER Use_Spread_Spectrum false
+SET_PARAMETER Use_Spread_Spectrum_1 false
+SET_PARAMETER Prim_In_Freq 50.000
+SET_PARAMETER In_Freq_Units Units_MHz
+SET_PARAMETER In_Jitter_Units Units_UI
+SET_PARAMETER Relative_Inclk REL_PRIMARY
+SET_PARAMETER Secondary_In_Freq 100.000
+SET_PARAMETER Jitter_Options UI
+SET_PARAMETER Clkin1_UI_Jitter 0.010
+SET_PARAMETER Clkin2_UI_Jitter 0.010
+SET_PARAMETER Prim_In_Jitter 0.010
+SET_PARAMETER Secondary_In_Jitter 0.010
+SET_PARAMETER Clkin1_Jitter_Ps 200.0
+SET_PARAMETER Clkin2_Jitter_Ps 100.0
+SET_PARAMETER Clkout2_Used false
+SET_PARAMETER Clkout3_Used false
+SET_PARAMETER Clkout4_Used false
+SET_PARAMETER Clkout5_Used false
+SET_PARAMETER Clkout6_Used false
+SET_PARAMETER Clkout7_Used false
+SET_PARAMETER Num_Out_Clks 1
+SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
+SET_PARAMETER primary_port CLK_IN1
+SET_PARAMETER CLK_OUT1_port CLK_OUT1
+SET_PARAMETER CLK_OUT2_port CLK_OUT2
+SET_PARAMETER CLK_OUT3_port CLK_OUT3
+SET_PARAMETER CLK_OUT4_port CLK_OUT4
+SET_PARAMETER CLK_OUT5_port CLK_OUT5
+SET_PARAMETER CLK_OUT6_port CLK_OUT6
+SET_PARAMETER CLK_OUT7_port CLK_OUT7
+SET_PARAMETER DADDR_port DADDR
+SET_PARAMETER DCLK_port DCLK
+SET_PARAMETER DRDY_port DRDY
+SET_PARAMETER DWE_port DWE
+SET_PARAMETER DIN_port DIN
+SET_PARAMETER DOUT_port DOUT
+SET_PARAMETER DEN_port DEN
+SET_PARAMETER PSCLK_port PSCLK
+SET_PARAMETER PSEN_port PSEN
+SET_PARAMETER PSINCDEC_port PSINCDEC
+SET_PARAMETER PSDONE_port PSDONE
+SET_PARAMETER Clkout1_Requested_Out_Freq 107.000
+SET_PARAMETER Clkout1_Requested_Phase 0.000
+SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout2_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout2_Requested_Phase 0.000
+SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout3_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout3_Requested_Phase 0.000
+SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout4_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout4_Requested_Phase 0.000
+SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout5_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout5_Requested_Phase 0.000
+SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout6_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout6_Requested_Phase 0.000
+SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout7_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout7_Requested_Phase 0.000
+SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.000
+SET_PARAMETER Use_Max_I_Jitter false
+SET_PARAMETER Use_Min_O_Jitter false
+SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
+SET_PARAMETER Use_Inclk_Switchover false
+SET_PARAMETER secondary_port CLK_IN2
+SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
+SET_PARAMETER Clkout1_Drives BUFG
+SET_PARAMETER Clkout2_Drives BUFG
+SET_PARAMETER Clkout3_Drives BUFG
+SET_PARAMETER Clkout4_Drives BUFG
+SET_PARAMETER Clkout5_Drives BUFG
+SET_PARAMETER Clkout6_Drives BUFG
+SET_PARAMETER Clkout7_Drives BUFG
+SET_PARAMETER Feedback_Source FDBK_AUTO
+SET_PARAMETER Clkfb_In_Signaling SINGLE
+SET_PARAMETER CLKFB_IN_port CLKFB_IN
+SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
+SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
+SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
+SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
+SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
+SET_PARAMETER Platform nt64
+SET_PARAMETER Summary_Strings empty
+SET_PARAMETER Use_Locked false
+SET_PARAMETER calc_done DONE
+SET_PARAMETER Use_Reset false
+SET_PARAMETER Use_Power_Down false
+SET_PARAMETER Use_Status false
+SET_PARAMETER Use_Freeze false
+SET_PARAMETER Use_Clk_Valid false
+SET_PARAMETER Use_Inclk_Stopped false
+SET_PARAMETER Use_Clkfb_Stopped false
+SET_PARAMETER RESET_port RESET
+SET_PARAMETER LOCKED_port LOCKED
+SET_PARAMETER Power_Down_port POWER_DOWN
+SET_PARAMETER CLK_VALID_port CLK_VALID
+SET_PARAMETER STATUS_port STATUS
+SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
+SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
+SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
+SET_PARAMETER Override_Mmcm false
+SET_PARAMETER Mmcm_Notes None
+SET_PARAMETER Mmcm_Divclk_Divide 1
+SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
+SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
+SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
+SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkin1_Period 10.000
+SET_PARAMETER Mmcm_Clkin2_Period 10.000
+SET_PARAMETER Mmcm_Clkout4_Cascade false
+SET_PARAMETER Mmcm_Clock_Hold false
+SET_PARAMETER Mmcm_Compensation ZHOLD
+SET_PARAMETER Mmcm_Ref_Jitter1 0.010
+SET_PARAMETER Mmcm_Ref_Jitter2 0.010
+SET_PARAMETER Mmcm_Startup_Wait false
+SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
+SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout0_Phase 0.000
+SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout1_Divide 1
+SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout1_Phase 0.000
+SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout2_Divide 1
+SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout2_Phase 0.000
+SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout3_Divide 1
+SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout3_Phase 0.000
+SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout4_Divide 1
+SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout4_Phase 0.000
+SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout5_Divide 1
+SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout5_Phase 0.000
+SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout6_Divide 1
+SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout6_Phase 0.000
+SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
+SET_PARAMETER Override_Dcm false
+SET_PARAMETER Dcm_Notes None
+SET_PARAMETER Dcm_Clkdv_Divide 2.0
+SET_PARAMETER Dcm_Clkfx_Divide 10
+SET_PARAMETER Dcm_Clkfx_Multiply 2
+SET_PARAMETER Dcm_Clkin_Divide_By_2 false
+SET_PARAMETER Dcm_Clkin_Period 20.000
+SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
+SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
+SET_PARAMETER Dcm_Phase_Shift 0
+SET_PARAMETER Dcm_Clk_Feedback NONE
+SET_PARAMETER Dcm_Startup_Wait false
+SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
+SET_PARAMETER Dcm_Clk_Out2_Port CLKFX
+SET_PARAMETER Dcm_Clk_Out3_Port CLK0
+SET_PARAMETER Dcm_Clk_Out4_Port CLK0
+SET_PARAMETER Dcm_Clk_Out5_Port CLK0
+SET_PARAMETER Dcm_Clk_Out6_Port CLK0
+SET_PARAMETER Override_Dcm_Clkgen false
+SET_PARAMETER Dcm_Clkgen_Notes None
+SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 1
+SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 4
+SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
+SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
+SET_PARAMETER Dcm_Clkgen_Startup_Wait false
+SET_PARAMETER Dcm_Clkgen_Clkin_Period 10.000
+SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
+SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
+SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
+SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX
+SET_PARAMETER Override_Pll false
+SET_PARAMETER Pll_Notes None
+SET_PARAMETER Pll_Bandwidth OPTIMIZED
+SET_PARAMETER Pll_Clkfbout_Mult 15
+SET_PARAMETER Pll_Clkfbout_Phase 0.000
+SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
+SET_PARAMETER Pll_Divclk_Divide 1
+SET_PARAMETER Pll_Clkin_Period 20.000
+SET_PARAMETER Pll_Compensation INTERNAL
+SET_PARAMETER Pll_Ref_Jitter 0.010
+SET_PARAMETER Pll_Clkout0_Divide 7
+SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout0_Phase 0.000
+SET_PARAMETER Pll_Clkout1_Divide 40
+SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout1_Phase 0.000
+SET_PARAMETER Pll_Clkout2_Divide 1
+SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout2_Phase 0.000
+SET_PARAMETER Pll_Clkout3_Divide 1
+SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout3_Phase 0.000
+SET_PARAMETER Pll_Clkout4_Divide 1
+SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout4_Phase 0.000
+SET_PARAMETER Pll_Clkout5_Divide 1
+SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout5_Phase 0.000
+SET_PARAMETER dcm_pll_cascade NONE
+SET_PARAMETER clock_mgr_type AUTO
+SET_PARAMETER primtype_sel PLL_BASE
+SET_PARAMETER primitive MMCM
+SET_PARAMETER SS_Mode CENTER_HIGH
+SET_PARAMETER SS_Mod_Freq 250
+SET_SIM_PARAMETER c_clkout2_used 0
+SET_SIM_PARAMETER c_clkout3_used 0
+SET_SIM_PARAMETER c_clkout4_used 0
+SET_SIM_PARAMETER c_clkout5_used 0
+SET_SIM_PARAMETER c_clkout6_used 0
+SET_SIM_PARAMETER c_clkout7_used 0
+SET_SIM_PARAMETER c_use_clkout1_bar 0
+SET_SIM_PARAMETER c_use_clkout2_bar 0
+SET_SIM_PARAMETER c_use_clkout3_bar 0
+SET_SIM_PARAMETER c_use_clkout4_bar 0
+SET_SIM_PARAMETER c_component_name spartan6_pll
+SET_SIM_PARAMETER c_platform nt64
+SET_SIM_PARAMETER c_use_freq_synth 1
+SET_SIM_PARAMETER c_use_phase_alignment 0
+SET_SIM_PARAMETER c_prim_in_jitter 0.010
+SET_SIM_PARAMETER c_secondary_in_jitter 0.010
+SET_SIM_PARAMETER c_jitter_sel No_Jitter
+SET_SIM_PARAMETER c_use_min_power 0
+SET_SIM_PARAMETER c_use_min_o_jitter 0
+SET_SIM_PARAMETER c_use_max_i_jitter 0
+SET_SIM_PARAMETER c_use_dyn_phase_shift 0
+SET_SIM_PARAMETER c_use_inclk_switchover 0
+SET_SIM_PARAMETER c_use_dyn_reconfig 0
+SET_SIM_PARAMETER c_use_spread_spectrum 0
+SET_SIM_PARAMETER c_use_spread_spectrum_1 0
+SET_SIM_PARAMETER c_primtype_sel PLL_BASE
+SET_SIM_PARAMETER c_use_clk_valid 0
+SET_SIM_PARAMETER c_prim_in_freq 50.000
+SET_SIM_PARAMETER c_in_freq_units Units_MHz
+SET_SIM_PARAMETER c_secondary_in_freq 100.000
+SET_SIM_PARAMETER c_feedback_source FDBK_AUTO
+SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
+SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
+SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
+SET_SIM_PARAMETER c_use_reset 0
+SET_SIM_PARAMETER c_use_locked 0
+SET_SIM_PARAMETER c_use_inclk_stopped 0
+SET_SIM_PARAMETER c_use_clkfb_stopped 0
+SET_SIM_PARAMETER c_use_power_down 0
+SET_SIM_PARAMETER c_use_status 0
+SET_SIM_PARAMETER c_use_freeze 0
+SET_SIM_PARAMETER c_num_out_clks 1
+SET_SIM_PARAMETER c_clkout1_drives BUFG
+SET_SIM_PARAMETER c_clkout2_drives BUFG
+SET_SIM_PARAMETER c_clkout3_drives BUFG
+SET_SIM_PARAMETER c_clkout4_drives BUFG
+SET_SIM_PARAMETER c_clkout5_drives BUFG
+SET_SIM_PARAMETER c_clkout6_drives BUFG
+SET_SIM_PARAMETER c_clkout7_drives BUFG
+SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock   Freq (MHz)    Input Jitter (UI)"
+SET_SIM_PARAMETER c_inclk_sum_row1 __primary__________50.000____________0.010
+SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock 
+SET_SIM_PARAMETER c_outclk_sum_row0a "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+SET_SIM_PARAMETER c_outclk_sum_row0b "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1___107.143______0.000______50.0______218.879____193.725
+SET_SIM_PARAMETER c_outclk_sum_row2 no_CLK_OUT2_output
+SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output 
+SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
+SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
+SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
+SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output 
+SET_SIM_PARAMETER c_clkout1_requested_out_freq 107.000
+SET_SIM_PARAMETER c_clkout2_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout3_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout4_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout5_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout6_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout7_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout2_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout3_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout4_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout1_out_freq 107.143
+SET_SIM_PARAMETER c_clkout2_out_freq N/A
+SET_SIM_PARAMETER c_clkout3_out_freq N/A
+SET_SIM_PARAMETER c_clkout4_out_freq N/A
+SET_SIM_PARAMETER c_clkout5_out_freq N/A
+SET_SIM_PARAMETER c_clkout6_out_freq N/A
+SET_SIM_PARAMETER c_clkout7_out_freq N/A
+SET_SIM_PARAMETER c_clkout1_phase 0.000
+SET_SIM_PARAMETER c_clkout2_phase N/A
+SET_SIM_PARAMETER c_clkout3_phase N/A
+SET_SIM_PARAMETER c_clkout4_phase N/A
+SET_SIM_PARAMETER c_clkout5_phase N/A
+SET_SIM_PARAMETER c_clkout6_phase N/A
+SET_SIM_PARAMETER c_clkout7_phase N/A
+SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
+SET_SIM_PARAMETER c_clkout2_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout3_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
+SET_SIM_PARAMETER c_mmcm_notes None
+SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
+SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
+SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
+SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
+SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
+SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
+SET_SIM_PARAMETER c_mmcm_divclk_divide 1
+SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
+SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
+SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
+SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
+SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
+SET_SIM_PARAMETER c_pll_notes None
+SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
+SET_SIM_PARAMETER c_pll_clkfbout_mult 15
+SET_SIM_PARAMETER c_pll_clkin_period 20.000
+SET_SIM_PARAMETER c_pll_compensation INTERNAL
+SET_SIM_PARAMETER c_pll_divclk_divide 1
+SET_SIM_PARAMETER c_pll_ref_jitter 0.010
+SET_SIM_PARAMETER c_pll_clkout0_divide 7
+SET_SIM_PARAMETER c_pll_clkout1_divide 40
+SET_SIM_PARAMETER c_pll_clkout2_divide 1
+SET_SIM_PARAMETER c_pll_clkout3_divide 1
+SET_SIM_PARAMETER c_pll_clkout4_divide 1
+SET_SIM_PARAMETER c_pll_clkout5_divide 1
+SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout2_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
+SET_SIM_PARAMETER c_dcm_notes None
+SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
+SET_SIM_PARAMETER c_dcm_clkfx_divide 10
+SET_SIM_PARAMETER c_dcm_clkfx_multiply 2
+SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
+SET_SIM_PARAMETER c_dcm_clkin_period 20.0
+SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
+SET_SIM_PARAMETER c_dcm_clk_feedback NONE
+SET_SIM_PARAMETER c_dcm_clk_feedback_port NONE
+SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
+SET_SIM_PARAMETER c_dcm_phase_shift 0
+SET_SIM_PARAMETER c_dcm_startup_wait FALSE
+SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
+SET_SIM_PARAMETER c_dcm_clk_out2_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out3_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
+SET_SIM_PARAMETER c_dcm_clkgen_notes None
+SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 1
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 4
+SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 20.0
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
+SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
+SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port NONE
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE
+SET_SIM_PARAMETER c_clock_mgr_type AUTO
+SET_SIM_PARAMETER c_override_mmcm 0
+SET_SIM_PARAMETER c_override_pll 0
+SET_SIM_PARAMETER c_override_dcm 0
+SET_SIM_PARAMETER c_override_dcm_clkgen 0
+SET_SIM_PARAMETER c_dcm_pll_cascade NONE
+SET_SIM_PARAMETER c_primary_port CLK_IN1
+SET_SIM_PARAMETER c_secondary_port CLK_IN2
+SET_SIM_PARAMETER c_clk_out1_port CLK_OUT1
+SET_SIM_PARAMETER c_clk_out2_port CLK_OUT2
+SET_SIM_PARAMETER c_clk_out3_port CLK_OUT3
+SET_SIM_PARAMETER c_clk_out4_port CLK_OUT4
+SET_SIM_PARAMETER c_clk_out5_port CLK_OUT5
+SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
+SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
+SET_SIM_PARAMETER c_reset_port RESET
+SET_SIM_PARAMETER c_locked_port LOCKED
+SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
+SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
+SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
+SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
+SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
+SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
+SET_SIM_PARAMETER c_power_down_port POWER_DOWN
+SET_SIM_PARAMETER c_daddr_port DADDR
+SET_SIM_PARAMETER c_dclk_port DCLK
+SET_SIM_PARAMETER c_drdy_port DRDY
+SET_SIM_PARAMETER c_dwe_port DWE
+SET_SIM_PARAMETER c_din_port DIN
+SET_SIM_PARAMETER c_dout_port DOUT
+SET_SIM_PARAMETER c_den_port DEN
+SET_SIM_PARAMETER c_psclk_port PSCLK
+SET_SIM_PARAMETER c_psen_port PSEN
+SET_SIM_PARAMETER c_psincdec_port PSINCDEC
+SET_SIM_PARAMETER c_psdone_port PSDONE
+SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
+SET_SIM_PARAMETER c_status_port STATUS
+SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
+SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
+SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
+SET_SIM_PARAMETER c_clkin1_jitter_ps 200.0
+SET_SIM_PARAMETER c_clkin2_jitter_ps 100.0
+SET_SIM_PARAMETER c_primitive MMCM
+SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
+SET_SIM_PARAMETER c_ss_mod_period 4000
+SET_CORE_NAME Clocking Wizard
+SET_CORE_VERSION 3.6
+SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
+SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
+SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
+SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
+SET_CORE_DATASHEET C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.496287952408.out b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.496287952408.out
new file mode 100644
index 0000000..a997e23
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.496287952408.out
@@ -0,0 +1,505 @@
+SET_FLAG DEBUG FALSE
+SET_FLAG MODE BATCH
+SET_FLAG STANDALONE_MODE FALSE
+SET_PREFERENCE devicefamily spartan6
+SET_PREFERENCE device xc6slx9
+SET_PREFERENCE speedgrade -3
+SET_PREFERENCE package tqg144
+SET_PREFERENCE verilogsim true
+SET_PREFERENCE vhdlsim false
+SET_PREFERENCE simulationfiles Behavioral
+SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
+SET_PREFERENCE outputdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/
+SET_PREFERENCE workingdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/
+SET_PREFERENCE subworkingdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/
+SET_PREFERENCE transientdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/_dbg/
+SET_PREFERENCE designentry Verilog
+SET_PREFERENCE flowvendor Other
+SET_PREFERENCE addpads false
+SET_PREFERENCE projectname coregen
+SET_PREFERENCE formalverification false
+SET_PREFERENCE asysymbol false
+SET_PREFERENCE implementationfiletype Ngc
+SET_PREFERENCE foundationsym false
+SET_PREFERENCE createndf false
+SET_PREFERENCE removerpms false
+SET_PARAMETER Component_Name spartan6_pll
+SET_PARAMETER Use_Freq_Synth true
+SET_PARAMETER Use_Phase_Alignment false
+SET_PARAMETER Use_Min_Power false
+SET_PARAMETER Use_Dyn_Phase_Shift false
+SET_PARAMETER Use_Dyn_Reconfig false
+SET_PARAMETER Jitter_Sel No_Jitter
+SET_PARAMETER Use_Spread_Spectrum false
+SET_PARAMETER Use_Spread_Spectrum_1 false
+SET_PARAMETER Prim_In_Freq 50.000
+SET_PARAMETER In_Freq_Units Units_MHz
+SET_PARAMETER In_Jitter_Units Units_UI
+SET_PARAMETER Relative_Inclk REL_PRIMARY
+SET_PARAMETER Secondary_In_Freq 100.000
+SET_PARAMETER Jitter_Options UI
+SET_PARAMETER Clkin1_UI_Jitter 0.010
+SET_PARAMETER Clkin2_UI_Jitter 0.010
+SET_PARAMETER Prim_In_Jitter 0.010
+SET_PARAMETER Secondary_In_Jitter 0.010
+SET_PARAMETER Clkin1_Jitter_Ps 200.0
+SET_PARAMETER Clkin2_Jitter_Ps 100.0
+SET_PARAMETER Clkout2_Used false
+SET_PARAMETER Clkout3_Used false
+SET_PARAMETER Clkout4_Used false
+SET_PARAMETER Clkout5_Used false
+SET_PARAMETER Clkout6_Used false
+SET_PARAMETER Clkout7_Used false
+SET_PARAMETER Num_Out_Clks 1
+SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
+SET_PARAMETER primary_port CLK_IN1
+SET_PARAMETER CLK_OUT1_port CLK_OUT1
+SET_PARAMETER CLK_OUT2_port CLK_OUT2
+SET_PARAMETER CLK_OUT3_port CLK_OUT3
+SET_PARAMETER CLK_OUT4_port CLK_OUT4
+SET_PARAMETER CLK_OUT5_port CLK_OUT5
+SET_PARAMETER CLK_OUT6_port CLK_OUT6
+SET_PARAMETER CLK_OUT7_port CLK_OUT7
+SET_PARAMETER DADDR_port DADDR
+SET_PARAMETER DCLK_port DCLK
+SET_PARAMETER DRDY_port DRDY
+SET_PARAMETER DWE_port DWE
+SET_PARAMETER DIN_port DIN
+SET_PARAMETER DOUT_port DOUT
+SET_PARAMETER DEN_port DEN
+SET_PARAMETER PSCLK_port PSCLK
+SET_PARAMETER PSEN_port PSEN
+SET_PARAMETER PSINCDEC_port PSINCDEC
+SET_PARAMETER PSDONE_port PSDONE
+SET_PARAMETER Clkout1_Requested_Out_Freq 110.000
+SET_PARAMETER Clkout1_Requested_Phase 0.000
+SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout2_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout2_Requested_Phase 0.000
+SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout3_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout3_Requested_Phase 0.000
+SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout4_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout4_Requested_Phase 0.000
+SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout5_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout5_Requested_Phase 0.000
+SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout6_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout6_Requested_Phase 0.000
+SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout7_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout7_Requested_Phase 0.000
+SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.000
+SET_PARAMETER Use_Max_I_Jitter false
+SET_PARAMETER Use_Min_O_Jitter false
+SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
+SET_PARAMETER Use_Inclk_Switchover false
+SET_PARAMETER secondary_port CLK_IN2
+SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
+SET_PARAMETER Clkout1_Drives BUFG
+SET_PARAMETER Clkout2_Drives BUFG
+SET_PARAMETER Clkout3_Drives BUFG
+SET_PARAMETER Clkout4_Drives BUFG
+SET_PARAMETER Clkout5_Drives BUFG
+SET_PARAMETER Clkout6_Drives BUFG
+SET_PARAMETER Clkout7_Drives BUFG
+SET_PARAMETER Feedback_Source FDBK_AUTO
+SET_PARAMETER Clkfb_In_Signaling SINGLE
+SET_PARAMETER CLKFB_IN_port CLKFB_IN
+SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
+SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
+SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
+SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
+SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
+SET_PARAMETER Platform nt64
+SET_PARAMETER Summary_Strings empty
+SET_PARAMETER Use_Locked false
+SET_PARAMETER calc_done DONE
+SET_PARAMETER Use_Reset false
+SET_PARAMETER Use_Power_Down false
+SET_PARAMETER Use_Status false
+SET_PARAMETER Use_Freeze false
+SET_PARAMETER Use_Clk_Valid false
+SET_PARAMETER Use_Inclk_Stopped false
+SET_PARAMETER Use_Clkfb_Stopped false
+SET_PARAMETER RESET_port RESET
+SET_PARAMETER LOCKED_port LOCKED
+SET_PARAMETER Power_Down_port POWER_DOWN
+SET_PARAMETER CLK_VALID_port CLK_VALID
+SET_PARAMETER STATUS_port STATUS
+SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
+SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
+SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
+SET_PARAMETER Override_Mmcm false
+SET_PARAMETER Mmcm_Notes None
+SET_PARAMETER Mmcm_Divclk_Divide 1
+SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
+SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
+SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
+SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkin1_Period 10.000
+SET_PARAMETER Mmcm_Clkin2_Period 10.000
+SET_PARAMETER Mmcm_Clkout4_Cascade false
+SET_PARAMETER Mmcm_Clock_Hold false
+SET_PARAMETER Mmcm_Compensation ZHOLD
+SET_PARAMETER Mmcm_Ref_Jitter1 0.010
+SET_PARAMETER Mmcm_Ref_Jitter2 0.010
+SET_PARAMETER Mmcm_Startup_Wait false
+SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
+SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout0_Phase 0.000
+SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout1_Divide 1
+SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout1_Phase 0.000
+SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout2_Divide 1
+SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout2_Phase 0.000
+SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout3_Divide 1
+SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout3_Phase 0.000
+SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout4_Divide 1
+SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout4_Phase 0.000
+SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout5_Divide 1
+SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout5_Phase 0.000
+SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout6_Divide 1
+SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout6_Phase 0.000
+SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
+SET_PARAMETER Override_Dcm false
+SET_PARAMETER Dcm_Notes None
+SET_PARAMETER Dcm_Clkdv_Divide 2.0
+SET_PARAMETER Dcm_Clkfx_Divide 5
+SET_PARAMETER Dcm_Clkfx_Multiply 11
+SET_PARAMETER Dcm_Clkin_Divide_By_2 false
+SET_PARAMETER Dcm_Clkin_Period 20.000
+SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
+SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
+SET_PARAMETER Dcm_Phase_Shift 0
+SET_PARAMETER Dcm_Clk_Feedback NONE
+SET_PARAMETER Dcm_Startup_Wait false
+SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
+SET_PARAMETER Dcm_Clk_Out2_Port CLKFX
+SET_PARAMETER Dcm_Clk_Out3_Port CLK0
+SET_PARAMETER Dcm_Clk_Out4_Port CLK0
+SET_PARAMETER Dcm_Clk_Out5_Port CLK0
+SET_PARAMETER Dcm_Clk_Out6_Port CLK0
+SET_PARAMETER Override_Dcm_Clkgen false
+SET_PARAMETER Dcm_Clkgen_Notes None
+SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 1
+SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 4
+SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
+SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
+SET_PARAMETER Dcm_Clkgen_Startup_Wait false
+SET_PARAMETER Dcm_Clkgen_Clkin_Period 10.000
+SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
+SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
+SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
+SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX
+SET_PARAMETER Override_Pll false
+SET_PARAMETER Pll_Notes None
+SET_PARAMETER Pll_Bandwidth OPTIMIZED
+SET_PARAMETER Pll_Clkfbout_Mult 8
+SET_PARAMETER Pll_Clkfbout_Phase 0.000
+SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
+SET_PARAMETER Pll_Divclk_Divide 1
+SET_PARAMETER Pll_Clkin_Period 20.0
+SET_PARAMETER Pll_Compensation INTERNAL
+SET_PARAMETER Pll_Ref_Jitter 0.010
+SET_PARAMETER Pll_Clkout0_Divide 128
+SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout0_Phase 0.000
+SET_PARAMETER Pll_Clkout1_Divide 40
+SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout1_Phase 0.000
+SET_PARAMETER Pll_Clkout2_Divide 1
+SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout2_Phase 0.000
+SET_PARAMETER Pll_Clkout3_Divide 1
+SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout3_Phase 0.000
+SET_PARAMETER Pll_Clkout4_Divide 1
+SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout4_Phase 0.000
+SET_PARAMETER Pll_Clkout5_Divide 1
+SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout5_Phase 0.000
+SET_PARAMETER dcm_pll_cascade NONE
+SET_PARAMETER clock_mgr_type AUTO
+SET_PARAMETER primtype_sel PLL_BASE
+SET_PARAMETER primitive MMCM
+SET_PARAMETER SS_Mode CENTER_HIGH
+SET_PARAMETER SS_Mod_Freq 250
+SET_SIM_PARAMETER c_clkout2_used 0
+SET_SIM_PARAMETER c_clkout3_used 0
+SET_SIM_PARAMETER c_clkout4_used 0
+SET_SIM_PARAMETER c_clkout5_used 0
+SET_SIM_PARAMETER c_clkout6_used 0
+SET_SIM_PARAMETER c_clkout7_used 0
+SET_SIM_PARAMETER c_use_clkout1_bar 0
+SET_SIM_PARAMETER c_use_clkout2_bar 0
+SET_SIM_PARAMETER c_use_clkout3_bar 0
+SET_SIM_PARAMETER c_use_clkout4_bar 0
+SET_SIM_PARAMETER c_component_name spartan6_pll
+SET_SIM_PARAMETER c_platform nt64
+SET_SIM_PARAMETER c_use_freq_synth 1
+SET_SIM_PARAMETER c_use_phase_alignment 0
+SET_SIM_PARAMETER c_prim_in_jitter 0.010
+SET_SIM_PARAMETER c_secondary_in_jitter 0.010
+SET_SIM_PARAMETER c_jitter_sel No_Jitter
+SET_SIM_PARAMETER c_use_min_power 0
+SET_SIM_PARAMETER c_use_min_o_jitter 0
+SET_SIM_PARAMETER c_use_max_i_jitter 0
+SET_SIM_PARAMETER c_use_dyn_phase_shift 0
+SET_SIM_PARAMETER c_use_inclk_switchover 0
+SET_SIM_PARAMETER c_use_dyn_reconfig 0
+SET_SIM_PARAMETER c_use_spread_spectrum 0
+SET_SIM_PARAMETER c_use_spread_spectrum_1 0
+SET_SIM_PARAMETER c_primtype_sel DCM_SP
+SET_SIM_PARAMETER c_use_clk_valid 0
+SET_SIM_PARAMETER c_prim_in_freq 50.000
+SET_SIM_PARAMETER c_in_freq_units Units_MHz
+SET_SIM_PARAMETER c_secondary_in_freq 100.000
+SET_SIM_PARAMETER c_feedback_source FDBK_AUTO
+SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
+SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
+SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
+SET_SIM_PARAMETER c_use_reset 0
+SET_SIM_PARAMETER c_use_locked 0
+SET_SIM_PARAMETER c_use_inclk_stopped 0
+SET_SIM_PARAMETER c_use_clkfb_stopped 0
+SET_SIM_PARAMETER c_use_power_down 0
+SET_SIM_PARAMETER c_use_status 0
+SET_SIM_PARAMETER c_use_freeze 0
+SET_SIM_PARAMETER c_num_out_clks 1
+SET_SIM_PARAMETER c_clkout1_drives BUFG
+SET_SIM_PARAMETER c_clkout2_drives BUFG
+SET_SIM_PARAMETER c_clkout3_drives BUFG
+SET_SIM_PARAMETER c_clkout4_drives BUFG
+SET_SIM_PARAMETER c_clkout5_drives BUFG
+SET_SIM_PARAMETER c_clkout6_drives BUFG
+SET_SIM_PARAMETER c_clkout7_drives BUFG
+SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock   Freq (MHz)    Input Jitter (UI)"
+SET_SIM_PARAMETER c_inclk_sum_row1 __primary__________50.000____________0.010
+SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock 
+SET_SIM_PARAMETER c_outclk_sum_row0a "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+SET_SIM_PARAMETER c_outclk_sum_row0b "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1___110.000______0.000______50.0______381.818____150.000
+SET_SIM_PARAMETER c_outclk_sum_row2 no_CLK_OUT2_output
+SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output 
+SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
+SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
+SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
+SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output 
+SET_SIM_PARAMETER c_clkout1_requested_out_freq 110.000
+SET_SIM_PARAMETER c_clkout2_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout3_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout4_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout5_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout6_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout7_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout2_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout3_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout4_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout1_out_freq 110.000
+SET_SIM_PARAMETER c_clkout2_out_freq N/A
+SET_SIM_PARAMETER c_clkout3_out_freq N/A
+SET_SIM_PARAMETER c_clkout4_out_freq N/A
+SET_SIM_PARAMETER c_clkout5_out_freq N/A
+SET_SIM_PARAMETER c_clkout6_out_freq N/A
+SET_SIM_PARAMETER c_clkout7_out_freq N/A
+SET_SIM_PARAMETER c_clkout1_phase 0.000
+SET_SIM_PARAMETER c_clkout2_phase N/A
+SET_SIM_PARAMETER c_clkout3_phase N/A
+SET_SIM_PARAMETER c_clkout4_phase N/A
+SET_SIM_PARAMETER c_clkout5_phase N/A
+SET_SIM_PARAMETER c_clkout6_phase N/A
+SET_SIM_PARAMETER c_clkout7_phase N/A
+SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
+SET_SIM_PARAMETER c_clkout2_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout3_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
+SET_SIM_PARAMETER c_mmcm_notes None
+SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
+SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
+SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
+SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
+SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
+SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
+SET_SIM_PARAMETER c_mmcm_divclk_divide 1
+SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
+SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
+SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
+SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
+SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
+SET_SIM_PARAMETER c_pll_notes None
+SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
+SET_SIM_PARAMETER c_pll_clkfbout_mult 8
+SET_SIM_PARAMETER c_pll_clkin_period 20.0
+SET_SIM_PARAMETER c_pll_compensation INTERNAL
+SET_SIM_PARAMETER c_pll_divclk_divide 1
+SET_SIM_PARAMETER c_pll_ref_jitter 0.010
+SET_SIM_PARAMETER c_pll_clkout0_divide 128
+SET_SIM_PARAMETER c_pll_clkout1_divide 40
+SET_SIM_PARAMETER c_pll_clkout2_divide 1
+SET_SIM_PARAMETER c_pll_clkout3_divide 1
+SET_SIM_PARAMETER c_pll_clkout4_divide 1
+SET_SIM_PARAMETER c_pll_clkout5_divide 1
+SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout2_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
+SET_SIM_PARAMETER c_dcm_notes None
+SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
+SET_SIM_PARAMETER c_dcm_clkfx_divide 5
+SET_SIM_PARAMETER c_dcm_clkfx_multiply 11
+SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
+SET_SIM_PARAMETER c_dcm_clkin_period 20.0
+SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
+SET_SIM_PARAMETER c_dcm_clk_feedback NONE
+SET_SIM_PARAMETER c_dcm_clk_feedback_port NONE
+SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
+SET_SIM_PARAMETER c_dcm_phase_shift 0
+SET_SIM_PARAMETER c_dcm_startup_wait FALSE
+SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
+SET_SIM_PARAMETER c_dcm_clk_out2_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out3_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
+SET_SIM_PARAMETER c_dcm_clkgen_notes None
+SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 1
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 4
+SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 20.0
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
+SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
+SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port NONE
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE
+SET_SIM_PARAMETER c_clock_mgr_type AUTO
+SET_SIM_PARAMETER c_override_mmcm 0
+SET_SIM_PARAMETER c_override_pll 0
+SET_SIM_PARAMETER c_override_dcm 0
+SET_SIM_PARAMETER c_override_dcm_clkgen 0
+SET_SIM_PARAMETER c_dcm_pll_cascade NONE
+SET_SIM_PARAMETER c_primary_port CLK_IN1
+SET_SIM_PARAMETER c_secondary_port CLK_IN2
+SET_SIM_PARAMETER c_clk_out1_port CLK_OUT1
+SET_SIM_PARAMETER c_clk_out2_port CLK_OUT2
+SET_SIM_PARAMETER c_clk_out3_port CLK_OUT3
+SET_SIM_PARAMETER c_clk_out4_port CLK_OUT4
+SET_SIM_PARAMETER c_clk_out5_port CLK_OUT5
+SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
+SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
+SET_SIM_PARAMETER c_reset_port RESET
+SET_SIM_PARAMETER c_locked_port LOCKED
+SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
+SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
+SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
+SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
+SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
+SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
+SET_SIM_PARAMETER c_power_down_port POWER_DOWN
+SET_SIM_PARAMETER c_daddr_port DADDR
+SET_SIM_PARAMETER c_dclk_port DCLK
+SET_SIM_PARAMETER c_drdy_port DRDY
+SET_SIM_PARAMETER c_dwe_port DWE
+SET_SIM_PARAMETER c_din_port DIN
+SET_SIM_PARAMETER c_dout_port DOUT
+SET_SIM_PARAMETER c_den_port DEN
+SET_SIM_PARAMETER c_psclk_port PSCLK
+SET_SIM_PARAMETER c_psen_port PSEN
+SET_SIM_PARAMETER c_psincdec_port PSINCDEC
+SET_SIM_PARAMETER c_psdone_port PSDONE
+SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
+SET_SIM_PARAMETER c_status_port STATUS
+SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
+SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
+SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
+SET_SIM_PARAMETER c_clkin1_jitter_ps 200.0
+SET_SIM_PARAMETER c_clkin2_jitter_ps 100.0
+SET_SIM_PARAMETER c_primitive MMCM
+SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
+SET_SIM_PARAMETER c_ss_mod_period 4000
+SET_CORE_NAME Clocking Wizard
+SET_CORE_VERSION 3.6
+SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
+SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
+SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
+SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
+SET_CORE_DATASHEET C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.507115344753.out b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.507115344753.out
new file mode 100644
index 0000000..a550f0f
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.507115344753.out
@@ -0,0 +1,505 @@
+SET_FLAG DEBUG FALSE
+SET_FLAG MODE BATCH
+SET_FLAG STANDALONE_MODE FALSE
+SET_PREFERENCE devicefamily spartan6
+SET_PREFERENCE device xc6slx9
+SET_PREFERENCE speedgrade -3
+SET_PREFERENCE package tqg144
+SET_PREFERENCE verilogsim true
+SET_PREFERENCE vhdlsim false
+SET_PREFERENCE simulationfiles Behavioral
+SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
+SET_PREFERENCE outputdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/
+SET_PREFERENCE workingdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/
+SET_PREFERENCE subworkingdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/
+SET_PREFERENCE transientdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/_dbg/
+SET_PREFERENCE designentry Verilog
+SET_PREFERENCE flowvendor Other
+SET_PREFERENCE addpads false
+SET_PREFERENCE projectname coregen
+SET_PREFERENCE formalverification false
+SET_PREFERENCE asysymbol false
+SET_PREFERENCE implementationfiletype Ngc
+SET_PREFERENCE foundationsym false
+SET_PREFERENCE createndf false
+SET_PREFERENCE removerpms false
+SET_PARAMETER Component_Name spartan6_pll
+SET_PARAMETER Use_Freq_Synth true
+SET_PARAMETER Use_Phase_Alignment false
+SET_PARAMETER Use_Min_Power false
+SET_PARAMETER Use_Dyn_Phase_Shift false
+SET_PARAMETER Use_Dyn_Reconfig false
+SET_PARAMETER Jitter_Sel No_Jitter
+SET_PARAMETER Use_Spread_Spectrum false
+SET_PARAMETER Use_Spread_Spectrum_1 false
+SET_PARAMETER Prim_In_Freq 50.000
+SET_PARAMETER In_Freq_Units Units_MHz
+SET_PARAMETER In_Jitter_Units Units_UI
+SET_PARAMETER Relative_Inclk REL_PRIMARY
+SET_PARAMETER Secondary_In_Freq 100.000
+SET_PARAMETER Jitter_Options UI
+SET_PARAMETER Clkin1_UI_Jitter 0.010
+SET_PARAMETER Clkin2_UI_Jitter 0.010
+SET_PARAMETER Prim_In_Jitter 0.010
+SET_PARAMETER Secondary_In_Jitter 0.010
+SET_PARAMETER Clkin1_Jitter_Ps 200.0
+SET_PARAMETER Clkin2_Jitter_Ps 100.0
+SET_PARAMETER Clkout2_Used false
+SET_PARAMETER Clkout3_Used false
+SET_PARAMETER Clkout4_Used false
+SET_PARAMETER Clkout5_Used false
+SET_PARAMETER Clkout6_Used false
+SET_PARAMETER Clkout7_Used false
+SET_PARAMETER Num_Out_Clks 1
+SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
+SET_PARAMETER primary_port CLK_IN1
+SET_PARAMETER CLK_OUT1_port CLK_OUT1
+SET_PARAMETER CLK_OUT2_port CLK_OUT2
+SET_PARAMETER CLK_OUT3_port CLK_OUT3
+SET_PARAMETER CLK_OUT4_port CLK_OUT4
+SET_PARAMETER CLK_OUT5_port CLK_OUT5
+SET_PARAMETER CLK_OUT6_port CLK_OUT6
+SET_PARAMETER CLK_OUT7_port CLK_OUT7
+SET_PARAMETER DADDR_port DADDR
+SET_PARAMETER DCLK_port DCLK
+SET_PARAMETER DRDY_port DRDY
+SET_PARAMETER DWE_port DWE
+SET_PARAMETER DIN_port DIN
+SET_PARAMETER DOUT_port DOUT
+SET_PARAMETER DEN_port DEN
+SET_PARAMETER PSCLK_port PSCLK
+SET_PARAMETER PSEN_port PSEN
+SET_PARAMETER PSINCDEC_port PSINCDEC
+SET_PARAMETER PSDONE_port PSDONE
+SET_PARAMETER Clkout1_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout1_Requested_Phase 0.000
+SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout2_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout2_Requested_Phase 0.000
+SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout3_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout3_Requested_Phase 0.000
+SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout4_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout4_Requested_Phase 0.000
+SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout5_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout5_Requested_Phase 0.000
+SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout6_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout6_Requested_Phase 0.000
+SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout7_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout7_Requested_Phase 0.000
+SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.000
+SET_PARAMETER Use_Max_I_Jitter false
+SET_PARAMETER Use_Min_O_Jitter false
+SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
+SET_PARAMETER Use_Inclk_Switchover false
+SET_PARAMETER secondary_port CLK_IN2
+SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
+SET_PARAMETER Clkout1_Drives BUFG
+SET_PARAMETER Clkout2_Drives BUFG
+SET_PARAMETER Clkout3_Drives BUFG
+SET_PARAMETER Clkout4_Drives BUFG
+SET_PARAMETER Clkout5_Drives BUFG
+SET_PARAMETER Clkout6_Drives BUFG
+SET_PARAMETER Clkout7_Drives BUFG
+SET_PARAMETER Feedback_Source FDBK_AUTO
+SET_PARAMETER Clkfb_In_Signaling SINGLE
+SET_PARAMETER CLKFB_IN_port CLKFB_IN
+SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
+SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
+SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
+SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
+SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
+SET_PARAMETER Platform nt64
+SET_PARAMETER Summary_Strings empty
+SET_PARAMETER Use_Locked false
+SET_PARAMETER calc_done DONE
+SET_PARAMETER Use_Reset false
+SET_PARAMETER Use_Power_Down false
+SET_PARAMETER Use_Status false
+SET_PARAMETER Use_Freeze false
+SET_PARAMETER Use_Clk_Valid false
+SET_PARAMETER Use_Inclk_Stopped false
+SET_PARAMETER Use_Clkfb_Stopped false
+SET_PARAMETER RESET_port RESET
+SET_PARAMETER LOCKED_port LOCKED
+SET_PARAMETER Power_Down_port POWER_DOWN
+SET_PARAMETER CLK_VALID_port CLK_VALID
+SET_PARAMETER STATUS_port STATUS
+SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
+SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
+SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
+SET_PARAMETER Override_Mmcm false
+SET_PARAMETER Mmcm_Notes None
+SET_PARAMETER Mmcm_Divclk_Divide 1
+SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
+SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
+SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
+SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkin1_Period 10.000
+SET_PARAMETER Mmcm_Clkin2_Period 10.000
+SET_PARAMETER Mmcm_Clkout4_Cascade false
+SET_PARAMETER Mmcm_Clock_Hold false
+SET_PARAMETER Mmcm_Compensation ZHOLD
+SET_PARAMETER Mmcm_Ref_Jitter1 0.010
+SET_PARAMETER Mmcm_Ref_Jitter2 0.010
+SET_PARAMETER Mmcm_Startup_Wait false
+SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
+SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout0_Phase 0.000
+SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout1_Divide 1
+SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout1_Phase 0.000
+SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout2_Divide 1
+SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout2_Phase 0.000
+SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout3_Divide 1
+SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout3_Phase 0.000
+SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout4_Divide 1
+SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout4_Phase 0.000
+SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout5_Divide 1
+SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout5_Phase 0.000
+SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout6_Divide 1
+SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout6_Phase 0.000
+SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
+SET_PARAMETER Override_Dcm false
+SET_PARAMETER Dcm_Notes None
+SET_PARAMETER Dcm_Clkdv_Divide 2.0
+SET_PARAMETER Dcm_Clkfx_Divide 1
+SET_PARAMETER Dcm_Clkfx_Multiply 2
+SET_PARAMETER Dcm_Clkin_Divide_By_2 false
+SET_PARAMETER Dcm_Clkin_Period 20.000
+SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
+SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
+SET_PARAMETER Dcm_Phase_Shift 0
+SET_PARAMETER Dcm_Clk_Feedback NONE
+SET_PARAMETER Dcm_Startup_Wait false
+SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
+SET_PARAMETER Dcm_Clk_Out2_Port CLKFX
+SET_PARAMETER Dcm_Clk_Out3_Port CLK0
+SET_PARAMETER Dcm_Clk_Out4_Port CLK0
+SET_PARAMETER Dcm_Clk_Out5_Port CLK0
+SET_PARAMETER Dcm_Clk_Out6_Port CLK0
+SET_PARAMETER Override_Dcm_Clkgen false
+SET_PARAMETER Dcm_Clkgen_Notes None
+SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 1
+SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 4
+SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
+SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
+SET_PARAMETER Dcm_Clkgen_Startup_Wait false
+SET_PARAMETER Dcm_Clkgen_Clkin_Period 10.000
+SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
+SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
+SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
+SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX
+SET_PARAMETER Override_Pll false
+SET_PARAMETER Pll_Notes None
+SET_PARAMETER Pll_Bandwidth OPTIMIZED
+SET_PARAMETER Pll_Clkfbout_Mult 8
+SET_PARAMETER Pll_Clkfbout_Phase 0.000
+SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
+SET_PARAMETER Pll_Divclk_Divide 1
+SET_PARAMETER Pll_Clkin_Period 20.0
+SET_PARAMETER Pll_Compensation INTERNAL
+SET_PARAMETER Pll_Ref_Jitter 0.010
+SET_PARAMETER Pll_Clkout0_Divide 4
+SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout0_Phase 0.000
+SET_PARAMETER Pll_Clkout1_Divide 40
+SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout1_Phase 0.000
+SET_PARAMETER Pll_Clkout2_Divide 1
+SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout2_Phase 0.000
+SET_PARAMETER Pll_Clkout3_Divide 1
+SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout3_Phase 0.000
+SET_PARAMETER Pll_Clkout4_Divide 1
+SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout4_Phase 0.000
+SET_PARAMETER Pll_Clkout5_Divide 1
+SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout5_Phase 0.000
+SET_PARAMETER dcm_pll_cascade NONE
+SET_PARAMETER clock_mgr_type AUTO
+SET_PARAMETER primtype_sel PLL_BASE
+SET_PARAMETER primitive MMCM
+SET_PARAMETER SS_Mode CENTER_HIGH
+SET_PARAMETER SS_Mod_Freq 250
+SET_SIM_PARAMETER c_clkout2_used 0
+SET_SIM_PARAMETER c_clkout3_used 0
+SET_SIM_PARAMETER c_clkout4_used 0
+SET_SIM_PARAMETER c_clkout5_used 0
+SET_SIM_PARAMETER c_clkout6_used 0
+SET_SIM_PARAMETER c_clkout7_used 0
+SET_SIM_PARAMETER c_use_clkout1_bar 0
+SET_SIM_PARAMETER c_use_clkout2_bar 0
+SET_SIM_PARAMETER c_use_clkout3_bar 0
+SET_SIM_PARAMETER c_use_clkout4_bar 0
+SET_SIM_PARAMETER c_component_name spartan6_pll
+SET_SIM_PARAMETER c_platform nt64
+SET_SIM_PARAMETER c_use_freq_synth 1
+SET_SIM_PARAMETER c_use_phase_alignment 0
+SET_SIM_PARAMETER c_prim_in_jitter 0.010
+SET_SIM_PARAMETER c_secondary_in_jitter 0.010
+SET_SIM_PARAMETER c_jitter_sel No_Jitter
+SET_SIM_PARAMETER c_use_min_power 0
+SET_SIM_PARAMETER c_use_min_o_jitter 0
+SET_SIM_PARAMETER c_use_max_i_jitter 0
+SET_SIM_PARAMETER c_use_dyn_phase_shift 0
+SET_SIM_PARAMETER c_use_inclk_switchover 0
+SET_SIM_PARAMETER c_use_dyn_reconfig 0
+SET_SIM_PARAMETER c_use_spread_spectrum 0
+SET_SIM_PARAMETER c_use_spread_spectrum_1 0
+SET_SIM_PARAMETER c_primtype_sel DCM_SP
+SET_SIM_PARAMETER c_use_clk_valid 0
+SET_SIM_PARAMETER c_prim_in_freq 50.000
+SET_SIM_PARAMETER c_in_freq_units Units_MHz
+SET_SIM_PARAMETER c_secondary_in_freq 100.000
+SET_SIM_PARAMETER c_feedback_source FDBK_AUTO
+SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
+SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
+SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
+SET_SIM_PARAMETER c_use_reset 0
+SET_SIM_PARAMETER c_use_locked 0
+SET_SIM_PARAMETER c_use_inclk_stopped 0
+SET_SIM_PARAMETER c_use_clkfb_stopped 0
+SET_SIM_PARAMETER c_use_power_down 0
+SET_SIM_PARAMETER c_use_status 0
+SET_SIM_PARAMETER c_use_freeze 0
+SET_SIM_PARAMETER c_num_out_clks 1
+SET_SIM_PARAMETER c_clkout1_drives BUFG
+SET_SIM_PARAMETER c_clkout2_drives BUFG
+SET_SIM_PARAMETER c_clkout3_drives BUFG
+SET_SIM_PARAMETER c_clkout4_drives BUFG
+SET_SIM_PARAMETER c_clkout5_drives BUFG
+SET_SIM_PARAMETER c_clkout6_drives BUFG
+SET_SIM_PARAMETER c_clkout7_drives BUFG
+SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock   Freq (MHz)    Input Jitter (UI)"
+SET_SIM_PARAMETER c_inclk_sum_row1 __primary__________50.000____________0.010
+SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock 
+SET_SIM_PARAMETER c_outclk_sum_row0a "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+SET_SIM_PARAMETER c_outclk_sum_row0b "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1___100.000______0.000______50.0______400.000____150.000
+SET_SIM_PARAMETER c_outclk_sum_row2 no_CLK_OUT2_output
+SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output 
+SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
+SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
+SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
+SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output 
+SET_SIM_PARAMETER c_clkout1_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout2_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout3_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout4_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout5_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout6_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout7_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout2_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout3_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout4_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout1_out_freq 100.000
+SET_SIM_PARAMETER c_clkout2_out_freq N/A
+SET_SIM_PARAMETER c_clkout3_out_freq N/A
+SET_SIM_PARAMETER c_clkout4_out_freq N/A
+SET_SIM_PARAMETER c_clkout5_out_freq N/A
+SET_SIM_PARAMETER c_clkout6_out_freq N/A
+SET_SIM_PARAMETER c_clkout7_out_freq N/A
+SET_SIM_PARAMETER c_clkout1_phase 0.000
+SET_SIM_PARAMETER c_clkout2_phase N/A
+SET_SIM_PARAMETER c_clkout3_phase N/A
+SET_SIM_PARAMETER c_clkout4_phase N/A
+SET_SIM_PARAMETER c_clkout5_phase N/A
+SET_SIM_PARAMETER c_clkout6_phase N/A
+SET_SIM_PARAMETER c_clkout7_phase N/A
+SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
+SET_SIM_PARAMETER c_clkout2_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout3_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
+SET_SIM_PARAMETER c_mmcm_notes None
+SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
+SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
+SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
+SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
+SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
+SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
+SET_SIM_PARAMETER c_mmcm_divclk_divide 1
+SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
+SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
+SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
+SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
+SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
+SET_SIM_PARAMETER c_pll_notes None
+SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
+SET_SIM_PARAMETER c_pll_clkfbout_mult 8
+SET_SIM_PARAMETER c_pll_clkin_period 20.0
+SET_SIM_PARAMETER c_pll_compensation INTERNAL
+SET_SIM_PARAMETER c_pll_divclk_divide 1
+SET_SIM_PARAMETER c_pll_ref_jitter 0.010
+SET_SIM_PARAMETER c_pll_clkout0_divide 4
+SET_SIM_PARAMETER c_pll_clkout1_divide 40
+SET_SIM_PARAMETER c_pll_clkout2_divide 1
+SET_SIM_PARAMETER c_pll_clkout3_divide 1
+SET_SIM_PARAMETER c_pll_clkout4_divide 1
+SET_SIM_PARAMETER c_pll_clkout5_divide 1
+SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout2_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
+SET_SIM_PARAMETER c_dcm_notes None
+SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
+SET_SIM_PARAMETER c_dcm_clkfx_divide 1
+SET_SIM_PARAMETER c_dcm_clkfx_multiply 2
+SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
+SET_SIM_PARAMETER c_dcm_clkin_period 20.0
+SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
+SET_SIM_PARAMETER c_dcm_clk_feedback NONE
+SET_SIM_PARAMETER c_dcm_clk_feedback_port NONE
+SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
+SET_SIM_PARAMETER c_dcm_phase_shift 0
+SET_SIM_PARAMETER c_dcm_startup_wait FALSE
+SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
+SET_SIM_PARAMETER c_dcm_clk_out2_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out3_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
+SET_SIM_PARAMETER c_dcm_clkgen_notes None
+SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 1
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 4
+SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 20.0
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
+SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
+SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port NONE
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE
+SET_SIM_PARAMETER c_clock_mgr_type AUTO
+SET_SIM_PARAMETER c_override_mmcm 0
+SET_SIM_PARAMETER c_override_pll 0
+SET_SIM_PARAMETER c_override_dcm 0
+SET_SIM_PARAMETER c_override_dcm_clkgen 0
+SET_SIM_PARAMETER c_dcm_pll_cascade NONE
+SET_SIM_PARAMETER c_primary_port CLK_IN1
+SET_SIM_PARAMETER c_secondary_port CLK_IN2
+SET_SIM_PARAMETER c_clk_out1_port CLK_OUT1
+SET_SIM_PARAMETER c_clk_out2_port CLK_OUT2
+SET_SIM_PARAMETER c_clk_out3_port CLK_OUT3
+SET_SIM_PARAMETER c_clk_out4_port CLK_OUT4
+SET_SIM_PARAMETER c_clk_out5_port CLK_OUT5
+SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
+SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
+SET_SIM_PARAMETER c_reset_port RESET
+SET_SIM_PARAMETER c_locked_port LOCKED
+SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
+SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
+SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
+SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
+SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
+SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
+SET_SIM_PARAMETER c_power_down_port POWER_DOWN
+SET_SIM_PARAMETER c_daddr_port DADDR
+SET_SIM_PARAMETER c_dclk_port DCLK
+SET_SIM_PARAMETER c_drdy_port DRDY
+SET_SIM_PARAMETER c_dwe_port DWE
+SET_SIM_PARAMETER c_din_port DIN
+SET_SIM_PARAMETER c_dout_port DOUT
+SET_SIM_PARAMETER c_den_port DEN
+SET_SIM_PARAMETER c_psclk_port PSCLK
+SET_SIM_PARAMETER c_psen_port PSEN
+SET_SIM_PARAMETER c_psincdec_port PSINCDEC
+SET_SIM_PARAMETER c_psdone_port PSDONE
+SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
+SET_SIM_PARAMETER c_status_port STATUS
+SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
+SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
+SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
+SET_SIM_PARAMETER c_clkin1_jitter_ps 200.0
+SET_SIM_PARAMETER c_clkin2_jitter_ps 100.0
+SET_SIM_PARAMETER c_primitive MMCM
+SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
+SET_SIM_PARAMETER c_ss_mod_period 4000
+SET_CORE_NAME Clocking Wizard
+SET_CORE_VERSION 3.6
+SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
+SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
+SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
+SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
+SET_CORE_DATASHEET C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>
diff --git a/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.736896934797.out b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.736896934797.out
new file mode 100644
index 0000000..a997e23
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/ipcore_dir/tmp/customization_gui.0.736896934797.out
@@ -0,0 +1,505 @@
+SET_FLAG DEBUG FALSE
+SET_FLAG MODE BATCH
+SET_FLAG STANDALONE_MODE FALSE
+SET_PREFERENCE devicefamily spartan6
+SET_PREFERENCE device xc6slx9
+SET_PREFERENCE speedgrade -3
+SET_PREFERENCE package tqg144
+SET_PREFERENCE verilogsim true
+SET_PREFERENCE vhdlsim false
+SET_PREFERENCE simulationfiles Behavioral
+SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
+SET_PREFERENCE outputdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/
+SET_PREFERENCE workingdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/
+SET_PREFERENCE subworkingdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/
+SET_PREFERENCE transientdirectory C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/_dbg/
+SET_PREFERENCE designentry Verilog
+SET_PREFERENCE flowvendor Other
+SET_PREFERENCE addpads false
+SET_PREFERENCE projectname coregen
+SET_PREFERENCE formalverification false
+SET_PREFERENCE asysymbol false
+SET_PREFERENCE implementationfiletype Ngc
+SET_PREFERENCE foundationsym false
+SET_PREFERENCE createndf false
+SET_PREFERENCE removerpms false
+SET_PARAMETER Component_Name spartan6_pll
+SET_PARAMETER Use_Freq_Synth true
+SET_PARAMETER Use_Phase_Alignment false
+SET_PARAMETER Use_Min_Power false
+SET_PARAMETER Use_Dyn_Phase_Shift false
+SET_PARAMETER Use_Dyn_Reconfig false
+SET_PARAMETER Jitter_Sel No_Jitter
+SET_PARAMETER Use_Spread_Spectrum false
+SET_PARAMETER Use_Spread_Spectrum_1 false
+SET_PARAMETER Prim_In_Freq 50.000
+SET_PARAMETER In_Freq_Units Units_MHz
+SET_PARAMETER In_Jitter_Units Units_UI
+SET_PARAMETER Relative_Inclk REL_PRIMARY
+SET_PARAMETER Secondary_In_Freq 100.000
+SET_PARAMETER Jitter_Options UI
+SET_PARAMETER Clkin1_UI_Jitter 0.010
+SET_PARAMETER Clkin2_UI_Jitter 0.010
+SET_PARAMETER Prim_In_Jitter 0.010
+SET_PARAMETER Secondary_In_Jitter 0.010
+SET_PARAMETER Clkin1_Jitter_Ps 200.0
+SET_PARAMETER Clkin2_Jitter_Ps 100.0
+SET_PARAMETER Clkout2_Used false
+SET_PARAMETER Clkout3_Used false
+SET_PARAMETER Clkout4_Used false
+SET_PARAMETER Clkout5_Used false
+SET_PARAMETER Clkout6_Used false
+SET_PARAMETER Clkout7_Used false
+SET_PARAMETER Num_Out_Clks 1
+SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
+SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
+SET_PARAMETER primary_port CLK_IN1
+SET_PARAMETER CLK_OUT1_port CLK_OUT1
+SET_PARAMETER CLK_OUT2_port CLK_OUT2
+SET_PARAMETER CLK_OUT3_port CLK_OUT3
+SET_PARAMETER CLK_OUT4_port CLK_OUT4
+SET_PARAMETER CLK_OUT5_port CLK_OUT5
+SET_PARAMETER CLK_OUT6_port CLK_OUT6
+SET_PARAMETER CLK_OUT7_port CLK_OUT7
+SET_PARAMETER DADDR_port DADDR
+SET_PARAMETER DCLK_port DCLK
+SET_PARAMETER DRDY_port DRDY
+SET_PARAMETER DWE_port DWE
+SET_PARAMETER DIN_port DIN
+SET_PARAMETER DOUT_port DOUT
+SET_PARAMETER DEN_port DEN
+SET_PARAMETER PSCLK_port PSCLK
+SET_PARAMETER PSEN_port PSEN
+SET_PARAMETER PSINCDEC_port PSINCDEC
+SET_PARAMETER PSDONE_port PSDONE
+SET_PARAMETER Clkout1_Requested_Out_Freq 110.000
+SET_PARAMETER Clkout1_Requested_Phase 0.000
+SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout2_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout2_Requested_Phase 0.000
+SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout3_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout3_Requested_Phase 0.000
+SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout4_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout4_Requested_Phase 0.000
+SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout5_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout5_Requested_Phase 0.000
+SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout6_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout6_Requested_Phase 0.000
+SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.000
+SET_PARAMETER Clkout7_Requested_Out_Freq 100.000
+SET_PARAMETER Clkout7_Requested_Phase 0.000
+SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.000
+SET_PARAMETER Use_Max_I_Jitter false
+SET_PARAMETER Use_Min_O_Jitter false
+SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
+SET_PARAMETER Use_Inclk_Switchover false
+SET_PARAMETER secondary_port CLK_IN2
+SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
+SET_PARAMETER Clkout1_Drives BUFG
+SET_PARAMETER Clkout2_Drives BUFG
+SET_PARAMETER Clkout3_Drives BUFG
+SET_PARAMETER Clkout4_Drives BUFG
+SET_PARAMETER Clkout5_Drives BUFG
+SET_PARAMETER Clkout6_Drives BUFG
+SET_PARAMETER Clkout7_Drives BUFG
+SET_PARAMETER Feedback_Source FDBK_AUTO
+SET_PARAMETER Clkfb_In_Signaling SINGLE
+SET_PARAMETER CLKFB_IN_port CLKFB_IN
+SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
+SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
+SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
+SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
+SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
+SET_PARAMETER Platform nt64
+SET_PARAMETER Summary_Strings empty
+SET_PARAMETER Use_Locked false
+SET_PARAMETER calc_done DONE
+SET_PARAMETER Use_Reset false
+SET_PARAMETER Use_Power_Down false
+SET_PARAMETER Use_Status false
+SET_PARAMETER Use_Freeze false
+SET_PARAMETER Use_Clk_Valid false
+SET_PARAMETER Use_Inclk_Stopped false
+SET_PARAMETER Use_Clkfb_Stopped false
+SET_PARAMETER RESET_port RESET
+SET_PARAMETER LOCKED_port LOCKED
+SET_PARAMETER Power_Down_port POWER_DOWN
+SET_PARAMETER CLK_VALID_port CLK_VALID
+SET_PARAMETER STATUS_port STATUS
+SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
+SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
+SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
+SET_PARAMETER Override_Mmcm false
+SET_PARAMETER Mmcm_Notes None
+SET_PARAMETER Mmcm_Divclk_Divide 1
+SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
+SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
+SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
+SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkin1_Period 10.000
+SET_PARAMETER Mmcm_Clkin2_Period 10.000
+SET_PARAMETER Mmcm_Clkout4_Cascade false
+SET_PARAMETER Mmcm_Clock_Hold false
+SET_PARAMETER Mmcm_Compensation ZHOLD
+SET_PARAMETER Mmcm_Ref_Jitter1 0.010
+SET_PARAMETER Mmcm_Ref_Jitter2 0.010
+SET_PARAMETER Mmcm_Startup_Wait false
+SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
+SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout0_Phase 0.000
+SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout1_Divide 1
+SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout1_Phase 0.000
+SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout2_Divide 1
+SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout2_Phase 0.000
+SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout3_Divide 1
+SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout3_Phase 0.000
+SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout4_Divide 1
+SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout4_Phase 0.000
+SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout5_Divide 1
+SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout5_Phase 0.000
+SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
+SET_PARAMETER Mmcm_Clkout6_Divide 1
+SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
+SET_PARAMETER Mmcm_Clkout6_Phase 0.000
+SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
+SET_PARAMETER Override_Dcm false
+SET_PARAMETER Dcm_Notes None
+SET_PARAMETER Dcm_Clkdv_Divide 2.0
+SET_PARAMETER Dcm_Clkfx_Divide 5
+SET_PARAMETER Dcm_Clkfx_Multiply 11
+SET_PARAMETER Dcm_Clkin_Divide_By_2 false
+SET_PARAMETER Dcm_Clkin_Period 20.000
+SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
+SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
+SET_PARAMETER Dcm_Phase_Shift 0
+SET_PARAMETER Dcm_Clk_Feedback NONE
+SET_PARAMETER Dcm_Startup_Wait false
+SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
+SET_PARAMETER Dcm_Clk_Out2_Port CLKFX
+SET_PARAMETER Dcm_Clk_Out3_Port CLK0
+SET_PARAMETER Dcm_Clk_Out4_Port CLK0
+SET_PARAMETER Dcm_Clk_Out5_Port CLK0
+SET_PARAMETER Dcm_Clk_Out6_Port CLK0
+SET_PARAMETER Override_Dcm_Clkgen false
+SET_PARAMETER Dcm_Clkgen_Notes None
+SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 1
+SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 4
+SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
+SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
+SET_PARAMETER Dcm_Clkgen_Startup_Wait false
+SET_PARAMETER Dcm_Clkgen_Clkin_Period 10.000
+SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
+SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
+SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
+SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX
+SET_PARAMETER Override_Pll false
+SET_PARAMETER Pll_Notes None
+SET_PARAMETER Pll_Bandwidth OPTIMIZED
+SET_PARAMETER Pll_Clkfbout_Mult 8
+SET_PARAMETER Pll_Clkfbout_Phase 0.000
+SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
+SET_PARAMETER Pll_Divclk_Divide 1
+SET_PARAMETER Pll_Clkin_Period 20.0
+SET_PARAMETER Pll_Compensation INTERNAL
+SET_PARAMETER Pll_Ref_Jitter 0.010
+SET_PARAMETER Pll_Clkout0_Divide 128
+SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout0_Phase 0.000
+SET_PARAMETER Pll_Clkout1_Divide 40
+SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout1_Phase 0.000
+SET_PARAMETER Pll_Clkout2_Divide 1
+SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout2_Phase 0.000
+SET_PARAMETER Pll_Clkout3_Divide 1
+SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout3_Phase 0.000
+SET_PARAMETER Pll_Clkout4_Divide 1
+SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout4_Phase 0.000
+SET_PARAMETER Pll_Clkout5_Divide 1
+SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
+SET_PARAMETER Pll_Clkout5_Phase 0.000
+SET_PARAMETER dcm_pll_cascade NONE
+SET_PARAMETER clock_mgr_type AUTO
+SET_PARAMETER primtype_sel PLL_BASE
+SET_PARAMETER primitive MMCM
+SET_PARAMETER SS_Mode CENTER_HIGH
+SET_PARAMETER SS_Mod_Freq 250
+SET_SIM_PARAMETER c_clkout2_used 0
+SET_SIM_PARAMETER c_clkout3_used 0
+SET_SIM_PARAMETER c_clkout4_used 0
+SET_SIM_PARAMETER c_clkout5_used 0
+SET_SIM_PARAMETER c_clkout6_used 0
+SET_SIM_PARAMETER c_clkout7_used 0
+SET_SIM_PARAMETER c_use_clkout1_bar 0
+SET_SIM_PARAMETER c_use_clkout2_bar 0
+SET_SIM_PARAMETER c_use_clkout3_bar 0
+SET_SIM_PARAMETER c_use_clkout4_bar 0
+SET_SIM_PARAMETER c_component_name spartan6_pll
+SET_SIM_PARAMETER c_platform nt64
+SET_SIM_PARAMETER c_use_freq_synth 1
+SET_SIM_PARAMETER c_use_phase_alignment 0
+SET_SIM_PARAMETER c_prim_in_jitter 0.010
+SET_SIM_PARAMETER c_secondary_in_jitter 0.010
+SET_SIM_PARAMETER c_jitter_sel No_Jitter
+SET_SIM_PARAMETER c_use_min_power 0
+SET_SIM_PARAMETER c_use_min_o_jitter 0
+SET_SIM_PARAMETER c_use_max_i_jitter 0
+SET_SIM_PARAMETER c_use_dyn_phase_shift 0
+SET_SIM_PARAMETER c_use_inclk_switchover 0
+SET_SIM_PARAMETER c_use_dyn_reconfig 0
+SET_SIM_PARAMETER c_use_spread_spectrum 0
+SET_SIM_PARAMETER c_use_spread_spectrum_1 0
+SET_SIM_PARAMETER c_primtype_sel DCM_SP
+SET_SIM_PARAMETER c_use_clk_valid 0
+SET_SIM_PARAMETER c_prim_in_freq 50.000
+SET_SIM_PARAMETER c_in_freq_units Units_MHz
+SET_SIM_PARAMETER c_secondary_in_freq 100.000
+SET_SIM_PARAMETER c_feedback_source FDBK_AUTO
+SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
+SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
+SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
+SET_SIM_PARAMETER c_use_reset 0
+SET_SIM_PARAMETER c_use_locked 0
+SET_SIM_PARAMETER c_use_inclk_stopped 0
+SET_SIM_PARAMETER c_use_clkfb_stopped 0
+SET_SIM_PARAMETER c_use_power_down 0
+SET_SIM_PARAMETER c_use_status 0
+SET_SIM_PARAMETER c_use_freeze 0
+SET_SIM_PARAMETER c_num_out_clks 1
+SET_SIM_PARAMETER c_clkout1_drives BUFG
+SET_SIM_PARAMETER c_clkout2_drives BUFG
+SET_SIM_PARAMETER c_clkout3_drives BUFG
+SET_SIM_PARAMETER c_clkout4_drives BUFG
+SET_SIM_PARAMETER c_clkout5_drives BUFG
+SET_SIM_PARAMETER c_clkout6_drives BUFG
+SET_SIM_PARAMETER c_clkout7_drives BUFG
+SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock   Freq (MHz)    Input Jitter (UI)"
+SET_SIM_PARAMETER c_inclk_sum_row1 __primary__________50.000____________0.010
+SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock 
+SET_SIM_PARAMETER c_outclk_sum_row0a "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+SET_SIM_PARAMETER c_outclk_sum_row0b "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1___110.000______0.000______50.0______381.818____150.000
+SET_SIM_PARAMETER c_outclk_sum_row2 no_CLK_OUT2_output
+SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output 
+SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output
+SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output
+SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
+SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output 
+SET_SIM_PARAMETER c_clkout1_requested_out_freq 110.000
+SET_SIM_PARAMETER c_clkout2_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout3_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout4_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout5_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout6_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout7_requested_out_freq 100.000
+SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout2_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout3_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout4_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
+SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.000
+SET_SIM_PARAMETER c_clkout1_out_freq 110.000
+SET_SIM_PARAMETER c_clkout2_out_freq N/A
+SET_SIM_PARAMETER c_clkout3_out_freq N/A
+SET_SIM_PARAMETER c_clkout4_out_freq N/A
+SET_SIM_PARAMETER c_clkout5_out_freq N/A
+SET_SIM_PARAMETER c_clkout6_out_freq N/A
+SET_SIM_PARAMETER c_clkout7_out_freq N/A
+SET_SIM_PARAMETER c_clkout1_phase 0.000
+SET_SIM_PARAMETER c_clkout2_phase N/A
+SET_SIM_PARAMETER c_clkout3_phase N/A
+SET_SIM_PARAMETER c_clkout4_phase N/A
+SET_SIM_PARAMETER c_clkout5_phase N/A
+SET_SIM_PARAMETER c_clkout6_phase N/A
+SET_SIM_PARAMETER c_clkout7_phase N/A
+SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
+SET_SIM_PARAMETER c_clkout2_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout3_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout4_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout5_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
+SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
+SET_SIM_PARAMETER c_mmcm_notes None
+SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
+SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
+SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
+SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
+SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
+SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
+SET_SIM_PARAMETER c_mmcm_divclk_divide 1
+SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
+SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
+SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
+SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
+SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
+SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
+SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
+SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
+SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
+SET_SIM_PARAMETER c_pll_notes None
+SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
+SET_SIM_PARAMETER c_pll_clkfbout_mult 8
+SET_SIM_PARAMETER c_pll_clkin_period 20.0
+SET_SIM_PARAMETER c_pll_compensation INTERNAL
+SET_SIM_PARAMETER c_pll_divclk_divide 1
+SET_SIM_PARAMETER c_pll_ref_jitter 0.010
+SET_SIM_PARAMETER c_pll_clkout0_divide 128
+SET_SIM_PARAMETER c_pll_clkout1_divide 40
+SET_SIM_PARAMETER c_pll_clkout2_divide 1
+SET_SIM_PARAMETER c_pll_clkout3_divide 1
+SET_SIM_PARAMETER c_pll_clkout4_divide 1
+SET_SIM_PARAMETER c_pll_clkout5_divide 1
+SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
+SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout2_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
+SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
+SET_SIM_PARAMETER c_dcm_notes None
+SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
+SET_SIM_PARAMETER c_dcm_clkfx_divide 5
+SET_SIM_PARAMETER c_dcm_clkfx_multiply 11
+SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
+SET_SIM_PARAMETER c_dcm_clkin_period 20.0
+SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
+SET_SIM_PARAMETER c_dcm_clk_feedback NONE
+SET_SIM_PARAMETER c_dcm_clk_feedback_port NONE
+SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
+SET_SIM_PARAMETER c_dcm_phase_shift 0
+SET_SIM_PARAMETER c_dcm_startup_wait FALSE
+SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
+SET_SIM_PARAMETER c_dcm_clk_out2_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out3_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out4_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out5_port NONE
+SET_SIM_PARAMETER c_dcm_clk_out6_port NONE
+SET_SIM_PARAMETER c_dcm_clkgen_notes None
+SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 1
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 4
+SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
+SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 20.0
+SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
+SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
+SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port NONE
+SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE
+SET_SIM_PARAMETER c_clock_mgr_type AUTO
+SET_SIM_PARAMETER c_override_mmcm 0
+SET_SIM_PARAMETER c_override_pll 0
+SET_SIM_PARAMETER c_override_dcm 0
+SET_SIM_PARAMETER c_override_dcm_clkgen 0
+SET_SIM_PARAMETER c_dcm_pll_cascade NONE
+SET_SIM_PARAMETER c_primary_port CLK_IN1
+SET_SIM_PARAMETER c_secondary_port CLK_IN2
+SET_SIM_PARAMETER c_clk_out1_port CLK_OUT1
+SET_SIM_PARAMETER c_clk_out2_port CLK_OUT2
+SET_SIM_PARAMETER c_clk_out3_port CLK_OUT3
+SET_SIM_PARAMETER c_clk_out4_port CLK_OUT4
+SET_SIM_PARAMETER c_clk_out5_port CLK_OUT5
+SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
+SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
+SET_SIM_PARAMETER c_reset_port RESET
+SET_SIM_PARAMETER c_locked_port LOCKED
+SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
+SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
+SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
+SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
+SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
+SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
+SET_SIM_PARAMETER c_power_down_port POWER_DOWN
+SET_SIM_PARAMETER c_daddr_port DADDR
+SET_SIM_PARAMETER c_dclk_port DCLK
+SET_SIM_PARAMETER c_drdy_port DRDY
+SET_SIM_PARAMETER c_dwe_port DWE
+SET_SIM_PARAMETER c_din_port DIN
+SET_SIM_PARAMETER c_dout_port DOUT
+SET_SIM_PARAMETER c_den_port DEN
+SET_SIM_PARAMETER c_psclk_port PSCLK
+SET_SIM_PARAMETER c_psen_port PSEN
+SET_SIM_PARAMETER c_psincdec_port PSINCDEC
+SET_SIM_PARAMETER c_psdone_port PSDONE
+SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
+SET_SIM_PARAMETER c_status_port STATUS
+SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
+SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
+SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
+SET_SIM_PARAMETER c_clkin1_jitter_ps 200.0
+SET_SIM_PARAMETER c_clkin2_jitter_ps 100.0
+SET_SIM_PARAMETER c_primitive MMCM
+SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
+SET_SIM_PARAMETER c_ss_mod_period 4000
+SET_CORE_NAME Clocking Wizard
+SET_CORE_VERSION 3.6
+SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
+SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
+SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
+SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
+SET_CORE_DATASHEET C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
+ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>
diff --git a/MCL86jr/FPGA/MCL86jr/iseconfig/MCL86jr.projectmgr b/MCL86jr/FPGA/MCL86jr/iseconfig/MCL86jr.projectmgr
new file mode 100644
index 0000000..4aef412
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/iseconfig/MCL86jr.projectmgr
@@ -0,0 +1,109 @@
+<?xml version='1.0' encoding='utf-8'?>
+<!--This is an ISE project configuration file.-->
+<!--It holds project specific layout data for the projectmgr plugin.-->
+<!--Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.-->
+<Project version="2" owner="projectmgr" name="MCL86jr" >
+   <!--This is an ISE project configuration file.-->
+   <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
+      <ClosedNodes>
+         <ClosedNodesVersion>2</ClosedNodesVersion>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem>MCL86jr (C:/MCL/MCL86/MCL86jr/src4synth/MCL86jr.v)</SelectedItem>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >1</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000020f000000020000000000000000000000000200000064ffffffff0000008100000003000000020000020f0000000100000003000000000000000100000003</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
+      <CurrentItem>MCL86jr (C:/MCL/MCL86/MCL86jr/src4synth/MCL86jr.v)</CurrentItem>
+   </ItemView>
+   <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
+         <ClosedNode>Design Utilities/Compile HDL Simulation Libraries</ClosedNode>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem>Design Utilities</SelectedItem>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000163000000010000000100000000000000000000000064ffffffff000000810000000000000001000001630000000100000000</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem>Design Utilities</CurrentItem>
+   </ItemView>
+   <ItemView guiview="File" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem>C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v</SelectedItem>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000028c000000040101000100000000000000000000000064ffffffff000000810000000000000004000001420000000100000000000000240000000100000000000000660000000100000000000000c00000000100000000</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem>C:\MCL\MCL86\MCL86jr\src4synth\MCL86jr.v</CurrentItem>
+   </ItemView>
+   <ItemView guiview="Library" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
+         <ClosedNode>work</ClosedNode>
+      </ClosedNodes>
+      <SelectedItems/>
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem>work</CurrentItem>
+   </ItemView>
+   <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
+         <ClosedNode>CORE Generator</ClosedNode>
+         <ClosedNode>Configure Target Device</ClosedNode>
+         <ClosedNode>Design Utilities/Compile HDL Simulation Libraries</ClosedNode>
+         <ClosedNode>Implement Design/Map</ClosedNode>
+         <ClosedNode>Implement Design/Place &amp; Route</ClosedNode>
+         <ClosedNode>Implement Design/Translate</ClosedNode>
+         <ClosedNode>Synthesize - XST</ClosedNode>
+         <ClosedNode>User Constraints</ClosedNode>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem>Generate Programming File</SelectedItem>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >7</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000153000000010000000100000000000000000000000064ffffffff000000810000000000000001000001530000000100000000</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem>Generate Programming File</CurrentItem>
+   </ItemView>
+   <SourceProcessView>000000ff00000000000000020000011b0000011b01000000040100000002</SourceProcessView>
+   <CurrentView>Implementation</CurrentView>
+   <ItemView engineview="SynthesisOnly" sourcetype="DESUT_XCO" guiview="Process" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
+         <ClosedNode>CORE Generator</ClosedNode>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem/>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000163000000010000000100000000000000000000000064ffffffff000000810000000000000001000001630000000100000000</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem/>
+   </ItemView>
+   <ItemView engineview="SynthesisOnly" sourcetype="DESUT_NGC" guiview="Process" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem/>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000163000000010000000100000000000000000000000064ffffffff000000810000000000000001000001630000000100000000</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem/>
+   </ItemView>
+</Project>
diff --git a/MCL86jr/FPGA/MCL86jr/iseconfig/MCL86jr.xreport b/MCL86jr/FPGA/MCL86jr/iseconfig/MCL86jr.xreport
new file mode 100644
index 0000000..7a81cd7
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/iseconfig/MCL86jr.xreport
@@ -0,0 +1,215 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<report-views version="2.0" >
+ <header>
+  <DateModified>2020-11-10T12:42:52</DateModified>
+  <ModuleName>MCL86jr</ModuleName>
+  <SummaryTimeStamp>2020-09-26T22:50:52</SummaryTimeStamp>
+  <SavedFilePath>C:/MCL/MCL86/MCL86jr/MCL86jr/iseconfig/MCL86jr.xreport</SavedFilePath>
+  <ImplementationReportsDirectory>C:/MCL/MCL86/MCL86jr/MCL86jr\</ImplementationReportsDirectory>
+  <DateInitialized>2020-09-12T20:32:54</DateInitialized>
+  <EnableMessageFiltering>false</EnableMessageFiltering>
+ </header>
+ <body>
+  <viewgroup label="Design Overview" >
+   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="MCL86jr_summary.html" label="Summary" >
+    <toc-item title="Design Overview" target="Design Overview" />
+    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
+    <toc-item title="Performance Summary" target="Performance Summary" />
+    <toc-item title="Failing Constraints" target="Failing Constraints" />
+    <toc-item title="Detailed Reports" target="Detailed Reports" />
+   </view>
+   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="MCL86jr_envsettings.html" label="System Settings" />
+   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="MCL86jr_map.xrpt" label="IOB Properties" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="MCL86jr_map.xrpt" label="Control Set Information" />
+   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="MCL86jr_map.xrpt" label="Module Level Utilization" />
+   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="MCL86jr.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
+   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="MCL86jr_par.xrpt" label="Pinout Report" />
+   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="MCL86jr_par.xrpt" label="Clock Report" />
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="MCL86jr.twx" label="Static Timing" />
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="MCL86jr_html/fit/report.htm" label="CPLD Fitter Report" />
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="MCL86jr_html/tim/report.htm" label="CPLD Timing Report" />
+  </viewgroup>
+  <viewgroup label="XPS Errors and Warnings" >
+   <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
+   <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
+   <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
+  </viewgroup>
+  <viewgroup label="XPS Reports" >
+   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
+   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
+   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
+   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="MCL86jr.log" label="System Log File" />
+  </viewgroup>
+  <viewgroup label="Errors and Warnings" >
+   <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
+   <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
+   <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
+   <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
+   <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
+   <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
+   <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
+   <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
+   <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
+   <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
+   <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
+  </viewgroup>
+  <viewgroup label="Detailed Reports" >
+   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="MCL86jr.syr" label="Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
+    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
+    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
+    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
+    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
+    <toc-item title="HDL Parsing" target="   HDL Parsing   " />
+    <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
+    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
+    <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
+    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
+    <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
+    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
+    <toc-item title="Partition Report" target="   Partition Report     " />
+    <toc-item title="Final Report" target="   Final Report   " />
+    <toc-item title="Design Summary" target="   Design Summary   " />
+    <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
+    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
+    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
+    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
+    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
+    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
+    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
+    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
+    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
+   </view>
+   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="MCL86jr.srr" label="Synplify Report" />
+   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="MCL86jr.prec_log" label="Precision Report" />
+   <view inputState="Synthesized" program="ngdbuild" type="Report" file="MCL86jr.bld" label="Translation Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Command Line" target="Command Line:" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
+   </view>
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="MCL86jr_map.mrp" label="Map Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
+    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
+    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
+    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
+    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
+    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
+    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
+    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
+    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
+    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
+    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
+    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
+    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="MCL86jr.par" label="Place and Route Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
+    <toc-item title="Router Information" target="Starting Router" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Clock Report" target="Generating Clock Report" />
+    <toc-item title="Timing Results" target="Timing Score:" />
+    <toc-item title="Final Summary" target="Peak Memory Usage:" />
+   </view>
+   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="MCL86jr.twr" label="Post-PAR Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="MCL86jr.rpt" label="CPLD Fitter Report (Text)" >
+    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
+    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
+    <toc-item title="Pin Resources" target="** Pin Resources **" />
+    <toc-item title="Global Resources" target="** Global Control Resources **" />
+   </view>
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="MCL86jr.tim" label="CPLD Timing Report (Text)" >
+    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
+    <toc-item title="Performance Summary" target="Performance Summary:" />
+   </view>
+   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="MCL86jr.pwr" label="Power Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Power summary" target="Power summary" />
+    <toc-item title="Thermal summary" target="Thermal summary" />
+   </view>
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="MCL86jr.bgn" label="Bitgen Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
+    <toc-item title="Final Summary" target="DRC detected" />
+   </view>
+  </viewgroup>
+  <viewgroup label="Secondary Reports" >
+   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
+   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/MCL86jr_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/MCL86jr_translate.nlf" label="Post-Translate Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="MCL86jr_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="MCL86jr_map.map" label="Map Log File" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Design Information" target="Design Information" />
+    <toc-item title="Design Summary" target="Design Summary" />
+   </view>
+   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
+   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MCL86jr_preroute.twr" label="Post-Map Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/MCL86jr_map.nlf" label="Post-Map Simulation Model Report" />
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MCL86jr_map.psr" label="Physical Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="MCL86jr_pad.txt" label="Pad Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="MCL86jr.unroutes" label="Unroutes Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MCL86jr_preroute.tsi" label="Post-Map Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MCL86jr.grf" label="Guide Results Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MCL86jr.dly" label="Asynchronous Delay Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MCL86jr.clk_rgn" label="Clock Region Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MCL86jr.tsi" label="Post-Place and Route Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="MCL86jr_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
+   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/MCL86jr_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="MCL86jr_sta.nlf" label="Primetime Netlist Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="MCL86jr.ibs" label="IBIS Model" >
+    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
+    <toc-item title="Component" target="Component " />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MCL86jr.lck" label="Back-annotate Pin Report" >
+    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
+    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MCL86jr.lpc" label="Locked Pin Constraints" >
+    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
+    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
+   </view>
+   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/MCL86jr_timesim.nlf" label="Post-Fit Simulation Model Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
+  </viewgroup>
+ </body>
+</report-views>
diff --git a/MCL86jr/FPGA/MCL86jr/mcl86jr.bgn b/MCL86jr/FPGA/MCL86jr/mcl86jr.bgn
new file mode 100644
index 0000000..7da1c4e
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/mcl86jr.bgn
@@ -0,0 +1,146 @@
+Release 14.7 - Bitgen P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Loading device for application Rf_Device from file '6slx9.nph' in environment
+C:\Xilinx\14.7\ISE_DS\ISE\.
+   "MCL86jr" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -3
+Opened constraints file MCL86jr.pcf.
+
+Wed Nov 11 19:11:46 2020
+
+C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -g INIT_9K:Yes -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:10 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:Yes -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 MCL86jr.ncd 
+
+INFO:Bitgen:341 - This design is using one or more 9K Block RAMs (RAMB8BWER). 
+   9K Block RAM initialization data, both user defined and default, requires a
+   special bit stream format.  For more information, please reference Xilinx
+   Answer Record 39999.
+Summary of Bitgen Options:
++----------------------+----------------------+
+| Option Name          | Current Setting      |
++----------------------+----------------------+
+| Compress             | (Not Specified)*     |
++----------------------+----------------------+
+| Readback             | (Not Specified)*     |
++----------------------+----------------------+
+| CRC                  | Enable**             |
++----------------------+----------------------+
+| DebugBitstream       | No**                 |
++----------------------+----------------------+
+| ConfigRate           | 10                   |
++----------------------+----------------------+
+| StartupClk           | Cclk**               |
++----------------------+----------------------+
+| DonePin              | Pullup*              |
++----------------------+----------------------+
+| ProgPin              | Pullup**             |
++----------------------+----------------------+
+| TckPin               | Pullup**             |
++----------------------+----------------------+
+| TdiPin               | Pullup**             |
++----------------------+----------------------+
+| TdoPin               | Pullup**             |
++----------------------+----------------------+
+| TmsPin               | Pullup**             |
++----------------------+----------------------+
+| UnusedPin            | Pulldown**           |
++----------------------+----------------------+
+| GWE_cycle            | 6**                  |
++----------------------+----------------------+
+| GTS_cycle            | 5**                  |
++----------------------+----------------------+
+| LCK_cycle            | NoWait**             |
++----------------------+----------------------+
+| DONE_cycle           | 4**                  |
++----------------------+----------------------+
+| Persist              | No*                  |
++----------------------+----------------------+
+| DriveDone            | No**                 |
++----------------------+----------------------+
+| DonePipe             | Yes                  |
++----------------------+----------------------+
+| Security             | None**               |
++----------------------+----------------------+
+| UserID               | 0xFFFFFFFF**         |
++----------------------+----------------------+
+| ActiveReconfig       | No*                  |
++----------------------+----------------------+
+| Partial              | (Not Specified)*     |
++----------------------+----------------------+
+| Encrypt              | No*                  |
++----------------------+----------------------+
+| Key0                 | pick*                |
++----------------------+----------------------+
+| StartCBC             | pick*                |
++----------------------+----------------------+
+| KeyFile              | (Not Specified)*     |
++----------------------+----------------------+
+| drive_awake          | No**                 |
++----------------------+----------------------+
+| Reset_on_err         | No**                 |
++----------------------+----------------------+
+| suspend_filter       | Yes*                 |
++----------------------+----------------------+
+| en_sw_gsr            | No**                 |
++----------------------+----------------------+
+| en_suspend           | No*                  |
++----------------------+----------------------+
+| sw_clk               | Startupclk**         |
++----------------------+----------------------+
+| sw_gwe_cycle         | 5**                  |
++----------------------+----------------------+
+| sw_gts_cycle         | 4**                  |
++----------------------+----------------------+
+| multipin_wakeup      | No**                 |
++----------------------+----------------------+
+| wakeup_mask          | 0x00*                |
++----------------------+----------------------+
+| ExtMasterCclk_en     | No**                 |
++----------------------+----------------------+
+| ExtMasterCclk_divide | 1*                   |
++----------------------+----------------------+
+| CrcCoverage          | No*                  |
++----------------------+----------------------+
+| glutmask             | Yes*                 |
++----------------------+----------------------+
+| next_config_addr     | 0x00000000*          |
++----------------------+----------------------+
+| next_config_new_mode | No*                  |
++----------------------+----------------------+
+| next_config_boot_mode | 001*                 |
++----------------------+----------------------+
+| next_config_register_write | Enable*              |
++----------------------+----------------------+
+| next_config_reboot   | Enable*              |
++----------------------+----------------------+
+| golden_config_addr   | 0x00000000*          |
++----------------------+----------------------+
+| failsafe_user        | 0x0000*              |
++----------------------+----------------------+
+| TIMER_CFG            | 0xFFFF               |
++----------------------+----------------------+
+| spi_buswidth         | 1**                  |
++----------------------+----------------------+
+| TimeStamp            | Default*             |
++----------------------+----------------------+
+| IEEE1532             | No*                  |
++----------------------+----------------------+
+| Binary               | No**                 |
++----------------------+----------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+There were 0 CONFIG constraint(s) processed from MCL86jr.pcf.
+
+
+Running DRC.
+INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance
+   with the CLKFX and CLKFX180 outputs of the DCM comp SPARTAN6PLL/dcm_sp_inst,
+   consult the device Data Sheet.
+WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
+   (RAMB8BWER).  9K Block RAM initialization data, both user defined and
+   default, may be incorrect and should not be used.  For more information,
+   please reference Xilinx Answer Record 39999.
+DRC detected 0 errors and 1 warnings.  Please see the previously displayed
+individual error or warning messages for more details.
+Creating bit map...
+Saving bit stream in "mcl86jr.bit".
+Bitstream generation is complete.
diff --git a/MCL86jr/FPGA/MCL86jr/mcl86jr.bit b/MCL86jr/FPGA/MCL86jr/mcl86jr.bit
new file mode 100644
index 0000000000000000000000000000000000000000..cdcb351300e245f3255d18cde8b1fc4bd5a2546f
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diff --git a/MCL86jr/FPGA/MCL86jr/mcl86jr.drc b/MCL86jr/FPGA/MCL86jr/mcl86jr.drc
new file mode 100644
index 0000000..db1f19a
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/mcl86jr.drc
@@ -0,0 +1,16 @@
+Release 14.7 Drc P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Wed Nov 11 19:11:46 2020
+
+drc -z MCL86jr.ncd MCL86jr.pcf
+
+INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance
+   with the CLKFX and CLKFX180 outputs of the DCM comp SPARTAN6PLL/dcm_sp_inst,
+   consult the device Data Sheet.
+WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
+   (RAMB8BWER).  9K Block RAM initialization data, both user defined and
+   default, may be incorrect and should not be used.  For more information,
+   please reference Xilinx Answer Record 39999.
+DRC detected 0 errors and 1 warnings.  Please see the previously displayed
+individual error or warning messages for more details.
diff --git a/MCL86jr/FPGA/MCL86jr/pa.fromHdl.tcl b/MCL86jr/FPGA/MCL86jr/pa.fromHdl.tcl
new file mode 100644
index 0000000..fd031a3
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/pa.fromHdl.tcl
@@ -0,0 +1,24 @@
+
+# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator
+
+create_project -name MCL86jr -dir "C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_1" -part xc6slx9tqg144-3
+set_param project.pinAheadLayout yes
+set srcset [get_property srcset [current_run -impl]]
+set_property target_constrs_file "MCL86jr.ucf" [current_fileset -constrset]
+set hdlfile [add_files [list {ipcore_dir/EU4Kx32.v}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+add_files [list {ipcore_dir/EU4Kx32.ngc}]
+set hdlfile [add_files [list {../src4synth/eu.v}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {../src4synth/biu_min.v}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {../src4synth/MCL86jr.v}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set_property top MCL86jr $srcset
+add_files [list {MCL86jr.ucf}] -fileset [get_property constrset [current_run]]
+add_files [list {ipcore_dir/EU4Kx32.ncf}] -fileset [get_property constrset [current_run]]
+open_rtl_design -part xc6slx9tqg144-3
diff --git a/MCL86jr/FPGA/MCL86jr/pa.fromNetlist.tcl b/MCL86jr/FPGA/MCL86jr/pa.fromNetlist.tcl
new file mode 100644
index 0000000..fb9698a
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/pa.fromNetlist.tcl
@@ -0,0 +1,12 @@
+
+# PlanAhead Launch Script for Post-Synthesis pin planning, created by Project Navigator
+
+create_project -name MCL86jr -dir "C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_3" -part xc6slx9tqg144-3
+set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+set_property edif_top_file "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ngc" [ get_property srcset [ current_run ] ]
+add_files -norecurse { {C:/MCL/MCL86/MCL86jr/MCL86jr} {ipcore_dir} }
+add_files [list {ipcore_dir/EU4Kx32.ncf}] -fileset [get_property constrset [current_run]]
+set_param project.pinAheadLayout  yes
+set_property target_constrs_file "MCL86jr.ucf" [current_fileset -constrset]
+add_files [list {MCL86jr.ucf}] -fileset [get_property constrset [current_run]]
+link_design
diff --git a/MCL86jr/FPGA/MCL86jr/par_usage_statistics.html b/MCL86jr/FPGA/MCL86jr/par_usage_statistics.html
new file mode 100644
index 0000000..5993c36
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/par_usage_statistics.html
@@ -0,0 +1,33 @@
+<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<xtag-section name="ParStatistics">
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1589</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>5837</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>5837</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>5708</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>4.2 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>4.6 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>8.2 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>8.8 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>19.7 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>23.0 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>33.2 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>33.2 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>33.2 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>33.3 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 11 CPU</xtag-par-property-name>=<xtag-par-property-value>33.8 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>5.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>7.7</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>7.5</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>6.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>3.3</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>3.2</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>10.7</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>7.6679</xtag-par-property-value></TD></TR>
+</xtag-section>
+</TABLE>
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead.ngc2edif.log b/MCL86jr/FPGA/MCL86jr/planAhead.ngc2edif.log
new file mode 100644
index 0000000..17e6594
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead.ngc2edif.log
@@ -0,0 +1,67 @@
+Release 14.7 - ngc2edif P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design EU4Kx32.ngc ...
+WARNING:NetListWriters:298 - No output is written to EU4Kx32.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file EU4Kx32.edif ...
+ngc2edif: Total memory usage is 79384 kilobytes
+
+Release 14.7 - ngc2edif P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design MCL86jr.ngc ...
+WARNING:NetListWriters:298 - No output is written to MCL86jr.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+WARNING:NetListWriters:306 - Signal bus EU_CORE/carry<16 : 3> on block MCL86jr
+   is not reconstructed, because there are some missing bus signals.
+WARNING:NetListWriters:306 - Signal bus
+   EU_CORE/eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT<12 : 0> on
+   block MCL86jr is not reconstructed, because there are some missing bus
+   signals.
+WARNING:NetListWriters:306 - Signal bus EU_CORE/eu_operand0<15 : 5> on block
+   MCL86jr is not reconstructed, because there are some missing bus signals.
+  finished :Prep
+Writing EDIF netlist file MCL86jr.edif ...
+ngc2edif: Total memory usage is 82712 kilobytes
+
+Release 14.7 - ngc2edif P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design EU4Kx32.ngc ...
+WARNING:NetListWriters:298 - No output is written to EU4Kx32.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file EU4Kx32.edif ...
+ngc2edif: Total memory usage is 78744 kilobytes
+
+Release 14.7 - ngc2edif P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design MCL86jr.ngc ...
+WARNING:NetListWriters:298 - No output is written to MCL86jr.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+WARNING:NetListWriters:306 - Signal bus EU_CORE/carry<16 : 3> on block MCL86jr
+   is not reconstructed, because there are some missing bus signals.
+WARNING:NetListWriters:306 - Signal bus EU_CORE/eu_operand0<15 : 5> on block
+   MCL86jr is not reconstructed, because there are some missing bus signals.
+  finished :Prep
+Writing EDIF netlist file MCL86jr.edif ...
+ngc2edif: Total memory usage is 82840 kilobytes
+
+Release 14.7 - ngc2edif P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design EU4Kx32.ngc ...
+WARNING:NetListWriters:298 - No output is written to EU4Kx32.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file EU4Kx32.edif ...
+ngc2edif: Total memory usage is 78744 kilobytes
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_pid2800.debug b/MCL86jr/FPGA/MCL86jr/planAhead_pid2800.debug
new file mode 100644
index 0000000..d3bf5e3
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_pid2800.debug
@@ -0,0 +1,72 @@
+#-------------------------------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013
+# Current time: 11/8/20 8:42:31 PM
+# Process ID: 2800
+# Platform: Windows
+#
+# This file is an indication that an internal application error occurred.
+# This information is useful for debugging. Please open a case with Xilinx
+# Technical Support with this file and a testcase attached.
+#-------------------------------------------------------------------------------
+11/8/20 8:42:31 PM
+ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
+HTclEvent: DEBUG_PORT_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: SIGNAL_MODIFY   Classes: ui.views.aR 
+HTclEvent: DEBUG_CORE_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: SIGNAL_BUS_MODIFY   Classes: ui.views.aR 
+
+	at ui.h.e.CF(SourceFile:217)
+	at ui.h.I.CF(SourceFile:702)
+	at ui.frmwork.HTclEventBroker.a(SourceFile:368)
+	at ui.frmwork.HTclEventBroker.bb(SourceFile:354)
+	at ui.project.a.een(SourceFile:759)
+	at ui.project.a.cleanup(SourceFile:608)
+	at ui.project.r.cleanup(SourceFile:631)
+	at ui.PlanAhead.aJj(SourceFile:335)
+	at ui.PlanAhead.a(SourceFile:1192)
+	at ui.frmwork.a.i.c(SourceFile:35)
+	at ui.frmwork.HTclEventBroker.a(SourceFile:233)
+	at ui.frmwork.HTclEventBroker.fireTclEvent(SourceFile:325)
+	at ui.frmwork.tcltasksi.task_manager_eval_in_tcl_or_bad_alloc(Native Method)
+	at ui.e.gY(SourceFile:195)
+	at ui.bl.run(SourceFile:882)
+	at ui.cd.run(SourceFile:1821)
+	at ui.views.F.aw.a(SourceFile:341)
+	at ui.cd.b(SourceFile:1809)
+	at ui.cd.a(SourceFile:1784)
+	at ui.PlanAhead.a(SourceFile:778)
+	at ui.aL.c(SourceFile:885)
+	at ui.aL.aHs(SourceFile:824)
+	at ui.bk.windowClosing(SourceFile:503)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:350)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.Window.processWindowEvent(Window.java:2051)
+	at javax.swing.JFrame.processWindowEvent(JFrame.java:296)
+	at java.awt.Window.processEvent(Window.java:2009)
+	at ui.aL.processEvent(SourceFile:1214)
+	at java.awt.Component.dispatchEventImpl(Component.java:4861)
+	at java.awt.Container.dispatchEventImpl(Container.java:2287)
+	at java.awt.Window.dispatchEventImpl(Window.java:2719)
+	at java.awt.Component.dispatchEvent(Component.java:4687)
+	at java.awt.EventQueue.dispatchEventImpl(EventQueue.java:729)
+	at java.awt.EventQueue.access$200(EventQueue.java:103)
+	at java.awt.EventQueue$3.run(EventQueue.java:688)
+	at java.awt.EventQueue$3.run(EventQueue.java:686)
+	at java.security.AccessController.doPrivileged(Native Method)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:87)
+	at java.awt.EventQueue$4.run(EventQueue.java:702)
+	at java.awt.EventQueue$4.run(EventQueue.java:700)
+	at java.security.AccessController.doPrivileged(Native Method)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76)
+	at java.awt.EventQueue.dispatchEvent(EventQueue.java:699)
+	at ui.frmwork.a.e.dispatchEvent(SourceFile:73)
+	at java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:242)
+	at java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:161)
+	at java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:150)
+	at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:146)
+	at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:138)
+	at java.awt.EventDispatchThread.run(EventDispatchThread.java:91)
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_pid6304.debug b/MCL86jr/FPGA/MCL86jr/planAhead_pid6304.debug
new file mode 100644
index 0000000..dd5138d
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_pid6304.debug
@@ -0,0 +1,74 @@
+#-------------------------------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013
+# Current time: 9/26/20 10:59:54 PM
+# Process ID: 6304
+# Platform: Windows
+#
+# This file is an indication that an internal application error occurred.
+# This information is useful for debugging. Please open a case with Xilinx
+# Technical Support with this file and a testcase attached.
+#-------------------------------------------------------------------------------
+9/26/20 10:59:54 PM
+ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
+HTclEvent: SIGNAL_BUS_MODIFY   Classes: ui.views.aR 
+HTclEvent: SIGNAL_MODIFY   Classes: ui.views.aR 
+HTclEvent: DEBUG_CORE_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: DEBUG_PORT_CONFIG_CHANGE   Classes: ui.views.aR 
+
+	at ui.h.e.CF(SourceFile:217)
+	at ui.h.I.CF(SourceFile:702)
+	at ui.frmwork.HTclEventBroker.a(SourceFile:368)
+	at ui.frmwork.HTclEventBroker.bb(SourceFile:354)
+	at ui.project.a.een(SourceFile:759)
+	at ui.project.a.cleanup(SourceFile:608)
+	at ui.project.r.cleanup(SourceFile:631)
+	at ui.PlanAhead.aJj(SourceFile:335)
+	at ui.PlanAhead.a(SourceFile:1192)
+	at ui.frmwork.a.i.c(SourceFile:35)
+	at ui.frmwork.HTclEventBroker.a(SourceFile:233)
+	at ui.frmwork.HTclEventBroker.fireTclEvent(SourceFile:325)
+	at ui.frmwork.tcltasksi.task_manager_eval_in_tcl_or_bad_alloc(Native Method)
+	at ui.e.gY(SourceFile:195)
+	at ui.bl.run(SourceFile:882)
+	at ui.cd.run(SourceFile:1821)
+	at ui.views.F.aw.a(SourceFile:341)
+	at ui.cd.b(SourceFile:1809)
+	at ui.cd.a(SourceFile:1784)
+	at ui.PlanAhead.a(SourceFile:778)
+	at ui.aL.c(SourceFile:885)
+	at ui.aL.aHs(SourceFile:824)
+	at ui.bk.windowClosing(SourceFile:503)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:350)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.Window.processWindowEvent(Window.java:2051)
+	at javax.swing.JFrame.processWindowEvent(JFrame.java:296)
+	at java.awt.Window.processEvent(Window.java:2009)
+	at ui.aL.processEvent(SourceFile:1214)
+	at java.awt.Component.dispatchEventImpl(Component.java:4861)
+	at java.awt.Container.dispatchEventImpl(Container.java:2287)
+	at java.awt.Window.dispatchEventImpl(Window.java:2719)
+	at java.awt.Component.dispatchEvent(Component.java:4687)
+	at java.awt.EventQueue.dispatchEventImpl(EventQueue.java:729)
+	at java.awt.EventQueue.access$200(EventQueue.java:103)
+	at java.awt.EventQueue$3.run(EventQueue.java:688)
+	at java.awt.EventQueue$3.run(EventQueue.java:686)
+	at java.security.AccessController.doPrivileged(Native Method)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:87)
+	at java.awt.EventQueue$4.run(EventQueue.java:702)
+	at java.awt.EventQueue$4.run(EventQueue.java:700)
+	at java.security.AccessController.doPrivileged(Native Method)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76)
+	at java.awt.EventQueue.dispatchEvent(EventQueue.java:699)
+	at ui.frmwork.a.e.dispatchEvent(SourceFile:73)
+	at java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:242)
+	at java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:161)
+	at java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:150)
+	at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:146)
+	at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:138)
+	at java.awt.EventDispatchThread.run(EventDispatchThread.java:91)
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_pid7676.debug b/MCL86jr/FPGA/MCL86jr/planAhead_pid7676.debug
new file mode 100644
index 0000000..fd391b1
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_pid7676.debug
@@ -0,0 +1,73 @@
+#-------------------------------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013
+# Current time: 9/26/20 10:57:23 PM
+# Process ID: 7676
+# Platform: Windows
+#
+# This file is an indication that an internal application error occurred.
+# This information is useful for debugging. Please open a case with Xilinx
+# Technical Support with this file and a testcase attached.
+#-------------------------------------------------------------------------------
+9/26/20 10:57:23 PM
+ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
+HTclEvent: DEBUG_CORE_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: DEBUG_PORT_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: SIGNAL_MODIFY   Classes: ui.views.aR 
+HTclEvent: SIGNAL_BUS_MODIFY   Classes: ui.views.aR 
+
+	at ui.h.e.CF(SourceFile:217)
+	at ui.h.I.CF(SourceFile:702)
+	at ui.frmwork.HTclEventBroker.a(SourceFile:368)
+	at ui.frmwork.HTclEventBroker.bb(SourceFile:354)
+	at ui.project.a.een(SourceFile:759)
+	at ui.project.a.cleanup(SourceFile:608)
+	at ui.project.r.cleanup(SourceFile:631)
+	at ui.PlanAhead.aJj(SourceFile:335)
+	at ui.PlanAhead.a(SourceFile:1192)
+	at ui.frmwork.a.i.c(SourceFile:35)
+	at ui.frmwork.HTclEventBroker.a(SourceFile:233)
+	at ui.frmwork.HTclEventBroker.fireTclEvent(SourceFile:325)
+	at ui.frmwork.tcltasksi.task_manager_eval_in_tcl_or_bad_alloc(Native Method)
+	at ui.e.gY(SourceFile:195)
+	at ui.bl.run(SourceFile:882)
+	at ui.cd.run(SourceFile:1821)
+	at ui.views.F.aw.a(SourceFile:335)
+	at ui.cd.b(SourceFile:1809)
+	at ui.cd.a(SourceFile:1784)
+	at ui.PlanAhead.a(SourceFile:778)
+	at ui.aL.c(SourceFile:885)
+	at ui.aL.aHs(SourceFile:824)
+	at ui.bk.windowClosing(SourceFile:503)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:350)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.Window.processWindowEvent(Window.java:2051)
+	at javax.swing.JFrame.processWindowEvent(JFrame.java:296)
+	at java.awt.Window.processEvent(Window.java:2009)
+	at ui.aL.processEvent(SourceFile:1214)
+	at java.awt.Component.dispatchEventImpl(Component.java:4861)
+	at java.awt.Container.dispatchEventImpl(Container.java:2287)
+	at java.awt.Window.dispatchEventImpl(Window.java:2719)
+	at java.awt.Component.dispatchEvent(Component.java:4687)
+	at java.awt.EventQueue.dispatchEventImpl(EventQueue.java:729)
+	at java.awt.EventQueue.access$200(EventQueue.java:103)
+	at java.awt.EventQueue$3.run(EventQueue.java:688)
+	at java.awt.EventQueue$3.run(EventQueue.java:686)
+	at java.security.AccessController.doPrivileged(Native Method)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:87)
+	at java.awt.EventQueue$4.run(EventQueue.java:702)
+	at java.awt.EventQueue$4.run(EventQueue.java:700)
+	at java.security.AccessController.doPrivileged(Native Method)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76)
+	at java.awt.EventQueue.dispatchEvent(EventQueue.java:699)
+	at ui.frmwork.a.e.dispatchEvent(SourceFile:73)
+	at java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:242)
+	at java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:161)
+	at java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:150)
+	at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:146)
+	at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:138)
+	at java.awt.EventDispatchThread.run(EventDispatchThread.java:91)
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_1/MCL86jr.data/constrs_1/fileset.xml b/MCL86jr/FPGA/MCL86jr/planAhead_run_1/MCL86jr.data/constrs_1/fileset.xml
new file mode 100644
index 0000000..2cef7e0
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_1/MCL86jr.data/constrs_1/fileset.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PPRDIR/../MCL86jr.ucf">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../ipcore_dir/EU4Kx32.ncf">
+      <FileInfo>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TargetConstrsFile" Val="$PPRDIR/../MCL86jr.ucf"/>
+      <Option Name="ConstrsType" Val="UCF"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_1/MCL86jr.data/sim_1/fileset.xml b/MCL86jr/FPGA/MCL86jr/planAhead_run_1/MCL86jr.data/sim_1/fileset.xml
new file mode 100644
index 0000000..0b3fd7a
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_1/MCL86jr.data/sim_1/fileset.xml
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="MCL86jr"/>
+      <Option Name="TopLib" Val="work"/>
+      <Option Name="TopRTLFile" Val="$PPRDIR/../../src4synth/MCL86jr.v"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+      <Option Name="SrcSet" Val="sources_1"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_1/MCL86jr.data/sources_1/fileset.xml b/MCL86jr/FPGA/MCL86jr/planAhead_run_1/MCL86jr.data/sources_1/fileset.xml
new file mode 100644
index 0000000..fa95031
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_1/MCL86jr.data/sources_1/fileset.xml
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PPRDIR/../ipcore_dir/EU4Kx32.v">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+        <Attr Name="UsedInSimulation" Val="1"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../ipcore_dir/EU4Kx32.ngc">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../../src4synth/eu.v">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+        <Attr Name="UsedInSimulation" Val="1"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../../src4synth/biu_min.v">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+        <Attr Name="UsedInSimulation" Val="1"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../../src4synth/MCL86jr.v">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+        <Attr Name="UsedInSimulation" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="MCL86jr"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_1/MCL86jr.data/wt/project.wpc b/MCL86jr/FPGA/MCL86jr/planAhead_run_1/MCL86jr.data/wt/project.wpc
new file mode 100644
index 0000000..5fed558
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_1/MCL86jr.data/wt/project.wpc
@@ -0,0 +1,4 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+6d6f64655f636f756e7465727c4953454d6f6465:1
+eof:
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_1/MCL86jr.data/wt/webtalk_pa.xml b/MCL86jr/FPGA/MCL86jr/planAhead_run_1/MCL86jr.data/wt/webtalk_pa.xml
new file mode 100644
index 0000000..d248a15
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_1/MCL86jr.data/wt/webtalk_pa.xml
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Sat Sep 26 22:57:18 2020">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="bc1bc9ee888c43f8992291fa5290dd91" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="PlanAhead Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="0" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="0" type="TclMode"/>
+<property name="ISEMode" value="14" type="ISEMode"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_1/MCL86jr.ppr b/MCL86jr/FPGA/MCL86jr/planAhead_run_1/MCL86jr.ppr
new file mode 100644
index 0000000..bb1e544
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_1/MCL86jr.ppr
@@ -0,0 +1,27 @@
+<?xml version="1.0"?>
+<!--Product Version: PlanAhead v14.7 (64-bit)-->
+<Project Version="4" Minor="36">
+	<FileSet Dir="sources_1" File="fileset.xml"/>
+	<FileSet Dir="constrs_1" File="fileset.xml"/>
+	<FileSet Dir="sim_1" File="fileset.xml"/>
+	<DefaultLaunch Dir="$PRUNDIR"/>
+	<DefaultPromote Dir="$PROMOTEDIR"/>
+	<Config>
+		<Option Name="Id" Val="8bfe1285b8bc42138c1b83209c7ba870"/>
+		<Option Name="Part" Val="xc6slx9tqg144-3"/>
+		<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+		<Option Name="TargetLanguage" Val="Verilog"/>
+		<Option Name="TargetSimulator" Val="ISim"/>
+		<Option Name="Board" Val=""/>
+		<Option Name="SourceMgmtMode" Val="All"/>
+		<Option Name="ActiveSimSet" Val="sim_1"/>
+		<Option Name="CxlOverwriteLibs" Val="1"/>
+		<Option Name="CxlFuncsim" Val="1"/>
+		<Option Name="CxlTimesim" Val="1"/>
+		<Option Name="CxlCore" Val="1"/>
+		<Option Name="CxlEdk" Val="0"/>
+		<Option Name="CxlExcludeCores" Val="1"/>
+		<Option Name="CxlExcludeSubLibs" Val="0"/>
+	</Config>
+</Project>
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_1/planAhead.jou b/MCL86jr/FPGA/MCL86jr/planAhead_run_1/planAhead.jou
new file mode 100644
index 0000000..88f7c17
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_1/planAhead.jou
@@ -0,0 +1,49 @@
+#-----------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013
+# Start of session at: Sat Sep 26 22:54:19 2020
+# Process ID: 7676
+# Log file: C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_1/planAhead.log
+# Journal file: C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_1/planAhead.jou
+#-----------------------------------------------------------
+start_gui
+source C:/MCL/MCL86/MCL86jr/MCL86jr/pa.fromHdl.tcl
+update_compile_order -fileset sim_1
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[8]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[7]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[6]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[5]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[4]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[3]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[2]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[1]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[0]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_1/planAhead.log b/MCL86jr/FPGA/MCL86jr/planAhead_run_1/planAhead.log
new file mode 100644
index 0000000..43f18d5
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_1/planAhead.log
@@ -0,0 +1,122 @@
+#-----------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013
+# Start of session at: Sat Sep 26 22:54:19 2020
+# Process ID: 7676
+# Log file: C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_1/planAhead.log
+# Journal file: C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_1/planAhead.jou
+#-----------------------------------------------------------
+INFO: [Common 17-78] Attempting to get a license: PlanAhead
+INFO: [Common 17-290] Got license for PlanAhead
+INFO: [Common 17-86] Your PlanAhead license expires in -1275 day(s)
+INFO: [Device 21-36] Loading parts and site information from C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
+Parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+Finished parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+start_gui
+source C:/MCL/MCL86/MCL86jr/MCL86jr/pa.fromHdl.tcl
+# create_project -name MCL86jr -dir "C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_1" -part xc6slx9tqg144-3
+create_project: Time (s): elapsed = 00:00:06 . Memory (MB): peak = 420.852 ; gain = 66.055
+# set_param project.pinAheadLayout yes
+# set srcset [get_property srcset [current_run -impl]]
+# set_property target_constrs_file "MCL86jr.ucf" [current_fileset -constrset]
+Adding file 'C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ucf' to fileset 'constrs_1'
+# set hdlfile [add_files [list {ipcore_dir/EU4Kx32.v}]]
+# set_property file_type Verilog $hdlfile
+# set_property library work $hdlfile
+# add_files [list {ipcore_dir/EU4Kx32.ngc}]
+# set hdlfile [add_files [list {../src4synth/eu.v}]]
+# set_property file_type Verilog $hdlfile
+# set_property library work $hdlfile
+# set hdlfile [add_files [list {../src4synth/biu_min.v}]]
+# set_property file_type Verilog $hdlfile
+# set_property library work $hdlfile
+# set hdlfile [add_files [list {../src4synth/MCL86jr.v}]]
+# set_property file_type Verilog $hdlfile
+# set_property library work $hdlfile
+# set_property top MCL86jr $srcset
+# add_files [list {MCL86jr.ucf}] -fileset [get_property constrset [current_run]]
+# add_files [list {ipcore_dir/EU4Kx32.ncf}] -fileset [get_property constrset [current_run]]
+# open_rtl_design -part xc6slx9tqg144-3
+Using Verific elaboration
+Parsing VHDL file "C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/lib/synplify/synattr.vhd" into library synplify
+Analyzing Verilog file "C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/EU4Kx32.v" into library work
+Analyzing Verilog file "C:/MCL/MCL86/MCL86jr/src4synth/eu.v" into library work
+Analyzing Verilog file "C:/MCL/MCL86/MCL86jr/src4synth/biu_min.v" into library work
+Analyzing Verilog file "C:/MCL/MCL86/MCL86jr/src4synth/MCL86jr.v" into library work
+Release 14.7 - ngc2edif P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design EU4Kx32.ngc ...
+WARNING:NetListWriters:298 - No output is written to EU4Kx32.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file EU4Kx32.edif ...
+ngc2edif: Total memory usage is 79384 kilobytes
+
+Reading core file 'C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/EU4Kx32.ngc' for (cell view 'EU4Kx32', library 'work', file 'EU4Kx32.v')
+Parsing EDIF File [./.Xil/PlanAhead-7676-MicroCoreLabs/ngc2edif/EU4Kx32.edif]
+Finished Parsing EDIF File [./.Xil/PlanAhead-7676-MicroCoreLabs/ngc2edif/EU4Kx32.edif]
+Loading clock regions from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/tqg144/Package.xml
+Loading io standards from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan6/IOStandards.xml
+Loading device configuration modes from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/ConfigModes.xml
+Loading list of drcs for the architecture : C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ucf]
+Finished Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ucf]
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Phase 0 | Netlist Checksum: 0a7e0a75
+open_rtl_design: Time (s): elapsed = 00:00:21 . Memory (MB): peak = 603.004 ; gain = 171.250
+update_compile_order -fileset sim_1
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[8]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[7]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[6]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[5]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[4]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[3]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[2]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[1]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[0]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+exit
+ERROR: [PlanAhead 12-106] *** Exception: ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
+HTclEvent: DEBUG_CORE_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: DEBUG_PORT_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: SIGNAL_MODIFY   Classes: ui.views.aR 
+HTclEvent: SIGNAL_BUS_MODIFY   Classes: ui.views.aR 
+ (See C:/MCL/MCL86/MCL86jr/MCL86jr\planAhead_pid7676.debug)
+ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
+INFO: [Common 17-206] Exiting PlanAhead at Sat Sep 26 22:57:24 2020...
+INFO: [Common 17-83] Releasing license: PlanAhead
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_1/planAhead_run.log b/MCL86jr/FPGA/MCL86jr/planAhead_run_1/planAhead_run.log
new file mode 100644
index 0000000..3a8e77f
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_1/planAhead_run.log
@@ -0,0 +1,113 @@
+
+****** PlanAhead v14.7 (64-bit)
+  **** Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013
+    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
+
+INFO: [Common 17-78] Attempting to get a license: PlanAhead
+INFO: [Common 17-290] Got license for PlanAhead
+INFO: [Common 17-86] Your PlanAhead license expires in -1275 day(s)
+INFO: [Device 21-36] Loading parts and site information from C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
+Parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+Finished parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+start_gui
+source C:/MCL/MCL86/MCL86jr/MCL86jr/pa.fromHdl.tcl
+# create_project -name MCL86jr -dir "C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_1" -part xc6slx9tqg144-3
+create_project: Time (s): elapsed = 00:00:06 . Memory (MB): peak = 420.852 ; gain = 66.055
+# set_param project.pinAheadLayout yes
+# set srcset [get_property srcset [current_run -impl]]
+# set_property target_constrs_file "MCL86jr.ucf" [current_fileset -constrset]
+Adding file 'C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ucf' to fileset 'constrs_1'
+# set hdlfile [add_files [list {ipcore_dir/EU4Kx32.v}]]
+# set_property file_type Verilog $hdlfile
+# set_property library work $hdlfile
+# add_files [list {ipcore_dir/EU4Kx32.ngc}]
+# set hdlfile [add_files [list {../src4synth/eu.v}]]
+# set_property file_type Verilog $hdlfile
+# set_property library work $hdlfile
+# set hdlfile [add_files [list {../src4synth/biu_min.v}]]
+# set_property file_type Verilog $hdlfile
+# set_property library work $hdlfile
+# set hdlfile [add_files [list {../src4synth/MCL86jr.v}]]
+# set_property file_type Verilog $hdlfile
+# set_property library work $hdlfile
+# set_property top MCL86jr $srcset
+# add_files [list {MCL86jr.ucf}] -fileset [get_property constrset [current_run]]
+# add_files [list {ipcore_dir/EU4Kx32.ncf}] -fileset [get_property constrset [current_run]]
+# open_rtl_design -part xc6slx9tqg144-3
+Using Verific elaboration
+Parsing VHDL file "C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/lib/synplify/synattr.vhd" into library synplify
+Analyzing Verilog file "C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/EU4Kx32.v" into library work
+Analyzing Verilog file "C:/MCL/MCL86/MCL86jr/src4synth/eu.v" into library work
+Analyzing Verilog file "C:/MCL/MCL86/MCL86jr/src4synth/biu_min.v" into library work
+Analyzing Verilog file "C:/MCL/MCL86/MCL86jr/src4synth/MCL86jr.v" into library work
+Release 14.7 - ngc2edif P.20131013 (nt64)

+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

+Reading design EU4Kx32.ngc ...

+WARNING:NetListWriters:298 - No output is written to EU4Kx32.xncf, ignored.

+Processing design ...

+   Preping design's networks ...

+   Preping design's macros ...

+  finished :Prep

+Writing EDIF netlist file EU4Kx32.edif ...

+ngc2edif: Total memory usage is 79384 kilobytes

+

+Reading core file 'C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/EU4Kx32.ngc' for (cell view 'EU4Kx32', library 'work', file 'EU4Kx32.v')
+Parsing EDIF File [./.Xil/PlanAhead-7676-MicroCoreLabs/ngc2edif/EU4Kx32.edif]
+Finished Parsing EDIF File [./.Xil/PlanAhead-7676-MicroCoreLabs/ngc2edif/EU4Kx32.edif]
+Loading clock regions from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/tqg144/Package.xml
+Loading io standards from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan6/IOStandards.xml
+Loading device configuration modes from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/ConfigModes.xml
+Loading list of drcs for the architecture : C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ucf]
+Finished Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ucf]
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Phase 0 | Netlist Checksum: 0a7e0a75
+open_rtl_design: Time (s): elapsed = 00:00:21 . Memory (MB): peak = 603.004 ; gain = 171.250
+update_compile_order -fileset sim_1
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[8]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[7]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[6]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[5]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[4]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[3]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[2]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[1]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[0]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed true [get_ports [list  {SRAM_A[9]}]]
+set_property is_loc_fixed false [get_ports [list  {SRAM_A[9]}]]
+exit
+ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
+INFO: [Common 17-206] Exiting PlanAhead at Sat Sep 26 22:57:24 2020...
+INFO: [Common 17-83] Releasing license: PlanAhead
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/cache/EU4Kx32_ngc_zx.edif b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/cache/EU4Kx32_ngc_zx.edif
new file mode 100644
index 0000000..612fd28
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/cache/EU4Kx32_ngc_zx.edif
@@ -0,0 +1,2660 @@
+(edif EU4Kx32
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2020 9 26 22 58 6)
+      (program "Xilinx ngc2edif" (version "P.20131013"))
+      (author "Xilinx. Inc ")
+      (comment "This EDIF netlist is to be used within supported synthesis tools")
+      (comment "for determining resource/timing estimates of the design component")
+      (comment "represented by this netlist.")
+      (comment "Command line: -mdp2sp -w -secure EU4Kx32.ngc EU4Kx32.edif ")))
+  (external UNISIMS
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell VCC
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port P
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell GND
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port G
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell RAMB16BWER
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port REGCEA
+              (direction INPUT)
+            )
+            (port CLKA
+              (direction INPUT)
+            )
+            (port ENB
+              (direction INPUT)
+            )
+            (port RSTB
+              (direction INPUT)
+            )
+            (port CLKB
+              (direction INPUT)
+            )
+            (port REGCEB
+              (direction INPUT)
+            )
+            (port RSTA
+              (direction INPUT)
+            )
+            (port ENA
+              (direction INPUT)
+            )
+            (port (array (rename DIPA "DIPA<3:0>") 4)
+              (direction INPUT))
+            (port (array (rename WEA "WEA<3:0>") 4)
+              (direction INPUT))
+            (port (array (rename DOA "DOA<31:0>") 32)
+              (direction OUTPUT))
+            (port (array (rename ADDRA "ADDRA<13:0>") 14)
+              (direction INPUT))
+            (port (array (rename ADDRB "ADDRB<13:0>") 14)
+              (direction INPUT))
+            (port (array (rename DIB "DIB<31:0>") 32)
+              (direction INPUT))
+            (port (array (rename DOPA "DOPA<3:0>") 4)
+              (direction OUTPUT))
+            (port (array (rename DIPB "DIPB<3:0>") 4)
+              (direction INPUT))
+            (port (array (rename DOPB "DOPB<3:0>") 4)
+              (direction OUTPUT))
+            (port (array (rename DOB "DOB<31:0>") 32)
+              (direction OUTPUT))
+            (port (array (rename WEB "WEB<3:0>") 4)
+              (direction INPUT))
+            (port (array (rename DIA "DIA<31:0>") 32)
+              (direction INPUT))
+          )
+      )
+    )
+    (cell RAMB8BWER
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port RSTBRST
+              (direction INPUT)
+            )
+            (port ENBRDEN
+              (direction INPUT)
+            )
+            (port REGCEA
+              (direction INPUT)
+            )
+            (port ENAWREN
+              (direction INPUT)
+            )
+            (port CLKAWRCLK
+              (direction INPUT)
+            )
+            (port CLKBRDCLK
+              (direction INPUT)
+            )
+            (port REGCEBREGCE
+              (direction INPUT)
+            )
+            (port RSTA
+              (direction INPUT)
+            )
+            (port (array (rename WEAWEL "WEAWEL<1:0>") 2)
+              (direction INPUT))
+            (port (array (rename DOADO "DOADO<15:0>") 16)
+              (direction OUTPUT))
+            (port (array (rename DOPADOP "DOPADOP<1:0>") 2)
+              (direction OUTPUT))
+            (port (array (rename DOPBDOP "DOPBDOP<1:0>") 2)
+              (direction OUTPUT))
+            (port (array (rename WEBWEU "WEBWEU<1:0>") 2)
+              (direction INPUT))
+            (port (array (rename ADDRAWRADDR "ADDRAWRADDR<12:0>") 13)
+              (direction INPUT))
+            (port (array (rename DIPBDIP "DIPBDIP<1:0>") 2)
+              (direction INPUT))
+            (port (array (rename DIBDI "DIBDI<15:0>") 16)
+              (direction INPUT))
+            (port (array (rename DIADI "DIADI<15:0>") 16)
+              (direction INPUT))
+            (port (array (rename ADDRBRDADDR "ADDRBRDADDR<12:0>") 13)
+              (direction INPUT))
+            (port (array (rename DOBDO "DOBDO<15:0>") 16)
+              (direction OUTPUT))
+            (port (array (rename DIPADIP "DIPADIP<1:0>") 2)
+              (direction INPUT))
+          )
+      )
+    )
+    (cell FDE
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port CE
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT3
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell INV
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+  )
+
+  (library EU4Kx32_lib
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell EU4Kx32
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port clka
+              (direction INPUT)
+            )
+            (port (array (rename addra "addra<11:0>") 12)
+              (direction INPUT))
+            (port (array (rename douta "douta<31:0>") 32)
+              (direction OUTPUT))
+            (designator "6slx9tqg144-2")
+            (property TYPE (string "EU4Kx32") (owner "Xilinx"))
+            (property BUS_INFO (string "12:INPUT:addra<11:0>") (owner "Xilinx"))
+            (property BUS_INFO (string "32:OUTPUT:douta<31:0>") (owner "Xilinx"))
+            (property X_CORE_INFO (string "blk_mem_gen_v7_3, Xilinx CORE Generator 14.7") (owner "Xilinx"))
+            (property CHECK_LICENSE_TYPE (string "EU4Kx32,blk_mem_gen_v7_3,{}") (owner "Xilinx"))
+            (property CORE_GENERATION_INFO (string "EU4Kx32,blk_mem_gen_v7_3,{c_addra_width=12,c_addrb_width=12,c_algorithm=1,c_axi_id_width=4,c_axi_slave_type=0,c_axi_type=1,c_byte_size=9,c_common_clk=0,c_default_data=0,c_disable_warn_bhv_coll=0,c_disable_warn_bhv_range=0,c_elaboration_dir=C_/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/,c_enable_32bit_address=0,c_family=spartan6,c_has_axi_id=0,c_has_ena=0,c_has_enb=0,c_has_injecterr=0,c_has_mem_output_regs_a=0,c_has_mem_output_regs_b=0,c_has_mux_output_regs_a=0,c_has_mux_output_regs_b=0,c_has_regcea=0,c_has_regceb=0,c_has_rsta=0,c_has_rstb=0,c_has_softecc_input_regs_a=0,c_has_softecc_output_regs_b=0,c_init_file=BlankString,c_init_file_name=EU4Kx32.mif,c_inita_val=0,c_initb_val=0,c_interface_type=0,c_load_init_file=1,c_mem_type=3,c_mux_pipeline_stages=0,c_prim_type=1,c_read_depth_a=4096,c_read_depth_b=4096,c_read_width_a=32,c_read_width_b=32,c_rst_priority_a=CE,c_rst_priority_b=CE,c_rst_type=SYNC,c_rstram_a=0,c_rstram_b=0,c_sim_collision_check=ALL,c_use_bram_block=0,c_use_byte_wea=0,c_use_byte_web=0,c_use_default_data=0,c_use_ecc=0,c_use_softecc=0,c_wea_width=1,c_web_width=1,c_write_depth_a=4096,c_write_depth_b=4096,c_write_mode_a=WRITE_FIRST,c_write_mode_b=WRITE_FIRST,c_write_width_a=32,c_write_width_b=32,c_xdevicefamily=spartan6}") (owner "Xilinx"))
+            (property SHREG_MIN_SIZE (string "-1") (owner "Xilinx"))
+            (property SHREG_EXTRACT_NGC (string "Yes") (owner "Xilinx"))
+            (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
+            (property NLW_MACRO_TAG (integer 0) (owner "Xilinx"))
+            (property NLW_MACRO_ALIAS (string "EU4Kx32_EU4Kx32") (owner "Xilinx"))
+          )
+          (contents
+            (instance XST_VCC
+              (viewRef view_1 (cellRef VCC (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance XST_GND
+              (viewRef view_1 (cellRef GND (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram")
+              (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRA<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIA<31:0>") (owner "Xilinx"))
+              (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx"))
+              (property DATA_WIDTH_A (integer 9) (owner "Xilinx"))
+              (property DATA_WIDTH_B (integer 9) (owner "Xilinx"))
+              (property DOA_REG (integer 0) (owner "Xilinx"))
+              (property DOB_REG (integer 0) (owner "Xilinx"))
+              (property EN_RSTRAM_A (string "FALSE") (owner "Xilinx"))
+              (property EN_RSTRAM_B (string "FALSE") (owner "Xilinx"))
+              (property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_05 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_06 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_07 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_00 (string "0000002052B2B7B10000002052B2B7B1000000002052B2B7000000002052B2B7") (owner "Xilinx"))
+              (property INIT_01 (string "000000000020B2B70000000020B322B7000000000020B2B7000000000020B2B7") (owner "Xilinx"))
+              (property INIT_02 (string "205352B22222B7B1205352B22222B7B100205352B22222B700205352B22222B7") (owner "Xilinx"))
+              (property INIT_03 (string "00002053B22222B7002053B22222B7B100002053B22222B700002053B22222B7") (owner "Xilinx"))
+              (property INIT_04 (string "00205352B222B7B100205352B222B7B10000205352B222B70000205352B222B7") (owner "Xilinx"))
+              (property INIT_05 (string "0000002053B222B700002053B222B7B10000002053B222B70000002053B222B7") (owner "Xilinx"))
+              (property INIT_06 (string "20A2738220A6738620A4738420A073800020A2820020A6860020A4840020A080") (owner "Xilinx"))
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+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
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+              (property WRITE_MODE_A (string "WRITE_FIRST") (owner "Xilinx"))
+              (property WRITE_MODE_B (string "WRITE_FIRST") (owner "Xilinx"))
+            )
+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram")
+              (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS)))
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+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
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+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
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+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
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+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux71 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux71")
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+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux151 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux151")
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+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux161 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux161")
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+              (property INIT (string "E4") (owner "Xilinx"))
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+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux171 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux171")
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+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux181 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux181")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
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+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux191 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux191")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
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+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux201 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux201")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
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+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux211 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux211")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
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+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux221 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux221")
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+              (property INIT_B (string "000000000") (owner "Xilinx"))
+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
+              (property RSTTYPE (string "SYNC") (owner "Xilinx"))
+              (property RST_PRIORITY_A (string "CE") (owner "Xilinx"))
+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
+              (property SRVAL_A (string "000000000") (owner "Xilinx"))
+              (property SRVAL_B (string "000000000") (owner "Xilinx"))
+              (property WRITE_MODE_A (string "WRITE_FIRST") (owner "Xilinx"))
+              (property WRITE_MODE_B (string "WRITE_FIRST") (owner "Xilinx"))
+            )
+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_bindec_a_bindec_inst_a_ADDR_0__GND_16_o_equal_1_o1_INV_0 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/ADDR[0]_GND_16_o_equal_1_o1_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (net N0
+              (joined
+                (portRef P (instanceRef XST_VCC))
+                (portRef CE (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_sel_pipe_0_renamed_0))
+                (portRef ENAWREN
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef ENA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net N1
+              (joined
+                (portRef G (instanceRef XST_GND))
+                (portRef (member ADDRAWRADDR 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIPADIP 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIPADIP 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIPBDIP 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIPBDIP 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member WEAWEL 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member WEAWEL 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member WEBWEU 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member WEBWEU 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef CLKBRDCLK
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef ENBRDEN
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef REGCEA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef REGCEBREGCE
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef RSTA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef RSTBRST
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_0_ "douta<0>")
+              (joined
+                (portRef (member douta 31))
+                (portRef (member DOADO 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+              )
+            )
+            (net (rename douta_1_ "douta<1>")
+              (joined
+                (portRef (member douta 30))
+                (portRef (member DOADO 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+              )
+            )
+            (net (rename douta_2_ "douta<2>")
+              (joined
+                (portRef (member douta 29))
+                (portRef (member DOA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_3_ "douta<3>")
+              (joined
+                (portRef (member douta 28))
+                (portRef (member DOA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_4_ "douta<4>")
+              (joined
+                (portRef (member douta 27))
+                (portRef (member DOA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_5_ "douta<5>")
+              (joined
+                (portRef (member douta 26))
+                (portRef (member DOA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_6_ "douta<6>")
+              (joined
+                (portRef (member douta 25))
+                (portRef (member DOA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_7_ "douta<7>")
+              (joined
+                (portRef (member douta 24))
+                (portRef (member DOA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_8_ "douta<8>")
+              (joined
+                (portRef (member douta 23))
+                (portRef (member DOA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_9_ "douta<9>")
+              (joined
+                (portRef (member douta 22))
+                (portRef (member DOA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_10_ "douta<10>")
+              (joined
+                (portRef (member douta 21))
+                (portRef (member DOA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_11_ "douta<11>")
+              (joined
+                (portRef (member douta 20))
+                (portRef (member DOA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_12_ "douta<12>")
+              (joined
+                (portRef (member douta 19))
+                (portRef (member DOA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_13_ "douta<13>")
+              (joined
+                (portRef (member douta 18))
+                (portRef (member DOA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_14_ "douta<14>")
+              (joined
+                (portRef (member douta 17))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux61))
+              )
+            )
+            (net (rename douta_15_ "douta<15>")
+              (joined
+                (portRef (member douta 16))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux71))
+              )
+            )
+            (net (rename douta_16_ "douta<16>")
+              (joined
+                (portRef (member douta 15))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux81))
+              )
+            )
+            (net (rename douta_17_ "douta<17>")
+              (joined
+                (portRef (member douta 14))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux91))
+              )
+            )
+            (net (rename douta_18_ "douta<18>")
+              (joined
+                (portRef (member douta 13))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux101))
+              )
+            )
+            (net (rename douta_19_ "douta<19>")
+              (joined
+                (portRef (member douta 12))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux111))
+              )
+            )
+            (net (rename douta_20_ "douta<20>")
+              (joined
+                (portRef (member douta 11))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux131))
+              )
+            )
+            (net (rename douta_21_ "douta<21>")
+              (joined
+                (portRef (member douta 10))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux141))
+              )
+            )
+            (net (rename douta_22_ "douta<22>")
+              (joined
+                (portRef (member douta 9))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux151))
+              )
+            )
+            (net (rename douta_23_ "douta<23>")
+              (joined
+                (portRef (member douta 8))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux161))
+              )
+            )
+            (net (rename douta_24_ "douta<24>")
+              (joined
+                (portRef (member douta 7))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux171))
+              )
+            )
+            (net (rename douta_25_ "douta<25>")
+              (joined
+                (portRef (member douta 6))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux181))
+              )
+            )
+            (net (rename douta_26_ "douta<26>")
+              (joined
+                (portRef (member douta 5))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux191))
+              )
+            )
+            (net (rename douta_27_ "douta<27>")
+              (joined
+                (portRef (member douta 4))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux201))
+              )
+            )
+            (net (rename douta_28_ "douta<28>")
+              (joined
+                (portRef (member douta 3))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux211))
+              )
+            )
+            (net (rename douta_29_ "douta<29>")
+              (joined
+                (portRef (member douta 2))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux221))
+              )
+            )
+            (net (rename douta_30_ "douta<30>")
+              (joined
+                (portRef (member douta 1))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux241))
+              )
+            )
+            (net (rename douta_31_ "douta<31>")
+              (joined
+                (portRef (member douta 0))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux251))
+              )
+            )
+            (net clka
+              (joined
+                (portRef clka)
+                (portRef C (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_sel_pipe_0_renamed_0))
+                (portRef CLKAWRCLK
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef CLKA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_0_ "addra<0>")
+              (joined
+                (portRef (member addra 11))
+                (portRef (member ADDRAWRADDR 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_1_ "addra<1>")
+              (joined
+                (portRef (member addra 10))
+                (portRef (member ADDRAWRADDR 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_2_ "addra<2>")
+              (joined
+                (portRef (member addra 9))
+                (portRef (member ADDRAWRADDR 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_3_ "addra<3>")
+              (joined
+                (portRef (member addra 8))
+                (portRef (member ADDRAWRADDR 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_4_ "addra<4>")
+              (joined
+                (portRef (member addra 7))
+                (portRef (member ADDRAWRADDR 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_5_ "addra<5>")
+              (joined
+                (portRef (member addra 6))
+                (portRef (member ADDRAWRADDR 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_6_ "addra<6>")
+              (joined
+                (portRef (member addra 5))
+                (portRef (member ADDRAWRADDR 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_7_ "addra<7>")
+              (joined
+                (portRef (member addra 4))
+                (portRef (member ADDRAWRADDR 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_8_ "addra<8>")
+              (joined
+                (portRef (member addra 3))
+                (portRef (member ADDRAWRADDR 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_9_ "addra<9>")
+              (joined
+                (portRef (member addra 2))
+                (portRef (member ADDRAWRADDR 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_10_ "addra<10>")
+              (joined
+                (portRef (member addra 1))
+                (portRef (member ADDRAWRADDR 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_11_ "addra<11>")
+              (joined
+                (portRef (member addra 0))
+                (portRef D (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_sel_pipe_0_renamed_0))
+                (portRef (member ADDRAWRADDR 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_bindec_a_bindec_inst_a_ADDR_0__GND_16_o_equal_1_o1_INV_0))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_bindec_a_bindec_inst_a_ADDR_0__GND_16_o_equal_1_o "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/ADDR[0]_GND_16_o_equal_1_o")
+              (joined
+                (portRef ENA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef O
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_bindec_a_bindec_inst_a_ADDR_0__GND_16_o_equal_1_o1_INV_0))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_sel_pipe_0 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/sel_pipe_0")
+              (joined
+                (portRef Q (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_sel_pipe_0_renamed_0))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux61))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux71))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux81))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux91))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux101))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux111))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux131))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux141))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux151))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux161))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux171))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux181))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux191))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux201))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux211))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux221))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux241))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux251))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_ram_douta_0_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_douta<0>")
+              (joined
+                (portRef (member DOA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux161))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_ram_douta_1_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_douta<1>")
+              (joined
+                (portRef (member DOA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux171))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_ram_douta_2_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_douta<2>")
+              (joined
+                (portRef (member DOA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux181))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_ram_douta_3_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_douta<3>")
+              (joined
+                (portRef (member DOA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux191))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_ram_douta_4_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_douta<4>")
+              (joined
+                (portRef (member DOA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux201))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_ram_douta_5_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_douta<5>")
+              (joined
+                (portRef (member DOA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux211))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_ram_douta_6_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_douta<6>")
+              (joined
+                (portRef (member DOA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux221))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_ram_douta_7_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_douta<7>")
+              (joined
+                (portRef (member DOA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux241))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_ram_douta_8_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_douta<8>")
+              (joined
+                (portRef (member DOPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux251))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_ram_douta_0_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_douta<0>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux161))
+                (portRef (member DOA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_ram_douta_1_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_douta<1>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux171))
+                (portRef (member DOA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_ram_douta_2_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_douta<2>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux181))
+                (portRef (member DOA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_ram_douta_3_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_douta<3>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux191))
+                (portRef (member DOA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_ram_douta_4_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_douta<4>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux201))
+                (portRef (member DOA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_ram_douta_5_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_douta<5>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux211))
+                (portRef (member DOA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_ram_douta_6_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_douta<6>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux221))
+                (portRef (member DOA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_ram_douta_7_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_douta<7>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux241))
+                (portRef (member DOA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_ram_douta_8_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_douta<8>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux251))
+                (portRef (member DOPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_ram_douta_0_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<0>")
+              (joined
+                (portRef (member DOA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux61))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_ram_douta_1_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<1>")
+              (joined
+                (portRef (member DOA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux71))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_ram_douta_2_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<2>")
+              (joined
+                (portRef (member DOA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux81))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_ram_douta_3_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<3>")
+              (joined
+                (portRef (member DOA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux91))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_ram_douta_4_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<4>")
+              (joined
+                (portRef (member DOA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux101))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_ram_douta_5_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<5>")
+              (joined
+                (portRef (member DOA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux111))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_ram_douta_6_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<6>")
+              (joined
+                (portRef (member DOA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux131))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_ram_douta_7_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<7>")
+              (joined
+                (portRef (member DOA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux141))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_ram_douta_8_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<8>")
+              (joined
+                (portRef (member DOPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux151))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_ram_douta_0_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<0>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux61))
+                (portRef (member DOA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_ram_douta_1_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<1>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux71))
+                (portRef (member DOA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_ram_douta_2_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<2>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux81))
+                (portRef (member DOA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_ram_douta_3_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<3>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux91))
+                (portRef (member DOA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_ram_douta_4_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<4>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux101))
+                (portRef (member DOA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_ram_douta_5_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<5>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux111))
+                (portRef (member DOA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_ram_douta_6_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<6>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux131))
+                (portRef (member DOA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_ram_douta_7_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<7>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux141))
+                (portRef (member DOA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_ram_douta_8_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<8>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux151))
+                (portRef (member DOPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+          )
+      )
+    )
+  )
+
+  (design EU4Kx32
+    (cellRef EU4Kx32
+      (libraryRef EU4Kx32_lib)
+    )
+    (property PART (string "6slx9tqg144-2") (owner "Xilinx"))
+  )
+)
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/cache/MCL86jr_ngc_zx.edif b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/cache/MCL86jr_ngc_zx.edif
new file mode 100644
index 0000000..c685b16
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/cache/MCL86jr_ngc_zx.edif
@@ -0,0 +1,29336 @@
+(edif MCL86jr
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2020 9 26 22 58 3)
+      (program "Xilinx ngc2edif" (version "P.20131013"))
+      (author "Xilinx. Inc ")
+      (comment "This EDIF netlist is to be used within supported synthesis tools")
+      (comment "for determining resource/timing estimates of the design component")
+      (comment "represented by this netlist.")
+      (comment "Command line: -mdp2sp -w -secure MCL86jr.ngc MCL86jr.edif ")))
+  (external UNISIMS
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell VCC
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port P
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell GND
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port G
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FD
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell XORCY
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CI
+              (direction INPUT)
+            )
+            (port LI
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell MUXCY
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CI
+              (direction INPUT)
+            )
+            (port DI
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT2
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FDRE
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port CE
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port R
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT3
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FDR
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port R
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FDE
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port CE
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FDSE
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port CE
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FDS
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT5
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port I3
+              (direction INPUT)
+            )
+            (port I4
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT6
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port I3
+              (direction INPUT)
+            )
+            (port I4
+              (direction INPUT)
+            )
+            (port I5
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell MUXF7
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell MUXF8
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT4
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port I3
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell IBUF
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell OBUF
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell IOBUF
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port T
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+            (port IO
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT1
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell BUFGP
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell INV
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell SRLC16E
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port A0
+              (direction INPUT)
+            )
+            (port A1
+              (direction INPUT)
+            )
+            (port A2
+              (direction INPUT)
+            )
+            (port A3
+              (direction INPUT)
+            )
+            (port CE
+              (direction INPUT)
+            )
+            (port CLK
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+            (port Q15
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+  )
+
+  (library MCL86jr_lib
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell EU4Kx32
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port clka
+              (direction INPUT)
+            )
+            (port (array (rename addra "addra<11:0>") 12)
+              (direction INPUT))
+            (port (array (rename douta "douta<31:0>") 32)
+              (direction OUTPUT))
+          )
+      )
+    )
+    (cell MCL86jr
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CORE_CLK
+              (direction INPUT)
+            )
+            (port CLK
+              (direction INPUT)
+            )
+            (port RESET
+              (direction INPUT)
+            )
+            (port READY
+              (direction INPUT)
+            )
+            (port INTR
+              (direction INPUT)
+            )
+            (port NMI
+              (direction INPUT)
+            )
+            (port A19
+              (direction OUTPUT)
+            )
+            (port A18
+              (direction OUTPUT)
+            )
+            (port A17
+              (direction OUTPUT)
+            )
+            (port A16
+              (direction OUTPUT)
+            )
+            (port A15
+              (direction OUTPUT)
+            )
+            (port A14
+              (direction OUTPUT)
+            )
+            (port A13
+              (direction OUTPUT)
+            )
+            (port A12
+              (direction OUTPUT)
+            )
+            (port A11
+              (direction OUTPUT)
+            )
+            (port A10
+              (direction OUTPUT)
+            )
+            (port A9
+              (direction OUTPUT)
+            )
+            (port A8
+              (direction OUTPUT)
+            )
+            (port AD7
+              (direction INOUT)
+            )
+            (port AD6
+              (direction INOUT)
+            )
+            (port AD5
+              (direction INOUT)
+            )
+            (port AD4
+              (direction INOUT)
+            )
+            (port AD3
+              (direction INOUT)
+            )
+            (port AD2
+              (direction INOUT)
+            )
+            (port AD1
+              (direction INOUT)
+            )
+            (port AD0
+              (direction INOUT)
+            )
+            (port ALE
+              (direction OUTPUT)
+            )
+            (port INTA_n
+              (direction OUTPUT)
+            )
+            (port RD_n
+              (direction OUTPUT)
+            )
+            (port WR_n
+              (direction OUTPUT)
+            )
+            (port IOM
+              (direction OUTPUT)
+            )
+            (port DTR
+              (direction OUTPUT)
+            )
+            (port DEN
+              (direction OUTPUT)
+            )
+            (port SSO_n
+              (direction OUTPUT)
+            )
+            (port SRAM_CE_n
+              (direction OUTPUT)
+            )
+            (port SRAM_OE_n
+              (direction OUTPUT)
+            )
+            (port SRAM_WE_n
+              (direction OUTPUT)
+            )
+            (port BUF1_OE_n
+              (direction OUTPUT)
+            )
+            (port BUF2_OE_n
+              (direction OUTPUT)
+            )
+            (port BUF2_DIR
+              (direction OUTPUT)
+            )
+            (port (array (rename SRAM_A "SRAM_A<18:0>") 19)
+              (direction OUTPUT))
+            (port (array (rename SRAM_D "SRAM_D<7:0>") 8)
+              (direction INOUT))
+            (port (array (rename LED "LED<7:0>") 8)
+              (direction OUTPUT))
+            (designator "xc6slx9-3-tqg144")
+            (property TYPE (string "MCL86jr") (owner "Xilinx"))
+            (property BUS_INFO (string "19:OUTPUT:SRAM_A<18:0>") (owner "Xilinx"))
+            (property BUS_INFO (string "8:INOUT:SRAM_D<7:0>") (owner "Xilinx"))
+            (property BUS_INFO (string "8:OUTPUT:LED<7:0>") (owner "Xilinx"))
+            (property SHREG_MIN_SIZE (string "2") (owner "Xilinx"))
+            (property X_CORE_INFO (string "blk_mem_gen_v7_3, Xilinx CORE Generator 14.7") (owner "Xilinx"))
+            (property SHREG_EXTRACT_NGC (string "YES") (owner "Xilinx"))
+            (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
+            (property NLW_MACRO_TAG (integer 0) (owner "Xilinx"))
+            (property NLW_MACRO_ALIAS (string "MCL86jr_MCL86jr") (owner "Xilinx"))
+          )
+          (contents
+            (instance XST_VCC
+              (viewRef view_1 (cellRef VCC (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance XST_GND
+              (viewRef view_1 (cellRef GND (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_0
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_1
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_2
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_3
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_4
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_5
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_6
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_7
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_8
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_9
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_10
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_11
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_12
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_13
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_14
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_15
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_16
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_17
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_18
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_19
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename t_reset_d3_renamed_1 "t_reset_d3")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_19__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_xor<19>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_18__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_xor<18>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_18__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<18>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_17__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_xor<17>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_17__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<17>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_16__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_xor<16>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_16__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<16>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_15__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_15__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<15>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_15__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<15>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_14__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_14__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_14__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<14>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_13__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_13__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_13__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<13>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_12__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_12__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_12__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<12>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_11__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_11__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_11__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<11>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_10__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_10__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_10__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<10>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_9__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_9__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_9__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<9>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_8__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_8__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_8__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<8>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_7__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_7__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_7__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<7>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_6__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_6__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_6__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<6>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_5__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_5__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_5__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<5>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_4__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_4__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_4__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<4>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_15__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_14__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_14__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_13__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_13__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_12__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_12__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_11__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_11__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_10__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_10__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_9__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_9__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_8__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_8__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_7__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_7__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_6__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_6__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_5__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_5__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_4__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_4__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_3__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_3__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_2__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_2__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_1__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_1__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_0__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_0__ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_19__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_xor<19>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_18__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_xor<18>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_18__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<18>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_17__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_xor<17>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_17__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<17>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_16__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_xor<16>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_16__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<16>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_15__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_15__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<15>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_15__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<15>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_14__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_14__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_14__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<14>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_13__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_13__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_13__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<13>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_12__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_12__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_12__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<12>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_11__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_11__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_11__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<11>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_10__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_10__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_10__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<10>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_9__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_9__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_9__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<9>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_8__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_8__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_8__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<8>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_7__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_7__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_7__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<7>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_6__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_6__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_6__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<6>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_5__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_5__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_5__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<5>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_4__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_4__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_4__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<4>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_19__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_xor<19>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_18__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_xor<18>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_18__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<18>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_17__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_xor<17>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_17__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<17>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_16__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_xor<16>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_16__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<16>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_15__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_15__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<15>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_15__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<15>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_14__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_14__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_14__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<14>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_13__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_13__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_13__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<13>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_12__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_12__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_12__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<12>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_11__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_11__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_11__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<11>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_10__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_10__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_10__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<10>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_9__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_9__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_9__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<9>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_8__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_8__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_8__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<8>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_7__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_7__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_7__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<7>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_6__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_6__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_6__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<6>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_5__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_5__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_5__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<5>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_4__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_4__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_4__ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<4>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_19__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_xor<19>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_18__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_xor<18>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_18__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<18>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_17__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_xor<17>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_17__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<17>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_16__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_xor<16>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_16__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<16>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_15__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_15__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<15>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_15__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<15>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_14__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_14__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_14__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<14>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_13__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_13__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_13__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<13>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_12__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_12__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_12__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<12>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_11__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_11__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_11__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<11>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_10__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_10__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_10__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<10>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_9__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_9__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_9__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<9>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_8__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_8__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_8__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<8>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_7__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_7__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_7__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<7>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_6__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_6__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_6__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<6>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_5__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_5__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_5__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<5>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_4__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_4__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_4__ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<4>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_12 "BIU_CORE/clock_cycle_counter_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_11 "BIU_CORE/clock_cycle_counter_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_10 "BIU_CORE/clock_cycle_counter_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_9 "BIU_CORE/clock_cycle_counter_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_8 "BIU_CORE/clock_cycle_counter_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_7 "BIU_CORE/clock_cycle_counter_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_6 "BIU_CORE/clock_cycle_counter_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_5 "BIU_CORE/clock_cycle_counter_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_4 "BIU_CORE/clock_cycle_counter_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_3 "BIU_CORE/clock_cycle_counter_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_2 "BIU_CORE/clock_cycle_counter_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_1 "BIU_CORE/clock_cycle_counter_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_0 "BIU_CORE/clock_cycle_counter_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_15 "BIU_CORE/pfq_addr_in_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_14 "BIU_CORE/pfq_addr_in_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_13 "BIU_CORE/pfq_addr_in_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_12 "BIU_CORE/pfq_addr_in_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_11 "BIU_CORE/pfq_addr_in_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_10 "BIU_CORE/pfq_addr_in_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_9 "BIU_CORE/pfq_addr_in_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_8 "BIU_CORE/pfq_addr_in_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_7 "BIU_CORE/pfq_addr_in_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_6 "BIU_CORE/pfq_addr_in_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_5 "BIU_CORE/pfq_addr_in_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_4 "BIU_CORE/pfq_addr_in_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_3 "BIU_CORE/pfq_addr_in_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_2 "BIU_CORE/pfq_addr_in_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_1 "BIU_CORE/pfq_addr_in_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_0 "BIU_CORE/pfq_addr_in_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_15 "BIU_CORE/pfq_addr_out_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_14 "BIU_CORE/pfq_addr_out_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_13 "BIU_CORE/pfq_addr_out_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_12 "BIU_CORE/pfq_addr_out_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_11 "BIU_CORE/pfq_addr_out_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_10 "BIU_CORE/pfq_addr_out_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_9 "BIU_CORE/pfq_addr_out_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_8 "BIU_CORE/pfq_addr_out_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_7 "BIU_CORE/pfq_addr_out_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_6 "BIU_CORE/pfq_addr_out_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_5 "BIU_CORE/pfq_addr_out_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_4 "BIU_CORE/pfq_addr_out_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_3 "BIU_CORE/pfq_addr_out_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_2 "BIU_CORE/pfq_addr_out_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_1 "BIU_CORE/pfq_addr_out_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_0 "BIU_CORE/pfq_addr_out_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_15__ "BIU_CORE/Mcount_pfq_addr_out_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_15__ "BIU_CORE/Mcount_pfq_addr_out_lut<15>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_14__ "BIU_CORE/Mcount_pfq_addr_out_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_14__ "BIU_CORE/Mcount_pfq_addr_out_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_14__ "BIU_CORE/Mcount_pfq_addr_out_lut<14>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_13__ "BIU_CORE/Mcount_pfq_addr_out_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_13__ "BIU_CORE/Mcount_pfq_addr_out_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_13__ "BIU_CORE/Mcount_pfq_addr_out_lut<13>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_12__ "BIU_CORE/Mcount_pfq_addr_out_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_12__ "BIU_CORE/Mcount_pfq_addr_out_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_12__ "BIU_CORE/Mcount_pfq_addr_out_lut<12>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_11__ "BIU_CORE/Mcount_pfq_addr_out_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_11__ "BIU_CORE/Mcount_pfq_addr_out_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_11__ "BIU_CORE/Mcount_pfq_addr_out_lut<11>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_10__ "BIU_CORE/Mcount_pfq_addr_out_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_10__ "BIU_CORE/Mcount_pfq_addr_out_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_10__ "BIU_CORE/Mcount_pfq_addr_out_lut<10>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_9__ "BIU_CORE/Mcount_pfq_addr_out_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_9__ "BIU_CORE/Mcount_pfq_addr_out_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_9__ "BIU_CORE/Mcount_pfq_addr_out_lut<9>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_8__ "BIU_CORE/Mcount_pfq_addr_out_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_8__ "BIU_CORE/Mcount_pfq_addr_out_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_8__ "BIU_CORE/Mcount_pfq_addr_out_lut<8>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_7__ "BIU_CORE/Mcount_pfq_addr_out_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_7__ "BIU_CORE/Mcount_pfq_addr_out_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_7__ "BIU_CORE/Mcount_pfq_addr_out_lut<7>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_6__ "BIU_CORE/Mcount_pfq_addr_out_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_6__ "BIU_CORE/Mcount_pfq_addr_out_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_6__ "BIU_CORE/Mcount_pfq_addr_out_lut<6>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_5__ "BIU_CORE/Mcount_pfq_addr_out_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_5__ "BIU_CORE/Mcount_pfq_addr_out_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_5__ "BIU_CORE/Mcount_pfq_addr_out_lut<5>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_4__ "BIU_CORE/Mcount_pfq_addr_out_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_4__ "BIU_CORE/Mcount_pfq_addr_out_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_4__ "BIU_CORE/Mcount_pfq_addr_out_lut<4>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_3__ "BIU_CORE/Mcount_pfq_addr_out_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_3__ "BIU_CORE/Mcount_pfq_addr_out_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_3__ "BIU_CORE/Mcount_pfq_addr_out_lut<3>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_2__ "BIU_CORE/Mcount_pfq_addr_out_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_2__ "BIU_CORE/Mcount_pfq_addr_out_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_2__ "BIU_CORE/Mcount_pfq_addr_out_lut<2>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_1__ "BIU_CORE/Mcount_pfq_addr_out_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_1__ "BIU_CORE/Mcount_pfq_addr_out_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_1__ "BIU_CORE/Mcount_pfq_addr_out_lut<1>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_0__ "BIU_CORE/Mcount_pfq_addr_out_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_0__ "BIU_CORE/Mcount_pfq_addr_out_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_0__ "BIU_CORE/Mcount_pfq_addr_out_lut<0>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_12__ "BIU_CORE/Mcount_clock_cycle_counter_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_11__ "BIU_CORE/Mcount_clock_cycle_counter_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_11__ "BIU_CORE/Mcount_clock_cycle_counter_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_10__ "BIU_CORE/Mcount_clock_cycle_counter_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_10__ "BIU_CORE/Mcount_clock_cycle_counter_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_9__ "BIU_CORE/Mcount_clock_cycle_counter_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_9__ "BIU_CORE/Mcount_clock_cycle_counter_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_8__ "BIU_CORE/Mcount_clock_cycle_counter_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_8__ "BIU_CORE/Mcount_clock_cycle_counter_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_7__ "BIU_CORE/Mcount_clock_cycle_counter_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_7__ "BIU_CORE/Mcount_clock_cycle_counter_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_6__ "BIU_CORE/Mcount_clock_cycle_counter_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_6__ "BIU_CORE/Mcount_clock_cycle_counter_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_5__ "BIU_CORE/Mcount_clock_cycle_counter_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_5__ "BIU_CORE/Mcount_clock_cycle_counter_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_4__ "BIU_CORE/Mcount_clock_cycle_counter_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_4__ "BIU_CORE/Mcount_clock_cycle_counter_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_3__ "BIU_CORE/Mcount_clock_cycle_counter_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_3__ "BIU_CORE/Mcount_clock_cycle_counter_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_2__ "BIU_CORE/Mcount_clock_cycle_counter_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_2__ "BIU_CORE/Mcount_clock_cycle_counter_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_1__ "BIU_CORE/Mcount_clock_cycle_counter_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_1__ "BIU_CORE/Mcount_clock_cycle_counter_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_0__ "BIU_CORE/Mcount_clock_cycle_counter_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_0__ "BIU_CORE/Mcount_clock_cycle_counter_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_15__ "BIU_CORE/Mcount_pfq_addr_in_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_15__ "BIU_CORE/Mcount_pfq_addr_in_lut<15>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_14__ "BIU_CORE/Mcount_pfq_addr_in_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_14__ "BIU_CORE/Mcount_pfq_addr_in_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_14__ "BIU_CORE/Mcount_pfq_addr_in_lut<14>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_13__ "BIU_CORE/Mcount_pfq_addr_in_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_13__ "BIU_CORE/Mcount_pfq_addr_in_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_13__ "BIU_CORE/Mcount_pfq_addr_in_lut<13>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_12__ "BIU_CORE/Mcount_pfq_addr_in_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_12__ "BIU_CORE/Mcount_pfq_addr_in_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_12__ "BIU_CORE/Mcount_pfq_addr_in_lut<12>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_11__ "BIU_CORE/Mcount_pfq_addr_in_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_11__ "BIU_CORE/Mcount_pfq_addr_in_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_11__ "BIU_CORE/Mcount_pfq_addr_in_lut<11>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_10__ "BIU_CORE/Mcount_pfq_addr_in_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_10__ "BIU_CORE/Mcount_pfq_addr_in_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_10__ "BIU_CORE/Mcount_pfq_addr_in_lut<10>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_9__ "BIU_CORE/Mcount_pfq_addr_in_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_9__ "BIU_CORE/Mcount_pfq_addr_in_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_9__ "BIU_CORE/Mcount_pfq_addr_in_lut<9>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_8__ "BIU_CORE/Mcount_pfq_addr_in_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_8__ "BIU_CORE/Mcount_pfq_addr_in_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_8__ "BIU_CORE/Mcount_pfq_addr_in_lut<8>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_7__ "BIU_CORE/Mcount_pfq_addr_in_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_7__ "BIU_CORE/Mcount_pfq_addr_in_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_7__ "BIU_CORE/Mcount_pfq_addr_in_lut<7>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_6__ "BIU_CORE/Mcount_pfq_addr_in_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_6__ "BIU_CORE/Mcount_pfq_addr_in_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_6__ "BIU_CORE/Mcount_pfq_addr_in_lut<6>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_5__ "BIU_CORE/Mcount_pfq_addr_in_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_5__ "BIU_CORE/Mcount_pfq_addr_in_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_5__ "BIU_CORE/Mcount_pfq_addr_in_lut<5>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_4__ "BIU_CORE/Mcount_pfq_addr_in_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_4__ "BIU_CORE/Mcount_pfq_addr_in_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_4__ "BIU_CORE/Mcount_pfq_addr_in_lut<4>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_3__ "BIU_CORE/Mcount_pfq_addr_in_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_3__ "BIU_CORE/Mcount_pfq_addr_in_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_3__ "BIU_CORE/Mcount_pfq_addr_in_lut<3>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_2__ "BIU_CORE/Mcount_pfq_addr_in_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_2__ "BIU_CORE/Mcount_pfq_addr_in_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_2__ "BIU_CORE/Mcount_pfq_addr_in_lut<2>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_1__ "BIU_CORE/Mcount_pfq_addr_in_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_1__ "BIU_CORE/Mcount_pfq_addr_in_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_1__ "BIU_CORE/Mcount_pfq_addr_in_lut<1>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_0__ "BIU_CORE/Mcount_pfq_addr_in_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_0__ "BIU_CORE/Mcount_pfq_addr_in_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_0__ "BIU_CORE/Mcount_pfq_addr_in_lut<0>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_DTR_renamed_2 "BIU_CORE/DTR")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_dtr_int_renamed_3 "BIU_CORE/dtr_int")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_top_byte_int_d1_7 "BIU_CORE/pfq_top_byte_int_d1_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_top_byte_int_d1_6 "BIU_CORE/pfq_top_byte_int_d1_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_top_byte_int_d1_5 "BIU_CORE/pfq_top_byte_int_d1_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_top_byte_int_d1_4 "BIU_CORE/pfq_top_byte_int_d1_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_top_byte_int_d1_3 "BIU_CORE/pfq_top_byte_int_d1_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_top_byte_int_d1_2 "BIU_CORE/pfq_top_byte_int_d1_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_top_byte_int_d1_1 "BIU_CORE/pfq_top_byte_int_d1_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_top_byte_int_d1_0 "BIU_CORE/pfq_top_byte_int_d1_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_nmi_d5_renamed_4 "BIU_CORE/nmi_d5")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_s_bits_2 "BIU_CORE/s_bits_2")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_s_bits_1 "BIU_CORE/s_bits_1")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_s_bits_0 "BIU_CORE/s_bits_0")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_15 "BIU_CORE/biu_return_data_int_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_14 "BIU_CORE/biu_return_data_int_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_13 "BIU_CORE/biu_return_data_int_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_12 "BIU_CORE/biu_return_data_int_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_11 "BIU_CORE/biu_return_data_int_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_10 "BIU_CORE/biu_return_data_int_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_9 "BIU_CORE/biu_return_data_int_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_8 "BIU_CORE/biu_return_data_int_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_7 "BIU_CORE/biu_return_data_int_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_6 "BIU_CORE/biu_return_data_int_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_5 "BIU_CORE/biu_return_data_int_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_4 "BIU_CORE/biu_return_data_int_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_3 "BIU_CORE/biu_return_data_int_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_2 "BIU_CORE/biu_return_data_int_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_1 "BIU_CORE/biu_return_data_int_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_0 "BIU_CORE/biu_return_data_int_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_nmi_d4_renamed_5 "BIU_CORE/nmi_d4")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clk_d4_renamed_6 "BIU_CORE/clk_d4")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry3_7 "BIU_CORE/pfq_entry3_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry3_6 "BIU_CORE/pfq_entry3_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry3_5 "BIU_CORE/pfq_entry3_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry3_4 "BIU_CORE/pfq_entry3_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry3_3 "BIU_CORE/pfq_entry3_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry3_2 "BIU_CORE/pfq_entry3_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry3_1 "BIU_CORE/pfq_entry3_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry3_0 "BIU_CORE/pfq_entry3_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry2_7 "BIU_CORE/pfq_entry2_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry2_6 "BIU_CORE/pfq_entry2_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry2_5 "BIU_CORE/pfq_entry2_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry2_4 "BIU_CORE/pfq_entry2_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry2_3 "BIU_CORE/pfq_entry2_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry2_2 "BIU_CORE/pfq_entry2_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry2_1 "BIU_CORE/pfq_entry2_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry2_0 "BIU_CORE/pfq_entry2_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry1_7 "BIU_CORE/pfq_entry1_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry1_6 "BIU_CORE/pfq_entry1_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry1_5 "BIU_CORE/pfq_entry1_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry1_4 "BIU_CORE/pfq_entry1_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry1_3 "BIU_CORE/pfq_entry1_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry1_2 "BIU_CORE/pfq_entry1_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry1_1 "BIU_CORE/pfq_entry1_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry1_0 "BIU_CORE/pfq_entry1_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry0_7 "BIU_CORE/pfq_entry0_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry0_6 "BIU_CORE/pfq_entry0_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry0_5 "BIU_CORE/pfq_entry0_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry0_4 "BIU_CORE/pfq_entry0_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry0_3 "BIU_CORE/pfq_entry0_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry0_2 "BIU_CORE/pfq_entry0_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry0_1 "BIU_CORE/pfq_entry0_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry0_0 "BIU_CORE/pfq_entry0_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_15 "BIU_CORE/pfq_addr_out_d1_15")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_14 "BIU_CORE/pfq_addr_out_d1_14")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_13 "BIU_CORE/pfq_addr_out_d1_13")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_12 "BIU_CORE/pfq_addr_out_d1_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_11 "BIU_CORE/pfq_addr_out_d1_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_10 "BIU_CORE/pfq_addr_out_d1_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_9 "BIU_CORE/pfq_addr_out_d1_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_8 "BIU_CORE/pfq_addr_out_d1_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_7 "BIU_CORE/pfq_addr_out_d1_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_6 "BIU_CORE/pfq_addr_out_d1_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_5 "BIU_CORE/pfq_addr_out_d1_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_4 "BIU_CORE/pfq_addr_out_d1_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_3 "BIU_CORE/pfq_addr_out_d1_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_2 "BIU_CORE/pfq_addr_out_d1_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_1 "BIU_CORE/pfq_addr_out_d1_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_0 "BIU_CORE/pfq_addr_out_d1_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_intr_d3_renamed_7 "BIU_CORE/intr_d3")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_nmi_d3_renamed_8 "BIU_CORE/nmi_d3")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clk_d3_renamed_9 "BIU_CORE/clk_d3")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_latched_data_in_7 "BIU_CORE/latched_data_in_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_latched_data_in_6 "BIU_CORE/latched_data_in_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_latched_data_in_5 "BIU_CORE/latched_data_in_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_latched_data_in_4 "BIU_CORE/latched_data_in_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_latched_data_in_3 "BIU_CORE/latched_data_in_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_latched_data_in_2 "BIU_CORE/latched_data_in_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_latched_data_in_1 "BIU_CORE/latched_data_in_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_latched_data_in_0 "BIU_CORE/latched_data_in_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ALE_renamed_10 "BIU_CORE/ALE")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_DEN_renamed_11 "BIU_CORE/DEN")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_WR_n_renamed_12 "BIU_CORE/WR_n")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_INTA_n_renamed_13 "BIU_CORE/INTA_n")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_RD_n_renamed_14 "BIU_CORE/RD_n")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_IOM_renamed_15 "BIU_CORE/IOM")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_intr_d2_renamed_16 "BIU_CORE/intr_d2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_nmi_d2_renamed_17 "BIU_CORE/nmi_d2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clk_d2_renamed_18 "BIU_CORE/clk_d2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_19_renamed_19 "BIU_CORE/addr_out_temp_19")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_18_renamed_20 "BIU_CORE/addr_out_temp_18")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_17_renamed_21 "BIU_CORE/addr_out_temp_17")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_16_renamed_22 "BIU_CORE/addr_out_temp_16")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_15_renamed_23 "BIU_CORE/addr_out_temp_15")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_14_renamed_24 "BIU_CORE/addr_out_temp_14")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_13_renamed_25 "BIU_CORE/addr_out_temp_13")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_12_renamed_26 "BIU_CORE/addr_out_temp_12")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_11_renamed_27 "BIU_CORE/addr_out_temp_11")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_10_renamed_28 "BIU_CORE/addr_out_temp_10")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_9_renamed_29 "BIU_CORE/addr_out_temp_9")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_8_renamed_30 "BIU_CORE/addr_out_temp_8")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_7_renamed_31 "BIU_CORE/addr_out_temp_7")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_6_renamed_32 "BIU_CORE/addr_out_temp_6")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_5_renamed_33 "BIU_CORE/addr_out_temp_5")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_4_renamed_34 "BIU_CORE/addr_out_temp_4")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_3_renamed_35 "BIU_CORE/addr_out_temp_3")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_2_renamed_36 "BIU_CORE/addr_out_temp_2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_1_renamed_37 "BIU_CORE/addr_out_temp_1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_0_renamed_38 "BIU_CORE/addr_out_temp_0")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_iom_int_renamed_39 "BIU_CORE/iom_int")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7 "BIU_CORE/biu_state_7")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_6 "BIU_CORE/biu_state_6")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_5 "BIU_CORE/biu_state_5")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_4 "BIU_CORE/biu_state_4")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_3 "BIU_CORE/biu_state_3")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_2 "BIU_CORE/biu_state_2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_1 "BIU_CORE/biu_state_1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_0 "BIU_CORE/biu_state_0")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_den_int_renamed_40 "BIU_CORE/den_int")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_wr_n_int_renamed_41 "BIU_CORE/wr_n_int")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_rd_n_int_renamed_42 "BIU_CORE/rd_n_int")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_inta_n_int_renamed_43 "BIU_CORE/inta_n_int")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clk_d1_renamed_44 "BIU_CORE/clk_d1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ale_int_renamed_45 "BIU_CORE/ale_int")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OE_renamed_46 "BIU_CORE/AD_OE")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_intr_d1_renamed_47 "BIU_CORE/intr_d1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_byte_num_renamed_48 "BIU_CORE/byte_num")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_biu_req_d1_renamed_49 "BIU_CORE/eu_biu_req_d1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ready_d1_renamed_50 "BIU_CORE/ready_d1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_19 "BIU_CORE/AD_OUT_19")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_18 "BIU_CORE/AD_OUT_18")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_17 "BIU_CORE/AD_OUT_17")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_16 "BIU_CORE/AD_OUT_16")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_15 "BIU_CORE/AD_OUT_15")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_14 "BIU_CORE/AD_OUT_14")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_13 "BIU_CORE/AD_OUT_13")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_12 "BIU_CORE/AD_OUT_12")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_11 "BIU_CORE/AD_OUT_11")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_10 "BIU_CORE/AD_OUT_10")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_9 "BIU_CORE/AD_OUT_9")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_8 "BIU_CORE/AD_OUT_8")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_7 "BIU_CORE/AD_OUT_7")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_6 "BIU_CORE/AD_OUT_6")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_5 "BIU_CORE/AD_OUT_5")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_4 "BIU_CORE/AD_OUT_4")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_3 "BIU_CORE/AD_OUT_3")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_2 "BIU_CORE/AD_OUT_2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_1 "BIU_CORE/AD_OUT_1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_0 "BIU_CORE/AD_OUT_0")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_done_int_renamed_51 "BIU_CORE/biu_done_int")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_write_renamed_52 "BIU_CORE/pfq_write")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_nmi_d1_renamed_53 "BIU_CORE/nmi_d1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_15 "BIU_CORE/eu_register_r3_d_15")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_14 "BIU_CORE/eu_register_r3_d_14")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_13 "BIU_CORE/eu_register_r3_d_13")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_12 "BIU_CORE/eu_register_r3_d_12")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_11 "BIU_CORE/eu_register_r3_d_11")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_10 "BIU_CORE/eu_register_r3_d_10")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_9 "BIU_CORE/eu_register_r3_d_9")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_8 "BIU_CORE/eu_register_r3_d_8")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_7 "BIU_CORE/eu_register_r3_d_7")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_6 "BIU_CORE/eu_register_r3_d_6")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_5 "BIU_CORE/eu_register_r3_d_5")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_4 "BIU_CORE/eu_register_r3_d_4")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_3 "BIU_CORE/eu_register_r3_d_3")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_2 "BIU_CORE/eu_register_r3_d_2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_1 "BIU_CORE/eu_register_r3_d_1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_0 "BIU_CORE/eu_register_r3_d_0")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_15 "BIU_CORE/biu_register_reg_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_14 "BIU_CORE/biu_register_reg_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_13 "BIU_CORE/biu_register_reg_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_12 "BIU_CORE/biu_register_reg_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_11 "BIU_CORE/biu_register_reg_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_10 "BIU_CORE/biu_register_reg_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_9 "BIU_CORE/biu_register_reg_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_8 "BIU_CORE/biu_register_reg_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_7 "BIU_CORE/biu_register_reg_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_6 "BIU_CORE/biu_register_reg_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_5 "BIU_CORE/biu_register_reg_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_4 "BIU_CORE/biu_register_reg_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_3 "BIU_CORE/biu_register_reg_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_2 "BIU_CORE/biu_register_reg_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_1 "BIU_CORE/biu_register_reg_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_0 "BIU_CORE/biu_register_reg_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_15 "BIU_CORE/biu_register_rm_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_14 "BIU_CORE/biu_register_rm_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_13 "BIU_CORE/biu_register_rm_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_12 "BIU_CORE/biu_register_rm_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_11 "BIU_CORE/biu_register_rm_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_10 "BIU_CORE/biu_register_rm_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_9 "BIU_CORE/biu_register_rm_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_8 "BIU_CORE/biu_register_rm_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_7 "BIU_CORE/biu_register_rm_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_6 "BIU_CORE/biu_register_rm_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_5 "BIU_CORE/biu_register_rm_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_4 "BIU_CORE/biu_register_rm_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_3 "BIU_CORE/biu_register_rm_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_2 "BIU_CORE/biu_register_rm_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_1 "BIU_CORE/biu_register_rm_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_0 "BIU_CORE/biu_register_rm_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_15 "BIU_CORE/biu_register_cs_15")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_14 "BIU_CORE/biu_register_cs_14")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_13 "BIU_CORE/biu_register_cs_13")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_12 "BIU_CORE/biu_register_cs_12")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_11 "BIU_CORE/biu_register_cs_11")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_10 "BIU_CORE/biu_register_cs_10")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_9 "BIU_CORE/biu_register_cs_9")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_8 "BIU_CORE/biu_register_cs_8")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_7 "BIU_CORE/biu_register_cs_7")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_6 "BIU_CORE/biu_register_cs_6")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_5 "BIU_CORE/biu_register_cs_5")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_4 "BIU_CORE/biu_register_cs_4")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_3 "BIU_CORE/biu_register_cs_3")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_2 "BIU_CORE/biu_register_cs_2")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_1 "BIU_CORE/biu_register_cs_1")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_0 "BIU_CORE/biu_register_cs_0")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_15 "BIU_CORE/biu_register_ds_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_14 "BIU_CORE/biu_register_ds_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_13 "BIU_CORE/biu_register_ds_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_12 "BIU_CORE/biu_register_ds_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_11 "BIU_CORE/biu_register_ds_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_10 "BIU_CORE/biu_register_ds_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_9 "BIU_CORE/biu_register_ds_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_8 "BIU_CORE/biu_register_ds_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_7 "BIU_CORE/biu_register_ds_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_6 "BIU_CORE/biu_register_ds_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_5 "BIU_CORE/biu_register_ds_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_4 "BIU_CORE/biu_register_ds_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_3 "BIU_CORE/biu_register_ds_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_2 "BIU_CORE/biu_register_ds_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_1 "BIU_CORE/biu_register_ds_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_0 "BIU_CORE/biu_register_ds_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_15 "BIU_CORE/biu_register_ss_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_14 "BIU_CORE/biu_register_ss_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_13 "BIU_CORE/biu_register_ss_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_12 "BIU_CORE/biu_register_ss_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_11 "BIU_CORE/biu_register_ss_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_10 "BIU_CORE/biu_register_ss_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_9 "BIU_CORE/biu_register_ss_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_8 "BIU_CORE/biu_register_ss_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_7 "BIU_CORE/biu_register_ss_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_6 "BIU_CORE/biu_register_ss_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_5 "BIU_CORE/biu_register_ss_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_4 "BIU_CORE/biu_register_ss_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_3 "BIU_CORE/biu_register_ss_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_2 "BIU_CORE/biu_register_ss_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_1 "BIU_CORE/biu_register_ss_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_0 "BIU_CORE/biu_register_ss_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_15 "BIU_CORE/biu_register_es_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_14 "BIU_CORE/biu_register_es_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_13 "BIU_CORE/biu_register_es_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_12 "BIU_CORE/biu_register_es_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_11 "BIU_CORE/biu_register_es_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_10 "BIU_CORE/biu_register_es_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_9 "BIU_CORE/biu_register_es_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_8 "BIU_CORE/biu_register_es_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_7 "BIU_CORE/biu_register_es_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_6 "BIU_CORE/biu_register_es_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_5 "BIU_CORE/biu_register_es_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_4 "BIU_CORE/biu_register_es_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_3 "BIU_CORE/biu_register_es_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_2 "BIU_CORE/biu_register_es_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_1 "BIU_CORE/biu_register_es_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_0 "BIU_CORE/biu_register_es_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ad_in_int_7 "BIU_CORE/ad_in_int_7")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ad_in_int_6 "BIU_CORE/ad_in_int_6")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ad_in_int_5 "BIU_CORE/ad_in_int_5")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ad_in_int_4 "BIU_CORE/ad_in_int_4")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ad_in_int_3 "BIU_CORE/ad_in_int_3")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ad_in_int_2 "BIU_CORE/ad_in_int_2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ad_in_int_1 "BIU_CORE/ad_in_int_1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ad_in_int_0 "BIU_CORE/ad_in_int_0")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux31_4_renamed_54 "EU_CORE/mux31_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF0F5533") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux31_5_renamed_55 "EU_CORE/mux31_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "33330F0F555500FF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux31_3_f7_renamed_56 "EU_CORE/mux31_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux31_51_renamed_57 "EU_CORE/mux31_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux31_6_renamed_58 "EU_CORE/mux31_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux31_4_f7_renamed_59 "EU_CORE/mux31_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux31_2_f8 "EU_CORE/mux31_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux29_4_renamed_60 "EU_CORE/mux29_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF330F55") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux29_5_renamed_61 "EU_CORE/mux29_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux29_3_f7_renamed_62 "EU_CORE/mux29_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux29_51_renamed_63 "EU_CORE/mux29_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux29_6_renamed_64 "EU_CORE/mux29_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux29_4_f7_renamed_65 "EU_CORE/mux29_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux29_2_f8 "EU_CORE/mux29_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux28_4_renamed_66 "EU_CORE/mux28_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF0F3355") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux28_5_renamed_67 "EU_CORE/mux28_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux28_3_f7_renamed_68 "EU_CORE/mux28_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux28_51_renamed_69 "EU_CORE/mux28_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux28_6_renamed_70 "EU_CORE/mux28_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux28_4_f7_renamed_71 "EU_CORE/mux28_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux28_2_f8 "EU_CORE/mux28_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux30_4_renamed_72 "EU_CORE/mux30_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF0F3355") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux30_5_renamed_73 "EU_CORE/mux30_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "33330F0F555500FF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux30_3_f7_renamed_74 "EU_CORE/mux30_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux30_51_renamed_75 "EU_CORE/mux30_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux30_6_renamed_76 "EU_CORE/mux30_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux30_4_f7_renamed_77 "EU_CORE/mux30_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux30_2_f8 "EU_CORE/mux30_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux27_6_renamed_78 "EU_CORE/mux27_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux27_7_renamed_79 "EU_CORE/mux27_7")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux27_71_renamed_80 "EU_CORE/mux27_71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux27_8_renamed_81 "EU_CORE/mux27_8")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F305") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux26_4_renamed_82 "EU_CORE/mux26_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF0F5533") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux26_5_renamed_83 "EU_CORE/mux26_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux26_3_f7_renamed_84 "EU_CORE/mux26_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux26_51_renamed_85 "EU_CORE/mux26_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux26_6_renamed_86 "EU_CORE/mux26_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux26_4_f7_renamed_87 "EU_CORE/mux26_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux26_2_f8 "EU_CORE/mux26_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux25_4_renamed_88 "EU_CORE/mux25_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF550F33") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux25_5_renamed_89 "EU_CORE/mux25_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux25_3_f7_renamed_90 "EU_CORE/mux25_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux25_51_renamed_91 "EU_CORE/mux25_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux25_6_renamed_92 "EU_CORE/mux25_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux25_4_f7_renamed_93 "EU_CORE/mux25_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux25_2_f8 "EU_CORE/mux25_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux24_4_renamed_94 "EU_CORE/mux24_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF550F33") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux24_5_renamed_95 "EU_CORE/mux24_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux24_3_f7_renamed_96 "EU_CORE/mux24_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux24_51_renamed_97 "EU_CORE/mux24_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux24_6_renamed_98 "EU_CORE/mux24_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux24_4_f7_renamed_99 "EU_CORE/mux24_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux24_2_f8 "EU_CORE/mux24_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux22_6_renamed_100 "EU_CORE/mux22_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux22_7_renamed_101 "EU_CORE/mux22_7")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux22_71_renamed_102 "EU_CORE/mux22_71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux22_8_renamed_103 "EU_CORE/mux22_8")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F5F3") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux21_6_renamed_104 "EU_CORE/mux21_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux21_7_renamed_105 "EU_CORE/mux21_7")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux21_71_renamed_106 "EU_CORE/mux21_71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux21_8_renamed_107 "EU_CORE/mux21_8")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F3F5") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux23_5_renamed_108 "EU_CORE/mux23_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux23_3_f7_renamed_109 "EU_CORE/mux23_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux23_51_renamed_110 "EU_CORE/mux23_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux23_6_renamed_111 "EU_CORE/mux23_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux23_4_f7_renamed_112 "EU_CORE/mux23_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux23_2_f8 "EU_CORE/mux23_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux20_4_renamed_113 "EU_CORE/mux20_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF0F5533") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux20_5_renamed_114 "EU_CORE/mux20_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux20_3_f7_renamed_115 "EU_CORE/mux20_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux20_51_renamed_116 "EU_CORE/mux20_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux20_6_renamed_117 "EU_CORE/mux20_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux20_4_f7_renamed_118 "EU_CORE/mux20_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux20_2_f8 "EU_CORE/mux20_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux19_4_renamed_119 "EU_CORE/mux19_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF330F55") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux19_5_renamed_120 "EU_CORE/mux19_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux19_3_f7_renamed_121 "EU_CORE/mux19_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux19_51_renamed_122 "EU_CORE/mux19_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux19_6_renamed_123 "EU_CORE/mux19_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux19_4_f7_renamed_124 "EU_CORE/mux19_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux19_2_f8 "EU_CORE/mux19_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux18_4_renamed_125 "EU_CORE/mux18_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF33550F") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux18_5_renamed_126 "EU_CORE/mux18_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux18_3_f7_renamed_127 "EU_CORE/mux18_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux18_51_renamed_128 "EU_CORE/mux18_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux18_6_renamed_129 "EU_CORE/mux18_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux18_4_f7_renamed_130 "EU_CORE/mux18_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux18_2_f8 "EU_CORE/mux18_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux17_6_renamed_131 "EU_CORE/mux17_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux17_7_renamed_132 "EU_CORE/mux17_7")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux17_71_renamed_133 "EU_CORE/mux17_71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux17_8_renamed_134 "EU_CORE/mux17_8")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F5F3") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux15_4_renamed_135 "EU_CORE/mux15_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00CCCCAAAAF0F0") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux15_5_renamed_136 "EU_CORE/mux15_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux15_3_f7_renamed_137 "EU_CORE/mux15_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux15_51_renamed_138 "EU_CORE/mux15_51")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCF0AA00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux15_6_renamed_139 "EU_CORE/mux15_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux15_4_f7_renamed_140 "EU_CORE/mux15_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux15_2_f8 "EU_CORE/mux15_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux14_4_renamed_141 "EU_CORE/mux14_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00F0F0AAAACCCC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux14_5_renamed_142 "EU_CORE/mux14_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux14_3_f7_renamed_143 "EU_CORE/mux14_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux14_51_renamed_144 "EU_CORE/mux14_51")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCF0AA00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux14_6_renamed_145 "EU_CORE/mux14_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux14_4_f7_renamed_146 "EU_CORE/mux14_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux14_2_f8 "EU_CORE/mux14_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux16_4_renamed_147 "EU_CORE/mux16_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF33550F") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux16_5_renamed_148 "EU_CORE/mux16_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux16_3_f7_renamed_149 "EU_CORE/mux16_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux16_51_renamed_150 "EU_CORE/mux16_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux16_6_renamed_151 "EU_CORE/mux16_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux16_4_f7_renamed_152 "EU_CORE/mux16_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux16_2_f8 "EU_CORE/mux16_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux13_4_renamed_153 "EU_CORE/mux13_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux13_5_renamed_154 "EU_CORE/mux13_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux13_3_f7_renamed_155 "EU_CORE/mux13_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux13_51_renamed_156 "EU_CORE/mux13_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCF0F0AAAAFF00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux13_6_renamed_157 "EU_CORE/mux13_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux13_4_f7_renamed_158 "EU_CORE/mux13_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux13_2_f8 "EU_CORE/mux13_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux12_4_renamed_159 "EU_CORE/mux12_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00F0F0CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux12_5_renamed_160 "EU_CORE/mux12_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux12_3_f7_renamed_161 "EU_CORE/mux12_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux12_51_renamed_162 "EU_CORE/mux12_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCF0F0AAAAFF00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux12_6_renamed_163 "EU_CORE/mux12_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux12_4_f7_renamed_164 "EU_CORE/mux12_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux12_2_f8 "EU_CORE/mux12_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux11_4_renamed_165 "EU_CORE/mux11_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0AAFFCC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux11_5_renamed_166 "EU_CORE/mux11_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux11_3_f7_renamed_167 "EU_CORE/mux11_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux11_51_renamed_168 "EU_CORE/mux11_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCF0F0AAAAFF00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux11_6_renamed_169 "EU_CORE/mux11_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux11_4_f7_renamed_170 "EU_CORE/mux11_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux11_2_f8 "EU_CORE/mux11_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux10_4_renamed_171 "EU_CORE/mux10_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00AAAAF0F0CCCC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux10_5_renamed_172 "EU_CORE/mux10_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux10_3_f7_renamed_173 "EU_CORE/mux10_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux10_51_renamed_174 "EU_CORE/mux10_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCF0F0AAAAFF00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux10_6_renamed_175 "EU_CORE/mux10_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux10_4_f7_renamed_176 "EU_CORE/mux10_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux10_2_f8 "EU_CORE/mux10_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux8_4_renamed_177 "EU_CORE/mux8_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux8_5_renamed_178 "EU_CORE/mux8_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux8_3_f7_renamed_179 "EU_CORE/mux8_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux8_51_renamed_180 "EU_CORE/mux8_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCF0F0AAAAFF00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux8_6_renamed_181 "EU_CORE/mux8_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux8_4_f7_renamed_182 "EU_CORE/mux8_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux8_2_f8 "EU_CORE/mux8_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux7_4_renamed_183 "EU_CORE/mux7_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00F0F0CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux7_5_renamed_184 "EU_CORE/mux7_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux7_3_f7_renamed_185 "EU_CORE/mux7_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux7_51_renamed_186 "EU_CORE/mux7_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCF0F0AAAAFF00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux7_6_renamed_187 "EU_CORE/mux7_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux7_4_f7_renamed_188 "EU_CORE/mux7_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux7_2_f8 "EU_CORE/mux7_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux9_4_renamed_189 "EU_CORE/mux9_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00F0F0CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux9_5_renamed_190 "EU_CORE/mux9_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux9_3_f7_renamed_191 "EU_CORE/mux9_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux9_51_renamed_192 "EU_CORE/mux9_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCF0F0AAAAFF00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux9_6_renamed_193 "EU_CORE/mux9_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux9_4_f7_renamed_194 "EU_CORE/mux9_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux9_2_f8 "EU_CORE/mux9_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux6_6_renamed_195 "EU_CORE/mux6_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux6_7_renamed_196 "EU_CORE/mux6_7")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCF0AA00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux6_71_renamed_197 "EU_CORE/mux6_71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux6_8_renamed_198 "EU_CORE/mux6_8")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F000AACC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux5_6_renamed_199 "EU_CORE/mux5_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux5_7_renamed_200 "EU_CORE/mux5_7")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCF0AA00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux5_71_renamed_201 "EU_CORE/mux5_71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux5_8_renamed_202 "EU_CORE/mux5_8")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F000AACC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux4_4_renamed_203 "EU_CORE/mux4_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00CCCCAAAAF0F0") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux4_5_renamed_204 "EU_CORE/mux4_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux4_3_f7_renamed_205 "EU_CORE/mux4_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux4_51_renamed_206 "EU_CORE/mux4_51")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCF0AA00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux4_6_renamed_207 "EU_CORE/mux4_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux4_4_f7_renamed_208 "EU_CORE/mux4_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux4_2_f8 "EU_CORE/mux4_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux3_4_renamed_209 "EU_CORE/mux3_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00AAAACCCC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux3_5_renamed_210 "EU_CORE/mux3_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux3_3_f7_renamed_211 "EU_CORE/mux3_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux3_51_renamed_212 "EU_CORE/mux3_51")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCF0AA00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux3_6_renamed_213 "EU_CORE/mux3_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux3_4_f7_renamed_214 "EU_CORE/mux3_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux3_2_f8 "EU_CORE/mux3_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux1_6_renamed_215 "EU_CORE/mux1_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux1_7_renamed_216 "EU_CORE/mux1_7")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCF0AA00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux1_71_renamed_217 "EU_CORE/mux1_71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux1_8_renamed_218 "EU_CORE/mux1_8")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F000AACC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux_4_renamed_219 "EU_CORE/mux_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00AAAAF0F0CCCC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux_5_renamed_220 "EU_CORE/mux_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux_3_f7_renamed_221 "EU_CORE/mux_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux_51_renamed_222 "EU_CORE/mux_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCF0F0AAAAFF00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux_6_renamed_223 "EU_CORE/mux_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux_4_f7_renamed_224 "EU_CORE/mux_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux_2_f8 "EU_CORE/mux_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux2_4_renamed_225 "EU_CORE/mux2_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00CCCCAAAAF0F0") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux2_5_renamed_226 "EU_CORE/mux2_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux2_3_f7_renamed_227 "EU_CORE/mux2_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux2_51_renamed_228 "EU_CORE/mux2_51")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCF0AA00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux2_6_renamed_229 "EU_CORE/mux2_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux2_4_f7_renamed_230 "EU_CORE/mux2_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux2_2_f8 "EU_CORE/mux2_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_11 "EU_CORE/eu_rom_address_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_10 "EU_CORE/eu_rom_address_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_12 "EU_CORE/eu_rom_address_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_9 "EU_CORE/eu_rom_address_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_8 "EU_CORE/eu_rom_address_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_7 "EU_CORE/eu_rom_address_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_6 "EU_CORE/eu_rom_address_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_5 "EU_CORE/eu_rom_address_5")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_4 "EU_CORE/eu_rom_address_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_3 "EU_CORE/eu_rom_address_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_2 "EU_CORE/eu_rom_address_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_1 "EU_CORE/eu_rom_address_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_0 "EU_CORE/eu_rom_address_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_xor_12__ "EU_CORE/Mcount_eu_rom_address_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_lut_12__ "EU_CORE/Mcount_eu_rom_address_lut<12>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_xor_11__ "EU_CORE/Mcount_eu_rom_address_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_cy_11__ "EU_CORE/Mcount_eu_rom_address_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_xor_10__ "EU_CORE/Mcount_eu_rom_address_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_cy_10__ "EU_CORE/Mcount_eu_rom_address_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_xor_9__ "EU_CORE/Mcount_eu_rom_address_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_cy_9__ "EU_CORE/Mcount_eu_rom_address_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_xor_8__ "EU_CORE/Mcount_eu_rom_address_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_cy_8__ "EU_CORE/Mcount_eu_rom_address_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_xor_7__ "EU_CORE/Mcount_eu_rom_address_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_cy_7__ "EU_CORE/Mcount_eu_rom_address_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_xor_6__ "EU_CORE/Mcount_eu_rom_address_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_cy_6__ "EU_CORE/Mcount_eu_rom_address_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_xor_5__ "EU_CORE/Mcount_eu_rom_address_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_cy_5__ "EU_CORE/Mcount_eu_rom_address_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_xor_4__ "EU_CORE/Mcount_eu_rom_address_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_cy_4__ "EU_CORE/Mcount_eu_rom_address_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_xor_3__ "EU_CORE/Mcount_eu_rom_address_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_cy_3__ "EU_CORE/Mcount_eu_rom_address_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_xor_2__ "EU_CORE/Mcount_eu_rom_address_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_cy_2__ "EU_CORE/Mcount_eu_rom_address_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_lut_2__ "EU_CORE/Mcount_eu_rom_address_lut<2>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_xor_1__ "EU_CORE/Mcount_eu_rom_address_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_cy_1__ "EU_CORE/Mcount_eu_rom_address_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_lut_1__ "EU_CORE/Mcount_eu_rom_address_lut<1>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_xor_0__ "EU_CORE/Mcount_eu_rom_address_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_cy_0__ "EU_CORE/Mcount_eu_rom_address_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_lut_0__ "EU_CORE/Mcount_eu_rom_address_lut<0>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_15 "EU_CORE/eu_register_r0_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_14 "EU_CORE/eu_register_r0_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_13 "EU_CORE/eu_register_r0_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_12 "EU_CORE/eu_register_r0_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_11 "EU_CORE/eu_register_r0_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_10 "EU_CORE/eu_register_r0_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_9 "EU_CORE/eu_register_r0_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_8 "EU_CORE/eu_register_r0_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_7 "EU_CORE/eu_register_r0_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_6 "EU_CORE/eu_register_r0_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_5 "EU_CORE/eu_register_r0_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_4 "EU_CORE/eu_register_r0_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_3 "EU_CORE/eu_register_r0_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_2 "EU_CORE/eu_register_r0_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_1 "EU_CORE/eu_register_r0_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_0 "EU_CORE/eu_register_r0_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_15 "EU_CORE/eu_alu_last_result_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_14 "EU_CORE/eu_alu_last_result_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_13 "EU_CORE/eu_alu_last_result_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_12 "EU_CORE/eu_alu_last_result_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_11 "EU_CORE/eu_alu_last_result_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_10 "EU_CORE/eu_alu_last_result_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_9 "EU_CORE/eu_alu_last_result_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_8 "EU_CORE/eu_alu_last_result_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_7 "EU_CORE/eu_alu_last_result_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_6 "EU_CORE/eu_alu_last_result_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_5 "EU_CORE/eu_alu_last_result_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_4 "EU_CORE/eu_alu_last_result_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_3 "EU_CORE/eu_alu_last_result_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_2 "EU_CORE/eu_alu_last_result_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_1 "EU_CORE/eu_alu_last_result_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_0 "EU_CORE/eu_alu_last_result_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_51 "EU_CORE/eu_calling_address_51")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_50 "EU_CORE/eu_calling_address_50")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_49 "EU_CORE/eu_calling_address_49")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_48 "EU_CORE/eu_calling_address_48")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_47 "EU_CORE/eu_calling_address_47")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_46 "EU_CORE/eu_calling_address_46")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_45 "EU_CORE/eu_calling_address_45")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_44 "EU_CORE/eu_calling_address_44")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_43 "EU_CORE/eu_calling_address_43")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_42 "EU_CORE/eu_calling_address_42")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_41 "EU_CORE/eu_calling_address_41")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_40 "EU_CORE/eu_calling_address_40")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_39 "EU_CORE/eu_calling_address_39")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_38 "EU_CORE/eu_calling_address_38")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_37 "EU_CORE/eu_calling_address_37")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_36 "EU_CORE/eu_calling_address_36")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_35 "EU_CORE/eu_calling_address_35")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_34 "EU_CORE/eu_calling_address_34")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_33 "EU_CORE/eu_calling_address_33")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_32 "EU_CORE/eu_calling_address_32")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_31 "EU_CORE/eu_calling_address_31")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_30 "EU_CORE/eu_calling_address_30")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_29 "EU_CORE/eu_calling_address_29")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_28 "EU_CORE/eu_calling_address_28")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_27 "EU_CORE/eu_calling_address_27")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_26 "EU_CORE/eu_calling_address_26")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_25 "EU_CORE/eu_calling_address_25")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_24 "EU_CORE/eu_calling_address_24")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_23 "EU_CORE/eu_calling_address_23")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_22 "EU_CORE/eu_calling_address_22")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_21 "EU_CORE/eu_calling_address_21")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_20 "EU_CORE/eu_calling_address_20")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_19 "EU_CORE/eu_calling_address_19")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_18 "EU_CORE/eu_calling_address_18")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_17 "EU_CORE/eu_calling_address_17")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_16 "EU_CORE/eu_calling_address_16")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_15 "EU_CORE/eu_calling_address_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_14 "EU_CORE/eu_calling_address_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_13 "EU_CORE/eu_calling_address_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_12 "EU_CORE/eu_calling_address_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_11 "EU_CORE/eu_calling_address_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_10 "EU_CORE/eu_calling_address_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_9 "EU_CORE/eu_calling_address_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_8 "EU_CORE/eu_calling_address_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_7 "EU_CORE/eu_calling_address_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_6 "EU_CORE/eu_calling_address_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_5 "EU_CORE/eu_calling_address_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_4 "EU_CORE/eu_calling_address_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_3 "EU_CORE/eu_calling_address_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_2 "EU_CORE/eu_calling_address_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_1 "EU_CORE/eu_calling_address_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_0 "EU_CORE/eu_calling_address_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_add_overflow8_renamed_231 "EU_CORE/eu_add_overflow8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_add_overflow16_renamed_232 "EU_CORE/eu_add_overflow16")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flag_t_d_renamed_233 "EU_CORE/eu_flag_t_d")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_biu_done_d2_renamed_234 "EU_CORE/biu_done_d2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_15 "EU_CORE/eu_biu_dataout_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_14 "EU_CORE/eu_biu_dataout_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_13 "EU_CORE/eu_biu_dataout_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_12 "EU_CORE/eu_biu_dataout_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_11 "EU_CORE/eu_biu_dataout_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_10 "EU_CORE/eu_biu_dataout_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_9 "EU_CORE/eu_biu_dataout_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_8 "EU_CORE/eu_biu_dataout_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_7 "EU_CORE/eu_biu_dataout_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_6 "EU_CORE/eu_biu_dataout_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_5 "EU_CORE/eu_biu_dataout_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_4 "EU_CORE/eu_biu_dataout_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_3 "EU_CORE/eu_biu_dataout_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_2 "EU_CORE/eu_biu_dataout_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_1 "EU_CORE/eu_biu_dataout_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_0 "EU_CORE/eu_biu_dataout_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_15 "EU_CORE/eu_biu_command_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_14 "EU_CORE/eu_biu_command_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_13 "EU_CORE/eu_biu_command_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_12 "EU_CORE/eu_biu_command_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_11 "EU_CORE/eu_biu_command_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_10 "EU_CORE/eu_biu_command_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_9 "EU_CORE/eu_biu_command_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_8 "EU_CORE/eu_biu_command_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_7 "EU_CORE/eu_biu_command_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_6 "EU_CORE/eu_biu_command_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_5 "EU_CORE/eu_biu_command_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_4 "EU_CORE/eu_biu_command_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_3 "EU_CORE/eu_biu_command_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_2 "EU_CORE/eu_biu_command_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_1 "EU_CORE/eu_biu_command_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_0 "EU_CORE/eu_biu_command_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_15 "EU_CORE/eu_register_r2_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_14 "EU_CORE/eu_register_r2_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_13 "EU_CORE/eu_register_r2_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_12 "EU_CORE/eu_register_r2_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_11 "EU_CORE/eu_register_r2_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_10 "EU_CORE/eu_register_r2_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_9 "EU_CORE/eu_register_r2_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_8 "EU_CORE/eu_register_r2_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_7 "EU_CORE/eu_register_r2_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_6 "EU_CORE/eu_register_r2_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_5 "EU_CORE/eu_register_r2_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_4 "EU_CORE/eu_register_r2_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_3 "EU_CORE/eu_register_r2_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_2 "EU_CORE/eu_register_r2_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_1 "EU_CORE/eu_register_r2_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_0 "EU_CORE/eu_register_r2_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_15 "EU_CORE/eu_register_r1_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_14 "EU_CORE/eu_register_r1_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_13 "EU_CORE/eu_register_r1_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_12 "EU_CORE/eu_register_r1_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_11 "EU_CORE/eu_register_r1_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_10 "EU_CORE/eu_register_r1_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_9 "EU_CORE/eu_register_r1_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_8 "EU_CORE/eu_register_r1_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_7 "EU_CORE/eu_register_r1_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_6 "EU_CORE/eu_register_r1_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_5 "EU_CORE/eu_register_r1_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_4 "EU_CORE/eu_register_r1_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_3 "EU_CORE/eu_register_r1_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_2 "EU_CORE/eu_register_r1_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_1 "EU_CORE/eu_register_r1_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_0 "EU_CORE/eu_register_r1_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_15 "EU_CORE/eu_register_r3_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_14 "EU_CORE/eu_register_r3_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_13 "EU_CORE/eu_register_r3_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_12 "EU_CORE/eu_register_r3_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_11 "EU_CORE/eu_register_r3_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_10 "EU_CORE/eu_register_r3_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_9 "EU_CORE/eu_register_r3_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_8 "EU_CORE/eu_register_r3_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_7 "EU_CORE/eu_register_r3_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_6 "EU_CORE/eu_register_r3_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_5 "EU_CORE/eu_register_r3_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_4 "EU_CORE/eu_register_r3_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_3 "EU_CORE/eu_register_r3_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_2 "EU_CORE/eu_register_r3_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_1 "EU_CORE/eu_register_r3_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_0 "EU_CORE/eu_register_r3_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_15 "EU_CORE/eu_flags_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_14 "EU_CORE/eu_flags_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_13 "EU_CORE/eu_flags_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_12 "EU_CORE/eu_flags_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_11 "EU_CORE/eu_flags_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_10 "EU_CORE/eu_flags_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_9 "EU_CORE/eu_flags_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_8 "EU_CORE/eu_flags_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_7 "EU_CORE/eu_flags_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_6 "EU_CORE/eu_flags_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_5 "EU_CORE/eu_flags_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_4 "EU_CORE/eu_flags_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_3 "EU_CORE/eu_flags_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_2 "EU_CORE/eu_flags_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_1 "EU_CORE/eu_flags_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_0 "EU_CORE/eu_flags_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_15 "EU_CORE/eu_register_di_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_14 "EU_CORE/eu_register_di_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_13 "EU_CORE/eu_register_di_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_12 "EU_CORE/eu_register_di_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_11 "EU_CORE/eu_register_di_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_10 "EU_CORE/eu_register_di_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_9 "EU_CORE/eu_register_di_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_8 "EU_CORE/eu_register_di_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_7 "EU_CORE/eu_register_di_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_6 "EU_CORE/eu_register_di_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_5 "EU_CORE/eu_register_di_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_4 "EU_CORE/eu_register_di_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_3 "EU_CORE/eu_register_di_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_2 "EU_CORE/eu_register_di_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_1 "EU_CORE/eu_register_di_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_0 "EU_CORE/eu_register_di_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_15 "EU_CORE/eu_register_bp_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_14 "EU_CORE/eu_register_bp_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_13 "EU_CORE/eu_register_bp_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_12 "EU_CORE/eu_register_bp_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_11 "EU_CORE/eu_register_bp_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_10 "EU_CORE/eu_register_bp_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_9 "EU_CORE/eu_register_bp_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_8 "EU_CORE/eu_register_bp_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_7 "EU_CORE/eu_register_bp_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_6 "EU_CORE/eu_register_bp_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_5 "EU_CORE/eu_register_bp_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_4 "EU_CORE/eu_register_bp_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_3 "EU_CORE/eu_register_bp_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_2 "EU_CORE/eu_register_bp_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_1 "EU_CORE/eu_register_bp_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_0 "EU_CORE/eu_register_bp_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_15 "EU_CORE/eu_register_sp_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_14 "EU_CORE/eu_register_sp_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_13 "EU_CORE/eu_register_sp_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_12 "EU_CORE/eu_register_sp_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_11 "EU_CORE/eu_register_sp_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_10 "EU_CORE/eu_register_sp_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_9 "EU_CORE/eu_register_sp_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_8 "EU_CORE/eu_register_sp_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_7 "EU_CORE/eu_register_sp_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_6 "EU_CORE/eu_register_sp_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_5 "EU_CORE/eu_register_sp_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_4 "EU_CORE/eu_register_sp_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_3 "EU_CORE/eu_register_sp_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_2 "EU_CORE/eu_register_sp_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_1 "EU_CORE/eu_register_sp_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_0 "EU_CORE/eu_register_sp_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_15 "EU_CORE/eu_register_si_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_14 "EU_CORE/eu_register_si_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_13 "EU_CORE/eu_register_si_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_12 "EU_CORE/eu_register_si_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_11 "EU_CORE/eu_register_si_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_10 "EU_CORE/eu_register_si_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_9 "EU_CORE/eu_register_si_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_8 "EU_CORE/eu_register_si_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_7 "EU_CORE/eu_register_si_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_6 "EU_CORE/eu_register_si_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_5 "EU_CORE/eu_register_si_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_4 "EU_CORE/eu_register_si_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_3 "EU_CORE/eu_register_si_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_2 "EU_CORE/eu_register_si_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_1 "EU_CORE/eu_register_si_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_0 "EU_CORE/eu_register_si_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_15 "EU_CORE/eu_register_dx_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_14 "EU_CORE/eu_register_dx_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_13 "EU_CORE/eu_register_dx_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_12 "EU_CORE/eu_register_dx_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_11 "EU_CORE/eu_register_dx_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_10 "EU_CORE/eu_register_dx_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_9 "EU_CORE/eu_register_dx_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_8 "EU_CORE/eu_register_dx_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_7 "EU_CORE/eu_register_dx_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_6 "EU_CORE/eu_register_dx_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_5 "EU_CORE/eu_register_dx_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_4 "EU_CORE/eu_register_dx_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_3 "EU_CORE/eu_register_dx_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_2 "EU_CORE/eu_register_dx_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_1 "EU_CORE/eu_register_dx_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_0 "EU_CORE/eu_register_dx_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_15 "EU_CORE/eu_register_cx_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_14 "EU_CORE/eu_register_cx_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_13 "EU_CORE/eu_register_cx_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_12 "EU_CORE/eu_register_cx_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_11 "EU_CORE/eu_register_cx_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_10 "EU_CORE/eu_register_cx_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_9 "EU_CORE/eu_register_cx_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_8 "EU_CORE/eu_register_cx_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_7 "EU_CORE/eu_register_cx_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_6 "EU_CORE/eu_register_cx_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_5 "EU_CORE/eu_register_cx_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_4 "EU_CORE/eu_register_cx_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_3 "EU_CORE/eu_register_cx_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_2 "EU_CORE/eu_register_cx_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_1 "EU_CORE/eu_register_cx_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_0 "EU_CORE/eu_register_cx_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_15 "EU_CORE/eu_register_bx_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_14 "EU_CORE/eu_register_bx_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_13 "EU_CORE/eu_register_bx_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_12 "EU_CORE/eu_register_bx_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_11 "EU_CORE/eu_register_bx_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_10 "EU_CORE/eu_register_bx_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_9 "EU_CORE/eu_register_bx_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_8 "EU_CORE/eu_register_bx_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_7 "EU_CORE/eu_register_bx_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_6 "EU_CORE/eu_register_bx_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_5 "EU_CORE/eu_register_bx_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_4 "EU_CORE/eu_register_bx_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_3 "EU_CORE/eu_register_bx_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_2 "EU_CORE/eu_register_bx_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_1 "EU_CORE/eu_register_bx_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_0 "EU_CORE/eu_register_bx_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_15 "EU_CORE/eu_register_ax_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_14 "EU_CORE/eu_register_ax_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_13 "EU_CORE/eu_register_ax_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_12 "EU_CORE/eu_register_ax_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_11 "EU_CORE/eu_register_ax_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_10 "EU_CORE/eu_register_ax_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_9 "EU_CORE/eu_register_ax_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_8 "EU_CORE/eu_register_ax_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_7 "EU_CORE/eu_register_ax_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_6 "EU_CORE/eu_register_ax_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_5 "EU_CORE/eu_register_ax_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_4 "EU_CORE/eu_register_ax_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_3 "EU_CORE/eu_register_ax_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_2 "EU_CORE/eu_register_ax_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_1 "EU_CORE/eu_register_ax_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_0 "EU_CORE/eu_register_ax_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_add_carry8_renamed_235 "EU_CORE/eu_add_carry8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_add_carry_renamed_236 "EU_CORE/eu_add_carry")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_add_aux_carry_renamed_237 "EU_CORE/eu_add_aux_carry")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_stall_pipeline_renamed_238 "EU_CORE/eu_stall_pipeline")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_biu_done_d1_renamed_239 "EU_CORE/biu_done_d1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__ale_int_Select_176_o1 "BIU_CORE/biu_state[7]_ale_int_Select_176_o1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFF8A8AAA8A") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_Select_163_o112 "BIU_CORE/biu_state[7]_GND_10_o_Select_163_o112")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFF4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0865_inv1 "BIU_CORE/_n0865_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___13___BIU_CORE/_n0865_inv1") (owner "Xilinx"))
+              (property INIT (string "08000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0861_inv1 "BIU_CORE/_n0861_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___13___BIU_CORE/_n0865_inv1") (owner "Xilinx"))
+              (property INIT (string "04000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0857_inv1 "BIU_CORE/_n0857_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___12___BIU_CORE/_n0857_inv1") (owner "Xilinx"))
+              (property INIT (string "08000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0853_inv1 "BIU_CORE/_n0853_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___12___BIU_CORE/_n0857_inv1") (owner "Xilinx"))
+              (property INIT (string "04000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0905_inv1 "BIU_CORE/_n0905_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___14___BIU_CORE/_n0905_inv1") (owner "Xilinx"))
+              (property INIT (string "04000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0849_inv1 "BIU_CORE/_n0849_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___14___BIU_CORE/_n0905_inv1") (owner "Xilinx"))
+              (property INIT (string "01000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n09261 "BIU_CORE/_n09261")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___9___BIU_CORE/_n09261") (owner "Xilinx"))
+              (property INIT (string "E8AFA8AF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_11_o1 "BIU_CORE/eu_biu_req_caught_eu_biu_req_code[4]_AND_11_o1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0008000000000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_state_7__GND_10_o_add_87_OUT_cy_4_11 "BIU_CORE/Madd_biu_state[7]_GND_10_o_add_87_OUT_cy<4>11")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "80000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_biu_req_code_4__PWR_2_o_equal_102_o_4_1 "BIU_CORE/eu_biu_req_code[4]_PWR_2_o_equal_102_o<4>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___8___BIU_CORE/eu_biu_req_code[4]_PWR_2_o_equal_102_o<4>1") (owner "Xilinx"))
+              (property INIT (string "01000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_out91 "BIU_CORE/out91")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFEFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_150_o_7_2 "BIU_CORE/biu_state[7]_GND_10_o_equal_150_o<7>2")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "04000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_146_o_7_2 "BIU_CORE/biu_state[7]_GND_10_o_equal_146_o<7>2")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___1___BIU_CORE/biu_state[7]_GND_10_o_equal_146_o<7>2") (owner "Xilinx"))
+              (property INIT (string "0100") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_148_o_7_1 "BIU_CORE/biu_state[7]_GND_10_o_equal_148_o<7>1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___5___BIU_CORE/biu_state[7]_GND_10_o_equal_148_o<7>1") (owner "Xilinx"))
+              (property INIT (string "0200") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_159_o_7_1 "BIU_CORE/biu_state[7]_GND_10_o_equal_159_o<7>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___0___BIU_CORE/biu_state[7]_GND_10_o_equal_159_o<7>1") (owner "Xilinx"))
+              (property INIT (string "00200000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n09181 "BIU_CORE/_n09181")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___8___BIU_CORE/eu_biu_req_code[4]_PWR_2_o_equal_102_o<4>1") (owner "Xilinx"))
+              (property INIT (string "02400140") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_111 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<5>111")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0008800800008000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__biu_done_int_Select_169_o111 "BIU_CORE/biu_state[7]_biu_done_int_Select_169_o111")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFF4000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux171 "BIU_CORE/mux171")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux161 "BIU_CORE/mux161")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux1091 "BIU_CORE/mux1091")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux1081 "BIU_CORE/mux1081")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux1071 "BIU_CORE/mux1071")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux1061 "BIU_CORE/mux1061")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux1051 "BIU_CORE/mux1051")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux1041 "BIU_CORE/mux1041")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux1031 "BIU_CORE/mux1031")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux1021 "BIU_CORE/mux1021")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux10151 "BIU_CORE/mux10151")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux10141 "BIU_CORE/mux10141")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux10131 "BIU_CORE/mux10131")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux10121 "BIU_CORE/mux10121")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux10111 "BIU_CORE/mux10111")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux1011 "BIU_CORE/mux1011")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_pfq_top_byte_int81 "BIU_CORE/Mmux_pfq_top_byte_int81")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_pfq_top_byte_int71 "BIU_CORE/Mmux_pfq_top_byte_int71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_pfq_top_byte_int61 "BIU_CORE/Mmux_pfq_top_byte_int61")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_pfq_top_byte_int51 "BIU_CORE/Mmux_pfq_top_byte_int51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_pfq_top_byte_int41 "BIU_CORE/Mmux_pfq_top_byte_int41")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_pfq_top_byte_int31 "BIU_CORE/Mmux_pfq_top_byte_int31")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_pfq_top_byte_int21 "BIU_CORE/Mmux_pfq_top_byte_int21")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_pfq_top_byte_int11 "BIU_CORE/Mmux_pfq_top_byte_int11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_biu_req_code_4__INV_26_o1 "BIU_CORE/eu_biu_req_code[4]_INV_26_o1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___15___BIU_CORE/eu_biu_req_code[4]_INV_26_o1") (owner "Xilinx"))
+              (property INIT (string "022022AA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_Select_163_o1 "BIU_CORE/biu_state[7]_GND_10_o_Select_163_o1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFA8AAA8AAA8AA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_151_o_7_1 "BIU_CORE/biu_state[7]_GND_10_o_equal_151_o<7>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___0___BIU_CORE/biu_state[7]_GND_10_o_equal_159_o<7>1") (owner "Xilinx"))
+              (property INIT (string "01000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_150_o_7_11 "BIU_CORE/biu_state[7]_GND_10_o_equal_150_o<7>11")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0010") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_154_o_7_1 "BIU_CORE/biu_state[7]_GND_10_o_equal_154_o<7>1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___2___BIU_CORE/biu_state[7]_GND_10_o_equal_154_o<7>1") (owner "Xilinx"))
+              (property INIT (string "4000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_153_o_7_1 "BIU_CORE/biu_state[7]_GND_10_o_equal_153_o<7>1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___2___BIU_CORE/biu_state[7]_GND_10_o_equal_154_o<7>1") (owner "Xilinx"))
+              (property INIT (string "4000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_152_o_7_2 "BIU_CORE/biu_state[7]_GND_10_o_equal_152_o<7>2")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___6___BIU_CORE/biu_state[7]_GND_10_o_equal_152_o<7>2") (owner "Xilinx"))
+              (property INIT (string "0100") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_152_o_7_11 "BIU_CORE/biu_state[7]_GND_10_o_equal_152_o<7>11")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00004000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_147_o_7_1 "BIU_CORE/biu_state[7]_GND_10_o_equal_147_o<7>1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___3___BIU_CORE/biu_state[7]_GND_10_o_equal_147_o<7>1") (owner "Xilinx"))
+              (property INIT (string "0200") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_156_o_7_1 "BIU_CORE/biu_state[7]_GND_10_o_equal_156_o<7>1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___1___BIU_CORE/biu_state[7]_GND_10_o_equal_146_o<7>2") (owner "Xilinx"))
+              (property INIT (string "8000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_155_o_7_1 "BIU_CORE/biu_state[7]_GND_10_o_equal_155_o<7>1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___3___BIU_CORE/biu_state[7]_GND_10_o_equal_147_o<7>1") (owner "Xilinx"))
+              (property INIT (string "0200") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_146_o_7_11 "BIU_CORE/biu_state[7]_GND_10_o_equal_146_o<7>11")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00000001") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_n00331_renamed_240 "BIU_CORE/n00331")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT17 "BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT17")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___55___BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT17") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT81 "BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT81")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___55___BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT17") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT91 "BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT91")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___54___BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT91") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT101 "BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT101")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___54___BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT91") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT111 "BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT111")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___53___BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT111") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT121 "BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT121")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___53___BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT111") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT131 "BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT131")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___52___BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT131") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT141 "BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT141")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___52___BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT131") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_biu_segment11 "BIU_CORE/Mmux_biu_segment11")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___49___BIU_CORE/Mmux_biu_segment11") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_biu_segment21 "BIU_CORE/Mmux_biu_segment21")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___49___BIU_CORE/Mmux_biu_segment11") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0870_inv1 "BIU_CORE/_n0870_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___59___BIU_CORE/_n0870_inv1") (owner "Xilinx"))
+              (property INIT (string "FF10") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0889_inv1 "BIU_CORE/_n0889_inv1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___59___BIU_CORE/_n0870_inv1") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0886_inv1 "BIU_CORE/_n0886_inv1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___41___BIU_CORE/_n0886_inv1") (owner "Xilinx"))
+              (property INIT (string "80") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0882_inv1 "BIU_CORE/_n0882_inv1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___41___BIU_CORE/_n0886_inv1") (owner "Xilinx"))
+              (property INIT (string "20") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0878_inv1 "BIU_CORE/_n0878_inv1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___40___BIU_CORE/_n0878_inv1") (owner "Xilinx"))
+              (property INIT (string "20") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0874_inv1 "BIU_CORE/_n0874_inv1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___40___BIU_CORE/_n0878_inv1") (owner "Xilinx"))
+              (property INIT (string "02") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__wr_n_int_Select_182_o1 "BIU_CORE/biu_state[7]_wr_n_int_Select_182_o1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF8F88") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__rd_n_int_Select_180_o1 "BIU_CORE/biu_state[7]_rd_n_int_Select_180_o1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFEAEAEA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_biu_strobe_1__PWR_2_o_equal_61_o_1_1 "BIU_CORE/eu_biu_strobe[1]_PWR_2_o_equal_61_o<1>1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_word_cycle_byte_num_AND_34_o1 "BIU_CORE/word_cycle_byte_num_AND_34_o1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___48___BIU_CORE/word_cycle_byte_num_AND_34_o1") (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clk_d4_clk_d2_AND_30_o1 "BIU_CORE/clk_d4_clk_d2_AND_30_o1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___42___BIU_CORE/clk_d4_clk_d2_AND_30_o1") (owner "Xilinx"))
+              (property INIT (string "02") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1080_inv21 "EU_CORE/_n1080_inv21")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___18___EU_CORE/_n1080_inv21") (owner "Xilinx"))
+              (property INIT (string "1110") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1084_inv11 "EU_CORE/_n1084_inv11")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___18___EU_CORE/_n1080_inv21") (owner "Xilinx"))
+              (property INIT (string "2220") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_stall_pipeline_eu_opcode_type_2__AND_114_o1 "EU_CORE/eu_stall_pipeline_eu_opcode_type[2]_AND_114_o1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___26___EU_CORE/eu_stall_pipeline_eu_opcode_type[2]_AND_114_o1") (owner "Xilinx"))
+              (property INIT (string "54") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1128_inv1 "EU_CORE/_n1128_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___22___EU_CORE/_n1128_inv1") (owner "Xilinx"))
+              (property INIT (string "4000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1132_inv1 "EU_CORE/_n1132_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___19___EU_CORE/_n1132_inv1") (owner "Xilinx"))
+              (property INIT (string "4000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1120_inv1 "EU_CORE/_n1120_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___22___EU_CORE/_n1128_inv1") (owner "Xilinx"))
+              (property INIT (string "4000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1124_inv1 "EU_CORE/_n1124_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___25___EU_CORE/_n1124_inv1") (owner "Xilinx"))
+              (property INIT (string "4000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1112_inv1 "EU_CORE/_n1112_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___24___EU_CORE/_n1112_inv1") (owner "Xilinx"))
+              (property INIT (string "0200") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1116_inv1 "EU_CORE/_n1116_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___25___EU_CORE/_n1124_inv1") (owner "Xilinx"))
+              (property INIT (string "0200") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1104_inv1 "EU_CORE/_n1104_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___24___EU_CORE/_n1112_inv1") (owner "Xilinx"))
+              (property INIT (string "4000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1108_inv1 "EU_CORE/_n1108_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___21___EU_CORE/_n1108_inv1") (owner "Xilinx"))
+              (property INIT (string "4000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1096_inv1 "EU_CORE/_n1096_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0200") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1100_inv1 "EU_CORE/_n1100_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___21___EU_CORE/_n1108_inv1") (owner "Xilinx"))
+              (property INIT (string "0200") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1088_inv1 "EU_CORE/_n1088_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___20___EU_CORE/_n1088_inv1") (owner "Xilinx"))
+              (property INIT (string "0200") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1092_inv1 "EU_CORE/_n1092_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___23___EU_CORE/_n1092_inv1") (owner "Xilinx"))
+              (property INIT (string "0200") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1080_inv1 "EU_CORE/_n1080_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___20___EU_CORE/_n1088_inv1") (owner "Xilinx"))
+              (property INIT (string "0100") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1084_inv1_renamed_241 "EU_CORE/_n1084_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___23___EU_CORE/_n1092_inv1") (owner "Xilinx"))
+              (property INIT (string "0100") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_3_1 "EU_CORE/carry<3>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0080AAEAA0A8FAFE") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_data_23_31 "EU_CORE/eu_rom_data<23>31")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "028A46CE139B57DF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_data_23_21 "EU_CORE/eu_rom_data<23>21")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "028A46CE139B57DF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_data_23_11 "EU_CORE/eu_rom_data<23>11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "028A46CE139B57DF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_data_23_1 "EU_CORE/eu_rom_data<23>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "028A46CE139B57DF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_data_19_21 "EU_CORE/eu_rom_data<19>21")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_data_19_11 "EU_CORE/eu_rom_data<19>11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_data_19_1 "EU_CORE/eu_rom_data<19>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457911 "EU_CORE/Mmux_n0457911")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F731") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_8_1 "EU_CORE/carry<8>1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "B2") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_4_1 "EU_CORE/carry<4>1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___17___EU_CORE/carry<4>1") (owner "Xilinx"))
+              (property INIT (string "B2") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1411 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1411")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___27___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1411") (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1110 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1110")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___28___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1110") (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1210 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1210")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___29___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1210") (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1310 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1310")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___30___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1310") (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o141 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o141")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___31___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o141") (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o151 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o151")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___32___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o151") (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o161 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o161")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___33___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o161") (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o181 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o181")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___35___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o181") (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o171 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o171")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___34___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o171") (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o191 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o191")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___36___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o191") (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1101 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1101")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___37___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1101") (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1111 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1111")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___38___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1111") (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1131 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1131")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1121 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1121")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___39___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1121") (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1141 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1141")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1151 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1151")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1161 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1161")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1181 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1181")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1171 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1171")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1191 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1191")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1201 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1201")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1211 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1211")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1231 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1231")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1221 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1221")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1241 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1241")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1251 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1251")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1261 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1261")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1281 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1281")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1271 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1271")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1291 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1291")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1301 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1301")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1311 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1311")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1331 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1331")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1321 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1321")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1341 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1341")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1351 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1351")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1361 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1361")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1381 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1381")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1371 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1371")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFD58A80") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1136_inv1 "EU_CORE/_n1136_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___19___EU_CORE/_n1132_inv1") (owner "Xilinx"))
+              (property INIT (string "8000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1391 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1391")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___43___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1391") (owner "Xilinx"))
+              (property INIT (string "BF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mxor_carry_8__carry_7__XOR_142_o_xo_0_1 "EU_CORE/Mxor_carry[8]_carry[7]_XOR_142_o_xo<0>1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "42") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT14 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT14")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___39___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1121") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT21 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT21")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___38___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1111") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT31 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT31")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___37___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1101") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT41 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT41")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___36___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o191") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT51 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT51")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___35___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o181") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT61 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT61")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___34___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o171") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT71 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT71")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___33___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o161") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT81 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT81")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___32___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o151") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT91 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT91")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___31___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o141") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT101 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT101")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___30___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1310") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT111 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT111")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___29___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1210") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT121 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT121")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___28___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1110") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT131 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT131")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___27___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1411") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1157_inv1 "EU_CORE/_n1157_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___43___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1391") (owner "Xilinx"))
+              (property INIT (string "7FFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_new_instruction1_renamed_242 "EU_CORE/new_instruction1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "5555555755555555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_stall_pipeline_eu_opcode_type_2__AND_112_o1 "EU_CORE/eu_stall_pipeline_eu_opcode_type[2]_AND_112_o1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___26___EU_CORE/eu_stall_pipeline_eu_opcode_type[2]_AND_114_o1") (owner "Xilinx"))
+              (property INIT (string "0100") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_intr_asserted1 "EU_CORE/intr_asserted1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___58___EU_CORE/intr_asserted1") (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__biu_done_int_Select_169_o1_renamed_243 "BIU_CORE/biu_state[7]_biu_done_int_Select_169_o1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFF44444404") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__biu_done_int_Select_169_o3_renamed_244 "BIU_CORE/biu_state[7]_biu_done_int_Select_169_o3")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FEFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__biu_done_int_Select_169_o4 "BIU_CORE/biu_state[7]_biu_done_int_Select_169_o4")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFA8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0988_SW0 "BIU_CORE/_n0988_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0988_renamed_245 "BIU_CORE/_n0988")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFEEFEFFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n09781_renamed_246 "BIU_CORE/_n09781")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n09782_renamed_247 "BIU_CORE/_n09782")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<3>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___11___BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<3>1") (owner "Xilinx"))
+              (property INIT (string "00101000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_2_renamed_248 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<3>2")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_3_renamed_249 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<3>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<3>4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFEAEAEA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_2_renamed_250 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<2>2")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_3_renamed_251 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<2>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<2>4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFEAEAEA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_2_renamed_252 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<1>2")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_3_renamed_253 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<1>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<1>4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFEAEAEA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_2_renamed_254 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<0>2")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_3_renamed_255 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<0>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_4_renamed_256 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<0>4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFEAEAEA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_6_1_renamed_257 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<6>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFF80000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0910_inv_SW0 "BIU_CORE/_n0910_inv_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0910_inv_renamed_258 "BIU_CORE/_n0910_inv")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAAAAAAAAAAAA28") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__biu_done_int_Select_169_o2_SW0 "BIU_CORE/biu_state[7]_biu_done_int_Select_169_o2_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___56___BIU_CORE/biu_state[7]_biu_done_int_Select_169_o2_SW0") (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__biu_done_int_Select_169_o2_renamed_259 "BIU_CORE/biu_state[7]_biu_done_int_Select_169_o2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0008000000000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4__SW0 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<4>_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___4___BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<4>_SW0") (owner "Xilinx"))
+              (property INIT (string "7FFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_1_renamed_260 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<0>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "10107AFAFFDFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_2_renamed_261 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<0>2")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___56___BIU_CORE/biu_state[7]_biu_done_int_Select_169_o2_SW0") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_3_renamed_262 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<0>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF8F88") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_Select_161_o_SW0 "BIU_CORE/biu_state[7]_GND_10_o_Select_161_o_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___45___BIU_CORE/biu_state[7]_GND_10_o_Select_161_o_SW0") (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_Select_161_o_renamed_263 "BIU_CORE/biu_state[7]_GND_10_o_Select_161_o")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A2A2FFA2A2A2A2A2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__inta_n_int_Select_184_o_SW0 "BIU_CORE/biu_state[7]_inta_n_int_Select_184_o_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___45___BIU_CORE/biu_state[7]_GND_10_o_Select_161_o_SW0") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__inta_n_int_Select_184_o_renamed_264 "BIU_CORE/biu_state[7]_inta_n_int_Select_184_o")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFAAAA8880") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_12_SW0 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<5>12_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___11___BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<3>1") (owner "Xilinx"))
+              (property INIT (string "EAAF80AF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OE_Select_174_o_renamed_265 "BIU_CORE/biu_state[7]_AD_OE_Select_174_o")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFAAA8AA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_149_o_7__SW0 "BIU_CORE/biu_state[7]_GND_10_o_equal_149_o<7>_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___44___BIU_CORE/biu_state[7]_GND_10_o_equal_149_o<7>_SW0") (owner "Xilinx"))
+              (property INIT (string "FB") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_149_o_7__ "BIU_CORE/biu_state[7]_GND_10_o_equal_149_o<7>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000001000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_Select_163_o1112_renamed_266 "BIU_CORE/biu_state[7]_GND_10_o_Select_163_o1112")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___5___BIU_CORE/biu_state[7]_GND_10_o_equal_148_o<7>1") (owner "Xilinx"))
+              (property INIT (string "9400") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_Select_163_o1113 "BIU_CORE/biu_state[7]_GND_10_o_Select_163_o1113")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFF8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_157_o_7_1_SW0 "BIU_CORE/biu_state[7]_GND_10_o_equal_157_o<7>1_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_157_o_7_1_renamed_267 "BIU_CORE/biu_state[7]_GND_10_o_equal_157_o<7>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000080") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT3_SW0 "BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_123_OUT3_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___10___BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_123_OUT3_SW0") (owner "Xilinx"))
+              (property INIT (string "FAF8FF5F") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT3 "BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_123_OUT3")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8FFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_2_renamed_268 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<9>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000020002000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_3_renamed_269 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<9>3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0444004040000040") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_4_renamed_270 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<9>4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFF8FFF8FFF8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_5 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<9>5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFEAAAEAAAEAAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_2_renamed_271 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<8>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000020002000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_3_renamed_272 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<8>3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0444004040000040") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_4_renamed_273 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<8>4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFF8FFF8FFF8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_5 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<8>5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFEAAAEAAAEAAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_2_renamed_274 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<7>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000020002000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_3_renamed_275 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<7>3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0444004040000040") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_4_renamed_276 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<7>4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFF8FFF8FFF8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_5 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<7>5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFEAAAEAAAEAAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_2_renamed_277 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<6>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000020002000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_3_renamed_278 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<6>3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0444004040000040") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_4_renamed_279 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<6>4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFF8FFF8FFF8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_5 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<6>5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFEAAAEAAAEAAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_2_renamed_280 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<5>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000020002000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_3_renamed_281 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<5>3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0444004040000040") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_4_renamed_282 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<5>4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFF8FFF8FFF8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_5 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<5>5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFEAAAEAAAEAAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_2_renamed_283 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<4>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000020002000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_3_renamed_284 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<4>3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0444004040000040") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_4_renamed_285 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<4>4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFF8FFF8FFF8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_5 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<4>5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFEAAAEAAAEAAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_2_renamed_286 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<15>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000020002000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_3_renamed_287 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<15>3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0444004040000040") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_4_renamed_288 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<15>4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFF8FFF8FFF8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_5 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<15>5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFEAAAEAAAEAAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_2_renamed_289 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<14>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000020002000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_3_renamed_290 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<14>3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0444004040000040") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_4_renamed_291 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<14>4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFF8FFF8FFF8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_5 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<14>5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFEAAAEAAAEAAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_2_renamed_292 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<13>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000020002000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_3_renamed_293 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<13>3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0444004040000040") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_4_renamed_294 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<13>4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFF8FFF8FFF8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_5 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<13>5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFEAAAEAAAEAAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_2_renamed_295 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<12>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000020002000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_3_renamed_296 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<12>3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0444004040000040") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_4_renamed_297 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<12>4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFF8FFF8FFF8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_5 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<12>5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFEAAAEAAAEAAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_2_renamed_298 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<11>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000020002000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_3_renamed_299 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<11>3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0444004040000040") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_4_renamed_300 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<11>4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFF8FFF8FFF8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_5 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<11>5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFEAAAEAAAEAAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_2_renamed_301 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<10>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000020002000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_3_renamed_302 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<10>3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0444004040000040") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_4_renamed_303 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<10>4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFF8FFF8FFF8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_5_renamed_304 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<10>5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFEAAAEAAAEAAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT1_SW0 "BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_123_OUT1_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___10___BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_123_OUT3_SW0") (owner "Xilinx"))
+              (property INIT (string "FEFFCE8F") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT1 "BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_123_OUT1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___47___BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_123_OUT1") (owner "Xilinx"))
+              (property INIT (string "A222") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT2_SW0 "BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_123_OUT2_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___9___BIU_CORE/_n09261") (owner "Xilinx"))
+              (property INIT (string "EEBFE7BF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT2 "BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_123_OUT2")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A222") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n10042_renamed_305 "BIU_CORE/_n10042")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___6___BIU_CORE/biu_state[7]_GND_10_o_equal_152_o<7>2") (owner "Xilinx"))
+              (property INIT (string "2082") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__den_int_Select_178_o112_renamed_306 "BIU_CORE/biu_state[7]_den_int_Select_178_o112")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___7___BIU_CORE/biu_state[7]_den_int_Select_178_o112") (owner "Xilinx"))
+              (property INIT (string "0220") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__den_int_Select_178_o113 "BIU_CORE/biu_state[7]_den_int_Select_178_o113")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFE") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_1_renamed_307 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<19>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8888800080008000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_2_renamed_308 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<19>2")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFEAEAEA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<19>3")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___51___BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<19>3") (owner "Xilinx"))
+              (property INIT (string "EC") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_1_renamed_309 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<18>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8888800080008000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_2_renamed_310 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<18>2")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFEAEAEA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<18>3")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___51___BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<19>3") (owner "Xilinx"))
+              (property INIT (string "EC") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_1_renamed_311 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<17>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8888800080008000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_2_renamed_312 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<17>2")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFEAEAEA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<17>3")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___50___BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<17>3") (owner "Xilinx"))
+              (property INIT (string "EC") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_1_renamed_313 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<16>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8888800080008000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_2_renamed_314 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<16>2")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFEAEAEA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<16>3")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___50___BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<17>3") (owner "Xilinx"))
+              (property INIT (string "EC") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_0__ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<0>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_1__ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<1>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_2__ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<2>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_3__ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<3>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_4__ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<4>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_5__ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<5>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_6__ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<6>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_7__ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<7>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__den_int_Select_178_o_SW0 "BIU_CORE/biu_state[7]_den_int_Select_178_o_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1B") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__den_int_Select_178_o_renamed_315 "BIU_CORE/biu_state[7]_den_int_Select_178_o")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFAAAAAAA8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_BIU_CLK_COUNTER_ZERO_12_1_renamed_316 "BIU_CORE/BIU_CLK_COUNTER_ZERO<12>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_BIU_CLK_COUNTER_ZERO_12_2 "BIU_CORE/BIU_CLK_COUNTER_ZERO<12>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_BIU_CLK_COUNTER_ZERO_12_3 "BIU_CORE/BIU_CLK_COUNTER_ZERO<12>3")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "40") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045761_renamed_317 "EU_CORE/Mmux_n045761")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFDF5757DF8B5703") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045762 "EU_CORE/Mmux_n045762")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF405540554055") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045764 "EU_CORE/Mmux_n045764")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0880") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045721_renamed_318 "EU_CORE/Mmux_n045721")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "038B") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045722 "EU_CORE/Mmux_n045722")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BBABABAB33232303") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045724 "EU_CORE/Mmux_n045724")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0880") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457134 "EU_CORE/Mmux_n0457134")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8008") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457121_renamed_319 "EU_CORE/Mmux_n0457121")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "038B") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457122 "EU_CORE/Mmux_n0457122")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BBABABAB33232303") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT111_renamed_320 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT111")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT112 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT112")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EFEA4540") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT101_renamed_321 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT101")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT102 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT102")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EFEA4540") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT91_renamed_322 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT91")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT92 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT92")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EFEA4540") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT81_renamed_323 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT81")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT82 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT82")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EFEA4540") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT71_renamed_324 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT72 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT72")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EFEA4540") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT31_renamed_325 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT31")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E8E0C8C028200800") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT32 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT32")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1154005411100010") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT21_renamed_326 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT21")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E8E0C8C028200800") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT22 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT22")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1154005411100010") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT131_renamed_327 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT131")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E8E0C8C028200800") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT132 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT132")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1154005411100010") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045731_renamed_328 "EU_CORE/Mmux_n045731")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "50D855DD73FB77FF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045732 "EU_CORE/Mmux_n045732")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF045504550455") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045716_SW0 "EU_CORE/Mmux_n045716_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "67036F0B33673B6F") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045716_SW1 "EU_CORE/Mmux_n045716_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E783EF8BB3E7BBEF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045716_SW2 "EU_CORE/Mmux_n045716_SW2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "63076B0F37633F6B") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045716_SW3 "EU_CORE/Mmux_n045716_SW3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E387EB8FB7E3BFEB") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045716 "EU_CORE/Mmux_n045716")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F5F5A0A0DD88DD88") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045714_SW0 "EU_CORE/Mmux_n045714_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "98FC187CCC984C18") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045714_SW1 "EU_CORE/Mmux_n045714_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "90F41074C4904410") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045714_SW2 "EU_CORE/Mmux_n045714_SW2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9CF81C78C89C481C") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045714_SW3 "EU_CORE/Mmux_n045714_SW3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "94F01470C0944014") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045714 "EU_CORE/Mmux_n045714")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "272727270055AAFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457101_renamed_329 "EU_CORE/Mmux_n0457101")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___16___EU_CORE/Mmux_n0457101") (owner "Xilinx"))
+              (property INIT (string "1151") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457102_renamed_330 "EU_CORE/Mmux_n0457102")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "5073D8FB5577DDFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457103 "EU_CORE/Mmux_n0457103")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___16___EU_CORE/Mmux_n0457101") (owner "Xilinx"))
+              (property INIT (string "8338B00B") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457104 "EU_CORE/Mmux_n0457104")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FDF8") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045741 "EU_CORE/Mmux_n045741")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "08000A0888808A88") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045742_renamed_331 "EU_CORE/Mmux_n045742")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___57___EU_CORE/Mmux_n045742") (owner "Xilinx"))
+              (property INIT (string "02") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457151 "EU_CORE/Mmux_n0457151")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "08000A0888808A88") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457152_renamed_332 "EU_CORE/Mmux_n0457152")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___46___EU_CORE/Mmux_n0457152") (owner "Xilinx"))
+              (property INIT (string "02") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457111_renamed_333 "EU_CORE/Mmux_n0457111")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88808A8808000A08") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457112_renamed_334 "EU_CORE/Mmux_n0457112")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___46___EU_CORE/Mmux_n0457152") (owner "Xilinx"))
+              (property INIT (string "02") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457113 "EU_CORE/Mmux_n0457113")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFCC40FFFFCC04") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT61 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT61")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0AAAACCCCFF00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT62 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT62")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FDDD7555A8882000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT51 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT51")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00AACCF0") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT52 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT52")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FDDD7555A8882000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT121_renamed_335 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT121")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BAB832308A880200") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT122 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT122")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "5554151451501110") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT1_SW0 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT1_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT1 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CA0FC00FCA00C000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1157_0_2_SW0 "EU_CORE/_n1157<0>2_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FEBA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1157_0_2_renamed_336 "EU_CORE/_n1157<0>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000010") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_stall_pipeline_eu_jump_boolean_AND_116_o_inv_renamed_337 "EU_CORE/eu_stall_pipeline_eu_jump_boolean_AND_116_o_inv")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFFFB") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_n0072_15_1_renamed_338 "EU_CORE/n0072<15>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_n0072_15_2 "EU_CORE/n0072<15>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_n0072_15_3 "EU_CORE/n0072<15>3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0001000000000000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_parity_SW0 "EU_CORE/eu_parity_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "69") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_parity_renamed_339 "EU_CORE/eu_parity")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6996966996696996") (owner "Xilinx"))
+            )
+            (instance (rename CLK_IBUF_renamed_340 "CLK_IBUF")
+              (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename RESET_IBUF_renamed_341 "RESET_IBUF")
+              (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename READY_IBUF_renamed_342 "READY_IBUF")
+              (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename INTR_IBUF_renamed_343 "INTR_IBUF")
+              (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename NMI_IBUF_renamed_344 "NMI_IBUF")
+              (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_D_7_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_D_6_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_D_5_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_D_4_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_D_3_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_D_2_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_D_1_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_D_0_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance AD7_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance AD6_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance AD5_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance AD4_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance AD3_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance AD2_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance AD1_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance AD0_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_18_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_17_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_16_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_15_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_14_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_13_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_12_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_11_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_10_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_9_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_8_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_7_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_6_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_5_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_4_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_3_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_2_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_1_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_0_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance LED_7_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance LED_6_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance LED_5_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance LED_4_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance LED_3_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance LED_2_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance LED_1_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance LED_0_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A19_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A18_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A17_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A16_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A15_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A14_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A13_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A12_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A11_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A10_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A9_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A8_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance ALE_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance INTA_n_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance RD_n_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance WR_n_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance IOM_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance DTR_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance DEN_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SSO_n_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_CE_n_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_OE_n_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_WE_n_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance BUF1_OE_n_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance BUF2_OE_n_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance BUF2_DIR_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_biu_req_caught_renamed_345 "BIU_CORE/eu_biu_req_caught")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_nmi_caught_renamed_346 "BIU_CORE/nmi_caught")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_tr_latched_renamed_347 "EU_CORE/eu_tr_latched")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_biu_done_caught_renamed_348 "EU_CORE/biu_done_caught")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_14__rt_renamed_349 "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<14>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_13__rt_renamed_350 "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<13>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_12__rt_renamed_351 "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<12>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_11__rt_renamed_352 "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<11>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_10__rt_renamed_353 "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<10>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_9__rt_renamed_354 "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<9>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_8__rt_renamed_355 "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<8>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_7__rt_renamed_356 "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<7>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_6__rt_renamed_357 "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<6>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_5__rt_renamed_358 "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<5>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_4__rt_renamed_359 "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<4>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_3__rt_renamed_360 "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<3>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_2__rt_renamed_361 "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<2>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_1__rt_renamed_362 "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_18__rt_renamed_363 "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<18>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_17__rt_renamed_364 "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<17>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_16__rt_renamed_365 "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<16>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_18__rt_renamed_366 "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<18>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_17__rt_renamed_367 "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<17>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_16__rt_renamed_368 "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<16>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_18__rt_renamed_369 "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<18>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_17__rt_renamed_370 "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<17>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_16__rt_renamed_371 "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<16>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_15__rt_renamed_372 "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_xor<15>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_19__rt_renamed_373 "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_xor<19>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_19__rt_renamed_374 "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_xor<19>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_19__rt_renamed_375 "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_xor<19>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_BIU_INTR_renamed_376 "BIU_CORE/BIU_INTR")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename t_reset_d4_renamed_377 "t_reset_d4")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_word_cycle_renamed_378 "BIU_CORE/word_cycle")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_intr_enable_delayed_renamed_379 "EU_CORE/intr_enable_delayed")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1 "EU_CORE/carry<5>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DD4D4D44") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045771_SW1 "EU_CORE/Mmux_n045771_SW1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "C99F") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_13_1_SW0 "EU_CORE/carry<13>1_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF5577117F155701") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_13_1_SW1 "EU_CORE/carry<13>1_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "80EAA8FE88EEAAFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux23_4_renamed_380 "EU_CORE/mux23_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF55550FFF3333") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045733_SW0 "EU_CORE/Mmux_n045733_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045734 "EU_CORE/Mmux_n045734")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF0540FFFF0045") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045763_SW0 "EU_CORE/Mmux_n045763_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FBAEAEFB") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045763_SW1 "EU_CORE/Mmux_n045763_SW1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BAEFEFBA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_11_1_SW0 "EU_CORE/carry<11>1_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8EAF0A8E0A8E0A8E") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_11_1_SW1 "EU_CORE/carry<11>1_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8EAF8EAF8EAF0A8E") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_7_1_SW0 "EU_CORE/carry<7>1_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00AAA0FA80EAA8FE") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_7_1_SW1 "EU_CORE/carry<7>1_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "80EAA8FEA0FAAAFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457411_SW0 "EU_CORE/Mmux_n0457411_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AFAFFAFABEAFEBFA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457411_SW1 "EU_CORE/Mmux_n0457411_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BEAFEBFABEBEEBEB") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045743 "EU_CORE/Mmux_n045743")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "ECEEECEEECECEEEE") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_9_1_SW0 "EU_CORE/carry<9>1_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FBB0F220") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_9_1_SW1 "EU_CORE/carry<9>1_SW1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FBB0F220") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_11_1 "EU_CORE/carry<11>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FEF81070") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW0 "EU_CORE/carry<15>1_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FAE8") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW1 "EU_CORE/carry<15>1_SW1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E8A0") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_16_1 "EU_CORE/carry<16>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F3C0FA50") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW2 "EU_CORE/carry<15>1_SW2")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FADB") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW3 "EU_CORE/carry<15>1_SW3")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DB5F") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mxor_carry_16__carry_15__XOR_141_o_xo_0_1 "EU_CORE/Mxor_carry[16]_carry[15]_XOR_141_o_xo<0>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0C3F05AF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045772 "EU_CORE/Mmux_n045772")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "77227272") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5__ "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<5>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "55555554DDDDDDDC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457123_SW0 "EU_CORE/Mmux_n0457123_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457124 "EU_CORE/Mmux_n0457124")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF0540FFFF0045") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_31 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<10>31")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFF8A02FFFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n04571111 "EU_CORE/Mmux_n04571111")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___17___EU_CORE/carry<4>1") (owner "Xilinx"))
+              (property INIT (string "9C99CC9C") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045723_SW0 "EU_CORE/Mmux_n045723_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FBAEAEFB") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045723_SW1 "EU_CORE/Mmux_n045723_SW1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BAEFEFBA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045725 "EU_CORE/Mmux_n045725")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F4F4F5F5F4F5F4F5") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n04571511_SW0 "EU_CORE/Mmux_n04571511_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AFAFFAFABEAFEBFA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n04571511_SW1 "EU_CORE/Mmux_n04571511_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BEAFEBFABEBEEBEB") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457153 "EU_CORE/Mmux_n0457153")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F8FAF8FAF8F8FAFA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045754 "EU_CORE/Mmux_n045754")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0FBF4FFF0F2FDFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_13_1_SW4 "EU_CORE/carry<13>1_SW4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFD2002DF0000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_13_1_SW5 "EU_CORE/carry<13>1_SW5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFB4004BF0000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045765 "EU_CORE/Mmux_n045765")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F4F4F5F4F4F5F5F5") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_7_1 "EU_CORE/carry<7>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW4 "EU_CORE/carry<5>1_SW4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCEEECFE008880C8") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW5 "EU_CORE/carry<5>1_SW5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "ECFEEEFF80C888CC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_9_1 "EU_CORE/carry<9>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0E4D8CC") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n09783_SW0 "BIU_CORE/_n09783_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___47___BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_123_OUT1") (owner "Xilinx"))
+              (property INIT (string "D1") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_21 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<0>21")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFECFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW1 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<4>1_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFEAAAEAAAEAAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_6_2 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<6>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAFEFEAAFEAAFEAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW2 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<4>1_SW2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0111111105555555") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4__ "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<4>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF82C382C382C3") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457135_SW0 "EU_CORE/Mmux_n0457135_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EBBEBBEE") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457135_SW1 "EU_CORE/Mmux_n0457135_SW1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EEBBEBBE") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457136 "EU_CORE/Mmux_n0457136")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF4545FFFF4455") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_out21 "BIU_CORE/out21")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFEEFE") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_equal_150_o_7_2_SW0 "BIU_CORE/biu_state[7]_GND_10_o_equal_150_o<7>2_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FB") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_Select_163_o1111_renamed_381 "BIU_CORE/biu_state[7]_GND_10_o_Select_163_o1111")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "41F1414100F00000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW0 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<1>21_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___44___BIU_CORE/biu_state[7]_GND_10_o_equal_149_o<7>_SW0") (owner "Xilinx"))
+              (property INIT (string "9333") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_7_1 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<7>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "5555555555545454") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW1 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<1>21_SW1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___4___BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<4>_SW0") (owner "Xilinx"))
+              (property INIT (string "9333") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_3_1 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<3>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "5555555555545454") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW2 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<1>21_SW2")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFEA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_2_1 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<2>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAFEFEAAFEAAFEAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_1 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<1>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFF66666660") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045751_SW0 "EU_CORE/Mmux_n045751_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "71") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045752 "EU_CORE/Mmux_n045752")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "D9115111FB337333") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_13_1_SW2 "EU_CORE/carry<13>1_SW2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BFFAFABFBAFFFFBA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_13_1_SW3 "EU_CORE/carry<13>1_SW3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BFFAFABFBAFFFFBA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457133_SW0 "EU_CORE/Mmux_n0457133_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8E") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457133_renamed_382 "EU_CORE/Mmux_n0457133")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "3BBB33B30B8B0383") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_lut_3__ "EU_CORE/Mcount_eu_rom_address_lut<3>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F3C0AAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_lut_4__ "EU_CORE/Mcount_eu_rom_address_lut<4>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F3C0AAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_lut_5__ "EU_CORE/Mcount_eu_rom_address_lut<5>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F3C0AAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_lut_6__ "EU_CORE/Mcount_eu_rom_address_lut<6>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F3C0AAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_lut_7__ "EU_CORE/Mcount_eu_rom_address_lut<7>")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F3C0AAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_lut_8__ "EU_CORE/Mcount_eu_rom_address_lut<8>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FCAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_lut_9__ "EU_CORE/Mcount_eu_rom_address_lut<9>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FCAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_lut_10__ "EU_CORE/Mcount_eu_rom_address_lut<10>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FCAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mcount_eu_rom_address_lut_11__ "EU_CORE/Mcount_eu_rom_address_lut<11>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FCAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_8_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<8>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EEAAECA0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_9_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<9>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EEAAECA0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_10_2 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<10>2")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EEAAECA0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_11_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<11>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EEAAECA0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_12_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<12>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EEAAECA0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_13_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<13>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EEAAECA0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_14_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<14>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EEAAECA0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_15_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<15>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EEAAECA0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_16_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<16>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EECCEAC0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_17_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<17>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EECCEAC0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_18_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<18>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EECCEAC0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_19_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<19>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EECCEAC0") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_system_signals_7_1 "EU_CORE/system_signals<7>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6FFFF6FFFF6FFFF6") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW1 "EU_CORE/carry<5>1_SW1")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW1_F "EU_CORE/carry<5>1_SW1_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000CCEE0000ECFE") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW1_G "EU_CORE/carry<5>1_SW1_G")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCEEFFFFECFEFFFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW2 "EU_CORE/carry<5>1_SW2")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW2_F "EU_CORE/carry<5>1_SW2_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "000080C8000088CC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW2_G "EU_CORE/carry<5>1_SW2_G")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "80C8FFFF88CCFFFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW3 "EU_CORE/carry<5>1_SW3")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW3_F "EU_CORE/carry<5>1_SW3_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000ECFE0000EEFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW3_G "EU_CORE/carry<5>1_SW3_G")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "ECFEFFFFEEFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n04571_SW4 "EU_CORE/Mmux_n04571_SW4")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___57___EU_CORE/Mmux_n045742") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n04571 "EU_CORE/Mmux_n04571")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "64003064EC88B8EC") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_word_cycle_rstpot1_renamed_383 "BIU_CORE/word_cycle_rstpot1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "54101010") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_intr_enable_delayed_rstpot1_renamed_384 "EU_CORE/intr_enable_delayed_rstpot1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___58___EU_CORE/intr_asserted1") (owner "Xilinx"))
+              (property INIT (string "2220") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_biu_req_caught_glue_set_renamed_385 "BIU_CORE/eu_biu_req_caught_glue_set")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "22F2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_nmi_caught_glue_set_renamed_386 "BIU_CORE/nmi_caught_glue_set")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00800080FFFF0080") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_tr_latched_glue_set_renamed_387 "EU_CORE/eu_tr_latched_glue_set")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "22F2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n10044_SW0 "BIU_CORE/_n10044_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFEFFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n10044 "BIU_CORE/_n10044")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFF8220") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0867_inv1 "BIU_CORE/_n0867_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFDDFFFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_Select_163_o112_SW0 "BIU_CORE/biu_state[7]_GND_10_o_Select_163_o112_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "02") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0929_0_11 "BIU_CORE/_n0929<0>11")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___15___BIU_CORE/eu_biu_req_code[4]_INV_26_o1") (owner "Xilinx"))
+              (property INIT (string "15734444") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_full_GND_10_o_equal_118_o1 "BIU_CORE/pfq_full_GND_10_o_equal_118_o1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF6FF66FF6FFFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_12_renamed_388 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<5>12")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000080") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_1_renamed_389 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<9>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8888F88888888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_1_renamed_390 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<8>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8888F88888888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_1_renamed_391 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<7>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8888F88888888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_1_renamed_392 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<15>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8888F88888888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_1_renamed_393 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<14>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8888F88888888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_1_renamed_394 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<13>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8888F88888888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_1_renamed_395 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<12>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8888F88888888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_1_renamed_396 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<11>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8888F88888888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_1_renamed_397 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<10>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8888F88888888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW0 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<4>1_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888898") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_empty1 "BIU_CORE/pfq_empty1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0897_inv1 "BIU_CORE/_n0897_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___7___BIU_CORE/biu_state[7]_den_int_Select_178_o112") (owner "Xilinx"))
+              (property INIT (string "04000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_s_bits_2__word_cycle_AND_33_o1 "BIU_CORE/s_bits[2]_word_cycle_AND_33_o1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888880") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_0__SW0 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<0>_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EA2A") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_1__SW0 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<1>_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EA2A") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_2__SW0 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<2>_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EA2A") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_3__SW0 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<3>_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EA2A") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_4__SW0 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<4>_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EA2A") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_5__SW0 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<5>_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EA2A") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_6__SW0 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<6>_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EA2A") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_7__SW0 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<7>_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___48___BIU_CORE/word_cycle_byte_num_AND_34_o1") (owner "Xilinx"))
+              (property INIT (string "EA2A") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5__SW0_SW0 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<5>_SW0_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9555555555555555") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_0__ "BIU_CORE/Mcount_clock_cycle_counter_lut<0>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4575") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_1__ "BIU_CORE/Mcount_clock_cycle_counter_lut<1>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4575") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_2__ "BIU_CORE/Mcount_clock_cycle_counter_lut<2>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4575") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_3__ "BIU_CORE/Mcount_clock_cycle_counter_lut<3>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4575") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_4__ "BIU_CORE/Mcount_clock_cycle_counter_lut<4>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4575") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_5__ "BIU_CORE/Mcount_clock_cycle_counter_lut<5>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4575") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_11_o_inv1 "BIU_CORE/eu_biu_req_caught_eu_biu_req_code[4]_AND_11_o_inv1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FDFFFFFFFFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_6__ "BIU_CORE/Mcount_clock_cycle_counter_lut<6>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4575") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_7__ "BIU_CORE/Mcount_clock_cycle_counter_lut<7>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4575") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_8__ "BIU_CORE/Mcount_clock_cycle_counter_lut<8>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4575") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_9__ "BIU_CORE/Mcount_clock_cycle_counter_lut<9>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4575") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_10__ "BIU_CORE/Mcount_clock_cycle_counter_lut<10>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4575") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_11__ "BIU_CORE/Mcount_clock_cycle_counter_lut<11>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4575") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_12__ "BIU_CORE/Mcount_clock_cycle_counter_lut<12>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4575") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_BIU_INTR_rstpot_renamed_398 "BIU_CORE/BIU_INTR_rstpot")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___42___BIU_CORE/clk_d4_clk_d2_AND_30_o1") (owner "Xilinx"))
+              (property INIT (string "ABAAA8AA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_1_renamed_399 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<6>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8888F88888888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_1_renamed_400 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<5>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8888F88888888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_1_renamed_401 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<4>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8888F88888888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_4 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<0>4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF5540") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OE_Select_174_o_SW0 "BIU_CORE/biu_state[7]_AD_OE_Select_174_o_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFF8000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW3 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<1>21_SW3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAAAAAEAAAAAAAA") (owner "Xilinx"))
+            )
+            (instance (rename t_reset_d4_rstpot_renamed_402 "t_reset_d4_rstpot")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_biu_done_caught_glue_set_renamed_403 "EU_CORE/biu_done_caught_glue_set")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A2A2FFA2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT21 "BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT21")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8080808080808000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT31 "BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT31")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8080808080808000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT41 "BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT41")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8080808080808000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT51 "BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8080808080808000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT61 "BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT61")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8080808080808000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT71 "BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8080808080808000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT151 "BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT151")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8080808080808000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT161 "BIU_CORE/Mmux_GND_10_o_latched_data_in[7]_mux_139_OUT161")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8080808080808000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_21 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<10>21")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000001000000") (owner "Xilinx"))
+            )
+            (instance (rename CORE_CLK_BUFGP_renamed_404 "CORE_CLK_BUFGP")
+              (viewRef view_1 (cellRef BUFGP (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_lut_0__INV_0 "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_lut<0>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance BUF2_DIR_inv1_INV_0
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_RESET_INT_inv1_INV_0 "BIU_CORE/RESET_INT_inv1_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_s_bits_2__INV_27_o1_INV_0 "BIU_CORE/s_bits[2]_INV_27_o1_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045783 "EU_CORE/Mmux_n045783")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045783_F "EU_CORE/Mmux_n045783_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EF1010EF55FF5555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045783_G "EU_CORE/Mmux_n045783_G")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "5515DD9D7737FFBF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT43 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT43")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT43_F "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT43_F")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD64B920") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT43_G "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT43_G")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045793 "EU_CORE/Mmux_n045793")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045793_F "EU_CORE/Mmux_n045793_F")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "C3965D5D") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045793_G "EU_CORE/Mmux_n045793_G")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "51FFFBFF5155FB55") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW4 "EU_CORE/carry<15>1_SW4")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW4_F "EU_CORE/carry<15>1_SW4_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "D7D77DD77DD77D7D") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW4_G "EU_CORE/carry<15>1_SW4_G")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "7") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW0 "EU_CORE/carry<5>1_SW0")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW0_F "EU_CORE/carry<5>1_SW0_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFF08088A08") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW0_G "EU_CORE/carry<5>1_SW0_G")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000800080808880") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW5 "EU_CORE/carry<15>1_SW5")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW5_F "EU_CORE/carry<15>1_SW5_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "D7D7D77DD77D7D7D") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW5_G "EU_CORE/carry<15>1_SW5_G")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "7") (owner "Xilinx"))
+            )
+            (instance (rename Mshreg_t_biu_ad_oe_d2_renamed_405 "Mshreg_t_biu_ad_oe_d2")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename t_biu_ad_oe_d2_renamed_406 "t_biu_ad_oe_d2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mshreg_t_reset_d2_renamed_407 "Mshreg_t_reset_d2")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename t_reset_d2_renamed_408 "t_reset_d2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_15_renamed_409 "BIU_CORE/Mshreg_biu_return_data_int_d2_15")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_15 "BIU_CORE/biu_return_data_int_d2_15")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_14_renamed_410 "BIU_CORE/Mshreg_biu_return_data_int_d2_14")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_14 "BIU_CORE/biu_return_data_int_d2_14")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_13_renamed_411 "BIU_CORE/Mshreg_biu_return_data_int_d2_13")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_13 "BIU_CORE/biu_return_data_int_d2_13")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_12_renamed_412 "BIU_CORE/Mshreg_biu_return_data_int_d2_12")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_12 "BIU_CORE/biu_return_data_int_d2_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_11_renamed_413 "BIU_CORE/Mshreg_biu_return_data_int_d2_11")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_11 "BIU_CORE/biu_return_data_int_d2_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_10_renamed_414 "BIU_CORE/Mshreg_biu_return_data_int_d2_10")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_10 "BIU_CORE/biu_return_data_int_d2_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_9_renamed_415 "BIU_CORE/Mshreg_biu_return_data_int_d2_9")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_9 "BIU_CORE/biu_return_data_int_d2_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_8_renamed_416 "BIU_CORE/Mshreg_biu_return_data_int_d2_8")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_8 "BIU_CORE/biu_return_data_int_d2_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_7_renamed_417 "BIU_CORE/Mshreg_biu_return_data_int_d2_7")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_7 "BIU_CORE/biu_return_data_int_d2_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_6_renamed_418 "BIU_CORE/Mshreg_biu_return_data_int_d2_6")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_6 "BIU_CORE/biu_return_data_int_d2_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_3_renamed_419 "BIU_CORE/Mshreg_biu_return_data_int_d2_3")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_3 "BIU_CORE/biu_return_data_int_d2_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_5_renamed_420 "BIU_CORE/Mshreg_biu_return_data_int_d2_5")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_5 "BIU_CORE/biu_return_data_int_d2_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_4_renamed_421 "BIU_CORE/Mshreg_biu_return_data_int_d2_4")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_4 "BIU_CORE/biu_return_data_int_d2_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_2_renamed_422 "BIU_CORE/Mshreg_biu_return_data_int_d2_2")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_2 "BIU_CORE/biu_return_data_int_d2_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_1_renamed_423 "BIU_CORE/Mshreg_biu_return_data_int_d2_1")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_1 "BIU_CORE/biu_return_data_int_d2_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_0_renamed_424 "BIU_CORE/Mshreg_biu_return_data_int_d2_0")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_0 "BIU_CORE/biu_return_data_int_d2_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_15_renamed_425 "BIU_CORE/Mshreg_biu_register_rm_d2_15")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_15 "BIU_CORE/biu_register_rm_d2_15")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_12_renamed_426 "BIU_CORE/Mshreg_biu_register_rm_d2_12")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_12 "BIU_CORE/biu_register_rm_d2_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_14_renamed_427 "BIU_CORE/Mshreg_biu_register_rm_d2_14")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_14 "BIU_CORE/biu_register_rm_d2_14")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_13_renamed_428 "BIU_CORE/Mshreg_biu_register_rm_d2_13")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_13 "BIU_CORE/biu_register_rm_d2_13")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_11_renamed_429 "BIU_CORE/Mshreg_biu_register_rm_d2_11")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_11 "BIU_CORE/biu_register_rm_d2_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_10_renamed_430 "BIU_CORE/Mshreg_biu_register_rm_d2_10")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_10 "BIU_CORE/biu_register_rm_d2_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_9_renamed_431 "BIU_CORE/Mshreg_biu_register_rm_d2_9")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_9 "BIU_CORE/biu_register_rm_d2_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_8_renamed_432 "BIU_CORE/Mshreg_biu_register_rm_d2_8")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_8 "BIU_CORE/biu_register_rm_d2_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_5_renamed_433 "BIU_CORE/Mshreg_biu_register_rm_d2_5")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_5 "BIU_CORE/biu_register_rm_d2_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_7_renamed_434 "BIU_CORE/Mshreg_biu_register_rm_d2_7")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_7 "BIU_CORE/biu_register_rm_d2_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_6_renamed_435 "BIU_CORE/Mshreg_biu_register_rm_d2_6")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_6 "BIU_CORE/biu_register_rm_d2_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_4_renamed_436 "BIU_CORE/Mshreg_biu_register_rm_d2_4")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_4 "BIU_CORE/biu_register_rm_d2_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_3_renamed_437 "BIU_CORE/Mshreg_biu_register_rm_d2_3")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_3 "BIU_CORE/biu_register_rm_d2_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_2_renamed_438 "BIU_CORE/Mshreg_biu_register_rm_d2_2")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_2 "BIU_CORE/biu_register_rm_d2_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_1_renamed_439 "BIU_CORE/Mshreg_biu_register_rm_d2_1")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_1 "BIU_CORE/biu_register_rm_d2_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_14_renamed_440 "BIU_CORE/Mshreg_biu_register_ds_d2_14")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_14 "BIU_CORE/biu_register_ds_d2_14")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_0_renamed_441 "BIU_CORE/Mshreg_biu_register_rm_d2_0")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_0 "BIU_CORE/biu_register_rm_d2_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_15_renamed_442 "BIU_CORE/Mshreg_biu_register_ds_d2_15")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_15 "BIU_CORE/biu_register_ds_d2_15")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_13_renamed_443 "BIU_CORE/Mshreg_biu_register_ds_d2_13")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_13 "BIU_CORE/biu_register_ds_d2_13")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_12_renamed_444 "BIU_CORE/Mshreg_biu_register_ds_d2_12")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_12 "BIU_CORE/biu_register_ds_d2_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_11_renamed_445 "BIU_CORE/Mshreg_biu_register_ds_d2_11")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_11 "BIU_CORE/biu_register_ds_d2_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_10_renamed_446 "BIU_CORE/Mshreg_biu_register_ds_d2_10")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_10 "BIU_CORE/biu_register_ds_d2_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_7_renamed_447 "BIU_CORE/Mshreg_biu_register_ds_d2_7")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_7 "BIU_CORE/biu_register_ds_d2_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_9_renamed_448 "BIU_CORE/Mshreg_biu_register_ds_d2_9")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_9 "BIU_CORE/biu_register_ds_d2_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_8_renamed_449 "BIU_CORE/Mshreg_biu_register_ds_d2_8")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_8 "BIU_CORE/biu_register_ds_d2_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_6_renamed_450 "BIU_CORE/Mshreg_biu_register_ds_d2_6")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_6 "BIU_CORE/biu_register_ds_d2_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_5_renamed_451 "BIU_CORE/Mshreg_biu_register_ds_d2_5")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_5 "BIU_CORE/biu_register_ds_d2_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_4_renamed_452 "BIU_CORE/Mshreg_biu_register_ds_d2_4")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_4 "BIU_CORE/biu_register_ds_d2_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_3_renamed_453 "BIU_CORE/Mshreg_biu_register_ds_d2_3")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_3 "BIU_CORE/biu_register_ds_d2_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_0_renamed_454 "BIU_CORE/Mshreg_biu_register_ds_d2_0")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_0 "BIU_CORE/biu_register_ds_d2_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_2_renamed_455 "BIU_CORE/Mshreg_biu_register_ds_d2_2")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_2 "BIU_CORE/biu_register_ds_d2_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_1_renamed_456 "BIU_CORE/Mshreg_biu_register_ds_d2_1")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_1 "BIU_CORE/biu_register_ds_d2_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_15_renamed_457 "BIU_CORE/Mshreg_biu_register_reg_d2_15")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_15 "BIU_CORE/biu_register_reg_d2_15")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_14_renamed_458 "BIU_CORE/Mshreg_biu_register_reg_d2_14")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_14 "BIU_CORE/biu_register_reg_d2_14")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_13_renamed_459 "BIU_CORE/Mshreg_biu_register_reg_d2_13")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_13 "BIU_CORE/biu_register_reg_d2_13")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_12_renamed_460 "BIU_CORE/Mshreg_biu_register_reg_d2_12")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_12 "BIU_CORE/biu_register_reg_d2_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_9_renamed_461 "BIU_CORE/Mshreg_biu_register_reg_d2_9")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_9 "BIU_CORE/biu_register_reg_d2_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_11_renamed_462 "BIU_CORE/Mshreg_biu_register_reg_d2_11")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_11 "BIU_CORE/biu_register_reg_d2_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_10_renamed_463 "BIU_CORE/Mshreg_biu_register_reg_d2_10")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_10 "BIU_CORE/biu_register_reg_d2_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_8_renamed_464 "BIU_CORE/Mshreg_biu_register_reg_d2_8")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_8 "BIU_CORE/biu_register_reg_d2_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_7_renamed_465 "BIU_CORE/Mshreg_biu_register_reg_d2_7")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_7 "BIU_CORE/biu_register_reg_d2_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_6_renamed_466 "BIU_CORE/Mshreg_biu_register_reg_d2_6")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_6 "BIU_CORE/biu_register_reg_d2_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_5_renamed_467 "BIU_CORE/Mshreg_biu_register_reg_d2_5")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_5 "BIU_CORE/biu_register_reg_d2_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_4_renamed_468 "BIU_CORE/Mshreg_biu_register_reg_d2_4")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_4 "BIU_CORE/biu_register_reg_d2_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_3_renamed_469 "BIU_CORE/Mshreg_biu_register_reg_d2_3")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_3 "BIU_CORE/biu_register_reg_d2_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_2_renamed_470 "BIU_CORE/Mshreg_biu_register_reg_d2_2")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_2 "BIU_CORE/biu_register_reg_d2_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_1_renamed_471 "BIU_CORE/Mshreg_biu_register_reg_d2_1")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_1 "BIU_CORE/biu_register_reg_d2_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_0_renamed_472 "BIU_CORE/Mshreg_biu_register_reg_d2_0")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_0 "BIU_CORE/biu_register_reg_d2_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_15_renamed_473 "BIU_CORE/Mshreg_biu_register_ss_d2_15")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_15 "BIU_CORE/biu_register_ss_d2_15")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_14_renamed_474 "BIU_CORE/Mshreg_biu_register_ss_d2_14")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_14 "BIU_CORE/biu_register_ss_d2_14")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_13_renamed_475 "BIU_CORE/Mshreg_biu_register_ss_d2_13")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_13 "BIU_CORE/biu_register_ss_d2_13")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_10_renamed_476 "BIU_CORE/Mshreg_biu_register_ss_d2_10")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_10 "BIU_CORE/biu_register_ss_d2_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_12_renamed_477 "BIU_CORE/Mshreg_biu_register_ss_d2_12")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_12 "BIU_CORE/biu_register_ss_d2_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_11_renamed_478 "BIU_CORE/Mshreg_biu_register_ss_d2_11")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_11 "BIU_CORE/biu_register_ss_d2_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_9_renamed_479 "BIU_CORE/Mshreg_biu_register_ss_d2_9")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_9 "BIU_CORE/biu_register_ss_d2_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_8_renamed_480 "BIU_CORE/Mshreg_biu_register_ss_d2_8")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_8 "BIU_CORE/biu_register_ss_d2_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_7_renamed_481 "BIU_CORE/Mshreg_biu_register_ss_d2_7")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_7 "BIU_CORE/biu_register_ss_d2_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_6_renamed_482 "BIU_CORE/Mshreg_biu_register_ss_d2_6")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_6 "BIU_CORE/biu_register_ss_d2_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_3_renamed_483 "BIU_CORE/Mshreg_biu_register_ss_d2_3")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_3 "BIU_CORE/biu_register_ss_d2_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_5_renamed_484 "BIU_CORE/Mshreg_biu_register_ss_d2_5")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_5 "BIU_CORE/biu_register_ss_d2_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_4_renamed_485 "BIU_CORE/Mshreg_biu_register_ss_d2_4")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_4 "BIU_CORE/biu_register_ss_d2_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_2_renamed_486 "BIU_CORE/Mshreg_biu_register_ss_d2_2")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_2 "BIU_CORE/biu_register_ss_d2_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_1_renamed_487 "BIU_CORE/Mshreg_biu_register_ss_d2_1")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_1 "BIU_CORE/biu_register_ss_d2_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_0_renamed_488 "BIU_CORE/Mshreg_biu_register_ss_d2_0")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_0 "BIU_CORE/biu_register_ss_d2_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_15_renamed_489 "BIU_CORE/Mshreg_biu_register_es_d2_15")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_15 "BIU_CORE/biu_register_es_d2_15")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_12_renamed_490 "BIU_CORE/Mshreg_biu_register_es_d2_12")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_12 "BIU_CORE/biu_register_es_d2_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_14_renamed_491 "BIU_CORE/Mshreg_biu_register_es_d2_14")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_14 "BIU_CORE/biu_register_es_d2_14")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_13_renamed_492 "BIU_CORE/Mshreg_biu_register_es_d2_13")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_13 "BIU_CORE/biu_register_es_d2_13")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_11_renamed_493 "BIU_CORE/Mshreg_biu_register_es_d2_11")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_11 "BIU_CORE/biu_register_es_d2_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_10_renamed_494 "BIU_CORE/Mshreg_biu_register_es_d2_10")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_10 "BIU_CORE/biu_register_es_d2_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_9_renamed_495 "BIU_CORE/Mshreg_biu_register_es_d2_9")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_9 "BIU_CORE/biu_register_es_d2_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_8_renamed_496 "BIU_CORE/Mshreg_biu_register_es_d2_8")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_8 "BIU_CORE/biu_register_es_d2_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_5_renamed_497 "BIU_CORE/Mshreg_biu_register_es_d2_5")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_5 "BIU_CORE/biu_register_es_d2_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_7_renamed_498 "BIU_CORE/Mshreg_biu_register_es_d2_7")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_7 "BIU_CORE/biu_register_es_d2_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_6_renamed_499 "BIU_CORE/Mshreg_biu_register_es_d2_6")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_6 "BIU_CORE/biu_register_es_d2_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_4_renamed_500 "BIU_CORE/Mshreg_biu_register_es_d2_4")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_4 "BIU_CORE/biu_register_es_d2_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_3_renamed_501 "BIU_CORE/Mshreg_biu_register_es_d2_3")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_3 "BIU_CORE/biu_register_es_d2_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_2_renamed_502 "BIU_CORE/Mshreg_biu_register_es_d2_2")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_2 "BIU_CORE/biu_register_es_d2_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_1_renamed_503 "BIU_CORE/Mshreg_biu_register_es_d2_1")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_1 "BIU_CORE/biu_register_es_d2_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_14_renamed_504 "BIU_CORE/Mshreg_biu_register_cs_d2_14")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_14 "BIU_CORE/biu_register_cs_d2_14")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_0_renamed_505 "BIU_CORE/Mshreg_biu_register_es_d2_0")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_0 "BIU_CORE/biu_register_es_d2_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_15_renamed_506 "BIU_CORE/Mshreg_biu_register_cs_d2_15")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_15 "BIU_CORE/biu_register_cs_d2_15")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_13_renamed_507 "BIU_CORE/Mshreg_biu_register_cs_d2_13")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_13 "BIU_CORE/biu_register_cs_d2_13")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_12_renamed_508 "BIU_CORE/Mshreg_biu_register_cs_d2_12")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_12 "BIU_CORE/biu_register_cs_d2_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_11_renamed_509 "BIU_CORE/Mshreg_biu_register_cs_d2_11")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_11 "BIU_CORE/biu_register_cs_d2_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_10_renamed_510 "BIU_CORE/Mshreg_biu_register_cs_d2_10")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_10 "BIU_CORE/biu_register_cs_d2_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_7_renamed_511 "BIU_CORE/Mshreg_biu_register_cs_d2_7")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_7 "BIU_CORE/biu_register_cs_d2_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_9_renamed_512 "BIU_CORE/Mshreg_biu_register_cs_d2_9")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_9 "BIU_CORE/biu_register_cs_d2_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_8_renamed_513 "BIU_CORE/Mshreg_biu_register_cs_d2_8")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_8 "BIU_CORE/biu_register_cs_d2_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_6_renamed_514 "BIU_CORE/Mshreg_biu_register_cs_d2_6")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_6 "BIU_CORE/biu_register_cs_d2_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_5_renamed_515 "BIU_CORE/Mshreg_biu_register_cs_d2_5")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_5 "BIU_CORE/biu_register_cs_d2_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_4_renamed_516 "BIU_CORE/Mshreg_biu_register_cs_d2_4")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_4 "BIU_CORE/biu_register_cs_d2_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_3_renamed_517 "BIU_CORE/Mshreg_biu_register_cs_d2_3")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_3 "BIU_CORE/biu_register_cs_d2_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_0_renamed_518 "BIU_CORE/Mshreg_biu_register_cs_d2_0")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_0 "BIU_CORE/biu_register_cs_d2_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_2_renamed_519 "BIU_CORE/Mshreg_biu_register_cs_d2_2")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_2 "BIU_CORE/biu_register_cs_d2_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_1_renamed_520 "BIU_CORE/Mshreg_biu_register_cs_d2_1")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_1 "BIU_CORE/biu_register_cs_d2_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_EU4Kx32_i "EU_CORE/EU4Kx32_i")
+              (viewRef view_1 (cellRef EU4Kx32 (libraryRef MCL86jr_lib)))
+              (property BUS_INFO (string "12:INPUT:addra<11:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:douta<31:0>") (owner "Xilinx"))
+            )
+            (net CORE_CLK_BUFGP
+              (joined
+                (portRef C (instanceRef t_biu_ad_out_d_0))
+                (portRef C (instanceRef t_biu_ad_out_d_1))
+                (portRef C (instanceRef t_biu_ad_out_d_2))
+                (portRef C (instanceRef t_biu_ad_out_d_3))
+                (portRef C (instanceRef t_biu_ad_out_d_4))
+                (portRef C (instanceRef t_biu_ad_out_d_5))
+                (portRef C (instanceRef t_biu_ad_out_d_6))
+                (portRef C (instanceRef t_biu_ad_out_d_7))
+                (portRef C (instanceRef t_biu_ad_out_d_8))
+                (portRef C (instanceRef t_biu_ad_out_d_9))
+                (portRef C (instanceRef t_biu_ad_out_d_10))
+                (portRef C (instanceRef t_biu_ad_out_d_11))
+                (portRef C (instanceRef t_biu_ad_out_d_12))
+                (portRef C (instanceRef t_biu_ad_out_d_13))
+                (portRef C (instanceRef t_biu_ad_out_d_14))
+                (portRef C (instanceRef t_biu_ad_out_d_15))
+                (portRef C (instanceRef t_biu_ad_out_d_16))
+                (portRef C (instanceRef t_biu_ad_out_d_17))
+                (portRef C (instanceRef t_biu_ad_out_d_18))
+                (portRef C (instanceRef t_biu_ad_out_d_19))
+                (portRef C (instanceRef t_reset_d3_renamed_1))
+                (portRef C (instanceRef BIU_CORE_ad_in_int_0))
+                (portRef C (instanceRef BIU_CORE_ad_in_int_1))
+                (portRef C (instanceRef BIU_CORE_ad_in_int_2))
+                (portRef C (instanceRef BIU_CORE_ad_in_int_3))
+                (portRef C (instanceRef BIU_CORE_ad_in_int_4))
+                (portRef C (instanceRef BIU_CORE_ad_in_int_5))
+                (portRef C (instanceRef BIU_CORE_ad_in_int_6))
+                (portRef C (instanceRef BIU_CORE_ad_in_int_7))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_0))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_1))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_2))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_3))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_4))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_5))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_6))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_7))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_8))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_9))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_10))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_11))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_12))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_13))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_14))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_15))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_0))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_1))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_2))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_3))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_4))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_5))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_6))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_7))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_8))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_9))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_10))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_11))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_12))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_13))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_14))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_15))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_0))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_1))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_2))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_3))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_4))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_5))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_6))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_7))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_8))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_9))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_10))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_11))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_12))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_13))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_14))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_15))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_0))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_1))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_2))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_3))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_4))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_5))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_6))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_7))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_8))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_9))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_10))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_11))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_12))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_13))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_14))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_15))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_0))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_1))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_2))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_3))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_4))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_5))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_6))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_7))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_8))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_9))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_10))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_11))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_12))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_13))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_14))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_15))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_0))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_1))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_2))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_3))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_4))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_5))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_6))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_7))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_8))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_9))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_10))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_11))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_12))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_13))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_14))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_15))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_0))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_1))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_2))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_3))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_4))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_5))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_6))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_7))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_8))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_9))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_10))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_11))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_12))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_13))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_14))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_15))
+                (portRef C (instanceRef BIU_CORE_nmi_d1_renamed_53))
+                (portRef C (instanceRef BIU_CORE_pfq_write_renamed_52))
+                (portRef C (instanceRef BIU_CORE_biu_done_int_renamed_51))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_0))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_1))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_2))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_3))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_4))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_5))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_6))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_7))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_8))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_9))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_10))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_11))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_12))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_13))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_14))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_15))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_16))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_17))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_18))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_19))
+                (portRef C (instanceRef BIU_CORE_ready_d1_renamed_50))
+                (portRef C (instanceRef BIU_CORE_eu_biu_req_d1_renamed_49))
+                (portRef C (instanceRef BIU_CORE_byte_num_renamed_48))
+                (portRef C (instanceRef BIU_CORE_intr_d1_renamed_47))
+                (portRef C (instanceRef BIU_CORE_AD_OE_renamed_46))
+                (portRef C (instanceRef BIU_CORE_ale_int_renamed_45))
+                (portRef C (instanceRef BIU_CORE_clk_d1_renamed_44))
+                (portRef C (instanceRef BIU_CORE_inta_n_int_renamed_43))
+                (portRef C (instanceRef BIU_CORE_rd_n_int_renamed_42))
+                (portRef C (instanceRef BIU_CORE_wr_n_int_renamed_41))
+                (portRef C (instanceRef BIU_CORE_den_int_renamed_40))
+                (portRef C (instanceRef BIU_CORE_biu_state_0))
+                (portRef C (instanceRef BIU_CORE_biu_state_1))
+                (portRef C (instanceRef BIU_CORE_biu_state_2))
+                (portRef C (instanceRef BIU_CORE_biu_state_3))
+                (portRef C (instanceRef BIU_CORE_biu_state_4))
+                (portRef C (instanceRef BIU_CORE_biu_state_5))
+                (portRef C (instanceRef BIU_CORE_biu_state_6))
+                (portRef C (instanceRef BIU_CORE_biu_state_7))
+                (portRef C (instanceRef BIU_CORE_iom_int_renamed_39))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_0_renamed_38))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_1_renamed_37))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_2_renamed_36))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_3_renamed_35))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_4_renamed_34))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_5_renamed_33))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_6_renamed_32))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_7_renamed_31))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_8_renamed_30))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_9_renamed_29))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_10_renamed_28))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_11_renamed_27))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_12_renamed_26))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_13_renamed_25))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_14_renamed_24))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_15_renamed_23))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_16_renamed_22))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_17_renamed_21))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_18_renamed_20))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_19_renamed_19))
+                (portRef C (instanceRef BIU_CORE_clk_d2_renamed_18))
+                (portRef C (instanceRef BIU_CORE_nmi_d2_renamed_17))
+                (portRef C (instanceRef BIU_CORE_intr_d2_renamed_16))
+                (portRef C (instanceRef BIU_CORE_IOM_renamed_15))
+                (portRef C (instanceRef BIU_CORE_RD_n_renamed_14))
+                (portRef C (instanceRef BIU_CORE_INTA_n_renamed_13))
+                (portRef C (instanceRef BIU_CORE_WR_n_renamed_12))
+                (portRef C (instanceRef BIU_CORE_DEN_renamed_11))
+                (portRef C (instanceRef BIU_CORE_ALE_renamed_10))
+                (portRef C (instanceRef BIU_CORE_latched_data_in_0))
+                (portRef C (instanceRef BIU_CORE_latched_data_in_1))
+                (portRef C (instanceRef BIU_CORE_latched_data_in_2))
+                (portRef C (instanceRef BIU_CORE_latched_data_in_3))
+                (portRef C (instanceRef BIU_CORE_latched_data_in_4))
+                (portRef C (instanceRef BIU_CORE_latched_data_in_5))
+                (portRef C (instanceRef BIU_CORE_latched_data_in_6))
+                (portRef C (instanceRef BIU_CORE_latched_data_in_7))
+                (portRef C (instanceRef BIU_CORE_clk_d3_renamed_9))
+                (portRef C (instanceRef BIU_CORE_nmi_d3_renamed_8))
+                (portRef C (instanceRef BIU_CORE_intr_d3_renamed_7))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_0))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_1))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_2))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_3))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_4))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_5))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_6))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_7))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_8))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_9))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_10))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_11))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_12))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_13))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_14))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_15))
+                (portRef C (instanceRef BIU_CORE_pfq_entry0_0))
+                (portRef C (instanceRef BIU_CORE_pfq_entry0_1))
+                (portRef C (instanceRef BIU_CORE_pfq_entry0_2))
+                (portRef C (instanceRef BIU_CORE_pfq_entry0_3))
+                (portRef C (instanceRef BIU_CORE_pfq_entry0_4))
+                (portRef C (instanceRef BIU_CORE_pfq_entry0_5))
+                (portRef C (instanceRef BIU_CORE_pfq_entry0_6))
+                (portRef C (instanceRef BIU_CORE_pfq_entry0_7))
+                (portRef C (instanceRef BIU_CORE_pfq_entry1_0))
+                (portRef C (instanceRef BIU_CORE_pfq_entry1_1))
+                (portRef C (instanceRef BIU_CORE_pfq_entry1_2))
+                (portRef C (instanceRef BIU_CORE_pfq_entry1_3))
+                (portRef C (instanceRef BIU_CORE_pfq_entry1_4))
+                (portRef C (instanceRef BIU_CORE_pfq_entry1_5))
+                (portRef C (instanceRef BIU_CORE_pfq_entry1_6))
+                (portRef C (instanceRef BIU_CORE_pfq_entry1_7))
+                (portRef C (instanceRef BIU_CORE_pfq_entry2_0))
+                (portRef C (instanceRef BIU_CORE_pfq_entry2_1))
+                (portRef C (instanceRef BIU_CORE_pfq_entry2_2))
+                (portRef C (instanceRef BIU_CORE_pfq_entry2_3))
+                (portRef C (instanceRef BIU_CORE_pfq_entry2_4))
+                (portRef C (instanceRef BIU_CORE_pfq_entry2_5))
+                (portRef C (instanceRef BIU_CORE_pfq_entry2_6))
+                (portRef C (instanceRef BIU_CORE_pfq_entry2_7))
+                (portRef C (instanceRef BIU_CORE_pfq_entry3_0))
+                (portRef C (instanceRef BIU_CORE_pfq_entry3_1))
+                (portRef C (instanceRef BIU_CORE_pfq_entry3_2))
+                (portRef C (instanceRef BIU_CORE_pfq_entry3_3))
+                (portRef C (instanceRef BIU_CORE_pfq_entry3_4))
+                (portRef C (instanceRef BIU_CORE_pfq_entry3_5))
+                (portRef C (instanceRef BIU_CORE_pfq_entry3_6))
+                (portRef C (instanceRef BIU_CORE_pfq_entry3_7))
+                (portRef C (instanceRef BIU_CORE_clk_d4_renamed_6))
+                (portRef C (instanceRef BIU_CORE_nmi_d4_renamed_5))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_0))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_1))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_2))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_3))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_4))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_5))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_6))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_7))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_8))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_9))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_10))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_11))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_12))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_13))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_14))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_15))
+                (portRef C (instanceRef BIU_CORE_s_bits_0))
+                (portRef C (instanceRef BIU_CORE_s_bits_1))
+                (portRef C (instanceRef BIU_CORE_s_bits_2))
+                (portRef C (instanceRef BIU_CORE_nmi_d5_renamed_4))
+                (portRef C (instanceRef BIU_CORE_pfq_top_byte_int_d1_0))
+                (portRef C (instanceRef BIU_CORE_pfq_top_byte_int_d1_1))
+                (portRef C (instanceRef BIU_CORE_pfq_top_byte_int_d1_2))
+                (portRef C (instanceRef BIU_CORE_pfq_top_byte_int_d1_3))
+                (portRef C (instanceRef BIU_CORE_pfq_top_byte_int_d1_4))
+                (portRef C (instanceRef BIU_CORE_pfq_top_byte_int_d1_5))
+                (portRef C (instanceRef BIU_CORE_pfq_top_byte_int_d1_6))
+                (portRef C (instanceRef BIU_CORE_pfq_top_byte_int_d1_7))
+                (portRef C (instanceRef BIU_CORE_dtr_int_renamed_3))
+                (portRef C (instanceRef BIU_CORE_DTR_renamed_2))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_0))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_1))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_2))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_3))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_4))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_5))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_6))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_7))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_8))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_9))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_10))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_11))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_12))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_13))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_14))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_15))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_0))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_1))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_2))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_3))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_4))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_5))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_6))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_7))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_8))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_9))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_10))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_11))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_12))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_13))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_14))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_15))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_0))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_1))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_2))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_3))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_4))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_5))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_6))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_7))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_8))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_9))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_10))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_11))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_12))
+                (portRef C (instanceRef EU_CORE_biu_done_d1_renamed_239))
+                (portRef C (instanceRef EU_CORE_eu_stall_pipeline_renamed_238))
+                (portRef C (instanceRef EU_CORE_eu_add_aux_carry_renamed_237))
+                (portRef C (instanceRef EU_CORE_eu_add_carry_renamed_236))
+                (portRef C (instanceRef EU_CORE_eu_add_carry8_renamed_235))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_0))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_1))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_2))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_3))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_4))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_5))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_6))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_7))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_8))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_9))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_10))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_11))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_12))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_13))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_14))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_15))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_0))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_1))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_2))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_3))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_4))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_5))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_6))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_7))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_8))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_9))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_10))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_11))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_12))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_13))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_14))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_15))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_0))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_1))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_2))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_3))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_4))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_5))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_6))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_7))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_8))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_9))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_10))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_11))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_12))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_13))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_14))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_15))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_0))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_1))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_2))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_3))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_4))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_5))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_6))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_7))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_8))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_9))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_10))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_11))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_12))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_13))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_14))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_15))
+                (portRef C (instanceRef EU_CORE_eu_register_si_0))
+                (portRef C (instanceRef EU_CORE_eu_register_si_1))
+                (portRef C (instanceRef EU_CORE_eu_register_si_2))
+                (portRef C (instanceRef EU_CORE_eu_register_si_3))
+                (portRef C (instanceRef EU_CORE_eu_register_si_4))
+                (portRef C (instanceRef EU_CORE_eu_register_si_5))
+                (portRef C (instanceRef EU_CORE_eu_register_si_6))
+                (portRef C (instanceRef EU_CORE_eu_register_si_7))
+                (portRef C (instanceRef EU_CORE_eu_register_si_8))
+                (portRef C (instanceRef EU_CORE_eu_register_si_9))
+                (portRef C (instanceRef EU_CORE_eu_register_si_10))
+                (portRef C (instanceRef EU_CORE_eu_register_si_11))
+                (portRef C (instanceRef EU_CORE_eu_register_si_12))
+                (portRef C (instanceRef EU_CORE_eu_register_si_13))
+                (portRef C (instanceRef EU_CORE_eu_register_si_14))
+                (portRef C (instanceRef EU_CORE_eu_register_si_15))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_0))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_1))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_2))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_3))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_4))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_5))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_6))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_7))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_8))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_9))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_10))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_11))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_12))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_13))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_14))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_15))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_0))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_1))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_2))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_3))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_4))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_5))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_6))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_7))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_8))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_9))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_10))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_11))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_12))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_13))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_14))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_15))
+                (portRef C (instanceRef EU_CORE_eu_register_di_0))
+                (portRef C (instanceRef EU_CORE_eu_register_di_1))
+                (portRef C (instanceRef EU_CORE_eu_register_di_2))
+                (portRef C (instanceRef EU_CORE_eu_register_di_3))
+                (portRef C (instanceRef EU_CORE_eu_register_di_4))
+                (portRef C (instanceRef EU_CORE_eu_register_di_5))
+                (portRef C (instanceRef EU_CORE_eu_register_di_6))
+                (portRef C (instanceRef EU_CORE_eu_register_di_7))
+                (portRef C (instanceRef EU_CORE_eu_register_di_8))
+                (portRef C (instanceRef EU_CORE_eu_register_di_9))
+                (portRef C (instanceRef EU_CORE_eu_register_di_10))
+                (portRef C (instanceRef EU_CORE_eu_register_di_11))
+                (portRef C (instanceRef EU_CORE_eu_register_di_12))
+                (portRef C (instanceRef EU_CORE_eu_register_di_13))
+                (portRef C (instanceRef EU_CORE_eu_register_di_14))
+                (portRef C (instanceRef EU_CORE_eu_register_di_15))
+                (portRef C (instanceRef EU_CORE_eu_flags_0))
+                (portRef C (instanceRef EU_CORE_eu_flags_1))
+                (portRef C (instanceRef EU_CORE_eu_flags_2))
+                (portRef C (instanceRef EU_CORE_eu_flags_3))
+                (portRef C (instanceRef EU_CORE_eu_flags_4))
+                (portRef C (instanceRef EU_CORE_eu_flags_5))
+                (portRef C (instanceRef EU_CORE_eu_flags_6))
+                (portRef C (instanceRef EU_CORE_eu_flags_7))
+                (portRef C (instanceRef EU_CORE_eu_flags_8))
+                (portRef C (instanceRef EU_CORE_eu_flags_9))
+                (portRef C (instanceRef EU_CORE_eu_flags_10))
+                (portRef C (instanceRef EU_CORE_eu_flags_11))
+                (portRef C (instanceRef EU_CORE_eu_flags_12))
+                (portRef C (instanceRef EU_CORE_eu_flags_13))
+                (portRef C (instanceRef EU_CORE_eu_flags_14))
+                (portRef C (instanceRef EU_CORE_eu_flags_15))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_0))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_1))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_2))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_3))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_4))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_5))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_6))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_7))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_8))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_9))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_10))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_11))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_12))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_13))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_14))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_15))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_0))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_1))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_2))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_3))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_4))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_5))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_6))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_7))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_8))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_9))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_10))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_11))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_12))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_13))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_14))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_15))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_0))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_1))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_2))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_3))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_4))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_5))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_6))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_7))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_8))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_9))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_10))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_11))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_12))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_13))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_14))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_15))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_0))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_1))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_2))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_3))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_4))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_5))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_6))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_7))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_8))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_9))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_10))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_11))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_12))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_13))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_14))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_15))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_0))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_1))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_2))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_3))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_4))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_5))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_6))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_7))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_8))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_9))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_10))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_11))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_12))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_13))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_14))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_15))
+                (portRef C (instanceRef EU_CORE_biu_done_d2_renamed_234))
+                (portRef C (instanceRef EU_CORE_eu_flag_t_d_renamed_233))
+                (portRef C (instanceRef EU_CORE_eu_add_overflow16_renamed_232))
+                (portRef C (instanceRef EU_CORE_eu_add_overflow8_renamed_231))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_0))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_1))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_2))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_3))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_4))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_5))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_6))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_7))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_8))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_9))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_10))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_11))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_12))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_13))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_14))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_15))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_16))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_17))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_18))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_19))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_20))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_21))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_22))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_23))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_24))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_25))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_26))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_27))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_28))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_29))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_30))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_31))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_32))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_33))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_34))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_35))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_36))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_37))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_38))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_39))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_40))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_41))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_42))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_43))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_44))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_45))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_46))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_47))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_48))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_49))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_50))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_51))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_0))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_1))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_2))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_3))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_4))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_5))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_6))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_7))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_8))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_9))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_10))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_11))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_12))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_13))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_14))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_15))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_0))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_1))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_2))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_3))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_4))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_5))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_6))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_7))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_8))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_9))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_10))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_11))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_12))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_13))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_14))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_15))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_0))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_1))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_2))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_3))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_4))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_5))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_6))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_7))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_8))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_9))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_12))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_10))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_11))
+                (portRef C (instanceRef BIU_CORE_eu_biu_req_caught_renamed_345))
+                (portRef C (instanceRef BIU_CORE_nmi_caught_renamed_346))
+                (portRef C (instanceRef EU_CORE_eu_tr_latched_renamed_347))
+                (portRef C (instanceRef EU_CORE_biu_done_caught_renamed_348))
+                (portRef C (instanceRef BIU_CORE_BIU_INTR_renamed_376))
+                (portRef C (instanceRef t_reset_d4_renamed_377))
+                (portRef C (instanceRef BIU_CORE_word_cycle_renamed_378))
+                (portRef C (instanceRef EU_CORE_intr_enable_delayed_renamed_379))
+                (portRef O (instanceRef CORE_CLK_BUFGP_renamed_404))
+                (portRef CLK (instanceRef Mshreg_t_biu_ad_oe_d2_renamed_405))
+                (portRef C (instanceRef t_biu_ad_oe_d2_renamed_406))
+                (portRef CLK (instanceRef Mshreg_t_reset_d2_renamed_407))
+                (portRef C (instanceRef t_reset_d2_renamed_408))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_15_renamed_409))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_15))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_14_renamed_410))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_14))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_13_renamed_411))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_13))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_12_renamed_412))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_12))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_11_renamed_413))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_11))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_10_renamed_414))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_10))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_9_renamed_415))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_9))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_8_renamed_416))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_8))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_7_renamed_417))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_7))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_6_renamed_418))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_6))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_3_renamed_419))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_3))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_5_renamed_420))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_5))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_4_renamed_421))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_4))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_2_renamed_422))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_2))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_1_renamed_423))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_1))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_0_renamed_424))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_0))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_15_renamed_425))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_15))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_12_renamed_426))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_12))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_14_renamed_427))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_14))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_13_renamed_428))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_13))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_11_renamed_429))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_11))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_10_renamed_430))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_10))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_9_renamed_431))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_9))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_8_renamed_432))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_8))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_5_renamed_433))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_5))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_7_renamed_434))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_7))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_6_renamed_435))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_6))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_4_renamed_436))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_4))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_3_renamed_437))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_3))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_2_renamed_438))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_2))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_1_renamed_439))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_1))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_14_renamed_440))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_14))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_0_renamed_441))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_0))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_15_renamed_442))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_15))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_13_renamed_443))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_13))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_12_renamed_444))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_12))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_11_renamed_445))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_11))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_10_renamed_446))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_10))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_7_renamed_447))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_7))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_9_renamed_448))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_9))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_8_renamed_449))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_8))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_6_renamed_450))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_6))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_5_renamed_451))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_5))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_4_renamed_452))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_4))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_3_renamed_453))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_3))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_0_renamed_454))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_0))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_2_renamed_455))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_2))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_1_renamed_456))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_1))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_15_renamed_457))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_15))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_14_renamed_458))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_14))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_13_renamed_459))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_13))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_12_renamed_460))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_12))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_9_renamed_461))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_9))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_11_renamed_462))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_11))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_10_renamed_463))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_10))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_8_renamed_464))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_8))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_7_renamed_465))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_7))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_6_renamed_466))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_6))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_5_renamed_467))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_5))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_4_renamed_468))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_4))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_3_renamed_469))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_3))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_2_renamed_470))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_2))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_1_renamed_471))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_1))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_0_renamed_472))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_0))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_15_renamed_473))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_15))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_14_renamed_474))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_14))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_13_renamed_475))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_13))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_10_renamed_476))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_10))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_12_renamed_477))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_12))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_11_renamed_478))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_11))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_9_renamed_479))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_9))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_8_renamed_480))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_8))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_7_renamed_481))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_7))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_6_renamed_482))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_6))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_3_renamed_483))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_3))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_5_renamed_484))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_5))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_4_renamed_485))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_4))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_2_renamed_486))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_2))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_1_renamed_487))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_1))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_0_renamed_488))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_0))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_15_renamed_489))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_15))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_12_renamed_490))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_12))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_14_renamed_491))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_14))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_13_renamed_492))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_13))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_11_renamed_493))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_11))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_10_renamed_494))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_10))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_9_renamed_495))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_9))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_8_renamed_496))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_8))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_5_renamed_497))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_5))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_7_renamed_498))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_7))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_6_renamed_499))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_6))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_4_renamed_500))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_4))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_3_renamed_501))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_3))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_2_renamed_502))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_2))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_1_renamed_503))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_1))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_14_renamed_504))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_14))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_0_renamed_505))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_0))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_15_renamed_506))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_15))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_13_renamed_507))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_13))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_12_renamed_508))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_12))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_11_renamed_509))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_11))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_10_renamed_510))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_10))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_7_renamed_511))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_7))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_9_renamed_512))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_9))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_8_renamed_513))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_8))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_6_renamed_514))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_6))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_5_renamed_515))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_5))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_4_renamed_516))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_4))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_3_renamed_517))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_3))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_0_renamed_518))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_0))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_2_renamed_519))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_2))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_1_renamed_520))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_1))
+                (portRef clka (instanceRef EU_CORE_EU4Kx32_i))
+              )
+            )
+            (net CLK_IBUF
+              (joined
+                (portRef D (instanceRef BIU_CORE_clk_d1_renamed_44))
+                (portRef O (instanceRef CLK_IBUF_renamed_340))
+              )
+            )
+            (net RESET_IBUF
+              (joined
+                (portRef O (instanceRef RESET_IBUF_renamed_341))
+                (portRef D (instanceRef Mshreg_t_reset_d2_renamed_407))
+              )
+            )
+            (net READY_IBUF
+              (joined
+                (portRef D (instanceRef BIU_CORE_ready_d1_renamed_50))
+                (portRef O (instanceRef READY_IBUF_renamed_342))
+              )
+            )
+            (net INTR_IBUF
+              (joined
+                (portRef D (instanceRef BIU_CORE_intr_d1_renamed_47))
+                (portRef O (instanceRef INTR_IBUF_renamed_343))
+              )
+            )
+            (net NMI_IBUF
+              (joined
+                (portRef D (instanceRef BIU_CORE_nmi_d1_renamed_53))
+                (portRef O (instanceRef NMI_IBUF_renamed_344))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_19_ "BIU_CORE/AD_OUT<19>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_19))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_19))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_19_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_18_ "BIU_CORE/AD_OUT<18>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_18))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_18))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_18_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_17_ "BIU_CORE/AD_OUT<17>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_17))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_17))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_17_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_16_ "BIU_CORE/AD_OUT<16>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_16))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_16))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_16_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_15_ "BIU_CORE/AD_OUT<15>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_15))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_15))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_15_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_14_ "BIU_CORE/AD_OUT<14>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_14))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_14))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_14_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_13_ "BIU_CORE/AD_OUT<13>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_13))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_13))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_13_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_12_ "BIU_CORE/AD_OUT<12>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_12))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_12))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_12_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_11_ "BIU_CORE/AD_OUT<11>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_11))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_11))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_11_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_10_ "BIU_CORE/AD_OUT<10>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_10))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_10))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_10_2))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_9_ "BIU_CORE/AD_OUT<9>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_9))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_9))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_9_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_8_ "BIU_CORE/AD_OUT<8>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_8))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_8))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_8_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_7_ "BIU_CORE/AD_OUT<7>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_7))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_7))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_7__))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_6_ "BIU_CORE/AD_OUT<6>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_6))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_6))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_6__))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_5_ "BIU_CORE/AD_OUT<5>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_5))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_5))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_5__))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_4_ "BIU_CORE/AD_OUT<4>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_4))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_4))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_4__))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_3_ "BIU_CORE/AD_OUT<3>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_3))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_3))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_3__))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_2_ "BIU_CORE/AD_OUT<2>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_2))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_2))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_2__))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_1_ "BIU_CORE/AD_OUT<1>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_1))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_1__))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_0_ "BIU_CORE/AD_OUT<0>")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_0))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_0))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_0__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_d1_7_ "BIU_CORE/pfq_top_byte_int_d1<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_top_byte_int_d1_7))
+                (portRef I2 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT111_renamed_320))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT112))
+                (portRef I3 (instanceRef EU_CORE_mux13_51_renamed_156))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_d1_6_ "BIU_CORE/pfq_top_byte_int_d1<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_top_byte_int_d1_6))
+                (portRef I2 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT101_renamed_321))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT102))
+                (portRef I3 (instanceRef EU_CORE_mux12_51_renamed_162))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_d1_5_ "BIU_CORE/pfq_top_byte_int_d1<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_top_byte_int_d1_5))
+                (portRef I2 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT91_renamed_322))
+                (portRef I3 (instanceRef EU_CORE_mux11_51_renamed_168))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_d1_4_ "BIU_CORE/pfq_top_byte_int_d1<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_top_byte_int_d1_4))
+                (portRef I2 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT81_renamed_323))
+                (portRef I3 (instanceRef EU_CORE_mux10_51_renamed_174))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_d1_3_ "BIU_CORE/pfq_top_byte_int_d1<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_top_byte_int_d1_3))
+                (portRef I2 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT71_renamed_324))
+                (portRef I3 (instanceRef EU_CORE_mux9_51_renamed_192))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_d1_2_ "BIU_CORE/pfq_top_byte_int_d1<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_top_byte_int_d1_2))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT92))
+                (portRef I3 (instanceRef EU_CORE_mux8_51_renamed_180))
+                (portRef I0 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT61))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_d1_1_ "BIU_CORE/pfq_top_byte_int_d1<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_top_byte_int_d1_1))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT82))
+                (portRef I3 (instanceRef EU_CORE_mux7_51_renamed_186))
+                (portRef I0 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT51))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_d1_0_ "BIU_CORE/pfq_top_byte_int_d1<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_top_byte_int_d1_0))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT72))
+                (portRef I3 (instanceRef EU_CORE_mux_51_renamed_222))
+                (portRef I0 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT1_SW0))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_15_ "BIU_CORE/pfq_addr_out_d1<15>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_15))
+                (portRef I0 (instanceRef EU_CORE_mux6_71_renamed_197))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_14_ "BIU_CORE/pfq_addr_out_d1<14>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_14))
+                (portRef I0 (instanceRef EU_CORE_mux5_71_renamed_201))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_13_ "BIU_CORE/pfq_addr_out_d1<13>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_13))
+                (portRef I0 (instanceRef EU_CORE_mux4_5_renamed_204))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_12_ "BIU_CORE/pfq_addr_out_d1<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_12))
+                (portRef I0 (instanceRef EU_CORE_mux3_5_renamed_210))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_11_ "BIU_CORE/pfq_addr_out_d1<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_11))
+                (portRef I0 (instanceRef EU_CORE_mux2_5_renamed_226))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_10_ "BIU_CORE/pfq_addr_out_d1<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_10))
+                (portRef I0 (instanceRef EU_CORE_mux1_71_renamed_217))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_9_ "BIU_CORE/pfq_addr_out_d1<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_9))
+                (portRef I0 (instanceRef EU_CORE_mux15_5_renamed_136))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_8_ "BIU_CORE/pfq_addr_out_d1<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_8))
+                (portRef I0 (instanceRef EU_CORE_mux14_5_renamed_142))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_7_ "BIU_CORE/pfq_addr_out_d1<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_7))
+                (portRef I0 (instanceRef EU_CORE_mux13_5_renamed_154))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_6_ "BIU_CORE/pfq_addr_out_d1<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_6))
+                (portRef I0 (instanceRef EU_CORE_mux12_5_renamed_160))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_5_ "BIU_CORE/pfq_addr_out_d1<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_5))
+                (portRef I0 (instanceRef EU_CORE_mux11_5_renamed_166))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_4_ "BIU_CORE/pfq_addr_out_d1<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_4))
+                (portRef I0 (instanceRef EU_CORE_mux10_5_renamed_172))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_3_ "BIU_CORE/pfq_addr_out_d1<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_3))
+                (portRef I0 (instanceRef EU_CORE_mux9_5_renamed_190))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_2_ "BIU_CORE/pfq_addr_out_d1<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_2))
+                (portRef I0 (instanceRef EU_CORE_mux8_5_renamed_178))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_1_ "BIU_CORE/pfq_addr_out_d1<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_1))
+                (portRef I0 (instanceRef EU_CORE_mux7_5_renamed_184))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_0_ "BIU_CORE/pfq_addr_out_d1<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_0))
+                (portRef I0 (instanceRef EU_CORE_mux_5_renamed_220))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_15_ "BIU_CORE/biu_register_es_d2<15>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux6_6_renamed_195))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_14_ "BIU_CORE/biu_register_es_d2<14>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux5_6_renamed_199))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_13_ "BIU_CORE/biu_register_es_d2<13>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux4_6_renamed_207))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_12_ "BIU_CORE/biu_register_es_d2<12>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux3_6_renamed_213))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_11_ "BIU_CORE/biu_register_es_d2<11>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux2_6_renamed_229))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_10_ "BIU_CORE/biu_register_es_d2<10>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux1_6_renamed_215))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_9_ "BIU_CORE/biu_register_es_d2<9>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux15_6_renamed_139))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_8_ "BIU_CORE/biu_register_es_d2<8>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux14_6_renamed_145))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_7_ "BIU_CORE/biu_register_es_d2<7>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux13_6_renamed_157))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_6_ "BIU_CORE/biu_register_es_d2<6>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux12_6_renamed_163))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_5_ "BIU_CORE/biu_register_es_d2<5>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux11_6_renamed_169))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_4_ "BIU_CORE/biu_register_es_d2<4>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux10_6_renamed_175))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_3_ "BIU_CORE/biu_register_es_d2<3>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux9_6_renamed_193))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_2_ "BIU_CORE/biu_register_es_d2<2>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux8_6_renamed_181))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_1_ "BIU_CORE/biu_register_es_d2<1>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux7_6_renamed_187))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_0_ "BIU_CORE/biu_register_es_d2<0>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux_6_renamed_223))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_15_ "BIU_CORE/biu_register_ss_d2<15>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux6_6_renamed_195))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_14_ "BIU_CORE/biu_register_ss_d2<14>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux5_6_renamed_199))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_13_ "BIU_CORE/biu_register_ss_d2<13>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux4_6_renamed_207))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_12_ "BIU_CORE/biu_register_ss_d2<12>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux3_6_renamed_213))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_11_ "BIU_CORE/biu_register_ss_d2<11>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux2_6_renamed_229))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_10_ "BIU_CORE/biu_register_ss_d2<10>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux1_6_renamed_215))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_9_ "BIU_CORE/biu_register_ss_d2<9>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux15_6_renamed_139))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_8_ "BIU_CORE/biu_register_ss_d2<8>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux14_6_renamed_145))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_7_ "BIU_CORE/biu_register_ss_d2<7>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux13_6_renamed_157))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_6_ "BIU_CORE/biu_register_ss_d2<6>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux12_6_renamed_163))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_5_ "BIU_CORE/biu_register_ss_d2<5>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux11_6_renamed_169))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_4_ "BIU_CORE/biu_register_ss_d2<4>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux10_6_renamed_175))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_3_ "BIU_CORE/biu_register_ss_d2<3>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux9_6_renamed_193))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_2_ "BIU_CORE/biu_register_ss_d2<2>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux8_6_renamed_181))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_1_ "BIU_CORE/biu_register_ss_d2<1>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux7_6_renamed_187))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_0_ "BIU_CORE/biu_register_ss_d2<0>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux_6_renamed_223))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_15_ "BIU_CORE/biu_register_cs_d2<15>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux6_6_renamed_195))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_14_ "BIU_CORE/biu_register_cs_d2<14>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux5_6_renamed_199))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_13_ "BIU_CORE/biu_register_cs_d2<13>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux4_6_renamed_207))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_12_ "BIU_CORE/biu_register_cs_d2<12>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux3_6_renamed_213))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_11_ "BIU_CORE/biu_register_cs_d2<11>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux2_6_renamed_229))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_10_ "BIU_CORE/biu_register_cs_d2<10>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux1_6_renamed_215))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_9_ "BIU_CORE/biu_register_cs_d2<9>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux15_6_renamed_139))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_8_ "BIU_CORE/biu_register_cs_d2<8>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux14_6_renamed_145))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_7_ "BIU_CORE/biu_register_cs_d2<7>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux13_6_renamed_157))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_6_ "BIU_CORE/biu_register_cs_d2<6>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux12_6_renamed_163))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_5_ "BIU_CORE/biu_register_cs_d2<5>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux11_6_renamed_169))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_4_ "BIU_CORE/biu_register_cs_d2<4>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux10_6_renamed_175))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_3_ "BIU_CORE/biu_register_cs_d2<3>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux9_6_renamed_193))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_2_ "BIU_CORE/biu_register_cs_d2<2>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux8_6_renamed_181))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_1_ "BIU_CORE/biu_register_cs_d2<1>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux7_6_renamed_187))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_0_ "BIU_CORE/biu_register_cs_d2<0>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux_6_renamed_223))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_15_ "BIU_CORE/biu_register_ds_d2<15>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux6_6_renamed_195))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_14_ "BIU_CORE/biu_register_ds_d2<14>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux5_6_renamed_199))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_13_ "BIU_CORE/biu_register_ds_d2<13>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux4_6_renamed_207))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_12_ "BIU_CORE/biu_register_ds_d2<12>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux3_6_renamed_213))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_11_ "BIU_CORE/biu_register_ds_d2<11>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux2_6_renamed_229))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_10_ "BIU_CORE/biu_register_ds_d2<10>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux1_6_renamed_215))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_9_ "BIU_CORE/biu_register_ds_d2<9>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux15_6_renamed_139))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_8_ "BIU_CORE/biu_register_ds_d2<8>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux14_6_renamed_145))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_7_ "BIU_CORE/biu_register_ds_d2<7>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux13_6_renamed_157))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_6_ "BIU_CORE/biu_register_ds_d2<6>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux12_6_renamed_163))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_5_ "BIU_CORE/biu_register_ds_d2<5>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux11_6_renamed_169))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_4_ "BIU_CORE/biu_register_ds_d2<4>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux10_6_renamed_175))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_3_ "BIU_CORE/biu_register_ds_d2<3>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux9_6_renamed_193))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_2_ "BIU_CORE/biu_register_ds_d2<2>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux8_6_renamed_181))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_1_ "BIU_CORE/biu_register_ds_d2<1>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux7_6_renamed_187))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_0_ "BIU_CORE/biu_register_ds_d2<0>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux_6_renamed_223))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_15_ "BIU_CORE/biu_register_rm_d2<15>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux6_7_renamed_196))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_14_ "BIU_CORE/biu_register_rm_d2<14>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux5_7_renamed_200))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_13_ "BIU_CORE/biu_register_rm_d2<13>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux4_51_renamed_206))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_12_ "BIU_CORE/biu_register_rm_d2<12>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux3_51_renamed_212))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_11_ "BIU_CORE/biu_register_rm_d2<11>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux2_51_renamed_228))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_10_ "BIU_CORE/biu_register_rm_d2<10>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux1_7_renamed_216))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_9_ "BIU_CORE/biu_register_rm_d2<9>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux15_51_renamed_138))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_8_ "BIU_CORE/biu_register_rm_d2<8>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux14_51_renamed_144))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_7_ "BIU_CORE/biu_register_rm_d2<7>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux13_51_renamed_156))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_6_ "BIU_CORE/biu_register_rm_d2<6>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux12_51_renamed_162))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_5_ "BIU_CORE/biu_register_rm_d2<5>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux11_51_renamed_168))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_4_ "BIU_CORE/biu_register_rm_d2<4>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux10_51_renamed_174))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_3_ "BIU_CORE/biu_register_rm_d2<3>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux9_51_renamed_192))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_2_ "BIU_CORE/biu_register_rm_d2<2>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux8_51_renamed_180))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_1_ "BIU_CORE/biu_register_rm_d2<1>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux7_51_renamed_186))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_0_ "BIU_CORE/biu_register_rm_d2<0>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux_51_renamed_222))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_15_ "BIU_CORE/biu_register_reg_d2<15>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux6_7_renamed_196))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_14_ "BIU_CORE/biu_register_reg_d2<14>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux5_7_renamed_200))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_13_ "BIU_CORE/biu_register_reg_d2<13>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux4_51_renamed_206))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_12_ "BIU_CORE/biu_register_reg_d2<12>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux3_51_renamed_212))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_11_ "BIU_CORE/biu_register_reg_d2<11>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux2_51_renamed_228))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_10_ "BIU_CORE/biu_register_reg_d2<10>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux1_7_renamed_216))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_9_ "BIU_CORE/biu_register_reg_d2<9>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux15_51_renamed_138))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_8_ "BIU_CORE/biu_register_reg_d2<8>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux14_51_renamed_144))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_7_ "BIU_CORE/biu_register_reg_d2<7>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux13_51_renamed_156))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_6_ "BIU_CORE/biu_register_reg_d2<6>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux12_51_renamed_162))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_5_ "BIU_CORE/biu_register_reg_d2<5>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux11_51_renamed_168))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_4_ "BIU_CORE/biu_register_reg_d2<4>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux10_51_renamed_174))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_3_ "BIU_CORE/biu_register_reg_d2<3>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux9_51_renamed_192))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_2_ "BIU_CORE/biu_register_reg_d2<2>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux8_51_renamed_180))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_1_ "BIU_CORE/biu_register_reg_d2<1>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux7_51_renamed_186))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_0_ "BIU_CORE/biu_register_reg_d2<0>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux_51_renamed_222))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_15_ "BIU_CORE/biu_return_data_int_d2<15>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux6_7_renamed_196))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_14_ "BIU_CORE/biu_return_data_int_d2<14>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux5_7_renamed_200))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_13_ "BIU_CORE/biu_return_data_int_d2<13>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux4_51_renamed_206))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_12_ "BIU_CORE/biu_return_data_int_d2<12>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux3_51_renamed_212))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_11_ "BIU_CORE/biu_return_data_int_d2<11>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux2_51_renamed_228))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_10_ "BIU_CORE/biu_return_data_int_d2<10>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux1_7_renamed_216))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_9_ "BIU_CORE/biu_return_data_int_d2<9>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux15_51_renamed_138))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_8_ "BIU_CORE/biu_return_data_int_d2<8>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux14_51_renamed_144))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_7_ "BIU_CORE/biu_return_data_int_d2<7>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux13_51_renamed_156))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_6_ "BIU_CORE/biu_return_data_int_d2<6>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux12_51_renamed_162))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_5_ "BIU_CORE/biu_return_data_int_d2<5>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux11_51_renamed_168))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_4_ "BIU_CORE/biu_return_data_int_d2<4>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux10_51_renamed_174))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_3_ "BIU_CORE/biu_return_data_int_d2<3>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux9_51_renamed_192))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_2_ "BIU_CORE/biu_return_data_int_d2<2>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux8_51_renamed_180))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_1_ "BIU_CORE/biu_return_data_int_d2<1>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux7_51_renamed_186))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_0_ "BIU_CORE/biu_return_data_int_d2<0>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux_51_renamed_222))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_INTA_n "BIU_CORE/INTA_n")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_INTA_n_renamed_13))
+                (portRef I (instanceRef INTA_n_OBUF))
+              )
+            )
+            (net (rename BIU_CORE_ALE "BIU_CORE/ALE")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_ALE_renamed_10))
+                (portRef I (instanceRef ALE_OBUF))
+              )
+            )
+            (net (rename BIU_CORE_RD_n "BIU_CORE/RD_n")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_RD_n_renamed_14))
+                (portRef I (instanceRef RD_n_OBUF))
+              )
+            )
+            (net (rename BIU_CORE_WR_n "BIU_CORE/WR_n")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_WR_n_renamed_12))
+                (portRef I (instanceRef WR_n_OBUF))
+              )
+            )
+            (net (rename BIU_CORE_s_bits_0_ "BIU_CORE/s_bits<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_s_bits_0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o1_renamed_243))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_161_o_renamed_263))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_184_o_renamed_264))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT1))
+                (portRef I (instanceRef SSO_n_OBUF))
+                (portRef I2 (instanceRef BIU_CORE_s_bits_2__word_cycle_AND_33_o1))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT21))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT31))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT41))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT51))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT61))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT71))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT151))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT161))
+              )
+            )
+            (net (rename BIU_CORE_IOM "BIU_CORE/IOM")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_IOM_renamed_15))
+                (portRef I (instanceRef IOM_OBUF))
+              )
+            )
+            (net (rename BIU_CORE_DTR "BIU_CORE/DTR")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_DTR_renamed_2))
+                (portRef I (instanceRef DTR_OBUF))
+              )
+            )
+            (net (rename BIU_CORE_DEN "BIU_CORE/DEN")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_DEN_renamed_11))
+                (portRef I (instanceRef DEN_OBUF))
+              )
+            )
+            (net (rename BIU_CORE_AD_OE "BIU_CORE/AD_OE")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_AD_OE_renamed_46))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_174_o_renamed_265))
+                (portRef D (instanceRef Mshreg_t_biu_ad_oe_d2_renamed_405))
+              )
+            )
+            (net (rename BIU_CORE_biu_done_int "BIU_CORE/biu_done_int")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_done_int_renamed_51))
+                (portRef D (instanceRef EU_CORE_biu_done_d1_renamed_239))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o4))
+                (portRef I1 (instanceRef BIU_CORE_eu_biu_req_caught_glue_set_renamed_385))
+              )
+            )
+            (net t_biu_clk_counter_zero
+              (joined
+                (portRef O (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_3))
+                (portRef I2 (instanceRef EU_CORE_mux19_4_renamed_119))
+                (portRef I3 (instanceRef EU_CORE_mux3_4_renamed_209))
+              )
+            )
+            (net (rename BIU_CORE_nmi_caught "BIU_CORE/nmi_caught")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux9_4_renamed_189))
+                (portRef Q (instanceRef BIU_CORE_nmi_caught_renamed_346))
+                (portRef I4 (instanceRef BIU_CORE_nmi_caught_glue_set_renamed_386))
+                (portRef I2 (instanceRef EU_CORE_mux25_4_renamed_88))
+              )
+            )
+            (net (rename BIU_CORE_BIU_INTR "BIU_CORE/BIU_INTR")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_intr_asserted1))
+                (portRef Q (instanceRef BIU_CORE_BIU_INTR_renamed_376))
+                (portRef I0 (instanceRef BIU_CORE_BIU_INTR_rstpot_renamed_398))
+                (portRef I2 (instanceRef EU_CORE_mux23_4_renamed_380))
+              )
+            )
+            (net t_pfq_empty
+              (joined
+                (portRef I1 (instanceRef BIU_CORE__n0870_inv1))
+                (portRef O (instanceRef BIU_CORE_pfq_empty1))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_15_ "EU_CORE/eu_biu_command<15>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_15))
+                (portRef I0 (instanceRef EU_CORE_mux22_8_renamed_103))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_14_ "EU_CORE/eu_biu_command<14>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_14))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_biu_segment11))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_biu_segment21))
+                (portRef I1 (instanceRef EU_CORE_mux21_8_renamed_107))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_13_ "EU_CORE/eu_biu_command<13>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_13))
+                (portRef I3 (instanceRef BIU_CORE__n0865_inv1))
+                (portRef I3 (instanceRef BIU_CORE__n0861_inv1))
+                (portRef I3 (instanceRef BIU_CORE__n0857_inv1))
+                (portRef I3 (instanceRef BIU_CORE__n0853_inv1))
+                (portRef I3 (instanceRef BIU_CORE__n0905_inv1))
+                (portRef I3 (instanceRef BIU_CORE__n0849_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n0870_inv1))
+                (portRef I0 (instanceRef BIU_CORE_eu_biu_strobe_1__PWR_2_o_equal_61_o_1_1))
+                (portRef I3 (instanceRef BIU_CORE__n0867_inv1))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_0__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_1__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_2__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_3__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_4__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_5__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_6__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_7__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_8__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_9__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_10__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_11__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_12__))
+                (portRef I2 (instanceRef EU_CORE_mux20_4_renamed_113))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_12_ "EU_CORE/eu_biu_command<12>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_12))
+                (portRef I1 (instanceRef EU_CORE_mux19_4_renamed_119))
+                (portRef I4 (instanceRef BIU_CORE__n0865_inv1))
+                (portRef I4 (instanceRef BIU_CORE__n0861_inv1))
+                (portRef I4 (instanceRef BIU_CORE__n0857_inv1))
+                (portRef I4 (instanceRef BIU_CORE__n0853_inv1))
+                (portRef I4 (instanceRef BIU_CORE__n0905_inv1))
+                (portRef I4 (instanceRef BIU_CORE__n0849_inv1))
+                (portRef I2 (instanceRef BIU_CORE__n0870_inv1))
+                (portRef I1 (instanceRef BIU_CORE_eu_biu_strobe_1__PWR_2_o_equal_61_o_1_1))
+                (portRef I2 (instanceRef BIU_CORE__n0867_inv1))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_0__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_1__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_2__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_3__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_4__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_5__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_6__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_7__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_8__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_9__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_10__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_11__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_12__))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_11_ "EU_CORE/eu_biu_command<11>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_11))
+                (portRef I1 (instanceRef EU_CORE_mux18_4_renamed_125))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_biu_segment21))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_10_ "EU_CORE/eu_biu_command<10>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_10))
+                (portRef I0 (instanceRef EU_CORE_mux17_8_renamed_134))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_biu_segment11))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_9_ "EU_CORE/eu_biu_command<9>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_biu_req_d1_renamed_49))
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_9))
+                (portRef I2 (instanceRef BIU_CORE_eu_biu_req_caught_glue_set_renamed_385))
+                (portRef I2 (instanceRef EU_CORE_biu_done_caught_glue_set_renamed_403))
+                (portRef I2 (instanceRef EU_CORE_mux31_4_renamed_54))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_8_ "EU_CORE/eu_biu_command<8>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_8))
+                (portRef I3 (instanceRef BIU_CORE__n09261))
+                (portRef I4 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_11_o1))
+                (portRef I3 (instanceRef BIU_CORE_eu_biu_req_code_4__PWR_2_o_equal_102_o_4_1))
+                (portRef I3 (instanceRef BIU_CORE__n09181))
+                (portRef I0 (instanceRef BIU_CORE_eu_biu_req_code_4__INV_26_o1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o2_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_1_renamed_260))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_12_SW0))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT3_SW0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_2_renamed_268))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_3_renamed_269))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_2_renamed_271))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_3_renamed_272))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_2_renamed_274))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_3_renamed_275))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_2_renamed_277))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_3_renamed_278))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_2_renamed_280))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_3_renamed_281))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_2_renamed_283))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_3_renamed_284))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_2_renamed_286))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_3_renamed_287))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_2_renamed_289))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_3_renamed_290))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_2_renamed_292))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_3_renamed_293))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_2_renamed_295))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_3_renamed_296))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_2_renamed_298))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_3_renamed_299))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_2_renamed_301))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_3_renamed_302))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT1_SW0))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT2_SW0))
+                (portRef I4 (instanceRef BIU_CORE__n0929_0_11))
+                (portRef I4 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_11_o_inv1))
+                (portRef I2 (instanceRef EU_CORE_mux30_4_renamed_72))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_7_ "EU_CORE/eu_biu_command<7>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_7))
+                (portRef I1 (instanceRef EU_CORE_mux29_4_renamed_60))
+                (portRef I2 (instanceRef BIU_CORE__n09261))
+                (portRef I5 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_11_o1))
+                (portRef I4 (instanceRef BIU_CORE_eu_biu_req_code_4__PWR_2_o_equal_102_o_4_1))
+                (portRef I2 (instanceRef BIU_CORE__n09181))
+                (portRef I4 (instanceRef BIU_CORE_eu_biu_req_code_4__INV_26_o1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o2_renamed_259))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_1_renamed_260))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_12_SW0))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT3_SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_2_renamed_268))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_3_renamed_269))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_2_renamed_271))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_3_renamed_272))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_2_renamed_274))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_3_renamed_275))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_2_renamed_277))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_3_renamed_278))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_2_renamed_280))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_3_renamed_281))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_2_renamed_283))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_3_renamed_284))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_2_renamed_286))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_3_renamed_287))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_2_renamed_289))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_3_renamed_290))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_2_renamed_292))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_3_renamed_293))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_2_renamed_295))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_3_renamed_296))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_2_renamed_298))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_3_renamed_299))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_2_renamed_301))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_3_renamed_302))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT1_SW0))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT2_SW0))
+                (portRef I1 (instanceRef BIU_CORE__n0929_0_11))
+                (portRef I5 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_11_o_inv1))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_6_ "EU_CORE/eu_biu_command<6>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_6))
+                (portRef I1 (instanceRef BIU_CORE__n0865_inv1))
+                (portRef I1 (instanceRef BIU_CORE__n0861_inv1))
+                (portRef I2 (instanceRef BIU_CORE__n0857_inv1))
+                (portRef I2 (instanceRef BIU_CORE__n0853_inv1))
+                (portRef I2 (instanceRef BIU_CORE__n0905_inv1))
+                (portRef I2 (instanceRef BIU_CORE__n0849_inv1))
+                (portRef I1 (instanceRef BIU_CORE__n09261))
+                (portRef I3 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_11_o1))
+                (portRef I2 (instanceRef BIU_CORE_eu_biu_req_code_4__PWR_2_o_equal_102_o_4_1))
+                (portRef I1 (instanceRef BIU_CORE__n09181))
+                (portRef I3 (instanceRef BIU_CORE_eu_biu_req_code_4__INV_26_o1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o2_renamed_259))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_1_renamed_260))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_12_SW0))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT3_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_2_renamed_268))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_3_renamed_269))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_2_renamed_271))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_3_renamed_272))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_2_renamed_274))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_3_renamed_275))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_2_renamed_277))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_3_renamed_278))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_2_renamed_280))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_3_renamed_281))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_2_renamed_283))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_3_renamed_284))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_2_renamed_286))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_3_renamed_287))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_2_renamed_289))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_3_renamed_290))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_2_renamed_292))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_3_renamed_293))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_2_renamed_295))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_3_renamed_296))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_2_renamed_298))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_3_renamed_299))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_2_renamed_301))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_3_renamed_302))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT1_SW0))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT2_SW0))
+                (portRef I3 (instanceRef BIU_CORE__n0929_0_11))
+                (portRef I1 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_11_o_inv1))
+                (portRef I2 (instanceRef EU_CORE_mux28_4_renamed_66))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_5_ "EU_CORE/eu_biu_command<5>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_5))
+                (portRef I1 (instanceRef EU_CORE_mux27_8_renamed_81))
+                (portRef I2 (instanceRef BIU_CORE__n0865_inv1))
+                (portRef I2 (instanceRef BIU_CORE__n0861_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n0857_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n0853_inv1))
+                (portRef I1 (instanceRef BIU_CORE__n0905_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n0849_inv1))
+                (portRef I4 (instanceRef BIU_CORE__n09261))
+                (portRef I2 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_11_o1))
+                (portRef I1 (instanceRef BIU_CORE_eu_biu_req_code_4__PWR_2_o_equal_102_o_4_1))
+                (portRef I4 (instanceRef BIU_CORE__n09181))
+                (portRef I2 (instanceRef BIU_CORE_eu_biu_req_code_4__INV_26_o1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o2_renamed_259))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_1_renamed_260))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_12_SW0))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT3_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_2_renamed_268))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_3_renamed_269))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_2_renamed_271))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_3_renamed_272))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_2_renamed_274))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_3_renamed_275))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_2_renamed_277))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_3_renamed_278))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_2_renamed_280))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_3_renamed_281))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_2_renamed_283))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_3_renamed_284))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_2_renamed_286))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_3_renamed_287))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_2_renamed_289))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_3_renamed_290))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_2_renamed_292))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_3_renamed_293))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_2_renamed_295))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_3_renamed_296))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_2_renamed_298))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_3_renamed_299))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_2_renamed_301))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_3_renamed_302))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT1_SW0))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT2_SW0))
+                (portRef I2 (instanceRef BIU_CORE__n0929_0_11))
+                (portRef I2 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_11_o_inv1))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_4_ "EU_CORE/eu_biu_command<4>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_4))
+                (portRef I0 (instanceRef BIU_CORE__n0865_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n0861_inv1))
+                (portRef I1 (instanceRef BIU_CORE__n0857_inv1))
+                (portRef I1 (instanceRef BIU_CORE__n0853_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n0905_inv1))
+                (portRef I1 (instanceRef BIU_CORE__n0849_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n09261))
+                (portRef I1 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_11_o1))
+                (portRef I0 (instanceRef BIU_CORE_eu_biu_req_code_4__PWR_2_o_equal_102_o_4_1))
+                (portRef I0 (instanceRef BIU_CORE__n09181))
+                (portRef I1 (instanceRef BIU_CORE_eu_biu_req_code_4__INV_26_o1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o2_renamed_259))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_1_renamed_260))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_12_SW0))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT3_SW0))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_2_renamed_268))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_3_renamed_269))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_2_renamed_271))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_3_renamed_272))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_2_renamed_274))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_3_renamed_275))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_2_renamed_277))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_3_renamed_278))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_2_renamed_280))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_3_renamed_281))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_2_renamed_283))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_3_renamed_284))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_2_renamed_286))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_3_renamed_287))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_2_renamed_289))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_3_renamed_290))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_2_renamed_292))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_3_renamed_293))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_2_renamed_295))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_3_renamed_296))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_2_renamed_298))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_3_renamed_299))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_2_renamed_301))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_3_renamed_302))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT1_SW0))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT2_SW0))
+                (portRef I0 (instanceRef BIU_CORE__n0929_0_11))
+                (portRef I3 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_11_o_inv1))
+                (portRef I2 (instanceRef EU_CORE_mux26_4_renamed_82))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_3_ "EU_CORE/eu_biu_command<3>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_3))
+                (portRef I0 (instanceRef EU_CORE_mux25_4_renamed_88))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_2_ "EU_CORE/eu_biu_command<2>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_2))
+                (portRef I0 (instanceRef EU_CORE_mux24_4_renamed_94))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_1_ "EU_CORE/eu_biu_command<1>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_1))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_biu_segment21))
+                (portRef I0 (instanceRef EU_CORE_mux23_4_renamed_380))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_0_ "EU_CORE/eu_biu_command<0>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_0))
+                (portRef I1 (instanceRef EU_CORE_mux16_4_renamed_147))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_biu_segment11))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_15_ "EU_CORE/eu_biu_dataout<15>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_es_15))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_15))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_15))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_15))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_15))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_15))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_15))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_7__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_14_ "EU_CORE/eu_biu_dataout<14>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_es_14))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_14))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_14))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_14))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_14))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_14))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_14))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_6__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_13_ "EU_CORE/eu_biu_dataout<13>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_es_13))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_13))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_13))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_13))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_13))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_13))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_13))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_5__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_12_ "EU_CORE/eu_biu_dataout<12>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_es_12))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_12))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_12))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_12))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_12))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_12))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_12))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_4__SW0))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_12__))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_11_ "EU_CORE/eu_biu_dataout<11>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_es_11))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_11))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_11))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_11))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_11))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_11))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_11))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_3__SW0))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_11__))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_10_ "EU_CORE/eu_biu_dataout<10>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_es_10))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_10))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_10))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_10))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_10))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_10))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_10))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_2__SW0))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_10__))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_9_ "EU_CORE/eu_biu_dataout<9>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_es_9))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_9))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_9))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_9))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_9))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_9))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_9))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_1__SW0))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_9__))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_8_ "EU_CORE/eu_biu_dataout<8>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_es_8))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_8))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_8))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_8))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_8))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_8))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_8))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_0__SW0))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_8__))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_7_ "EU_CORE/eu_biu_dataout<7>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_es_7))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_7))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_7))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_7))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_7))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_7))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_7))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_7__SW0))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_7__))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_6_ "EU_CORE/eu_biu_dataout<6>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_es_6))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_6))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_6))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_6))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_6))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_6))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_6))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_6__SW0))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_6__))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_5_ "EU_CORE/eu_biu_dataout<5>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_es_5))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_5))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_5))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_5))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_5))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_5))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_5))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT62))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_5__SW0))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_5__))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_4_ "EU_CORE/eu_biu_dataout<4>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_es_4))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_4))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_4))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_4))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_4))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_4))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_4))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT52))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_4__SW0))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_4__))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_3_ "EU_CORE/eu_biu_dataout<3>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_es_3))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_3))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_3))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_3))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_3))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_3))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_3))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT91_renamed_322))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT81_renamed_323))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_3__SW0))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_3__))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT1))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_2_ "EU_CORE/eu_biu_dataout<2>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_es_2))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_2))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_2))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_2))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_2))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_2))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_2))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT81_renamed_323))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT71_renamed_324))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_2__SW0))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_2__))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_1_ "EU_CORE/eu_biu_dataout<1>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_es_1))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_1))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_1))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_1))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_1))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_1))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_1))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT71_renamed_324))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_1__SW0))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_1__))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT61))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_0_ "EU_CORE/eu_biu_dataout<0>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_es_0))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_0))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_0))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_0))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_0))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_0))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_0__SW0))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_0__))
+                (portRef I2 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT61))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT51))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_15_ "EU_CORE/eu_register_r3<15>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_15))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_15))
+                (portRef I1 (instanceRef EU_CORE_mux22_8_renamed_103))
+                (portRef I1 (instanceRef EU_CORE_mux6_8_renamed_198))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_14_ "EU_CORE/eu_register_r3<14>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_14))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_14))
+                (portRef I0 (instanceRef EU_CORE_mux21_8_renamed_107))
+                (portRef I1 (instanceRef EU_CORE_mux5_8_renamed_202))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_13_ "EU_CORE/eu_register_r3<13>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_13))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_13))
+                (portRef I1 (instanceRef EU_CORE_mux20_4_renamed_113))
+                (portRef I2 (instanceRef EU_CORE_mux4_4_renamed_203))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_12_ "EU_CORE/eu_register_r3<12>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_12))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_12))
+                (portRef I0 (instanceRef EU_CORE_mux19_4_renamed_119))
+                (portRef I1 (instanceRef EU_CORE_mux3_4_renamed_209))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_11_ "EU_CORE/eu_register_r3<11>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_11))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_11))
+                (portRef I2 (instanceRef EU_CORE_mux18_4_renamed_125))
+                (portRef I2 (instanceRef EU_CORE_mux2_4_renamed_225))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_10_ "EU_CORE/eu_register_r3<10>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_10))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_10))
+                (portRef I1 (instanceRef EU_CORE_mux17_8_renamed_134))
+                (portRef I1 (instanceRef EU_CORE_mux1_8_renamed_218))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_9_ "EU_CORE/eu_register_r3<9>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_9))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_9))
+                (portRef I1 (instanceRef EU_CORE_mux31_4_renamed_54))
+                (portRef I2 (instanceRef EU_CORE_mux15_4_renamed_135))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_8_ "EU_CORE/eu_register_r3<8>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_8))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_8))
+                (portRef I0 (instanceRef EU_CORE_mux30_4_renamed_72))
+                (portRef I1 (instanceRef EU_CORE_mux14_4_renamed_141))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_7_ "EU_CORE/eu_register_r3<7>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_7))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_7))
+                (portRef I0 (instanceRef EU_CORE_mux29_4_renamed_60))
+                (portRef I0 (instanceRef EU_CORE_mux13_4_renamed_153))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_6_ "EU_CORE/eu_register_r3<6>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_6))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_6))
+                (portRef I0 (instanceRef EU_CORE_mux28_4_renamed_66))
+                (portRef I0 (instanceRef EU_CORE_mux12_4_renamed_159))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_5_ "EU_CORE/eu_register_r3<5>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_5))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_5))
+                (portRef I0 (instanceRef EU_CORE_mux27_8_renamed_81))
+                (portRef I1 (instanceRef EU_CORE_mux11_4_renamed_165))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_4_ "EU_CORE/eu_register_r3<4>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_4))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_4))
+                (portRef I1 (instanceRef EU_CORE_mux26_4_renamed_82))
+                (portRef I1 (instanceRef EU_CORE_mux10_4_renamed_171))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_3_ "EU_CORE/eu_register_r3<3>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_3))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_3))
+                (portRef I1 (instanceRef EU_CORE_mux25_4_renamed_88))
+                (portRef I0 (instanceRef EU_CORE_mux9_4_renamed_189))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_2_ "EU_CORE/eu_register_r3<2>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_2))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_2))
+                (portRef I1 (instanceRef EU_CORE_mux24_4_renamed_94))
+                (portRef I0 (instanceRef EU_CORE_mux8_4_renamed_177))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_1_ "EU_CORE/eu_register_r3<1>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_1))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_1))
+                (portRef I0 (instanceRef EU_CORE_mux7_4_renamed_183))
+                (portRef I1 (instanceRef EU_CORE_mux23_4_renamed_380))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_0_ "EU_CORE/eu_register_r3<0>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_0))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_0))
+                (portRef I2 (instanceRef EU_CORE_mux16_4_renamed_147))
+                (portRef I1 (instanceRef EU_CORE_mux_4_renamed_219))
+              )
+            )
+            (net (rename EU_CORE_eu_flags_13_ "EU_CORE/eu_flags<13>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_flags_13))
+                (portRef I0 (instanceRef EU_CORE_mux20_5_renamed_114))
+              )
+            )
+            (net (rename EU_CORE_eu_flags_12_ "EU_CORE/eu_flags<12>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_flags_12))
+                (portRef I5 (instanceRef BIU_CORE_nmi_caught_glue_set_renamed_386))
+                (portRef I0 (instanceRef EU_CORE_mux19_5_renamed_120))
+              )
+            )
+            (net t_biu_ad_oe_d2
+              (joined
+                (portRef I (instanceRef SRAM_CE_n_OBUF))
+                (portRef I (instanceRef SRAM_OE_n_OBUF))
+                (portRef I (instanceRef SRAM_WE_n_OBUF))
+                (portRef I (instanceRef BUF2_DIR_OBUF))
+                (portRef I (instanceRef BUF2_DIR_inv1_INV_0))
+                (portRef Q (instanceRef t_biu_ad_oe_d2_renamed_406))
+              )
+            )
+            (net (rename t_biu_ad_out_d_19_ "t_biu_ad_out_d<19>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_19))
+                (portRef I (instanceRef A19_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_18_ "t_biu_ad_out_d<18>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_18))
+                (portRef I (instanceRef SRAM_A_18_OBUF))
+                (portRef I (instanceRef A18_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_17_ "t_biu_ad_out_d<17>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_17))
+                (portRef I (instanceRef SRAM_A_17_OBUF))
+                (portRef I (instanceRef A17_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_16_ "t_biu_ad_out_d<16>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_16))
+                (portRef I (instanceRef SRAM_A_16_OBUF))
+                (portRef I (instanceRef A16_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_15_ "t_biu_ad_out_d<15>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_15))
+                (portRef I (instanceRef SRAM_A_15_OBUF))
+                (portRef I (instanceRef A15_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_14_ "t_biu_ad_out_d<14>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_14))
+                (portRef I (instanceRef SRAM_A_14_OBUF))
+                (portRef I (instanceRef A14_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_13_ "t_biu_ad_out_d<13>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_13))
+                (portRef I (instanceRef SRAM_A_13_OBUF))
+                (portRef I (instanceRef A13_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_12_ "t_biu_ad_out_d<12>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_12))
+                (portRef I (instanceRef SRAM_A_12_OBUF))
+                (portRef I (instanceRef A12_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_11_ "t_biu_ad_out_d<11>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_11))
+                (portRef I (instanceRef SRAM_A_11_OBUF))
+                (portRef I (instanceRef A11_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_10_ "t_biu_ad_out_d<10>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_10))
+                (portRef I (instanceRef SRAM_A_10_OBUF))
+                (portRef I (instanceRef A10_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_9_ "t_biu_ad_out_d<9>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_9))
+                (portRef I (instanceRef SRAM_A_9_OBUF))
+                (portRef I (instanceRef A9_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_8_ "t_biu_ad_out_d<8>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_8))
+                (portRef I (instanceRef SRAM_A_8_OBUF))
+                (portRef I (instanceRef A8_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_7_ "t_biu_ad_out_d<7>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_7))
+                (portRef I (instanceRef SRAM_D_7_OBUF))
+                (portRef I (instanceRef SRAM_A_7_OBUF))
+                (portRef I (instanceRef LED_7_OBUF))
+                (portRef I (instanceRef AD7_IOBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_6_ "t_biu_ad_out_d<6>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_6))
+                (portRef I (instanceRef SRAM_D_6_OBUF))
+                (portRef I (instanceRef SRAM_A_6_OBUF))
+                (portRef I (instanceRef LED_6_OBUF))
+                (portRef I (instanceRef AD6_IOBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_5_ "t_biu_ad_out_d<5>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_5))
+                (portRef I (instanceRef SRAM_D_5_OBUF))
+                (portRef I (instanceRef SRAM_A_5_OBUF))
+                (portRef I (instanceRef LED_5_OBUF))
+                (portRef I (instanceRef AD5_IOBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_4_ "t_biu_ad_out_d<4>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_4))
+                (portRef I (instanceRef SRAM_D_4_OBUF))
+                (portRef I (instanceRef SRAM_A_4_OBUF))
+                (portRef I (instanceRef LED_4_OBUF))
+                (portRef I (instanceRef AD4_IOBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_3_ "t_biu_ad_out_d<3>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_3))
+                (portRef I (instanceRef SRAM_D_3_OBUF))
+                (portRef I (instanceRef SRAM_A_3_OBUF))
+                (portRef I (instanceRef LED_3_OBUF))
+                (portRef I (instanceRef AD3_IOBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_2_ "t_biu_ad_out_d<2>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_2))
+                (portRef I (instanceRef SRAM_D_2_OBUF))
+                (portRef I (instanceRef SRAM_A_2_OBUF))
+                (portRef I (instanceRef LED_2_OBUF))
+                (portRef I (instanceRef AD2_IOBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_1_ "t_biu_ad_out_d<1>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_1))
+                (portRef I (instanceRef SRAM_D_1_OBUF))
+                (portRef I (instanceRef SRAM_A_1_OBUF))
+                (portRef I (instanceRef LED_1_OBUF))
+                (portRef I (instanceRef AD1_IOBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_0_ "t_biu_ad_out_d<0>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_0))
+                (portRef I (instanceRef SRAM_D_0_OBUF))
+                (portRef I (instanceRef SRAM_A_0_OBUF))
+                (portRef I (instanceRef LED_0_OBUF))
+                (portRef I (instanceRef AD0_IOBUF))
+              )
+            )
+            (net t_reset_d2
+              (joined
+                (portRef D (instanceRef t_reset_d3_renamed_1))
+                (portRef I2 (instanceRef t_reset_d4_rstpot_renamed_402))
+                (portRef Q (instanceRef t_reset_d2_renamed_408))
+              )
+            )
+            (net t_reset_d3
+              (joined
+                (portRef Q (instanceRef t_reset_d3_renamed_1))
+                (portRef I0 (instanceRef t_reset_d4_rstpot_renamed_402))
+              )
+            )
+            (net t_reset_d4
+              (joined
+                (portRef R (instanceRef BIU_CORE_ad_in_int_0))
+                (portRef R (instanceRef BIU_CORE_ad_in_int_1))
+                (portRef R (instanceRef BIU_CORE_ad_in_int_2))
+                (portRef R (instanceRef BIU_CORE_ad_in_int_3))
+                (portRef R (instanceRef BIU_CORE_ad_in_int_4))
+                (portRef R (instanceRef BIU_CORE_ad_in_int_5))
+                (portRef R (instanceRef BIU_CORE_ad_in_int_6))
+                (portRef R (instanceRef BIU_CORE_ad_in_int_7))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_0))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_1))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_2))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_3))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_4))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_5))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_6))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_7))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_8))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_9))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_10))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_11))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_12))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_13))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_14))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_15))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_0))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_1))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_2))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_3))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_4))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_5))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_6))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_7))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_8))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_9))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_10))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_11))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_12))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_13))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_14))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_15))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_0))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_1))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_2))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_3))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_4))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_5))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_6))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_7))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_8))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_9))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_10))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_11))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_12))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_13))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_14))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_15))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_0))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_1))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_2))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_3))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_4))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_5))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_6))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_7))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_8))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_9))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_10))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_11))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_12))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_13))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_14))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_15))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_0))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_1))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_2))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_3))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_4))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_5))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_6))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_7))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_8))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_9))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_10))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_11))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_12))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_13))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_14))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_15))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_0))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_1))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_2))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_3))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_4))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_5))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_6))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_7))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_8))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_9))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_10))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_11))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_12))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_13))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_14))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_15))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_0))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_1))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_2))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_3))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_4))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_5))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_6))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_7))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_8))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_9))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_10))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_11))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_12))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_13))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_14))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_15))
+                (portRef R (instanceRef BIU_CORE_nmi_d1_renamed_53))
+                (portRef R (instanceRef BIU_CORE_pfq_write_renamed_52))
+                (portRef R (instanceRef BIU_CORE_biu_done_int_renamed_51))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_0))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_1))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_2))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_3))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_4))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_5))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_6))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_7))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_8))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_9))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_10))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_11))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_12))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_13))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_14))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_15))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_16))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_17))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_18))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_19))
+                (portRef R (instanceRef BIU_CORE_ready_d1_renamed_50))
+                (portRef R (instanceRef BIU_CORE_eu_biu_req_d1_renamed_49))
+                (portRef R (instanceRef BIU_CORE_byte_num_renamed_48))
+                (portRef R (instanceRef BIU_CORE_intr_d1_renamed_47))
+                (portRef R (instanceRef BIU_CORE_AD_OE_renamed_46))
+                (portRef R (instanceRef BIU_CORE_ale_int_renamed_45))
+                (portRef R (instanceRef BIU_CORE_clk_d1_renamed_44))
+                (portRef S (instanceRef BIU_CORE_inta_n_int_renamed_43))
+                (portRef S (instanceRef BIU_CORE_rd_n_int_renamed_42))
+                (portRef S (instanceRef BIU_CORE_wr_n_int_renamed_41))
+                (portRef S (instanceRef BIU_CORE_den_int_renamed_40))
+                (portRef R (instanceRef BIU_CORE_biu_state_0))
+                (portRef R (instanceRef BIU_CORE_biu_state_1))
+                (portRef R (instanceRef BIU_CORE_biu_state_2))
+                (portRef R (instanceRef BIU_CORE_biu_state_3))
+                (portRef S (instanceRef BIU_CORE_biu_state_4))
+                (portRef R (instanceRef BIU_CORE_biu_state_5))
+                (portRef S (instanceRef BIU_CORE_biu_state_6))
+                (portRef S (instanceRef BIU_CORE_biu_state_7))
+                (portRef R (instanceRef BIU_CORE_iom_int_renamed_39))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_0_renamed_38))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_1_renamed_37))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_2_renamed_36))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_3_renamed_35))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_4_renamed_34))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_5_renamed_33))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_6_renamed_32))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_7_renamed_31))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_8_renamed_30))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_9_renamed_29))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_10_renamed_28))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_11_renamed_27))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_12_renamed_26))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_13_renamed_25))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_14_renamed_24))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_15_renamed_23))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_16_renamed_22))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_17_renamed_21))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_18_renamed_20))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_19_renamed_19))
+                (portRef R (instanceRef BIU_CORE_clk_d2_renamed_18))
+                (portRef R (instanceRef BIU_CORE_nmi_d2_renamed_17))
+                (portRef R (instanceRef BIU_CORE_intr_d2_renamed_16))
+                (portRef R (instanceRef BIU_CORE_IOM_renamed_15))
+                (portRef S (instanceRef BIU_CORE_RD_n_renamed_14))
+                (portRef S (instanceRef BIU_CORE_INTA_n_renamed_13))
+                (portRef S (instanceRef BIU_CORE_WR_n_renamed_12))
+                (portRef S (instanceRef BIU_CORE_DEN_renamed_11))
+                (portRef R (instanceRef BIU_CORE_latched_data_in_0))
+                (portRef R (instanceRef BIU_CORE_latched_data_in_1))
+                (portRef R (instanceRef BIU_CORE_latched_data_in_2))
+                (portRef R (instanceRef BIU_CORE_latched_data_in_3))
+                (portRef R (instanceRef BIU_CORE_latched_data_in_4))
+                (portRef R (instanceRef BIU_CORE_latched_data_in_5))
+                (portRef R (instanceRef BIU_CORE_latched_data_in_6))
+                (portRef R (instanceRef BIU_CORE_latched_data_in_7))
+                (portRef R (instanceRef BIU_CORE_clk_d3_renamed_9))
+                (portRef R (instanceRef BIU_CORE_nmi_d3_renamed_8))
+                (portRef R (instanceRef BIU_CORE_intr_d3_renamed_7))
+                (portRef R (instanceRef BIU_CORE_pfq_entry0_0))
+                (portRef R (instanceRef BIU_CORE_pfq_entry0_1))
+                (portRef R (instanceRef BIU_CORE_pfq_entry0_2))
+                (portRef R (instanceRef BIU_CORE_pfq_entry0_3))
+                (portRef R (instanceRef BIU_CORE_pfq_entry0_4))
+                (portRef R (instanceRef BIU_CORE_pfq_entry0_5))
+                (portRef R (instanceRef BIU_CORE_pfq_entry0_6))
+                (portRef R (instanceRef BIU_CORE_pfq_entry0_7))
+                (portRef R (instanceRef BIU_CORE_pfq_entry1_0))
+                (portRef R (instanceRef BIU_CORE_pfq_entry1_1))
+                (portRef R (instanceRef BIU_CORE_pfq_entry1_2))
+                (portRef R (instanceRef BIU_CORE_pfq_entry1_3))
+                (portRef R (instanceRef BIU_CORE_pfq_entry1_4))
+                (portRef R (instanceRef BIU_CORE_pfq_entry1_5))
+                (portRef R (instanceRef BIU_CORE_pfq_entry1_6))
+                (portRef R (instanceRef BIU_CORE_pfq_entry1_7))
+                (portRef R (instanceRef BIU_CORE_pfq_entry2_0))
+                (portRef R (instanceRef BIU_CORE_pfq_entry2_1))
+                (portRef R (instanceRef BIU_CORE_pfq_entry2_2))
+                (portRef R (instanceRef BIU_CORE_pfq_entry2_3))
+                (portRef R (instanceRef BIU_CORE_pfq_entry2_4))
+                (portRef R (instanceRef BIU_CORE_pfq_entry2_5))
+                (portRef R (instanceRef BIU_CORE_pfq_entry2_6))
+                (portRef R (instanceRef BIU_CORE_pfq_entry2_7))
+                (portRef R (instanceRef BIU_CORE_pfq_entry3_0))
+                (portRef R (instanceRef BIU_CORE_pfq_entry3_1))
+                (portRef R (instanceRef BIU_CORE_pfq_entry3_2))
+                (portRef R (instanceRef BIU_CORE_pfq_entry3_3))
+                (portRef R (instanceRef BIU_CORE_pfq_entry3_4))
+                (portRef R (instanceRef BIU_CORE_pfq_entry3_5))
+                (portRef R (instanceRef BIU_CORE_pfq_entry3_6))
+                (portRef R (instanceRef BIU_CORE_pfq_entry3_7))
+                (portRef R (instanceRef BIU_CORE_clk_d4_renamed_6))
+                (portRef R (instanceRef BIU_CORE_nmi_d4_renamed_5))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_0))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_1))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_2))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_3))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_4))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_5))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_6))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_7))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_8))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_9))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_10))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_11))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_12))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_13))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_14))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_15))
+                (portRef S (instanceRef BIU_CORE_s_bits_0))
+                (portRef S (instanceRef BIU_CORE_s_bits_1))
+                (portRef S (instanceRef BIU_CORE_s_bits_2))
+                (portRef R (instanceRef BIU_CORE_nmi_d5_renamed_4))
+                (portRef R (instanceRef BIU_CORE_dtr_int_renamed_3))
+                (portRef R (instanceRef BIU_CORE_DTR_renamed_2))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_0))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_1))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_2))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_3))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_4))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_5))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_6))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_7))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_8))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_9))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_10))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_11))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_12))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_13))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_14))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_15))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_0))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_1))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_2))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_3))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_4))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_5))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_6))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_7))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_8))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_9))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_10))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_11))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_12))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_13))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_14))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_15))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_0))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_1))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_2))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_3))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_4))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_5))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_6))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_7))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_8))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_9))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_10))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_11))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_12))
+                (portRef R (instanceRef EU_CORE_biu_done_d1_renamed_239))
+                (portRef R (instanceRef EU_CORE_eu_stall_pipeline_renamed_238))
+                (portRef R (instanceRef EU_CORE_eu_add_aux_carry_renamed_237))
+                (portRef R (instanceRef EU_CORE_eu_add_carry_renamed_236))
+                (portRef R (instanceRef EU_CORE_eu_add_carry8_renamed_235))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_0))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_1))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_2))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_3))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_4))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_5))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_6))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_7))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_8))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_9))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_10))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_11))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_12))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_13))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_14))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_15))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_0))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_1))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_2))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_3))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_4))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_5))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_6))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_7))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_8))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_9))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_10))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_11))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_12))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_13))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_14))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_15))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_0))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_1))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_2))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_3))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_4))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_5))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_6))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_7))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_8))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_9))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_10))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_11))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_12))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_13))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_14))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_15))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_0))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_1))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_2))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_3))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_4))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_5))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_6))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_7))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_8))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_9))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_10))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_11))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_12))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_13))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_14))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_15))
+                (portRef R (instanceRef EU_CORE_eu_register_si_0))
+                (portRef R (instanceRef EU_CORE_eu_register_si_1))
+                (portRef R (instanceRef EU_CORE_eu_register_si_2))
+                (portRef R (instanceRef EU_CORE_eu_register_si_3))
+                (portRef R (instanceRef EU_CORE_eu_register_si_4))
+                (portRef R (instanceRef EU_CORE_eu_register_si_5))
+                (portRef R (instanceRef EU_CORE_eu_register_si_6))
+                (portRef R (instanceRef EU_CORE_eu_register_si_7))
+                (portRef R (instanceRef EU_CORE_eu_register_si_8))
+                (portRef R (instanceRef EU_CORE_eu_register_si_9))
+                (portRef R (instanceRef EU_CORE_eu_register_si_10))
+                (portRef R (instanceRef EU_CORE_eu_register_si_11))
+                (portRef R (instanceRef EU_CORE_eu_register_si_12))
+                (portRef R (instanceRef EU_CORE_eu_register_si_13))
+                (portRef R (instanceRef EU_CORE_eu_register_si_14))
+                (portRef R (instanceRef EU_CORE_eu_register_si_15))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_0))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_1))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_2))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_3))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_4))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_5))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_6))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_7))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_8))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_9))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_10))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_11))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_12))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_13))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_14))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_15))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_0))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_1))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_2))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_3))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_4))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_5))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_6))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_7))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_8))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_9))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_10))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_11))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_12))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_13))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_14))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_15))
+                (portRef R (instanceRef EU_CORE_eu_register_di_0))
+                (portRef R (instanceRef EU_CORE_eu_register_di_1))
+                (portRef R (instanceRef EU_CORE_eu_register_di_2))
+                (portRef R (instanceRef EU_CORE_eu_register_di_3))
+                (portRef R (instanceRef EU_CORE_eu_register_di_4))
+                (portRef R (instanceRef EU_CORE_eu_register_di_5))
+                (portRef R (instanceRef EU_CORE_eu_register_di_6))
+                (portRef R (instanceRef EU_CORE_eu_register_di_7))
+                (portRef R (instanceRef EU_CORE_eu_register_di_8))
+                (portRef R (instanceRef EU_CORE_eu_register_di_9))
+                (portRef R (instanceRef EU_CORE_eu_register_di_10))
+                (portRef R (instanceRef EU_CORE_eu_register_di_11))
+                (portRef R (instanceRef EU_CORE_eu_register_di_12))
+                (portRef R (instanceRef EU_CORE_eu_register_di_13))
+                (portRef R (instanceRef EU_CORE_eu_register_di_14))
+                (portRef R (instanceRef EU_CORE_eu_register_di_15))
+                (portRef R (instanceRef EU_CORE_eu_flags_0))
+                (portRef R (instanceRef EU_CORE_eu_flags_1))
+                (portRef R (instanceRef EU_CORE_eu_flags_2))
+                (portRef R (instanceRef EU_CORE_eu_flags_3))
+                (portRef R (instanceRef EU_CORE_eu_flags_4))
+                (portRef R (instanceRef EU_CORE_eu_flags_5))
+                (portRef R (instanceRef EU_CORE_eu_flags_6))
+                (portRef R (instanceRef EU_CORE_eu_flags_7))
+                (portRef R (instanceRef EU_CORE_eu_flags_8))
+                (portRef R (instanceRef EU_CORE_eu_flags_9))
+                (portRef R (instanceRef EU_CORE_eu_flags_10))
+                (portRef R (instanceRef EU_CORE_eu_flags_11))
+                (portRef R (instanceRef EU_CORE_eu_flags_12))
+                (portRef R (instanceRef EU_CORE_eu_flags_13))
+                (portRef R (instanceRef EU_CORE_eu_flags_14))
+                (portRef R (instanceRef EU_CORE_eu_flags_15))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_0))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_1))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_2))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_3))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_4))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_5))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_6))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_7))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_8))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_9))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_10))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_11))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_12))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_13))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_14))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_15))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_0))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_1))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_2))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_3))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_4))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_5))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_6))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_7))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_8))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_9))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_10))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_11))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_12))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_13))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_14))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_15))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_0))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_1))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_2))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_3))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_4))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_5))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_6))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_7))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_8))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_9))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_10))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_11))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_12))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_13))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_14))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_15))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_0))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_1))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_2))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_3))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_4))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_5))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_6))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_7))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_8))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_9))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_10))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_11))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_12))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_13))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_14))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_15))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_0))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_1))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_2))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_3))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_4))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_5))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_6))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_7))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_8))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_9))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_10))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_11))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_12))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_13))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_14))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_15))
+                (portRef R (instanceRef EU_CORE_biu_done_d2_renamed_234))
+                (portRef R (instanceRef EU_CORE_eu_flag_t_d_renamed_233))
+                (portRef R (instanceRef EU_CORE_eu_add_overflow16_renamed_232))
+                (portRef R (instanceRef EU_CORE_eu_add_overflow8_renamed_231))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_0))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_1))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_2))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_3))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_4))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_5))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_6))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_7))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_8))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_9))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_10))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_11))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_12))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_13))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_14))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_15))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_16))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_17))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_18))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_19))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_20))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_21))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_22))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_23))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_24))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_25))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_26))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_27))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_28))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_29))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_30))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_31))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_32))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_33))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_34))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_35))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_36))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_37))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_38))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_39))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_40))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_41))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_42))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_43))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_44))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_45))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_46))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_47))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_48))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_49))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_50))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_51))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_0))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_1))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_2))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_3))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_4))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_5))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_6))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_7))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_8))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_9))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_10))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_11))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_12))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_13))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_14))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_15))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_0))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_1))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_2))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_3))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_4))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_5))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_6))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_7))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_8))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_9))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_10))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_11))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_12))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_13))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_14))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_15))
+                (portRef R (instanceRef EU_CORE_eu_rom_address_0))
+                (portRef R (instanceRef EU_CORE_eu_rom_address_1))
+                (portRef R (instanceRef EU_CORE_eu_rom_address_2))
+                (portRef R (instanceRef EU_CORE_eu_rom_address_3))
+                (portRef R (instanceRef EU_CORE_eu_rom_address_4))
+                (portRef S (instanceRef EU_CORE_eu_rom_address_5))
+                (portRef R (instanceRef EU_CORE_eu_rom_address_6))
+                (portRef R (instanceRef EU_CORE_eu_rom_address_7))
+                (portRef R (instanceRef EU_CORE_eu_rom_address_8))
+                (portRef R (instanceRef EU_CORE_eu_rom_address_9))
+                (portRef R (instanceRef EU_CORE_eu_rom_address_12))
+                (portRef R (instanceRef EU_CORE_eu_rom_address_10))
+                (portRef R (instanceRef EU_CORE_eu_rom_address_11))
+                (portRef R (instanceRef BIU_CORE_eu_biu_req_caught_renamed_345))
+                (portRef R (instanceRef BIU_CORE_nmi_caught_renamed_346))
+                (portRef R (instanceRef EU_CORE_eu_tr_latched_renamed_347))
+                (portRef R (instanceRef EU_CORE_biu_done_caught_renamed_348))
+                (portRef R (instanceRef BIU_CORE_BIU_INTR_renamed_376))
+                (portRef Q (instanceRef t_reset_d4_renamed_377))
+                (portRef I0 (instanceRef BIU_CORE_word_cycle_rstpot1_renamed_383))
+                (portRef I1 (instanceRef EU_CORE_intr_enable_delayed_rstpot1_renamed_384))
+                (portRef I1 (instanceRef t_reset_d4_rstpot_renamed_402))
+                (portRef I (instanceRef BIU_CORE_RESET_INT_inv1_INV_0))
+              )
+            )
+            (net AD7
+              (joined
+                (portRef AD7)
+                (portRef IO (instanceRef AD7_IOBUF))
+              )
+            )
+            (net AD6
+              (joined
+                (portRef AD6)
+                (portRef IO (instanceRef AD6_IOBUF))
+              )
+            )
+            (net AD5
+              (joined
+                (portRef AD5)
+                (portRef IO (instanceRef AD5_IOBUF))
+              )
+            )
+            (net AD4
+              (joined
+                (portRef AD4)
+                (portRef IO (instanceRef AD4_IOBUF))
+              )
+            )
+            (net AD3
+              (joined
+                (portRef AD3)
+                (portRef IO (instanceRef AD3_IOBUF))
+              )
+            )
+            (net AD2
+              (joined
+                (portRef AD2)
+                (portRef IO (instanceRef AD2_IOBUF))
+              )
+            )
+            (net AD1
+              (joined
+                (portRef AD1)
+                (portRef IO (instanceRef AD1_IOBUF))
+              )
+            )
+            (net AD0
+              (joined
+                (portRef AD0)
+                (portRef IO (instanceRef AD0_IOBUF))
+              )
+            )
+            (net N0
+              (joined
+                (portRef P (instanceRef XST_VCC))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_0__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_1__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_2__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_3__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_4__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_5__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_6__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_7__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_8__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_9__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_10__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_11__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_0__))
+                (portRef CE (instanceRef Mshreg_t_biu_ad_oe_d2_renamed_405))
+                (portRef CE (instanceRef t_biu_ad_oe_d2_renamed_406))
+                (portRef CE (instanceRef Mshreg_t_reset_d2_renamed_407))
+                (portRef CE (instanceRef t_reset_d2_renamed_408))
+              )
+            )
+            (net N1
+              (joined
+                (portRef G (instanceRef XST_GND))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_0__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_1__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_2__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_3__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_4__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_5__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_6__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_7__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_8__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_9__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_10__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_11__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_12__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_13__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_14__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_0__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_1__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_2__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_3__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_4__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_5__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_6__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_7__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_8__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_9__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_10__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_11__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_12__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_13__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_4__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_16__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_17__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_4__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_16__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_17__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_4__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_16__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_17__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_0__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_0__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_1__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_2__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_3__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_4__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_5__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_6__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_7__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_8__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_9__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_10__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_11__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_12__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_13__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_4__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_16__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_17__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_18__))
+                (portRef DI (instanceRef EU_CORE_Mcount_eu_rom_address_cy_0__))
+                (portRef DI (instanceRef EU_CORE_Mcount_eu_rom_address_cy_1__))
+                (portRef DI (instanceRef EU_CORE_Mcount_eu_rom_address_cy_2__))
+                (portRef DI (instanceRef EU_CORE_Mcount_eu_rom_address_cy_3__))
+                (portRef DI (instanceRef EU_CORE_Mcount_eu_rom_address_cy_4__))
+                (portRef DI (instanceRef EU_CORE_Mcount_eu_rom_address_cy_5__))
+                (portRef DI (instanceRef EU_CORE_Mcount_eu_rom_address_cy_6__))
+                (portRef DI (instanceRef EU_CORE_Mcount_eu_rom_address_cy_7__))
+                (portRef DI (instanceRef EU_CORE_Mcount_eu_rom_address_cy_8__))
+                (portRef DI (instanceRef EU_CORE_Mcount_eu_rom_address_cy_9__))
+                (portRef DI (instanceRef EU_CORE_Mcount_eu_rom_address_cy_10__))
+                (portRef DI (instanceRef EU_CORE_Mcount_eu_rom_address_cy_11__))
+                (portRef A0 (instanceRef Mshreg_t_biu_ad_oe_d2_renamed_405))
+                (portRef A1 (instanceRef Mshreg_t_biu_ad_oe_d2_renamed_405))
+                (portRef A2 (instanceRef Mshreg_t_biu_ad_oe_d2_renamed_405))
+                (portRef A3 (instanceRef Mshreg_t_biu_ad_oe_d2_renamed_405))
+                (portRef A0 (instanceRef Mshreg_t_reset_d2_renamed_407))
+                (portRef A1 (instanceRef Mshreg_t_reset_d2_renamed_407))
+                (portRef A2 (instanceRef Mshreg_t_reset_d2_renamed_407))
+                (portRef A3 (instanceRef Mshreg_t_reset_d2_renamed_407))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_15_renamed_409))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_15_renamed_409))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_15_renamed_409))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_15_renamed_409))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_14_renamed_410))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_14_renamed_410))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_14_renamed_410))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_14_renamed_410))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_13_renamed_411))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_13_renamed_411))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_13_renamed_411))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_13_renamed_411))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_12_renamed_412))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_12_renamed_412))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_12_renamed_412))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_12_renamed_412))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_11_renamed_413))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_11_renamed_413))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_11_renamed_413))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_11_renamed_413))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_10_renamed_414))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_10_renamed_414))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_10_renamed_414))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_10_renamed_414))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_9_renamed_415))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_9_renamed_415))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_9_renamed_415))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_9_renamed_415))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_8_renamed_416))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_8_renamed_416))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_8_renamed_416))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_8_renamed_416))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_7_renamed_417))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_7_renamed_417))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_7_renamed_417))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_7_renamed_417))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_6_renamed_418))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_6_renamed_418))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_6_renamed_418))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_6_renamed_418))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_3_renamed_419))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_3_renamed_419))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_3_renamed_419))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_3_renamed_419))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_5_renamed_420))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_5_renamed_420))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_5_renamed_420))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_5_renamed_420))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_4_renamed_421))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_4_renamed_421))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_4_renamed_421))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_4_renamed_421))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_2_renamed_422))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_2_renamed_422))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_2_renamed_422))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_2_renamed_422))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_1_renamed_423))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_1_renamed_423))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_1_renamed_423))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_1_renamed_423))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_0_renamed_424))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_0_renamed_424))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_0_renamed_424))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_0_renamed_424))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_15_renamed_425))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_15_renamed_425))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_15_renamed_425))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_15_renamed_425))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_12_renamed_426))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_12_renamed_426))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_12_renamed_426))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_12_renamed_426))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_14_renamed_427))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_14_renamed_427))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_14_renamed_427))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_14_renamed_427))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_13_renamed_428))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_13_renamed_428))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_13_renamed_428))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_13_renamed_428))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_11_renamed_429))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_11_renamed_429))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_11_renamed_429))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_11_renamed_429))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_10_renamed_430))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_10_renamed_430))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_10_renamed_430))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_10_renamed_430))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_9_renamed_431))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_9_renamed_431))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_9_renamed_431))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_9_renamed_431))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_8_renamed_432))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_8_renamed_432))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_8_renamed_432))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_8_renamed_432))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_5_renamed_433))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_5_renamed_433))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_5_renamed_433))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_5_renamed_433))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_7_renamed_434))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_7_renamed_434))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_7_renamed_434))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_7_renamed_434))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_6_renamed_435))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_6_renamed_435))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_6_renamed_435))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_6_renamed_435))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_4_renamed_436))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_4_renamed_436))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_4_renamed_436))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_4_renamed_436))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_3_renamed_437))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_3_renamed_437))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_3_renamed_437))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_3_renamed_437))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_2_renamed_438))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_2_renamed_438))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_2_renamed_438))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_2_renamed_438))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_1_renamed_439))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_1_renamed_439))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_1_renamed_439))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_1_renamed_439))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_14_renamed_440))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_14_renamed_440))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_14_renamed_440))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_14_renamed_440))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_0_renamed_441))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_0_renamed_441))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_0_renamed_441))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_0_renamed_441))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_15_renamed_442))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_15_renamed_442))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_15_renamed_442))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_15_renamed_442))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_13_renamed_443))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_13_renamed_443))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_13_renamed_443))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_13_renamed_443))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_12_renamed_444))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_12_renamed_444))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_12_renamed_444))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_12_renamed_444))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_11_renamed_445))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_11_renamed_445))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_11_renamed_445))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_11_renamed_445))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_10_renamed_446))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_10_renamed_446))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_10_renamed_446))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_10_renamed_446))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_7_renamed_447))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_7_renamed_447))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_7_renamed_447))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_7_renamed_447))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_9_renamed_448))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_9_renamed_448))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_9_renamed_448))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_9_renamed_448))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_8_renamed_449))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_8_renamed_449))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_8_renamed_449))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_8_renamed_449))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_6_renamed_450))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_6_renamed_450))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_6_renamed_450))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_6_renamed_450))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_5_renamed_451))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_5_renamed_451))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_5_renamed_451))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_5_renamed_451))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_4_renamed_452))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_4_renamed_452))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_4_renamed_452))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_4_renamed_452))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_3_renamed_453))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_3_renamed_453))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_3_renamed_453))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_3_renamed_453))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_0_renamed_454))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_0_renamed_454))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_0_renamed_454))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_0_renamed_454))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_2_renamed_455))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_2_renamed_455))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_2_renamed_455))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_2_renamed_455))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_1_renamed_456))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_1_renamed_456))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_1_renamed_456))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_1_renamed_456))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_15_renamed_457))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_15_renamed_457))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_15_renamed_457))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_15_renamed_457))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_14_renamed_458))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_14_renamed_458))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_14_renamed_458))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_14_renamed_458))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_13_renamed_459))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_13_renamed_459))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_13_renamed_459))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_13_renamed_459))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_12_renamed_460))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_12_renamed_460))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_12_renamed_460))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_12_renamed_460))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_9_renamed_461))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_9_renamed_461))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_9_renamed_461))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_9_renamed_461))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_11_renamed_462))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_11_renamed_462))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_11_renamed_462))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_11_renamed_462))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_10_renamed_463))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_10_renamed_463))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_10_renamed_463))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_10_renamed_463))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_8_renamed_464))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_8_renamed_464))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_8_renamed_464))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_8_renamed_464))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_7_renamed_465))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_7_renamed_465))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_7_renamed_465))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_7_renamed_465))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_6_renamed_466))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_6_renamed_466))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_6_renamed_466))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_6_renamed_466))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_5_renamed_467))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_5_renamed_467))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_5_renamed_467))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_5_renamed_467))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_4_renamed_468))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_4_renamed_468))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_4_renamed_468))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_4_renamed_468))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_3_renamed_469))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_3_renamed_469))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_3_renamed_469))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_3_renamed_469))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_2_renamed_470))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_2_renamed_470))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_2_renamed_470))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_2_renamed_470))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_1_renamed_471))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_1_renamed_471))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_1_renamed_471))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_1_renamed_471))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_0_renamed_472))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_0_renamed_472))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_0_renamed_472))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_0_renamed_472))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_15_renamed_473))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_15_renamed_473))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_15_renamed_473))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_15_renamed_473))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_14_renamed_474))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_14_renamed_474))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_14_renamed_474))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_14_renamed_474))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_13_renamed_475))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_13_renamed_475))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_13_renamed_475))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_13_renamed_475))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_10_renamed_476))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_10_renamed_476))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_10_renamed_476))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_10_renamed_476))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_12_renamed_477))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_12_renamed_477))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_12_renamed_477))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_12_renamed_477))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_11_renamed_478))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_11_renamed_478))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_11_renamed_478))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_11_renamed_478))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_9_renamed_479))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_9_renamed_479))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_9_renamed_479))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_9_renamed_479))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_8_renamed_480))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_8_renamed_480))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_8_renamed_480))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_8_renamed_480))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_7_renamed_481))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_7_renamed_481))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_7_renamed_481))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_7_renamed_481))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_6_renamed_482))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_6_renamed_482))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_6_renamed_482))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_6_renamed_482))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_3_renamed_483))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_3_renamed_483))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_3_renamed_483))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_3_renamed_483))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_5_renamed_484))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_5_renamed_484))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_5_renamed_484))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_5_renamed_484))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_4_renamed_485))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_4_renamed_485))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_4_renamed_485))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_4_renamed_485))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_2_renamed_486))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_2_renamed_486))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_2_renamed_486))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_2_renamed_486))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_1_renamed_487))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_1_renamed_487))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_1_renamed_487))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_1_renamed_487))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_0_renamed_488))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_0_renamed_488))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_0_renamed_488))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_0_renamed_488))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_15_renamed_489))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_15_renamed_489))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_15_renamed_489))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_15_renamed_489))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_12_renamed_490))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_12_renamed_490))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_12_renamed_490))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_12_renamed_490))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_14_renamed_491))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_14_renamed_491))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_14_renamed_491))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_14_renamed_491))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_13_renamed_492))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_13_renamed_492))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_13_renamed_492))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_13_renamed_492))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_11_renamed_493))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_11_renamed_493))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_11_renamed_493))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_11_renamed_493))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_10_renamed_494))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_10_renamed_494))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_10_renamed_494))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_10_renamed_494))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_9_renamed_495))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_9_renamed_495))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_9_renamed_495))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_9_renamed_495))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_8_renamed_496))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_8_renamed_496))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_8_renamed_496))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_8_renamed_496))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_5_renamed_497))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_5_renamed_497))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_5_renamed_497))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_5_renamed_497))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_7_renamed_498))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_7_renamed_498))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_7_renamed_498))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_7_renamed_498))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_6_renamed_499))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_6_renamed_499))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_6_renamed_499))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_6_renamed_499))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_4_renamed_500))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_4_renamed_500))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_4_renamed_500))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_4_renamed_500))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_3_renamed_501))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_3_renamed_501))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_3_renamed_501))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_3_renamed_501))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_2_renamed_502))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_2_renamed_502))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_2_renamed_502))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_2_renamed_502))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_1_renamed_503))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_1_renamed_503))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_1_renamed_503))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_1_renamed_503))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_14_renamed_504))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_14_renamed_504))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_14_renamed_504))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_14_renamed_504))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_0_renamed_505))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_0_renamed_505))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_0_renamed_505))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_0_renamed_505))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_15_renamed_506))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_15_renamed_506))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_15_renamed_506))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_15_renamed_506))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_13_renamed_507))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_13_renamed_507))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_13_renamed_507))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_13_renamed_507))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_12_renamed_508))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_12_renamed_508))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_12_renamed_508))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_12_renamed_508))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_11_renamed_509))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_11_renamed_509))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_11_renamed_509))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_11_renamed_509))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_10_renamed_510))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_10_renamed_510))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_10_renamed_510))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_10_renamed_510))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_7_renamed_511))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_7_renamed_511))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_7_renamed_511))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_7_renamed_511))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_9_renamed_512))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_9_renamed_512))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_9_renamed_512))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_9_renamed_512))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_8_renamed_513))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_8_renamed_513))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_8_renamed_513))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_8_renamed_513))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_6_renamed_514))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_6_renamed_514))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_6_renamed_514))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_6_renamed_514))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_5_renamed_515))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_5_renamed_515))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_5_renamed_515))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_5_renamed_515))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_4_renamed_516))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_4_renamed_516))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_4_renamed_516))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_4_renamed_516))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_3_renamed_517))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_3_renamed_517))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_3_renamed_517))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_3_renamed_517))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_0_renamed_518))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_0_renamed_518))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_0_renamed_518))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_0_renamed_518))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_2_renamed_519))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_2_renamed_519))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_2_renamed_519))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_2_renamed_519))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_1_renamed_520))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_1_renamed_520))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_1_renamed_520))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_1_renamed_520))
+              )
+            )
+            (net BUF2_DIR_inv
+              (joined
+                (portRef I (instanceRef BUF1_OE_n_OBUF))
+                (portRef I (instanceRef BUF2_OE_n_OBUF))
+                (portRef O (instanceRef BUF2_DIR_inv1_INV_0))
+                (portRef T (instanceRef AD7_IOBUF))
+                (portRef T (instanceRef AD6_IOBUF))
+                (portRef T (instanceRef AD5_IOBUF))
+                (portRef T (instanceRef AD4_IOBUF))
+                (portRef T (instanceRef AD3_IOBUF))
+                (portRef T (instanceRef AD2_IOBUF))
+                (portRef T (instanceRef AD1_IOBUF))
+                (portRef T (instanceRef AD0_IOBUF))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_12 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<5>12")
+              (joined
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW2))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_7_1))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_3_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW2))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_1))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_12_renamed_388))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__biu_done_int_Select_169_o2 "BIU_CORE/biu_state[7]_biu_done_int_Select_169_o2")
+              (joined
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o1_renamed_243))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_6_1_renamed_257))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o2_renamed_259))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_2_1))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<0>2")
+              (joined
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_4))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_4))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_4))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_4_renamed_256))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_21))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<10>3")
+              (joined
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_5))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_5))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_5))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_5))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_5))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_5))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_5))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_5))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_5))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_5))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_5))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_5_renamed_304))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_31))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_3))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_3))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_3))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_11 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<5>11")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_111))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_7_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_3_1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW2))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_equal_150_o_7_1 "BIU_CORE/biu_state[7]_GND_10_o_equal_150_o<7>1")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_150_o_7_2))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_151_o_7_1))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_150_o_7_11))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1111_renamed_381))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_159_o_7_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_equal_157_o_7_1 "BIU_CORE/biu_state[7]_GND_10_o_equal_157_o<7>1")
+              (joined
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__ale_int_Select_176_o1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o3_renamed_244))
+                (portRef I2 (instanceRef BIU_CORE__n0988_renamed_245))
+                (portRef I0 (instanceRef BIU_CORE__n09782_renamed_247))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_157_o_7_1_renamed_267))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o113))
+                (portRef I2 (instanceRef BIU_CORE_out21))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o112))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1113))
+                (portRef I0 (instanceRef BIU_CORE__n10044_SW0))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_equal_152_o_7_1 "BIU_CORE/biu_state[7]_GND_10_o_equal_152_o<7>1")
+              (joined
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o111))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_154_o_7_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_153_o_7_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_152_o_7_2))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_152_o_7_11))
+                (portRef I0 (instanceRef BIU_CORE__n10042_renamed_305))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW3))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1111_renamed_381))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_equal_146_o_7_1 "BIU_CORE/biu_state[7]_GND_10_o_equal_146_o<7>1")
+              (joined
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_146_o_7_2))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_148_o_7_1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_111))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_147_o_7_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_156_o_7_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_155_o_7_1))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_146_o_7_11))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_6_1_renamed_257))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o112_renamed_306))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW2))
+                (portRef I0 (instanceRef BIU_CORE__n10044))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o112_SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_12_renamed_388))
+                (portRef I3 (instanceRef BIU_CORE__n0897_inv1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_174_o_SW0))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_21))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1112_renamed_266))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<10>2")
+              (joined
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_4))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_4))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_4))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_4_renamed_256))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_2_renamed_308))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_2_renamed_310))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_2_renamed_312))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_2_renamed_314))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_21))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_Select_163_o111 "BIU_CORE/biu_state[7]_GND_10_o_Select_163_o111")
+              (joined
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o111))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1113))
+                (portRef I4 (instanceRef BIU_CORE_out21))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o112))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__den_int_Select_178_o11 "BIU_CORE/biu_state[7]_den_int_Select_178_o11")
+              (joined
+                (portRef I2 (instanceRef BIU_CORE_out91))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_174_o_renamed_265))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o113))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o_renamed_315))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__biu_done_int_Select_169_o11 "BIU_CORE/biu_state[7]_biu_done_int_Select_169_o11")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__ale_int_Select_176_o1))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o111))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_Select_163_o11 "BIU_CORE/biu_state[7]_GND_10_o_Select_163_o11")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o112))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_161_o_renamed_263))
+                (portRef I5 (instanceRef BIU_CORE__n10044_SW0))
+              )
+            )
+            (net (rename BIU_CORE__n0929_0_1 "BIU_CORE/_n0929<0>1")
+              (joined
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_1_renamed_307))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_1_renamed_309))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_1_renamed_311))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_1_renamed_313))
+                (portRef O (instanceRef BIU_CORE__n0929_0_11))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_18_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<18>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_19__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_17_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<17>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_17__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_18__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_16_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<16>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_16__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_17__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_17__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_15_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_15__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_16__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_16__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_15_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_15__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_15__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_14_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_15__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_14_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_14__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_14__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_13_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_13_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_13__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_13__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_12_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_12_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_12__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_12__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_11_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_11_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_11__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_11__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_10_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_10_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_10__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_10__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_9_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_9_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_9__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_9__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_8_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_8_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_8__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_8__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_7_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_7_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_7__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_7__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_6_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_6_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_6__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_6__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_5_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_5_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_5__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_5__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_4_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_cy<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_4_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_10_o_add_90_OUT_lut<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_4__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_4__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_14_ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_13_ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_12_ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_11_ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_10_ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_9_ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_8_ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_7_ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_6_ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_5_ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_4_ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_3_ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<3>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_3__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_2_ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<2>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_2__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_3__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_3__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_1_ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<1>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_1__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_2__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_2__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_0_ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<0>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_0__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_1__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_1__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_lut_0_ "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_lut<0>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_0__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_0__))
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_lut_0__INV_0))
+              )
+            )
+            (net (rename BIU_CORE_n00331 "BIU_CORE/n00331")
+              (joined
+                (portRef O (instanceRef BIU_CORE_n00331_renamed_240))
+                (portRef I3 (instanceRef BIU_CORE__n0910_inv_renamed_258))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_18_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<18>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_19__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_17_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<17>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_17__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_18__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_16_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<16>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_16__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_17__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_17__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_15_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_15__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_16__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_16__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_15_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_15__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_15__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_14_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_15__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_14_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_14__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_14__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_13_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_13_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_13__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_13__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_12_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_12_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_12__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_12__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_11_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_11_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_11__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_11__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_10_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_10_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_10__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_10__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_9_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_9_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_9__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_9__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_8_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_8_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_8__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_8__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_7_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_7_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_7__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_7__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_6_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_6_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_6__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_6__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_5_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_5_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_5__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_5__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_4_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_4_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_lut<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_4__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_4__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_18_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<18>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_19__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_17_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<17>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_17__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_18__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_16_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<16>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_16__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_17__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_17__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_15_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_15__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_16__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_16__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_15_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_15__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_15__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_14_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_15__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_14_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_14__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_14__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_13_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_13_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_13__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_13__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_12_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_12_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_12__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_12__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_11_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_11_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_11__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_11__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_10_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_10_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_10__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_10__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_9_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_9_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_9__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_9__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_8_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_8_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_8__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_8__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_7_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_7_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_7__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_7__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_6_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_6_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_6__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_6__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_5_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_5_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_5__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_5__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_4_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_4_ "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_lut<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_4__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_4__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_18_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<18>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_19__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_17_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<17>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_17__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_18__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_16_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<16>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_16__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_17__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_17__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_15_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_15__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_16__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_16__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_15_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_15__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_15__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_14_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_15__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_14_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_14__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_14__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_13_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_13_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_13__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_13__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_12_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_12_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_12__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_12__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_11_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_11_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_11__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_11__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_10_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_10_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_10__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_10__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_9_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_9_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_9__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_9__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_8_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_8_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_8__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_8__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_7_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_7_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_7__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_7__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_6_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_6_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_6__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_6__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_5_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_5_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_5__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_5__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_4_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_4_ "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_lut<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_4__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_4__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7_ "BIU_CORE/biu_state<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_state_7))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_149_o_7__SW0))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_157_o_7_1_renamed_267))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_150_o_7_11))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_152_o_7_11))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_146_o_7_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_6_ "BIU_CORE/biu_state<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_state_6))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_150_o_7_2))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_146_o_7_2))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_148_o_7_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_111))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_151_o_7_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_147_o_7_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_156_o_7_1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_155_o_7_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_6_1_renamed_257))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_149_o_7__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_157_o_7_1_renamed_267))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o112_renamed_306))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_6_2))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_150_o_7_2_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW0))
+                (portRef I2 (instanceRef BIU_CORE__n10044))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o112_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_12_renamed_388))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW0))
+                (portRef I2 (instanceRef BIU_CORE__n0897_inv1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_174_o_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_21))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_159_o_7_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_152_o_7_11))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1112_renamed_266))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_5_ "BIU_CORE/biu_state<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_state_5))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_150_o_7_2))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_151_o_7_1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_149_o_7__SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_157_o_7_1_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_6_2))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_150_o_7_2_SW0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5__SW0_SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_159_o_7_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_152_o_7_11))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_146_o_7_11))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_state_7__GND_10_o_add_87_OUT_cy_4_ "BIU_CORE/Madd_biu_state[7]_GND_10_o_add_87_OUT_cy<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_state_7__GND_10_o_add_87_OUT_cy_4_11))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_6_2))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW0))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_4_ "BIU_CORE/biu_state<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_state_4))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_state_7__GND_10_o_add_87_OUT_cy_4_11))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_150_o_7_2))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_151_o_7_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_146_o_7_11))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_149_o_7__SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_157_o_7_1_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_150_o_7_2_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5__SW0_SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_159_o_7_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_152_o_7_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_3_ "BIU_CORE/biu_state<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_state_3))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__ale_int_Select_176_o1))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_state_7__GND_10_o_add_87_OUT_cy_4_11))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o111))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_154_o_7_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_153_o_7_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_152_o_7_2))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o3_renamed_244))
+                (portRef I3 (instanceRef BIU_CORE__n0988_renamed_245))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4__SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_149_o_7__))
+                (portRef I2 (instanceRef BIU_CORE__n10042_renamed_305))
+                (portRef I3 (instanceRef BIU_CORE_out21))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5__SW0_SW0))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW3))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o112))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_150_o_7_11))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_146_o_7_11))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1113))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1111_renamed_381))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_2_ "BIU_CORE/biu_state<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_state_2))
+                (portRef I2 (instanceRef BIU_CORE_Madd_biu_state_7__GND_10_o_add_87_OUT_cy_4_11))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_146_o_7_2))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_148_o_7_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_111))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_152_o_7_11))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_147_o_7_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_156_o_7_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_155_o_7_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_6_1_renamed_257))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4__SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_149_o_7__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_157_o_7_1_renamed_267))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o112_renamed_306))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_2_1))
+                (portRef I1 (instanceRef BIU_CORE__n10044))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_12_renamed_388))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW0))
+                (portRef I0 (instanceRef BIU_CORE__n0897_inv1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5__SW0_SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_174_o_SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_21))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_150_o_7_11))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1112_renamed_266))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_1_ "BIU_CORE/biu_state<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_state_1))
+                (portRef I3 (instanceRef BIU_CORE_Madd_biu_state_7__GND_10_o_add_87_OUT_cy_4_11))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o111))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_154_o_7_1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_153_o_7_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_152_o_7_2))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4__SW0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_149_o_7__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_157_o_7_1_renamed_267))
+                (portRef I1 (instanceRef BIU_CORE__n10042_renamed_305))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_2_1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5__SW0_SW0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW3))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_150_o_7_11))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_146_o_7_11))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1111_renamed_381))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_0_ "BIU_CORE/biu_state<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_state_0))
+                (portRef I4 (instanceRef BIU_CORE_Madd_biu_state_7__GND_10_o_add_87_OUT_cy_4_11))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_150_o_7_2))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_146_o_7_2))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_148_o_7_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_111))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o111))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_151_o_7_1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_154_o_7_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_153_o_7_1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_152_o_7_2))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_147_o_7_1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_156_o_7_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_155_o_7_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_6_1_renamed_257))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4__SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_1_renamed_260))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_149_o_7__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_157_o_7_1_renamed_267))
+                (portRef I3 (instanceRef BIU_CORE__n10042_renamed_305))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o112_renamed_306))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW2))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW1))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_2_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_1))
+                (portRef I3 (instanceRef BIU_CORE__n10044))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o112_SW0))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_12_renamed_388))
+                (portRef I1 (instanceRef BIU_CORE__n0897_inv1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5__SW0_SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_4))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_174_o_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW3))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_21))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_159_o_7_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1112_renamed_266))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1111_renamed_381))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_15_ "BIU_CORE/Mcount_pfq_addr_out_lut<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_15__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out15 "BIU_CORE/Mcount_pfq_addr_out15")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_15__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_15))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_14_ "BIU_CORE/Mcount_pfq_addr_out_cy<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_14_ "BIU_CORE/Mcount_pfq_addr_out_lut<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_14__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_14__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out14 "BIU_CORE/Mcount_pfq_addr_out14")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_14__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_14))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_13_ "BIU_CORE/Mcount_pfq_addr_out_cy<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_13_ "BIU_CORE/Mcount_pfq_addr_out_lut<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_13__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_13__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out13 "BIU_CORE/Mcount_pfq_addr_out13")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_13__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_13))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_12_ "BIU_CORE/Mcount_pfq_addr_out_cy<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_12_ "BIU_CORE/Mcount_pfq_addr_out_lut<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_12__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_12__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out12 "BIU_CORE/Mcount_pfq_addr_out12")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_12__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_12))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_11_ "BIU_CORE/Mcount_pfq_addr_out_cy<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_11_ "BIU_CORE/Mcount_pfq_addr_out_lut<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_11__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_11__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out11 "BIU_CORE/Mcount_pfq_addr_out11")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_11__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_11))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_10_ "BIU_CORE/Mcount_pfq_addr_out_cy<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_10_ "BIU_CORE/Mcount_pfq_addr_out_lut<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_10__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_10__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out10 "BIU_CORE/Mcount_pfq_addr_out10")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_10__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_10))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_9_ "BIU_CORE/Mcount_pfq_addr_out_cy<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_9_ "BIU_CORE/Mcount_pfq_addr_out_lut<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_9__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_9__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out9 "BIU_CORE/Mcount_pfq_addr_out9")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_9__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_9))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_8_ "BIU_CORE/Mcount_pfq_addr_out_cy<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_8_ "BIU_CORE/Mcount_pfq_addr_out_lut<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_8__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_8__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out8 "BIU_CORE/Mcount_pfq_addr_out8")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_8__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_8))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_7_ "BIU_CORE/Mcount_pfq_addr_out_cy<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_7_ "BIU_CORE/Mcount_pfq_addr_out_lut<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_7__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_7__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out7 "BIU_CORE/Mcount_pfq_addr_out7")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_7__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_7))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_6_ "BIU_CORE/Mcount_pfq_addr_out_cy<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_6_ "BIU_CORE/Mcount_pfq_addr_out_lut<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_6__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_6__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out6 "BIU_CORE/Mcount_pfq_addr_out6")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_6__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_6))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_5_ "BIU_CORE/Mcount_pfq_addr_out_cy<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_5_ "BIU_CORE/Mcount_pfq_addr_out_lut<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_5__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_5__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out5 "BIU_CORE/Mcount_pfq_addr_out5")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_5__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_5))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_4_ "BIU_CORE/Mcount_pfq_addr_out_cy<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_4_ "BIU_CORE/Mcount_pfq_addr_out_lut<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_4__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_4__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out4 "BIU_CORE/Mcount_pfq_addr_out4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_4__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_4))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_3_ "BIU_CORE/Mcount_pfq_addr_out_cy<3>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_3__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_3_ "BIU_CORE/Mcount_pfq_addr_out_lut<3>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_3__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_3__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_3__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out3 "BIU_CORE/Mcount_pfq_addr_out3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_3__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_3))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_2_ "BIU_CORE/Mcount_pfq_addr_out_cy<2>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_2__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_3__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_3__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_2_ "BIU_CORE/Mcount_pfq_addr_out_lut<2>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_2__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_2__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_2__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out2 "BIU_CORE/Mcount_pfq_addr_out2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_2__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_2))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_1_ "BIU_CORE/Mcount_pfq_addr_out_cy<1>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_1__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_2__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_2__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_1_ "BIU_CORE/Mcount_pfq_addr_out_lut<1>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_1__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_1__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_1__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out1 "BIU_CORE/Mcount_pfq_addr_out1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_1__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_1))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_0_ "BIU_CORE/Mcount_pfq_addr_out_cy<0>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_0__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_1__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_1__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_0_ "BIU_CORE/Mcount_pfq_addr_out_lut<0>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_0__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_0__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_0__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out "BIU_CORE/Mcount_pfq_addr_out")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_0__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_0))
+              )
+            )
+            (net (rename BIU_CORE__n0870_inv "BIU_CORE/_n0870_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_0))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_1))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_2))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_3))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_4))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_5))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_6))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_7))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_8))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_9))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_10))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_11))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_12))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_13))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_14))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_15))
+                (portRef O (instanceRef BIU_CORE__n0870_inv1))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_12_ "BIU_CORE/Mcount_clock_cycle_counter_lut<12>")
+              (joined
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_12__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_12__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter12 "BIU_CORE/Mcount_clock_cycle_counter12")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_12__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_12))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_11_ "BIU_CORE/Mcount_clock_cycle_counter_cy<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_11_ "BIU_CORE/Mcount_clock_cycle_counter_lut<11>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_11__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_11__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_11__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter11 "BIU_CORE/Mcount_clock_cycle_counter11")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_11__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_11))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_10_ "BIU_CORE/Mcount_clock_cycle_counter_cy<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_10_ "BIU_CORE/Mcount_clock_cycle_counter_lut<10>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_10__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_10__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_10__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter10 "BIU_CORE/Mcount_clock_cycle_counter10")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_10__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_10))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_9_ "BIU_CORE/Mcount_clock_cycle_counter_cy<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_9_ "BIU_CORE/Mcount_clock_cycle_counter_lut<9>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_9__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_9__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_9__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter9 "BIU_CORE/Mcount_clock_cycle_counter9")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_9__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_9))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_8_ "BIU_CORE/Mcount_clock_cycle_counter_cy<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_8_ "BIU_CORE/Mcount_clock_cycle_counter_lut<8>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_8__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_8__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_8__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter8 "BIU_CORE/Mcount_clock_cycle_counter8")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_8__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_8))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_7_ "BIU_CORE/Mcount_clock_cycle_counter_cy<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_7_ "BIU_CORE/Mcount_clock_cycle_counter_lut<7>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_7__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_7__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_7__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter7 "BIU_CORE/Mcount_clock_cycle_counter7")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_7__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_7))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_6_ "BIU_CORE/Mcount_clock_cycle_counter_cy<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_6_ "BIU_CORE/Mcount_clock_cycle_counter_lut<6>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_6__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_6__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_6__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter6 "BIU_CORE/Mcount_clock_cycle_counter6")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_6__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_6))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_5_ "BIU_CORE/Mcount_clock_cycle_counter_cy<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_5_ "BIU_CORE/Mcount_clock_cycle_counter_lut<5>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_5__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_5__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_5__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter5 "BIU_CORE/Mcount_clock_cycle_counter5")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_5__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_5))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_4_ "BIU_CORE/Mcount_clock_cycle_counter_cy<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_4_ "BIU_CORE/Mcount_clock_cycle_counter_lut<4>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_4__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_4__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_4__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter4 "BIU_CORE/Mcount_clock_cycle_counter4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_4__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_4))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_3_ "BIU_CORE/Mcount_clock_cycle_counter_cy<3>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_3__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_3_ "BIU_CORE/Mcount_clock_cycle_counter_lut<3>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_3__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_3__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_3__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter3 "BIU_CORE/Mcount_clock_cycle_counter3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_3__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_3))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_2_ "BIU_CORE/Mcount_clock_cycle_counter_cy<2>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_2__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_3__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_3__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_2_ "BIU_CORE/Mcount_clock_cycle_counter_lut<2>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_2__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_2__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_2__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter2 "BIU_CORE/Mcount_clock_cycle_counter2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_2__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_2))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_1_ "BIU_CORE/Mcount_clock_cycle_counter_cy<1>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_1__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_2__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_2__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_1_ "BIU_CORE/Mcount_clock_cycle_counter_lut<1>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_1__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_1__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_1__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter1 "BIU_CORE/Mcount_clock_cycle_counter1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_1__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_1))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_0_ "BIU_CORE/Mcount_clock_cycle_counter_cy<0>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_0__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_1__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_1__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_0_ "BIU_CORE/Mcount_clock_cycle_counter_lut<0>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_0__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_0__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_0__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter "BIU_CORE/Mcount_clock_cycle_counter")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_0__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_0))
+              )
+            )
+            (net (rename BIU_CORE__n0867_inv "BIU_CORE/_n0867_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_0))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_1))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_2))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_3))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_4))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_5))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_6))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_7))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_8))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_9))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_10))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_11))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_12))
+                (portRef O (instanceRef BIU_CORE__n0867_inv1))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_15_ "BIU_CORE/Mcount_pfq_addr_in_lut<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_15__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in15 "BIU_CORE/Mcount_pfq_addr_in15")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_15__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_15))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_14_ "BIU_CORE/Mcount_pfq_addr_in_cy<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_14_ "BIU_CORE/Mcount_pfq_addr_in_lut<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_14__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_14__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in14 "BIU_CORE/Mcount_pfq_addr_in14")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_14__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_14))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_13_ "BIU_CORE/Mcount_pfq_addr_in_cy<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_13_ "BIU_CORE/Mcount_pfq_addr_in_lut<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_13__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_13__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in13 "BIU_CORE/Mcount_pfq_addr_in13")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_13__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_13))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_12_ "BIU_CORE/Mcount_pfq_addr_in_cy<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_12_ "BIU_CORE/Mcount_pfq_addr_in_lut<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_12__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_12__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in12 "BIU_CORE/Mcount_pfq_addr_in12")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_12__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_12))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_11_ "BIU_CORE/Mcount_pfq_addr_in_cy<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_11_ "BIU_CORE/Mcount_pfq_addr_in_lut<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_11__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_11__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in11 "BIU_CORE/Mcount_pfq_addr_in11")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_11__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_11))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_10_ "BIU_CORE/Mcount_pfq_addr_in_cy<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_10_ "BIU_CORE/Mcount_pfq_addr_in_lut<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_10__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_10__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in10 "BIU_CORE/Mcount_pfq_addr_in10")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_10__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_10))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_9_ "BIU_CORE/Mcount_pfq_addr_in_cy<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_9_ "BIU_CORE/Mcount_pfq_addr_in_lut<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_9__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_9__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in9 "BIU_CORE/Mcount_pfq_addr_in9")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_9__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_9))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_8_ "BIU_CORE/Mcount_pfq_addr_in_cy<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_8_ "BIU_CORE/Mcount_pfq_addr_in_lut<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_8__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_8__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in8 "BIU_CORE/Mcount_pfq_addr_in8")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_8__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_8))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_7_ "BIU_CORE/Mcount_pfq_addr_in_cy<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_7_ "BIU_CORE/Mcount_pfq_addr_in_lut<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_7__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_7__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in7 "BIU_CORE/Mcount_pfq_addr_in7")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_7__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_7))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_6_ "BIU_CORE/Mcount_pfq_addr_in_cy<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_6_ "BIU_CORE/Mcount_pfq_addr_in_lut<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_6__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_6__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in6 "BIU_CORE/Mcount_pfq_addr_in6")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_6__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_6))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_5_ "BIU_CORE/Mcount_pfq_addr_in_cy<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_5_ "BIU_CORE/Mcount_pfq_addr_in_lut<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_5__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_5__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in5 "BIU_CORE/Mcount_pfq_addr_in5")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_5__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_5))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_4_ "BIU_CORE/Mcount_pfq_addr_in_cy<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_4_ "BIU_CORE/Mcount_pfq_addr_in_lut<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_4__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_4__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in4 "BIU_CORE/Mcount_pfq_addr_in4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_4__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_4))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_3_ "BIU_CORE/Mcount_pfq_addr_in_cy<3>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_3__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_3_ "BIU_CORE/Mcount_pfq_addr_in_lut<3>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_3__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_3__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_3__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in3 "BIU_CORE/Mcount_pfq_addr_in3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_3__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_3))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_2_ "BIU_CORE/Mcount_pfq_addr_in_cy<2>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_2__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_3__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_3__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_2_ "BIU_CORE/Mcount_pfq_addr_in_lut<2>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_2__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_2__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_2__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in2 "BIU_CORE/Mcount_pfq_addr_in2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_2__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_2))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_1_ "BIU_CORE/Mcount_pfq_addr_in_cy<1>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_1__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_2__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_2__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_1_ "BIU_CORE/Mcount_pfq_addr_in_lut<1>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_1__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_1__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_1__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in1 "BIU_CORE/Mcount_pfq_addr_in1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_1__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_1))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_0_ "BIU_CORE/Mcount_pfq_addr_in_cy<0>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_0__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_1__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_1__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_0_ "BIU_CORE/Mcount_pfq_addr_in_lut<0>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_0__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_0__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_0__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in "BIU_CORE/Mcount_pfq_addr_in")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_0__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_0))
+              )
+            )
+            (net (rename BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_11_o_inv "BIU_CORE/eu_biu_req_caught_eu_biu_req_code[4]_AND_11_o_inv")
+              (joined
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_0__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_0__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_0__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_0__))
+                (portRef O (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_11_o_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n0889_inv "BIU_CORE/_n0889_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_0))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_1))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_2))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_3))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_4))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_5))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_6))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_7))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_8))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_9))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_10))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_11))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_12))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_13))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_14))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_15))
+                (portRef O (instanceRef BIU_CORE__n0889_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n0910_inv "BIU_CORE/_n0910_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_s_bits_0))
+                (portRef CE (instanceRef BIU_CORE_s_bits_1))
+                (portRef CE (instanceRef BIU_CORE_s_bits_2))
+                (portRef O (instanceRef BIU_CORE__n0910_inv_renamed_258))
+              )
+            )
+            (net (rename BIU_CORE__n0886_inv "BIU_CORE/_n0886_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_pfq_entry3_0))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry3_1))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry3_2))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry3_3))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry3_4))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry3_5))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry3_6))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry3_7))
+                (portRef O (instanceRef BIU_CORE__n0886_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n0882_inv "BIU_CORE/_n0882_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_pfq_entry2_0))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry2_1))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry2_2))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry2_3))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry2_4))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry2_5))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry2_6))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry2_7))
+                (portRef O (instanceRef BIU_CORE__n0882_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n0878_inv "BIU_CORE/_n0878_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_pfq_entry1_0))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry1_1))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry1_2))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry1_3))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry1_4))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry1_5))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry1_6))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry1_7))
+                (portRef O (instanceRef BIU_CORE__n0878_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n0874_inv "BIU_CORE/_n0874_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_pfq_entry0_0))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry0_1))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry0_2))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry0_3))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry0_4))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry0_5))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry0_6))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry0_7))
+                (portRef O (instanceRef BIU_CORE__n0874_inv1))
+              )
+            )
+            (net (rename BIU_CORE_RESET_INT_inv "BIU_CORE/RESET_INT_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_ALE_renamed_10))
+                (portRef CE (instanceRef BIU_CORE_pfq_top_byte_int_d1_0))
+                (portRef CE (instanceRef BIU_CORE_pfq_top_byte_int_d1_1))
+                (portRef CE (instanceRef BIU_CORE_pfq_top_byte_int_d1_2))
+                (portRef CE (instanceRef BIU_CORE_pfq_top_byte_int_d1_3))
+                (portRef CE (instanceRef BIU_CORE_pfq_top_byte_int_d1_4))
+                (portRef CE (instanceRef BIU_CORE_pfq_top_byte_int_d1_5))
+                (portRef CE (instanceRef BIU_CORE_pfq_top_byte_int_d1_6))
+                (portRef CE (instanceRef BIU_CORE_pfq_top_byte_int_d1_7))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_0))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_1))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_2))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_3))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_4))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_5))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_6))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_7))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_8))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_9))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_10))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_11))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_12))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_13))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_14))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_15))
+                (portRef O (instanceRef BIU_CORE_RESET_INT_inv1_INV_0))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_15_renamed_409))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_15))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_14_renamed_410))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_14))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_13_renamed_411))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_13))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_12_renamed_412))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_12))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_11_renamed_413))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_11))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_10_renamed_414))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_10))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_9_renamed_415))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_9))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_8_renamed_416))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_8))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_7_renamed_417))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_7))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_6_renamed_418))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_6))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_3_renamed_419))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_3))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_5_renamed_420))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_5))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_4_renamed_421))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_4))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_2_renamed_422))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_2))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_1_renamed_423))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_1))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_0_renamed_424))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_0))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_15_renamed_425))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_15))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_12_renamed_426))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_12))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_14_renamed_427))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_14))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_13_renamed_428))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_13))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_11_renamed_429))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_11))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_10_renamed_430))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_10))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_9_renamed_431))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_9))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_8_renamed_432))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_8))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_5_renamed_433))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_5))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_7_renamed_434))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_7))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_6_renamed_435))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_6))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_4_renamed_436))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_4))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_3_renamed_437))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_3))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_2_renamed_438))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_2))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_1_renamed_439))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_1))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_14_renamed_440))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_14))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_0_renamed_441))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_0))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_15_renamed_442))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_15))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_13_renamed_443))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_13))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_12_renamed_444))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_12))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_11_renamed_445))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_11))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_10_renamed_446))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_10))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_7_renamed_447))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_7))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_9_renamed_448))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_9))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_8_renamed_449))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_8))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_6_renamed_450))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_6))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_5_renamed_451))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_5))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_4_renamed_452))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_4))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_3_renamed_453))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_3))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_0_renamed_454))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_0))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_2_renamed_455))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_2))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_1_renamed_456))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_1))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_15_renamed_457))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_15))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_14_renamed_458))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_14))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_13_renamed_459))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_13))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_12_renamed_460))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_12))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_9_renamed_461))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_9))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_11_renamed_462))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_11))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_10_renamed_463))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_10))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_8_renamed_464))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_8))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_7_renamed_465))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_7))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_6_renamed_466))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_6))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_5_renamed_467))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_5))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_4_renamed_468))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_4))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_3_renamed_469))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_3))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_2_renamed_470))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_2))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_1_renamed_471))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_1))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_0_renamed_472))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_0))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_15_renamed_473))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_15))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_14_renamed_474))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_14))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_13_renamed_475))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_13))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_10_renamed_476))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_10))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_12_renamed_477))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_12))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_11_renamed_478))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_11))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_9_renamed_479))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_9))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_8_renamed_480))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_8))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_7_renamed_481))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_7))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_6_renamed_482))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_6))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_3_renamed_483))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_3))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_5_renamed_484))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_5))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_4_renamed_485))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_4))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_2_renamed_486))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_2))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_1_renamed_487))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_1))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_0_renamed_488))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_0))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_15_renamed_489))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_15))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_12_renamed_490))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_12))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_14_renamed_491))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_14))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_13_renamed_492))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_13))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_11_renamed_493))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_11))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_10_renamed_494))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_10))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_9_renamed_495))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_9))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_8_renamed_496))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_8))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_5_renamed_497))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_5))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_7_renamed_498))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_7))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_6_renamed_499))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_6))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_4_renamed_500))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_4))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_3_renamed_501))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_3))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_2_renamed_502))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_2))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_1_renamed_503))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_1))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_14_renamed_504))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_14))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_0_renamed_505))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_0))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_15_renamed_506))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_15))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_13_renamed_507))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_13))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_12_renamed_508))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_12))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_11_renamed_509))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_11))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_10_renamed_510))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_10))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_7_renamed_511))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_7))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_9_renamed_512))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_9))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_8_renamed_513))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_8))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_6_renamed_514))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_6))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_5_renamed_515))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_5))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_4_renamed_516))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_4))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_3_renamed_517))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_3))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_0_renamed_518))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_0))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_2_renamed_519))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_2))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_1_renamed_520))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_equal_146_o1 "BIU_CORE/biu_state[7]_GND_10_o_equal_146_o1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_146_o_7_2))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o111))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_3_renamed_249))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_3_renamed_251))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_3_renamed_253))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_3_renamed_255))
+                (portRef I0 (instanceRef BIU_CORE__n0910_inv_renamed_258))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o2_renamed_259))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_3_renamed_262))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_5))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_5))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_5))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_5))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_5))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_5))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_5))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_5))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_5))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_5))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_5))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_5_renamed_304))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o113))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_1_renamed_307))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_1_renamed_309))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_1_renamed_311))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_1_renamed_313))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_31))
+                (portRef I1 (instanceRef BIU_CORE_word_cycle_rstpot1_renamed_383))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_1_renamed_389))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_1_renamed_390))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_1_renamed_391))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_1_renamed_392))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_1_renamed_393))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_1_renamed_394))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_1_renamed_395))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_1_renamed_396))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_1_renamed_397))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_1_renamed_399))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_1_renamed_400))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_1_renamed_401))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_21))
+                (portRef I4 (instanceRef BIU_CORE__n10044_SW0))
+              )
+            )
+            (net (rename BIU_CORE__n0897_inv "BIU_CORE/_n0897_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_iom_int_renamed_39))
+                (portRef CE (instanceRef BIU_CORE_dtr_int_renamed_3))
+                (portRef O (instanceRef BIU_CORE__n0897_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n0865_inv "BIU_CORE/_n0865_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_0))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_1))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_2))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_3))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_4))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_5))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_6))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_7))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_8))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_9))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_10))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_11))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_12))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_13))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_14))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_15))
+                (portRef O (instanceRef BIU_CORE__n0865_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n0861_inv "BIU_CORE/_n0861_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_0))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_1))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_2))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_3))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_4))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_5))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_6))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_7))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_8))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_9))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_10))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_11))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_12))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_13))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_14))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_15))
+                (portRef O (instanceRef BIU_CORE__n0861_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n0905_inv "BIU_CORE/_n0905_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_0))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_1))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_2))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_3))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_4))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_5))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_6))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_7))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_8))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_9))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_10))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_11))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_12))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_13))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_14))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_15))
+                (portRef O (instanceRef BIU_CORE__n0905_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n0857_inv "BIU_CORE/_n0857_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_0))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_1))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_2))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_3))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_4))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_5))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_6))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_7))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_8))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_9))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_10))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_11))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_12))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_13))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_14))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_15))
+                (portRef O (instanceRef BIU_CORE__n0857_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n0853_inv "BIU_CORE/_n0853_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_0))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_1))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_2))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_3))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_4))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_5))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_6))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_7))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_8))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_9))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_10))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_11))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_12))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_13))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_14))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_15))
+                (portRef O (instanceRef BIU_CORE__n0853_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n0849_inv "BIU_CORE/_n0849_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_0))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_1))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_2))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_3))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_4))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_5))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_6))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_7))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_8))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_9))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_10))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_11))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_12))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_13))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_14))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_15))
+                (portRef O (instanceRef BIU_CORE__n0849_inv1))
+              )
+            )
+            (net (rename BIU_CORE_eu_biu_req_code_4__INV_26_o "BIU_CORE/eu_biu_req_code[4]_INV_26_o")
+              (joined
+                (portRef O (instanceRef BIU_CORE_eu_biu_req_code_4__INV_26_o1))
+                (portRef I3 (instanceRef BIU_CORE_word_cycle_rstpot1_renamed_383))
+              )
+            )
+            (net (rename BIU_CORE_pfq_full_GND_10_o_equal_118_o "BIU_CORE/pfq_full_GND_10_o_equal_118_o")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_2_renamed_261))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_31))
+                (portRef I0 (instanceRef BIU_CORE__n09783_SW0))
+                (portRef O (instanceRef BIU_CORE_pfq_full_GND_10_o_equal_118_o1))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_1_renamed_389))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_1_renamed_390))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_1_renamed_391))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_1_renamed_392))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_1_renamed_393))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_1_renamed_394))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_1_renamed_395))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_1_renamed_396))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_1_renamed_397))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_1_renamed_399))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_1_renamed_400))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_1_renamed_401))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_21))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__reduce_or_184_o "BIU_CORE/biu_state[7]_reduce_or_184_o")
+              (joined
+                (portRef O (instanceRef BIU_CORE_out91))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_182_o1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__rd_n_int_Select_180_o1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_184_o_renamed_264))
+              )
+            )
+            (net (rename BIU_CORE_n0190 "BIU_CORE/n0190")
+              (joined
+                (portRef I3 (instanceRef BIU_CORE_out91))
+                (portRef I5 (instanceRef BIU_CORE__n0988_renamed_245))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_161_o_renamed_263))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_31))
+                (portRef O (instanceRef BIU_CORE_out21))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_21))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_10_o_add_140_OUT_0_ "BIU_CORE/addr_out_temp[15]_GND_10_o_add_140_OUT<0>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_0__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_2_renamed_308))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_10_o_add_140_OUT_1_ "BIU_CORE/addr_out_temp[15]_GND_10_o_add_140_OUT<1>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_1__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_2_renamed_310))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_10_o_add_140_OUT_2_ "BIU_CORE/addr_out_temp[15]_GND_10_o_add_140_OUT<2>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_2__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_2_renamed_312))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_10_o_add_140_OUT_3_ "BIU_CORE/addr_out_temp[15]_GND_10_o_add_140_OUT<3>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_3__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_2_renamed_314))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_10_o_add_140_OUT_4_ "BIU_CORE/addr_out_temp[15]_GND_10_o_add_140_OUT<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_4__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_1_renamed_392))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_10_o_add_140_OUT_5_ "BIU_CORE/addr_out_temp[15]_GND_10_o_add_140_OUT<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_5__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_1_renamed_393))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_10_o_add_140_OUT_6_ "BIU_CORE/addr_out_temp[15]_GND_10_o_add_140_OUT<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_6__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_1_renamed_394))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_10_o_add_140_OUT_7_ "BIU_CORE/addr_out_temp[15]_GND_10_o_add_140_OUT<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_7__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_1_renamed_395))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_10_o_add_140_OUT_8_ "BIU_CORE/addr_out_temp[15]_GND_10_o_add_140_OUT<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_8__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_1_renamed_396))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_10_o_add_140_OUT_9_ "BIU_CORE/addr_out_temp[15]_GND_10_o_add_140_OUT<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_9__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_1_renamed_397))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_10_o_add_140_OUT_10_ "BIU_CORE/addr_out_temp[15]_GND_10_o_add_140_OUT<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_10__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_1_renamed_389))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_10_o_add_140_OUT_11_ "BIU_CORE/addr_out_temp[15]_GND_10_o_add_140_OUT<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_11__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_1_renamed_390))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_10_o_add_140_OUT_12_ "BIU_CORE/addr_out_temp[15]_GND_10_o_add_140_OUT<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_12__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_1_renamed_391))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_10_o_add_140_OUT_13_ "BIU_CORE/addr_out_temp[15]_GND_10_o_add_140_OUT<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_13__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_1_renamed_399))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_10_o_add_140_OUT_14_ "BIU_CORE/addr_out_temp[15]_GND_10_o_add_140_OUT<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_14__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_1_renamed_400))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_10_o_add_140_OUT_15_ "BIU_CORE/addr_out_temp[15]_GND_10_o_add_140_OUT<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_15__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_1_renamed_401))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<0>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_0_renamed_38))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<1>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_1_renamed_37))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<2>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_2_renamed_36))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<3>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_3_renamed_35))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<4>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_4_renamed_34))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<5>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_5_renamed_33))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<6>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_6_renamed_32))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<7>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_7_renamed_31))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<8>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_8_renamed_30))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<9>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_9_renamed_29))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_5_renamed_304))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<10>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_10_renamed_28))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<11>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_11_renamed_27))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<12>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_12_renamed_26))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<13>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_13_renamed_25))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<14>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_14_renamed_24))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<15>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_15_renamed_23))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<16>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_16_renamed_22))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<17>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_17_renamed_21))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<18>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_18_renamed_20))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<19>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_19_renamed_19))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_4_renamed_256))
+              )
+            )
+            (net (rename BIU_CORE__n1004 "BIU_CORE/_n1004")
+              (joined
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_0__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_1__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_2__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_3__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_4__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_5__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_6__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_7__))
+                (portRef O (instanceRef BIU_CORE__n10044))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_8_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_9_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_10_2))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_11_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_12_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_13_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_14_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_15_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_16_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_17_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_18_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_19_1))
+              )
+            )
+            (net (rename BIU_CORE__n0988 "BIU_CORE/_n0988")
+              (joined
+                (portRef O (instanceRef BIU_CORE__n0988_renamed_245))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_6_2))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_7_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_3_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_2_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_ "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<0>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_state_0))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_ "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<1>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_state_1))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_2_ "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<2>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_state_2))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_2_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_3_ "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<3>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_state_3))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_3_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_ "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<4>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_state_4))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_ "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<5>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_state_5))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_6_ "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<6>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_state_6))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_6_2))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_7_ "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<7>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_state_7))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_7_1))
+              )
+            )
+            (net (rename BIU_CORE__n0918 "BIU_CORE/_n0918")
+              (joined
+                (portRef O (instanceRef BIU_CORE__n09181))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_3_renamed_249))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_3_renamed_251))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_3_renamed_253))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_3_renamed_255))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_4_renamed_270))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_4_renamed_273))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_4_renamed_276))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_4_renamed_279))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_4_renamed_282))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_4_renamed_285))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_4_renamed_288))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_4_renamed_291))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_4_renamed_294))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_4_renamed_297))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_4_renamed_300))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_4_renamed_303))
+              )
+            )
+            (net (rename BIU_CORE__n0926 "BIU_CORE/_n0926")
+              (joined
+                (portRef O (instanceRef BIU_CORE__n09261))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT3))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT1))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT2))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_31))
+                (portRef I2 (instanceRef BIU_CORE__n09783_SW0))
+              )
+            )
+            (net (rename BIU_CORE_s_bits_2__INV_27_o "BIU_CORE/s_bits[2]_INV_27_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_iom_int_renamed_39))
+                (portRef O (instanceRef BIU_CORE_s_bits_2__INV_27_o1_INV_0))
+              )
+            )
+            (net (rename BIU_CORE_GND_10_o_latched_data_in_7__mux_139_OUT_0_ "BIU_CORE/GND_10_o_latched_data_in[7]_mux_139_OUT<0>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_0))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT17))
+              )
+            )
+            (net (rename BIU_CORE_GND_10_o_latched_data_in_7__mux_139_OUT_1_ "BIU_CORE/GND_10_o_latched_data_in[7]_mux_139_OUT<1>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_1))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT81))
+              )
+            )
+            (net (rename BIU_CORE_GND_10_o_latched_data_in_7__mux_139_OUT_2_ "BIU_CORE/GND_10_o_latched_data_in[7]_mux_139_OUT<2>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_2))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT91))
+              )
+            )
+            (net (rename BIU_CORE_GND_10_o_latched_data_in_7__mux_139_OUT_3_ "BIU_CORE/GND_10_o_latched_data_in[7]_mux_139_OUT<3>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_3))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT101))
+              )
+            )
+            (net (rename BIU_CORE_GND_10_o_latched_data_in_7__mux_139_OUT_4_ "BIU_CORE/GND_10_o_latched_data_in[7]_mux_139_OUT<4>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_4))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT111))
+              )
+            )
+            (net (rename BIU_CORE_GND_10_o_latched_data_in_7__mux_139_OUT_5_ "BIU_CORE/GND_10_o_latched_data_in[7]_mux_139_OUT<5>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_5))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT121))
+              )
+            )
+            (net (rename BIU_CORE_GND_10_o_latched_data_in_7__mux_139_OUT_6_ "BIU_CORE/GND_10_o_latched_data_in[7]_mux_139_OUT<6>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_6))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT131))
+              )
+            )
+            (net (rename BIU_CORE_GND_10_o_latched_data_in_7__mux_139_OUT_7_ "BIU_CORE/GND_10_o_latched_data_in[7]_mux_139_OUT<7>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_7))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT141))
+              )
+            )
+            (net (rename BIU_CORE_GND_10_o_latched_data_in_7__mux_139_OUT_8_ "BIU_CORE/GND_10_o_latched_data_in[7]_mux_139_OUT<8>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_8))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT151))
+              )
+            )
+            (net (rename BIU_CORE_GND_10_o_latched_data_in_7__mux_139_OUT_9_ "BIU_CORE/GND_10_o_latched_data_in[7]_mux_139_OUT<9>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_9))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT161))
+              )
+            )
+            (net (rename BIU_CORE_GND_10_o_latched_data_in_7__mux_139_OUT_10_ "BIU_CORE/GND_10_o_latched_data_in[7]_mux_139_OUT<10>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_10))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT21))
+              )
+            )
+            (net (rename BIU_CORE_GND_10_o_latched_data_in_7__mux_139_OUT_11_ "BIU_CORE/GND_10_o_latched_data_in[7]_mux_139_OUT<11>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_11))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT31))
+              )
+            )
+            (net (rename BIU_CORE_GND_10_o_latched_data_in_7__mux_139_OUT_12_ "BIU_CORE/GND_10_o_latched_data_in[7]_mux_139_OUT<12>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_12))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT41))
+              )
+            )
+            (net (rename BIU_CORE_GND_10_o_latched_data_in_7__mux_139_OUT_13_ "BIU_CORE/GND_10_o_latched_data_in[7]_mux_139_OUT<13>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_13))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT51))
+              )
+            )
+            (net (rename BIU_CORE_GND_10_o_latched_data_in_7__mux_139_OUT_14_ "BIU_CORE/GND_10_o_latched_data_in[7]_mux_139_OUT<14>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_14))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT61))
+              )
+            )
+            (net (rename BIU_CORE_GND_10_o_latched_data_in_7__mux_139_OUT_15_ "BIU_CORE/GND_10_o_latched_data_in[7]_mux_139_OUT<15>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_15))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT71))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_equal_147_o "BIU_CORE/biu_state[7]_GND_10_o_equal_147_o")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_147_o_7_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_3_renamed_262))
+                (portRef I3 (instanceRef BIU_CORE__n09781_renamed_246))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_equal_148_o "BIU_CORE/biu_state[7]_GND_10_o_equal_148_o")
+              (joined
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__ale_int_Select_176_o1))
+                (portRef I4 (instanceRef BIU_CORE_out91))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_148_o_7_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o3_renamed_244))
+                (portRef I1 (instanceRef BIU_CORE__n0988_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_174_o_renamed_265))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_0__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_1__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_2__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_3__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_4__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_5__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_6__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_7__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o_renamed_315))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o112))
+                (portRef I5 (instanceRef BIU_CORE__n09781_renamed_246))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_8_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_9_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_10_2))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_11_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_12_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_13_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_14_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_15_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_16_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_17_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_18_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_19_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_equal_150_o "BIU_CORE/biu_state[7]_GND_10_o_equal_150_o")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_150_o_7_2))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_182_o1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__rd_n_int_Select_180_o1))
+                (portRef I1 (instanceRef BIU_CORE__n0988_renamed_245))
+                (portRef I1 (instanceRef BIU_CORE__n09782_renamed_247))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_184_o_renamed_264))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_174_o_renamed_265))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_0__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_1__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_2__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_3__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_4__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_5__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_6__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_7__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o_renamed_315))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_8_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_9_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_10_2))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_11_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_12_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_13_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_14_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_15_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_16_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_17_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_18_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_19_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_equal_149_o "BIU_CORE/biu_state[7]_GND_10_o_equal_149_o")
+              (joined
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__ale_int_Select_176_o1))
+                (portRef I0 (instanceRef BIU_CORE_out91))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o3_renamed_244))
+                (portRef I4 (instanceRef BIU_CORE__n0988_renamed_245))
+                (portRef I2 (instanceRef BIU_CORE__n09782_renamed_247))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_149_o_7__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o_SW0))
+                (portRef I1 (instanceRef BIU_CORE_out21))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_174_o_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o112))
+                (portRef I1 (instanceRef BIU_CORE__n10044_SW0))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_equal_154_o "BIU_CORE/biu_state[7]_GND_10_o_equal_154_o")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_154_o_7_1))
+                (portRef I2 (instanceRef BIU_CORE__n0988_SW0))
+                (portRef I0 (instanceRef BIU_CORE_out21))
+                (portRef I2 (instanceRef BIU_CORE__n09781_renamed_246))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_equal_153_o "BIU_CORE/biu_state[7]_GND_10_o_equal_153_o")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_latched_data_in_0))
+                (portRef CE (instanceRef BIU_CORE_latched_data_in_1))
+                (portRef CE (instanceRef BIU_CORE_latched_data_in_2))
+                (portRef CE (instanceRef BIU_CORE_latched_data_in_3))
+                (portRef CE (instanceRef BIU_CORE_latched_data_in_4))
+                (portRef CE (instanceRef BIU_CORE_latched_data_in_5))
+                (portRef CE (instanceRef BIU_CORE_latched_data_in_6))
+                (portRef CE (instanceRef BIU_CORE_latched_data_in_7))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_153_o_7_1))
+                (portRef I3 (instanceRef BIU_CORE__n0988_SW0))
+                (portRef I3 (instanceRef BIU_CORE__n09782_renamed_247))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_161_o_renamed_263))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_equal_152_o "BIU_CORE/biu_state[7]_GND_10_o_equal_152_o")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_152_o_7_2))
+                (portRef I4 (instanceRef BIU_CORE__n09782_renamed_247))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5__))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW2))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_7_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_3_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW2))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_equal_151_o "BIU_CORE/biu_state[7]_GND_10_o_equal_151_o")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_out91))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_151_o_7_1))
+                (portRef I4 (instanceRef BIU_CORE__n0988_SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_174_o_SW0))
+                (portRef I1 (instanceRef BIU_CORE__n09781_renamed_246))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1113))
+                (portRef I2 (instanceRef BIU_CORE__n10044_SW0))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_equal_159_o "BIU_CORE/biu_state[7]_GND_10_o_equal_159_o")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_159_o_7_1))
+                (portRef I0 (instanceRef BIU_CORE__n09781_renamed_246))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_3_renamed_262))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o113))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1113))
+                (portRef I3 (instanceRef BIU_CORE__n10044_SW0))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_equal_156_o "BIU_CORE/biu_state[7]_GND_10_o_equal_156_o")
+              (joined
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_156_o_7_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_182_o1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__rd_n_int_Select_180_o1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o1_renamed_243))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_184_o_renamed_264))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_2_renamed_308))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_2_renamed_310))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_2_renamed_312))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_2_renamed_314))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o_renamed_315))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_21))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_1_renamed_389))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_1_renamed_390))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_1_renamed_391))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_1_renamed_392))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_1_renamed_393))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_1_renamed_394))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_1_renamed_395))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_1_renamed_396))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_1_renamed_397))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_1_renamed_399))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_1_renamed_400))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_1_renamed_401))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_equal_155_o "BIU_CORE/biu_state[7]_GND_10_o_equal_155_o")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_0))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_1))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_2))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_3))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_4))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_5))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_6))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_7))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_8))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_9))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_10))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_11))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_12))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_13))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_14))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_15))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_155_o_7_1))
+                (portRef I0 (instanceRef BIU_CORE__n0988_SW0))
+                (portRef I4 (instanceRef BIU_CORE__n09781_renamed_246))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__den_int_Select_178_o "BIU_CORE/biu_state[7]_den_int_Select_178_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_den_int_renamed_40))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o_renamed_315))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__wr_n_int_Select_182_o "BIU_CORE/biu_state[7]_wr_n_int_Select_182_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_wr_n_int_renamed_41))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_182_o1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__rd_n_int_Select_180_o "BIU_CORE/biu_state[7]_rd_n_int_Select_180_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_rd_n_int_renamed_42))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__rd_n_int_Select_180_o1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__inta_n_int_Select_184_o "BIU_CORE/biu_state[7]_inta_n_int_Select_184_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_inta_n_int_renamed_43))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_184_o_renamed_264))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__ale_int_Select_176_o "BIU_CORE/biu_state[7]_ale_int_Select_176_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_ale_int_renamed_45))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__ale_int_Select_176_o1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OE_Select_174_o "BIU_CORE/biu_state[7]_AD_OE_Select_174_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OE_renamed_46))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_174_o_renamed_265))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_Select_163_o "BIU_CORE/biu_state[7]_GND_10_o_Select_163_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_byte_num_renamed_48))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1))
+              )
+            )
+            (net (rename BIU_CORE_s_bits_2__word_cycle_AND_33_o "BIU_CORE/s_bits[2]_word_cycle_AND_33_o")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT17))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT81))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT91))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT101))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT111))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT121))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT131))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT141))
+                (portRef O (instanceRef BIU_CORE_s_bits_2__word_cycle_AND_33_o1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_0_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<0>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_0))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_0__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_1_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<1>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_1))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_1__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_2_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<2>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_2))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_2__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_3_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<3>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_3))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_3__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_4_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<4>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_4))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_4__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_5_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<5>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_5))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_5__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_6_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<6>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_6))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_6__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_7_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<7>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_7))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_7__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_8_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<8>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_8))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_8_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_9_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<9>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_9))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_9_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_10_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<10>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_10))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_10_2))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_11_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<11>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_11))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_11_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_12_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<12>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_12))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_12_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_13_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<13>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_13))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_13_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_14_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<14>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_14))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_14_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_15_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<15>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_15))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_15_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_16_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<16>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_16))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_16_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_17_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<17>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_17))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_17_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_18_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<18>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_18))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_18_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_19_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_172_OUT<19>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_19))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_19_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__biu_done_int_Select_169_o "BIU_CORE/biu_state[7]_biu_done_int_Select_169_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_done_int_renamed_51))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_Select_161_o "BIU_CORE/biu_state[7]_GND_10_o_Select_161_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_write_renamed_52))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_161_o_renamed_263))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_10_o_add_90_OUT_4_ "BIU_CORE/biu_muxed_segment[15]_GND_10_o_add_90_OUT<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_4__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_4_renamed_288))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_10_o_add_90_OUT_5_ "BIU_CORE/biu_muxed_segment[15]_GND_10_o_add_90_OUT<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_5__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_4_renamed_291))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_10_o_add_90_OUT_6_ "BIU_CORE/biu_muxed_segment[15]_GND_10_o_add_90_OUT<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_6__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_4_renamed_294))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_10_o_add_90_OUT_7_ "BIU_CORE/biu_muxed_segment[15]_GND_10_o_add_90_OUT<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_7__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_4_renamed_297))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_10_o_add_90_OUT_8_ "BIU_CORE/biu_muxed_segment[15]_GND_10_o_add_90_OUT<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_8__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_4_renamed_300))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_10_o_add_90_OUT_9_ "BIU_CORE/biu_muxed_segment[15]_GND_10_o_add_90_OUT<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_9__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_4_renamed_303))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_10_o_add_90_OUT_10_ "BIU_CORE/biu_muxed_segment[15]_GND_10_o_add_90_OUT<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_10__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_4_renamed_270))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_10_o_add_90_OUT_11_ "BIU_CORE/biu_muxed_segment[15]_GND_10_o_add_90_OUT<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_11__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_4_renamed_273))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_10_o_add_90_OUT_12_ "BIU_CORE/biu_muxed_segment[15]_GND_10_o_add_90_OUT<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_12__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_4_renamed_276))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_10_o_add_90_OUT_13_ "BIU_CORE/biu_muxed_segment[15]_GND_10_o_add_90_OUT<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_13__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_4_renamed_279))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_10_o_add_90_OUT_14_ "BIU_CORE/biu_muxed_segment[15]_GND_10_o_add_90_OUT<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_14__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_4_renamed_282))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_10_o_add_90_OUT_15_ "BIU_CORE/biu_muxed_segment[15]_GND_10_o_add_90_OUT<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_15__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_4_renamed_285))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_10_o_add_90_OUT_16_ "BIU_CORE/biu_muxed_segment[15]_GND_10_o_add_90_OUT<16>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_16__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_3_renamed_249))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_10_o_add_90_OUT_17_ "BIU_CORE/biu_muxed_segment[15]_GND_10_o_add_90_OUT<17>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_17__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_3_renamed_251))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_10_o_add_90_OUT_18_ "BIU_CORE/biu_muxed_segment[15]_GND_10_o_add_90_OUT<18>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_18__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_3_renamed_253))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_10_o_add_90_OUT_19_ "BIU_CORE/biu_muxed_segment[15]_GND_10_o_add_90_OUT<19>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_19__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_3_renamed_255))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_118_OUT_4_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_118_OUT<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_4__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_1_renamed_392))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_118_OUT_5_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_118_OUT<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_5__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_1_renamed_393))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_118_OUT_6_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_118_OUT<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_6__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_1_renamed_394))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_118_OUT_7_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_118_OUT<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_7__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_1_renamed_395))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_118_OUT_8_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_118_OUT<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_8__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_1_renamed_396))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_118_OUT_9_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_118_OUT<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_9__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_1_renamed_397))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_118_OUT_10_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_118_OUT<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_10__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_1_renamed_389))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_118_OUT_11_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_118_OUT<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_11__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_1_renamed_390))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_118_OUT_12_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_118_OUT<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_12__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_1_renamed_391))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_118_OUT_13_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_118_OUT<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_13__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_1_renamed_399))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_118_OUT_14_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_118_OUT<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_14__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_1_renamed_400))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_118_OUT_15_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_118_OUT<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_15__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_1_renamed_401))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_118_OUT_16_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_118_OUT<16>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_16__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_118_OUT_17_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_118_OUT<17>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_17__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_118_OUT_18_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_118_OUT<18>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_18__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_118_OUT_19_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_118_OUT<19>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_19__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_4_renamed_256))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_89_OUT_4_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_89_OUT<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_4__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_4_renamed_288))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_89_OUT_5_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_89_OUT<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_5__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_4_renamed_291))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_89_OUT_6_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_89_OUT<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_6__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_4_renamed_294))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_89_OUT_7_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_89_OUT<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_7__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_4_renamed_297))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_89_OUT_8_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_89_OUT<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_8__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_4_renamed_300))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_89_OUT_9_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_89_OUT<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_9__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_4_renamed_303))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_89_OUT_10_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_89_OUT<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_10__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_4_renamed_270))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_89_OUT_11_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_89_OUT<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_11__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_4_renamed_273))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_89_OUT_12_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_89_OUT<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_12__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_4_renamed_276))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_89_OUT_13_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_89_OUT<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_13__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_4_renamed_279))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_89_OUT_14_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_89_OUT<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_14__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_4_renamed_282))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_89_OUT_15_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_89_OUT<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_15__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_4_renamed_285))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_89_OUT_16_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_89_OUT<16>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_16__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_2_renamed_248))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_89_OUT_17_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_89_OUT<17>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_17__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_2_renamed_250))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_89_OUT_18_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_89_OUT<18>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_18__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_2_renamed_252))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_10_o_add_89_OUT_19_ "BIU_CORE/biu_register_cs[15]_GND_10_o_add_89_OUT<19>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_19__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_2_renamed_254))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_10_o_add_92_OUT_4_ "BIU_CORE/biu_register_ss[15]_GND_10_o_add_92_OUT<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_4__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_2_renamed_286))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_10_o_add_92_OUT_5_ "BIU_CORE/biu_register_ss[15]_GND_10_o_add_92_OUT<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_5__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_2_renamed_289))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_10_o_add_92_OUT_6_ "BIU_CORE/biu_register_ss[15]_GND_10_o_add_92_OUT<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_6__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_2_renamed_292))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_10_o_add_92_OUT_7_ "BIU_CORE/biu_register_ss[15]_GND_10_o_add_92_OUT<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_7__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_2_renamed_295))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_10_o_add_92_OUT_8_ "BIU_CORE/biu_register_ss[15]_GND_10_o_add_92_OUT<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_8__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_2_renamed_298))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_10_o_add_92_OUT_9_ "BIU_CORE/biu_register_ss[15]_GND_10_o_add_92_OUT<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_9__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_2_renamed_301))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_10_o_add_92_OUT_10_ "BIU_CORE/biu_register_ss[15]_GND_10_o_add_92_OUT<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_10__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_2_renamed_268))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_10_o_add_92_OUT_11_ "BIU_CORE/biu_register_ss[15]_GND_10_o_add_92_OUT<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_11__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_2_renamed_271))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_10_o_add_92_OUT_12_ "BIU_CORE/biu_register_ss[15]_GND_10_o_add_92_OUT<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_12__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_2_renamed_274))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_10_o_add_92_OUT_13_ "BIU_CORE/biu_register_ss[15]_GND_10_o_add_92_OUT<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_13__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_2_renamed_277))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_10_o_add_92_OUT_14_ "BIU_CORE/biu_register_ss[15]_GND_10_o_add_92_OUT<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_14__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_2_renamed_280))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_10_o_add_92_OUT_15_ "BIU_CORE/biu_register_ss[15]_GND_10_o_add_92_OUT<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_15__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_2_renamed_283))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_10_o_add_92_OUT_16_ "BIU_CORE/biu_register_ss[15]_GND_10_o_add_92_OUT<16>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_16__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_2_renamed_248))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_10_o_add_92_OUT_17_ "BIU_CORE/biu_register_ss[15]_GND_10_o_add_92_OUT<17>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_17__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_2_renamed_250))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_10_o_add_92_OUT_18_ "BIU_CORE/biu_register_ss[15]_GND_10_o_add_92_OUT<18>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_18__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_2_renamed_252))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_10_o_add_92_OUT_19_ "BIU_CORE/biu_register_ss[15]_GND_10_o_add_92_OUT<19>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_19__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_2_renamed_254))
+              )
+            )
+            (net (rename BIU_CORE_eu_biu_req_code_4__PWR_2_o_equal_102_o "BIU_CORE/eu_biu_req_code[4]_PWR_2_o_equal_102_o")
+              (joined
+                (portRef O (instanceRef BIU_CORE_eu_biu_req_code_4__PWR_2_o_equal_102_o_4_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_2_renamed_248))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_2_renamed_250))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_2_renamed_252))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_2_renamed_254))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_4_renamed_270))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_4_renamed_273))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_4_renamed_276))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_4_renamed_279))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_4_renamed_282))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_4_renamed_285))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_4_renamed_288))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_4_renamed_291))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_4_renamed_294))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_4_renamed_297))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_4_renamed_300))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_4_renamed_303))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_1_renamed_307))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_1_renamed_309))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_1_renamed_311))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_1_renamed_313))
+              )
+            )
+            (net (rename BIU_CORE_eu_biu_strobe_1__PWR_2_o_equal_61_o "BIU_CORE/eu_biu_strobe[1]_PWR_2_o_equal_61_o")
+              (joined
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_0__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_0__))
+                (portRef O (instanceRef BIU_CORE_eu_biu_strobe_1__PWR_2_o_equal_61_o_1_1))
+              )
+            )
+            (net (rename BIU_CORE_word_cycle_byte_num_AND_34_o "BIU_CORE/word_cycle_byte_num_AND_34_o")
+              (joined
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_111))
+                (portRef O (instanceRef BIU_CORE_word_cycle_byte_num_AND_34_o1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o1_renamed_243))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_6_1_renamed_257))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4__))
+              )
+            )
+            (net (rename BIU_CORE_s_bits_2__eu_biu_req_code_4__mux_123_OUT_0_ "BIU_CORE/s_bits[2]_eu_biu_req_code[4]_mux_123_OUT<0>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_s_bits_0))
+                (portRef O (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT1))
+              )
+            )
+            (net (rename BIU_CORE_s_bits_2__eu_biu_req_code_4__mux_123_OUT_1_ "BIU_CORE/s_bits[2]_eu_biu_req_code[4]_mux_123_OUT<1>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_s_bits_1))
+                (portRef O (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT2))
+              )
+            )
+            (net (rename BIU_CORE_s_bits_2__eu_biu_req_code_4__mux_123_OUT_2_ "BIU_CORE/s_bits[2]_eu_biu_req_code[4]_mux_123_OUT<2>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_s_bits_2))
+                (portRef O (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT3))
+              )
+            )
+            (net (rename BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_11_o "BIU_CORE/eu_biu_req_caught_eu_biu_req_code[4]_AND_11_o")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_0__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_1__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_2__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_3__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_4__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_5__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_6__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_7__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_8__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_9__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_10__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_11__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_12__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_13__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_14__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_15__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_0__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_1__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_2__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_3__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_4__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_5__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_6__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_7__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_8__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_9__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_10__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_11__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_12__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_13__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_14__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_15__))
+                (portRef O (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_11_o1))
+                (portRef I3 (instanceRef BIU_CORE__n0870_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n0889_inv1))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_0_ "BIU_CORE/pfq_top_byte_int<0>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_top_byte_int_d1_0))
+                (portRef O (instanceRef BIU_CORE_Mmux_pfq_top_byte_int11))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_1_ "BIU_CORE/pfq_top_byte_int<1>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_top_byte_int_d1_1))
+                (portRef O (instanceRef BIU_CORE_Mmux_pfq_top_byte_int21))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_2_ "BIU_CORE/pfq_top_byte_int<2>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_top_byte_int_d1_2))
+                (portRef O (instanceRef BIU_CORE_Mmux_pfq_top_byte_int31))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_3_ "BIU_CORE/pfq_top_byte_int<3>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_top_byte_int_d1_3))
+                (portRef O (instanceRef BIU_CORE_Mmux_pfq_top_byte_int41))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_4_ "BIU_CORE/pfq_top_byte_int<4>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_top_byte_int_d1_4))
+                (portRef O (instanceRef BIU_CORE_Mmux_pfq_top_byte_int51))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_5_ "BIU_CORE/pfq_top_byte_int<5>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_top_byte_int_d1_5))
+                (portRef O (instanceRef BIU_CORE_Mmux_pfq_top_byte_int61))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_6_ "BIU_CORE/pfq_top_byte_int<6>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_top_byte_int_d1_6))
+                (portRef O (instanceRef BIU_CORE_Mmux_pfq_top_byte_int71))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_7_ "BIU_CORE/pfq_top_byte_int<7>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_top_byte_int_d1_7))
+                (portRef O (instanceRef BIU_CORE_Mmux_pfq_top_byte_int81))
+              )
+            )
+            (net (rename BIU_CORE_clk_d4_clk_d2_AND_30_o "BIU_CORE/clk_d4_clk_d2_AND_30_o")
+              (joined
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_111))
+                (portRef O (instanceRef BIU_CORE_clk_d4_clk_d2_AND_30_o1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_3_renamed_262))
+                (portRef I4 (instanceRef BIU_CORE__n0897_inv1))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_0_ "BIU_CORE/biu_muxed_segment<0>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_4__))
+                (portRef O (instanceRef BIU_CORE_mux161))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_1_ "BIU_CORE/biu_muxed_segment<1>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_5__))
+                (portRef O (instanceRef BIU_CORE_mux1061))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_2_ "BIU_CORE/biu_muxed_segment<2>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_6__))
+                (portRef O (instanceRef BIU_CORE_mux1071))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_3_ "BIU_CORE/biu_muxed_segment<3>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_7__))
+                (portRef O (instanceRef BIU_CORE_mux1081))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_4_ "BIU_CORE/biu_muxed_segment<4>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_8__))
+                (portRef O (instanceRef BIU_CORE_mux1091))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_5_ "BIU_CORE/biu_muxed_segment<5>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_9__))
+                (portRef O (instanceRef BIU_CORE_mux10111))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_6_ "BIU_CORE/biu_muxed_segment<6>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_10__))
+                (portRef O (instanceRef BIU_CORE_mux10121))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_7_ "BIU_CORE/biu_muxed_segment<7>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_11__))
+                (portRef O (instanceRef BIU_CORE_mux10131))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_8_ "BIU_CORE/biu_muxed_segment<8>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_12__))
+                (portRef O (instanceRef BIU_CORE_mux10141))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_9_ "BIU_CORE/biu_muxed_segment<9>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_13__))
+                (portRef O (instanceRef BIU_CORE_mux10151))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_10_ "BIU_CORE/biu_muxed_segment<10>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_14__))
+                (portRef O (instanceRef BIU_CORE_mux171))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_11_ "BIU_CORE/biu_muxed_segment<11>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_15__))
+                (portRef O (instanceRef BIU_CORE_mux1011))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_12_ "BIU_CORE/biu_muxed_segment<12>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_16__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_16__))
+                (portRef O (instanceRef BIU_CORE_mux1021))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_13_ "BIU_CORE/biu_muxed_segment<13>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_17__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_17__))
+                (portRef O (instanceRef BIU_CORE_mux1031))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_14_ "BIU_CORE/biu_muxed_segment<14>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_18__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_18__))
+                (portRef O (instanceRef BIU_CORE_mux1041))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15_ "BIU_CORE/biu_muxed_segment<15>")
+              (joined
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_xor_19__))
+                (portRef O (instanceRef BIU_CORE_mux1051))
+              )
+            )
+            (net (rename BIU_CORE_biu_segment_0_ "BIU_CORE/biu_segment<0>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_mux171))
+                (portRef I0 (instanceRef BIU_CORE_mux161))
+                (portRef I0 (instanceRef BIU_CORE_mux1091))
+                (portRef I0 (instanceRef BIU_CORE_mux1081))
+                (portRef I0 (instanceRef BIU_CORE_mux1071))
+                (portRef I0 (instanceRef BIU_CORE_mux1061))
+                (portRef I0 (instanceRef BIU_CORE_mux1051))
+                (portRef I0 (instanceRef BIU_CORE_mux1041))
+                (portRef I0 (instanceRef BIU_CORE_mux1031))
+                (portRef I0 (instanceRef BIU_CORE_mux1021))
+                (portRef I0 (instanceRef BIU_CORE_mux10151))
+                (portRef I0 (instanceRef BIU_CORE_mux10141))
+                (portRef I0 (instanceRef BIU_CORE_mux10131))
+                (portRef I0 (instanceRef BIU_CORE_mux10121))
+                (portRef I0 (instanceRef BIU_CORE_mux10111))
+                (portRef I0 (instanceRef BIU_CORE_mux1011))
+                (portRef O (instanceRef BIU_CORE_Mmux_biu_segment11))
+              )
+            )
+            (net (rename BIU_CORE_biu_segment_1_ "BIU_CORE/biu_segment<1>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_mux171))
+                (portRef I1 (instanceRef BIU_CORE_mux161))
+                (portRef I1 (instanceRef BIU_CORE_mux1091))
+                (portRef I1 (instanceRef BIU_CORE_mux1081))
+                (portRef I1 (instanceRef BIU_CORE_mux1071))
+                (portRef I1 (instanceRef BIU_CORE_mux1061))
+                (portRef I1 (instanceRef BIU_CORE_mux1051))
+                (portRef I1 (instanceRef BIU_CORE_mux1041))
+                (portRef I1 (instanceRef BIU_CORE_mux1031))
+                (portRef I1 (instanceRef BIU_CORE_mux1021))
+                (portRef I1 (instanceRef BIU_CORE_mux10151))
+                (portRef I1 (instanceRef BIU_CORE_mux10141))
+                (portRef I1 (instanceRef BIU_CORE_mux10131))
+                (portRef I1 (instanceRef BIU_CORE_mux10121))
+                (portRef I1 (instanceRef BIU_CORE_mux10111))
+                (portRef I1 (instanceRef BIU_CORE_mux1011))
+                (portRef O (instanceRef BIU_CORE_Mmux_biu_segment21))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_0 "BIU_CORE/addr_out_temp_0")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_0_renamed_38))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_3))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_0__))
+                (portRef I (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_lut_0__INV_0))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_1 "BIU_CORE/addr_out_temp_1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_1_renamed_37))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_3))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_1__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_1__rt_renamed_362))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_2 "BIU_CORE/addr_out_temp_2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_2_renamed_36))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_3))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_2__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_2__rt_renamed_361))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_3 "BIU_CORE/addr_out_temp_3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_3_renamed_35))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_3))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_3__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_3__rt_renamed_360))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_4 "BIU_CORE/addr_out_temp_4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_4_renamed_34))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_5))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_4__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_4__rt_renamed_359))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_5 "BIU_CORE/addr_out_temp_5")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_5_renamed_33))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_5))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_5__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_5__rt_renamed_358))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_6 "BIU_CORE/addr_out_temp_6")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_6_renamed_32))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_5))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_6__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_6__rt_renamed_357))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_7 "BIU_CORE/addr_out_temp_7")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_7_renamed_31))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_5))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_7__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_7__rt_renamed_356))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_8 "BIU_CORE/addr_out_temp_8")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_8_renamed_30))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_5))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_8__rt_renamed_355))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_8_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_9 "BIU_CORE/addr_out_temp_9")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_9_renamed_29))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_5_renamed_304))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_9__rt_renamed_354))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_9_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_10 "BIU_CORE/addr_out_temp_10")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_10_renamed_28))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_5))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_10__rt_renamed_353))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_10_2))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_11 "BIU_CORE/addr_out_temp_11")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_11_renamed_27))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_5))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_11__rt_renamed_352))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_11_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_12 "BIU_CORE/addr_out_temp_12")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_12_renamed_26))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_5))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_12__rt_renamed_351))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_12_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_13 "BIU_CORE/addr_out_temp_13")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_13_renamed_25))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_5))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_13__rt_renamed_350))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_13_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_14 "BIU_CORE/addr_out_temp_14")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_14_renamed_24))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_5))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_14__rt_renamed_349))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_14_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15 "BIU_CORE/addr_out_temp_15")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_15_renamed_23))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_5))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_15__rt_renamed_372))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_15_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_16 "BIU_CORE/addr_out_temp_16")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_16_renamed_22))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_4))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_16_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_17 "BIU_CORE/addr_out_temp_17")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_17_renamed_21))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_4))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_17_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_18 "BIU_CORE/addr_out_temp_18")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_18_renamed_20))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_4))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_18_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_19 "BIU_CORE/addr_out_temp_19")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_19_renamed_19))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_4_renamed_256))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_19_1))
+              )
+            )
+            (net (rename BIU_CORE_word_cycle "BIU_CORE/word_cycle")
+              (joined
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1))
+                (portRef I0 (instanceRef BIU_CORE_word_cycle_byte_num_AND_34_o1))
+                (portRef Q (instanceRef BIU_CORE_word_cycle_renamed_378))
+                (portRef I2 (instanceRef BIU_CORE_word_cycle_rstpot1_renamed_383))
+                (portRef I0 (instanceRef BIU_CORE_s_bits_2__word_cycle_AND_33_o1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_0__SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_1__SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_2__SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_3__SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_4__SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_5__SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_6__SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_7__SW0))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT21))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT31))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT41))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT51))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT61))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT71))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT151))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT161))
+              )
+            )
+            (net (rename BIU_CORE_eu_biu_req_caught "BIU_CORE/eu_biu_req_caught")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_11_o1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_3_renamed_249))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_3_renamed_251))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_3_renamed_253))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_3_renamed_255))
+                (portRef I4 (instanceRef BIU_CORE__n0910_inv_renamed_258))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o2_SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_2_renamed_261))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT3))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_5))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_5))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_5))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_5))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_5))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_5))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_5))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_5))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_5))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_5))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_5))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_5_renamed_304))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT1))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT2))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_1_renamed_307))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_1_renamed_309))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_1_renamed_311))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_1_renamed_313))
+                (portRef Q (instanceRef BIU_CORE_eu_biu_req_caught_renamed_345))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_31))
+                (portRef I1 (instanceRef BIU_CORE__n09783_SW0))
+                (portRef I4 (instanceRef BIU_CORE_word_cycle_rstpot1_renamed_383))
+                (portRef I0 (instanceRef BIU_CORE_eu_biu_req_caught_glue_set_renamed_385))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_12_renamed_388))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_1_renamed_389))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_1_renamed_390))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_1_renamed_391))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_1_renamed_392))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_1_renamed_393))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_1_renamed_394))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_1_renamed_395))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_1_renamed_396))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_1_renamed_397))
+                (portRef I0 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_11_o_inv1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_1_renamed_399))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_1_renamed_400))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_1_renamed_401))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_21))
+              )
+            )
+            (net (rename BIU_CORE_s_bits_1_ "BIU_CORE/s_bits<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_s_bits_1))
+                (portRef D (instanceRef BIU_CORE_dtr_int_renamed_3))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_182_o1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__rd_n_int_Select_180_o1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o1_renamed_243))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_161_o_SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_184_o_SW0))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_174_o_renamed_265))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT2))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o_SW0))
+                (portRef I3 (instanceRef BIU_CORE_s_bits_2__word_cycle_AND_33_o1))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT21))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT31))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT41))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT51))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT61))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT71))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT151))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT161))
+              )
+            )
+            (net (rename BIU_CORE_s_bits_2_ "BIU_CORE/s_bits<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_s_bits_2))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o1_renamed_243))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_161_o_SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_184_o_SW0))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT3))
+                (portRef I4 (instanceRef BIU_CORE_s_bits_2__word_cycle_AND_33_o1))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT21))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT31))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT41))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT51))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT61))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT71))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT151))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT161))
+                (portRef I (instanceRef BIU_CORE_s_bits_2__INV_27_o1_INV_0))
+              )
+            )
+            (net (rename BIU_CORE_dtr_int "BIU_CORE/dtr_int")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_dtr_int_renamed_3))
+                (portRef D (instanceRef BIU_CORE_DTR_renamed_2))
+              )
+            )
+            (net (rename BIU_CORE_iom_int "BIU_CORE/iom_int")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_iom_int_renamed_39))
+                (portRef D (instanceRef BIU_CORE_IOM_renamed_15))
+              )
+            )
+            (net (rename BIU_CORE_latched_data_in_0_ "BIU_CORE/latched_data_in<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_latched_data_in_0))
+                (portRef D (instanceRef BIU_CORE_pfq_entry0_0))
+                (portRef D (instanceRef BIU_CORE_pfq_entry1_0))
+                (portRef D (instanceRef BIU_CORE_pfq_entry2_0))
+                (portRef D (instanceRef BIU_CORE_pfq_entry3_0))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT17))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT151))
+              )
+            )
+            (net (rename BIU_CORE_latched_data_in_1_ "BIU_CORE/latched_data_in<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_latched_data_in_1))
+                (portRef D (instanceRef BIU_CORE_pfq_entry0_1))
+                (portRef D (instanceRef BIU_CORE_pfq_entry1_1))
+                (portRef D (instanceRef BIU_CORE_pfq_entry2_1))
+                (portRef D (instanceRef BIU_CORE_pfq_entry3_1))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT81))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT161))
+              )
+            )
+            (net (rename BIU_CORE_latched_data_in_2_ "BIU_CORE/latched_data_in<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_latched_data_in_2))
+                (portRef D (instanceRef BIU_CORE_pfq_entry0_2))
+                (portRef D (instanceRef BIU_CORE_pfq_entry1_2))
+                (portRef D (instanceRef BIU_CORE_pfq_entry2_2))
+                (portRef D (instanceRef BIU_CORE_pfq_entry3_2))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT91))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT21))
+              )
+            )
+            (net (rename BIU_CORE_latched_data_in_3_ "BIU_CORE/latched_data_in<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_latched_data_in_3))
+                (portRef D (instanceRef BIU_CORE_pfq_entry0_3))
+                (portRef D (instanceRef BIU_CORE_pfq_entry1_3))
+                (portRef D (instanceRef BIU_CORE_pfq_entry2_3))
+                (portRef D (instanceRef BIU_CORE_pfq_entry3_3))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT101))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT31))
+              )
+            )
+            (net (rename BIU_CORE_latched_data_in_4_ "BIU_CORE/latched_data_in<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_latched_data_in_4))
+                (portRef D (instanceRef BIU_CORE_pfq_entry0_4))
+                (portRef D (instanceRef BIU_CORE_pfq_entry1_4))
+                (portRef D (instanceRef BIU_CORE_pfq_entry2_4))
+                (portRef D (instanceRef BIU_CORE_pfq_entry3_4))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT111))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT41))
+              )
+            )
+            (net (rename BIU_CORE_latched_data_in_5_ "BIU_CORE/latched_data_in<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_latched_data_in_5))
+                (portRef D (instanceRef BIU_CORE_pfq_entry0_5))
+                (portRef D (instanceRef BIU_CORE_pfq_entry1_5))
+                (portRef D (instanceRef BIU_CORE_pfq_entry2_5))
+                (portRef D (instanceRef BIU_CORE_pfq_entry3_5))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT121))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT51))
+              )
+            )
+            (net (rename BIU_CORE_latched_data_in_6_ "BIU_CORE/latched_data_in<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_latched_data_in_6))
+                (portRef D (instanceRef BIU_CORE_pfq_entry0_6))
+                (portRef D (instanceRef BIU_CORE_pfq_entry1_6))
+                (portRef D (instanceRef BIU_CORE_pfq_entry2_6))
+                (portRef D (instanceRef BIU_CORE_pfq_entry3_6))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT131))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT61))
+              )
+            )
+            (net (rename BIU_CORE_latched_data_in_7_ "BIU_CORE/latched_data_in<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_latched_data_in_7))
+                (portRef D (instanceRef BIU_CORE_pfq_entry0_7))
+                (portRef D (instanceRef BIU_CORE_pfq_entry1_7))
+                (portRef D (instanceRef BIU_CORE_pfq_entry2_7))
+                (portRef D (instanceRef BIU_CORE_pfq_entry3_7))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT141))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT71))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_8_ "BIU_CORE/biu_return_data_int<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_8))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_8_renamed_416))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_9_ "BIU_CORE/biu_return_data_int<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_9))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_9_renamed_415))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_10_ "BIU_CORE/biu_return_data_int<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_10))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_10_renamed_414))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_11_ "BIU_CORE/biu_return_data_int<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_11))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_11_renamed_413))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_12_ "BIU_CORE/biu_return_data_int<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_12))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_12_renamed_412))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_13_ "BIU_CORE/biu_return_data_int<13>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_13))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_13_renamed_411))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_14_ "BIU_CORE/biu_return_data_int<14>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_14))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_14_renamed_410))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_15_ "BIU_CORE/biu_return_data_int<15>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_15))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_15_renamed_409))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_0_ "BIU_CORE/biu_return_data_int<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_0))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT17))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_0_renamed_424))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_1_ "BIU_CORE/biu_return_data_int<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_1))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT81))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_1_renamed_423))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_2_ "BIU_CORE/biu_return_data_int<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_2))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT91))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_2_renamed_422))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_3_ "BIU_CORE/biu_return_data_int<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_3))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT101))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_3_renamed_419))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_4_ "BIU_CORE/biu_return_data_int<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_4))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT111))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_4_renamed_421))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_5_ "BIU_CORE/biu_return_data_int<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_5))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT121))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_5_renamed_420))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_6_ "BIU_CORE/biu_return_data_int<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_6))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT131))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_6_renamed_418))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_7_ "BIU_CORE/biu_return_data_int<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_7))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT141))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_7_renamed_417))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_3_ "BIU_CORE/pfq_addr_in<3>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_3__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_3))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_2_renamed_314))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_4_ "BIU_CORE/pfq_addr_in<4>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_4__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_4))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_4__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_5_ "BIU_CORE/pfq_addr_in<5>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_5__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_5))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_5__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_6_ "BIU_CORE/pfq_addr_in<6>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_6__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_6))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_6__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_7_ "BIU_CORE/pfq_addr_in<7>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_7__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_7))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_7__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_8_ "BIU_CORE/pfq_addr_in<8>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_8__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_8))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_8__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_9_ "BIU_CORE/pfq_addr_in<9>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_9__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_9))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_9__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_10_ "BIU_CORE/pfq_addr_in<10>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_10__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_10))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_10__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_11_ "BIU_CORE/pfq_addr_in<11>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_11__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_11))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_11__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_12_ "BIU_CORE/pfq_addr_in<12>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_12__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_12))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_12__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_13_ "BIU_CORE/pfq_addr_in<13>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_13__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_13))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_13__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_14_ "BIU_CORE/pfq_addr_in<14>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_14__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_14))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_14__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_15_ "BIU_CORE/pfq_addr_in<15>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_15__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_15))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_15__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_0_ "BIU_CORE/pfq_addr_in<0>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_0__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_0))
+                (portRef I2 (instanceRef BIU_CORE__n0886_inv1))
+                (portRef I1 (instanceRef BIU_CORE__n0882_inv1))
+                (portRef I2 (instanceRef BIU_CORE__n0878_inv1))
+                (portRef I2 (instanceRef BIU_CORE__n0874_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n0910_inv_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_2_renamed_308))
+                (portRef I2 (instanceRef BIU_CORE_pfq_full_GND_10_o_equal_118_o1))
+                (portRef I4 (instanceRef BIU_CORE_pfq_empty1))
+                (portRef I3 (instanceRef EU_CORE_system_signals_7_1))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_1_ "BIU_CORE/pfq_addr_in<1>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_1__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_1))
+                (portRef I1 (instanceRef BIU_CORE__n0886_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n0882_inv1))
+                (portRef I1 (instanceRef BIU_CORE__n0878_inv1))
+                (portRef I1 (instanceRef BIU_CORE__n0874_inv1))
+                (portRef I1 (instanceRef BIU_CORE__n0910_inv_renamed_258))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_2_renamed_310))
+                (portRef I0 (instanceRef BIU_CORE_pfq_full_GND_10_o_equal_118_o1))
+                (portRef I2 (instanceRef BIU_CORE_pfq_empty1))
+                (portRef I2 (instanceRef EU_CORE_system_signals_7_1))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_2_ "BIU_CORE/pfq_addr_in<2>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_2__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_2))
+                (portRef I0 (instanceRef BIU_CORE_n00331_renamed_240))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_2_renamed_312))
+                (portRef I4 (instanceRef BIU_CORE_pfq_full_GND_10_o_equal_118_o1))
+                (portRef I0 (instanceRef BIU_CORE_pfq_empty1))
+                (portRef I0 (instanceRef EU_CORE_system_signals_7_1))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry3_0_ "BIU_CORE/pfq_entry3<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry3_0))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int11))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry3_1_ "BIU_CORE/pfq_entry3<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry3_1))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int21))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry3_2_ "BIU_CORE/pfq_entry3<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry3_2))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int31))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry3_3_ "BIU_CORE/pfq_entry3<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry3_3))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int41))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry3_4_ "BIU_CORE/pfq_entry3<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry3_4))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int51))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry3_5_ "BIU_CORE/pfq_entry3<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry3_5))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int61))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry3_6_ "BIU_CORE/pfq_entry3<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry3_6))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int71))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry3_7_ "BIU_CORE/pfq_entry3<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry3_7))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int81))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry2_0_ "BIU_CORE/pfq_entry2<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry2_0))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int11))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry2_1_ "BIU_CORE/pfq_entry2<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry2_1))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int21))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry2_2_ "BIU_CORE/pfq_entry2<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry2_2))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int31))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry2_3_ "BIU_CORE/pfq_entry2<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry2_3))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int41))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry2_4_ "BIU_CORE/pfq_entry2<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry2_4))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int51))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry2_5_ "BIU_CORE/pfq_entry2<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry2_5))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int61))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry2_6_ "BIU_CORE/pfq_entry2<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry2_6))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int71))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry2_7_ "BIU_CORE/pfq_entry2<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry2_7))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int81))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry1_0_ "BIU_CORE/pfq_entry1<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry1_0))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int11))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry1_1_ "BIU_CORE/pfq_entry1<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry1_1))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int21))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry1_2_ "BIU_CORE/pfq_entry1<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry1_2))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int31))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry1_3_ "BIU_CORE/pfq_entry1<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry1_3))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int41))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry1_4_ "BIU_CORE/pfq_entry1<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry1_4))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int51))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry1_5_ "BIU_CORE/pfq_entry1<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry1_5))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int61))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry1_6_ "BIU_CORE/pfq_entry1<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry1_6))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int71))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry1_7_ "BIU_CORE/pfq_entry1<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry1_7))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int81))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry0_0_ "BIU_CORE/pfq_entry0<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry0_0))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int11))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry0_1_ "BIU_CORE/pfq_entry0<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry0_1))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int21))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry0_2_ "BIU_CORE/pfq_entry0<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry0_2))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int31))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry0_3_ "BIU_CORE/pfq_entry0<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry0_3))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int41))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry0_4_ "BIU_CORE/pfq_entry0<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry0_4))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int51))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry0_5_ "BIU_CORE/pfq_entry0<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry0_5))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int61))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry0_6_ "BIU_CORE/pfq_entry0<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry0_6))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int71))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry0_7_ "BIU_CORE/pfq_entry0<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry0_7))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int81))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_3_ "BIU_CORE/pfq_addr_out<3>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_3))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_3__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_3))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_1_renamed_313))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_4_ "BIU_CORE/pfq_addr_out<4>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_4))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_4__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_4))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_4__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_5_ "BIU_CORE/pfq_addr_out<5>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_5))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_5__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_5))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_5__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_6_ "BIU_CORE/pfq_addr_out<6>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_6))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_6__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_6))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_6__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_7_ "BIU_CORE/pfq_addr_out<7>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_7))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_7__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_7))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_7__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_8_ "BIU_CORE/pfq_addr_out<8>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_8))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_8__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_8))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_8__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_9_ "BIU_CORE/pfq_addr_out<9>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_9))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_9__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_9))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_9__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_10_ "BIU_CORE/pfq_addr_out<10>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_10))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_10__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_10))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_10__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_11_ "BIU_CORE/pfq_addr_out<11>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_11))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_11__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_11))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_11__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_12_ "BIU_CORE/pfq_addr_out<12>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_12))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_12__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_12))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_12__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_13_ "BIU_CORE/pfq_addr_out<13>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_13))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_13__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_13))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_13__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_14_ "BIU_CORE/pfq_addr_out<14>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_14))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_14__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_14))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_14__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_15_ "BIU_CORE/pfq_addr_out<15>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_15))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_15__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_15))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_15__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_2_ "BIU_CORE/pfq_addr_out<2>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_2))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_2__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_2))
+                (portRef I1 (instanceRef BIU_CORE_n00331_renamed_240))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_1_renamed_311))
+                (portRef I5 (instanceRef BIU_CORE_pfq_full_GND_10_o_equal_118_o1))
+                (portRef I1 (instanceRef BIU_CORE_pfq_empty1))
+                (portRef I1 (instanceRef EU_CORE_system_signals_7_1))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_0_ "BIU_CORE/pfq_addr_out<0>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_0))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_0__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_0))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int81))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int71))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int61))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int51))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int41))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int31))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int21))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int11))
+                (portRef I1 (instanceRef BIU_CORE__n0910_inv_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_1_renamed_307))
+                (portRef I3 (instanceRef BIU_CORE_pfq_full_GND_10_o_equal_118_o1))
+                (portRef I5 (instanceRef BIU_CORE_pfq_empty1))
+                (portRef I5 (instanceRef EU_CORE_system_signals_7_1))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_1_ "BIU_CORE/pfq_addr_out<1>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_1))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_1__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_1))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int81))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int71))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int61))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int51))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int41))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int31))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int21))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int11))
+                (portRef I2 (instanceRef BIU_CORE__n0910_inv_renamed_258))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_1_renamed_309))
+                (portRef I1 (instanceRef BIU_CORE_pfq_full_GND_10_o_equal_118_o1))
+                (portRef I3 (instanceRef BIU_CORE_pfq_empty1))
+                (portRef I4 (instanceRef EU_CORE_system_signals_7_1))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_0_ "BIU_CORE/clock_cycle_counter<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_0))
+                (portRef I1 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_1_renamed_316))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_0__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_1_ "BIU_CORE/clock_cycle_counter<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_1))
+                (portRef I0 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_1_renamed_316))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_1__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_2_ "BIU_CORE/clock_cycle_counter<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_2))
+                (portRef I2 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_1_renamed_316))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_2__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_3_ "BIU_CORE/clock_cycle_counter<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_3))
+                (portRef I3 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_1_renamed_316))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_3__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_4_ "BIU_CORE/clock_cycle_counter<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_4))
+                (portRef I4 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_1_renamed_316))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_4__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_5_ "BIU_CORE/clock_cycle_counter<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_5))
+                (portRef I5 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_1_renamed_316))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_5__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_6_ "BIU_CORE/clock_cycle_counter<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_6))
+                (portRef I1 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_2))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_6__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_7_ "BIU_CORE/clock_cycle_counter<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_7))
+                (portRef I0 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_2))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_7__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_8_ "BIU_CORE/clock_cycle_counter<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_8))
+                (portRef I2 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_2))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_8__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_9_ "BIU_CORE/clock_cycle_counter<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_9))
+                (portRef I3 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_2))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_9__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_10_ "BIU_CORE/clock_cycle_counter<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_10))
+                (portRef I4 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_2))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_10__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_11_ "BIU_CORE/clock_cycle_counter<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_11))
+                (portRef I5 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_2))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_11__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_12_ "BIU_CORE/clock_cycle_counter<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_12))
+                (portRef I1 (instanceRef BIU_CORE__n0867_inv1))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_12__))
+                (portRef I0 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_3))
+              )
+            )
+            (net (rename BIU_CORE_den_int "BIU_CORE/den_int")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_den_int_renamed_40))
+                (portRef D (instanceRef BIU_CORE_DEN_renamed_11))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o_renamed_315))
+              )
+            )
+            (net (rename BIU_CORE_wr_n_int "BIU_CORE/wr_n_int")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_wr_n_int_renamed_41))
+                (portRef D (instanceRef BIU_CORE_WR_n_renamed_12))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_182_o1))
+              )
+            )
+            (net (rename BIU_CORE_rd_n_int "BIU_CORE/rd_n_int")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_rd_n_int_renamed_42))
+                (portRef D (instanceRef BIU_CORE_RD_n_renamed_14))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__rd_n_int_Select_180_o1))
+              )
+            )
+            (net (rename BIU_CORE_inta_n_int "BIU_CORE/inta_n_int")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_inta_n_int_renamed_43))
+                (portRef D (instanceRef BIU_CORE_INTA_n_renamed_13))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_184_o_renamed_264))
+              )
+            )
+            (net (rename BIU_CORE_clk_d1 "BIU_CORE/clk_d1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clk_d1_renamed_44))
+                (portRef D (instanceRef BIU_CORE_clk_d2_renamed_18))
+              )
+            )
+            (net (rename BIU_CORE_ale_int "BIU_CORE/ale_int")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_ale_int_renamed_45))
+                (portRef D (instanceRef BIU_CORE_ALE_renamed_10))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__ale_int_Select_176_o1))
+              )
+            )
+            (net (rename BIU_CORE_intr_d3 "BIU_CORE/intr_d3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_intr_d3_renamed_7))
+                (portRef I4 (instanceRef BIU_CORE_BIU_INTR_rstpot_renamed_398))
+              )
+            )
+            (net (rename BIU_CORE_intr_d2 "BIU_CORE/intr_d2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_intr_d2_renamed_16))
+                (portRef D (instanceRef BIU_CORE_intr_d3_renamed_7))
+              )
+            )
+            (net (rename BIU_CORE_intr_d1 "BIU_CORE/intr_d1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_intr_d1_renamed_47))
+                (portRef D (instanceRef BIU_CORE_intr_d2_renamed_16))
+              )
+            )
+            (net (rename BIU_CORE_byte_num "BIU_CORE/byte_num")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_byte_num_renamed_48))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1))
+                (portRef I1 (instanceRef BIU_CORE_word_cycle_byte_num_AND_34_o1))
+                (portRef I1 (instanceRef BIU_CORE_s_bits_2__word_cycle_AND_33_o1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_0__SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_1__SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_2__SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_3__SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_4__SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_5__SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_6__SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_7__SW0))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT21))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT31))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT41))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT51))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT61))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT71))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT151))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_10_o_latched_data_in_7__mux_139_OUT161))
+              )
+            )
+            (net (rename BIU_CORE_eu_biu_req_d1 "BIU_CORE/eu_biu_req_d1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_biu_req_d1_renamed_49))
+                (portRef I3 (instanceRef BIU_CORE_eu_biu_req_caught_glue_set_renamed_385))
+                (portRef I1 (instanceRef EU_CORE_biu_done_caught_glue_set_renamed_403))
+              )
+            )
+            (net (rename BIU_CORE_ready_d1 "BIU_CORE/ready_d1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_ready_d1_renamed_50))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW1))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW2))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_7_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_3_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW2))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_4))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW3))
+              )
+            )
+            (net (rename BIU_CORE_pfq_write "BIU_CORE/pfq_write")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_write_renamed_52))
+                (portRef I1 (instanceRef BIU_CORE__n0889_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n0886_inv1))
+                (portRef I2 (instanceRef BIU_CORE__n0882_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n0878_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n0874_inv1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_161_o_renamed_263))
+              )
+            )
+            (net (rename BIU_CORE_nmi_d5 "BIU_CORE/nmi_d5")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_nmi_d5_renamed_4))
+                (portRef I3 (instanceRef BIU_CORE_nmi_caught_glue_set_renamed_386))
+              )
+            )
+            (net (rename BIU_CORE_nmi_d4 "BIU_CORE/nmi_d4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_nmi_d4_renamed_5))
+                (portRef D (instanceRef BIU_CORE_nmi_d5_renamed_4))
+                (portRef I2 (instanceRef BIU_CORE_nmi_caught_glue_set_renamed_386))
+              )
+            )
+            (net (rename BIU_CORE_nmi_d3 "BIU_CORE/nmi_d3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_nmi_d3_renamed_8))
+                (portRef D (instanceRef BIU_CORE_nmi_d4_renamed_5))
+                (portRef I1 (instanceRef BIU_CORE_nmi_caught_glue_set_renamed_386))
+              )
+            )
+            (net (rename BIU_CORE_nmi_d2 "BIU_CORE/nmi_d2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_nmi_d2_renamed_17))
+                (portRef D (instanceRef BIU_CORE_nmi_d3_renamed_8))
+                (portRef I0 (instanceRef BIU_CORE_nmi_caught_glue_set_renamed_386))
+              )
+            )
+            (net (rename BIU_CORE_nmi_d1 "BIU_CORE/nmi_d1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_nmi_d1_renamed_53))
+                (portRef D (instanceRef BIU_CORE_nmi_d2_renamed_17))
+              )
+            )
+            (net (rename BIU_CORE_clk_d4 "BIU_CORE/clk_d4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clk_d4_renamed_6))
+                (portRef I2 (instanceRef BIU_CORE_clk_d4_clk_d2_AND_30_o1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW0))
+                (portRef I1 (instanceRef BIU_CORE_BIU_INTR_rstpot_renamed_398))
+              )
+            )
+            (net (rename BIU_CORE_clk_d3 "BIU_CORE/clk_d3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clk_d3_renamed_9))
+                (portRef D (instanceRef BIU_CORE_clk_d4_renamed_6))
+                (portRef I1 (instanceRef BIU_CORE_clk_d4_clk_d2_AND_30_o1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW0))
+                (portRef I2 (instanceRef BIU_CORE_BIU_INTR_rstpot_renamed_398))
+              )
+            )
+            (net (rename BIU_CORE_clk_d2 "BIU_CORE/clk_d2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clk_d2_renamed_18))
+                (portRef D (instanceRef BIU_CORE_clk_d3_renamed_9))
+                (portRef I0 (instanceRef BIU_CORE_clk_d4_clk_d2_AND_30_o1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW0))
+                (portRef I3 (instanceRef BIU_CORE_BIU_INTR_rstpot_renamed_398))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_0_ "BIU_CORE/eu_register_r3_d<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_0))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_0__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_0__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_1_renamed_307))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_1_ "BIU_CORE/eu_register_r3_d<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_1))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_1__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_1__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_1_renamed_309))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_2_ "BIU_CORE/eu_register_r3_d<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_2))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_2__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_2__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_1_renamed_311))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_3_ "BIU_CORE/eu_register_r3_d<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_3))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_3__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_3__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_1_renamed_313))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_4_ "BIU_CORE/eu_register_r3_d<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_4))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_4__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_4__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_4__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_4__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_4__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_3_renamed_287))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_5_ "BIU_CORE/eu_register_r3_d<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_5))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_5__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_5__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_5__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_5__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_5__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_3_renamed_290))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_6_ "BIU_CORE/eu_register_r3_d<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_6))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_6__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_6__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_6__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_6__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_6__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_3_renamed_293))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_7_ "BIU_CORE/eu_register_r3_d<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_7))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_7__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_7__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_7__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_7__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_7__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_3_renamed_296))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_8_ "BIU_CORE/eu_register_r3_d<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_8))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_8__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_8__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_8__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_8__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_8__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_3_renamed_299))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_9_ "BIU_CORE/eu_register_r3_d<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_9))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_9__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_9__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_9__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_9__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_9__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_3_renamed_302))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_10_ "BIU_CORE/eu_register_r3_d<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_10))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_10__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_10__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_10__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_10__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_10__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_3_renamed_269))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_11_ "BIU_CORE/eu_register_r3_d<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_11))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_11__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_11__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_11__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_11__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_11__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_3_renamed_272))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_12_ "BIU_CORE/eu_register_r3_d<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_12))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_12__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_12__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_12__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_12__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_12__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_3_renamed_275))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_13_ "BIU_CORE/eu_register_r3_d<13>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_13))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_13__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_13__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_13__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_13__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_13__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_3_renamed_278))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_14_ "BIU_CORE/eu_register_r3_d<14>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_14))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_14__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_14__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_14__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_14__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_14__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_3_renamed_281))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_15_ "BIU_CORE/eu_register_r3_d<15>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_15))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_15__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_15__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_15__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_lut_15__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_10_o_add_90_OUT_cy_15__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_3_renamed_284))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_0_ "BIU_CORE/biu_register_cs<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_0))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_4__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_4__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_4__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_4__))
+                (portRef I4 (instanceRef BIU_CORE_mux161))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_0_renamed_518))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_1_ "BIU_CORE/biu_register_cs<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_1))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_5__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_5__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_5__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_5__))
+                (portRef I4 (instanceRef BIU_CORE_mux1061))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_1_renamed_520))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_2_ "BIU_CORE/biu_register_cs<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_2))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_6__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_6__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_6__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_6__))
+                (portRef I4 (instanceRef BIU_CORE_mux1071))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_2_renamed_519))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_3_ "BIU_CORE/biu_register_cs<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_3))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_7__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_7__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_7__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_7__))
+                (portRef I4 (instanceRef BIU_CORE_mux1081))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_3_renamed_517))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_4_ "BIU_CORE/biu_register_cs<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_4))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_8__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_8__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_8__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_8__))
+                (portRef I4 (instanceRef BIU_CORE_mux1091))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_4_renamed_516))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_5_ "BIU_CORE/biu_register_cs<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_5))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_9__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_9__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_9__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_9__))
+                (portRef I4 (instanceRef BIU_CORE_mux10111))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_5_renamed_515))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_6_ "BIU_CORE/biu_register_cs<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_6))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_10__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_10__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_10__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_10__))
+                (portRef I4 (instanceRef BIU_CORE_mux10121))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_6_renamed_514))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_7_ "BIU_CORE/biu_register_cs<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_7))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_11__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_11__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_11__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_11__))
+                (portRef I4 (instanceRef BIU_CORE_mux10131))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_7_renamed_511))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_8_ "BIU_CORE/biu_register_cs<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_8))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_12__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_12__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_12__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_12__))
+                (portRef I4 (instanceRef BIU_CORE_mux10141))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_8_renamed_513))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_9_ "BIU_CORE/biu_register_cs<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_9))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_13__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_13__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_13__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_13__))
+                (portRef I4 (instanceRef BIU_CORE_mux10151))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_9_renamed_512))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_10_ "BIU_CORE/biu_register_cs<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_10))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_14__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_14__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_14__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_14__))
+                (portRef I4 (instanceRef BIU_CORE_mux171))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_10_renamed_510))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_11_ "BIU_CORE/biu_register_cs<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_11))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_lut_15__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_15__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_lut_15__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_15__))
+                (portRef I4 (instanceRef BIU_CORE_mux1011))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_11_renamed_509))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_12_ "BIU_CORE/biu_register_cs<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_12))
+                (portRef I4 (instanceRef BIU_CORE_mux1021))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_16__rt_renamed_365))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_16__rt_renamed_371))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_12_renamed_508))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_13_ "BIU_CORE/biu_register_cs<13>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_13))
+                (portRef I4 (instanceRef BIU_CORE_mux1031))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_17__rt_renamed_364))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_17__rt_renamed_370))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_13_renamed_507))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_14_ "BIU_CORE/biu_register_cs<14>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_14))
+                (portRef I4 (instanceRef BIU_CORE_mux1041))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_18__rt_renamed_363))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_18__rt_renamed_369))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_14_renamed_504))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15_ "BIU_CORE/biu_register_cs<15>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_15))
+                (portRef I4 (instanceRef BIU_CORE_mux1051))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_19__rt_renamed_373))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_19__rt_renamed_375))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_15_renamed_506))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_0_ "BIU_CORE/biu_register_reg<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_0))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_0_renamed_472))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_1_ "BIU_CORE/biu_register_reg<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_1))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_1_renamed_471))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_2_ "BIU_CORE/biu_register_reg<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_2))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_2_renamed_470))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_3_ "BIU_CORE/biu_register_reg<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_3))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_3_renamed_469))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_4_ "BIU_CORE/biu_register_reg<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_4))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_4_renamed_468))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_5_ "BIU_CORE/biu_register_reg<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_5))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_5_renamed_467))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_6_ "BIU_CORE/biu_register_reg<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_6))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_6_renamed_466))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_7_ "BIU_CORE/biu_register_reg<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_7))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_7_renamed_465))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_8_ "BIU_CORE/biu_register_reg<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_8))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_8_renamed_464))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_9_ "BIU_CORE/biu_register_reg<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_9))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_9_renamed_461))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_10_ "BIU_CORE/biu_register_reg<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_10))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_10_renamed_463))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_11_ "BIU_CORE/biu_register_reg<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_11))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_11_renamed_462))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_12_ "BIU_CORE/biu_register_reg<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_12))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_12_renamed_460))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_13_ "BIU_CORE/biu_register_reg<13>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_13))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_13_renamed_459))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_14_ "BIU_CORE/biu_register_reg<14>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_14))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_14_renamed_458))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_15_ "BIU_CORE/biu_register_reg<15>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_15))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_15_renamed_457))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_0_ "BIU_CORE/biu_register_rm<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_0))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_0_renamed_441))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_1_ "BIU_CORE/biu_register_rm<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_1))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_1_renamed_439))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_2_ "BIU_CORE/biu_register_rm<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_2))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_2_renamed_438))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_3_ "BIU_CORE/biu_register_rm<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_3))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_3_renamed_437))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_4_ "BIU_CORE/biu_register_rm<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_4))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_4_renamed_436))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_5_ "BIU_CORE/biu_register_rm<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_5))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_5_renamed_433))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_6_ "BIU_CORE/biu_register_rm<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_6))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_6_renamed_435))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_7_ "BIU_CORE/biu_register_rm<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_7))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_7_renamed_434))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_8_ "BIU_CORE/biu_register_rm<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_8))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_8_renamed_432))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_9_ "BIU_CORE/biu_register_rm<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_9))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_9_renamed_431))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_10_ "BIU_CORE/biu_register_rm<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_10))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_10_renamed_430))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_11_ "BIU_CORE/biu_register_rm<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_11))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_11_renamed_429))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_12_ "BIU_CORE/biu_register_rm<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_12))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_12_renamed_426))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_13_ "BIU_CORE/biu_register_rm<13>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_13))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_13_renamed_428))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_14_ "BIU_CORE/biu_register_rm<14>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_14))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_14_renamed_427))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_15_ "BIU_CORE/biu_register_rm<15>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_15))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_15_renamed_425))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_0_ "BIU_CORE/biu_register_ds<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_0))
+                (portRef I3 (instanceRef BIU_CORE_mux161))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_0_renamed_454))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_1_ "BIU_CORE/biu_register_ds<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_1))
+                (portRef I3 (instanceRef BIU_CORE_mux1061))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_1_renamed_456))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_2_ "BIU_CORE/biu_register_ds<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_2))
+                (portRef I3 (instanceRef BIU_CORE_mux1071))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_2_renamed_455))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_3_ "BIU_CORE/biu_register_ds<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_3))
+                (portRef I3 (instanceRef BIU_CORE_mux1081))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_3_renamed_453))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_4_ "BIU_CORE/biu_register_ds<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_4))
+                (portRef I3 (instanceRef BIU_CORE_mux1091))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_4_renamed_452))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_5_ "BIU_CORE/biu_register_ds<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_5))
+                (portRef I3 (instanceRef BIU_CORE_mux10111))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_5_renamed_451))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_6_ "BIU_CORE/biu_register_ds<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_6))
+                (portRef I3 (instanceRef BIU_CORE_mux10121))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_6_renamed_450))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_7_ "BIU_CORE/biu_register_ds<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_7))
+                (portRef I3 (instanceRef BIU_CORE_mux10131))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_7_renamed_447))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_8_ "BIU_CORE/biu_register_ds<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_8))
+                (portRef I3 (instanceRef BIU_CORE_mux10141))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_8_renamed_449))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_9_ "BIU_CORE/biu_register_ds<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_9))
+                (portRef I3 (instanceRef BIU_CORE_mux10151))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_9_renamed_448))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_10_ "BIU_CORE/biu_register_ds<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_10))
+                (portRef I3 (instanceRef BIU_CORE_mux171))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_10_renamed_446))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_11_ "BIU_CORE/biu_register_ds<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_11))
+                (portRef I3 (instanceRef BIU_CORE_mux1011))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_11_renamed_445))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_12_ "BIU_CORE/biu_register_ds<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_12))
+                (portRef I3 (instanceRef BIU_CORE_mux1021))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_12_renamed_444))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_13_ "BIU_CORE/biu_register_ds<13>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_13))
+                (portRef I3 (instanceRef BIU_CORE_mux1031))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_13_renamed_443))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_14_ "BIU_CORE/biu_register_ds<14>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_14))
+                (portRef I3 (instanceRef BIU_CORE_mux1041))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_14_renamed_440))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_15_ "BIU_CORE/biu_register_ds<15>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_15))
+                (portRef I3 (instanceRef BIU_CORE_mux1051))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_15_renamed_442))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_0_ "BIU_CORE/biu_register_ss<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_0))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_4__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_4__))
+                (portRef I2 (instanceRef BIU_CORE_mux161))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_0_renamed_488))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_1_ "BIU_CORE/biu_register_ss<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_1))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_5__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_5__))
+                (portRef I2 (instanceRef BIU_CORE_mux1061))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_1_renamed_487))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_2_ "BIU_CORE/biu_register_ss<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_2))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_6__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_6__))
+                (portRef I2 (instanceRef BIU_CORE_mux1071))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_2_renamed_486))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_3_ "BIU_CORE/biu_register_ss<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_3))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_7__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_7__))
+                (portRef I2 (instanceRef BIU_CORE_mux1081))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_3_renamed_483))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_4_ "BIU_CORE/biu_register_ss<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_4))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_8__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_8__))
+                (portRef I2 (instanceRef BIU_CORE_mux1091))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_4_renamed_485))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_5_ "BIU_CORE/biu_register_ss<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_5))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_9__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_9__))
+                (portRef I2 (instanceRef BIU_CORE_mux10111))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_5_renamed_484))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_6_ "BIU_CORE/biu_register_ss<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_6))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_10__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_10__))
+                (portRef I2 (instanceRef BIU_CORE_mux10121))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_6_renamed_482))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_7_ "BIU_CORE/biu_register_ss<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_7))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_11__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_11__))
+                (portRef I2 (instanceRef BIU_CORE_mux10131))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_7_renamed_481))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_8_ "BIU_CORE/biu_register_ss<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_8))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_12__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_12__))
+                (portRef I2 (instanceRef BIU_CORE_mux10141))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_8_renamed_480))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_9_ "BIU_CORE/biu_register_ss<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_9))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_13__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_13__))
+                (portRef I2 (instanceRef BIU_CORE_mux10151))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_9_renamed_479))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_10_ "BIU_CORE/biu_register_ss<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_10))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_14__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_14__))
+                (portRef I2 (instanceRef BIU_CORE_mux171))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_10_renamed_476))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_11_ "BIU_CORE/biu_register_ss<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_11))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_lut_15__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_15__))
+                (portRef I2 (instanceRef BIU_CORE_mux1011))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_11_renamed_478))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_12_ "BIU_CORE/biu_register_ss<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_12))
+                (portRef I2 (instanceRef BIU_CORE_mux1021))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_16__rt_renamed_368))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_12_renamed_477))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_13_ "BIU_CORE/biu_register_ss<13>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_13))
+                (portRef I2 (instanceRef BIU_CORE_mux1031))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_17__rt_renamed_367))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_13_renamed_475))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_14_ "BIU_CORE/biu_register_ss<14>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_14))
+                (portRef I2 (instanceRef BIU_CORE_mux1041))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_18__rt_renamed_366))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_14_renamed_474))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15_ "BIU_CORE/biu_register_ss<15>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_15))
+                (portRef I2 (instanceRef BIU_CORE_mux1051))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_19__rt_renamed_374))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_15_renamed_473))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_0_ "BIU_CORE/biu_register_es<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_0))
+                (portRef I5 (instanceRef BIU_CORE_mux161))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_0_renamed_505))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_1_ "BIU_CORE/biu_register_es<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_1))
+                (portRef I5 (instanceRef BIU_CORE_mux1061))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_1_renamed_503))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_2_ "BIU_CORE/biu_register_es<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_2))
+                (portRef I5 (instanceRef BIU_CORE_mux1071))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_2_renamed_502))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_3_ "BIU_CORE/biu_register_es<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_3))
+                (portRef I5 (instanceRef BIU_CORE_mux1081))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_3_renamed_501))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_4_ "BIU_CORE/biu_register_es<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_4))
+                (portRef I5 (instanceRef BIU_CORE_mux1091))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_4_renamed_500))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_5_ "BIU_CORE/biu_register_es<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_5))
+                (portRef I5 (instanceRef BIU_CORE_mux10111))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_5_renamed_497))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_6_ "BIU_CORE/biu_register_es<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_6))
+                (portRef I5 (instanceRef BIU_CORE_mux10121))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_6_renamed_499))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_7_ "BIU_CORE/biu_register_es<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_7))
+                (portRef I5 (instanceRef BIU_CORE_mux10131))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_7_renamed_498))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_8_ "BIU_CORE/biu_register_es<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_8))
+                (portRef I5 (instanceRef BIU_CORE_mux10141))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_8_renamed_496))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_9_ "BIU_CORE/biu_register_es<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_9))
+                (portRef I5 (instanceRef BIU_CORE_mux10151))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_9_renamed_495))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_10_ "BIU_CORE/biu_register_es<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_10))
+                (portRef I5 (instanceRef BIU_CORE_mux171))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_10_renamed_494))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_11_ "BIU_CORE/biu_register_es<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_11))
+                (portRef I5 (instanceRef BIU_CORE_mux1011))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_11_renamed_493))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_12_ "BIU_CORE/biu_register_es<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_12))
+                (portRef I5 (instanceRef BIU_CORE_mux1021))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_12_renamed_490))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_13_ "BIU_CORE/biu_register_es<13>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_13))
+                (portRef I5 (instanceRef BIU_CORE_mux1031))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_13_renamed_492))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_14_ "BIU_CORE/biu_register_es<14>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_14))
+                (portRef I5 (instanceRef BIU_CORE_mux1041))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_14_renamed_491))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_15_ "BIU_CORE/biu_register_es<15>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_15))
+                (portRef I5 (instanceRef BIU_CORE_mux1051))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_15_renamed_489))
+              )
+            )
+            (net (rename BIU_CORE_ad_in_int_0_ "BIU_CORE/ad_in_int<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_ad_in_int_0))
+                (portRef D (instanceRef BIU_CORE_latched_data_in_0))
+              )
+            )
+            (net (rename BIU_CORE_ad_in_int_1_ "BIU_CORE/ad_in_int<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_ad_in_int_1))
+                (portRef D (instanceRef BIU_CORE_latched_data_in_1))
+              )
+            )
+            (net (rename BIU_CORE_ad_in_int_2_ "BIU_CORE/ad_in_int<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_ad_in_int_2))
+                (portRef D (instanceRef BIU_CORE_latched_data_in_2))
+              )
+            )
+            (net (rename BIU_CORE_ad_in_int_3_ "BIU_CORE/ad_in_int<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_ad_in_int_3))
+                (portRef D (instanceRef BIU_CORE_latched_data_in_3))
+              )
+            )
+            (net (rename BIU_CORE_ad_in_int_4_ "BIU_CORE/ad_in_int<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_ad_in_int_4))
+                (portRef D (instanceRef BIU_CORE_latched_data_in_4))
+              )
+            )
+            (net (rename BIU_CORE_ad_in_int_5_ "BIU_CORE/ad_in_int<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_ad_in_int_5))
+                (portRef D (instanceRef BIU_CORE_latched_data_in_5))
+              )
+            )
+            (net (rename BIU_CORE_ad_in_int_6_ "BIU_CORE/ad_in_int<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_ad_in_int_6))
+                (portRef D (instanceRef BIU_CORE_latched_data_in_6))
+              )
+            )
+            (net (rename BIU_CORE_ad_in_int_7_ "BIU_CORE/ad_in_int<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_ad_in_int_7))
+                (portRef D (instanceRef BIU_CORE_latched_data_in_7))
+              )
+            )
+            (net (rename EU_CORE__n1157_0_2 "EU_CORE/_n1157<0>2")
+              (joined
+                (portRef D (instanceRef EU_CORE_eu_stall_pipeline_renamed_238))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_0))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_1))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_2))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_3))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_4))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_5))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_6))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_7))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_8))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_9))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_10))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_11))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_12))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_13))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_14))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_15))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_16))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_17))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_18))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_19))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_20))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_21))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_22))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_23))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_24))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_25))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_26))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_27))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_28))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_29))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_30))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_31))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_32))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_33))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_34))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_35))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_36))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_37))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_38))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_39))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_40))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_41))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_42))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_43))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_44))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_45))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_46))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_47))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_48))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_49))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_50))
+                (portRef CE (instanceRef EU_CORE_eu_calling_address_51))
+                (portRef O (instanceRef EU_CORE__n1157_0_2_renamed_336))
+                (portRef I2 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_12__))
+                (portRef I2 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_2__))
+                (portRef I2 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_1__))
+                (portRef I2 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_0__))
+                (portRef I3 (instanceRef EU_CORE__n1157_inv1))
+                (portRef I4 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_3__))
+                (portRef I4 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_4__))
+                (portRef I4 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_5__))
+                (portRef I4 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_6__))
+                (portRef I4 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_7__))
+                (portRef I3 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_8__))
+                (portRef I3 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_9__))
+                (portRef I3 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_10__))
+                (portRef I3 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_11__))
+              )
+            )
+            (net (rename EU_CORE__n1080_inv2 "EU_CORE/_n1080_inv2")
+              (joined
+                (portRef O (instanceRef EU_CORE__n1080_inv21))
+                (portRef I2 (instanceRef EU_CORE__n1128_inv1))
+                (portRef I3 (instanceRef EU_CORE__n1120_inv1))
+                (portRef I0 (instanceRef EU_CORE__n1112_inv1))
+                (portRef I1 (instanceRef EU_CORE__n1104_inv1))
+                (portRef I0 (instanceRef EU_CORE__n1096_inv1))
+                (portRef I3 (instanceRef EU_CORE__n1088_inv1))
+                (portRef I3 (instanceRef EU_CORE__n1080_inv1))
+              )
+            )
+            (net (rename EU_CORE__n1084_inv1 "EU_CORE/_n1084_inv1")
+              (joined
+                (portRef O (instanceRef EU_CORE__n1084_inv11))
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+                (portRef S (instanceRef EU_CORE_carry_5_1_SW1))
+                (portRef S (instanceRef EU_CORE_carry_5_1_SW2))
+                (portRef S (instanceRef EU_CORE_carry_5_1_SW3))
+                (portRef I5 (instanceRef EU_CORE_carry_5_1_SW0_F))
+                (portRef I0 (instanceRef EU_CORE_carry_5_1_SW0_G))
+                (portRef I1 (instanceRef EU_CORE_carry_7_1_SW0))
+                (portRef I1 (instanceRef EU_CORE_carry_7_1_SW1))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n0457133_SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_operand1_7_ "EU_CORE/eu_operand1<7>")
+              (joined
+                (portRef O (instanceRef EU_CORE_mux13_2_f8))
+                (portRef I0 (instanceRef EU_CORE_carry_8_1))
+                (portRef I0 (instanceRef EU_CORE_Mxor_carry_8__carry_7__XOR_142_o_xo_0_1))
+                (portRef I2 (instanceRef EU_CORE_carry_7_1_SW1))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n04571511_SW1))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045714_SW0))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045714_SW1))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045714_SW2))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045714_SW3))
+                (portRef I2 (instanceRef EU_CORE_carry_7_1_SW0))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n04571511_SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_operand1_8_ "EU_CORE/eu_operand1<8>")
+              (joined
+                (portRef O (instanceRef EU_CORE_mux14_2_f8))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n0457151))
+                (portRef I0 (instanceRef EU_CORE_carry_7_1_SW0))
+                (portRef I0 (instanceRef EU_CORE_carry_7_1_SW1))
+                (portRef I2 (instanceRef EU_CORE_Mmux_n04571511_SW0))
+                (portRef I2 (instanceRef EU_CORE_Mmux_n04571511_SW1))
+              )
+            )
+            (net (rename EU_CORE_eu_operand1_9_ "EU_CORE/eu_operand1<9>")
+              (joined
+                (portRef O (instanceRef EU_CORE_mux15_2_f8))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045716_SW0))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045716_SW1))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045716_SW3))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045716_SW2))
+                (portRef I0 (instanceRef EU_CORE_carry_9_1_SW0))
+                (portRef I0 (instanceRef EU_CORE_carry_9_1_SW1))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045723_SW0))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045723_SW1))
+                (portRef I0 (instanceRef EU_CORE_Mmux_n045754))
+                (portRef I0 (instanceRef EU_CORE_carry_13_1_SW4))
+                (portRef I0 (instanceRef EU_CORE_carry_13_1_SW5))
+              )
+            )
+            (net (rename EU_CORE_eu_operand1_10_ "EU_CORE/eu_operand1<10>")
+              (joined
+                (portRef O (instanceRef EU_CORE_eu_rom_data_19_1))
+                (portRef I4 (instanceRef EU_CORE_carry_11_1_SW1))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045722))
+                (portRef I2 (instanceRef EU_CORE_Mmux_n045724))
+                (portRef I4 (instanceRef EU_CORE_carry_11_1_SW0))
+                (portRef I2 (instanceRef EU_CORE_carry_9_1_SW0))
+                (portRef I2 (instanceRef EU_CORE_carry_9_1_SW1))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045723_SW0))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045723_SW1))
+              )
+            )
+            (net (rename EU_CORE_eu_operand1_11_ "EU_CORE/eu_operand1<11>")
+              (joined
+                (portRef O (instanceRef EU_CORE_mux2_2_f8))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045732))
+                (portRef I0 (instanceRef EU_CORE_Mmux_n045733_SW0))
+                (portRef I1 (instanceRef EU_CORE_carry_11_1_SW1))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n0457411_SW1))
+                (portRef I2 (instanceRef EU_CORE_Mmux_n045731_renamed_328))
+                (portRef I2 (instanceRef EU_CORE_carry_13_1_SW0))
+                (portRef I2 (instanceRef EU_CORE_carry_13_1_SW1))
+                (portRef I1 (instanceRef EU_CORE_carry_11_1_SW0))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n0457411_SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_operand1_12_ "EU_CORE/eu_operand1<12>")
+              (joined
+                (portRef O (instanceRef EU_CORE_mux3_2_f8))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045741))
+                (portRef I0 (instanceRef EU_CORE_carry_11_1_SW1))
+                (portRef I1 (instanceRef EU_CORE_carry_13_1_SW0))
+                (portRef I1 (instanceRef EU_CORE_carry_13_1_SW1))
+                (portRef I0 (instanceRef EU_CORE_carry_11_1_SW0))
+                (portRef I2 (instanceRef EU_CORE_Mmux_n0457411_SW0))
+                (portRef I2 (instanceRef EU_CORE_Mmux_n0457411_SW1))
+              )
+            )
+            (net (rename EU_CORE_eu_operand1_13_ "EU_CORE/eu_operand1<13>")
+              (joined
+                (portRef O (instanceRef EU_CORE_mux4_2_f8))
+                (portRef I0 (instanceRef EU_CORE_carry_13_1_SW0))
+                (portRef I0 (instanceRef EU_CORE_carry_13_1_SW1))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045763_SW0))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045763_SW1))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045751_SW0))
+                (portRef I3 (instanceRef EU_CORE_carry_13_1_SW2))
+                (portRef I3 (instanceRef EU_CORE_carry_13_1_SW3))
+              )
+            )
+            (net (rename EU_CORE_eu_operand1_14_ "EU_CORE/eu_operand1<14>")
+              (joined
+                (portRef O (instanceRef EU_CORE_eu_rom_data_19_11))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045762))
+                (portRef I1 (instanceRef EU_CORE_carry_15_1_SW0))
+                (portRef I1 (instanceRef EU_CORE_carry_15_1_SW2))
+                (portRef I5 (instanceRef EU_CORE_carry_15_1_SW4_F))
+                (portRef I5 (instanceRef EU_CORE_carry_15_1_SW5_F))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045761_renamed_317))
+                (portRef I2 (instanceRef EU_CORE_Mmux_n045764))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045763_SW0))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045763_SW1))
+                (portRef I1 (instanceRef EU_CORE_carry_15_1_SW1))
+                (portRef I1 (instanceRef EU_CORE_carry_15_1_SW3))
+              )
+            )
+            (net (rename EU_CORE_eu_operand1_15_ "EU_CORE/eu_operand1<15>")
+              (joined
+                (portRef O (instanceRef EU_CORE_eu_rom_data_19_21))
+                (portRef I1 (instanceRef EU_CORE_carry_15_1_SW4_F))
+                (portRef I1 (instanceRef EU_CORE_carry_15_1_SW5_F))
+                (portRef I2 (instanceRef EU_CORE_Mmux_n045771_SW1))
+                (portRef I0 (instanceRef EU_CORE_carry_15_1_SW0))
+                (portRef I0 (instanceRef EU_CORE_carry_15_1_SW1))
+                (portRef I0 (instanceRef EU_CORE_carry_15_1_SW2))
+                (portRef I0 (instanceRef EU_CORE_carry_15_1_SW3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__biu_done_int_Select_169_o1 "BIU_CORE/biu_state[7]_biu_done_int_Select_169_o1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o1_renamed_243))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__biu_done_int_Select_169_o3 "BIU_CORE/biu_state[7]_biu_done_int_Select_169_o3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o3_renamed_244))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o4))
+              )
+            )
+            (net N2
+              (joined
+                (portRef O (instanceRef BIU_CORE__n0988_SW0))
+                (portRef I0 (instanceRef BIU_CORE__n0988_renamed_245))
+              )
+            )
+            (net (rename BIU_CORE__n09781 "BIU_CORE/_n09781")
+              (joined
+                (portRef O (instanceRef BIU_CORE__n09781_renamed_246))
+                (portRef I5 (instanceRef BIU_CORE__n09782_renamed_247))
+              )
+            )
+            (net (rename BIU_CORE__n09782 "BIU_CORE/_n09782")
+              (joined
+                (portRef O (instanceRef BIU_CORE__n09782_renamed_247))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_31))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_21))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<3>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_2_renamed_248))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_3_renamed_249))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<3>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_3_renamed_249))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<2>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_2_renamed_250))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_3_renamed_251))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<2>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_3_renamed_251))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<1>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_2_renamed_252))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_3_renamed_253))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<1>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_3_renamed_253))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<0>1")
+              (joined
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_2_renamed_254))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_1_2_renamed_252))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_2_2_renamed_250))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_3_2_renamed_248))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<0>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_2_renamed_254))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_3_renamed_255))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<0>4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_3_renamed_255))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_4_renamed_256))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_6_1 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<6>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_6_1_renamed_257))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_6_2))
+              )
+            )
+            (net N4
+              (joined
+                (portRef O (instanceRef BIU_CORE__n0910_inv_SW0))
+                (portRef I5 (instanceRef BIU_CORE__n0910_inv_renamed_258))
+              )
+            )
+            (net N6
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o2_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_169_o2_renamed_259))
+              )
+            )
+            (net N8
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4__SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4__))
+              )
+            )
+            (net N10
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW2))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW0))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_1 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<0>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_1_renamed_260))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_2_renamed_261))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_2 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<0>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_2_renamed_261))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_3_renamed_262))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_3 "BIU_CORE/biu_state[7]_GND_10_o_select_167_OUT<0>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_3_renamed_262))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_0_4))
+              )
+            )
+            (net N12
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_161_o_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_161_o_renamed_263))
+              )
+            )
+            (net N14
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_184_o_SW0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_184_o_renamed_264))
+              )
+            )
+            (net N16
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_12_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5_12_renamed_388))
+              )
+            )
+            (net N18
+              (joined
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_174_o_renamed_265))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_174_o_SW0))
+              )
+            )
+            (net N20
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_149_o_7__SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_149_o_7__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_Select_163_o1111 "BIU_CORE/biu_state[7]_GND_10_o_Select_163_o1111")
+              (joined
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1113))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1111_renamed_381))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_10_o_Select_163_o1112 "BIU_CORE/biu_state[7]_GND_10_o_Select_163_o1112")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1112_renamed_266))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1113))
+              )
+            )
+            (net N22
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_157_o_7_1_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_10_o_equal_157_o_7_1_renamed_267))
+              )
+            )
+            (net N24
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT3_SW0))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<9>1")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_5))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_1_renamed_389))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<9>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_2_renamed_268))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_4_renamed_270))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<9>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_3_renamed_269))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_4_renamed_270))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<9>4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_4_renamed_270))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_9_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<8>1")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_5))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_1_renamed_390))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<8>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_2_renamed_271))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_4_renamed_273))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<8>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_3_renamed_272))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_4_renamed_273))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<8>4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_4_renamed_273))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_8_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<7>1")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_5))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_1_renamed_391))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<7>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_2_renamed_274))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_4_renamed_276))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<7>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_3_renamed_275))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_4_renamed_276))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<7>4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_4_renamed_276))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_7_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<6>1")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_5))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_1_renamed_399))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<6>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_2_renamed_277))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_4_renamed_279))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<6>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_3_renamed_278))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_4_renamed_279))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<6>4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_4_renamed_279))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_6_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<5>1")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_5))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_1_renamed_400))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<5>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_2_renamed_280))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_4_renamed_282))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<5>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_3_renamed_281))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_4_renamed_282))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<5>4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_4_renamed_282))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_5_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<4>1")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_5))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_1_renamed_401))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<4>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_2_renamed_283))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_4_renamed_285))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<4>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_3_renamed_284))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_4_renamed_285))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<4>4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_4_renamed_285))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_4_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<15>1")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_5))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_1_renamed_392))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<15>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_2_renamed_286))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_4_renamed_288))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<15>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_3_renamed_287))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_4_renamed_288))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<15>4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_4_renamed_288))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_15_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<14>1")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_5))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_1_renamed_393))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<14>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_2_renamed_289))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_4_renamed_291))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<14>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_3_renamed_290))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_4_renamed_291))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<14>4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_4_renamed_291))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_14_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<13>1")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_5))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_1_renamed_394))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<13>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_2_renamed_292))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_4_renamed_294))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<13>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_3_renamed_293))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_4_renamed_294))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<13>4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_4_renamed_294))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_13_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<12>1")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_5))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_1_renamed_395))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<12>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_2_renamed_295))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_4_renamed_297))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<12>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_3_renamed_296))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_4_renamed_297))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<12>4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_4_renamed_297))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_12_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<11>1")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_5))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_1_renamed_396))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<11>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_2_renamed_298))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_4_renamed_300))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<11>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_3_renamed_299))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_4_renamed_300))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<11>4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_4_renamed_300))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_11_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<10>1")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_5_renamed_304))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_1_renamed_397))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<10>4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_2_renamed_301))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_4_renamed_303))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_5 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<10>5")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_3_renamed_302))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_4_renamed_303))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_6 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<10>6")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_4_renamed_303))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_10_5_renamed_304))
+              )
+            )
+            (net N26
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT1_SW0))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT1))
+              )
+            )
+            (net N28
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT2_SW0))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_123_OUT2))
+              )
+            )
+            (net (rename BIU_CORE__n10042 "BIU_CORE/_n10042")
+              (joined
+                (portRef O (instanceRef BIU_CORE__n10042_renamed_305))
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+                (portRef I4 (instanceRef BIU_CORE__n10044))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__den_int_Select_178_o112 "BIU_CORE/biu_state[7]_den_int_Select_178_o112")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o112_renamed_306))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o113))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<19>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_1_renamed_307))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_2_renamed_308))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<19>2")
+              (joined
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+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_19_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<18>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_1_renamed_309))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_2_renamed_310))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<18>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_2_renamed_310))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_18_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<17>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_1_renamed_311))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_2_renamed_312))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<17>2")
+              (joined
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+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_17_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<16>1")
+              (joined
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+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_2_renamed_314))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_165_OUT<16>2")
+              (joined
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+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_16_3))
+              )
+            )
+            (net N30
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_0__))
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+              )
+            )
+            (net N32
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_1__))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_1__SW0))
+              )
+            )
+            (net N34
+              (joined
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+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_2__SW0))
+              )
+            )
+            (net N36
+              (joined
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+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_3__SW0))
+              )
+            )
+            (net N38
+              (joined
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+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_4__SW0))
+              )
+            )
+            (net N40
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_5__))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_5__SW0))
+              )
+            )
+            (net N42
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_6__))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_6__SW0))
+              )
+            )
+            (net N44
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_7__))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_172_OUT_7__SW0))
+              )
+            )
+            (net N48
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o_SW0))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__den_int_Select_178_o_renamed_315))
+              )
+            )
+            (net (rename BIU_CORE_BIU_CLK_COUNTER_ZERO_12_ "BIU_CORE/BIU_CLK_COUNTER_ZERO<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_1_renamed_316))
+                (portRef I0 (instanceRef BIU_CORE__n0867_inv1))
+                (portRef I1 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_3))
+              )
+            )
+            (net (rename BIU_CORE_BIU_CLK_COUNTER_ZERO_12_1 "BIU_CORE/BIU_CLK_COUNTER_ZERO<12>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_2))
+                (portRef I4 (instanceRef BIU_CORE__n0867_inv1))
+                (portRef I2 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_3))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n04576 "EU_CORE/Mmux_n04576")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045761_renamed_317))
+                (portRef I5 (instanceRef EU_CORE_Mmux_n045762))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n045761 "EU_CORE/Mmux_n045761")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045762))
+                (portRef I2 (instanceRef EU_CORE_Mmux_n045765))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n045763 "EU_CORE/Mmux_n045763")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045764))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045765))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n04572 "EU_CORE/Mmux_n04572")
+              (joined
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+                (portRef I5 (instanceRef EU_CORE_Mmux_n045722))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n045721 "EU_CORE/Mmux_n045721")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045722))
+                (portRef I2 (instanceRef EU_CORE_Mmux_n045725))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n045723 "EU_CORE/Mmux_n045723")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045724))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045725))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n0457132 "EU_CORE/Mmux_n0457132")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n0457133_renamed_382))
+                (portRef I4 (instanceRef EU_CORE_Mmux_n0457136))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n0457133 "EU_CORE/Mmux_n0457133")
+              (joined
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+                (portRef I1 (instanceRef EU_CORE_Mmux_n0457136))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n045712 "EU_CORE/Mmux_n045712")
+              (joined
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+                (portRef I5 (instanceRef EU_CORE_Mmux_n0457122))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n0457121 "EU_CORE/Mmux_n0457121")
+              (joined
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+                (portRef I4 (instanceRef EU_CORE_Mmux_n0457124))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT11 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT11")
+              (joined
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+                (portRef I3 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_7__))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT111 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT111")
+              (joined
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+                (portRef I2 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_7__))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT10 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT10")
+              (joined
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+                (portRef I3 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_6__))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT101 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT101")
+              (joined
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+                (portRef I2 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_6__))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT9 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT9")
+              (joined
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+                (portRef I3 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_5__))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT91 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT91")
+              (joined
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+                (portRef I2 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_5__))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT8 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT8")
+              (joined
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+                (portRef I3 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_4__))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT81 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT81")
+              (joined
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+                (portRef I2 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_4__))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT7 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT7")
+              (joined
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+                (portRef I3 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_3__))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT71 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT71")
+              (joined
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+                (portRef I2 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_3__))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT3 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT3")
+              (joined
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+                (portRef I2 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_11__))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT31 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT31")
+              (joined
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+                (portRef I1 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_11__))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT2 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT2")
+              (joined
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+                (portRef I2 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_10__))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT21 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT21")
+              (joined
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+                (portRef I1 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_10__))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT13 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT13")
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+                (portRef I2 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_9__))
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+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT131 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT131")
+              (joined
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+                (portRef I1 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_9__))
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+            (net (rename EU_CORE_Mmux_n0457152 "EU_CORE/Mmux_n0457152")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n0457152_renamed_332))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n0457153))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n045711 "EU_CORE/Mmux_n045711")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n0457111_renamed_333))
+                (portRef I4 (instanceRef EU_CORE_Mmux_n0457113))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n0457112 "EU_CORE/Mmux_n0457112")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n0457112_renamed_334))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n0457113))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT6 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT6")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT61))
+                (portRef I5 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT62))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT5 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT5")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT51))
+                (portRef I5 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT52))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT12 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT12")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT121_renamed_335))
+                (portRef I2 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_8__))
+              )
+            )
+            (net (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT121 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT121")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT122))
+                (portRef I1 (instanceRef EU_CORE_Mcount_eu_rom_address_lut_8__))
+              )
+            )
+            (net N65
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT1_SW0))
+                (portRef I5 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT1))
+              )
+            )
+            (net N67
+              (joined
+                (portRef O (instanceRef EU_CORE__n1157_0_2_SW0))
+                (portRef I5 (instanceRef EU_CORE__n1157_0_2_renamed_336))
+                (portRef I5 (instanceRef EU_CORE_eu_stall_pipeline_eu_jump_boolean_AND_116_o_inv_renamed_337))
+              )
+            )
+            (net (rename EU_CORE_n0072_renamed_0_15_ "EU_CORE/n0072<15>")
+              (joined
+                (portRef O (instanceRef EU_CORE_n0072_15_1_renamed_338))
+                (portRef I5 (instanceRef EU_CORE_n0072_15_3))
+              )
+            )
+            (net (rename EU_CORE_n0072_15_1 "EU_CORE/n0072<15>1")
+              (joined
+                (portRef O (instanceRef EU_CORE_n0072_15_2))
+                (portRef I4 (instanceRef EU_CORE_n0072_15_3))
+              )
+            )
+            (net N71
+              (joined
+                (portRef O (instanceRef EU_CORE_eu_parity_SW0))
+                (portRef I5 (instanceRef EU_CORE_eu_parity_renamed_339))
+              )
+            )
+            (net CORE_CLK
+              (joined
+                (portRef CORE_CLK)
+                (portRef I (instanceRef CORE_CLK_BUFGP_renamed_404))
+              )
+            )
+            (net CLK
+              (joined
+                (portRef CLK)
+                (portRef I (instanceRef CLK_IBUF_renamed_340))
+              )
+            )
+            (net RESET
+              (joined
+                (portRef RESET)
+                (portRef I (instanceRef RESET_IBUF_renamed_341))
+              )
+            )
+            (net READY
+              (joined
+                (portRef READY)
+                (portRef I (instanceRef READY_IBUF_renamed_342))
+              )
+            )
+            (net INTR
+              (joined
+                (portRef INTR)
+                (portRef I (instanceRef INTR_IBUF_renamed_343))
+              )
+            )
+            (net NMI
+              (joined
+                (portRef NMI)
+                (portRef I (instanceRef NMI_IBUF_renamed_344))
+              )
+            )
+            (net (rename SRAM_D_7_ "SRAM_D<7>")
+              (joined
+                (portRef (member SRAM_D 0))
+                (portRef O (instanceRef SRAM_D_7_OBUF))
+              )
+            )
+            (net (rename SRAM_D_6_ "SRAM_D<6>")
+              (joined
+                (portRef (member SRAM_D 1))
+                (portRef O (instanceRef SRAM_D_6_OBUF))
+              )
+            )
+            (net (rename SRAM_D_5_ "SRAM_D<5>")
+              (joined
+                (portRef (member SRAM_D 2))
+                (portRef O (instanceRef SRAM_D_5_OBUF))
+              )
+            )
+            (net (rename SRAM_D_4_ "SRAM_D<4>")
+              (joined
+                (portRef (member SRAM_D 3))
+                (portRef O (instanceRef SRAM_D_4_OBUF))
+              )
+            )
+            (net (rename SRAM_D_3_ "SRAM_D<3>")
+              (joined
+                (portRef (member SRAM_D 4))
+                (portRef O (instanceRef SRAM_D_3_OBUF))
+              )
+            )
+            (net (rename SRAM_D_2_ "SRAM_D<2>")
+              (joined
+                (portRef (member SRAM_D 5))
+                (portRef O (instanceRef SRAM_D_2_OBUF))
+              )
+            )
+            (net (rename SRAM_D_1_ "SRAM_D<1>")
+              (joined
+                (portRef (member SRAM_D 6))
+                (portRef O (instanceRef SRAM_D_1_OBUF))
+              )
+            )
+            (net (rename SRAM_D_0_ "SRAM_D<0>")
+              (joined
+                (portRef (member SRAM_D 7))
+                (portRef O (instanceRef SRAM_D_0_OBUF))
+              )
+            )
+            (net N73
+              (joined
+                (portRef D (instanceRef BIU_CORE_ad_in_int_7))
+                (portRef O (instanceRef AD7_IOBUF))
+              )
+            )
+            (net N74
+              (joined
+                (portRef D (instanceRef BIU_CORE_ad_in_int_6))
+                (portRef O (instanceRef AD6_IOBUF))
+              )
+            )
+            (net N75
+              (joined
+                (portRef D (instanceRef BIU_CORE_ad_in_int_5))
+                (portRef O (instanceRef AD5_IOBUF))
+              )
+            )
+            (net N76
+              (joined
+                (portRef D (instanceRef BIU_CORE_ad_in_int_4))
+                (portRef O (instanceRef AD4_IOBUF))
+              )
+            )
+            (net N77
+              (joined
+                (portRef D (instanceRef BIU_CORE_ad_in_int_3))
+                (portRef O (instanceRef AD3_IOBUF))
+              )
+            )
+            (net N78
+              (joined
+                (portRef D (instanceRef BIU_CORE_ad_in_int_2))
+                (portRef O (instanceRef AD2_IOBUF))
+              )
+            )
+            (net N79
+              (joined
+                (portRef D (instanceRef BIU_CORE_ad_in_int_1))
+                (portRef O (instanceRef AD1_IOBUF))
+              )
+            )
+            (net N80
+              (joined
+                (portRef D (instanceRef BIU_CORE_ad_in_int_0))
+                (portRef O (instanceRef AD0_IOBUF))
+              )
+            )
+            (net (rename SRAM_A_18_ "SRAM_A<18>")
+              (joined
+                (portRef (member SRAM_A 0))
+                (portRef O (instanceRef SRAM_A_18_OBUF))
+              )
+            )
+            (net (rename SRAM_A_17_ "SRAM_A<17>")
+              (joined
+                (portRef (member SRAM_A 1))
+                (portRef O (instanceRef SRAM_A_17_OBUF))
+              )
+            )
+            (net (rename SRAM_A_16_ "SRAM_A<16>")
+              (joined
+                (portRef (member SRAM_A 2))
+                (portRef O (instanceRef SRAM_A_16_OBUF))
+              )
+            )
+            (net (rename SRAM_A_15_ "SRAM_A<15>")
+              (joined
+                (portRef (member SRAM_A 3))
+                (portRef O (instanceRef SRAM_A_15_OBUF))
+              )
+            )
+            (net (rename SRAM_A_14_ "SRAM_A<14>")
+              (joined
+                (portRef (member SRAM_A 4))
+                (portRef O (instanceRef SRAM_A_14_OBUF))
+              )
+            )
+            (net (rename SRAM_A_13_ "SRAM_A<13>")
+              (joined
+                (portRef (member SRAM_A 5))
+                (portRef O (instanceRef SRAM_A_13_OBUF))
+              )
+            )
+            (net (rename SRAM_A_12_ "SRAM_A<12>")
+              (joined
+                (portRef (member SRAM_A 6))
+                (portRef O (instanceRef SRAM_A_12_OBUF))
+              )
+            )
+            (net (rename SRAM_A_11_ "SRAM_A<11>")
+              (joined
+                (portRef (member SRAM_A 7))
+                (portRef O (instanceRef SRAM_A_11_OBUF))
+              )
+            )
+            (net (rename SRAM_A_10_ "SRAM_A<10>")
+              (joined
+                (portRef (member SRAM_A 8))
+                (portRef O (instanceRef SRAM_A_10_OBUF))
+              )
+            )
+            (net (rename SRAM_A_9_ "SRAM_A<9>")
+              (joined
+                (portRef (member SRAM_A 9))
+                (portRef O (instanceRef SRAM_A_9_OBUF))
+              )
+            )
+            (net (rename SRAM_A_8_ "SRAM_A<8>")
+              (joined
+                (portRef (member SRAM_A 10))
+                (portRef O (instanceRef SRAM_A_8_OBUF))
+              )
+            )
+            (net (rename SRAM_A_7_ "SRAM_A<7>")
+              (joined
+                (portRef (member SRAM_A 11))
+                (portRef O (instanceRef SRAM_A_7_OBUF))
+              )
+            )
+            (net (rename SRAM_A_6_ "SRAM_A<6>")
+              (joined
+                (portRef (member SRAM_A 12))
+                (portRef O (instanceRef SRAM_A_6_OBUF))
+              )
+            )
+            (net (rename SRAM_A_5_ "SRAM_A<5>")
+              (joined
+                (portRef (member SRAM_A 13))
+                (portRef O (instanceRef SRAM_A_5_OBUF))
+              )
+            )
+            (net (rename SRAM_A_4_ "SRAM_A<4>")
+              (joined
+                (portRef (member SRAM_A 14))
+                (portRef O (instanceRef SRAM_A_4_OBUF))
+              )
+            )
+            (net (rename SRAM_A_3_ "SRAM_A<3>")
+              (joined
+                (portRef (member SRAM_A 15))
+                (portRef O (instanceRef SRAM_A_3_OBUF))
+              )
+            )
+            (net (rename SRAM_A_2_ "SRAM_A<2>")
+              (joined
+                (portRef (member SRAM_A 16))
+                (portRef O (instanceRef SRAM_A_2_OBUF))
+              )
+            )
+            (net (rename SRAM_A_1_ "SRAM_A<1>")
+              (joined
+                (portRef (member SRAM_A 17))
+                (portRef O (instanceRef SRAM_A_1_OBUF))
+              )
+            )
+            (net (rename SRAM_A_0_ "SRAM_A<0>")
+              (joined
+                (portRef (member SRAM_A 18))
+                (portRef O (instanceRef SRAM_A_0_OBUF))
+              )
+            )
+            (net (rename LED_7_ "LED<7>")
+              (joined
+                (portRef (member LED 0))
+                (portRef O (instanceRef LED_7_OBUF))
+              )
+            )
+            (net (rename LED_6_ "LED<6>")
+              (joined
+                (portRef (member LED 1))
+                (portRef O (instanceRef LED_6_OBUF))
+              )
+            )
+            (net (rename LED_5_ "LED<5>")
+              (joined
+                (portRef (member LED 2))
+                (portRef O (instanceRef LED_5_OBUF))
+              )
+            )
+            (net (rename LED_4_ "LED<4>")
+              (joined
+                (portRef (member LED 3))
+                (portRef O (instanceRef LED_4_OBUF))
+              )
+            )
+            (net (rename LED_3_ "LED<3>")
+              (joined
+                (portRef (member LED 4))
+                (portRef O (instanceRef LED_3_OBUF))
+              )
+            )
+            (net (rename LED_2_ "LED<2>")
+              (joined
+                (portRef (member LED 5))
+                (portRef O (instanceRef LED_2_OBUF))
+              )
+            )
+            (net (rename LED_1_ "LED<1>")
+              (joined
+                (portRef (member LED 6))
+                (portRef O (instanceRef LED_1_OBUF))
+              )
+            )
+            (net (rename LED_0_ "LED<0>")
+              (joined
+                (portRef (member LED 7))
+                (portRef O (instanceRef LED_0_OBUF))
+              )
+            )
+            (net A19
+              (joined
+                (portRef A19)
+                (portRef O (instanceRef A19_OBUF))
+              )
+            )
+            (net A18
+              (joined
+                (portRef A18)
+                (portRef O (instanceRef A18_OBUF))
+              )
+            )
+            (net A17
+              (joined
+                (portRef A17)
+                (portRef O (instanceRef A17_OBUF))
+              )
+            )
+            (net A16
+              (joined
+                (portRef A16)
+                (portRef O (instanceRef A16_OBUF))
+              )
+            )
+            (net A15
+              (joined
+                (portRef A15)
+                (portRef O (instanceRef A15_OBUF))
+              )
+            )
+            (net A14
+              (joined
+                (portRef A14)
+                (portRef O (instanceRef A14_OBUF))
+              )
+            )
+            (net A13
+              (joined
+                (portRef A13)
+                (portRef O (instanceRef A13_OBUF))
+              )
+            )
+            (net A12
+              (joined
+                (portRef A12)
+                (portRef O (instanceRef A12_OBUF))
+              )
+            )
+            (net A11
+              (joined
+                (portRef A11)
+                (portRef O (instanceRef A11_OBUF))
+              )
+            )
+            (net A10
+              (joined
+                (portRef A10)
+                (portRef O (instanceRef A10_OBUF))
+              )
+            )
+            (net A9
+              (joined
+                (portRef A9)
+                (portRef O (instanceRef A9_OBUF))
+              )
+            )
+            (net A8
+              (joined
+                (portRef A8)
+                (portRef O (instanceRef A8_OBUF))
+              )
+            )
+            (net ALE
+              (joined
+                (portRef ALE)
+                (portRef O (instanceRef ALE_OBUF))
+              )
+            )
+            (net INTA_n
+              (joined
+                (portRef INTA_n)
+                (portRef O (instanceRef INTA_n_OBUF))
+              )
+            )
+            (net RD_n
+              (joined
+                (portRef RD_n)
+                (portRef O (instanceRef RD_n_OBUF))
+              )
+            )
+            (net WR_n
+              (joined
+                (portRef WR_n)
+                (portRef O (instanceRef WR_n_OBUF))
+              )
+            )
+            (net IOM
+              (joined
+                (portRef IOM)
+                (portRef O (instanceRef IOM_OBUF))
+              )
+            )
+            (net DTR
+              (joined
+                (portRef DTR)
+                (portRef O (instanceRef DTR_OBUF))
+              )
+            )
+            (net DEN
+              (joined
+                (portRef DEN)
+                (portRef O (instanceRef DEN_OBUF))
+              )
+            )
+            (net SSO_n
+              (joined
+                (portRef SSO_n)
+                (portRef O (instanceRef SSO_n_OBUF))
+              )
+            )
+            (net SRAM_CE_n
+              (joined
+                (portRef SRAM_CE_n)
+                (portRef O (instanceRef SRAM_CE_n_OBUF))
+              )
+            )
+            (net SRAM_OE_n
+              (joined
+                (portRef SRAM_OE_n)
+                (portRef O (instanceRef SRAM_OE_n_OBUF))
+              )
+            )
+            (net SRAM_WE_n
+              (joined
+                (portRef SRAM_WE_n)
+                (portRef O (instanceRef SRAM_WE_n_OBUF))
+              )
+            )
+            (net BUF1_OE_n
+              (joined
+                (portRef BUF1_OE_n)
+                (portRef O (instanceRef BUF1_OE_n_OBUF))
+              )
+            )
+            (net BUF2_OE_n
+              (joined
+                (portRef BUF2_OE_n)
+                (portRef O (instanceRef BUF2_OE_n_OBUF))
+              )
+            )
+            (net BUF2_DIR
+              (joined
+                (portRef BUF2_DIR)
+                (portRef O (instanceRef BUF2_DIR_OBUF))
+              )
+            )
+            (net (rename BIU_CORE_eu_biu_req_caught_glue_set "BIU_CORE/eu_biu_req_caught_glue_set")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_biu_req_caught_renamed_345))
+                (portRef O (instanceRef BIU_CORE_eu_biu_req_caught_glue_set_renamed_385))
+              )
+            )
+            (net (rename BIU_CORE_nmi_caught_glue_set "BIU_CORE/nmi_caught_glue_set")
+              (joined
+                (portRef D (instanceRef BIU_CORE_nmi_caught_renamed_346))
+                (portRef O (instanceRef BIU_CORE_nmi_caught_glue_set_renamed_386))
+              )
+            )
+            (net (rename EU_CORE_eu_tr_latched_glue_set "EU_CORE/eu_tr_latched_glue_set")
+              (joined
+                (portRef D (instanceRef EU_CORE_eu_tr_latched_renamed_347))
+                (portRef O (instanceRef EU_CORE_eu_tr_latched_glue_set_renamed_387))
+              )
+            )
+            (net (rename EU_CORE_biu_done_caught_glue_set "EU_CORE/biu_done_caught_glue_set")
+              (joined
+                (portRef D (instanceRef EU_CORE_biu_done_caught_renamed_348))
+                (portRef O (instanceRef EU_CORE_biu_done_caught_glue_set_renamed_403))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_14__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<14>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_14__rt_renamed_349))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_14__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_13__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<13>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_13__rt_renamed_350))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_13__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_12__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<12>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_12__rt_renamed_351))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_12__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_11__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<11>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_11__rt_renamed_352))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_11__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_10__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<10>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_10__rt_renamed_353))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_10__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_9__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<9>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_9__rt_renamed_354))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_9__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_8__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<8>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_8__rt_renamed_355))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_8__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_7__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<7>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_7__rt_renamed_356))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_7__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_6__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<6>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_6__rt_renamed_357))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_6__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_5__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<5>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_5__rt_renamed_358))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_5__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_4__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<4>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_4__rt_renamed_359))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_4__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_3__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<3>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_3__rt_renamed_360))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_3__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_3__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_2__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<2>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_2__rt_renamed_361))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_2__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_2__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_1__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_cy<1>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_1__rt_renamed_362))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_cy_1__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_1__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_18__rt "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<18>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_18__rt_renamed_363))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_18__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_18__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_17__rt "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<17>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_17__rt_renamed_364))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_17__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_17__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_16__rt "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_cy<16>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_16__rt_renamed_365))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_cy_16__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_16__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_18__rt "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<18>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_18__rt_renamed_366))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_18__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_18__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_17__rt "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<17>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_17__rt_renamed_367))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_17__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_17__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_16__rt "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_cy<16>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_16__rt_renamed_368))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_cy_16__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_16__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_18__rt "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<18>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_18__rt_renamed_369))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_18__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_18__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_17__rt "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<17>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_17__rt_renamed_370))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_17__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_17__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_16__rt "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_cy<16>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_16__rt_renamed_371))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_cy_16__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_16__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_15__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_10_o_add_140_OUT_xor<15>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_15__rt_renamed_372))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_10_o_add_140_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_19__rt "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_89_OUT_xor<19>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_19__rt_renamed_373))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_89_OUT_xor_19__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_19__rt "BIU_CORE/Madd_biu_register_ss[15]_GND_10_o_add_92_OUT_xor<19>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_19__rt_renamed_374))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_10_o_add_92_OUT_xor_19__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_19__rt "BIU_CORE/Madd_biu_register_cs[15]_GND_10_o_add_118_OUT_xor<19>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_19__rt_renamed_375))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_10_o_add_118_OUT_xor_19__))
+              )
+            )
+            (net (rename BIU_CORE_BIU_INTR_rstpot "BIU_CORE/BIU_INTR_rstpot")
+              (joined
+                (portRef D (instanceRef BIU_CORE_BIU_INTR_renamed_376))
+                (portRef O (instanceRef BIU_CORE_BIU_INTR_rstpot_renamed_398))
+              )
+            )
+            (net t_reset_d4_rstpot
+              (joined
+                (portRef D (instanceRef t_reset_d4_renamed_377))
+                (portRef O (instanceRef t_reset_d4_rstpot_renamed_402))
+              )
+            )
+            (net (rename BIU_CORE_word_cycle_rstpot1 "BIU_CORE/word_cycle_rstpot1")
+              (joined
+                (portRef D (instanceRef BIU_CORE_word_cycle_renamed_378))
+                (portRef O (instanceRef BIU_CORE_word_cycle_rstpot1_renamed_383))
+              )
+            )
+            (net (rename EU_CORE_intr_enable_delayed_rstpot1 "EU_CORE/intr_enable_delayed_rstpot1")
+              (joined
+                (portRef D (instanceRef EU_CORE_intr_enable_delayed_renamed_379))
+                (portRef O (instanceRef EU_CORE_intr_enable_delayed_rstpot1_renamed_384))
+              )
+            )
+            (net N100
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045771_SW1))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045772))
+              )
+            )
+            (net N103
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_13_1_SW0))
+                (portRef I3 (instanceRef EU_CORE_carry_15_1_SW4_F))
+                (portRef I0 (instanceRef EU_CORE_carry_16_1))
+                (portRef I0 (instanceRef EU_CORE_Mxor_carry_16__carry_15__XOR_141_o_xo_0_1))
+              )
+            )
+            (net N104
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_13_1_SW1))
+                (portRef I1 (instanceRef EU_CORE_carry_16_1))
+                (portRef I1 (instanceRef EU_CORE_Mxor_carry_16__carry_15__XOR_141_o_xo_0_1))
+                (portRef I4 (instanceRef EU_CORE_carry_15_1_SW5_F))
+              )
+            )
+            (net N106
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045733_SW0))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045734))
+              )
+            )
+            (net N108
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045763_SW0))
+                (portRef I4 (instanceRef EU_CORE_carry_13_1_SW4))
+                (portRef I4 (instanceRef EU_CORE_carry_13_1_SW5))
+              )
+            )
+            (net N109
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045763_SW1))
+                (portRef I5 (instanceRef EU_CORE_carry_13_1_SW4))
+                (portRef I5 (instanceRef EU_CORE_carry_13_1_SW5))
+              )
+            )
+            (net N111
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_11_1_SW0))
+                (portRef I3 (instanceRef EU_CORE_carry_13_1_SW4))
+                (portRef I2 (instanceRef EU_CORE_carry_13_1_SW5))
+                (portRef I5 (instanceRef EU_CORE_carry_13_1_SW2))
+              )
+            )
+            (net N112
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_11_1_SW1))
+                (portRef I2 (instanceRef EU_CORE_carry_13_1_SW4))
+                (portRef I3 (instanceRef EU_CORE_carry_13_1_SW5))
+                (portRef I5 (instanceRef EU_CORE_carry_13_1_SW3))
+              )
+            )
+            (net N114
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_7_1_SW0))
+                (portRef I4 (instanceRef EU_CORE_carry_9_1_SW0))
+                (portRef I1 (instanceRef EU_CORE_carry_9_1))
+              )
+            )
+            (net N115
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_7_1_SW1))
+                (portRef I4 (instanceRef EU_CORE_carry_9_1_SW1))
+                (portRef I2 (instanceRef EU_CORE_carry_9_1))
+              )
+            )
+            (net N117
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n0457411_SW0))
+                (portRef I4 (instanceRef EU_CORE_Mmux_n045743))
+              )
+            )
+            (net N118
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n0457411_SW1))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045743))
+              )
+            )
+            (net N120
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_9_1_SW0))
+                (portRef I2 (instanceRef EU_CORE_carry_11_1))
+              )
+            )
+            (net N121
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_9_1_SW1))
+                (portRef I4 (instanceRef EU_CORE_carry_11_1))
+              )
+            )
+            (net N123
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_15_1_SW0))
+                (portRef I2 (instanceRef EU_CORE_carry_16_1))
+              )
+            )
+            (net N124
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_15_1_SW1))
+                (portRef I3 (instanceRef EU_CORE_carry_16_1))
+              )
+            )
+            (net N126
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_15_1_SW2))
+                (portRef I2 (instanceRef EU_CORE_Mxor_carry_16__carry_15__XOR_141_o_xo_0_1))
+              )
+            )
+            (net N127
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_15_1_SW3))
+                (portRef I3 (instanceRef EU_CORE_Mxor_carry_16__carry_15__XOR_141_o_xo_0_1))
+              )
+            )
+            (net N129
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_15_1_SW4))
+                (portRef I2 (instanceRef EU_CORE_Mmux_n045772))
+              )
+            )
+            (net N130
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_15_1_SW5))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045772))
+              )
+            )
+            (net N132
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5__))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_5__SW0_SW0))
+              )
+            )
+            (net N134
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n0457123_SW0))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n0457124))
+              )
+            )
+            (net N136
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045723_SW0))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045725))
+              )
+            )
+            (net N137
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045723_SW1))
+                (portRef I4 (instanceRef EU_CORE_Mmux_n045725))
+              )
+            )
+            (net N139
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n04571511_SW0))
+                (portRef I4 (instanceRef EU_CORE_Mmux_n0457153))
+              )
+            )
+            (net N140
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n04571511_SW1))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n0457153))
+              )
+            )
+            (net N142
+              (joined
+                (portRef I4 (instanceRef EU_CORE_Mmux_n045754))
+                (portRef O (instanceRef EU_CORE_carry_13_1_SW2))
+              )
+            )
+            (net N143
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_13_1_SW3))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045754))
+              )
+            )
+            (net N145
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_13_1_SW4))
+                (portRef I5 (instanceRef EU_CORE_Mmux_n045765))
+              )
+            )
+            (net N146
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_13_1_SW5))
+                (portRef I4 (instanceRef EU_CORE_Mmux_n045765))
+              )
+            )
+            (net N148
+              (joined
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+              )
+            )
+            (net N149
+              (joined
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+                (portRef O (instanceRef EU_CORE_carry_5_1_SW1))
+              )
+            )
+            (net N150
+              (joined
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+                (portRef O (instanceRef EU_CORE_carry_5_1_SW2))
+              )
+            )
+            (net N151
+              (joined
+                (portRef I3 (instanceRef EU_CORE_carry_7_1))
+                (portRef O (instanceRef EU_CORE_carry_5_1_SW3))
+              )
+            )
+            (net N153
+              (joined
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+                (portRef I3 (instanceRef EU_CORE_carry_9_1))
+              )
+            )
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+              (joined
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+                (portRef I4 (instanceRef EU_CORE_carry_9_1))
+              )
+            )
+            (net N156
+              (joined
+                (portRef O (instanceRef BIU_CORE__n09783_SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_165_OUT_0_21))
+              )
+            )
+            (net N158
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4_1_SW1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_6_2))
+              )
+            )
+            (net N160
+              (joined
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+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_4__))
+              )
+            )
+            (net N162
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n0457135_SW0))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n0457136))
+              )
+            )
+            (net N163
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n0457135_SW1))
+                (portRef I2 (instanceRef EU_CORE_Mmux_n0457136))
+              )
+            )
+            (net N165
+              (joined
+                (portRef I5 (instanceRef BIU_CORE_out21))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o112_SW0))
+              )
+            )
+            (net N167
+              (joined
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+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_10_o_Select_163_o1111_renamed_381))
+              )
+            )
+            (net N169
+              (joined
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+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_7_1))
+              )
+            )
+            (net N171
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_3_1))
+              )
+            )
+            (net N173
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW2))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_2_1))
+              )
+            )
+            (net N175
+              (joined
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_1))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_10_o_select_167_OUT_1_21_SW3))
+              )
+            )
+            (net N177
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045751_SW0))
+                (portRef I5 (instanceRef EU_CORE_Mmux_n045752))
+              )
+            )
+            (net N179
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n0457133_SW0))
+                (portRef I5 (instanceRef EU_CORE_Mmux_n0457133_renamed_382))
+              )
+            )
+            (net N183
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_5_1_SW1_F))
+                (portRef I0 (instanceRef EU_CORE_carry_5_1_SW1))
+              )
+            )
+            (net N184
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_5_1_SW1_G))
+                (portRef I1 (instanceRef EU_CORE_carry_5_1_SW1))
+              )
+            )
+            (net N185
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_5_1_SW2_F))
+                (portRef I0 (instanceRef EU_CORE_carry_5_1_SW2))
+              )
+            )
+            (net N186
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_5_1_SW2_G))
+                (portRef I1 (instanceRef EU_CORE_carry_5_1_SW2))
+              )
+            )
+            (net N187
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_5_1_SW3_F))
+                (portRef I0 (instanceRef EU_CORE_carry_5_1_SW3))
+              )
+            )
+            (net N188
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_5_1_SW3_G))
+                (portRef I1 (instanceRef EU_CORE_carry_5_1_SW3))
+              )
+            )
+            (net N189
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n04571_SW4))
+                (portRef I5 (instanceRef EU_CORE_Mmux_n04571))
+              )
+            )
+            (net N191
+              (joined
+                (portRef O (instanceRef BIU_CORE__n10044_SW0))
+                (portRef I5 (instanceRef BIU_CORE__n10044))
+              )
+            )
+            (net N193
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045783_F))
+                (portRef I0 (instanceRef EU_CORE_Mmux_n045783))
+              )
+            )
+            (net N194
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045783_G))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045783))
+              )
+            )
+            (net N195
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT43_F))
+                (portRef I0 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT43))
+              )
+            )
+            (net N196
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT43_G))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_rom_address_12__wide_mux_146_OUT43))
+              )
+            )
+            (net N197
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045793_F))
+                (portRef I0 (instanceRef EU_CORE_Mmux_n045793))
+              )
+            )
+            (net N198
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045793_G))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045793))
+              )
+            )
+            (net N199
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_15_1_SW4_F))
+                (portRef I0 (instanceRef EU_CORE_carry_15_1_SW4))
+              )
+            )
+            (net N200
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_15_1_SW4_G))
+                (portRef I1 (instanceRef EU_CORE_carry_15_1_SW4))
+              )
+            )
+            (net N201
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_5_1_SW0_F))
+                (portRef I0 (instanceRef EU_CORE_carry_5_1_SW0))
+              )
+            )
+            (net N202
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_5_1_SW0_G))
+                (portRef I1 (instanceRef EU_CORE_carry_5_1_SW0))
+              )
+            )
+            (net N203
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_15_1_SW5_F))
+                (portRef I0 (instanceRef EU_CORE_carry_15_1_SW5))
+              )
+            )
+            (net N204
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_15_1_SW5_G))
+                (portRef I1 (instanceRef EU_CORE_carry_15_1_SW5))
+              )
+            )
+            (net Mshreg_t_biu_ad_oe_d2
+              (joined
+                (portRef Q (instanceRef Mshreg_t_biu_ad_oe_d2_renamed_405))
+                (portRef D (instanceRef t_biu_ad_oe_d2_renamed_406))
+              )
+            )
+            (net Mshreg_t_reset_d2
+              (joined
+                (portRef Q (instanceRef Mshreg_t_reset_d2_renamed_407))
+                (portRef D (instanceRef t_reset_d2_renamed_408))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_15 "BIU_CORE/Mshreg_biu_return_data_int_d2_15")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_15_renamed_409))
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_14 "BIU_CORE/Mshreg_biu_return_data_int_d2_14")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_14_renamed_410))
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_13 "BIU_CORE/Mshreg_biu_return_data_int_d2_13")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_13_renamed_411))
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_12 "BIU_CORE/Mshreg_biu_return_data_int_d2_12")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_12_renamed_412))
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_11 "BIU_CORE/Mshreg_biu_return_data_int_d2_11")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_11_renamed_413))
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_10 "BIU_CORE/Mshreg_biu_return_data_int_d2_10")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_10_renamed_414))
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_9 "BIU_CORE/Mshreg_biu_return_data_int_d2_9")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_9_renamed_415))
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_8 "BIU_CORE/Mshreg_biu_return_data_int_d2_8")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_8_renamed_416))
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_7 "BIU_CORE/Mshreg_biu_return_data_int_d2_7")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_7_renamed_417))
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_6 "BIU_CORE/Mshreg_biu_return_data_int_d2_6")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_6_renamed_418))
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_3 "BIU_CORE/Mshreg_biu_return_data_int_d2_3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_3_renamed_419))
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_5 "BIU_CORE/Mshreg_biu_return_data_int_d2_5")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_5_renamed_420))
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_4 "BIU_CORE/Mshreg_biu_return_data_int_d2_4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_4_renamed_421))
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_2 "BIU_CORE/Mshreg_biu_return_data_int_d2_2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_2_renamed_422))
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_1 "BIU_CORE/Mshreg_biu_return_data_int_d2_1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_1_renamed_423))
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_0 "BIU_CORE/Mshreg_biu_return_data_int_d2_0")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_0_renamed_424))
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_15 "BIU_CORE/Mshreg_biu_register_rm_d2_15")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_15_renamed_425))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_12 "BIU_CORE/Mshreg_biu_register_rm_d2_12")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_12_renamed_426))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_14 "BIU_CORE/Mshreg_biu_register_rm_d2_14")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_14_renamed_427))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_13 "BIU_CORE/Mshreg_biu_register_rm_d2_13")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_13_renamed_428))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_11 "BIU_CORE/Mshreg_biu_register_rm_d2_11")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_11_renamed_429))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_10 "BIU_CORE/Mshreg_biu_register_rm_d2_10")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_10_renamed_430))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_9 "BIU_CORE/Mshreg_biu_register_rm_d2_9")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_9_renamed_431))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_8 "BIU_CORE/Mshreg_biu_register_rm_d2_8")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_8_renamed_432))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_5 "BIU_CORE/Mshreg_biu_register_rm_d2_5")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_5_renamed_433))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_7 "BIU_CORE/Mshreg_biu_register_rm_d2_7")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_7_renamed_434))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_6 "BIU_CORE/Mshreg_biu_register_rm_d2_6")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_6_renamed_435))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_4 "BIU_CORE/Mshreg_biu_register_rm_d2_4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_4_renamed_436))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_3 "BIU_CORE/Mshreg_biu_register_rm_d2_3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_3_renamed_437))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_2 "BIU_CORE/Mshreg_biu_register_rm_d2_2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_2_renamed_438))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_1 "BIU_CORE/Mshreg_biu_register_rm_d2_1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_1_renamed_439))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_14 "BIU_CORE/Mshreg_biu_register_ds_d2_14")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_14_renamed_440))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_0 "BIU_CORE/Mshreg_biu_register_rm_d2_0")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_0_renamed_441))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_15 "BIU_CORE/Mshreg_biu_register_ds_d2_15")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_15_renamed_442))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_13 "BIU_CORE/Mshreg_biu_register_ds_d2_13")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_13_renamed_443))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_12 "BIU_CORE/Mshreg_biu_register_ds_d2_12")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_12_renamed_444))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_11 "BIU_CORE/Mshreg_biu_register_ds_d2_11")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_11_renamed_445))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_10 "BIU_CORE/Mshreg_biu_register_ds_d2_10")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_10_renamed_446))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_7 "BIU_CORE/Mshreg_biu_register_ds_d2_7")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_7_renamed_447))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_9 "BIU_CORE/Mshreg_biu_register_ds_d2_9")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_9_renamed_448))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_8 "BIU_CORE/Mshreg_biu_register_ds_d2_8")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_8_renamed_449))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_6 "BIU_CORE/Mshreg_biu_register_ds_d2_6")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_6_renamed_450))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_5 "BIU_CORE/Mshreg_biu_register_ds_d2_5")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_5_renamed_451))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_4 "BIU_CORE/Mshreg_biu_register_ds_d2_4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_4_renamed_452))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_3 "BIU_CORE/Mshreg_biu_register_ds_d2_3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_3_renamed_453))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_0 "BIU_CORE/Mshreg_biu_register_ds_d2_0")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_0_renamed_454))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_2 "BIU_CORE/Mshreg_biu_register_ds_d2_2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_2_renamed_455))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_1 "BIU_CORE/Mshreg_biu_register_ds_d2_1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_1_renamed_456))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_15 "BIU_CORE/Mshreg_biu_register_reg_d2_15")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_15_renamed_457))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_14 "BIU_CORE/Mshreg_biu_register_reg_d2_14")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_14_renamed_458))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_13 "BIU_CORE/Mshreg_biu_register_reg_d2_13")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_13_renamed_459))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_12 "BIU_CORE/Mshreg_biu_register_reg_d2_12")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_12_renamed_460))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_9 "BIU_CORE/Mshreg_biu_register_reg_d2_9")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_9_renamed_461))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_11 "BIU_CORE/Mshreg_biu_register_reg_d2_11")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_11_renamed_462))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_10 "BIU_CORE/Mshreg_biu_register_reg_d2_10")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_10_renamed_463))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_8 "BIU_CORE/Mshreg_biu_register_reg_d2_8")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_8_renamed_464))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_7 "BIU_CORE/Mshreg_biu_register_reg_d2_7")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_7_renamed_465))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_6 "BIU_CORE/Mshreg_biu_register_reg_d2_6")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_6_renamed_466))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_5 "BIU_CORE/Mshreg_biu_register_reg_d2_5")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_5_renamed_467))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_4 "BIU_CORE/Mshreg_biu_register_reg_d2_4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_4_renamed_468))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_3 "BIU_CORE/Mshreg_biu_register_reg_d2_3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_3_renamed_469))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_2 "BIU_CORE/Mshreg_biu_register_reg_d2_2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_2_renamed_470))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_1 "BIU_CORE/Mshreg_biu_register_reg_d2_1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_1_renamed_471))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_0 "BIU_CORE/Mshreg_biu_register_reg_d2_0")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_0_renamed_472))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_15 "BIU_CORE/Mshreg_biu_register_ss_d2_15")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_15_renamed_473))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_14 "BIU_CORE/Mshreg_biu_register_ss_d2_14")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_14_renamed_474))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_13 "BIU_CORE/Mshreg_biu_register_ss_d2_13")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_13_renamed_475))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_10 "BIU_CORE/Mshreg_biu_register_ss_d2_10")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_10_renamed_476))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_12 "BIU_CORE/Mshreg_biu_register_ss_d2_12")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_12_renamed_477))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_11 "BIU_CORE/Mshreg_biu_register_ss_d2_11")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_11_renamed_478))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_9 "BIU_CORE/Mshreg_biu_register_ss_d2_9")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_9_renamed_479))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_8 "BIU_CORE/Mshreg_biu_register_ss_d2_8")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_8_renamed_480))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_7 "BIU_CORE/Mshreg_biu_register_ss_d2_7")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_7_renamed_481))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_6 "BIU_CORE/Mshreg_biu_register_ss_d2_6")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_6_renamed_482))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_3 "BIU_CORE/Mshreg_biu_register_ss_d2_3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_3_renamed_483))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_5 "BIU_CORE/Mshreg_biu_register_ss_d2_5")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_5_renamed_484))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_4 "BIU_CORE/Mshreg_biu_register_ss_d2_4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_4_renamed_485))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_2 "BIU_CORE/Mshreg_biu_register_ss_d2_2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_2_renamed_486))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_1 "BIU_CORE/Mshreg_biu_register_ss_d2_1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_1_renamed_487))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_0 "BIU_CORE/Mshreg_biu_register_ss_d2_0")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_0_renamed_488))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_15 "BIU_CORE/Mshreg_biu_register_es_d2_15")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_15_renamed_489))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_12 "BIU_CORE/Mshreg_biu_register_es_d2_12")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_12_renamed_490))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_14 "BIU_CORE/Mshreg_biu_register_es_d2_14")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_14_renamed_491))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_13 "BIU_CORE/Mshreg_biu_register_es_d2_13")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_13_renamed_492))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_11 "BIU_CORE/Mshreg_biu_register_es_d2_11")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_11_renamed_493))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_10 "BIU_CORE/Mshreg_biu_register_es_d2_10")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_10_renamed_494))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_9 "BIU_CORE/Mshreg_biu_register_es_d2_9")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_9_renamed_495))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_8 "BIU_CORE/Mshreg_biu_register_es_d2_8")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_8_renamed_496))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_5 "BIU_CORE/Mshreg_biu_register_es_d2_5")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_5_renamed_497))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_7 "BIU_CORE/Mshreg_biu_register_es_d2_7")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_7_renamed_498))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_6 "BIU_CORE/Mshreg_biu_register_es_d2_6")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_6_renamed_499))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_4 "BIU_CORE/Mshreg_biu_register_es_d2_4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_4_renamed_500))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_3 "BIU_CORE/Mshreg_biu_register_es_d2_3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_3_renamed_501))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_2 "BIU_CORE/Mshreg_biu_register_es_d2_2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_2_renamed_502))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_1 "BIU_CORE/Mshreg_biu_register_es_d2_1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_1_renamed_503))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_14 "BIU_CORE/Mshreg_biu_register_cs_d2_14")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_14_renamed_504))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_0 "BIU_CORE/Mshreg_biu_register_es_d2_0")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_0_renamed_505))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_15 "BIU_CORE/Mshreg_biu_register_cs_d2_15")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_15_renamed_506))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_13 "BIU_CORE/Mshreg_biu_register_cs_d2_13")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_13_renamed_507))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_12 "BIU_CORE/Mshreg_biu_register_cs_d2_12")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_12_renamed_508))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_11 "BIU_CORE/Mshreg_biu_register_cs_d2_11")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_11_renamed_509))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_10 "BIU_CORE/Mshreg_biu_register_cs_d2_10")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_10_renamed_510))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_7 "BIU_CORE/Mshreg_biu_register_cs_d2_7")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_7_renamed_511))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_9 "BIU_CORE/Mshreg_biu_register_cs_d2_9")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_9_renamed_512))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_8 "BIU_CORE/Mshreg_biu_register_cs_d2_8")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_8_renamed_513))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_6 "BIU_CORE/Mshreg_biu_register_cs_d2_6")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_6_renamed_514))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_5 "BIU_CORE/Mshreg_biu_register_cs_d2_5")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_5_renamed_515))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_4 "BIU_CORE/Mshreg_biu_register_cs_d2_4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_4_renamed_516))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_3 "BIU_CORE/Mshreg_biu_register_cs_d2_3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_3_renamed_517))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_0 "BIU_CORE/Mshreg_biu_register_cs_d2_0")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_0_renamed_518))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_2 "BIU_CORE/Mshreg_biu_register_cs_d2_2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_2_renamed_519))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_1 "BIU_CORE/Mshreg_biu_register_cs_d2_1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_1_renamed_520))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_1))
+              )
+            )
+          )
+      )
+    )
+  )
+
+  (design MCL86jr
+    (cellRef MCL86jr
+      (libraryRef MCL86jr_lib)
+    )
+    (property PART (string "xc6slx9-3-tqg144") (owner "Xilinx"))
+  )
+)
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/constrs_1/fileset.xml b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/constrs_1/fileset.xml
new file mode 100644
index 0000000..0f19ad9
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/constrs_1/fileset.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PPRDIR/../ipcore_dir/EU4Kx32.ncf">
+      <FileInfo>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../MCL86jr.ucf">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TargetConstrsFile" Val="$PPRDIR/../MCL86jr.ucf"/>
+      <Option Name="ConstrsType" Val="UCF"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/runs/impl_1.psg b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/runs/impl_1.psg
new file mode 100644
index 0000000..147f3a9
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/runs/impl_1.psg
@@ -0,0 +1,20 @@
+<?xml version="1.0"?>
+<Strategy Version="1" Minor="2">
+	<StratHandle Name="ISE Defaults" Flow="ISE14">
+		<Desc>ISE Defaults, including packing registers in IOs off</Desc>
+	</StratHandle>
+	<Step Id="ngdbuild">
+	</Step>
+	<Step Id="map">
+		<Option Id="FFPackEnum">3</Option>
+	</Step>
+	<Step Id="par">
+	</Step>
+	<Step Id="trce">
+	</Step>
+	<Step Id="xdl">
+	</Step>
+	<Step Id="bitgen">
+	</Step>
+</Strategy>
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/runs/runs.xml b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/runs/runs.xml
new file mode 100644
index 0000000..389cab4
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/runs/runs.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="8">
+	<Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc6slx9tqg144-3" ConstrsSet="constrs_1" Description="ISE Defaults, including packing registers in IOs off" State="current"/>
+</Runs>
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/sim_1/fileset.xml b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/sim_1/fileset.xml
new file mode 100644
index 0000000..65babe3
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/sim_1/fileset.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+      <Option Name="SrcSet" Val="sources_1"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/sources_1/fileset.xml b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/sources_1/fileset.xml
new file mode 100644
index 0000000..32c0375
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/sources_1/fileset.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+    <Filter Type="EDIFSrcs"/>
+    <File Path="$PPRDIR/../MCL86jr.ngc">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../ipcore_dir/EU4Kx32.ngc">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="GateLvl"/>
+      <Option Name="GateLvlMode" Val="EDIF"/>
+      <Option Name="TopFile" Val="$PPRDIR/../MCL86jr.ngc"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/wt/java_command_handlers.wdf b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/wt/java_command_handlers.wdf
new file mode 100644
index 0000000..45545f8
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/wt/java_command_handlers.wdf
@@ -0,0 +1,3 @@
+version:1
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697470726f70657274696573:32:00:00
+eof:1589079264
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/wt/project.wpc b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/wt/project.wpc
new file mode 100644
index 0000000..5fed558
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/wt/project.wpc
@@ -0,0 +1,4 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+6d6f64655f636f756e7465727c4953454d6f6465:1
+eof:
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/wt/webtalk_pa.xml b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/wt/webtalk_pa.xml
new file mode 100644
index 0000000..39bcf2a
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.data/wt/webtalk_pa.xml
@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Sat Sep 26 22:59:51 2020">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="8373322441fb45818fa220c689841eb6" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="GateLvl" type="DesignMode"/>
+<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="EditProperties" value="2" type="JavaHandler"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="0" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="0" type="TclMode"/>
+<property name="ISEMode" value="16" type="ISEMode"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.ppr b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.ppr
new file mode 100644
index 0000000..86fe36c
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/MCL86jr.ppr
@@ -0,0 +1,28 @@
+<?xml version="1.0"?>
+<!--Product Version: PlanAhead v14.7 (64-bit)-->
+<Project Version="4" Minor="36">
+	<FileSet Dir="sources_1" File="fileset.xml"/>
+	<FileSet Dir="constrs_1" File="fileset.xml"/>
+	<FileSet Dir="sim_1" File="fileset.xml"/>
+	<RunSet Dir="runs" File="runs.xml"/>
+	<DefaultLaunch Dir="$PRUNDIR"/>
+	<DefaultPromote Dir="$PROMOTEDIR"/>
+	<Config>
+		<Option Name="Id" Val="713cafbeeb464fe287defb04efa9970e"/>
+		<Option Name="Part" Val="xc6slx9tqg144-3"/>
+		<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+		<Option Name="TargetLanguage" Val="Verilog"/>
+		<Option Name="TargetSimulator" Val="ISim"/>
+		<Option Name="Board" Val=""/>
+		<Option Name="SourceMgmtMode" Val="All"/>
+		<Option Name="ActiveSimSet" Val="sim_1"/>
+		<Option Name="CxlOverwriteLibs" Val="1"/>
+		<Option Name="CxlFuncsim" Val="1"/>
+		<Option Name="CxlTimesim" Val="1"/>
+		<Option Name="CxlCore" Val="1"/>
+		<Option Name="CxlEdk" Val="0"/>
+		<Option Name="CxlExcludeCores" Val="1"/>
+		<Option Name="CxlExcludeSubLibs" Val="0"/>
+	</Config>
+</Project>
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_2/planAhead.jou b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/planAhead.jou
new file mode 100644
index 0000000..63f928d
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/planAhead.jou
@@ -0,0 +1,10 @@
+#-----------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013
+# Start of session at: Sat Sep 26 22:57:51 2020
+# Process ID: 6304
+# Log file: C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_2/planAhead.log
+# Journal file: C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_2/planAhead.jou
+#-----------------------------------------------------------
+start_gui
+source C:/MCL/MCL86/MCL86jr/MCL86jr/pa.fromNetlist.tcl
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_2/planAhead.log b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/planAhead.log
new file mode 100644
index 0000000..3dd2237
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/planAhead.log
@@ -0,0 +1,95 @@
+#-----------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013
+# Start of session at: Sat Sep 26 22:57:51 2020
+# Process ID: 6304
+# Log file: C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_2/planAhead.log
+# Journal file: C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_2/planAhead.jou
+#-----------------------------------------------------------
+INFO: [Common 17-78] Attempting to get a license: PlanAhead
+INFO: [Common 17-290] Got license for PlanAhead
+INFO: [Common 17-86] Your PlanAhead license expires in -1275 day(s)
+INFO: [Device 21-36] Loading parts and site information from C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
+Parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+Finished parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+start_gui
+source C:/MCL/MCL86/MCL86jr/MCL86jr/pa.fromNetlist.tcl
+# create_project -name MCL86jr -dir "C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_2" -part xc6slx9tqg144-3
+# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+# set_property edif_top_file "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {C:/MCL/MCL86/MCL86jr/MCL86jr} {ipcore_dir} }
+# add_files [list {ipcore_dir/EU4Kx32.ncf}] -fileset [get_property constrset [current_run]]
+# set_param project.pinAheadLayout  yes
+# set_property target_constrs_file "MCL86jr.ucf" [current_fileset -constrset]
+Adding file 'C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ucf' to fileset 'constrs_1'
+# add_files [list {MCL86jr.ucf}] -fileset [get_property constrset [current_run]]
+# link_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to project part: xc6slx9tqg144-3
+Release 14.7 - ngc2edif P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design MCL86jr.ngc ...
+WARNING:NetListWriters:298 - No output is written to MCL86jr.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+WARNING:NetListWriters:306 - Signal bus EU_CORE/carry<16 : 3> on block MCL86jr
+   is not reconstructed, because there are some missing bus signals.
+WARNING:NetListWriters:306 - Signal bus
+   EU_CORE/eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT<12 : 0> on
+   block MCL86jr is not reconstructed, because there are some missing bus
+   signals.
+WARNING:NetListWriters:306 - Signal bus EU_CORE/eu_operand0<15 : 5> on block
+   MCL86jr is not reconstructed, because there are some missing bus signals.
+  finished :Prep
+Writing EDIF netlist file MCL86jr.edif ...
+ngc2edif: Total memory usage is 82712 kilobytes
+
+Parsing EDIF File [./planAhead_run_2/MCL86jr.data/cache/MCL86jr_ngc_zx.edif]
+Finished Parsing EDIF File [./planAhead_run_2/MCL86jr.data/cache/MCL86jr_ngc_zx.edif]
+Release 14.7 - ngc2edif P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design EU4Kx32.ngc ...
+WARNING:NetListWriters:298 - No output is written to EU4Kx32.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file EU4Kx32.edif ...
+ngc2edif: Total memory usage is 78744 kilobytes
+
+Reading core file 'C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/EU4Kx32.ngc' for (cell view 'EU4Kx32', library 'MCL86jr_lib', file 'MCL86jr.ngc')
+Parsing EDIF File [./planAhead_run_2/MCL86jr.data/cache/EU4Kx32_ngc_zx.edif]
+Finished Parsing EDIF File [./planAhead_run_2/MCL86jr.data/cache/EU4Kx32_ngc_zx.edif]
+INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+WARNING: [Netlist 29-43] Netlist 'MCL86jr' is not ideal for floorplanning, since the cellview 'MCL86jr' defined in file 'MCL86jr.ngc' contains large number of primitives.  Please consider enabling hierarchy in synthesis if you want to do floorplanning.
+Loading clock regions from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/tqg144/Package.xml
+Loading io standards from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan6/IOStandards.xml
+Loading device configuration modes from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/ConfigModes.xml
+Loading list of drcs for the architecture : C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/EU4Kx32.ncf]
+Finished Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/EU4Kx32.ncf]
+Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ucf]
+Finished Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ucf]
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 9 instances were transformed.
+  BUFGP => BUFGP (IBUF, BUFG): 1 instances
+  IOBUF => IOBUF (OBUFT, IBUF): 8 instances
+
+Phase 0 | Netlist Checksum: 1658b132
+link_design: Time (s): elapsed = 00:00:15 . Memory (MB): peak = 607.238 ; gain = 172.105
+exit
+ERROR: [PlanAhead 12-106] *** Exception: ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
+HTclEvent: SIGNAL_BUS_MODIFY   Classes: ui.views.aR 
+HTclEvent: SIGNAL_MODIFY   Classes: ui.views.aR 
+HTclEvent: DEBUG_CORE_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: DEBUG_PORT_CONFIG_CHANGE   Classes: ui.views.aR 
+ (See C:/MCL/MCL86/MCL86jr/MCL86jr\planAhead_pid6304.debug)
+ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
+INFO: [Common 17-206] Exiting PlanAhead at Sat Sep 26 22:59:55 2020...
+INFO: [Common 17-83] Releasing license: PlanAhead
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_2/planAhead_run.log b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/planAhead_run.log
new file mode 100644
index 0000000..8d1609a
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_2/planAhead_run.log
@@ -0,0 +1,86 @@
+
+****** PlanAhead v14.7 (64-bit)
+  **** Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013
+    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
+
+INFO: [Common 17-78] Attempting to get a license: PlanAhead
+INFO: [Common 17-290] Got license for PlanAhead
+INFO: [Common 17-86] Your PlanAhead license expires in -1275 day(s)
+INFO: [Device 21-36] Loading parts and site information from C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
+Parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+Finished parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+start_gui
+source C:/MCL/MCL86/MCL86jr/MCL86jr/pa.fromNetlist.tcl
+# create_project -name MCL86jr -dir "C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_2" -part xc6slx9tqg144-3
+# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+# set_property edif_top_file "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {C:/MCL/MCL86/MCL86jr/MCL86jr} {ipcore_dir} }
+# add_files [list {ipcore_dir/EU4Kx32.ncf}] -fileset [get_property constrset [current_run]]
+# set_param project.pinAheadLayout  yes
+# set_property target_constrs_file "MCL86jr.ucf" [current_fileset -constrset]
+Adding file 'C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ucf' to fileset 'constrs_1'
+# add_files [list {MCL86jr.ucf}] -fileset [get_property constrset [current_run]]
+# link_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to project part: xc6slx9tqg144-3
+Release 14.7 - ngc2edif P.20131013 (nt64)

+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

+Reading design MCL86jr.ngc ...

+WARNING:NetListWriters:298 - No output is written to MCL86jr.xncf, ignored.

+Processing design ...

+   Preping design's networks ...

+   Preping design's macros ...

+WARNING:NetListWriters:306 - Signal bus EU_CORE/carry<16 : 3> on block MCL86jr

+   is not reconstructed, because there are some missing bus signals.

+WARNING:NetListWriters:306 - Signal bus

+   EU_CORE/eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT<12 : 0> on

+   block MCL86jr is not reconstructed, because there are some missing bus

+   signals.

+WARNING:NetListWriters:306 - Signal bus EU_CORE/eu_operand0<15 : 5> on block

+   MCL86jr is not reconstructed, because there are some missing bus signals.

+  finished :Prep

+Writing EDIF netlist file MCL86jr.edif ...

+ngc2edif: Total memory usage is 82712 kilobytes

+

+Parsing EDIF File [./planAhead_run_2/MCL86jr.data/cache/MCL86jr_ngc_zx.edif]
+Finished Parsing EDIF File [./planAhead_run_2/MCL86jr.data/cache/MCL86jr_ngc_zx.edif]
+Release 14.7 - ngc2edif P.20131013 (nt64)

+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

+Reading design EU4Kx32.ngc ...

+WARNING:NetListWriters:298 - No output is written to EU4Kx32.xncf, ignored.

+Processing design ...

+   Preping design's networks ...

+   Preping design's macros ...

+  finished :Prep

+Writing EDIF netlist file EU4Kx32.edif ...

+ngc2edif: Total memory usage is 78744 kilobytes

+

+Reading core file 'C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/EU4Kx32.ngc' for (cell view 'EU4Kx32', library 'MCL86jr_lib', file 'MCL86jr.ngc')
+Parsing EDIF File [./planAhead_run_2/MCL86jr.data/cache/EU4Kx32_ngc_zx.edif]
+Finished Parsing EDIF File [./planAhead_run_2/MCL86jr.data/cache/EU4Kx32_ngc_zx.edif]
+INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+WARNING: [Netlist 29-43] Netlist 'MCL86jr' is not ideal for floorplanning, since the cellview 'MCL86jr' defined in file 'MCL86jr.ngc' contains large number of primitives.  Please consider enabling hierarchy in synthesis if you want to do floorplanning.
+Loading clock regions from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/tqg144/Package.xml
+Loading io standards from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan6/IOStandards.xml
+Loading device configuration modes from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/ConfigModes.xml
+Loading list of drcs for the architecture : C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/EU4Kx32.ncf]
+Finished Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/EU4Kx32.ncf]
+Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ucf]
+Finished Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ucf]
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 9 instances were transformed.
+  BUFGP => BUFGP (IBUF, BUFG): 1 instances
+  IOBUF => IOBUF (OBUFT, IBUF): 8 instances
+
+Phase 0 | Netlist Checksum: 1658b132
+link_design: Time (s): elapsed = 00:00:15 . Memory (MB): peak = 607.238 ; gain = 172.105
+exit
+ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
+INFO: [Common 17-206] Exiting PlanAhead at Sat Sep 26 22:59:55 2020...
+INFO: [Common 17-83] Releasing license: PlanAhead
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/cache/EU4Kx32_ngc_zx.edif b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/cache/EU4Kx32_ngc_zx.edif
new file mode 100644
index 0000000..65c4b38
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/cache/EU4Kx32_ngc_zx.edif
@@ -0,0 +1,2660 @@
+(edif EU4Kx32
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2020 11 8 20 37 46)
+      (program "Xilinx ngc2edif" (version "P.20131013"))
+      (author "Xilinx. Inc ")
+      (comment "This EDIF netlist is to be used within supported synthesis tools")
+      (comment "for determining resource/timing estimates of the design component")
+      (comment "represented by this netlist.")
+      (comment "Command line: -mdp2sp -w -secure EU4Kx32.ngc EU4Kx32.edif ")))
+  (external UNISIMS
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell VCC
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port P
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell GND
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port G
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell RAMB16BWER
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port REGCEA
+              (direction INPUT)
+            )
+            (port CLKA
+              (direction INPUT)
+            )
+            (port ENB
+              (direction INPUT)
+            )
+            (port RSTB
+              (direction INPUT)
+            )
+            (port CLKB
+              (direction INPUT)
+            )
+            (port REGCEB
+              (direction INPUT)
+            )
+            (port RSTA
+              (direction INPUT)
+            )
+            (port ENA
+              (direction INPUT)
+            )
+            (port (array (rename DIPA "DIPA<3:0>") 4)
+              (direction INPUT))
+            (port (array (rename WEA "WEA<3:0>") 4)
+              (direction INPUT))
+            (port (array (rename DOA "DOA<31:0>") 32)
+              (direction OUTPUT))
+            (port (array (rename ADDRA "ADDRA<13:0>") 14)
+              (direction INPUT))
+            (port (array (rename ADDRB "ADDRB<13:0>") 14)
+              (direction INPUT))
+            (port (array (rename DIB "DIB<31:0>") 32)
+              (direction INPUT))
+            (port (array (rename DOPA "DOPA<3:0>") 4)
+              (direction OUTPUT))
+            (port (array (rename DIPB "DIPB<3:0>") 4)
+              (direction INPUT))
+            (port (array (rename DOPB "DOPB<3:0>") 4)
+              (direction OUTPUT))
+            (port (array (rename DOB "DOB<31:0>") 32)
+              (direction OUTPUT))
+            (port (array (rename WEB "WEB<3:0>") 4)
+              (direction INPUT))
+            (port (array (rename DIA "DIA<31:0>") 32)
+              (direction INPUT))
+          )
+      )
+    )
+    (cell RAMB8BWER
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port RSTBRST
+              (direction INPUT)
+            )
+            (port ENBRDEN
+              (direction INPUT)
+            )
+            (port REGCEA
+              (direction INPUT)
+            )
+            (port ENAWREN
+              (direction INPUT)
+            )
+            (port CLKAWRCLK
+              (direction INPUT)
+            )
+            (port CLKBRDCLK
+              (direction INPUT)
+            )
+            (port REGCEBREGCE
+              (direction INPUT)
+            )
+            (port RSTA
+              (direction INPUT)
+            )
+            (port (array (rename WEAWEL "WEAWEL<1:0>") 2)
+              (direction INPUT))
+            (port (array (rename DOADO "DOADO<15:0>") 16)
+              (direction OUTPUT))
+            (port (array (rename DOPADOP "DOPADOP<1:0>") 2)
+              (direction OUTPUT))
+            (port (array (rename DOPBDOP "DOPBDOP<1:0>") 2)
+              (direction OUTPUT))
+            (port (array (rename WEBWEU "WEBWEU<1:0>") 2)
+              (direction INPUT))
+            (port (array (rename ADDRAWRADDR "ADDRAWRADDR<12:0>") 13)
+              (direction INPUT))
+            (port (array (rename DIPBDIP "DIPBDIP<1:0>") 2)
+              (direction INPUT))
+            (port (array (rename DIBDI "DIBDI<15:0>") 16)
+              (direction INPUT))
+            (port (array (rename DIADI "DIADI<15:0>") 16)
+              (direction INPUT))
+            (port (array (rename ADDRBRDADDR "ADDRBRDADDR<12:0>") 13)
+              (direction INPUT))
+            (port (array (rename DOBDO "DOBDO<15:0>") 16)
+              (direction OUTPUT))
+            (port (array (rename DIPADIP "DIPADIP<1:0>") 2)
+              (direction INPUT))
+          )
+      )
+    )
+    (cell FDE
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port CE
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT3
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell INV
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+  )
+
+  (library EU4Kx32_lib
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell EU4Kx32
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port clka
+              (direction INPUT)
+            )
+            (port (array (rename addra "addra<11:0>") 12)
+              (direction INPUT))
+            (port (array (rename douta "douta<31:0>") 32)
+              (direction OUTPUT))
+            (designator "6slx9tqg144-2")
+            (property TYPE (string "EU4Kx32") (owner "Xilinx"))
+            (property BUS_INFO (string "12:INPUT:addra<11:0>") (owner "Xilinx"))
+            (property BUS_INFO (string "32:OUTPUT:douta<31:0>") (owner "Xilinx"))
+            (property X_CORE_INFO (string "blk_mem_gen_v7_3, Xilinx CORE Generator 14.7") (owner "Xilinx"))
+            (property CHECK_LICENSE_TYPE (string "EU4Kx32,blk_mem_gen_v7_3,{}") (owner "Xilinx"))
+            (property CORE_GENERATION_INFO (string "EU4Kx32,blk_mem_gen_v7_3,{c_addra_width=12,c_addrb_width=12,c_algorithm=1,c_axi_id_width=4,c_axi_slave_type=0,c_axi_type=1,c_byte_size=9,c_common_clk=0,c_default_data=0,c_disable_warn_bhv_coll=0,c_disable_warn_bhv_range=0,c_elaboration_dir=C_/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/tmp/_cg/,c_enable_32bit_address=0,c_family=spartan6,c_has_axi_id=0,c_has_ena=0,c_has_enb=0,c_has_injecterr=0,c_has_mem_output_regs_a=0,c_has_mem_output_regs_b=0,c_has_mux_output_regs_a=0,c_has_mux_output_regs_b=0,c_has_regcea=0,c_has_regceb=0,c_has_rsta=0,c_has_rstb=0,c_has_softecc_input_regs_a=0,c_has_softecc_output_regs_b=0,c_init_file=BlankString,c_init_file_name=EU4Kx32.mif,c_inita_val=0,c_initb_val=0,c_interface_type=0,c_load_init_file=1,c_mem_type=3,c_mux_pipeline_stages=0,c_prim_type=1,c_read_depth_a=4096,c_read_depth_b=4096,c_read_width_a=32,c_read_width_b=32,c_rst_priority_a=CE,c_rst_priority_b=CE,c_rst_type=SYNC,c_rstram_a=0,c_rstram_b=0,c_sim_collision_check=ALL,c_use_bram_block=0,c_use_byte_wea=0,c_use_byte_web=0,c_use_default_data=0,c_use_ecc=0,c_use_softecc=0,c_wea_width=1,c_web_width=1,c_write_depth_a=4096,c_write_depth_b=4096,c_write_mode_a=WRITE_FIRST,c_write_mode_b=WRITE_FIRST,c_write_width_a=32,c_write_width_b=32,c_xdevicefamily=spartan6}") (owner "Xilinx"))
+            (property SHREG_MIN_SIZE (string "-1") (owner "Xilinx"))
+            (property SHREG_EXTRACT_NGC (string "Yes") (owner "Xilinx"))
+            (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
+            (property NLW_MACRO_TAG (integer 0) (owner "Xilinx"))
+            (property NLW_MACRO_ALIAS (string "EU4Kx32_EU4Kx32") (owner "Xilinx"))
+          )
+          (contents
+            (instance XST_VCC
+              (viewRef view_1 (cellRef VCC (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance XST_GND
+              (viewRef view_1 (cellRef GND (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram")
+              (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRA<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEA<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOA<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "4:INPUT:WEB<3:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:INPUT:DIA<31:0>") (owner "Xilinx"))
+              (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx"))
+              (property DATA_WIDTH_A (integer 9) (owner "Xilinx"))
+              (property DATA_WIDTH_B (integer 9) (owner "Xilinx"))
+              (property DOA_REG (integer 0) (owner "Xilinx"))
+              (property DOB_REG (integer 0) (owner "Xilinx"))
+              (property EN_RSTRAM_A (string "FALSE") (owner "Xilinx"))
+              (property EN_RSTRAM_B (string "FALSE") (owner "Xilinx"))
+              (property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_05 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_06 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INITP_07 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx"))
+              (property INIT_00 (string "0000002052B2B7B10000002052B2B7B1000000002052B2B7000000002052B2B7") (owner "Xilinx"))
+              (property INIT_01 (string "000000000020B2B70000000020B322B7000000000020B2B7000000000020B2B7") (owner "Xilinx"))
+              (property INIT_02 (string "205352B22222B7B1205352B22222B7B100205352B22222B700205352B22222B7") (owner "Xilinx"))
+              (property INIT_03 (string "00002053B22222B7002053B22222B7B100002053B22222B700002053B22222B7") (owner "Xilinx"))
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+              (property WRITE_MODE_B (string "WRITE_FIRST") (owner "Xilinx"))
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+              (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx"))
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+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux71 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux71")
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+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___5___U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux111") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux131 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux131")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___5___U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux111") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
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+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux141 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux141")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___4___U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux141") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux151 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux151")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___4___U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux141") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux161 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux161")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___3___U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux161") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux171 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux171")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___3___U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux161") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux181 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux181")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___2___U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux181") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux191 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux191")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___2___U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux181") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux201 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux201")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___6___U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux101") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux211 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux211")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___1___U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux211") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux221 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux221")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
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+              (property PK_HLUTNM (string "___XLNM___1___U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux211") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
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+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux241 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux241")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
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+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux251 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/Mmux_dout_mux251")
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+              (property INIT_FILE (string "NONE") (owner "Xilinx"))
+              (property RSTTYPE (string "SYNC") (owner "Xilinx"))
+              (property RST_PRIORITY_A (string "CE") (owner "Xilinx"))
+              (property RST_PRIORITY_B (string "CE") (owner "Xilinx"))
+              (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx"))
+              (property SIM_DEVICE (string "SPARTAN6") (owner "Xilinx"))
+              (property SRVAL_A (string "000000000") (owner "Xilinx"))
+              (property SRVAL_B (string "000000000") (owner "Xilinx"))
+              (property WRITE_MODE_A (string "WRITE_FIRST") (owner "Xilinx"))
+              (property WRITE_MODE_B (string "WRITE_FIRST") (owner "Xilinx"))
+            )
+            (instance (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_bindec_a_bindec_inst_a_ADDR_0__GND_16_o_equal_1_o1_INV_0 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/ADDR[0]_GND_16_o_equal_1_o1_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (net N0
+              (joined
+                (portRef P (instanceRef XST_VCC))
+                (portRef CE (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_sel_pipe_0_renamed_0))
+                (portRef ENAWREN
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef ENA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net N1
+              (joined
+                (portRef G (instanceRef XST_GND))
+                (portRef (member ADDRAWRADDR 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRBRDADDR 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIADI 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIBDI 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIPADIP 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIPADIP 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIPBDIP 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member DIPBDIP 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member WEAWEL 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member WEAWEL 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member WEBWEU 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member WEBWEU 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef CLKBRDCLK
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef ENBRDEN
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef REGCEA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef REGCEBREGCE
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef RSTA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef RSTBRST
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 12) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 13) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 16) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 17) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 18) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 19) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 20) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 21) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 22) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 23) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIB 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member DIPB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member WEB 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef REGCEB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef RSTB
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_0_ "douta<0>")
+              (joined
+                (portRef (member douta 31))
+                (portRef (member DOADO 15) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+              )
+            )
+            (net (rename douta_1_ "douta<1>")
+              (joined
+                (portRef (member douta 30))
+                (portRef (member DOADO 14) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+              )
+            )
+            (net (rename douta_2_ "douta<2>")
+              (joined
+                (portRef (member douta 29))
+                (portRef (member DOA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_3_ "douta<3>")
+              (joined
+                (portRef (member douta 28))
+                (portRef (member DOA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_4_ "douta<4>")
+              (joined
+                (portRef (member douta 27))
+                (portRef (member DOA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_5_ "douta<5>")
+              (joined
+                (portRef (member douta 26))
+                (portRef (member DOA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_6_ "douta<6>")
+              (joined
+                (portRef (member douta 25))
+                (portRef (member DOA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_7_ "douta<7>")
+              (joined
+                (portRef (member douta 24))
+                (portRef (member DOA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_8_ "douta<8>")
+              (joined
+                (portRef (member douta 23))
+                (portRef (member DOA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_9_ "douta<9>")
+              (joined
+                (portRef (member douta 22))
+                (portRef (member DOA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_10_ "douta<10>")
+              (joined
+                (portRef (member douta 21))
+                (portRef (member DOA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_11_ "douta<11>")
+              (joined
+                (portRef (member douta 20))
+                (portRef (member DOA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_12_ "douta<12>")
+              (joined
+                (portRef (member douta 19))
+                (portRef (member DOA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_13_ "douta<13>")
+              (joined
+                (portRef (member douta 18))
+                (portRef (member DOA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename douta_14_ "douta<14>")
+              (joined
+                (portRef (member douta 17))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux61))
+              )
+            )
+            (net (rename douta_15_ "douta<15>")
+              (joined
+                (portRef (member douta 16))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux71))
+              )
+            )
+            (net (rename douta_16_ "douta<16>")
+              (joined
+                (portRef (member douta 15))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux81))
+              )
+            )
+            (net (rename douta_17_ "douta<17>")
+              (joined
+                (portRef (member douta 14))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux91))
+              )
+            )
+            (net (rename douta_18_ "douta<18>")
+              (joined
+                (portRef (member douta 13))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux101))
+              )
+            )
+            (net (rename douta_19_ "douta<19>")
+              (joined
+                (portRef (member douta 12))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux111))
+              )
+            )
+            (net (rename douta_20_ "douta<20>")
+              (joined
+                (portRef (member douta 11))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux131))
+              )
+            )
+            (net (rename douta_21_ "douta<21>")
+              (joined
+                (portRef (member douta 10))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux141))
+              )
+            )
+            (net (rename douta_22_ "douta<22>")
+              (joined
+                (portRef (member douta 9))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux151))
+              )
+            )
+            (net (rename douta_23_ "douta<23>")
+              (joined
+                (portRef (member douta 8))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux161))
+              )
+            )
+            (net (rename douta_24_ "douta<24>")
+              (joined
+                (portRef (member douta 7))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux171))
+              )
+            )
+            (net (rename douta_25_ "douta<25>")
+              (joined
+                (portRef (member douta 6))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux181))
+              )
+            )
+            (net (rename douta_26_ "douta<26>")
+              (joined
+                (portRef (member douta 5))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux191))
+              )
+            )
+            (net (rename douta_27_ "douta<27>")
+              (joined
+                (portRef (member douta 4))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux201))
+              )
+            )
+            (net (rename douta_28_ "douta<28>")
+              (joined
+                (portRef (member douta 3))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux211))
+              )
+            )
+            (net (rename douta_29_ "douta<29>")
+              (joined
+                (portRef (member douta 2))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux221))
+              )
+            )
+            (net (rename douta_30_ "douta<30>")
+              (joined
+                (portRef (member douta 1))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux241))
+              )
+            )
+            (net (rename douta_31_ "douta<31>")
+              (joined
+                (portRef (member douta 0))
+                (portRef O (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux251))
+              )
+            )
+            (net clka
+              (joined
+                (portRef clka)
+                (portRef C (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_sel_pipe_0_renamed_0))
+                (portRef CLKAWRCLK
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef CLKA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef CLKA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_0_ "addra<0>")
+              (joined
+                (portRef (member addra 11))
+                (portRef (member ADDRAWRADDR 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 11) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_1_ "addra<1>")
+              (joined
+                (portRef (member addra 10))
+                (portRef (member ADDRAWRADDR 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 10) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_2_ "addra<2>")
+              (joined
+                (portRef (member addra 9))
+                (portRef (member ADDRAWRADDR 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 9) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_3_ "addra<3>")
+              (joined
+                (portRef (member addra 8))
+                (portRef (member ADDRAWRADDR 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 8) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_4_ "addra<4>")
+              (joined
+                (portRef (member addra 7))
+                (portRef (member ADDRAWRADDR 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 7) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_5_ "addra<5>")
+              (joined
+                (portRef (member addra 6))
+                (portRef (member ADDRAWRADDR 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 6) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_6_ "addra<6>")
+              (joined
+                (portRef (member addra 5))
+                (portRef (member ADDRAWRADDR 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 5) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_7_ "addra<7>")
+              (joined
+                (portRef (member addra 4))
+                (portRef (member ADDRAWRADDR 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 4) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_8_ "addra<8>")
+              (joined
+                (portRef (member addra 3))
+                (portRef (member ADDRAWRADDR 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_9_ "addra<9>")
+              (joined
+                (portRef (member addra 2))
+                (portRef (member ADDRAWRADDR 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 2) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_10_ "addra<10>")
+              (joined
+                (portRef (member addra 1))
+                (portRef (member ADDRAWRADDR 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 1) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename addra_11_ "addra<11>")
+              (joined
+                (portRef (member addra 0))
+                (portRef D (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_sel_pipe_0_renamed_0))
+                (portRef (member ADDRAWRADDR 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0__ram_r_s6_init_ram_SP_SIMPLE_PRIM9_ram))
+                (portRef (member ADDRA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef (member ADDRA 0) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_bindec_a_bindec_inst_a_ADDR_0__GND_16_o_equal_1_o1_INV_0))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_bindec_a_bindec_inst_a_ADDR_0__GND_16_o_equal_1_o "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/ADDR[0]_GND_16_o_equal_1_o")
+              (joined
+                (portRef ENA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef ENA
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef O
+ (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_bindec_a_bindec_inst_a_ADDR_0__GND_16_o_equal_1_o1_INV_0))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_sel_pipe_0 "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_a.A/sel_pipe_0")
+              (joined
+                (portRef Q (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_sel_pipe_0_renamed_0))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux61))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux71))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux81))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux91))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux101))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux111))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux131))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux141))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux151))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux161))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux171))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux181))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux191))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux201))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux211))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux221))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux241))
+                (portRef I0 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux251))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_ram_douta_0_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_douta<0>")
+              (joined
+                (portRef (member DOA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux161))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_ram_douta_1_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_douta<1>")
+              (joined
+                (portRef (member DOA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux171))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_ram_douta_2_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_douta<2>")
+              (joined
+                (portRef (member DOA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux181))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_ram_douta_3_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_douta<3>")
+              (joined
+                (portRef (member DOA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux191))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_ram_douta_4_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_douta<4>")
+              (joined
+                (portRef (member DOA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux201))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_ram_douta_5_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_douta<5>")
+              (joined
+                (portRef (member DOA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux211))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_ram_douta_6_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_douta<6>")
+              (joined
+                (portRef (member DOA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux221))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_ram_douta_7_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_douta<7>")
+              (joined
+                (portRef (member DOA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux241))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_ram_douta_8_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.ram_douta<8>")
+              (joined
+                (portRef (member DOPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux251))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_ram_douta_0_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_douta<0>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux161))
+                (portRef (member DOA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_ram_douta_1_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_douta<1>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux171))
+                (portRef (member DOA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_ram_douta_2_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_douta<2>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux181))
+                (portRef (member DOA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_ram_douta_3_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_douta<3>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux191))
+                (portRef (member DOA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_ram_douta_4_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_douta<4>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux201))
+                (portRef (member DOA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_ram_douta_5_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_douta<5>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux211))
+                (portRef (member DOA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_ram_douta_6_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_douta<6>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux221))
+                (portRef (member DOA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_ram_douta_7_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_douta<7>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux241))
+                (portRef (member DOA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_ram_douta_8_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.ram_douta<8>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux251))
+                (portRef (member DOPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_ram_douta_0_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<0>")
+              (joined
+                (portRef (member DOA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux61))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_ram_douta_1_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<1>")
+              (joined
+                (portRef (member DOA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux71))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_ram_douta_2_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<2>")
+              (joined
+                (portRef (member DOA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux81))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_ram_douta_3_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<3>")
+              (joined
+                (portRef (member DOA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux91))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_ram_douta_4_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<4>")
+              (joined
+                (portRef (member DOA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux101))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_ram_douta_5_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<5>")
+              (joined
+                (portRef (member DOA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux111))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_ram_douta_6_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<6>")
+              (joined
+                (portRef (member DOA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux131))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_ram_douta_7_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<7>")
+              (joined
+                (portRef (member DOA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux141))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_ram_douta_8_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.ram_douta<8>")
+              (joined
+                (portRef (member DOPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+                (portRef I2 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux151))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_ram_douta_0_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<0>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux61))
+                (portRef (member DOA 31) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_ram_douta_1_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<1>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux71))
+                (portRef (member DOA 30) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_ram_douta_2_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<2>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux81))
+                (portRef (member DOA 29) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_ram_douta_3_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<3>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux91))
+                (portRef (member DOA 28) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_ram_douta_4_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<4>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux101))
+                (portRef (member DOA 27) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_ram_douta_5_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<5>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux111))
+                (portRef (member DOA 26) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_ram_douta_6_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<6>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux131))
+                (portRef (member DOA 25) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_ram_douta_7_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<7>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux141))
+                (portRef (member DOA 24) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+            (net (rename U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_ram_douta_8_ "U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.ram_douta<8>")
+              (joined
+                (portRef I1 (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_has_mux_a_A_Mmux_dout_mux151))
+                (portRef (member DOPA 3) (instanceRef U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4__ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram))
+              )
+            )
+          )
+      )
+    )
+  )
+
+  (design EU4Kx32
+    (cellRef EU4Kx32
+      (libraryRef EU4Kx32_lib)
+    )
+    (property PART (string "6slx9tqg144-2") (owner "Xilinx"))
+  )
+)
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/cache/MCL86jr_ngc_zx.edif b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/cache/MCL86jr_ngc_zx.edif
new file mode 100644
index 0000000..a28a6fd
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/cache/MCL86jr_ngc_zx.edif
@@ -0,0 +1,30706 @@
+(edif MCL86jr
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2020 11 8 20 37 42)
+      (program "Xilinx ngc2edif" (version "P.20131013"))
+      (author "Xilinx. Inc ")
+      (comment "This EDIF netlist is to be used within supported synthesis tools")
+      (comment "for determining resource/timing estimates of the design component")
+      (comment "represented by this netlist.")
+      (comment "Command line: -mdp2sp -w -secure MCL86jr.ngc MCL86jr.edif ")))
+  (external UNISIMS
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell VCC
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port P
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell GND
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port G
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FD
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FDRE
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port CE
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port R
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FDSE
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port CE
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell MUXCY
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CI
+              (direction INPUT)
+            )
+            (port DI
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell XORCY
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CI
+              (direction INPUT)
+            )
+            (port LI
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell BUFG
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port O
+              (direction OUTPUT)
+            )
+            (port I
+              (direction INPUT)
+            )
+          )
+      )
+    )
+    (cell DCM_SP
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CLK2X180
+              (direction OUTPUT)
+            )
+            (port PSCLK
+              (direction INPUT)
+            )
+            (port CLK2X
+              (direction OUTPUT)
+            )
+            (port CLKFX
+              (direction OUTPUT)
+            )
+            (port CLK180
+              (direction OUTPUT)
+            )
+            (port CLK270
+              (direction OUTPUT)
+            )
+            (port RST
+              (direction INPUT)
+            )
+            (port PSINCDEC
+              (direction INPUT)
+            )
+            (port CLKIN
+              (direction INPUT)
+            )
+            (port CLKFB
+              (direction INPUT)
+            )
+            (port PSEN
+              (direction INPUT)
+            )
+            (port CLK0
+              (direction OUTPUT)
+            )
+            (port CLKFX180
+              (direction OUTPUT)
+            )
+            (port CLKDV
+              (direction OUTPUT)
+            )
+            (port PSDONE
+              (direction OUTPUT)
+            )
+            (port CLK90
+              (direction OUTPUT)
+            )
+            (port LOCKED
+              (direction OUTPUT)
+            )
+            (port DSSEN
+              (direction INPUT)
+            )
+            (port (rename STATUS_7_ "STATUS<7>")
+              (direction OUTPUT)
+              (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx"))
+              (property PIN_BUSIDX (integer 0) (owner "Xilinx"))
+            )
+            (port (rename STATUS_6_ "STATUS<6>")
+              (direction OUTPUT)
+              (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx"))
+              (property PIN_BUSIDX (integer 1) (owner "Xilinx"))
+            )
+            (port (rename STATUS_5_ "STATUS<5>")
+              (direction OUTPUT)
+              (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx"))
+              (property PIN_BUSIDX (integer 2) (owner "Xilinx"))
+            )
+            (port (rename STATUS_4_ "STATUS<4>")
+              (direction OUTPUT)
+              (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx"))
+              (property PIN_BUSIDX (integer 3) (owner "Xilinx"))
+            )
+            (port (rename STATUS_3_ "STATUS<3>")
+              (direction OUTPUT)
+              (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx"))
+              (property PIN_BUSIDX (integer 4) (owner "Xilinx"))
+            )
+            (port (rename STATUS_2_ "STATUS<2>")
+              (direction OUTPUT)
+              (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx"))
+              (property PIN_BUSIDX (integer 5) (owner "Xilinx"))
+            )
+            (port (rename STATUS_1_ "STATUS<1>")
+              (direction OUTPUT)
+              (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx"))
+              (property PIN_BUSIDX (integer 6) (owner "Xilinx"))
+            )
+            (port (rename STATUS_0_ "STATUS<0>")
+              (direction OUTPUT)
+              (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx"))
+              (property PIN_BUSIDX (integer 7) (owner "Xilinx"))
+            )
+          )
+      )
+    )
+    (cell IBUFG
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT2
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT3
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FDE
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port CE
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FDR
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port R
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
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+    (cell FDS
+      (cellType GENERIC)
+        (view view_1
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+            (port C
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+            (port D
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+            )
+            (port S
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT5
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port I3
+              (direction INPUT)
+            )
+            (port I4
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT6
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port I3
+              (direction INPUT)
+            )
+            (port I4
+              (direction INPUT)
+            )
+            (port I5
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell MUXF7
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell MUXF8
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT4
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port I3
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell IBUF
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell OBUF
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell IOBUF
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port T
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+            (port IO
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT1
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell INV
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell SRLC16E
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port A0
+              (direction INPUT)
+            )
+            (port A1
+              (direction INPUT)
+            )
+            (port A2
+              (direction INPUT)
+            )
+            (port A3
+              (direction INPUT)
+            )
+            (port CE
+              (direction INPUT)
+            )
+            (port CLK
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+            (port Q15
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+  )
+
+  (library MCL86jr_lib
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell EU4Kx32
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port clka
+              (direction INPUT)
+            )
+            (port (array (rename addra "addra<11:0>") 12)
+              (direction INPUT))
+            (port (array (rename douta "douta<31:0>") 32)
+              (direction OUTPUT))
+          )
+      )
+    )
+    (cell MCL86jr
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CORE_CLK
+              (direction INPUT)
+            )
+            (port CLK
+              (direction INPUT)
+            )
+            (port RESET
+              (direction INPUT)
+            )
+            (port READY
+              (direction INPUT)
+            )
+            (port INTR
+              (direction INPUT)
+            )
+            (port NMI
+              (direction INPUT)
+            )
+            (port A19
+              (direction OUTPUT)
+            )
+            (port A18
+              (direction OUTPUT)
+            )
+            (port A17
+              (direction OUTPUT)
+            )
+            (port A16
+              (direction OUTPUT)
+            )
+            (port A15
+              (direction OUTPUT)
+            )
+            (port A14
+              (direction OUTPUT)
+            )
+            (port A13
+              (direction OUTPUT)
+            )
+            (port A12
+              (direction OUTPUT)
+            )
+            (port A11
+              (direction OUTPUT)
+            )
+            (port A10
+              (direction OUTPUT)
+            )
+            (port A9
+              (direction OUTPUT)
+            )
+            (port A8
+              (direction OUTPUT)
+            )
+            (port AD7
+              (direction INOUT)
+            )
+            (port AD6
+              (direction INOUT)
+            )
+            (port AD5
+              (direction INOUT)
+            )
+            (port AD4
+              (direction INOUT)
+            )
+            (port AD3
+              (direction INOUT)
+            )
+            (port AD2
+              (direction INOUT)
+            )
+            (port AD1
+              (direction INOUT)
+            )
+            (port AD0
+              (direction INOUT)
+            )
+            (port ALE
+              (direction OUTPUT)
+            )
+            (port INTA_n
+              (direction OUTPUT)
+            )
+            (port RD_n
+              (direction OUTPUT)
+            )
+            (port WR_n
+              (direction OUTPUT)
+            )
+            (port IOM
+              (direction OUTPUT)
+            )
+            (port DTR
+              (direction OUTPUT)
+            )
+            (port DEN
+              (direction OUTPUT)
+            )
+            (port SSO_n
+              (direction OUTPUT)
+            )
+            (port SRAM_CE_n
+              (direction OUTPUT)
+            )
+            (port SRAM_OE_n
+              (direction OUTPUT)
+            )
+            (port SRAM_WE_n
+              (direction OUTPUT)
+            )
+            (port BUF1_OE_n
+              (direction OUTPUT)
+            )
+            (port BUF2_OE_n
+              (direction OUTPUT)
+            )
+            (port BUF2_DIR
+              (direction OUTPUT)
+            )
+            (port (array (rename SRAM_A "SRAM_A<18:0>") 19)
+              (direction OUTPUT))
+            (port (array (rename SRAM_D "SRAM_D<7:0>") 8)
+              (direction INOUT))
+            (port (array (rename LED "LED<7:0>") 8)
+              (direction OUTPUT))
+            (designator "xc6slx9-3-tqg144")
+            (property TYPE (string "MCL86jr") (owner "Xilinx"))
+            (property BUS_INFO (string "19:OUTPUT:SRAM_A<18:0>") (owner "Xilinx"))
+            (property BUS_INFO (string "8:INOUT:SRAM_D<7:0>") (owner "Xilinx"))
+            (property BUS_INFO (string "8:OUTPUT:LED<7:0>") (owner "Xilinx"))
+            (property SHREG_MIN_SIZE (string "2") (owner "Xilinx"))
+            (property X_CORE_INFO (string "blk_mem_gen_v7_3, Xilinx CORE Generator 14.7") (owner "Xilinx"))
+            (property CORE_GENERATION_INFO (string "spartan6_pll,clk_wiz_v3_6,{component_name=spartan6_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}") (owner "Xilinx"))
+            (property SHREG_EXTRACT_NGC (string "YES") (owner "Xilinx"))
+            (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
+            (property NLW_MACRO_TAG (integer 0) (owner "Xilinx"))
+            (property NLW_MACRO_ALIAS (string "MCL86jr_MCL86jr") (owner "Xilinx"))
+          )
+          (contents
+            (instance XST_VCC
+              (viewRef view_1 (cellRef VCC (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance XST_GND
+              (viewRef view_1 (cellRef GND (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_0
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_1
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_2
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_3
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_4
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_5
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_6
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_7
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_8
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_9
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_10
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_11
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_12
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_13
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_14
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_15
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_16
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_17
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_18
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance t_biu_ad_out_d_19
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance led_int_0
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance led_int_1
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance led_int_2
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance led_int_3
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance led_int_4
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance led_int_5
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance led_int_6
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance led_int_7
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename prescaler_d_renamed_1 "prescaler_d")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename t_reset_d3_renamed_2 "t_reset_d3")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance prescaler_0
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_1
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_2
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_3
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_4
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_5
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_6
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_7
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_8
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_9
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_10
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_11
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_12
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_13
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_14
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_15
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_16
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_17
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_18
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_19
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_20
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance prescaler_21
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_0__ "Mcount_prescaler_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_0__ "Mcount_prescaler_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_1__ "Mcount_prescaler_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_1__ "Mcount_prescaler_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_2__ "Mcount_prescaler_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_2__ "Mcount_prescaler_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_3__ "Mcount_prescaler_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_3__ "Mcount_prescaler_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_4__ "Mcount_prescaler_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_4__ "Mcount_prescaler_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_5__ "Mcount_prescaler_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_5__ "Mcount_prescaler_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_6__ "Mcount_prescaler_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_6__ "Mcount_prescaler_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_7__ "Mcount_prescaler_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_7__ "Mcount_prescaler_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_8__ "Mcount_prescaler_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_8__ "Mcount_prescaler_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_9__ "Mcount_prescaler_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_9__ "Mcount_prescaler_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_10__ "Mcount_prescaler_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_10__ "Mcount_prescaler_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_11__ "Mcount_prescaler_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_11__ "Mcount_prescaler_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_12__ "Mcount_prescaler_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_12__ "Mcount_prescaler_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_13__ "Mcount_prescaler_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_13__ "Mcount_prescaler_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_14__ "Mcount_prescaler_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_14__ "Mcount_prescaler_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_15__ "Mcount_prescaler_cy<15>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_15__ "Mcount_prescaler_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_16__ "Mcount_prescaler_cy<16>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_16__ "Mcount_prescaler_xor<16>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_17__ "Mcount_prescaler_cy<17>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_17__ "Mcount_prescaler_xor<17>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_18__ "Mcount_prescaler_cy<18>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_18__ "Mcount_prescaler_xor<18>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_19__ "Mcount_prescaler_cy<19>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_19__ "Mcount_prescaler_xor<19>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_20__ "Mcount_prescaler_cy<20>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_20__ "Mcount_prescaler_xor<20>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_21__ "Mcount_prescaler_xor<21>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename SPARTAN6PLL_clkout1_buf "SPARTAN6PLL/clkout1_buf")
+              (viewRef view_1 (cellRef BUFG (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx"))
+            )
+            (instance (rename SPARTAN6PLL_dcm_sp_inst "SPARTAN6PLL/dcm_sp_inst")
+              (viewRef view_1 (cellRef DCM_SP (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property BUS_INFO (string "8:OUTPUT:STATUS<7:0>") (owner "Xilinx"))
+              (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx"))
+              (property CLKIN_DIVIDE_BY_2 (string "FALSE") (owner "Xilinx"))
+              (property CLKOUT_PHASE_SHIFT (string "NONE") (owner "Xilinx"))
+              (property CLK_FEEDBACK (string "NONE") (owner "Xilinx"))
+              (property DESKEW_ADJUST (string "SYSTEM_SYNCHRONOUS") (owner "Xilinx"))
+              (property DFS_FREQUENCY_MODE (string "LOW") (owner "Xilinx"))
+              (property DLL_FREQUENCY_MODE (string "LOW") (owner "Xilinx"))
+              (property DSS_MODE (string "NONE") (owner "Xilinx"))
+              (property DUTY_CYCLE_CORRECTION (string "TRUE") (owner "Xilinx"))
+              (property FACTORY_JF (string "16'B1100000010000000") (owner "Xilinx"))
+              (property STARTUP_WAIT (string "FALSE") (owner "Xilinx"))
+              (property CLKFX_DIVIDE (integer 1) (owner "Xilinx"))
+              (property CLKFX_MULTIPLY (integer 2) (owner "Xilinx"))
+              (property PHASE_SHIFT (integer 0) (owner "Xilinx"))
+              (property CLKDV_DIVIDE (number (e 2 0)) (owner "Xilinx"))
+              (property CLKIN_PERIOD (string "20.000000") (owner "Xilinx"))
+              (property VERY_HIGH_FREQUENCY (string "FALSE") (owner "Xilinx"))
+            )
+            (instance (rename SPARTAN6PLL_clkin1_buf "SPARTAN6PLL/clkin1_buf")
+              (viewRef view_1 (cellRef IBUFG (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx"))
+              (property CAPACITANCE (string "DONT_CARE") (owner "Xilinx"))
+              (property IBUF_DELAY_VALUE (string "0") (owner "Xilinx"))
+              (property IBUF_LOW_PWR (string "TRUE") (owner "Xilinx"))
+              (property IOSTANDARD (string "DEFAULT") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_19__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_xor<19>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_18__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_xor<18>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_18__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<18>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_17__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_xor<17>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_17__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<17>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_16__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_xor<16>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_16__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<16>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_15__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_15__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<15>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_15__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<15>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_14__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_14__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_14__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<14>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_13__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_13__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_13__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<13>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_12__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_12__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_12__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<12>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_11__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_11__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_11__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<11>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_10__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_10__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_10__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<10>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_9__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_9__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_9__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<9>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_8__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_8__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_8__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<8>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_7__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_7__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_7__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<7>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_6__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_6__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_6__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<6>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_5__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_5__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_5__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<5>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_4__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_4__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_4__ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<4>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_15__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_14__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_14__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_13__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_13__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_12__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_12__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_11__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_11__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_10__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_10__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_9__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_9__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_8__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_8__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_7__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_7__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_6__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_6__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_5__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_5__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_4__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_4__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_3__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_3__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_2__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_2__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_1__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_1__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_0__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_0__ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_19__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_xor<19>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_18__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_xor<18>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_18__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<18>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_17__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_xor<17>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_17__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<17>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_16__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_xor<16>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_16__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<16>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_15__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_15__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<15>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_15__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<15>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_14__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_14__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_14__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<14>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_13__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_13__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_13__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<13>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_12__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_12__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_12__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<12>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_11__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_11__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_11__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<11>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_10__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_10__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_10__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<10>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_9__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_9__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_9__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<9>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_8__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_8__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_8__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<8>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_7__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_7__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_7__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<7>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_6__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_6__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_6__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<6>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_5__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_5__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_5__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<5>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_4__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_4__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_4__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<4>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_19__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_xor<19>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_18__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_xor<18>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_18__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<18>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_17__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_xor<17>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_17__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<17>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_16__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_xor<16>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_16__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<16>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_15__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_15__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<15>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_15__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<15>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_14__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_14__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_14__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<14>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_13__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_13__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_13__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<13>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_12__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_12__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_12__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<12>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_11__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_11__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_11__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<11>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_10__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_10__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_10__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<10>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_9__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_9__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_9__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<9>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_8__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_8__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_8__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<8>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_7__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_7__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_7__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<7>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_6__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_6__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_6__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<6>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_5__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_5__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_5__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<5>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_4__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_4__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_4__ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<4>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_19__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_xor<19>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_18__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_xor<18>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_18__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<18>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_17__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_xor<17>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_17__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<17>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_16__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_xor<16>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_16__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<16>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_15__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_15__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<15>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_15__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<15>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_14__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_14__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_14__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<14>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_13__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_13__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_13__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<13>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_12__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_12__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_12__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<12>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_11__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_11__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_11__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<11>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_10__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_10__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_10__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<10>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_9__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_9__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_9__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<9>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_8__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_8__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_8__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<8>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_7__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_7__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_7__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<7>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_6__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_6__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_6__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<6>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_5__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_5__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_5__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<5>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_4__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_4__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_4__ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<4>")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_15 "BIU_CORE/pfq_addr_out_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_14 "BIU_CORE/pfq_addr_out_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_13 "BIU_CORE/pfq_addr_out_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_12 "BIU_CORE/pfq_addr_out_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_11 "BIU_CORE/pfq_addr_out_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_10 "BIU_CORE/pfq_addr_out_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_9 "BIU_CORE/pfq_addr_out_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_8 "BIU_CORE/pfq_addr_out_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_7 "BIU_CORE/pfq_addr_out_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_6 "BIU_CORE/pfq_addr_out_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_5 "BIU_CORE/pfq_addr_out_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_4 "BIU_CORE/pfq_addr_out_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_3 "BIU_CORE/pfq_addr_out_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_2 "BIU_CORE/pfq_addr_out_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_1 "BIU_CORE/pfq_addr_out_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_0 "BIU_CORE/pfq_addr_out_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_12 "BIU_CORE/clock_cycle_counter_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_11 "BIU_CORE/clock_cycle_counter_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_10 "BIU_CORE/clock_cycle_counter_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_9 "BIU_CORE/clock_cycle_counter_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_8 "BIU_CORE/clock_cycle_counter_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_7 "BIU_CORE/clock_cycle_counter_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_6 "BIU_CORE/clock_cycle_counter_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_5 "BIU_CORE/clock_cycle_counter_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_4 "BIU_CORE/clock_cycle_counter_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_3 "BIU_CORE/clock_cycle_counter_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_2 "BIU_CORE/clock_cycle_counter_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_1 "BIU_CORE/clock_cycle_counter_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clock_cycle_counter_0 "BIU_CORE/clock_cycle_counter_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_15 "BIU_CORE/pfq_addr_in_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_14 "BIU_CORE/pfq_addr_in_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_13 "BIU_CORE/pfq_addr_in_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_12 "BIU_CORE/pfq_addr_in_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_11 "BIU_CORE/pfq_addr_in_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_10 "BIU_CORE/pfq_addr_in_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_9 "BIU_CORE/pfq_addr_in_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_8 "BIU_CORE/pfq_addr_in_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_7 "BIU_CORE/pfq_addr_in_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_6 "BIU_CORE/pfq_addr_in_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_5 "BIU_CORE/pfq_addr_in_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_4 "BIU_CORE/pfq_addr_in_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_3 "BIU_CORE/pfq_addr_in_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_2 "BIU_CORE/pfq_addr_in_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_1 "BIU_CORE/pfq_addr_in_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_in_0 "BIU_CORE/pfq_addr_in_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_15__ "BIU_CORE/Mcount_pfq_addr_in_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_15__ "BIU_CORE/Mcount_pfq_addr_in_lut<15>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_14__ "BIU_CORE/Mcount_pfq_addr_in_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_14__ "BIU_CORE/Mcount_pfq_addr_in_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_14__ "BIU_CORE/Mcount_pfq_addr_in_lut<14>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_13__ "BIU_CORE/Mcount_pfq_addr_in_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_13__ "BIU_CORE/Mcount_pfq_addr_in_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_13__ "BIU_CORE/Mcount_pfq_addr_in_lut<13>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_12__ "BIU_CORE/Mcount_pfq_addr_in_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_12__ "BIU_CORE/Mcount_pfq_addr_in_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_12__ "BIU_CORE/Mcount_pfq_addr_in_lut<12>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_11__ "BIU_CORE/Mcount_pfq_addr_in_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_11__ "BIU_CORE/Mcount_pfq_addr_in_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_11__ "BIU_CORE/Mcount_pfq_addr_in_lut<11>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_10__ "BIU_CORE/Mcount_pfq_addr_in_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_10__ "BIU_CORE/Mcount_pfq_addr_in_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_10__ "BIU_CORE/Mcount_pfq_addr_in_lut<10>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_9__ "BIU_CORE/Mcount_pfq_addr_in_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_9__ "BIU_CORE/Mcount_pfq_addr_in_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_9__ "BIU_CORE/Mcount_pfq_addr_in_lut<9>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_8__ "BIU_CORE/Mcount_pfq_addr_in_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_8__ "BIU_CORE/Mcount_pfq_addr_in_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_8__ "BIU_CORE/Mcount_pfq_addr_in_lut<8>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_7__ "BIU_CORE/Mcount_pfq_addr_in_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_7__ "BIU_CORE/Mcount_pfq_addr_in_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_7__ "BIU_CORE/Mcount_pfq_addr_in_lut<7>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_6__ "BIU_CORE/Mcount_pfq_addr_in_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_6__ "BIU_CORE/Mcount_pfq_addr_in_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_6__ "BIU_CORE/Mcount_pfq_addr_in_lut<6>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_5__ "BIU_CORE/Mcount_pfq_addr_in_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_5__ "BIU_CORE/Mcount_pfq_addr_in_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_5__ "BIU_CORE/Mcount_pfq_addr_in_lut<5>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_4__ "BIU_CORE/Mcount_pfq_addr_in_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_4__ "BIU_CORE/Mcount_pfq_addr_in_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_4__ "BIU_CORE/Mcount_pfq_addr_in_lut<4>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_3__ "BIU_CORE/Mcount_pfq_addr_in_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_3__ "BIU_CORE/Mcount_pfq_addr_in_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_3__ "BIU_CORE/Mcount_pfq_addr_in_lut<3>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_2__ "BIU_CORE/Mcount_pfq_addr_in_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_2__ "BIU_CORE/Mcount_pfq_addr_in_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_2__ "BIU_CORE/Mcount_pfq_addr_in_lut<2>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_1__ "BIU_CORE/Mcount_pfq_addr_in_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_1__ "BIU_CORE/Mcount_pfq_addr_in_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_1__ "BIU_CORE/Mcount_pfq_addr_in_lut<1>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_xor_0__ "BIU_CORE/Mcount_pfq_addr_in_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_cy_0__ "BIU_CORE/Mcount_pfq_addr_in_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_in_lut_0__ "BIU_CORE/Mcount_pfq_addr_in_lut<0>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_15__ "BIU_CORE/Mcount_pfq_addr_out_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_15__ "BIU_CORE/Mcount_pfq_addr_out_lut<15>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_14__ "BIU_CORE/Mcount_pfq_addr_out_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_14__ "BIU_CORE/Mcount_pfq_addr_out_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_14__ "BIU_CORE/Mcount_pfq_addr_out_lut<14>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_13__ "BIU_CORE/Mcount_pfq_addr_out_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_13__ "BIU_CORE/Mcount_pfq_addr_out_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_13__ "BIU_CORE/Mcount_pfq_addr_out_lut<13>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_12__ "BIU_CORE/Mcount_pfq_addr_out_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_12__ "BIU_CORE/Mcount_pfq_addr_out_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_12__ "BIU_CORE/Mcount_pfq_addr_out_lut<12>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_11__ "BIU_CORE/Mcount_pfq_addr_out_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_11__ "BIU_CORE/Mcount_pfq_addr_out_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_11__ "BIU_CORE/Mcount_pfq_addr_out_lut<11>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_10__ "BIU_CORE/Mcount_pfq_addr_out_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_10__ "BIU_CORE/Mcount_pfq_addr_out_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_10__ "BIU_CORE/Mcount_pfq_addr_out_lut<10>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_9__ "BIU_CORE/Mcount_pfq_addr_out_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_9__ "BIU_CORE/Mcount_pfq_addr_out_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_9__ "BIU_CORE/Mcount_pfq_addr_out_lut<9>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_8__ "BIU_CORE/Mcount_pfq_addr_out_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_8__ "BIU_CORE/Mcount_pfq_addr_out_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_8__ "BIU_CORE/Mcount_pfq_addr_out_lut<8>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_7__ "BIU_CORE/Mcount_pfq_addr_out_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_7__ "BIU_CORE/Mcount_pfq_addr_out_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_7__ "BIU_CORE/Mcount_pfq_addr_out_lut<7>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_6__ "BIU_CORE/Mcount_pfq_addr_out_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_6__ "BIU_CORE/Mcount_pfq_addr_out_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_6__ "BIU_CORE/Mcount_pfq_addr_out_lut<6>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_5__ "BIU_CORE/Mcount_pfq_addr_out_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_5__ "BIU_CORE/Mcount_pfq_addr_out_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_5__ "BIU_CORE/Mcount_pfq_addr_out_lut<5>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_4__ "BIU_CORE/Mcount_pfq_addr_out_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_4__ "BIU_CORE/Mcount_pfq_addr_out_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_4__ "BIU_CORE/Mcount_pfq_addr_out_lut<4>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_3__ "BIU_CORE/Mcount_pfq_addr_out_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_3__ "BIU_CORE/Mcount_pfq_addr_out_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_3__ "BIU_CORE/Mcount_pfq_addr_out_lut<3>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_2__ "BIU_CORE/Mcount_pfq_addr_out_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_2__ "BIU_CORE/Mcount_pfq_addr_out_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_2__ "BIU_CORE/Mcount_pfq_addr_out_lut<2>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_1__ "BIU_CORE/Mcount_pfq_addr_out_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_1__ "BIU_CORE/Mcount_pfq_addr_out_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_1__ "BIU_CORE/Mcount_pfq_addr_out_lut<1>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_xor_0__ "BIU_CORE/Mcount_pfq_addr_out_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_cy_0__ "BIU_CORE/Mcount_pfq_addr_out_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_pfq_addr_out_lut_0__ "BIU_CORE/Mcount_pfq_addr_out_lut<0>")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_12__ "BIU_CORE/Mcount_clock_cycle_counter_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_11__ "BIU_CORE/Mcount_clock_cycle_counter_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_11__ "BIU_CORE/Mcount_clock_cycle_counter_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_10__ "BIU_CORE/Mcount_clock_cycle_counter_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_10__ "BIU_CORE/Mcount_clock_cycle_counter_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_9__ "BIU_CORE/Mcount_clock_cycle_counter_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_9__ "BIU_CORE/Mcount_clock_cycle_counter_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_8__ "BIU_CORE/Mcount_clock_cycle_counter_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_8__ "BIU_CORE/Mcount_clock_cycle_counter_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_7__ "BIU_CORE/Mcount_clock_cycle_counter_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_7__ "BIU_CORE/Mcount_clock_cycle_counter_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_6__ "BIU_CORE/Mcount_clock_cycle_counter_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_6__ "BIU_CORE/Mcount_clock_cycle_counter_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_5__ "BIU_CORE/Mcount_clock_cycle_counter_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_5__ "BIU_CORE/Mcount_clock_cycle_counter_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_4__ "BIU_CORE/Mcount_clock_cycle_counter_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_4__ "BIU_CORE/Mcount_clock_cycle_counter_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_3__ "BIU_CORE/Mcount_clock_cycle_counter_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_3__ "BIU_CORE/Mcount_clock_cycle_counter_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_2__ "BIU_CORE/Mcount_clock_cycle_counter_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_2__ "BIU_CORE/Mcount_clock_cycle_counter_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_1__ "BIU_CORE/Mcount_clock_cycle_counter_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_1__ "BIU_CORE/Mcount_clock_cycle_counter_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_xor_0__ "BIU_CORE/Mcount_clock_cycle_counter_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_cy_0__ "BIU_CORE/Mcount_clock_cycle_counter_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_top_byte_int_d1_7 "BIU_CORE/pfq_top_byte_int_d1_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_top_byte_int_d1_6 "BIU_CORE/pfq_top_byte_int_d1_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_top_byte_int_d1_5 "BIU_CORE/pfq_top_byte_int_d1_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_top_byte_int_d1_4 "BIU_CORE/pfq_top_byte_int_d1_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_top_byte_int_d1_3 "BIU_CORE/pfq_top_byte_int_d1_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_top_byte_int_d1_2 "BIU_CORE/pfq_top_byte_int_d1_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_top_byte_int_d1_1 "BIU_CORE/pfq_top_byte_int_d1_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_top_byte_int_d1_0 "BIU_CORE/pfq_top_byte_int_d1_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_nmi_d5_renamed_3 "BIU_CORE/nmi_d5")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_s_bits_2 "BIU_CORE/s_bits_2")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_s_bits_1 "BIU_CORE/s_bits_1")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_s_bits_0 "BIU_CORE/s_bits_0")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_15 "BIU_CORE/biu_return_data_int_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_14 "BIU_CORE/biu_return_data_int_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_13 "BIU_CORE/biu_return_data_int_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_12 "BIU_CORE/biu_return_data_int_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_11 "BIU_CORE/biu_return_data_int_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_10 "BIU_CORE/biu_return_data_int_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_9 "BIU_CORE/biu_return_data_int_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_8 "BIU_CORE/biu_return_data_int_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_7 "BIU_CORE/biu_return_data_int_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_6 "BIU_CORE/biu_return_data_int_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_5 "BIU_CORE/biu_return_data_int_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_4 "BIU_CORE/biu_return_data_int_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_3 "BIU_CORE/biu_return_data_int_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_2 "BIU_CORE/biu_return_data_int_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_1 "BIU_CORE/biu_return_data_int_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_0 "BIU_CORE/biu_return_data_int_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ALE_renamed_4 "BIU_CORE/ALE")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_nmi_d4_renamed_5 "BIU_CORE/nmi_d4")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clk_d4_renamed_6 "BIU_CORE/clk_d4")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry3_7 "BIU_CORE/pfq_entry3_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry3_6 "BIU_CORE/pfq_entry3_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry3_5 "BIU_CORE/pfq_entry3_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry3_4 "BIU_CORE/pfq_entry3_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry3_3 "BIU_CORE/pfq_entry3_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry3_2 "BIU_CORE/pfq_entry3_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry3_1 "BIU_CORE/pfq_entry3_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry3_0 "BIU_CORE/pfq_entry3_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry2_7 "BIU_CORE/pfq_entry2_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry2_6 "BIU_CORE/pfq_entry2_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry2_5 "BIU_CORE/pfq_entry2_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry2_4 "BIU_CORE/pfq_entry2_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry2_3 "BIU_CORE/pfq_entry2_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry2_2 "BIU_CORE/pfq_entry2_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry2_1 "BIU_CORE/pfq_entry2_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry2_0 "BIU_CORE/pfq_entry2_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry0_7 "BIU_CORE/pfq_entry0_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry0_6 "BIU_CORE/pfq_entry0_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry0_5 "BIU_CORE/pfq_entry0_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry0_4 "BIU_CORE/pfq_entry0_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry0_3 "BIU_CORE/pfq_entry0_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry0_2 "BIU_CORE/pfq_entry0_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry0_1 "BIU_CORE/pfq_entry0_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry0_0 "BIU_CORE/pfq_entry0_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry1_7 "BIU_CORE/pfq_entry1_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry1_6 "BIU_CORE/pfq_entry1_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry1_5 "BIU_CORE/pfq_entry1_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry1_4 "BIU_CORE/pfq_entry1_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry1_3 "BIU_CORE/pfq_entry1_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry1_2 "BIU_CORE/pfq_entry1_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry1_1 "BIU_CORE/pfq_entry1_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_entry1_0 "BIU_CORE/pfq_entry1_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_15 "BIU_CORE/pfq_addr_out_d1_15")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_14 "BIU_CORE/pfq_addr_out_d1_14")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_13 "BIU_CORE/pfq_addr_out_d1_13")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_12 "BIU_CORE/pfq_addr_out_d1_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_11 "BIU_CORE/pfq_addr_out_d1_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_10 "BIU_CORE/pfq_addr_out_d1_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_9 "BIU_CORE/pfq_addr_out_d1_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_8 "BIU_CORE/pfq_addr_out_d1_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_7 "BIU_CORE/pfq_addr_out_d1_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_6 "BIU_CORE/pfq_addr_out_d1_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_5 "BIU_CORE/pfq_addr_out_d1_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_4 "BIU_CORE/pfq_addr_out_d1_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_3 "BIU_CORE/pfq_addr_out_d1_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_2 "BIU_CORE/pfq_addr_out_d1_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_1 "BIU_CORE/pfq_addr_out_d1_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_addr_out_d1_0 "BIU_CORE/pfq_addr_out_d1_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_intr_d3_renamed_7 "BIU_CORE/intr_d3")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_nmi_d3_renamed_8 "BIU_CORE/nmi_d3")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clk_d3_renamed_9 "BIU_CORE/clk_d3")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_latched_data_in_7 "BIU_CORE/latched_data_in_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_latched_data_in_6 "BIU_CORE/latched_data_in_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_latched_data_in_5 "BIU_CORE/latched_data_in_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_latched_data_in_4 "BIU_CORE/latched_data_in_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_latched_data_in_3 "BIU_CORE/latched_data_in_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_latched_data_in_2 "BIU_CORE/latched_data_in_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_latched_data_in_1 "BIU_CORE/latched_data_in_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_latched_data_in_0 "BIU_CORE/latched_data_in_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_DEN_renamed_10 "BIU_CORE/DEN")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_WR_n_renamed_11 "BIU_CORE/WR_n")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_INTA_n_renamed_12 "BIU_CORE/INTA_n")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_RD_n_renamed_13 "BIU_CORE/RD_n")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_DTR_renamed_14 "BIU_CORE/DTR")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_IOM_renamed_15 "BIU_CORE/IOM")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_intr_d2_renamed_16 "BIU_CORE/intr_d2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_nmi_d2_renamed_17 "BIU_CORE/nmi_d2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clk_d2_renamed_18 "BIU_CORE/clk_d2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_19_renamed_19 "BIU_CORE/AD_OUT_19")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_18_renamed_20 "BIU_CORE/AD_OUT_18")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_17_renamed_21 "BIU_CORE/AD_OUT_17")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_16_renamed_22 "BIU_CORE/AD_OUT_16")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_15_renamed_23 "BIU_CORE/AD_OUT_15")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_14_renamed_24 "BIU_CORE/AD_OUT_14")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_13_renamed_25 "BIU_CORE/AD_OUT_13")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_12_renamed_26 "BIU_CORE/AD_OUT_12")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_11_renamed_27 "BIU_CORE/AD_OUT_11")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_10_renamed_28 "BIU_CORE/AD_OUT_10")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_9_renamed_29 "BIU_CORE/AD_OUT_9")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_8_renamed_30 "BIU_CORE/AD_OUT_8")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_7_renamed_31 "BIU_CORE/AD_OUT_7")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_6_renamed_32 "BIU_CORE/AD_OUT_6")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_5_renamed_33 "BIU_CORE/AD_OUT_5")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_4_renamed_34 "BIU_CORE/AD_OUT_4")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_3_renamed_35 "BIU_CORE/AD_OUT_3")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_2_renamed_36 "BIU_CORE/AD_OUT_2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_1_renamed_37 "BIU_CORE/AD_OUT_1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OUT_0_renamed_38 "BIU_CORE/AD_OUT_0")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_19_renamed_39 "BIU_CORE/addr_out_temp_19")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_18_renamed_40 "BIU_CORE/addr_out_temp_18")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_17_renamed_41 "BIU_CORE/addr_out_temp_17")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_16_renamed_42 "BIU_CORE/addr_out_temp_16")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_15_renamed_43 "BIU_CORE/addr_out_temp_15")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_14_renamed_44 "BIU_CORE/addr_out_temp_14")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_13_renamed_45 "BIU_CORE/addr_out_temp_13")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_12_renamed_46 "BIU_CORE/addr_out_temp_12")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_11_renamed_47 "BIU_CORE/addr_out_temp_11")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_10_renamed_48 "BIU_CORE/addr_out_temp_10")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_9_renamed_49 "BIU_CORE/addr_out_temp_9")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_8_renamed_50 "BIU_CORE/addr_out_temp_8")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_7_renamed_51 "BIU_CORE/addr_out_temp_7")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_6_renamed_52 "BIU_CORE/addr_out_temp_6")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_5_renamed_53 "BIU_CORE/addr_out_temp_5")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_4_renamed_54 "BIU_CORE/addr_out_temp_4")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_3_renamed_55 "BIU_CORE/addr_out_temp_3")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_2_renamed_56 "BIU_CORE/addr_out_temp_2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_1_renamed_57 "BIU_CORE/addr_out_temp_1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_addr_out_temp_0_renamed_58 "BIU_CORE/addr_out_temp_0")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7 "BIU_CORE/biu_state_7")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_6 "BIU_CORE/biu_state_6")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_5 "BIU_CORE/biu_state_5")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_4 "BIU_CORE/biu_state_4")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_3 "BIU_CORE/biu_state_3")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_2 "BIU_CORE/biu_state_2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_1 "BIU_CORE/biu_state_1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_0 "BIU_CORE/biu_state_0")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_den_int_renamed_59 "BIU_CORE/den_int")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_wr_n_int_renamed_60 "BIU_CORE/wr_n_int")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_rd_n_int_renamed_61 "BIU_CORE/rd_n_int")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_inta_n_int_renamed_62 "BIU_CORE/inta_n_int")
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clk_d1_renamed_63 "BIU_CORE/clk_d1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_dtr_int_renamed_64 "BIU_CORE/dtr_int")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_AD_OE_renamed_65 "BIU_CORE/AD_OE")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_intr_d1_renamed_66 "BIU_CORE/intr_d1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_byte_num_renamed_67 "BIU_CORE/byte_num")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_biu_req_d1_renamed_68 "BIU_CORE/eu_biu_req_d1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ready_d1_renamed_69 "BIU_CORE/ready_d1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_write_renamed_70 "BIU_CORE/pfq_write")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_done_int_renamed_71 "BIU_CORE/biu_done_int")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_nmi_d1_renamed_72 "BIU_CORE/nmi_d1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_15 "BIU_CORE/biu_register_cs_15")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_14 "BIU_CORE/biu_register_cs_14")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_13 "BIU_CORE/biu_register_cs_13")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_12 "BIU_CORE/biu_register_cs_12")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_11 "BIU_CORE/biu_register_cs_11")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_10 "BIU_CORE/biu_register_cs_10")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_9 "BIU_CORE/biu_register_cs_9")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_8 "BIU_CORE/biu_register_cs_8")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_7 "BIU_CORE/biu_register_cs_7")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_6 "BIU_CORE/biu_register_cs_6")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_5 "BIU_CORE/biu_register_cs_5")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_4 "BIU_CORE/biu_register_cs_4")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_3 "BIU_CORE/biu_register_cs_3")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_2 "BIU_CORE/biu_register_cs_2")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_1 "BIU_CORE/biu_register_cs_1")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_0 "BIU_CORE/biu_register_cs_0")
+              (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_15 "BIU_CORE/biu_register_reg_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_14 "BIU_CORE/biu_register_reg_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_13 "BIU_CORE/biu_register_reg_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_12 "BIU_CORE/biu_register_reg_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_11 "BIU_CORE/biu_register_reg_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_10 "BIU_CORE/biu_register_reg_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_9 "BIU_CORE/biu_register_reg_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_8 "BIU_CORE/biu_register_reg_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_7 "BIU_CORE/biu_register_reg_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_6 "BIU_CORE/biu_register_reg_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_5 "BIU_CORE/biu_register_reg_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_4 "BIU_CORE/biu_register_reg_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_3 "BIU_CORE/biu_register_reg_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_2 "BIU_CORE/biu_register_reg_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_1 "BIU_CORE/biu_register_reg_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_0 "BIU_CORE/biu_register_reg_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_15 "BIU_CORE/eu_register_r3_d_15")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_14 "BIU_CORE/eu_register_r3_d_14")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_13 "BIU_CORE/eu_register_r3_d_13")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_12 "BIU_CORE/eu_register_r3_d_12")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_11 "BIU_CORE/eu_register_r3_d_11")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_10 "BIU_CORE/eu_register_r3_d_10")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_9 "BIU_CORE/eu_register_r3_d_9")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_8 "BIU_CORE/eu_register_r3_d_8")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_7 "BIU_CORE/eu_register_r3_d_7")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_6 "BIU_CORE/eu_register_r3_d_6")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_5 "BIU_CORE/eu_register_r3_d_5")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_4 "BIU_CORE/eu_register_r3_d_4")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_3 "BIU_CORE/eu_register_r3_d_3")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_2 "BIU_CORE/eu_register_r3_d_2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_1 "BIU_CORE/eu_register_r3_d_1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_register_r3_d_0 "BIU_CORE/eu_register_r3_d_0")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_15 "BIU_CORE/biu_register_rm_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_14 "BIU_CORE/biu_register_rm_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_13 "BIU_CORE/biu_register_rm_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_12 "BIU_CORE/biu_register_rm_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_11 "BIU_CORE/biu_register_rm_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_10 "BIU_CORE/biu_register_rm_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_9 "BIU_CORE/biu_register_rm_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_8 "BIU_CORE/biu_register_rm_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_7 "BIU_CORE/biu_register_rm_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_6 "BIU_CORE/biu_register_rm_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_5 "BIU_CORE/biu_register_rm_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_4 "BIU_CORE/biu_register_rm_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_3 "BIU_CORE/biu_register_rm_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_2 "BIU_CORE/biu_register_rm_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_1 "BIU_CORE/biu_register_rm_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_0 "BIU_CORE/biu_register_rm_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_15 "BIU_CORE/biu_register_ds_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_14 "BIU_CORE/biu_register_ds_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_13 "BIU_CORE/biu_register_ds_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_12 "BIU_CORE/biu_register_ds_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_11 "BIU_CORE/biu_register_ds_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_10 "BIU_CORE/biu_register_ds_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_9 "BIU_CORE/biu_register_ds_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_8 "BIU_CORE/biu_register_ds_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_7 "BIU_CORE/biu_register_ds_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_6 "BIU_CORE/biu_register_ds_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_5 "BIU_CORE/biu_register_ds_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_4 "BIU_CORE/biu_register_ds_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_3 "BIU_CORE/biu_register_ds_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_2 "BIU_CORE/biu_register_ds_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_1 "BIU_CORE/biu_register_ds_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_0 "BIU_CORE/biu_register_ds_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_15 "BIU_CORE/biu_register_es_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_14 "BIU_CORE/biu_register_es_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_13 "BIU_CORE/biu_register_es_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_12 "BIU_CORE/biu_register_es_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_11 "BIU_CORE/biu_register_es_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_10 "BIU_CORE/biu_register_es_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_9 "BIU_CORE/biu_register_es_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_8 "BIU_CORE/biu_register_es_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_7 "BIU_CORE/biu_register_es_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_6 "BIU_CORE/biu_register_es_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_5 "BIU_CORE/biu_register_es_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_4 "BIU_CORE/biu_register_es_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_3 "BIU_CORE/biu_register_es_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_2 "BIU_CORE/biu_register_es_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_1 "BIU_CORE/biu_register_es_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_0 "BIU_CORE/biu_register_es_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ad_in_int_7 "BIU_CORE/ad_in_int_7")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ad_in_int_6 "BIU_CORE/ad_in_int_6")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ad_in_int_5 "BIU_CORE/ad_in_int_5")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ad_in_int_4 "BIU_CORE/ad_in_int_4")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ad_in_int_3 "BIU_CORE/ad_in_int_3")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ad_in_int_2 "BIU_CORE/ad_in_int_2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ad_in_int_1 "BIU_CORE/ad_in_int_1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ad_in_int_0 "BIU_CORE/ad_in_int_0")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_15 "BIU_CORE/biu_register_ss_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_14 "BIU_CORE/biu_register_ss_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_13 "BIU_CORE/biu_register_ss_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_12 "BIU_CORE/biu_register_ss_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_11 "BIU_CORE/biu_register_ss_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_10 "BIU_CORE/biu_register_ss_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_9 "BIU_CORE/biu_register_ss_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_8 "BIU_CORE/biu_register_ss_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_7 "BIU_CORE/biu_register_ss_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_6 "BIU_CORE/biu_register_ss_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_5 "BIU_CORE/biu_register_ss_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_4 "BIU_CORE/biu_register_ss_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_3 "BIU_CORE/biu_register_ss_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_2 "BIU_CORE/biu_register_ss_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_1 "BIU_CORE/biu_register_ss_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_0 "BIU_CORE/biu_register_ss_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux31_4_renamed_73 "EU_CORE/mux31_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF0F5533") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux31_5_renamed_74 "EU_CORE/mux31_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "33330F0F555500FF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux31_3_f7_renamed_75 "EU_CORE/mux31_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux31_51_renamed_76 "EU_CORE/mux31_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux31_6_renamed_77 "EU_CORE/mux31_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux31_4_f7_renamed_78 "EU_CORE/mux31_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux31_2_f8 "EU_CORE/mux31_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux29_4_renamed_79 "EU_CORE/mux29_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF330F55") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux29_5_renamed_80 "EU_CORE/mux29_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux29_3_f7_renamed_81 "EU_CORE/mux29_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux29_51_renamed_82 "EU_CORE/mux29_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux29_6_renamed_83 "EU_CORE/mux29_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux29_4_f7_renamed_84 "EU_CORE/mux29_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux29_2_f8 "EU_CORE/mux29_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux28_4_renamed_85 "EU_CORE/mux28_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF0F3355") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux28_5_renamed_86 "EU_CORE/mux28_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux28_3_f7_renamed_87 "EU_CORE/mux28_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux28_51_renamed_88 "EU_CORE/mux28_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux28_6_renamed_89 "EU_CORE/mux28_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux28_4_f7_renamed_90 "EU_CORE/mux28_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux28_2_f8 "EU_CORE/mux28_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux30_4_renamed_91 "EU_CORE/mux30_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF0F3355") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux30_5_renamed_92 "EU_CORE/mux30_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "33330F0F555500FF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux30_3_f7_renamed_93 "EU_CORE/mux30_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux30_51_renamed_94 "EU_CORE/mux30_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux30_6_renamed_95 "EU_CORE/mux30_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux30_4_f7_renamed_96 "EU_CORE/mux30_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux30_2_f8 "EU_CORE/mux30_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux27_6_renamed_97 "EU_CORE/mux27_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux27_7_renamed_98 "EU_CORE/mux27_7")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux27_71_renamed_99 "EU_CORE/mux27_71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux27_8_renamed_100 "EU_CORE/mux27_8")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F305") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux26_4_renamed_101 "EU_CORE/mux26_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF0F5533") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux26_5_renamed_102 "EU_CORE/mux26_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux26_3_f7_renamed_103 "EU_CORE/mux26_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux26_51_renamed_104 "EU_CORE/mux26_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux26_6_renamed_105 "EU_CORE/mux26_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux26_4_f7_renamed_106 "EU_CORE/mux26_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux26_2_f8 "EU_CORE/mux26_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux25_4_renamed_107 "EU_CORE/mux25_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF550F33") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux25_5_renamed_108 "EU_CORE/mux25_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux25_3_f7_renamed_109 "EU_CORE/mux25_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux25_51_renamed_110 "EU_CORE/mux25_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux25_6_renamed_111 "EU_CORE/mux25_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux25_4_f7_renamed_112 "EU_CORE/mux25_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux25_2_f8 "EU_CORE/mux25_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux24_4_renamed_113 "EU_CORE/mux24_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF550F33") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux24_5_renamed_114 "EU_CORE/mux24_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux24_3_f7_renamed_115 "EU_CORE/mux24_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux24_51_renamed_116 "EU_CORE/mux24_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux24_6_renamed_117 "EU_CORE/mux24_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux24_4_f7_renamed_118 "EU_CORE/mux24_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux24_2_f8 "EU_CORE/mux24_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux23_5_renamed_119 "EU_CORE/mux23_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux23_3_f7_renamed_120 "EU_CORE/mux23_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux23_51_renamed_121 "EU_CORE/mux23_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux23_6_renamed_122 "EU_CORE/mux23_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux23_4_f7_renamed_123 "EU_CORE/mux23_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux23_2_f8 "EU_CORE/mux23_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux22_6_renamed_124 "EU_CORE/mux22_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux22_7_renamed_125 "EU_CORE/mux22_7")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux22_71_renamed_126 "EU_CORE/mux22_71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux22_8_renamed_127 "EU_CORE/mux22_8")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F5F3") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux21_6_renamed_128 "EU_CORE/mux21_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux21_7_renamed_129 "EU_CORE/mux21_7")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux21_71_renamed_130 "EU_CORE/mux21_71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux21_8_renamed_131 "EU_CORE/mux21_8")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F3F5") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux20_4_renamed_132 "EU_CORE/mux20_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF0F5533") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux20_5_renamed_133 "EU_CORE/mux20_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux20_3_f7_renamed_134 "EU_CORE/mux20_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux20_51_renamed_135 "EU_CORE/mux20_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux20_6_renamed_136 "EU_CORE/mux20_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux20_4_f7_renamed_137 "EU_CORE/mux20_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux20_2_f8 "EU_CORE/mux20_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux19_4_renamed_138 "EU_CORE/mux19_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF330F55") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux19_5_renamed_139 "EU_CORE/mux19_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux19_3_f7_renamed_140 "EU_CORE/mux19_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux19_51_renamed_141 "EU_CORE/mux19_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux19_6_renamed_142 "EU_CORE/mux19_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux19_4_f7_renamed_143 "EU_CORE/mux19_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux19_2_f8 "EU_CORE/mux19_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux18_4_renamed_144 "EU_CORE/mux18_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF33550F") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux18_5_renamed_145 "EU_CORE/mux18_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux18_3_f7_renamed_146 "EU_CORE/mux18_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux18_51_renamed_147 "EU_CORE/mux18_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux18_6_renamed_148 "EU_CORE/mux18_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux18_4_f7_renamed_149 "EU_CORE/mux18_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux18_2_f8 "EU_CORE/mux18_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux17_6_renamed_150 "EU_CORE/mux17_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux17_7_renamed_151 "EU_CORE/mux17_7")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux17_71_renamed_152 "EU_CORE/mux17_71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux17_8_renamed_153 "EU_CORE/mux17_8")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F5F3") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux16_4_renamed_154 "EU_CORE/mux16_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF33550F") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux16_5_renamed_155 "EU_CORE/mux16_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux16_3_f7_renamed_156 "EU_CORE/mux16_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux16_51_renamed_157 "EU_CORE/mux16_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux16_6_renamed_158 "EU_CORE/mux16_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F00FF33335555") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux16_4_f7_renamed_159 "EU_CORE/mux16_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux16_2_f8 "EU_CORE/mux16_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux14_4_renamed_160 "EU_CORE/mux14_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00F0F0AAAACCCC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux14_5_renamed_161 "EU_CORE/mux14_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux14_3_f7_renamed_162 "EU_CORE/mux14_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux14_51_renamed_163 "EU_CORE/mux14_51")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCF0AA00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux14_6_renamed_164 "EU_CORE/mux14_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux14_4_f7_renamed_165 "EU_CORE/mux14_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux14_2_f8 "EU_CORE/mux14_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux13_4_renamed_166 "EU_CORE/mux13_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux13_5_renamed_167 "EU_CORE/mux13_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux13_3_f7_renamed_168 "EU_CORE/mux13_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux13_51_renamed_169 "EU_CORE/mux13_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCF0F0AAAAFF00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux13_6_renamed_170 "EU_CORE/mux13_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux13_4_f7_renamed_171 "EU_CORE/mux13_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux13_2_f8 "EU_CORE/mux13_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux15_4_renamed_172 "EU_CORE/mux15_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00CCCCAAAAF0F0") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux15_5_renamed_173 "EU_CORE/mux15_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux15_3_f7_renamed_174 "EU_CORE/mux15_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux15_51_renamed_175 "EU_CORE/mux15_51")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCF0AA00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux15_6_renamed_176 "EU_CORE/mux15_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux15_4_f7_renamed_177 "EU_CORE/mux15_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux15_2_f8 "EU_CORE/mux15_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux12_4_renamed_178 "EU_CORE/mux12_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00F0F0CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux12_5_renamed_179 "EU_CORE/mux12_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux12_3_f7_renamed_180 "EU_CORE/mux12_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux12_51_renamed_181 "EU_CORE/mux12_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCF0F0AAAAFF00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux12_6_renamed_182 "EU_CORE/mux12_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux12_4_f7_renamed_183 "EU_CORE/mux12_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux12_2_f8 "EU_CORE/mux12_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux11_4_renamed_184 "EU_CORE/mux11_4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0AAFFCC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux11_5_renamed_185 "EU_CORE/mux11_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux11_3_f7_renamed_186 "EU_CORE/mux11_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux11_51_renamed_187 "EU_CORE/mux11_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCF0F0AAAAFF00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux11_6_renamed_188 "EU_CORE/mux11_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux11_4_f7_renamed_189 "EU_CORE/mux11_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux11_2_f8 "EU_CORE/mux11_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux10_4_renamed_190 "EU_CORE/mux10_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00AAAAF0F0CCCC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux10_5_renamed_191 "EU_CORE/mux10_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux10_3_f7_renamed_192 "EU_CORE/mux10_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux10_51_renamed_193 "EU_CORE/mux10_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCF0F0AAAAFF00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux10_6_renamed_194 "EU_CORE/mux10_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux10_4_f7_renamed_195 "EU_CORE/mux10_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux10_2_f8 "EU_CORE/mux10_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux9_4_renamed_196 "EU_CORE/mux9_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00F0F0CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux9_5_renamed_197 "EU_CORE/mux9_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux9_3_f7_renamed_198 "EU_CORE/mux9_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux9_51_renamed_199 "EU_CORE/mux9_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCF0F0AAAAFF00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux9_6_renamed_200 "EU_CORE/mux9_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux9_4_f7_renamed_201 "EU_CORE/mux9_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux9_2_f8 "EU_CORE/mux9_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux8_4_renamed_202 "EU_CORE/mux8_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux8_5_renamed_203 "EU_CORE/mux8_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux8_3_f7_renamed_204 "EU_CORE/mux8_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux8_51_renamed_205 "EU_CORE/mux8_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCF0F0AAAAFF00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux8_6_renamed_206 "EU_CORE/mux8_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux8_4_f7_renamed_207 "EU_CORE/mux8_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux8_2_f8 "EU_CORE/mux8_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux7_4_renamed_208 "EU_CORE/mux7_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00F0F0CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux7_5_renamed_209 "EU_CORE/mux7_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux7_3_f7_renamed_210 "EU_CORE/mux7_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux7_51_renamed_211 "EU_CORE/mux7_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCF0F0AAAAFF00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux7_6_renamed_212 "EU_CORE/mux7_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux7_4_f7_renamed_213 "EU_CORE/mux7_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux7_2_f8 "EU_CORE/mux7_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux6_6_renamed_214 "EU_CORE/mux6_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux6_7_renamed_215 "EU_CORE/mux6_7")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCF0AA00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux6_71_renamed_216 "EU_CORE/mux6_71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux6_8_renamed_217 "EU_CORE/mux6_8")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F000AACC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux5_6_renamed_218 "EU_CORE/mux5_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux5_7_renamed_219 "EU_CORE/mux5_7")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCF0AA00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux5_71_renamed_220 "EU_CORE/mux5_71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux5_8_renamed_221 "EU_CORE/mux5_8")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F000AACC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux4_4_renamed_222 "EU_CORE/mux4_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00CCCCAAAAF0F0") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux4_5_renamed_223 "EU_CORE/mux4_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux4_3_f7_renamed_224 "EU_CORE/mux4_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux4_51_renamed_225 "EU_CORE/mux4_51")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCF0AA00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux4_6_renamed_226 "EU_CORE/mux4_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux4_4_f7_renamed_227 "EU_CORE/mux4_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux4_2_f8 "EU_CORE/mux4_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux3_4_renamed_228 "EU_CORE/mux3_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00AAAACCCC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux3_5_renamed_229 "EU_CORE/mux3_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux3_3_f7_renamed_230 "EU_CORE/mux3_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux3_51_renamed_231 "EU_CORE/mux3_51")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCF0AA00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux3_6_renamed_232 "EU_CORE/mux3_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux3_4_f7_renamed_233 "EU_CORE/mux3_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux3_2_f8 "EU_CORE/mux3_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux2_4_renamed_234 "EU_CORE/mux2_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00CCCCAAAAF0F0") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux2_5_renamed_235 "EU_CORE/mux2_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux2_3_f7_renamed_236 "EU_CORE/mux2_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux2_51_renamed_237 "EU_CORE/mux2_51")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCF0AA00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux2_6_renamed_238 "EU_CORE/mux2_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux2_4_f7_renamed_239 "EU_CORE/mux2_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux2_2_f8 "EU_CORE/mux2_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux1_6_renamed_240 "EU_CORE/mux1_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux1_7_renamed_241 "EU_CORE/mux1_7")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCF0AA00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux1_71_renamed_242 "EU_CORE/mux1_71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux1_8_renamed_243 "EU_CORE/mux1_8")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F000AACC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux_4_renamed_244 "EU_CORE/mux_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF00AAAAF0F0CCCC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux_5_renamed_245 "EU_CORE/mux_5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux_3_f7_renamed_246 "EU_CORE/mux_3_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux_51_renamed_247 "EU_CORE/mux_51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCCCF0F0AAAAFF00") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux_6_renamed_248 "EU_CORE/mux_6")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0F0FF00CCCCAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux_4_f7_renamed_249 "EU_CORE/mux_4_f7")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux_2_f8 "EU_CORE/mux_2_f8")
+              (viewRef view_1 (cellRef MUXF8 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_12__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_11__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_11__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_10__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_10__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_9__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_9__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_8__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_8__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_7__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_7__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_6__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_6__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_5__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_5__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_4__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_4__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_3__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_3__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_2__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_2__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_1__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_1__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_0__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_0__ "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_15 "EU_CORE/eu_register_r0_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_14 "EU_CORE/eu_register_r0_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_13 "EU_CORE/eu_register_r0_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_12 "EU_CORE/eu_register_r0_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_11 "EU_CORE/eu_register_r0_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_10 "EU_CORE/eu_register_r0_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_9 "EU_CORE/eu_register_r0_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_8 "EU_CORE/eu_register_r0_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_7 "EU_CORE/eu_register_r0_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_6 "EU_CORE/eu_register_r0_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_5 "EU_CORE/eu_register_r0_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_4 "EU_CORE/eu_register_r0_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_3 "EU_CORE/eu_register_r0_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_2 "EU_CORE/eu_register_r0_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_1 "EU_CORE/eu_register_r0_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r0_0 "EU_CORE/eu_register_r0_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_15 "EU_CORE/eu_alu_last_result_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_14 "EU_CORE/eu_alu_last_result_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_13 "EU_CORE/eu_alu_last_result_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_12 "EU_CORE/eu_alu_last_result_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_11 "EU_CORE/eu_alu_last_result_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_10 "EU_CORE/eu_alu_last_result_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_9 "EU_CORE/eu_alu_last_result_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_8 "EU_CORE/eu_alu_last_result_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_7 "EU_CORE/eu_alu_last_result_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_6 "EU_CORE/eu_alu_last_result_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_5 "EU_CORE/eu_alu_last_result_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_4 "EU_CORE/eu_alu_last_result_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_3 "EU_CORE/eu_alu_last_result_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_2 "EU_CORE/eu_alu_last_result_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_1 "EU_CORE/eu_alu_last_result_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_alu_last_result_0 "EU_CORE/eu_alu_last_result_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_12 "EU_CORE/eu_rom_address_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_11 "EU_CORE/eu_rom_address_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_10 "EU_CORE/eu_rom_address_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_9 "EU_CORE/eu_rom_address_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_8 "EU_CORE/eu_rom_address_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_7 "EU_CORE/eu_rom_address_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_6 "EU_CORE/eu_rom_address_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_5 "EU_CORE/eu_rom_address_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_4 "EU_CORE/eu_rom_address_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_3 "EU_CORE/eu_rom_address_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_2 "EU_CORE/eu_rom_address_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_1 "EU_CORE/eu_rom_address_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_address_0 "EU_CORE/eu_rom_address_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_51 "EU_CORE/eu_calling_address_51")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_50 "EU_CORE/eu_calling_address_50")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_49 "EU_CORE/eu_calling_address_49")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_48 "EU_CORE/eu_calling_address_48")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_47 "EU_CORE/eu_calling_address_47")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_46 "EU_CORE/eu_calling_address_46")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_45 "EU_CORE/eu_calling_address_45")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_44 "EU_CORE/eu_calling_address_44")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_43 "EU_CORE/eu_calling_address_43")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_42 "EU_CORE/eu_calling_address_42")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_41 "EU_CORE/eu_calling_address_41")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_40 "EU_CORE/eu_calling_address_40")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_39 "EU_CORE/eu_calling_address_39")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_38 "EU_CORE/eu_calling_address_38")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_37 "EU_CORE/eu_calling_address_37")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_36 "EU_CORE/eu_calling_address_36")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_35 "EU_CORE/eu_calling_address_35")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_34 "EU_CORE/eu_calling_address_34")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_33 "EU_CORE/eu_calling_address_33")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_32 "EU_CORE/eu_calling_address_32")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_31 "EU_CORE/eu_calling_address_31")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_30 "EU_CORE/eu_calling_address_30")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_29 "EU_CORE/eu_calling_address_29")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_28 "EU_CORE/eu_calling_address_28")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_27 "EU_CORE/eu_calling_address_27")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_26 "EU_CORE/eu_calling_address_26")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_25 "EU_CORE/eu_calling_address_25")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_24 "EU_CORE/eu_calling_address_24")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_23 "EU_CORE/eu_calling_address_23")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_22 "EU_CORE/eu_calling_address_22")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_21 "EU_CORE/eu_calling_address_21")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_20 "EU_CORE/eu_calling_address_20")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_19 "EU_CORE/eu_calling_address_19")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_18 "EU_CORE/eu_calling_address_18")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_17 "EU_CORE/eu_calling_address_17")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_16 "EU_CORE/eu_calling_address_16")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_15 "EU_CORE/eu_calling_address_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_14 "EU_CORE/eu_calling_address_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_13 "EU_CORE/eu_calling_address_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_12 "EU_CORE/eu_calling_address_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_11 "EU_CORE/eu_calling_address_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_10 "EU_CORE/eu_calling_address_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_9 "EU_CORE/eu_calling_address_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_8 "EU_CORE/eu_calling_address_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_7 "EU_CORE/eu_calling_address_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_6 "EU_CORE/eu_calling_address_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_5 "EU_CORE/eu_calling_address_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_4 "EU_CORE/eu_calling_address_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_3 "EU_CORE/eu_calling_address_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_2 "EU_CORE/eu_calling_address_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_1 "EU_CORE/eu_calling_address_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_calling_address_0 "EU_CORE/eu_calling_address_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_add_overflow8_renamed_250 "EU_CORE/eu_add_overflow8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_add_overflow16_renamed_251 "EU_CORE/eu_add_overflow16")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flag_t_d_renamed_252 "EU_CORE/eu_flag_t_d")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_biu_done_d2_renamed_253 "EU_CORE/biu_done_d2")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_15 "EU_CORE/eu_biu_dataout_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_14 "EU_CORE/eu_biu_dataout_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_13 "EU_CORE/eu_biu_dataout_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_12 "EU_CORE/eu_biu_dataout_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_11 "EU_CORE/eu_biu_dataout_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_10 "EU_CORE/eu_biu_dataout_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_9 "EU_CORE/eu_biu_dataout_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_8 "EU_CORE/eu_biu_dataout_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_7 "EU_CORE/eu_biu_dataout_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_6 "EU_CORE/eu_biu_dataout_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_5 "EU_CORE/eu_biu_dataout_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_4 "EU_CORE/eu_biu_dataout_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_3 "EU_CORE/eu_biu_dataout_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_2 "EU_CORE/eu_biu_dataout_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_1 "EU_CORE/eu_biu_dataout_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_dataout_0 "EU_CORE/eu_biu_dataout_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_15 "EU_CORE/eu_biu_command_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_14 "EU_CORE/eu_biu_command_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_13 "EU_CORE/eu_biu_command_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_12 "EU_CORE/eu_biu_command_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_11 "EU_CORE/eu_biu_command_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_10 "EU_CORE/eu_biu_command_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_9 "EU_CORE/eu_biu_command_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_8 "EU_CORE/eu_biu_command_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_7 "EU_CORE/eu_biu_command_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_6 "EU_CORE/eu_biu_command_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_5 "EU_CORE/eu_biu_command_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_4 "EU_CORE/eu_biu_command_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_3 "EU_CORE/eu_biu_command_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_2 "EU_CORE/eu_biu_command_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_1 "EU_CORE/eu_biu_command_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_biu_command_0 "EU_CORE/eu_biu_command_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_15 "EU_CORE/eu_register_r2_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_14 "EU_CORE/eu_register_r2_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_13 "EU_CORE/eu_register_r2_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_12 "EU_CORE/eu_register_r2_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_11 "EU_CORE/eu_register_r2_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_10 "EU_CORE/eu_register_r2_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_9 "EU_CORE/eu_register_r2_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_8 "EU_CORE/eu_register_r2_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_7 "EU_CORE/eu_register_r2_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_6 "EU_CORE/eu_register_r2_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_5 "EU_CORE/eu_register_r2_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_4 "EU_CORE/eu_register_r2_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_3 "EU_CORE/eu_register_r2_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_2 "EU_CORE/eu_register_r2_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_1 "EU_CORE/eu_register_r2_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r2_0 "EU_CORE/eu_register_r2_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_15 "EU_CORE/eu_register_r1_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_14 "EU_CORE/eu_register_r1_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_13 "EU_CORE/eu_register_r1_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_12 "EU_CORE/eu_register_r1_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_11 "EU_CORE/eu_register_r1_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_10 "EU_CORE/eu_register_r1_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_9 "EU_CORE/eu_register_r1_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_8 "EU_CORE/eu_register_r1_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_7 "EU_CORE/eu_register_r1_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_6 "EU_CORE/eu_register_r1_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_5 "EU_CORE/eu_register_r1_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_4 "EU_CORE/eu_register_r1_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_3 "EU_CORE/eu_register_r1_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_2 "EU_CORE/eu_register_r1_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_1 "EU_CORE/eu_register_r1_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r1_0 "EU_CORE/eu_register_r1_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_15 "EU_CORE/eu_register_r3_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_14 "EU_CORE/eu_register_r3_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_13 "EU_CORE/eu_register_r3_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_12 "EU_CORE/eu_register_r3_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_11 "EU_CORE/eu_register_r3_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_10 "EU_CORE/eu_register_r3_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_9 "EU_CORE/eu_register_r3_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_8 "EU_CORE/eu_register_r3_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_7 "EU_CORE/eu_register_r3_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_6 "EU_CORE/eu_register_r3_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_5 "EU_CORE/eu_register_r3_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_4 "EU_CORE/eu_register_r3_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_3 "EU_CORE/eu_register_r3_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_2 "EU_CORE/eu_register_r3_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_1 "EU_CORE/eu_register_r3_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_r3_0 "EU_CORE/eu_register_r3_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_15 "EU_CORE/eu_flags_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_14 "EU_CORE/eu_flags_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_13 "EU_CORE/eu_flags_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_12 "EU_CORE/eu_flags_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_11 "EU_CORE/eu_flags_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_10 "EU_CORE/eu_flags_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_9 "EU_CORE/eu_flags_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_8 "EU_CORE/eu_flags_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_7 "EU_CORE/eu_flags_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_6 "EU_CORE/eu_flags_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_5 "EU_CORE/eu_flags_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_4 "EU_CORE/eu_flags_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_3 "EU_CORE/eu_flags_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_2 "EU_CORE/eu_flags_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_1 "EU_CORE/eu_flags_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_flags_0 "EU_CORE/eu_flags_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_15 "EU_CORE/eu_register_di_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_14 "EU_CORE/eu_register_di_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_13 "EU_CORE/eu_register_di_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_12 "EU_CORE/eu_register_di_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_11 "EU_CORE/eu_register_di_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_10 "EU_CORE/eu_register_di_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_9 "EU_CORE/eu_register_di_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_8 "EU_CORE/eu_register_di_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_7 "EU_CORE/eu_register_di_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_6 "EU_CORE/eu_register_di_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_5 "EU_CORE/eu_register_di_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_4 "EU_CORE/eu_register_di_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_3 "EU_CORE/eu_register_di_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_2 "EU_CORE/eu_register_di_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_1 "EU_CORE/eu_register_di_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_di_0 "EU_CORE/eu_register_di_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_15 "EU_CORE/eu_register_bp_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_14 "EU_CORE/eu_register_bp_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_13 "EU_CORE/eu_register_bp_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_12 "EU_CORE/eu_register_bp_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_11 "EU_CORE/eu_register_bp_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_10 "EU_CORE/eu_register_bp_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_9 "EU_CORE/eu_register_bp_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_8 "EU_CORE/eu_register_bp_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_7 "EU_CORE/eu_register_bp_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_6 "EU_CORE/eu_register_bp_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_5 "EU_CORE/eu_register_bp_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_4 "EU_CORE/eu_register_bp_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_3 "EU_CORE/eu_register_bp_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_2 "EU_CORE/eu_register_bp_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_1 "EU_CORE/eu_register_bp_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bp_0 "EU_CORE/eu_register_bp_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_15 "EU_CORE/eu_register_sp_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_14 "EU_CORE/eu_register_sp_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_13 "EU_CORE/eu_register_sp_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_12 "EU_CORE/eu_register_sp_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_11 "EU_CORE/eu_register_sp_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_10 "EU_CORE/eu_register_sp_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_9 "EU_CORE/eu_register_sp_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_8 "EU_CORE/eu_register_sp_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_7 "EU_CORE/eu_register_sp_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_6 "EU_CORE/eu_register_sp_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_5 "EU_CORE/eu_register_sp_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_4 "EU_CORE/eu_register_sp_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_3 "EU_CORE/eu_register_sp_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_2 "EU_CORE/eu_register_sp_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_1 "EU_CORE/eu_register_sp_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_sp_0 "EU_CORE/eu_register_sp_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_15 "EU_CORE/eu_register_si_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_14 "EU_CORE/eu_register_si_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_13 "EU_CORE/eu_register_si_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_12 "EU_CORE/eu_register_si_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_11 "EU_CORE/eu_register_si_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_10 "EU_CORE/eu_register_si_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_9 "EU_CORE/eu_register_si_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_8 "EU_CORE/eu_register_si_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_7 "EU_CORE/eu_register_si_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_6 "EU_CORE/eu_register_si_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_5 "EU_CORE/eu_register_si_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_4 "EU_CORE/eu_register_si_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_3 "EU_CORE/eu_register_si_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_2 "EU_CORE/eu_register_si_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_1 "EU_CORE/eu_register_si_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_si_0 "EU_CORE/eu_register_si_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_15 "EU_CORE/eu_register_dx_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_14 "EU_CORE/eu_register_dx_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_13 "EU_CORE/eu_register_dx_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_12 "EU_CORE/eu_register_dx_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_11 "EU_CORE/eu_register_dx_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_10 "EU_CORE/eu_register_dx_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_9 "EU_CORE/eu_register_dx_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_8 "EU_CORE/eu_register_dx_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_7 "EU_CORE/eu_register_dx_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_6 "EU_CORE/eu_register_dx_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_5 "EU_CORE/eu_register_dx_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_4 "EU_CORE/eu_register_dx_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_3 "EU_CORE/eu_register_dx_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_2 "EU_CORE/eu_register_dx_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_1 "EU_CORE/eu_register_dx_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_dx_0 "EU_CORE/eu_register_dx_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_15 "EU_CORE/eu_register_cx_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_14 "EU_CORE/eu_register_cx_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_13 "EU_CORE/eu_register_cx_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_12 "EU_CORE/eu_register_cx_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_11 "EU_CORE/eu_register_cx_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_10 "EU_CORE/eu_register_cx_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_9 "EU_CORE/eu_register_cx_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_8 "EU_CORE/eu_register_cx_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_7 "EU_CORE/eu_register_cx_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_6 "EU_CORE/eu_register_cx_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_5 "EU_CORE/eu_register_cx_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_4 "EU_CORE/eu_register_cx_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_3 "EU_CORE/eu_register_cx_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_2 "EU_CORE/eu_register_cx_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_1 "EU_CORE/eu_register_cx_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_cx_0 "EU_CORE/eu_register_cx_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_15 "EU_CORE/eu_register_bx_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_14 "EU_CORE/eu_register_bx_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_13 "EU_CORE/eu_register_bx_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_12 "EU_CORE/eu_register_bx_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_11 "EU_CORE/eu_register_bx_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_10 "EU_CORE/eu_register_bx_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_9 "EU_CORE/eu_register_bx_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_8 "EU_CORE/eu_register_bx_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_7 "EU_CORE/eu_register_bx_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_6 "EU_CORE/eu_register_bx_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_5 "EU_CORE/eu_register_bx_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_4 "EU_CORE/eu_register_bx_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_3 "EU_CORE/eu_register_bx_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_2 "EU_CORE/eu_register_bx_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_1 "EU_CORE/eu_register_bx_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_bx_0 "EU_CORE/eu_register_bx_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_15 "EU_CORE/eu_register_ax_15")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_14 "EU_CORE/eu_register_ax_14")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_13 "EU_CORE/eu_register_ax_13")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_12 "EU_CORE/eu_register_ax_12")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_11 "EU_CORE/eu_register_ax_11")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_10 "EU_CORE/eu_register_ax_10")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_9 "EU_CORE/eu_register_ax_9")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_8 "EU_CORE/eu_register_ax_8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_7 "EU_CORE/eu_register_ax_7")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_6 "EU_CORE/eu_register_ax_6")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_5 "EU_CORE/eu_register_ax_5")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_4 "EU_CORE/eu_register_ax_4")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_3 "EU_CORE/eu_register_ax_3")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_2 "EU_CORE/eu_register_ax_2")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_1 "EU_CORE/eu_register_ax_1")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_register_ax_0 "EU_CORE/eu_register_ax_0")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_add_aux_carry_renamed_254 "EU_CORE/eu_add_aux_carry")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_add_carry8_renamed_255 "EU_CORE/eu_add_carry8")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_add_carry_renamed_256 "EU_CORE/eu_add_carry")
+              (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_stall_pipeline_renamed_257 "EU_CORE/eu_stall_pipeline")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_biu_done_d1_renamed_258 "EU_CORE/biu_done_d1")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename prescaler_d_prescaler_21__AND_2_o1 "prescaler_d_prescaler[21]_AND_2_o1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___42___prescaler_d_prescaler[21]_AND_2_o1") (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename Mmux_led_int_6__led_int_0__mux_29_OUT81 "Mmux_led_int[6]_led_int[0]_mux_29_OUT81")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___47___Mmux_led_int[6]_led_int[0]_mux_29_OUT81") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename Mmux_led_int_6__led_int_0__mux_29_OUT71 "Mmux_led_int[6]_led_int[0]_mux_29_OUT71")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___46___Mmux_led_int[6]_led_int[0]_mux_29_OUT71") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename Mmux_led_int_6__led_int_0__mux_29_OUT61 "Mmux_led_int[6]_led_int[0]_mux_29_OUT61")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___47___Mmux_led_int[6]_led_int[0]_mux_29_OUT81") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename Mmux_led_int_6__led_int_0__mux_29_OUT51 "Mmux_led_int[6]_led_int[0]_mux_29_OUT51")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___46___Mmux_led_int[6]_led_int[0]_mux_29_OUT71") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename Mmux_led_int_6__led_int_0__mux_29_OUT41 "Mmux_led_int[6]_led_int[0]_mux_29_OUT41")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___45___Mmux_led_int[6]_led_int[0]_mux_29_OUT41") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename Mmux_led_int_6__led_int_0__mux_29_OUT31 "Mmux_led_int[6]_led_int[0]_mux_29_OUT31")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___44___Mmux_led_int[6]_led_int[0]_mux_29_OUT31") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename Mmux_led_int_6__led_int_0__mux_29_OUT21 "Mmux_led_int[6]_led_int[0]_mux_29_OUT21")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___45___Mmux_led_int[6]_led_int[0]_mux_29_OUT41") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename Mmux_led_int_6__led_int_0__mux_29_OUT11 "Mmux_led_int[6]_led_int[0]_mux_29_OUT11")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___44___Mmux_led_int[6]_led_int[0]_mux_29_OUT31") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename &_n01121 "_n01121")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___42___prescaler_d_prescaler[21]_AND_2_o1") (owner "Xilinx"))
+              (property INIT (string "8808") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n0996_inv1 "BIU_CORE/_n0996_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___7___BIU_CORE/_n0996_inv1") (owner "Xilinx"))
+              (property INIT (string "01000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n1012_inv1 "BIU_CORE/_n1012_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___7___BIU_CORE/_n0996_inv1") (owner "Xilinx"))
+              (property INIT (string "08000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n1008_inv1 "BIU_CORE/_n1008_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___6___BIU_CORE/_n1008_inv1") (owner "Xilinx"))
+              (property INIT (string "04000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n1071_inv1 "BIU_CORE/_n1071_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___6___BIU_CORE/_n1008_inv1") (owner "Xilinx"))
+              (property INIT (string "04000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n1004_inv1 "BIU_CORE/_n1004_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___5___BIU_CORE/_n1004_inv1") (owner "Xilinx"))
+              (property INIT (string "08000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n1000_inv1 "BIU_CORE/_n1000_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___5___BIU_CORE/_n1004_inv1") (owner "Xilinx"))
+              (property INIT (string "04000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_15_o1 "BIU_CORE/eu_biu_req_caught_eu_biu_req_code[4]_AND_15_o1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000008000000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_state_7__GND_14_o_add_93_OUT_cy_5_11 "BIU_CORE/Madd_biu_state[7]_GND_14_o_add_93_OUT_cy<5>11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8000000000000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_2_1 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<2>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___43___BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<2>1") (owner "Xilinx"))
+              (property INIT (string "EC6CCC00") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n114121 "BIU_CORE/_n114121")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF7000FFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_biu_req_code_4__PWR_6_o_equal_108_o_4_1 "BIU_CORE/eu_biu_req_code[4]_PWR_6_o_equal_108_o<4>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___0___BIU_CORE/eu_biu_req_code[4]_PWR_6_o_equal_108_o<4>1") (owner "Xilinx"))
+              (property INIT (string "01000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_equal_169_o_7_1 "BIU_CORE/biu_state[7]_GND_14_o_equal_169_o<7>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___11___BIU_CORE/biu_state[7]_GND_14_o_equal_169_o<7>1") (owner "Xilinx"))
+              (property INIT (string "01000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n10811 "BIU_CORE/_n10811")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___4___BIU_CORE/_n10811") (owner "Xilinx"))
+              (property INIT (string "02400140") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_22 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<0>22")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFFFF80") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_biu_req_code_4__INV_33_o1 "BIU_CORE/eu_biu_req_code[4]_INV_33_o1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___3___BIU_CORE/eu_biu_req_code[4]_INV_33_o1") (owner "Xilinx"))
+              (property INIT (string "022022AA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_out1 "BIU_CORE/out1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___1___BIU_CORE/out1") (owner "Xilinx"))
+              (property INIT (string "17445F44") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0_11 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<0>11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFF44445444") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_out21 "BIU_CORE/out21")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF33FF10") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_10_11 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<10>11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFF0040") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_31 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<10>31")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFDC") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OE_Select_192_o1 "BIU_CORE/biu_state[7]_AD_OE_Select_192_o1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFA2EEA2FFA2A2A2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux171 "BIU_CORE/mux171")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux161 "BIU_CORE/mux161")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux1091 "BIU_CORE/mux1091")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux1081 "BIU_CORE/mux1081")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux1071 "BIU_CORE/mux1071")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux1061 "BIU_CORE/mux1061")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux1051 "BIU_CORE/mux1051")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux1041 "BIU_CORE/mux1041")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux1031 "BIU_CORE/mux1031")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux1021 "BIU_CORE/mux1021")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux10151 "BIU_CORE/mux10151")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux10141 "BIU_CORE/mux10141")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux10131 "BIU_CORE/mux10131")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux10121 "BIU_CORE/mux10121")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux10111 "BIU_CORE/mux10111")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_mux1011 "BIU_CORE/mux1011")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_pfq_top_byte_int81 "BIU_CORE/Mmux_pfq_top_byte_int81")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_pfq_top_byte_int71 "BIU_CORE/Mmux_pfq_top_byte_int71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_pfq_top_byte_int61 "BIU_CORE/Mmux_pfq_top_byte_int61")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_pfq_top_byte_int51 "BIU_CORE/Mmux_pfq_top_byte_int51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_pfq_top_byte_int41 "BIU_CORE/Mmux_pfq_top_byte_int41")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_pfq_top_byte_int31 "BIU_CORE/Mmux_pfq_top_byte_int31")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_pfq_top_byte_int21 "BIU_CORE/Mmux_pfq_top_byte_int21")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_pfq_top_byte_int11 "BIU_CORE/Mmux_pfq_top_byte_int11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n10841 "BIU_CORE/_n10841")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___4___BIU_CORE/_n10811") (owner "Xilinx"))
+              (property INIT (string "15400404") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n11741 "BIU_CORE/_n11741")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFF8A") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_Select_178_o1 "BIU_CORE/biu_state[7]_GND_14_o_Select_178_o1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF8A8A8A8A8A8A8A") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n10921 "BIU_CORE/_n10921")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___0___BIU_CORE/eu_biu_req_code[4]_PWR_6_o_equal_108_o<4>1") (owner "Xilinx"))
+              (property INIT (string "00101000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_7_1 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<7>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___9___BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<7>1") (owner "Xilinx"))
+              (property INIT (string "EA6AAA00") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_6_1 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<6>1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___9___BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<7>1") (owner "Xilinx"))
+              (property INIT (string "E6A0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_equal_176_o_7_21 "BIU_CORE/biu_state[7]_GND_14_o_equal_176_o<7>21")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "01") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_equal_176_o_7_11 "BIU_CORE/biu_state[7]_GND_14_o_equal_176_o<7>11")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "20") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_1_renamed_259 "BIU_CORE/biu_state[7]_GND_14_o_equal_166_o<7>1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___23___BIU_CORE/biu_state[7]_GND_14_o_equal_166_o<7>1") (owner "Xilinx"))
+              (property INIT (string "02") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_equal_172_o_7_1 "BIU_CORE/biu_state[7]_GND_14_o_equal_172_o<7>1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___23___BIU_CORE/biu_state[7]_GND_14_o_equal_166_o<7>1") (owner "Xilinx"))
+              (property INIT (string "20") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_equal_167_o_7_1 "BIU_CORE/biu_state[7]_GND_14_o_equal_167_o<7>1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___20___BIU_CORE/biu_state[7]_GND_14_o_equal_167_o<7>1") (owner "Xilinx"))
+              (property INIT (string "20") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_8_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<8>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EAAAC000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_9_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<9>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EAAAC000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_10_1_renamed_260 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<10>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EAAAC000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_11_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<11>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EAAAC000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_12_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<12>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EAAAC000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_13_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<13>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EAAAC000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_14_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<14>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EAAAC000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_15_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<15>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EAAAC000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_16_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<16>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "ECCCA000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_17_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<17>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "ECCCA000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_18_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<18>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "ECCCA000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_19_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<19>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "ECCCA000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT17 "BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT17")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___54___BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT17") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT81 "BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT81")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___54___BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT17") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT91 "BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT91")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___53___BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT91") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT101 "BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT101")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___53___BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT91") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT111 "BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT111")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___52___BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT111") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT121 "BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT121")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___52___BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT111") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT131 "BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT131")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___51___BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT131") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT141 "BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT141")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___51___BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT131") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_biu_segment11 "BIU_CORE/Mmux_biu_segment11")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___50___BIU_CORE/Mmux_biu_segment11") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_biu_segment21 "BIU_CORE/Mmux_biu_segment21")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___50___BIU_CORE/Mmux_biu_segment11") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n1036_inv1 "BIU_CORE/_n1036_inv1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___57___BIU_CORE/_n1036_inv1") (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n1017_inv1 "BIU_CORE/_n1017_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___57___BIU_CORE/_n1036_inv1") (owner "Xilinx"))
+              (property INIT (string "FF10") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n1033_inv1 "BIU_CORE/_n1033_inv1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___40___BIU_CORE/_n1033_inv1") (owner "Xilinx"))
+              (property INIT (string "80") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n1029_inv1 "BIU_CORE/_n1029_inv1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___40___BIU_CORE/_n1033_inv1") (owner "Xilinx"))
+              (property INIT (string "20") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n1021_inv1 "BIU_CORE/_n1021_inv1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___39___BIU_CORE/_n1021_inv1") (owner "Xilinx"))
+              (property INIT (string "02") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n1025_inv1 "BIU_CORE/_n1025_inv1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___39___BIU_CORE/_n1021_inv1") (owner "Xilinx"))
+              (property INIT (string "20") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n07981 "BIU_CORE/_n07981")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___41___BIU_CORE/_n07981") (owner "Xilinx"))
+              (property INIT (string "02") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_biu_strobe_1__PWR_6_o_equal_67_o_1_1 "BIU_CORE/eu_biu_strobe[1]_PWR_6_o_equal_67_o<1>1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "4") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clk_falling_edge1 "BIU_CORE/clk_falling_edge1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___22___BIU_CORE/clk_falling_edge1") (owner "Xilinx"))
+              (property INIT (string "20") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_clk_rising_edge1 "BIU_CORE/clk_rising_edge1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___22___BIU_CORE/clk_falling_edge1") (owner "Xilinx"))
+              (property INIT (string "02") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1100_inv21 "EU_CORE/_n1100_inv21")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___12___EU_CORE/_n1100_inv21") (owner "Xilinx"))
+              (property INIT (string "1110") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1104_inv11 "EU_CORE/_n1104_inv11")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___12___EU_CORE/_n1100_inv21") (owner "Xilinx"))
+              (property INIT (string "2220") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_stall_pipeline_eu_opcode_type_2__AND_134_o1 "EU_CORE/eu_stall_pipeline_eu_opcode_type[2]_AND_134_o1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___21___EU_CORE/eu_stall_pipeline_eu_opcode_type[2]_AND_134_o1") (owner "Xilinx"))
+              (property INIT (string "54") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1148_inv1 "EU_CORE/_n1148_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___16___EU_CORE/_n1148_inv1") (owner "Xilinx"))
+              (property INIT (string "0800") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1152_inv1 "EU_CORE/_n1152_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___13___EU_CORE/_n1152_inv1") (owner "Xilinx"))
+              (property INIT (string "0800") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1140_inv1 "EU_CORE/_n1140_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___16___EU_CORE/_n1148_inv1") (owner "Xilinx"))
+              (property INIT (string "0800") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1144_inv1 "EU_CORE/_n1144_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___19___EU_CORE/_n1144_inv1") (owner "Xilinx"))
+              (property INIT (string "0800") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1132_inv1 "EU_CORE/_n1132_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0400") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1136_inv1 "EU_CORE/_n1136_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___19___EU_CORE/_n1144_inv1") (owner "Xilinx"))
+              (property INIT (string "0400") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1124_inv1 "EU_CORE/_n1124_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___18___EU_CORE/_n1124_inv1") (owner "Xilinx"))
+              (property INIT (string "0800") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1128_inv1 "EU_CORE/_n1128_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___15___EU_CORE/_n1128_inv1") (owner "Xilinx"))
+              (property INIT (string "0800") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1116_inv1 "EU_CORE/_n1116_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___18___EU_CORE/_n1124_inv1") (owner "Xilinx"))
+              (property INIT (string "0400") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1120_inv1 "EU_CORE/_n1120_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___15___EU_CORE/_n1128_inv1") (owner "Xilinx"))
+              (property INIT (string "0400") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1108_inv1 "EU_CORE/_n1108_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___14___EU_CORE/_n1108_inv1") (owner "Xilinx"))
+              (property INIT (string "0400") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1112_inv1 "EU_CORE/_n1112_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___17___EU_CORE/_n1112_inv1") (owner "Xilinx"))
+              (property INIT (string "0400") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1100_inv1 "EU_CORE/_n1100_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___14___EU_CORE/_n1108_inv1") (owner "Xilinx"))
+              (property INIT (string "0002") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1104_inv1_renamed_261 "EU_CORE/_n1104_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___17___EU_CORE/_n1112_inv1") (owner "Xilinx"))
+              (property INIT (string "0002") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1391 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1391")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___25___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1391") (owner "Xilinx"))
+              (property INIT (string "BF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1371 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1371")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1381 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1381")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1361 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1361")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1351 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1351")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1341 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1341")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1321 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1321")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1331 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1331")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1311 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1311")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1301 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1301")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1291 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1291")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1271 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1271")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1281 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1281")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1261 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1261")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1251 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1251")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1241 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1241")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1221 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1221")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1231 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1231")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1211 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1211")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1201 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1201")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1191 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1191")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1171 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1171")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1181 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1181")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1161 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1161")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1151 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1151")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1141 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1141")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1121 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1121")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___38___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1121") (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1131 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1131")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1111 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1111")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___37___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1111") (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1101 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1101")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___36___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1101") (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o191 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o191")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___35___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o191") (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o171 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o171")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___33___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o171") (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o181 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o181")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___34___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o181") (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o161 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o161")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___32___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o161") (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o151 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o151")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___31___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o151") (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o142 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o142")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___30___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o142") (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o131 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o131")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___29___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o131") (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o121 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o121")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___28___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o121") (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o111 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o111")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___27___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o111") (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1411 "EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1411")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___26___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1411") (owner "Xilinx"))
+              (property INIT (string "FD5DA808") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mxor_carry_8__carry_7__XOR_142_o_xo_0_1 "EU_CORE/Mxor_carry[8]_carry[7]_XOR_142_o_xo<0>1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "42") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_8_1 "EU_CORE/carry<8>1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "B2") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_data_23_21 "EU_CORE/eu_rom_data<23>21")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "08192A3B4C5D6E7F") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_data_19_21 "EU_CORE/eu_rom_data<19>21")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1156_inv1 "EU_CORE/_n1156_inv1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___13___EU_CORE/_n1152_inv1") (owner "Xilinx"))
+              (property INIT (string "8000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_3_1 "EU_CORE/carry<3>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0080AAEAA0A8FAFE") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_4_1 "EU_CORE/carry<4>1")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___10___EU_CORE/carry<4>1") (owner "Xilinx"))
+              (property INIT (string "B2") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_data_23_11 "EU_CORE/eu_rom_data<23>11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "08192A3B4C5D6E7F") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_data_19_11 "EU_CORE/eu_rom_data<19>11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_data_23_31 "EU_CORE/eu_rom_data<23>31")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "08192A3B4C5D6E7F") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_data_23_1 "EU_CORE/eu_rom_data<23>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "08192A3B4C5D6E7F") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_rom_data_19_1 "EU_CORE/eu_rom_data<19>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457911 "EU_CORE/Mmux_n0457911")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F731") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1090_inv1 "EU_CORE/_n1090_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT1411 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT1411")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___25___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1391") (owner "Xilinx"))
+              (property INIT (string "89") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT14 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT14")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___38___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1121") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT21 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT21")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___37___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1111") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT31 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT31")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___36___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1101") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT41 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT41")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___35___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o191") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT51 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT51")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___34___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o181") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT61 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT61")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___33___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o171") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT71 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT71")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___32___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o161") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT81 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT81")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___31___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o151") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT91 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT91")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___30___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o142") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT101 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT101")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___29___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o131") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT111 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT111")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___28___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o121") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT121 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT121")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___27___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o111") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT131 "EU_CORE/Mmux_eu_calling_address[51]_eu_calling_address[38]_mux_145_OUT131")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___26___EU_CORE/Mmux_eu_opcode_jump_src[2]_eu_calling_address[51]_Mux_147_o1411") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE__n1159_inv1 "EU_CORE/_n1159_inv1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00010000FFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_stall_pipeline_eu_opcode_type_2__AND_132_o1 "EU_CORE/eu_stall_pipeline_eu_opcode_type[2]_AND_132_o1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___21___EU_CORE/eu_stall_pipeline_eu_opcode_type[2]_AND_134_o1") (owner "Xilinx"))
+              (property INIT (string "0002") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_intr_asserted1 "EU_CORE/intr_asserted1")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___56___EU_CORE/intr_asserted1") (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT31_renamed_262 "BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_129_OUT31")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "11115313") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT32 "BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_129_OUT32")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BAAAFFFF1000FFFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT33 "BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_129_OUT33")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AE") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT11 "BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_129_OUT11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0404000447444744") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT12 "BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_129_OUT12")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AA08") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT21 "BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_129_OUT21")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0062006228600860") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT22 "BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_129_OUT22")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AA08") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_1_renamed_263 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<0>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFAAAA8808") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__den_int_Select_196_o1_renamed_264 "BIU_CORE/biu_state[7]_den_int_Select_196_o1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF200020002000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__den_int_Select_196_o2_renamed_265 "BIU_CORE/biu_state[7]_den_int_Select_196_o2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF515551555155") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__den_int_Select_196_o3_renamed_266 "BIU_CORE/biu_state[7]_den_int_Select_196_o3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "08080008FFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__den_int_Select_196_o4 "BIU_CORE/biu_state[7]_den_int_Select_196_o4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFAAA8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__wr_n_int_Select_198_o_SW0 "BIU_CORE/biu_state[7]_wr_n_int_Select_198_o_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFAA2A") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__wr_n_int_Select_198_o_renamed_267 "BIU_CORE/biu_state[7]_wr_n_int_Select_198_o")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFA8AAAAAAA8AA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__biu_done_int_Select_186_o_SW0 "BIU_CORE/biu_state[7]_biu_done_int_Select_186_o_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFF08080008") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__biu_done_int_Select_186_o_renamed_268 "BIU_CORE/biu_state[7]_biu_done_int_Select_186_o")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFAAAA8AAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_2_renamed_269 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>2")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF2000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_4_renamed_270 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF080808") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_5 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFEAAAAFEFEAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_5__SW0 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<5>_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___24___BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<5>_SW0") (owner "Xilinx"))
+              (property INIT (string "7F") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_5__ "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<5>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAEAAA6AAAAA0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_4__SW0 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<4>_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___49___BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<4>_SW0") (owner "Xilinx"))
+              (property INIT (string "7") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_4__ "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<4>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAEAAA6AAAAA0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3__SW0 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<3>_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___43___BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<2>1") (owner "Xilinx"))
+              (property INIT (string "8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3__ "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<3>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFEAFF6AFFAAFF00") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_1_renamed_271 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "5151FF517373FF73") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__dtr_int_Select_189_o11_renamed_272 "BIU_CORE/biu_state[7]_dtr_int_Select_189_o11")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFF8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_211_renamed_273 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>211")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0400") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_213 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>213")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF2000FFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_2_renamed_274 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<3>2")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_3_renamed_275 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<3>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<3>4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFF8F8F8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_2_renamed_276 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<2>2")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_3_renamed_277 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<2>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<2>4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFF8F8F8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_2_renamed_278 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<1>2")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_3_renamed_279 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<1>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<1>4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFEAFFC0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_2_renamed_280 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<0>2")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_3_renamed_281 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<0>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_4_renamed_282 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<0>4")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFEAFFC0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_Select_180_o1_renamed_283 "BIU_CORE/biu_state[7]_GND_14_o_Select_180_o1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAAAAA8AAAAAAAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_Select_180_o2 "BIU_CORE/biu_state[7]_GND_14_o_Select_180_o2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFF80000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__dtr_int_Select_189_o1_renamed_284 "BIU_CORE/biu_state[7]_dtr_int_Select_189_o1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0200008002000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n1063_inv_SW0 "BIU_CORE/_n1063_inv_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FDFFFDBFFFFFFDBF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_1_renamed_285 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<19>1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_2_renamed_286 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<19>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF80808080808080") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<19>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFF8F8F8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_1_renamed_287 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<18>1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_2_renamed_288 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<18>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF80808080808080") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<18>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFF8F8F8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_1_renamed_289 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<17>1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_2_renamed_290 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<17>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF80808080808080") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<17>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFF8F8F8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_1_renamed_291 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<16>1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_2_renamed_292 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<16>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF80808080808080") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<16>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFF8F8F8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_1_renamed_293 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<9>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F8888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_2_renamed_294 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<9>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_3_renamed_295 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<9>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<9>4")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FEEE") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_1_renamed_296 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<8>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F8888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_2_renamed_297 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<8>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_3_renamed_298 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<8>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<8>4")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FEEE") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_1_renamed_299 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<7>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F8888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_2_renamed_300 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<7>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_3_renamed_301 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<7>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<7>4")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FEEE") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_1_renamed_302 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<6>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F8888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_2_renamed_303 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<6>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_3_renamed_304 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<6>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<6>4")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FEEE") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_1_renamed_305 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<5>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F8888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_2_renamed_306 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<5>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_3_renamed_307 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<5>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<5>4")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FEEE") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_1_renamed_308 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<4>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F8888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_2_renamed_309 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<4>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_3_renamed_310 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<4>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<4>4")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FEEE") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_1_renamed_311 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<15>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F8888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_2_renamed_312 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<15>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_3_renamed_313 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<15>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<15>4")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FEEE") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_1_renamed_314 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<14>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F8888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_2_renamed_315 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<14>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_3_renamed_316 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<14>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<14>4")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FEEE") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_1_renamed_317 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<13>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F8888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_2_renamed_318 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<13>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_3_renamed_319 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<13>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<13>4")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FEEE") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_1_renamed_320 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<12>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F8888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_2_renamed_321 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<12>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_3_renamed_322 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<12>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<12>4")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FEEE") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_1_renamed_323 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<11>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F8888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_2_renamed_324 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<11>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_3_renamed_325 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<11>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<11>4")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FEEE") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_1_renamed_326 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<10>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F8888888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_2_renamed_327 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<10>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFF888F888F888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_3_renamed_328 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<10>3")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88888000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_4_renamed_329 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<10>4")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FEEE") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_2_renamed_330 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<0>2")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AA2A8808") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_3 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<0>3")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FDF8") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_7__ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<7>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFA888A888A888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_6__ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<6>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFA888A888A888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_5__ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<5>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFA888A888A888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_4__ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<4>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFA888A888A888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_3__ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<3>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFA888A888A888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_2__ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<2>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFA888A888A888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_1__ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<1>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFA888A888A888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0__ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<0>")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFA888A888A888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_BIU_CLK_COUNTER_ZERO_12_1_renamed_331 "BIU_CORE/BIU_CLK_COUNTER_ZERO<12>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_BIU_CLK_COUNTER_ZERO_12_2 "BIU_CORE/BIU_CLK_COUNTER_ZERO<12>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_BIU_CLK_COUNTER_ZERO_12_3 "BIU_CORE/BIU_CLK_COUNTER_ZERO<12>3")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "40") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045761_renamed_332 "EU_CORE/Mmux_n045761")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFDF5757DF8B5703") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045762 "EU_CORE/Mmux_n045762")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF405540554055") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045764 "EU_CORE/Mmux_n045764")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0880") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045721_renamed_333 "EU_CORE/Mmux_n045721")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "038B") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045722 "EU_CORE/Mmux_n045722")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BBABABAB33232303") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045724 "EU_CORE/Mmux_n045724")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0880") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457134 "EU_CORE/Mmux_n0457134")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8008") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457121_renamed_334 "EU_CORE/Mmux_n0457121")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "038B") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457122 "EU_CORE/Mmux_n0457122")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BBABABAB33232303") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045714_SW0 "EU_CORE/Mmux_n045714_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "98FC187CCC984C18") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045714_SW1 "EU_CORE/Mmux_n045714_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "90F41074C4904410") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045714_SW2 "EU_CORE/Mmux_n045714_SW2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9CF81C78C89C481C") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045714_SW3 "EU_CORE/Mmux_n045714_SW3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "94F01470C0944014") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045714 "EU_CORE/Mmux_n045714")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "272727270055AAFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045716_SW0 "EU_CORE/Mmux_n045716_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "67036F0B33673B6F") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045716_SW1 "EU_CORE/Mmux_n045716_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E783EF8BB3E7BBEF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045716_SW2 "EU_CORE/Mmux_n045716_SW2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "63076B0F37633F6B") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045716_SW3 "EU_CORE/Mmux_n045716_SW3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E387EB8FB7E3BFEB") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045716 "EU_CORE/Mmux_n045716")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F5F5A0A0DD88DD88") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045731_renamed_335 "EU_CORE/Mmux_n045731")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "50D855DD73FB77FF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045732 "EU_CORE/Mmux_n045732")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF045504550455") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT181_renamed_336 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT181")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT182 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT182")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EFEA4540") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT183 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT183")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFCFFCCCEEEEEEEE") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT201_renamed_337 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT201")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT202 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT202")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EFEA4540") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT203 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT203")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "3303300022222222") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT221_renamed_338 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT221")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT222 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT222")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EFEA4540") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT223 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT223")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "3303300022222222") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT261_renamed_339 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT261")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E8E0C8C028200800") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT262 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT262")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1154005411100010") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT263 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT263")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "55504444") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT41_renamed_340 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT41")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E8E0C8C028200800") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT42 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT42")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1154005411100010") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT43 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT43")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "55504444") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT61_renamed_341 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT61")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E8E0C8C028200800") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT62 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT62")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1154005411100010") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT63 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT63")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "55504444") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT81_renamed_342 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT81")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E8E0C8C028200800") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT82 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT82")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1154005411100010") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT83 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT83")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "55504444") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457111_renamed_343 "EU_CORE/Mmux_n0457111")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "88808A8808000A08") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457112_renamed_344 "EU_CORE/Mmux_n0457112")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___48___EU_CORE/Mmux_n0457112") (owner "Xilinx"))
+              (property INIT (string "02") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457113 "EU_CORE/Mmux_n0457113")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFCC40FFFFCC04") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045741 "EU_CORE/Mmux_n045741")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "08000A0888808A88") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045742_renamed_345 "EU_CORE/Mmux_n045742")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___55___EU_CORE/Mmux_n045742") (owner "Xilinx"))
+              (property INIT (string "02") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457151 "EU_CORE/Mmux_n0457151")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "08000A0888808A88") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457152_renamed_346 "EU_CORE/Mmux_n0457152")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___48___EU_CORE/Mmux_n0457112") (owner "Xilinx"))
+              (property INIT (string "02") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_n0072_15_1_renamed_347 "EU_CORE/n0072<15>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_n0072_15_2 "EU_CORE/n0072<15>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_n0072_15_3 "EU_CORE/n0072<15>3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0001000000000000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_stall_pipeline_eu_jump_boolean_AND_136_o_SW0 "EU_CORE/eu_stall_pipeline_eu_jump_boolean_AND_136_o_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FEBA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_stall_pipeline_eu_jump_boolean_AND_136_o_renamed_348 "EU_CORE/eu_stall_pipeline_eu_jump_boolean_AND_136_o")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000010") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT141_renamed_349 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT141")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "5E0E5404") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT142_renamed_350 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT142")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BEAEBAAA14041000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT143 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT143")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F0C000A0A0A0A") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT161_renamed_351 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT161")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "5E0E5404") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT162 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT162")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BEAEBAAA14041000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT163 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT163")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0F0F0C000A0A0A0A") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT101_renamed_352 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT101")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "5E0E5404") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT102 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT102")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FDDD7555A8882000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT103 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT103")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "3022") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT121_renamed_353 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT121")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT122 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT122")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EC20") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT123 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT123")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "3303300022222222") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT21_renamed_354 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT21")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "D9C85140") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT22_renamed_355 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT22")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E444") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT23 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT23")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "3022") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT241_renamed_356 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT241")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BAB832308A880200") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT242 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT242")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "5554151451501110") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT243 "EU_CORE/Mmux_eu_rom_address[12]_GND_15_o_mux_205_OUT243")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "55504444") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_parity_SW0 "EU_CORE/eu_parity_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "69") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_parity_renamed_357 "EU_CORE/eu_parity")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6996966996696996") (owner "Xilinx"))
+            )
+            (instance (rename CLK_IBUF_renamed_358 "CLK_IBUF")
+              (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename RESET_IBUF_renamed_359 "RESET_IBUF")
+              (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename READY_IBUF_renamed_360 "READY_IBUF")
+              (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename INTR_IBUF_renamed_361 "INTR_IBUF")
+              (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename NMI_IBUF_renamed_362 "NMI_IBUF")
+              (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_D_7_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_D_6_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_D_5_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_D_4_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_D_3_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_D_2_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_D_1_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_D_0_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance AD7_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance AD6_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance AD5_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance AD4_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance AD3_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance AD2_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance AD1_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance AD0_IOBUF
+              (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_18_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_17_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_16_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_15_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_14_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_13_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_12_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_11_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_10_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_9_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_8_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_7_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_6_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_5_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_4_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_3_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_2_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_1_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_A_0_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename LED_7_OBUF_renamed_363 "LED_7_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename LED_6_OBUF_renamed_364 "LED_6_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename LED_5_OBUF_renamed_365 "LED_5_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename LED_4_OBUF_renamed_366 "LED_4_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename LED_3_OBUF_renamed_367 "LED_3_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename LED_2_OBUF_renamed_368 "LED_2_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename LED_1_OBUF_renamed_369 "LED_1_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename LED_0_OBUF_renamed_370 "LED_0_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A19_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A18_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A17_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A16_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A15_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A14_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A13_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A12_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A11_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A10_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A9_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A8_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance ALE_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance INTA_n_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance RD_n_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance WR_n_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance IOM_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance DTR_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance DEN_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SSO_n_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_CE_n_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance SRAM_OE_n_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename SRAM_WE_n_OBUF_renamed_371 "SRAM_WE_n_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance BUF1_OE_n_OBUF
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BUF2_OE_n_OBUF_renamed_372 "BUF2_OE_n_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BUF2_DIR_OBUF_renamed_373 "BUF2_DIR_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename t_reset_d4_renamed_374 "t_reset_d4")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_biu_req_caught_renamed_375 "BIU_CORE/eu_biu_req_caught")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_nmi_caught_renamed_376 "BIU_CORE/nmi_caught")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_tr_latched_renamed_377 "EU_CORE/eu_tr_latched")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_biu_done_caught_renamed_378 "EU_CORE/biu_done_caught")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_1__rt_renamed_379 "Mcount_prescaler_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_2__rt_renamed_380 "Mcount_prescaler_cy<2>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_3__rt_renamed_381 "Mcount_prescaler_cy<3>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_4__rt_renamed_382 "Mcount_prescaler_cy<4>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_5__rt_renamed_383 "Mcount_prescaler_cy<5>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_6__rt_renamed_384 "Mcount_prescaler_cy<6>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_7__rt_renamed_385 "Mcount_prescaler_cy<7>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_8__rt_renamed_386 "Mcount_prescaler_cy<8>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_9__rt_renamed_387 "Mcount_prescaler_cy<9>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_10__rt_renamed_388 "Mcount_prescaler_cy<10>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_11__rt_renamed_389 "Mcount_prescaler_cy<11>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_12__rt_renamed_390 "Mcount_prescaler_cy<12>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_13__rt_renamed_391 "Mcount_prescaler_cy<13>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_14__rt_renamed_392 "Mcount_prescaler_cy<14>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_15__rt_renamed_393 "Mcount_prescaler_cy<15>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_16__rt_renamed_394 "Mcount_prescaler_cy<16>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_17__rt_renamed_395 "Mcount_prescaler_cy<17>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_18__rt_renamed_396 "Mcount_prescaler_cy<18>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_19__rt_renamed_397 "Mcount_prescaler_cy<19>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_cy_20__rt_renamed_398 "Mcount_prescaler_cy<20>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_14__rt_renamed_399 "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<14>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_13__rt_renamed_400 "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<13>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_12__rt_renamed_401 "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<12>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_11__rt_renamed_402 "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<11>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_10__rt_renamed_403 "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<10>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_9__rt_renamed_404 "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<9>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_8__rt_renamed_405 "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<8>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_7__rt_renamed_406 "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<7>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_6__rt_renamed_407 "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<6>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_5__rt_renamed_408 "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<5>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_4__rt_renamed_409 "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<4>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_3__rt_renamed_410 "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<3>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_2__rt_renamed_411 "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<2>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_1__rt_renamed_412 "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_18__rt_renamed_413 "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<18>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_17__rt_renamed_414 "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<17>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_16__rt_renamed_415 "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<16>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_18__rt_renamed_416 "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<18>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_17__rt_renamed_417 "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<17>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_16__rt_renamed_418 "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<16>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_18__rt_renamed_419 "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<18>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_17__rt_renamed_420 "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<17>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_16__rt_renamed_421 "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<16>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_11__rt_renamed_422 "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<11>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_10__rt_renamed_423 "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<10>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_9__rt_renamed_424 "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<9>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_8__rt_renamed_425 "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<8>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_7__rt_renamed_426 "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<7>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_6__rt_renamed_427 "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<6>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_5__rt_renamed_428 "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<5>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_4__rt_renamed_429 "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<4>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_3__rt_renamed_430 "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<3>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_2__rt_renamed_431 "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<2>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_1__rt_renamed_432 "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_xor_21__rt_renamed_433 "Mcount_prescaler_xor<21>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_15__rt_renamed_434 "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_xor<15>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_19__rt_renamed_435 "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_xor<19>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_19__rt_renamed_436 "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_xor<19>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_19__rt_renamed_437 "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_xor<19>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_12__rt_renamed_438 "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_xor<12>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_BIU_INTR_renamed_439 "BIU_CORE/BIU_INTR")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ale_int_renamed_440 "BIU_CORE/ale_int")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_iom_int_renamed_441 "BIU_CORE/iom_int")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_intr_enable_delayed_rstpot_renamed_442 "EU_CORE/intr_enable_delayed_rstpot")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___56___EU_CORE/intr_asserted1") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_intr_enable_delayed_renamed_443 "EU_CORE/intr_enable_delayed")
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename led_go_left_renamed_444 "led_go_left")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_word_cycle_renamed_445 "BIU_CORE/word_cycle")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1 "EU_CORE/carry<5>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DD4D4D44") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045771_SW1 "EU_CORE/Mmux_n045771_SW1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "C99F") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_13_1_SW0 "EU_CORE/carry<13>1_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FF5577117F155701") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_13_1_SW1 "EU_CORE/carry<13>1_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "80EAA8FE88EEAAFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_mux23_4_renamed_446 "EU_CORE/mux23_4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF55550FFF3333") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045733_SW0 "EU_CORE/Mmux_n045733_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045734 "EU_CORE/Mmux_n045734")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF0540FFFF0045") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045763_SW0 "EU_CORE/Mmux_n045763_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FBAEAEFB") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045763_SW1 "EU_CORE/Mmux_n045763_SW1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BAEFEFBA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_11_1_SW0 "EU_CORE/carry<11>1_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8EAF0A8E0A8E0A8E") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_11_1_SW1 "EU_CORE/carry<11>1_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8EAF8EAF8EAF0A8E") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_7_1_SW0 "EU_CORE/carry<7>1_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00AAA0FA80EAA8FE") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_7_1_SW1 "EU_CORE/carry<7>1_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "80EAA8FEA0FAAAFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457411_SW0 "EU_CORE/Mmux_n0457411_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AFAFFAFABEAFEBFA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457411_SW1 "EU_CORE/Mmux_n0457411_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BEAFEBFABEBEEBEB") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045743 "EU_CORE/Mmux_n045743")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "ECEEECEEECECEEEE") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_9_1_SW0 "EU_CORE/carry<9>1_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FBB0F220") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_9_1_SW1 "EU_CORE/carry<9>1_SW1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FBB0F220") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_11_1 "EU_CORE/carry<11>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FEF81070") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW0 "EU_CORE/carry<15>1_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FADB") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW1 "EU_CORE/carry<15>1_SW1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DB5F") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mxor_carry_16__carry_15__XOR_141_o_xo_0_1 "EU_CORE/Mxor_carry[16]_carry[15]_XOR_141_o_xo<0>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0C3F05AF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW2 "EU_CORE/carry<15>1_SW2")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FAE8") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW3 "EU_CORE/carry<15>1_SW3")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E8A0") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_16_1 "EU_CORE/carry<16>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F3C0FA50") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045772 "EU_CORE/Mmux_n045772")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "77227272") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457123_SW0 "EU_CORE/Mmux_n0457123_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457124 "EU_CORE/Mmux_n0457124")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF0540FFFF0045") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n04571111 "EU_CORE/Mmux_n04571111")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___10___EU_CORE/carry<4>1") (owner "Xilinx"))
+              (property INIT (string "9C99CC9C") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045723_SW0 "EU_CORE/Mmux_n045723_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FBAEAEFB") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045723_SW1 "EU_CORE/Mmux_n045723_SW1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BAEFEFBA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045725 "EU_CORE/Mmux_n045725")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F4F4F5F5F4F5F4F5") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n04571511_SW0 "EU_CORE/Mmux_n04571511_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AFAFFAFABEAFEBFA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n04571511_SW1 "EU_CORE/Mmux_n04571511_SW1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BEAFEBFABEBEEBEB") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457153 "EU_CORE/Mmux_n0457153")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F8FAF8FAF8F8FAFA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045754 "EU_CORE/Mmux_n045754")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0FBF4FFF0F2FDFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_13_1_SW4 "EU_CORE/carry<13>1_SW4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFD2002DF0000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_13_1_SW5 "EU_CORE/carry<13>1_SW5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFB4004BF0000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045765 "EU_CORE/Mmux_n045765")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F4F4F5F4F4F5F5F5") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_7_1 "EU_CORE/carry<7>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FD75B931EC64A820") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW4 "EU_CORE/carry<5>1_SW4")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCEEECFE008880C8") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW5 "EU_CORE/carry<5>1_SW5")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "ECFEEEFF80C888CC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_9_1 "EU_CORE/carry<9>1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "F0E4D8CC") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__inta_n_int_Select_202_o_SW0_SW0 "BIU_CORE/biu_state[7]_inta_n_int_Select_202_o_SW0_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFAAA8AAAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__inta_n_int_Select_202_o_renamed_447 "BIU_CORE/biu_state[7]_inta_n_int_Select_202_o")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFA8AAAAAAA8AA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__rd_n_int_Select_200_o_SW0_SW0 "BIU_CORE/biu_state[7]_rd_n_int_Select_200_o_SW0_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFF888AAAAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__rd_n_int_Select_200_o_renamed_448 "BIU_CORE/biu_state[7]_rd_n_int_Select_200_o")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFA8AAAAAAA8AA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_equal_173_o_7_11 "BIU_CORE/biu_state[7]_GND_14_o_equal_173_o<7>11")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___24___BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<5>_SW0") (owner "Xilinx"))
+              (property INIT (string "04000000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457135_SW0 "EU_CORE/Mmux_n0457135_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EBBEBBEE") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457135_SW1 "EU_CORE/Mmux_n0457135_SW1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EEBBEBBE") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457136 "EU_CORE/Mmux_n0457136")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF4545FFFF4455") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045751_SW0 "EU_CORE/Mmux_n045751_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "71") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045752 "EU_CORE/Mmux_n045752")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8B83BBB30B033B33") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_13_1_SW2 "EU_CORE/carry<13>1_SW2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BFFAFABFBAFFFFBA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_13_1_SW3 "EU_CORE/carry<13>1_SW3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BFFAFABFBAFFFFBA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3_11 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<3>11")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFF00000020") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__dtr_int_Select_189_o121 "BIU_CORE/biu_state[7]_dtr_int_Select_189_o121")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___20___BIU_CORE/biu_state[7]_GND_14_o_equal_167_o<7>1") (owner "Xilinx"))
+              (property INIT (string "FFFF20FF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n11411 "BIU_CORE/_n11411")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFF02020028") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_111 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>111")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFFFFFF1000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_212_renamed_449 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>212")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFF20000000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457133_SW0 "EU_CORE/Mmux_n0457133_SW0")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8E") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457133_renamed_450 "EU_CORE/Mmux_n0457133")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "3BBB33B30B8B0383") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_1_SW0 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<0>1_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000002000200000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n11521 "BIU_CORE/_n11521")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000400040400") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_equal_174_o_7_1 "BIU_CORE/biu_state[7]_GND_14_o_equal_174_o<7>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0100000000000000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_system_signals_7_1 "EU_CORE/system_signals<7>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6FFFF6FFFF6FFFF6") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_21 "BIU_CORE/biu_state[7]_GND_14_o_equal_166_o<7>21")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_equal_170_o_7_1 "BIU_CORE/biu_state[7]_GND_14_o_equal_170_o<7>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000040000000000") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW0 "EU_CORE/carry<5>1_SW0")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW0_F "EU_CORE/carry<5>1_SW0_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00000088000080C8") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW0_G "EU_CORE/carry<5>1_SW0_G")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0088FFFF80C8FFFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW1 "EU_CORE/carry<5>1_SW1")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW1_F "EU_CORE/carry<5>1_SW1_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000CCEE0000ECFE") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW1_G "EU_CORE/carry<5>1_SW1_G")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "CCEEFFFFECFEFFFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW2 "EU_CORE/carry<5>1_SW2")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW2_F "EU_CORE/carry<5>1_SW2_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "000080C8000088CC") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW2_G "EU_CORE/carry<5>1_SW2_G")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "80C8FFFF88CCFFFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW3 "EU_CORE/carry<5>1_SW3")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW3_F "EU_CORE/carry<5>1_SW3_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000ECFE0000EEFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_5_1_SW3_G "EU_CORE/carry<5>1_SW3_G")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "ECFEFFFFEEFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457104 "EU_CORE/Mmux_n0457104")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n04571_SW4 "EU_CORE/Mmux_n04571_SW4")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___55___EU_CORE/Mmux_n045742") (owner "Xilinx"))
+              (property INIT (string "E4") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n04571 "EU_CORE/Mmux_n04571")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "64003064EC88B8EC") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_word_cycle_rstpot1_renamed_451 "BIU_CORE/word_cycle_rstpot1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "54101010") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_biu_req_caught_glue_set_renamed_452 "BIU_CORE/eu_biu_req_caught_glue_set")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "22F2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_nmi_caught_glue_set_renamed_453 "BIU_CORE/nmi_caught_glue_set")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "00800080FFFF0080") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_eu_tr_latched_glue_set_renamed_454 "EU_CORE/eu_tr_latched_glue_set")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "22F2") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ale_int_rstpot_SW0 "BIU_CORE/ale_int_rstpot_SW0")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___49___BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<4>_SW0") (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_ale_int_rstpot_renamed_455 "BIU_CORE/ale_int_rstpot")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAAAEAAAAAAA2AA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__den_int_Select_196_o113_SW0 "BIU_CORE/biu_state[7]_den_int_Select_196_o113_SW0")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___11___BIU_CORE/biu_state[7]_GND_14_o_equal_169_o<7>1") (owner "Xilinx"))
+              (property INIT (string "028A") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__den_int_Select_196_o113 "BIU_CORE/biu_state[7]_den_int_Select_196_o113")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFFFFFF5D554800") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_21_SW1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<0>21_SW1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___1___BIU_CORE/out1") (owner "Xilinx"))
+              (property INIT (string "EFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_21_renamed_456 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<0>21")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000020002000200") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_3_SW1 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>3_SW1")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FBFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_3_renamed_457 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000040000000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_1_SW0 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>1_SW0")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFF7FFFFFFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n1014_inv1 "BIU_CORE/_n1014_inv1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "DFDDFFFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__inta_n_int_Select_202_o21 "BIU_CORE/biu_state[7]_inta_n_int_Select_202_o21")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000008000000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n1076_inv_SW1 "BIU_CORE/_n1076_inv_SW1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "06000006") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE__n1076_inv_renamed_458 "BIU_CORE/_n1076_inv")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0002020002020202") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_biu_req_code_4__GND_14_o_select_117_OUT_0_11 "BIU_CORE/eu_biu_req_code[4]_GND_14_o_select_117_OUT<0>11")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___3___BIU_CORE/eu_biu_req_code[4]_INV_33_o1") (owner "Xilinx"))
+              (property INIT (string "15734444") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_full_GND_14_o_equal_124_o1 "BIU_CORE/pfq_full_GND_14_o_equal_124_o1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFFF6FF66FF6FFFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_pfq_empty1 "BIU_CORE/pfq_empty1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9009000000009009") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_equal_173_o_7_2 "BIU_CORE/biu_state[7]_GND_14_o_equal_173_o<7>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000040000000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_s_bits_2__word_cycle_AND_36_o1 "BIU_CORE/s_bits[2]_word_cycle_AND_36_o1")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___41___BIU_CORE/_n07981") (owner "Xilinx"))
+              (property INIT (string "88888880") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_0__ "BIU_CORE/Mcount_clock_cycle_counter_lut<0>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "515D") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_1__ "BIU_CORE/Mcount_clock_cycle_counter_lut<1>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "515D") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_2__ "BIU_CORE/Mcount_clock_cycle_counter_lut<2>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "515D") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_3__ "BIU_CORE/Mcount_clock_cycle_counter_lut<3>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "515D") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_4__ "BIU_CORE/Mcount_clock_cycle_counter_lut<4>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "515D") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_5__ "BIU_CORE/Mcount_clock_cycle_counter_lut<5>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "515D") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_15_o_inv1 "BIU_CORE/eu_biu_req_caught_eu_biu_req_code[4]_AND_15_o_inv1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFF7FFFFFFFFFFFF") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_6__ "BIU_CORE/Mcount_clock_cycle_counter_lut<6>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "515D") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_7__ "BIU_CORE/Mcount_clock_cycle_counter_lut<7>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "515D") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_8__ "BIU_CORE/Mcount_clock_cycle_counter_lut<8>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "515D") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_9__ "BIU_CORE/Mcount_clock_cycle_counter_lut<9>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "515D") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_10__ "BIU_CORE/Mcount_clock_cycle_counter_lut<10>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "515D") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_11__ "BIU_CORE/Mcount_clock_cycle_counter_lut<11>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "515D") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mcount_clock_cycle_counter_lut_12__ "BIU_CORE/Mcount_clock_cycle_counter_lut<12>")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "515D") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_BIU_INTR_rstpot_renamed_459 "BIU_CORE/BIU_INTR_rstpot")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "ABAAA8AA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_111 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<10>111")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___2___BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<10>111") (owner "Xilinx"))
+              (property INIT (string "00000010") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_21 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<10>21")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___2___BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<10>111") (owner "Xilinx"))
+              (property INIT (string "01000000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_7__SW0 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<7>_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_6__SW0 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<6>_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_5__SW0 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<5>_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_4__SW0 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<4>_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_3__SW0 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<3>_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_2__SW0 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<2>_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_1__SW0 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<1>_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0__SW0 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<0>_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "A8880888") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457104_F "EU_CORE/Mmux_n0457104_F")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "9379B15B") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__dtr_int_Select_189_o3 "BIU_CORE/biu_state[7]_dtr_int_Select_189_o3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "FFAAAAAAFF8AAAAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n0457104_G "EU_CORE/Mmux_n0457104_G")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "55155F1FF5B5FFBF") (owner "Xilinx"))
+            )
+            (instance (rename led_go_left_rstpot_renamed_460 "led_go_left_rstpot")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "BBAA8AAA") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_biu_done_caught_glue_set_renamed_461 "EU_CORE/biu_done_caught_glue_set")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8A8AFF8A") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT21 "BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT21")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8080808080808000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT31 "BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT31")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8080808080808000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT41 "BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT41")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8080808080808000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT51 "BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT51")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8080808080808000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT61 "BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT61")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8080808080808000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT71 "BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT71")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8080808080808000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT151 "BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT151")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8080808080808000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT161 "BIU_CORE/Mmux_GND_14_o_latched_data_in[7]_mux_157_OUT161")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8080808080808000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_11 "BIU_CORE/biu_state[7]_GND_14_o_equal_166_o<7>11")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___8___BIU_CORE/biu_state[7]_GND_14_o_equal_166_o<7>11") (owner "Xilinx"))
+              (property INIT (string "0001") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__dtr_int_Select_189_o11_SW0 "BIU_CORE/biu_state[7]_dtr_int_Select_189_o11_SW0")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property PK_HLUTNM (string "___XLNM___8___BIU_CORE/biu_state[7]_GND_14_o_equal_166_o<7>11") (owner "Xilinx"))
+              (property INIT (string "00010100") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_iom_int_rstpot_renamed_462 "BIU_CORE/iom_int_rstpot")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8AAAAAAABAAAAAAA") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_state_7__GND_14_o_Select_180_o112 "BIU_CORE/biu_state[7]_GND_14_o_Select_180_o112")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "054D015000000000") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_prescaler_lut_0__INV_0 "Mcount_prescaler_lut<0>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_lut_0__INV_0 "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_lut<0>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_lut_0__INV_0 "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_lut<0>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance BUF2_DIR1_INV_0
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename LED_7_1_INV_0 "LED<7>1_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename LED_6_1_INV_0 "LED<6>1_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename LED_5_1_INV_0 "LED<5>1_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename LED_4_1_INV_0 "LED<4>1_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename LED_3_1_INV_0 "LED<3>1_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename LED_2_1_INV_0 "LED<2>1_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename &_n01041_INV_0 "_n01041_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename LED_0_1_INV_0 "LED<0>1_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_RESET_INT_inv1_INV_0 "BIU_CORE/RESET_INT_inv1_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_n0457_1_4 "EU_CORE/n0457<1>4")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_n0457_1_4_F "EU_CORE/n0457<1>4_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "929F929F926F929F") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_n0457_1_4_G "EU_CORE/n0457<1>4_G")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "55155F1FF5B5FFBF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045793 "EU_CORE/Mmux_n045793")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045793_F "EU_CORE/Mmux_n045793_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "EBBEFFFF4114FFFF") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_Mmux_n045793_G "EU_CORE/Mmux_n045793_G")
+              (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "6056E8DE") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW4 "EU_CORE/carry<15>1_SW4")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW4_F "EU_CORE/carry<15>1_SW4_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "D7D77DD77DD77D7D") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW4_G "EU_CORE/carry<15>1_SW4_G")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "7") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW5 "EU_CORE/carry<15>1_SW5")
+              (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW5_F "EU_CORE/carry<15>1_SW5_F")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "D7D7D77DD77D7D7D") (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_carry_15_1_SW5_G "EU_CORE/carry<15>1_SW5_G")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "7") (owner "Xilinx"))
+            )
+            (instance (rename Mshreg_t_biu_ad_oe_d2_renamed_463 "Mshreg_t_biu_ad_oe_d2")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename t_biu_ad_oe_d2_renamed_464 "t_biu_ad_oe_d2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mshreg_t_reset_d2_renamed_465 "Mshreg_t_reset_d2")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename t_reset_d2_renamed_466 "t_reset_d2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_15_renamed_467 "BIU_CORE/Mshreg_biu_return_data_int_d2_15")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_15 "BIU_CORE/biu_return_data_int_d2_15")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_14_renamed_468 "BIU_CORE/Mshreg_biu_return_data_int_d2_14")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_14 "BIU_CORE/biu_return_data_int_d2_14")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_13_renamed_469 "BIU_CORE/Mshreg_biu_return_data_int_d2_13")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_13 "BIU_CORE/biu_return_data_int_d2_13")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_12_renamed_470 "BIU_CORE/Mshreg_biu_return_data_int_d2_12")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_12 "BIU_CORE/biu_return_data_int_d2_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_11_renamed_471 "BIU_CORE/Mshreg_biu_return_data_int_d2_11")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_11 "BIU_CORE/biu_return_data_int_d2_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_10_renamed_472 "BIU_CORE/Mshreg_biu_return_data_int_d2_10")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_10 "BIU_CORE/biu_return_data_int_d2_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_9_renamed_473 "BIU_CORE/Mshreg_biu_return_data_int_d2_9")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_9 "BIU_CORE/biu_return_data_int_d2_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_8_renamed_474 "BIU_CORE/Mshreg_biu_return_data_int_d2_8")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_8 "BIU_CORE/biu_return_data_int_d2_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_7_renamed_475 "BIU_CORE/Mshreg_biu_return_data_int_d2_7")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_7 "BIU_CORE/biu_return_data_int_d2_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_6_renamed_476 "BIU_CORE/Mshreg_biu_return_data_int_d2_6")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_6 "BIU_CORE/biu_return_data_int_d2_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_3_renamed_477 "BIU_CORE/Mshreg_biu_return_data_int_d2_3")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_3 "BIU_CORE/biu_return_data_int_d2_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_5_renamed_478 "BIU_CORE/Mshreg_biu_return_data_int_d2_5")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_5 "BIU_CORE/biu_return_data_int_d2_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_4_renamed_479 "BIU_CORE/Mshreg_biu_return_data_int_d2_4")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_4 "BIU_CORE/biu_return_data_int_d2_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_2_renamed_480 "BIU_CORE/Mshreg_biu_return_data_int_d2_2")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_2 "BIU_CORE/biu_return_data_int_d2_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_1_renamed_481 "BIU_CORE/Mshreg_biu_return_data_int_d2_1")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_1 "BIU_CORE/biu_return_data_int_d2_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_return_data_int_d2_0_renamed_482 "BIU_CORE/Mshreg_biu_return_data_int_d2_0")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_return_data_int_d2_0 "BIU_CORE/biu_return_data_int_d2_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_15_renamed_483 "BIU_CORE/Mshreg_biu_register_reg_d2_15")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_15 "BIU_CORE/biu_register_reg_d2_15")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_12_renamed_484 "BIU_CORE/Mshreg_biu_register_reg_d2_12")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_12 "BIU_CORE/biu_register_reg_d2_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_14_renamed_485 "BIU_CORE/Mshreg_biu_register_reg_d2_14")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_14 "BIU_CORE/biu_register_reg_d2_14")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_13_renamed_486 "BIU_CORE/Mshreg_biu_register_reg_d2_13")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_13 "BIU_CORE/biu_register_reg_d2_13")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_11_renamed_487 "BIU_CORE/Mshreg_biu_register_reg_d2_11")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_11 "BIU_CORE/biu_register_reg_d2_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_10_renamed_488 "BIU_CORE/Mshreg_biu_register_reg_d2_10")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_10 "BIU_CORE/biu_register_reg_d2_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_9_renamed_489 "BIU_CORE/Mshreg_biu_register_reg_d2_9")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_9 "BIU_CORE/biu_register_reg_d2_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_8_renamed_490 "BIU_CORE/Mshreg_biu_register_reg_d2_8")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_8 "BIU_CORE/biu_register_reg_d2_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_5_renamed_491 "BIU_CORE/Mshreg_biu_register_reg_d2_5")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_5 "BIU_CORE/biu_register_reg_d2_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_7_renamed_492 "BIU_CORE/Mshreg_biu_register_reg_d2_7")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_7 "BIU_CORE/biu_register_reg_d2_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_6_renamed_493 "BIU_CORE/Mshreg_biu_register_reg_d2_6")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_6 "BIU_CORE/biu_register_reg_d2_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_4_renamed_494 "BIU_CORE/Mshreg_biu_register_reg_d2_4")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_4 "BIU_CORE/biu_register_reg_d2_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_3_renamed_495 "BIU_CORE/Mshreg_biu_register_reg_d2_3")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_3 "BIU_CORE/biu_register_reg_d2_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_2_renamed_496 "BIU_CORE/Mshreg_biu_register_reg_d2_2")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_2 "BIU_CORE/biu_register_reg_d2_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_1_renamed_497 "BIU_CORE/Mshreg_biu_register_reg_d2_1")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_1 "BIU_CORE/biu_register_reg_d2_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_14_renamed_498 "BIU_CORE/Mshreg_biu_register_rm_d2_14")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_14 "BIU_CORE/biu_register_rm_d2_14")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_reg_d2_0_renamed_499 "BIU_CORE/Mshreg_biu_register_reg_d2_0")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_reg_d2_0 "BIU_CORE/biu_register_reg_d2_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_15_renamed_500 "BIU_CORE/Mshreg_biu_register_rm_d2_15")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_15 "BIU_CORE/biu_register_rm_d2_15")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_13_renamed_501 "BIU_CORE/Mshreg_biu_register_rm_d2_13")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_13 "BIU_CORE/biu_register_rm_d2_13")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_12_renamed_502 "BIU_CORE/Mshreg_biu_register_rm_d2_12")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_12 "BIU_CORE/biu_register_rm_d2_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_11_renamed_503 "BIU_CORE/Mshreg_biu_register_rm_d2_11")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_11 "BIU_CORE/biu_register_rm_d2_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_10_renamed_504 "BIU_CORE/Mshreg_biu_register_rm_d2_10")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_10 "BIU_CORE/biu_register_rm_d2_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_7_renamed_505 "BIU_CORE/Mshreg_biu_register_rm_d2_7")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_7 "BIU_CORE/biu_register_rm_d2_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_9_renamed_506 "BIU_CORE/Mshreg_biu_register_rm_d2_9")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_9 "BIU_CORE/biu_register_rm_d2_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_8_renamed_507 "BIU_CORE/Mshreg_biu_register_rm_d2_8")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_8 "BIU_CORE/biu_register_rm_d2_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_6_renamed_508 "BIU_CORE/Mshreg_biu_register_rm_d2_6")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_6 "BIU_CORE/biu_register_rm_d2_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_5_renamed_509 "BIU_CORE/Mshreg_biu_register_rm_d2_5")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_5 "BIU_CORE/biu_register_rm_d2_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_4_renamed_510 "BIU_CORE/Mshreg_biu_register_rm_d2_4")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_4 "BIU_CORE/biu_register_rm_d2_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_3_renamed_511 "BIU_CORE/Mshreg_biu_register_rm_d2_3")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_3 "BIU_CORE/biu_register_rm_d2_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_0_renamed_512 "BIU_CORE/Mshreg_biu_register_rm_d2_0")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_0 "BIU_CORE/biu_register_rm_d2_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_2_renamed_513 "BIU_CORE/Mshreg_biu_register_rm_d2_2")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_2 "BIU_CORE/biu_register_rm_d2_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_rm_d2_1_renamed_514 "BIU_CORE/Mshreg_biu_register_rm_d2_1")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_rm_d2_1 "BIU_CORE/biu_register_rm_d2_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_15_renamed_515 "BIU_CORE/Mshreg_biu_register_ds_d2_15")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_15 "BIU_CORE/biu_register_ds_d2_15")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_14_renamed_516 "BIU_CORE/Mshreg_biu_register_ds_d2_14")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_14 "BIU_CORE/biu_register_ds_d2_14")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_13_renamed_517 "BIU_CORE/Mshreg_biu_register_ds_d2_13")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_13 "BIU_CORE/biu_register_ds_d2_13")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_12_renamed_518 "BIU_CORE/Mshreg_biu_register_ds_d2_12")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_12 "BIU_CORE/biu_register_ds_d2_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_9_renamed_519 "BIU_CORE/Mshreg_biu_register_ds_d2_9")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_9 "BIU_CORE/biu_register_ds_d2_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_11_renamed_520 "BIU_CORE/Mshreg_biu_register_ds_d2_11")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_11 "BIU_CORE/biu_register_ds_d2_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_10_renamed_521 "BIU_CORE/Mshreg_biu_register_ds_d2_10")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_10 "BIU_CORE/biu_register_ds_d2_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_8_renamed_522 "BIU_CORE/Mshreg_biu_register_ds_d2_8")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_8 "BIU_CORE/biu_register_ds_d2_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_7_renamed_523 "BIU_CORE/Mshreg_biu_register_ds_d2_7")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_7 "BIU_CORE/biu_register_ds_d2_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_6_renamed_524 "BIU_CORE/Mshreg_biu_register_ds_d2_6")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_6 "BIU_CORE/biu_register_ds_d2_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_5_renamed_525 "BIU_CORE/Mshreg_biu_register_ds_d2_5")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_5 "BIU_CORE/biu_register_ds_d2_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_4_renamed_526 "BIU_CORE/Mshreg_biu_register_ds_d2_4")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_4 "BIU_CORE/biu_register_ds_d2_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_3_renamed_527 "BIU_CORE/Mshreg_biu_register_ds_d2_3")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_3 "BIU_CORE/biu_register_ds_d2_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_2_renamed_528 "BIU_CORE/Mshreg_biu_register_ds_d2_2")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_2 "BIU_CORE/biu_register_ds_d2_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_1_renamed_529 "BIU_CORE/Mshreg_biu_register_ds_d2_1")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_1 "BIU_CORE/biu_register_ds_d2_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ds_d2_0_renamed_530 "BIU_CORE/Mshreg_biu_register_ds_d2_0")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ds_d2_0 "BIU_CORE/biu_register_ds_d2_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_15_renamed_531 "BIU_CORE/Mshreg_biu_register_ss_d2_15")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_15 "BIU_CORE/biu_register_ss_d2_15")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_14_renamed_532 "BIU_CORE/Mshreg_biu_register_ss_d2_14")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_14 "BIU_CORE/biu_register_ss_d2_14")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_13_renamed_533 "BIU_CORE/Mshreg_biu_register_ss_d2_13")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_13 "BIU_CORE/biu_register_ss_d2_13")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_10_renamed_534 "BIU_CORE/Mshreg_biu_register_ss_d2_10")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_10 "BIU_CORE/biu_register_ss_d2_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_12_renamed_535 "BIU_CORE/Mshreg_biu_register_ss_d2_12")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_12 "BIU_CORE/biu_register_ss_d2_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_11_renamed_536 "BIU_CORE/Mshreg_biu_register_ss_d2_11")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_11 "BIU_CORE/biu_register_ss_d2_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_9_renamed_537 "BIU_CORE/Mshreg_biu_register_ss_d2_9")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_9 "BIU_CORE/biu_register_ss_d2_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_8_renamed_538 "BIU_CORE/Mshreg_biu_register_ss_d2_8")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_8 "BIU_CORE/biu_register_ss_d2_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_7_renamed_539 "BIU_CORE/Mshreg_biu_register_ss_d2_7")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_7 "BIU_CORE/biu_register_ss_d2_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_6_renamed_540 "BIU_CORE/Mshreg_biu_register_ss_d2_6")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_6 "BIU_CORE/biu_register_ss_d2_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_3_renamed_541 "BIU_CORE/Mshreg_biu_register_ss_d2_3")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_3 "BIU_CORE/biu_register_ss_d2_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_5_renamed_542 "BIU_CORE/Mshreg_biu_register_ss_d2_5")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_5 "BIU_CORE/biu_register_ss_d2_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_4_renamed_543 "BIU_CORE/Mshreg_biu_register_ss_d2_4")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_4 "BIU_CORE/biu_register_ss_d2_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_2_renamed_544 "BIU_CORE/Mshreg_biu_register_ss_d2_2")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_2 "BIU_CORE/biu_register_ss_d2_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_1_renamed_545 "BIU_CORE/Mshreg_biu_register_ss_d2_1")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_1 "BIU_CORE/biu_register_ss_d2_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_ss_d2_0_renamed_546 "BIU_CORE/Mshreg_biu_register_ss_d2_0")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_ss_d2_0 "BIU_CORE/biu_register_ss_d2_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_15_renamed_547 "BIU_CORE/Mshreg_biu_register_es_d2_15")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_15 "BIU_CORE/biu_register_es_d2_15")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_12_renamed_548 "BIU_CORE/Mshreg_biu_register_es_d2_12")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_12 "BIU_CORE/biu_register_es_d2_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_14_renamed_549 "BIU_CORE/Mshreg_biu_register_es_d2_14")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_14 "BIU_CORE/biu_register_es_d2_14")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_13_renamed_550 "BIU_CORE/Mshreg_biu_register_es_d2_13")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_13 "BIU_CORE/biu_register_es_d2_13")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_11_renamed_551 "BIU_CORE/Mshreg_biu_register_es_d2_11")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_11 "BIU_CORE/biu_register_es_d2_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_10_renamed_552 "BIU_CORE/Mshreg_biu_register_es_d2_10")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_10 "BIU_CORE/biu_register_es_d2_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_9_renamed_553 "BIU_CORE/Mshreg_biu_register_es_d2_9")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_9 "BIU_CORE/biu_register_es_d2_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_8_renamed_554 "BIU_CORE/Mshreg_biu_register_es_d2_8")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_8 "BIU_CORE/biu_register_es_d2_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_5_renamed_555 "BIU_CORE/Mshreg_biu_register_es_d2_5")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_5 "BIU_CORE/biu_register_es_d2_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_7_renamed_556 "BIU_CORE/Mshreg_biu_register_es_d2_7")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_7 "BIU_CORE/biu_register_es_d2_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_6_renamed_557 "BIU_CORE/Mshreg_biu_register_es_d2_6")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_6 "BIU_CORE/biu_register_es_d2_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_4_renamed_558 "BIU_CORE/Mshreg_biu_register_es_d2_4")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_4 "BIU_CORE/biu_register_es_d2_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_3_renamed_559 "BIU_CORE/Mshreg_biu_register_es_d2_3")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_3 "BIU_CORE/biu_register_es_d2_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_2_renamed_560 "BIU_CORE/Mshreg_biu_register_es_d2_2")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_2 "BIU_CORE/biu_register_es_d2_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_1_renamed_561 "BIU_CORE/Mshreg_biu_register_es_d2_1")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_1 "BIU_CORE/biu_register_es_d2_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_14_renamed_562 "BIU_CORE/Mshreg_biu_register_cs_d2_14")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_14 "BIU_CORE/biu_register_cs_d2_14")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_es_d2_0_renamed_563 "BIU_CORE/Mshreg_biu_register_es_d2_0")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_es_d2_0 "BIU_CORE/biu_register_es_d2_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_15_renamed_564 "BIU_CORE/Mshreg_biu_register_cs_d2_15")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_15 "BIU_CORE/biu_register_cs_d2_15")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_13_renamed_565 "BIU_CORE/Mshreg_biu_register_cs_d2_13")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_13 "BIU_CORE/biu_register_cs_d2_13")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_12_renamed_566 "BIU_CORE/Mshreg_biu_register_cs_d2_12")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_12 "BIU_CORE/biu_register_cs_d2_12")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_11_renamed_567 "BIU_CORE/Mshreg_biu_register_cs_d2_11")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_11 "BIU_CORE/biu_register_cs_d2_11")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_10_renamed_568 "BIU_CORE/Mshreg_biu_register_cs_d2_10")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_10 "BIU_CORE/biu_register_cs_d2_10")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_7_renamed_569 "BIU_CORE/Mshreg_biu_register_cs_d2_7")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_7 "BIU_CORE/biu_register_cs_d2_7")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_9_renamed_570 "BIU_CORE/Mshreg_biu_register_cs_d2_9")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_9 "BIU_CORE/biu_register_cs_d2_9")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_8_renamed_571 "BIU_CORE/Mshreg_biu_register_cs_d2_8")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_8 "BIU_CORE/biu_register_cs_d2_8")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_6_renamed_572 "BIU_CORE/Mshreg_biu_register_cs_d2_6")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_6 "BIU_CORE/biu_register_cs_d2_6")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_5_renamed_573 "BIU_CORE/Mshreg_biu_register_cs_d2_5")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_5 "BIU_CORE/biu_register_cs_d2_5")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_4_renamed_574 "BIU_CORE/Mshreg_biu_register_cs_d2_4")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_4 "BIU_CORE/biu_register_cs_d2_4")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_3_renamed_575 "BIU_CORE/Mshreg_biu_register_cs_d2_3")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_3 "BIU_CORE/biu_register_cs_d2_3")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_0_renamed_576 "BIU_CORE/Mshreg_biu_register_cs_d2_0")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_0 "BIU_CORE/biu_register_cs_d2_0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_2_renamed_577 "BIU_CORE/Mshreg_biu_register_cs_d2_2")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_2 "BIU_CORE/biu_register_cs_d2_2")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_Mshreg_biu_register_cs_d2_1_renamed_578 "BIU_CORE/Mshreg_biu_register_cs_d2_1")
+              (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000") (owner "Xilinx"))
+            )
+            (instance (rename BIU_CORE_biu_register_cs_d2_1 "BIU_CORE/biu_register_cs_d2_1")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename EU_CORE_EU4Kx32_i "EU_CORE/EU4Kx32_i")
+              (viewRef view_1 (cellRef EU4Kx32 (libraryRef MCL86jr_lib)))
+              (property BUS_INFO (string "12:INPUT:addra<11:0>") (owner "Xilinx"))
+              (property BUS_INFO (string "32:OUTPUT:douta<31:0>") (owner "Xilinx"))
+            )
+            (net CORE_CLK
+              (joined
+                (portRef CORE_CLK)
+                (portRef I (instanceRef SPARTAN6PLL_clkin1_buf))
+              )
+            )
+            (net CLK_IBUF
+              (joined
+                (portRef D (instanceRef BIU_CORE_clk_d1_renamed_63))
+                (portRef O (instanceRef CLK_IBUF_renamed_358))
+              )
+            )
+            (net RESET_IBUF
+              (joined
+                (portRef O (instanceRef RESET_IBUF_renamed_359))
+                (portRef D (instanceRef Mshreg_t_reset_d2_renamed_465))
+              )
+            )
+            (net READY_IBUF
+              (joined
+                (portRef D (instanceRef BIU_CORE_ready_d1_renamed_69))
+                (portRef O (instanceRef READY_IBUF_renamed_360))
+              )
+            )
+            (net INTR_IBUF
+              (joined
+                (portRef D (instanceRef BIU_CORE_intr_d1_renamed_66))
+                (portRef O (instanceRef INTR_IBUF_renamed_361))
+              )
+            )
+            (net NMI_IBUF
+              (joined
+                (portRef D (instanceRef BIU_CORE_nmi_d1_renamed_72))
+                (portRef O (instanceRef NMI_IBUF_renamed_362))
+              )
+            )
+            (net core_clk_int
+              (joined
+                (portRef C (instanceRef t_biu_ad_out_d_0))
+                (portRef C (instanceRef t_biu_ad_out_d_1))
+                (portRef C (instanceRef t_biu_ad_out_d_2))
+                (portRef C (instanceRef t_biu_ad_out_d_3))
+                (portRef C (instanceRef t_biu_ad_out_d_4))
+                (portRef C (instanceRef t_biu_ad_out_d_5))
+                (portRef C (instanceRef t_biu_ad_out_d_6))
+                (portRef C (instanceRef t_biu_ad_out_d_7))
+                (portRef C (instanceRef t_biu_ad_out_d_8))
+                (portRef C (instanceRef t_biu_ad_out_d_9))
+                (portRef C (instanceRef t_biu_ad_out_d_10))
+                (portRef C (instanceRef t_biu_ad_out_d_11))
+                (portRef C (instanceRef t_biu_ad_out_d_12))
+                (portRef C (instanceRef t_biu_ad_out_d_13))
+                (portRef C (instanceRef t_biu_ad_out_d_14))
+                (portRef C (instanceRef t_biu_ad_out_d_15))
+                (portRef C (instanceRef t_biu_ad_out_d_16))
+                (portRef C (instanceRef t_biu_ad_out_d_17))
+                (portRef C (instanceRef t_biu_ad_out_d_18))
+                (portRef C (instanceRef t_biu_ad_out_d_19))
+                (portRef C (instanceRef led_int_0))
+                (portRef C (instanceRef led_int_1))
+                (portRef C (instanceRef led_int_2))
+                (portRef C (instanceRef led_int_3))
+                (portRef C (instanceRef led_int_4))
+                (portRef C (instanceRef led_int_5))
+                (portRef C (instanceRef led_int_6))
+                (portRef C (instanceRef led_int_7))
+                (portRef C (instanceRef prescaler_d_renamed_1))
+                (portRef C (instanceRef t_reset_d3_renamed_2))
+                (portRef C (instanceRef prescaler_0))
+                (portRef C (instanceRef prescaler_1))
+                (portRef C (instanceRef prescaler_2))
+                (portRef C (instanceRef prescaler_3))
+                (portRef C (instanceRef prescaler_4))
+                (portRef C (instanceRef prescaler_5))
+                (portRef C (instanceRef prescaler_6))
+                (portRef C (instanceRef prescaler_7))
+                (portRef C (instanceRef prescaler_8))
+                (portRef C (instanceRef prescaler_9))
+                (portRef C (instanceRef prescaler_10))
+                (portRef C (instanceRef prescaler_11))
+                (portRef C (instanceRef prescaler_12))
+                (portRef C (instanceRef prescaler_13))
+                (portRef C (instanceRef prescaler_14))
+                (portRef C (instanceRef prescaler_15))
+                (portRef C (instanceRef prescaler_16))
+                (portRef C (instanceRef prescaler_17))
+                (portRef C (instanceRef prescaler_18))
+                (portRef C (instanceRef prescaler_19))
+                (portRef C (instanceRef prescaler_20))
+                (portRef C (instanceRef prescaler_21))
+                (portRef O (instanceRef SPARTAN6PLL_clkout1_buf))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_0))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_1))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_2))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_3))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_4))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_5))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_6))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_7))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_8))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_9))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_10))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_11))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_12))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_13))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_14))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_15))
+                (portRef C (instanceRef BIU_CORE_ad_in_int_0))
+                (portRef C (instanceRef BIU_CORE_ad_in_int_1))
+                (portRef C (instanceRef BIU_CORE_ad_in_int_2))
+                (portRef C (instanceRef BIU_CORE_ad_in_int_3))
+                (portRef C (instanceRef BIU_CORE_ad_in_int_4))
+                (portRef C (instanceRef BIU_CORE_ad_in_int_5))
+                (portRef C (instanceRef BIU_CORE_ad_in_int_6))
+                (portRef C (instanceRef BIU_CORE_ad_in_int_7))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_0))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_1))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_2))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_3))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_4))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_5))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_6))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_7))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_8))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_9))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_10))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_11))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_12))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_13))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_14))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_15))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_0))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_1))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_2))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_3))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_4))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_5))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_6))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_7))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_8))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_9))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_10))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_11))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_12))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_13))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_14))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_15))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_0))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_1))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_2))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_3))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_4))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_5))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_6))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_7))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_8))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_9))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_10))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_11))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_12))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_13))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_14))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_15))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_0))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_1))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_2))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_3))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_4))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_5))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_6))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_7))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_8))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_9))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_10))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_11))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_12))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_13))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_14))
+                (portRef C (instanceRef BIU_CORE_eu_register_r3_d_15))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_0))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_1))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_2))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_3))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_4))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_5))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_6))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_7))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_8))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_9))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_10))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_11))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_12))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_13))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_14))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_15))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_0))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_1))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_2))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_3))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_4))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_5))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_6))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_7))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_8))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_9))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_10))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_11))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_12))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_13))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_14))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_15))
+                (portRef C (instanceRef BIU_CORE_nmi_d1_renamed_72))
+                (portRef C (instanceRef BIU_CORE_biu_done_int_renamed_71))
+                (portRef C (instanceRef BIU_CORE_pfq_write_renamed_70))
+                (portRef C (instanceRef BIU_CORE_ready_d1_renamed_69))
+                (portRef C (instanceRef BIU_CORE_eu_biu_req_d1_renamed_68))
+                (portRef C (instanceRef BIU_CORE_byte_num_renamed_67))
+                (portRef C (instanceRef BIU_CORE_intr_d1_renamed_66))
+                (portRef C (instanceRef BIU_CORE_AD_OE_renamed_65))
+                (portRef C (instanceRef BIU_CORE_dtr_int_renamed_64))
+                (portRef C (instanceRef BIU_CORE_clk_d1_renamed_63))
+                (portRef C (instanceRef BIU_CORE_inta_n_int_renamed_62))
+                (portRef C (instanceRef BIU_CORE_rd_n_int_renamed_61))
+                (portRef C (instanceRef BIU_CORE_wr_n_int_renamed_60))
+                (portRef C (instanceRef BIU_CORE_den_int_renamed_59))
+                (portRef C (instanceRef BIU_CORE_biu_state_0))
+                (portRef C (instanceRef BIU_CORE_biu_state_1))
+                (portRef C (instanceRef BIU_CORE_biu_state_2))
+                (portRef C (instanceRef BIU_CORE_biu_state_3))
+                (portRef C (instanceRef BIU_CORE_biu_state_4))
+                (portRef C (instanceRef BIU_CORE_biu_state_5))
+                (portRef C (instanceRef BIU_CORE_biu_state_6))
+                (portRef C (instanceRef BIU_CORE_biu_state_7))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_0_renamed_58))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_1_renamed_57))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_2_renamed_56))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_3_renamed_55))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_4_renamed_54))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_5_renamed_53))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_6_renamed_52))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_7_renamed_51))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_8_renamed_50))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_9_renamed_49))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_10_renamed_48))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_11_renamed_47))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_12_renamed_46))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_13_renamed_45))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_14_renamed_44))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_15_renamed_43))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_16_renamed_42))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_17_renamed_41))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_18_renamed_40))
+                (portRef C (instanceRef BIU_CORE_addr_out_temp_19_renamed_39))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_0_renamed_38))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_1_renamed_37))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_2_renamed_36))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_3_renamed_35))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_4_renamed_34))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_5_renamed_33))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_6_renamed_32))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_7_renamed_31))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_8_renamed_30))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_9_renamed_29))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_10_renamed_28))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_11_renamed_27))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_12_renamed_26))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_13_renamed_25))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_14_renamed_24))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_15_renamed_23))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_16_renamed_22))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_17_renamed_21))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_18_renamed_20))
+                (portRef C (instanceRef BIU_CORE_AD_OUT_19_renamed_19))
+                (portRef C (instanceRef BIU_CORE_clk_d2_renamed_18))
+                (portRef C (instanceRef BIU_CORE_nmi_d2_renamed_17))
+                (portRef C (instanceRef BIU_CORE_intr_d2_renamed_16))
+                (portRef C (instanceRef BIU_CORE_IOM_renamed_15))
+                (portRef C (instanceRef BIU_CORE_DTR_renamed_14))
+                (portRef C (instanceRef BIU_CORE_RD_n_renamed_13))
+                (portRef C (instanceRef BIU_CORE_INTA_n_renamed_12))
+                (portRef C (instanceRef BIU_CORE_WR_n_renamed_11))
+                (portRef C (instanceRef BIU_CORE_DEN_renamed_10))
+                (portRef C (instanceRef BIU_CORE_latched_data_in_0))
+                (portRef C (instanceRef BIU_CORE_latched_data_in_1))
+                (portRef C (instanceRef BIU_CORE_latched_data_in_2))
+                (portRef C (instanceRef BIU_CORE_latched_data_in_3))
+                (portRef C (instanceRef BIU_CORE_latched_data_in_4))
+                (portRef C (instanceRef BIU_CORE_latched_data_in_5))
+                (portRef C (instanceRef BIU_CORE_latched_data_in_6))
+                (portRef C (instanceRef BIU_CORE_latched_data_in_7))
+                (portRef C (instanceRef BIU_CORE_clk_d3_renamed_9))
+                (portRef C (instanceRef BIU_CORE_nmi_d3_renamed_8))
+                (portRef C (instanceRef BIU_CORE_intr_d3_renamed_7))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_0))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_1))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_2))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_3))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_4))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_5))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_6))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_7))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_8))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_9))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_10))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_11))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_12))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_13))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_14))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_d1_15))
+                (portRef C (instanceRef BIU_CORE_pfq_entry1_0))
+                (portRef C (instanceRef BIU_CORE_pfq_entry1_1))
+                (portRef C (instanceRef BIU_CORE_pfq_entry1_2))
+                (portRef C (instanceRef BIU_CORE_pfq_entry1_3))
+                (portRef C (instanceRef BIU_CORE_pfq_entry1_4))
+                (portRef C (instanceRef BIU_CORE_pfq_entry1_5))
+                (portRef C (instanceRef BIU_CORE_pfq_entry1_6))
+                (portRef C (instanceRef BIU_CORE_pfq_entry1_7))
+                (portRef C (instanceRef BIU_CORE_pfq_entry0_0))
+                (portRef C (instanceRef BIU_CORE_pfq_entry0_1))
+                (portRef C (instanceRef BIU_CORE_pfq_entry0_2))
+                (portRef C (instanceRef BIU_CORE_pfq_entry0_3))
+                (portRef C (instanceRef BIU_CORE_pfq_entry0_4))
+                (portRef C (instanceRef BIU_CORE_pfq_entry0_5))
+                (portRef C (instanceRef BIU_CORE_pfq_entry0_6))
+                (portRef C (instanceRef BIU_CORE_pfq_entry0_7))
+                (portRef C (instanceRef BIU_CORE_pfq_entry2_0))
+                (portRef C (instanceRef BIU_CORE_pfq_entry2_1))
+                (portRef C (instanceRef BIU_CORE_pfq_entry2_2))
+                (portRef C (instanceRef BIU_CORE_pfq_entry2_3))
+                (portRef C (instanceRef BIU_CORE_pfq_entry2_4))
+                (portRef C (instanceRef BIU_CORE_pfq_entry2_5))
+                (portRef C (instanceRef BIU_CORE_pfq_entry2_6))
+                (portRef C (instanceRef BIU_CORE_pfq_entry2_7))
+                (portRef C (instanceRef BIU_CORE_pfq_entry3_0))
+                (portRef C (instanceRef BIU_CORE_pfq_entry3_1))
+                (portRef C (instanceRef BIU_CORE_pfq_entry3_2))
+                (portRef C (instanceRef BIU_CORE_pfq_entry3_3))
+                (portRef C (instanceRef BIU_CORE_pfq_entry3_4))
+                (portRef C (instanceRef BIU_CORE_pfq_entry3_5))
+                (portRef C (instanceRef BIU_CORE_pfq_entry3_6))
+                (portRef C (instanceRef BIU_CORE_pfq_entry3_7))
+                (portRef C (instanceRef BIU_CORE_clk_d4_renamed_6))
+                (portRef C (instanceRef BIU_CORE_nmi_d4_renamed_5))
+                (portRef C (instanceRef BIU_CORE_ALE_renamed_4))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_0))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_1))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_2))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_3))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_4))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_5))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_6))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_7))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_8))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_9))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_10))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_11))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_12))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_13))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_14))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_15))
+                (portRef C (instanceRef BIU_CORE_s_bits_0))
+                (portRef C (instanceRef BIU_CORE_s_bits_1))
+                (portRef C (instanceRef BIU_CORE_s_bits_2))
+                (portRef C (instanceRef BIU_CORE_nmi_d5_renamed_3))
+                (portRef C (instanceRef BIU_CORE_pfq_top_byte_int_d1_0))
+                (portRef C (instanceRef BIU_CORE_pfq_top_byte_int_d1_1))
+                (portRef C (instanceRef BIU_CORE_pfq_top_byte_int_d1_2))
+                (portRef C (instanceRef BIU_CORE_pfq_top_byte_int_d1_3))
+                (portRef C (instanceRef BIU_CORE_pfq_top_byte_int_d1_4))
+                (portRef C (instanceRef BIU_CORE_pfq_top_byte_int_d1_5))
+                (portRef C (instanceRef BIU_CORE_pfq_top_byte_int_d1_6))
+                (portRef C (instanceRef BIU_CORE_pfq_top_byte_int_d1_7))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_0))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_1))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_2))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_3))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_4))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_5))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_6))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_7))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_8))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_9))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_10))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_11))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_12))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_13))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_14))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_in_15))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_0))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_1))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_2))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_3))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_4))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_5))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_6))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_7))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_8))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_9))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_10))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_11))
+                (portRef C (instanceRef BIU_CORE_clock_cycle_counter_12))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_0))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_1))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_2))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_3))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_4))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_5))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_6))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_7))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_8))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_9))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_10))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_11))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_12))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_13))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_14))
+                (portRef C (instanceRef BIU_CORE_pfq_addr_out_15))
+                (portRef C (instanceRef EU_CORE_biu_done_d1_renamed_258))
+                (portRef C (instanceRef EU_CORE_eu_stall_pipeline_renamed_257))
+                (portRef C (instanceRef EU_CORE_eu_add_carry_renamed_256))
+                (portRef C (instanceRef EU_CORE_eu_add_carry8_renamed_255))
+                (portRef C (instanceRef EU_CORE_eu_add_aux_carry_renamed_254))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_0))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_1))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_2))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_3))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_4))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_5))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_6))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_7))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_8))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_9))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_10))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_11))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_12))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_13))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_14))
+                (portRef C (instanceRef EU_CORE_eu_register_ax_15))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_0))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_1))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_2))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_3))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_4))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_5))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_6))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_7))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_8))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_9))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_10))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_11))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_12))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_13))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_14))
+                (portRef C (instanceRef EU_CORE_eu_register_bx_15))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_0))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_1))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_2))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_3))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_4))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_5))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_6))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_7))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_8))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_9))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_10))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_11))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_12))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_13))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_14))
+                (portRef C (instanceRef EU_CORE_eu_register_cx_15))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_0))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_1))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_2))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_3))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_4))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_5))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_6))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_7))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_8))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_9))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_10))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_11))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_12))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_13))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_14))
+                (portRef C (instanceRef EU_CORE_eu_register_dx_15))
+                (portRef C (instanceRef EU_CORE_eu_register_si_0))
+                (portRef C (instanceRef EU_CORE_eu_register_si_1))
+                (portRef C (instanceRef EU_CORE_eu_register_si_2))
+                (portRef C (instanceRef EU_CORE_eu_register_si_3))
+                (portRef C (instanceRef EU_CORE_eu_register_si_4))
+                (portRef C (instanceRef EU_CORE_eu_register_si_5))
+                (portRef C (instanceRef EU_CORE_eu_register_si_6))
+                (portRef C (instanceRef EU_CORE_eu_register_si_7))
+                (portRef C (instanceRef EU_CORE_eu_register_si_8))
+                (portRef C (instanceRef EU_CORE_eu_register_si_9))
+                (portRef C (instanceRef EU_CORE_eu_register_si_10))
+                (portRef C (instanceRef EU_CORE_eu_register_si_11))
+                (portRef C (instanceRef EU_CORE_eu_register_si_12))
+                (portRef C (instanceRef EU_CORE_eu_register_si_13))
+                (portRef C (instanceRef EU_CORE_eu_register_si_14))
+                (portRef C (instanceRef EU_CORE_eu_register_si_15))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_0))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_1))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_2))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_3))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_4))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_5))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_6))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_7))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_8))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_9))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_10))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_11))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_12))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_13))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_14))
+                (portRef C (instanceRef EU_CORE_eu_register_sp_15))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_0))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_1))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_2))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_3))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_4))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_5))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_6))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_7))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_8))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_9))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_10))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_11))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_12))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_13))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_14))
+                (portRef C (instanceRef EU_CORE_eu_register_bp_15))
+                (portRef C (instanceRef EU_CORE_eu_register_di_0))
+                (portRef C (instanceRef EU_CORE_eu_register_di_1))
+                (portRef C (instanceRef EU_CORE_eu_register_di_2))
+                (portRef C (instanceRef EU_CORE_eu_register_di_3))
+                (portRef C (instanceRef EU_CORE_eu_register_di_4))
+                (portRef C (instanceRef EU_CORE_eu_register_di_5))
+                (portRef C (instanceRef EU_CORE_eu_register_di_6))
+                (portRef C (instanceRef EU_CORE_eu_register_di_7))
+                (portRef C (instanceRef EU_CORE_eu_register_di_8))
+                (portRef C (instanceRef EU_CORE_eu_register_di_9))
+                (portRef C (instanceRef EU_CORE_eu_register_di_10))
+                (portRef C (instanceRef EU_CORE_eu_register_di_11))
+                (portRef C (instanceRef EU_CORE_eu_register_di_12))
+                (portRef C (instanceRef EU_CORE_eu_register_di_13))
+                (portRef C (instanceRef EU_CORE_eu_register_di_14))
+                (portRef C (instanceRef EU_CORE_eu_register_di_15))
+                (portRef C (instanceRef EU_CORE_eu_flags_0))
+                (portRef C (instanceRef EU_CORE_eu_flags_1))
+                (portRef C (instanceRef EU_CORE_eu_flags_2))
+                (portRef C (instanceRef EU_CORE_eu_flags_3))
+                (portRef C (instanceRef EU_CORE_eu_flags_4))
+                (portRef C (instanceRef EU_CORE_eu_flags_5))
+                (portRef C (instanceRef EU_CORE_eu_flags_6))
+                (portRef C (instanceRef EU_CORE_eu_flags_7))
+                (portRef C (instanceRef EU_CORE_eu_flags_8))
+                (portRef C (instanceRef EU_CORE_eu_flags_9))
+                (portRef C (instanceRef EU_CORE_eu_flags_10))
+                (portRef C (instanceRef EU_CORE_eu_flags_11))
+                (portRef C (instanceRef EU_CORE_eu_flags_12))
+                (portRef C (instanceRef EU_CORE_eu_flags_13))
+                (portRef C (instanceRef EU_CORE_eu_flags_14))
+                (portRef C (instanceRef EU_CORE_eu_flags_15))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_0))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_1))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_2))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_3))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_4))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_5))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_6))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_7))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_8))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_9))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_10))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_11))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_12))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_13))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_14))
+                (portRef C (instanceRef EU_CORE_eu_register_r3_15))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_0))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_1))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_2))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_3))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_4))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_5))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_6))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_7))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_8))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_9))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_10))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_11))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_12))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_13))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_14))
+                (portRef C (instanceRef EU_CORE_eu_register_r1_15))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_0))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_1))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_2))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_3))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_4))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_5))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_6))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_7))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_8))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_9))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_10))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_11))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_12))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_13))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_14))
+                (portRef C (instanceRef EU_CORE_eu_register_r2_15))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_0))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_1))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_2))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_3))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_4))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_5))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_6))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_7))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_8))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_9))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_10))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_11))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_12))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_13))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_14))
+                (portRef C (instanceRef EU_CORE_eu_biu_command_15))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_0))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_1))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_2))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_3))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_4))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_5))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_6))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_7))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_8))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_9))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_10))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_11))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_12))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_13))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_14))
+                (portRef C (instanceRef EU_CORE_eu_biu_dataout_15))
+                (portRef C (instanceRef EU_CORE_biu_done_d2_renamed_253))
+                (portRef C (instanceRef EU_CORE_eu_flag_t_d_renamed_252))
+                (portRef C (instanceRef EU_CORE_eu_add_overflow16_renamed_251))
+                (portRef C (instanceRef EU_CORE_eu_add_overflow8_renamed_250))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_0))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_1))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_2))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_3))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_4))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_5))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_6))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_7))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_8))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_9))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_10))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_11))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_12))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_13))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_14))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_15))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_16))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_17))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_18))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_19))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_20))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_21))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_22))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_23))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_24))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_25))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_26))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_27))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_28))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_29))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_30))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_31))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_32))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_33))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_34))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_35))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_36))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_37))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_38))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_39))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_40))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_41))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_42))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_43))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_44))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_45))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_46))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_47))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_48))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_49))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_50))
+                (portRef C (instanceRef EU_CORE_eu_calling_address_51))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_0))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_1))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_2))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_3))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_4))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_5))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_6))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_7))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_8))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_9))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_10))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_11))
+                (portRef C (instanceRef EU_CORE_eu_rom_address_12))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_0))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_1))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_2))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_3))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_4))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_5))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_6))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_7))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_8))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_9))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_10))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_11))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_12))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_13))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_14))
+                (portRef C (instanceRef EU_CORE_eu_alu_last_result_15))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_0))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_1))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_2))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_3))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_4))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_5))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_6))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_7))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_8))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_9))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_10))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_11))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_12))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_13))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_14))
+                (portRef C (instanceRef EU_CORE_eu_register_r0_15))
+                (portRef C (instanceRef t_reset_d4_renamed_374))
+                (portRef C (instanceRef BIU_CORE_eu_biu_req_caught_renamed_375))
+                (portRef C (instanceRef BIU_CORE_nmi_caught_renamed_376))
+                (portRef C (instanceRef EU_CORE_eu_tr_latched_renamed_377))
+                (portRef C (instanceRef EU_CORE_biu_done_caught_renamed_378))
+                (portRef C (instanceRef BIU_CORE_BIU_INTR_renamed_439))
+                (portRef C (instanceRef BIU_CORE_ale_int_renamed_440))
+                (portRef C (instanceRef BIU_CORE_iom_int_renamed_441))
+                (portRef C (instanceRef EU_CORE_intr_enable_delayed_renamed_443))
+                (portRef C (instanceRef led_go_left_renamed_444))
+                (portRef C (instanceRef BIU_CORE_word_cycle_renamed_445))
+                (portRef CLK (instanceRef Mshreg_t_biu_ad_oe_d2_renamed_463))
+                (portRef C (instanceRef t_biu_ad_oe_d2_renamed_464))
+                (portRef CLK (instanceRef Mshreg_t_reset_d2_renamed_465))
+                (portRef C (instanceRef t_reset_d2_renamed_466))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_15_renamed_467))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_15))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_14_renamed_468))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_14))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_13_renamed_469))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_13))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_12_renamed_470))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_12))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_11_renamed_471))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_11))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_10_renamed_472))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_10))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_9_renamed_473))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_9))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_8_renamed_474))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_8))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_7_renamed_475))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_7))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_6_renamed_476))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_6))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_3_renamed_477))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_3))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_5_renamed_478))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_5))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_4_renamed_479))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_4))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_2_renamed_480))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_2))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_1_renamed_481))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_1))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_0_renamed_482))
+                (portRef C (instanceRef BIU_CORE_biu_return_data_int_d2_0))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_15_renamed_483))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_15))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_12_renamed_484))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_12))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_14_renamed_485))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_14))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_13_renamed_486))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_13))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_11_renamed_487))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_11))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_10_renamed_488))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_10))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_9_renamed_489))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_9))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_8_renamed_490))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_8))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_5_renamed_491))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_5))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_7_renamed_492))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_7))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_6_renamed_493))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_6))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_4_renamed_494))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_4))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_3_renamed_495))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_3))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_2_renamed_496))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_2))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_1_renamed_497))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_1))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_14_renamed_498))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_14))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_0_renamed_499))
+                (portRef C (instanceRef BIU_CORE_biu_register_reg_d2_0))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_15_renamed_500))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_15))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_13_renamed_501))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_13))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_12_renamed_502))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_12))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_11_renamed_503))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_11))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_10_renamed_504))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_10))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_7_renamed_505))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_7))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_9_renamed_506))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_9))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_8_renamed_507))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_8))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_6_renamed_508))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_6))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_5_renamed_509))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_5))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_4_renamed_510))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_4))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_3_renamed_511))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_3))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_0_renamed_512))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_0))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_2_renamed_513))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_2))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_1_renamed_514))
+                (portRef C (instanceRef BIU_CORE_biu_register_rm_d2_1))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_15_renamed_515))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_15))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_14_renamed_516))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_14))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_13_renamed_517))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_13))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_12_renamed_518))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_12))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_9_renamed_519))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_9))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_11_renamed_520))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_11))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_10_renamed_521))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_10))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_8_renamed_522))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_8))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_7_renamed_523))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_7))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_6_renamed_524))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_6))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_5_renamed_525))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_5))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_4_renamed_526))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_4))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_3_renamed_527))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_3))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_2_renamed_528))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_2))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_1_renamed_529))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_1))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_0_renamed_530))
+                (portRef C (instanceRef BIU_CORE_biu_register_ds_d2_0))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_15_renamed_531))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_15))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_14_renamed_532))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_14))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_13_renamed_533))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_13))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_10_renamed_534))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_10))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_12_renamed_535))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_12))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_11_renamed_536))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_11))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_9_renamed_537))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_9))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_8_renamed_538))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_8))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_7_renamed_539))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_7))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_6_renamed_540))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_6))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_3_renamed_541))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_3))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_5_renamed_542))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_5))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_4_renamed_543))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_4))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_2_renamed_544))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_2))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_1_renamed_545))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_1))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_0_renamed_546))
+                (portRef C (instanceRef BIU_CORE_biu_register_ss_d2_0))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_15_renamed_547))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_15))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_12_renamed_548))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_12))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_14_renamed_549))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_14))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_13_renamed_550))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_13))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_11_renamed_551))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_11))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_10_renamed_552))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_10))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_9_renamed_553))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_9))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_8_renamed_554))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_8))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_5_renamed_555))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_5))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_7_renamed_556))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_7))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_6_renamed_557))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_6))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_4_renamed_558))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_4))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_3_renamed_559))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_3))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_2_renamed_560))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_2))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_1_renamed_561))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_1))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_14_renamed_562))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_14))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_0_renamed_563))
+                (portRef C (instanceRef BIU_CORE_biu_register_es_d2_0))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_15_renamed_564))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_15))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_13_renamed_565))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_13))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_12_renamed_566))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_12))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_11_renamed_567))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_11))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_10_renamed_568))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_10))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_7_renamed_569))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_7))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_9_renamed_570))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_9))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_8_renamed_571))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_8))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_6_renamed_572))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_6))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_5_renamed_573))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_5))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_4_renamed_574))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_4))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_3_renamed_575))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_3))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_0_renamed_576))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_0))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_2_renamed_577))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_2))
+                (portRef CLK (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_1_renamed_578))
+                (portRef C (instanceRef BIU_CORE_biu_register_cs_d2_1))
+                (portRef clka (instanceRef EU_CORE_EU4Kx32_i))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_19 "BIU_CORE/AD_OUT_19")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_19))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_19_renamed_19))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_19_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_18 "BIU_CORE/AD_OUT_18")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_18))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_18_renamed_20))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_18_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_17 "BIU_CORE/AD_OUT_17")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_17))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_17_renamed_21))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_17_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_16 "BIU_CORE/AD_OUT_16")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_16))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_16_renamed_22))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_16_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_15 "BIU_CORE/AD_OUT_15")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_15))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_15_renamed_23))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_15_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_14 "BIU_CORE/AD_OUT_14")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_14))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_14_renamed_24))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_14_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_13 "BIU_CORE/AD_OUT_13")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_13))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_13_renamed_25))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_13_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_12 "BIU_CORE/AD_OUT_12")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_12))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_12_renamed_26))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_12_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_11 "BIU_CORE/AD_OUT_11")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_11))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_11_renamed_27))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_11_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_10 "BIU_CORE/AD_OUT_10")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_10))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_10_renamed_28))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_10_1_renamed_260))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_9 "BIU_CORE/AD_OUT_9")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_9))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_9_renamed_29))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_9_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_8 "BIU_CORE/AD_OUT_8")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_8))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_8_renamed_30))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_8_1))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_7 "BIU_CORE/AD_OUT_7")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_7))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_7_renamed_31))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_7__))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_6 "BIU_CORE/AD_OUT_6")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_6))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_6_renamed_32))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_6__))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_5 "BIU_CORE/AD_OUT_5")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_5))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_5_renamed_33))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_5__))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_4 "BIU_CORE/AD_OUT_4")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_4))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_4_renamed_34))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_4__))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_3 "BIU_CORE/AD_OUT_3")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_3))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_3_renamed_35))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_3__))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_2 "BIU_CORE/AD_OUT_2")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_2))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_2_renamed_36))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_2__))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_1 "BIU_CORE/AD_OUT_1")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_1))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_1_renamed_37))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_1__))
+              )
+            )
+            (net (rename BIU_CORE_AD_OUT_0 "BIU_CORE/AD_OUT_0")
+              (joined
+                (portRef D (instanceRef t_biu_ad_out_d_0))
+                (portRef Q (instanceRef BIU_CORE_AD_OUT_0_renamed_38))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_d1_7_ "BIU_CORE/pfq_top_byte_int_d1<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_top_byte_int_d1_7))
+                (portRef I2 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT221_renamed_338))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT222))
+                (portRef I3 (instanceRef EU_CORE_mux13_51_renamed_169))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_d1_6_ "BIU_CORE/pfq_top_byte_int_d1<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_top_byte_int_d1_6))
+                (portRef I2 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT201_renamed_337))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT202))
+                (portRef I3 (instanceRef EU_CORE_mux12_51_renamed_181))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_d1_5_ "BIU_CORE/pfq_top_byte_int_d1<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_top_byte_int_d1_5))
+                (portRef I2 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT181_renamed_336))
+                (portRef I3 (instanceRef EU_CORE_mux11_51_renamed_187))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_d1_4_ "BIU_CORE/pfq_top_byte_int_d1<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_top_byte_int_d1_4))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT161_renamed_351))
+                (portRef I3 (instanceRef EU_CORE_mux10_51_renamed_193))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_d1_3_ "BIU_CORE/pfq_top_byte_int_d1<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_top_byte_int_d1_3))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT141_renamed_349))
+                (portRef I3 (instanceRef EU_CORE_mux9_51_renamed_199))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_d1_2_ "BIU_CORE/pfq_top_byte_int_d1<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_top_byte_int_d1_2))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT182))
+                (portRef I2 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT121_renamed_353))
+                (portRef I3 (instanceRef EU_CORE_mux8_51_renamed_205))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_d1_1_ "BIU_CORE/pfq_top_byte_int_d1<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_top_byte_int_d1_1))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT162))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT101_renamed_352))
+                (portRef I3 (instanceRef EU_CORE_mux7_51_renamed_211))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_d1_0_ "BIU_CORE/pfq_top_byte_int_d1<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_top_byte_int_d1_0))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT142_renamed_350))
+                (portRef I2 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT21_renamed_354))
+                (portRef I3 (instanceRef EU_CORE_mux_51_renamed_247))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_15_ "BIU_CORE/pfq_addr_out_d1<15>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_15))
+                (portRef I0 (instanceRef EU_CORE_mux6_71_renamed_216))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_14_ "BIU_CORE/pfq_addr_out_d1<14>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_14))
+                (portRef I0 (instanceRef EU_CORE_mux5_71_renamed_220))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_13_ "BIU_CORE/pfq_addr_out_d1<13>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_13))
+                (portRef I0 (instanceRef EU_CORE_mux4_5_renamed_223))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_12_ "BIU_CORE/pfq_addr_out_d1<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_12))
+                (portRef I0 (instanceRef EU_CORE_mux3_5_renamed_229))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_11_ "BIU_CORE/pfq_addr_out_d1<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_11))
+                (portRef I0 (instanceRef EU_CORE_mux2_5_renamed_235))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_10_ "BIU_CORE/pfq_addr_out_d1<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_10))
+                (portRef I0 (instanceRef EU_CORE_mux1_71_renamed_242))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_9_ "BIU_CORE/pfq_addr_out_d1<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_9))
+                (portRef I0 (instanceRef EU_CORE_mux15_5_renamed_173))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_8_ "BIU_CORE/pfq_addr_out_d1<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_8))
+                (portRef I0 (instanceRef EU_CORE_mux14_5_renamed_161))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_7_ "BIU_CORE/pfq_addr_out_d1<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_7))
+                (portRef I0 (instanceRef EU_CORE_mux13_5_renamed_167))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_6_ "BIU_CORE/pfq_addr_out_d1<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_6))
+                (portRef I0 (instanceRef EU_CORE_mux12_5_renamed_179))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_5_ "BIU_CORE/pfq_addr_out_d1<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_5))
+                (portRef I0 (instanceRef EU_CORE_mux11_5_renamed_185))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_4_ "BIU_CORE/pfq_addr_out_d1<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_4))
+                (portRef I0 (instanceRef EU_CORE_mux10_5_renamed_191))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_3_ "BIU_CORE/pfq_addr_out_d1<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_3))
+                (portRef I0 (instanceRef EU_CORE_mux9_5_renamed_197))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_2_ "BIU_CORE/pfq_addr_out_d1<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_2))
+                (portRef I0 (instanceRef EU_CORE_mux8_5_renamed_203))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_1_ "BIU_CORE/pfq_addr_out_d1<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_1))
+                (portRef I0 (instanceRef EU_CORE_mux7_5_renamed_209))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_d1_0_ "BIU_CORE/pfq_addr_out_d1<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_d1_0))
+                (portRef I0 (instanceRef EU_CORE_mux_5_renamed_245))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_15_ "BIU_CORE/biu_register_es_d2<15>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux6_6_renamed_214))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_14_ "BIU_CORE/biu_register_es_d2<14>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux5_6_renamed_218))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_13_ "BIU_CORE/biu_register_es_d2<13>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux4_6_renamed_226))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_12_ "BIU_CORE/biu_register_es_d2<12>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux3_6_renamed_232))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_11_ "BIU_CORE/biu_register_es_d2<11>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux2_6_renamed_238))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_10_ "BIU_CORE/biu_register_es_d2<10>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux1_6_renamed_240))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_9_ "BIU_CORE/biu_register_es_d2<9>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux15_6_renamed_176))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_8_ "BIU_CORE/biu_register_es_d2<8>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux14_6_renamed_164))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_7_ "BIU_CORE/biu_register_es_d2<7>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux13_6_renamed_170))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_6_ "BIU_CORE/biu_register_es_d2<6>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux12_6_renamed_182))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_5_ "BIU_CORE/biu_register_es_d2<5>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux11_6_renamed_188))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_4_ "BIU_CORE/biu_register_es_d2<4>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux10_6_renamed_194))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_3_ "BIU_CORE/biu_register_es_d2<3>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux9_6_renamed_200))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_2_ "BIU_CORE/biu_register_es_d2<2>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux8_6_renamed_206))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_1_ "BIU_CORE/biu_register_es_d2<1>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux7_6_renamed_212))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_d2_0_ "BIU_CORE/biu_register_es_d2<0>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux_6_renamed_248))
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_15_ "BIU_CORE/biu_register_ss_d2<15>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux6_6_renamed_214))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_14_ "BIU_CORE/biu_register_ss_d2<14>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux5_6_renamed_218))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_13_ "BIU_CORE/biu_register_ss_d2<13>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux4_6_renamed_226))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_12_ "BIU_CORE/biu_register_ss_d2<12>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux3_6_renamed_232))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_11_ "BIU_CORE/biu_register_ss_d2<11>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux2_6_renamed_238))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_10_ "BIU_CORE/biu_register_ss_d2<10>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux1_6_renamed_240))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_9_ "BIU_CORE/biu_register_ss_d2<9>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux15_6_renamed_176))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_8_ "BIU_CORE/biu_register_ss_d2<8>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux14_6_renamed_164))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_7_ "BIU_CORE/biu_register_ss_d2<7>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux13_6_renamed_170))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_6_ "BIU_CORE/biu_register_ss_d2<6>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux12_6_renamed_182))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_5_ "BIU_CORE/biu_register_ss_d2<5>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux11_6_renamed_188))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_4_ "BIU_CORE/biu_register_ss_d2<4>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux10_6_renamed_194))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_3_ "BIU_CORE/biu_register_ss_d2<3>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux9_6_renamed_200))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_2_ "BIU_CORE/biu_register_ss_d2<2>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux8_6_renamed_206))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_1_ "BIU_CORE/biu_register_ss_d2<1>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux7_6_renamed_212))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_d2_0_ "BIU_CORE/biu_register_ss_d2<0>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux_6_renamed_248))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_15_ "BIU_CORE/biu_register_cs_d2<15>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux6_6_renamed_214))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_14_ "BIU_CORE/biu_register_cs_d2<14>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux5_6_renamed_218))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_13_ "BIU_CORE/biu_register_cs_d2<13>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux4_6_renamed_226))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_12_ "BIU_CORE/biu_register_cs_d2<12>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux3_6_renamed_232))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_11_ "BIU_CORE/biu_register_cs_d2<11>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux2_6_renamed_238))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_10_ "BIU_CORE/biu_register_cs_d2<10>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux1_6_renamed_240))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_9_ "BIU_CORE/biu_register_cs_d2<9>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux15_6_renamed_176))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_8_ "BIU_CORE/biu_register_cs_d2<8>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux14_6_renamed_164))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_7_ "BIU_CORE/biu_register_cs_d2<7>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux13_6_renamed_170))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_6_ "BIU_CORE/biu_register_cs_d2<6>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux12_6_renamed_182))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_5_ "BIU_CORE/biu_register_cs_d2<5>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux11_6_renamed_188))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_4_ "BIU_CORE/biu_register_cs_d2<4>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux10_6_renamed_194))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_3_ "BIU_CORE/biu_register_cs_d2<3>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux9_6_renamed_200))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_2_ "BIU_CORE/biu_register_cs_d2<2>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux8_6_renamed_206))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_1_ "BIU_CORE/biu_register_cs_d2<1>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux7_6_renamed_212))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_d2_0_ "BIU_CORE/biu_register_cs_d2<0>")
+              (joined
+                (portRef I3 (instanceRef EU_CORE_mux_6_renamed_248))
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_15_ "BIU_CORE/biu_register_ds_d2<15>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux6_6_renamed_214))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_14_ "BIU_CORE/biu_register_ds_d2<14>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux5_6_renamed_218))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_13_ "BIU_CORE/biu_register_ds_d2<13>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux4_6_renamed_226))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_12_ "BIU_CORE/biu_register_ds_d2<12>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux3_6_renamed_232))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_11_ "BIU_CORE/biu_register_ds_d2<11>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux2_6_renamed_238))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_10_ "BIU_CORE/biu_register_ds_d2<10>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux1_6_renamed_240))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_9_ "BIU_CORE/biu_register_ds_d2<9>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux15_6_renamed_176))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_8_ "BIU_CORE/biu_register_ds_d2<8>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux14_6_renamed_164))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_7_ "BIU_CORE/biu_register_ds_d2<7>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux13_6_renamed_170))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_6_ "BIU_CORE/biu_register_ds_d2<6>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux12_6_renamed_182))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_5_ "BIU_CORE/biu_register_ds_d2<5>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux11_6_renamed_188))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_4_ "BIU_CORE/biu_register_ds_d2<4>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux10_6_renamed_194))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_3_ "BIU_CORE/biu_register_ds_d2<3>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux9_6_renamed_200))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_2_ "BIU_CORE/biu_register_ds_d2<2>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux8_6_renamed_206))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_1_ "BIU_CORE/biu_register_ds_d2<1>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux7_6_renamed_212))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_d2_0_ "BIU_CORE/biu_register_ds_d2<0>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux_6_renamed_248))
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_15_ "BIU_CORE/biu_register_rm_d2<15>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux6_7_renamed_215))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_14_ "BIU_CORE/biu_register_rm_d2<14>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux5_7_renamed_219))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_13_ "BIU_CORE/biu_register_rm_d2<13>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux4_51_renamed_225))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_12_ "BIU_CORE/biu_register_rm_d2<12>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux3_51_renamed_231))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_11_ "BIU_CORE/biu_register_rm_d2<11>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux2_51_renamed_237))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_10_ "BIU_CORE/biu_register_rm_d2<10>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux1_7_renamed_241))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_9_ "BIU_CORE/biu_register_rm_d2<9>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux15_51_renamed_175))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_8_ "BIU_CORE/biu_register_rm_d2<8>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux14_51_renamed_163))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_7_ "BIU_CORE/biu_register_rm_d2<7>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux13_51_renamed_169))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_6_ "BIU_CORE/biu_register_rm_d2<6>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux12_51_renamed_181))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_5_ "BIU_CORE/biu_register_rm_d2<5>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux11_51_renamed_187))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_4_ "BIU_CORE/biu_register_rm_d2<4>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux10_51_renamed_193))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_3_ "BIU_CORE/biu_register_rm_d2<3>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux9_51_renamed_199))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_2_ "BIU_CORE/biu_register_rm_d2<2>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux8_51_renamed_205))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_1_ "BIU_CORE/biu_register_rm_d2<1>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux7_51_renamed_211))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_d2_0_ "BIU_CORE/biu_register_rm_d2<0>")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_mux_51_renamed_247))
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_15_ "BIU_CORE/biu_register_reg_d2<15>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux6_7_renamed_215))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_14_ "BIU_CORE/biu_register_reg_d2<14>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux5_7_renamed_219))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_13_ "BIU_CORE/biu_register_reg_d2<13>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux4_51_renamed_225))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_12_ "BIU_CORE/biu_register_reg_d2<12>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux3_51_renamed_231))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_11_ "BIU_CORE/biu_register_reg_d2<11>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux2_51_renamed_237))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_10_ "BIU_CORE/biu_register_reg_d2<10>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux1_7_renamed_241))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_9_ "BIU_CORE/biu_register_reg_d2<9>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux15_51_renamed_175))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_8_ "BIU_CORE/biu_register_reg_d2<8>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux14_51_renamed_163))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_7_ "BIU_CORE/biu_register_reg_d2<7>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux13_51_renamed_169))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_6_ "BIU_CORE/biu_register_reg_d2<6>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux12_51_renamed_181))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_5_ "BIU_CORE/biu_register_reg_d2<5>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux11_51_renamed_187))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_4_ "BIU_CORE/biu_register_reg_d2<4>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux10_51_renamed_193))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_3_ "BIU_CORE/biu_register_reg_d2<3>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux9_51_renamed_199))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_2_ "BIU_CORE/biu_register_reg_d2<2>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux8_51_renamed_205))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_1_ "BIU_CORE/biu_register_reg_d2<1>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux7_51_renamed_211))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_d2_0_ "BIU_CORE/biu_register_reg_d2<0>")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux_51_renamed_247))
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_15_ "BIU_CORE/biu_return_data_int_d2<15>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux6_7_renamed_215))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_14_ "BIU_CORE/biu_return_data_int_d2<14>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux5_7_renamed_219))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_13_ "BIU_CORE/biu_return_data_int_d2<13>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux4_51_renamed_225))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_12_ "BIU_CORE/biu_return_data_int_d2<12>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux3_51_renamed_231))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_11_ "BIU_CORE/biu_return_data_int_d2<11>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux2_51_renamed_237))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_10_ "BIU_CORE/biu_return_data_int_d2<10>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux1_7_renamed_241))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_9_ "BIU_CORE/biu_return_data_int_d2<9>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux15_51_renamed_175))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_8_ "BIU_CORE/biu_return_data_int_d2<8>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux14_51_renamed_163))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_7_ "BIU_CORE/biu_return_data_int_d2<7>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux13_51_renamed_169))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_6_ "BIU_CORE/biu_return_data_int_d2<6>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux12_51_renamed_181))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_5_ "BIU_CORE/biu_return_data_int_d2<5>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux11_51_renamed_187))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_4_ "BIU_CORE/biu_return_data_int_d2<4>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux10_51_renamed_193))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_3_ "BIU_CORE/biu_return_data_int_d2<3>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux9_51_renamed_199))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_2_ "BIU_CORE/biu_return_data_int_d2<2>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux8_51_renamed_205))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_1_ "BIU_CORE/biu_return_data_int_d2<1>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux7_51_renamed_211))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_d2_0_ "BIU_CORE/biu_return_data_int_d2<0>")
+              (joined
+                (portRef I1 (instanceRef EU_CORE_mux_51_renamed_247))
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_INTA_n "BIU_CORE/INTA_n")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_INTA_n_renamed_12))
+                (portRef I (instanceRef INTA_n_OBUF))
+              )
+            )
+            (net (rename BIU_CORE_ALE "BIU_CORE/ALE")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_ALE_renamed_4))
+                (portRef I (instanceRef ALE_OBUF))
+              )
+            )
+            (net (rename BIU_CORE_RD_n "BIU_CORE/RD_n")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_RD_n_renamed_13))
+                (portRef I (instanceRef RD_n_OBUF))
+              )
+            )
+            (net (rename BIU_CORE_WR_n "BIU_CORE/WR_n")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_WR_n_renamed_11))
+                (portRef I (instanceRef WR_n_OBUF))
+              )
+            )
+            (net (rename BIU_CORE_s_bits_0_ "BIU_CORE/s_bits<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_s_bits_0))
+                (portRef I2 (instanceRef BIU_CORE__n07981))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT11))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT12))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o1_renamed_264))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o3_renamed_266))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_198_o_SW0))
+                (portRef I (instanceRef SSO_n_OBUF))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o_SW0_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__rd_n_int_Select_200_o_SW0_SW0))
+                (portRef I2 (instanceRef BIU_CORE_s_bits_2__word_cycle_AND_36_o1))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT21))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT31))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT41))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT51))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT61))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT71))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT151))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT161))
+              )
+            )
+            (net (rename BIU_CORE_IOM "BIU_CORE/IOM")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_IOM_renamed_15))
+                (portRef I (instanceRef IOM_OBUF))
+              )
+            )
+            (net (rename BIU_CORE_DTR "BIU_CORE/DTR")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_DTR_renamed_14))
+                (portRef I (instanceRef DTR_OBUF))
+              )
+            )
+            (net (rename BIU_CORE_DEN "BIU_CORE/DEN")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_DEN_renamed_10))
+                (portRef I (instanceRef DEN_OBUF))
+              )
+            )
+            (net (rename BIU_CORE_AD_OE "BIU_CORE/AD_OE")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_AD_OE_renamed_65))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_192_o1))
+                (portRef D (instanceRef Mshreg_t_biu_ad_oe_d2_renamed_463))
+              )
+            )
+            (net (rename BIU_CORE_biu_done_int "BIU_CORE/biu_done_int")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_done_int_renamed_71))
+                (portRef D (instanceRef EU_CORE_biu_done_d1_renamed_258))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_186_o_renamed_268))
+                (portRef I1 (instanceRef BIU_CORE_eu_biu_req_caught_glue_set_renamed_452))
+              )
+            )
+            (net t_biu_clk_counter_zero
+              (joined
+                (portRef O (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_3))
+                (portRef I2 (instanceRef EU_CORE_mux19_4_renamed_138))
+                (portRef I3 (instanceRef EU_CORE_mux3_4_renamed_228))
+              )
+            )
+            (net (rename BIU_CORE_nmi_caught "BIU_CORE/nmi_caught")
+              (joined
+                (portRef I2 (instanceRef EU_CORE_mux9_4_renamed_196))
+                (portRef Q (instanceRef BIU_CORE_nmi_caught_renamed_376))
+                (portRef I4 (instanceRef BIU_CORE_nmi_caught_glue_set_renamed_453))
+                (portRef I2 (instanceRef EU_CORE_mux25_4_renamed_107))
+              )
+            )
+            (net (rename BIU_CORE_BIU_INTR "BIU_CORE/BIU_INTR")
+              (joined
+                (portRef I0 (instanceRef EU_CORE_intr_asserted1))
+                (portRef Q (instanceRef BIU_CORE_BIU_INTR_renamed_439))
+                (portRef I0 (instanceRef BIU_CORE_BIU_INTR_rstpot_renamed_459))
+                (portRef I2 (instanceRef EU_CORE_mux23_4_renamed_446))
+              )
+            )
+            (net t_pfq_empty
+              (joined
+                (portRef I1 (instanceRef BIU_CORE__n1017_inv1))
+                (portRef O (instanceRef BIU_CORE_pfq_empty1))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_15_ "EU_CORE/eu_biu_command<15>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_15))
+                (portRef I0 (instanceRef EU_CORE_mux22_8_renamed_127))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_14_ "EU_CORE/eu_biu_command<14>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_14))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_biu_segment11))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_biu_segment21))
+                (portRef I1 (instanceRef EU_CORE_mux21_8_renamed_131))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_13_ "EU_CORE/eu_biu_command<13>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_13))
+                (portRef I3 (instanceRef BIU_CORE__n0996_inv1))
+                (portRef I3 (instanceRef BIU_CORE__n1012_inv1))
+                (portRef I3 (instanceRef BIU_CORE__n1008_inv1))
+                (portRef I3 (instanceRef BIU_CORE__n1071_inv1))
+                (portRef I3 (instanceRef BIU_CORE__n1004_inv1))
+                (portRef I3 (instanceRef BIU_CORE__n1000_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n1017_inv1))
+                (portRef I1 (instanceRef BIU_CORE_eu_biu_strobe_1__PWR_6_o_equal_67_o_1_1))
+                (portRef I3 (instanceRef BIU_CORE__n1014_inv1))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_0__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_1__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_2__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_3__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_4__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_5__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_6__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_7__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_8__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_9__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_10__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_11__))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_12__))
+                (portRef I2 (instanceRef EU_CORE_mux20_4_renamed_132))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_12_ "EU_CORE/eu_biu_command<12>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_12))
+                (portRef I1 (instanceRef EU_CORE_mux19_4_renamed_138))
+                (portRef I4 (instanceRef BIU_CORE__n0996_inv1))
+                (portRef I4 (instanceRef BIU_CORE__n1012_inv1))
+                (portRef I4 (instanceRef BIU_CORE__n1008_inv1))
+                (portRef I4 (instanceRef BIU_CORE__n1071_inv1))
+                (portRef I4 (instanceRef BIU_CORE__n1004_inv1))
+                (portRef I4 (instanceRef BIU_CORE__n1000_inv1))
+                (portRef I2 (instanceRef BIU_CORE__n1017_inv1))
+                (portRef I0 (instanceRef BIU_CORE_eu_biu_strobe_1__PWR_6_o_equal_67_o_1_1))
+                (portRef I2 (instanceRef BIU_CORE__n1014_inv1))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_0__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_1__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_2__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_3__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_4__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_5__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_6__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_7__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_8__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_9__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_10__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_11__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_12__))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_11_ "EU_CORE/eu_biu_command<11>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_11))
+                (portRef I1 (instanceRef EU_CORE_mux18_4_renamed_144))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_biu_segment21))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_10_ "EU_CORE/eu_biu_command<10>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_10))
+                (portRef I0 (instanceRef EU_CORE_mux17_8_renamed_153))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_biu_segment11))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_9_ "EU_CORE/eu_biu_command<9>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_biu_req_d1_renamed_68))
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_9))
+                (portRef I2 (instanceRef BIU_CORE_eu_biu_req_caught_glue_set_renamed_452))
+                (portRef I1 (instanceRef EU_CORE_biu_done_caught_glue_set_renamed_461))
+                (portRef I2 (instanceRef EU_CORE_mux31_4_renamed_73))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_8_ "EU_CORE/eu_biu_command<8>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_8))
+                (portRef I2 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_15_o1))
+                (portRef I3 (instanceRef BIU_CORE_eu_biu_req_code_4__PWR_6_o_equal_108_o_4_1))
+                (portRef I3 (instanceRef BIU_CORE__n10811))
+                (portRef I0 (instanceRef BIU_CORE_eu_biu_req_code_4__INV_33_o1))
+                (portRef I3 (instanceRef BIU_CORE_out1))
+                (portRef I4 (instanceRef BIU_CORE__n10841))
+                (portRef I2 (instanceRef BIU_CORE__n10921))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT32))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT11))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT21))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_21_SW1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_3_SW1))
+                (portRef I4 (instanceRef BIU_CORE_eu_biu_req_code_4__GND_14_o_select_117_OUT_0_11))
+                (portRef I4 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_15_o_inv1))
+                (portRef I2 (instanceRef EU_CORE_mux30_4_renamed_91))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_7_ "EU_CORE/eu_biu_command<7>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_7))
+                (portRef I1 (instanceRef EU_CORE_mux29_4_renamed_79))
+                (portRef I1 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_15_o1))
+                (portRef I4 (instanceRef BIU_CORE_eu_biu_req_code_4__PWR_6_o_equal_108_o_4_1))
+                (portRef I2 (instanceRef BIU_CORE__n10811))
+                (portRef I4 (instanceRef BIU_CORE_eu_biu_req_code_4__INV_33_o1))
+                (portRef I1 (instanceRef BIU_CORE_out1))
+                (portRef I1 (instanceRef BIU_CORE__n10841))
+                (portRef I1 (instanceRef BIU_CORE__n10921))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT31_renamed_262))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT32))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT11))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT21))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_21_SW1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_3_SW1))
+                (portRef I1 (instanceRef BIU_CORE_eu_biu_req_code_4__GND_14_o_select_117_OUT_0_11))
+                (portRef I1 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_15_o_inv1))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_6_ "EU_CORE/eu_biu_command<6>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_6))
+                (portRef I2 (instanceRef BIU_CORE__n0996_inv1))
+                (portRef I1 (instanceRef BIU_CORE__n1012_inv1))
+                (portRef I1 (instanceRef BIU_CORE__n1008_inv1))
+                (portRef I2 (instanceRef BIU_CORE__n1071_inv1))
+                (portRef I2 (instanceRef BIU_CORE__n1004_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n1000_inv1))
+                (portRef I3 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_15_o1))
+                (portRef I2 (instanceRef BIU_CORE_eu_biu_req_code_4__PWR_6_o_equal_108_o_4_1))
+                (portRef I1 (instanceRef BIU_CORE__n10811))
+                (portRef I3 (instanceRef BIU_CORE_eu_biu_req_code_4__INV_33_o1))
+                (portRef I2 (instanceRef BIU_CORE_out1))
+                (portRef I2 (instanceRef BIU_CORE__n10841))
+                (portRef I4 (instanceRef BIU_CORE__n10921))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT31_renamed_262))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT32))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT11))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT21))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_21_SW1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_3_SW1))
+                (portRef I3 (instanceRef BIU_CORE_eu_biu_req_code_4__GND_14_o_select_117_OUT_0_11))
+                (portRef I3 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_15_o_inv1))
+                (portRef I2 (instanceRef EU_CORE_mux28_4_renamed_85))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_5_ "EU_CORE/eu_biu_command<5>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_5))
+                (portRef I1 (instanceRef EU_CORE_mux27_8_renamed_100))
+                (portRef I1 (instanceRef BIU_CORE__n0996_inv1))
+                (portRef I2 (instanceRef BIU_CORE__n1012_inv1))
+                (portRef I2 (instanceRef BIU_CORE__n1008_inv1))
+                (portRef I1 (instanceRef BIU_CORE__n1071_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n1004_inv1))
+                (portRef I2 (instanceRef BIU_CORE__n1000_inv1))
+                (portRef I4 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_15_o1))
+                (portRef I1 (instanceRef BIU_CORE_eu_biu_req_code_4__PWR_6_o_equal_108_o_4_1))
+                (portRef I4 (instanceRef BIU_CORE__n10811))
+                (portRef I2 (instanceRef BIU_CORE_eu_biu_req_code_4__INV_33_o1))
+                (portRef I4 (instanceRef BIU_CORE_out1))
+                (portRef I3 (instanceRef BIU_CORE__n10841))
+                (portRef I0 (instanceRef BIU_CORE__n10921))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT31_renamed_262))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT11))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT21))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_21_SW1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_3_SW1))
+                (portRef I2 (instanceRef BIU_CORE_eu_biu_req_code_4__GND_14_o_select_117_OUT_0_11))
+                (portRef I2 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_15_o_inv1))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_4_ "EU_CORE/eu_biu_command<4>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_4))
+                (portRef I0 (instanceRef BIU_CORE__n0996_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n1012_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n1008_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n1071_inv1))
+                (portRef I1 (instanceRef BIU_CORE__n1004_inv1))
+                (portRef I1 (instanceRef BIU_CORE__n1000_inv1))
+                (portRef I5 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_15_o1))
+                (portRef I0 (instanceRef BIU_CORE_eu_biu_req_code_4__PWR_6_o_equal_108_o_4_1))
+                (portRef I0 (instanceRef BIU_CORE__n10811))
+                (portRef I1 (instanceRef BIU_CORE_eu_biu_req_code_4__INV_33_o1))
+                (portRef I0 (instanceRef BIU_CORE_out1))
+                (portRef I0 (instanceRef BIU_CORE__n10841))
+                (portRef I3 (instanceRef BIU_CORE__n10921))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT31_renamed_262))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT32))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT11))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT21))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_21_SW1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_3_renamed_457))
+                (portRef I0 (instanceRef BIU_CORE_eu_biu_req_code_4__GND_14_o_select_117_OUT_0_11))
+                (portRef I5 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_15_o_inv1))
+                (portRef I2 (instanceRef EU_CORE_mux26_4_renamed_101))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_3_ "EU_CORE/eu_biu_command<3>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_3))
+                (portRef I0 (instanceRef EU_CORE_mux25_4_renamed_107))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_2_ "EU_CORE/eu_biu_command<2>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_2))
+                (portRef I0 (instanceRef EU_CORE_mux24_4_renamed_113))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_1_ "EU_CORE/eu_biu_command<1>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_1))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_biu_segment21))
+                (portRef I0 (instanceRef EU_CORE_mux23_4_renamed_446))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_command_0_ "EU_CORE/eu_biu_command<0>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_biu_command_0))
+                (portRef I1 (instanceRef EU_CORE_mux16_4_renamed_154))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_biu_segment11))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_15_ "EU_CORE/eu_biu_dataout<15>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_15))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_15))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_15))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_15))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_15))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_15))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_15))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_7__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_14_ "EU_CORE/eu_biu_dataout<14>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_14))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_14))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_14))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_14))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_14))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_14))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_14))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_6__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_13_ "EU_CORE/eu_biu_dataout<13>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_13))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_13))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_13))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_13))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_13))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_13))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_13))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_5__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_12_ "EU_CORE/eu_biu_dataout<12>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_12))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_12))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_12))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_12))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_12))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_12))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_12))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_12__))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_4__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_11_ "EU_CORE/eu_biu_dataout<11>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_11))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_11))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_11))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_11))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_11))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_11))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_11))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_11__))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_3__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_10_ "EU_CORE/eu_biu_dataout<10>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_10))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_10))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_10))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_10))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_10))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_10))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_10))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_10__))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_2__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_9_ "EU_CORE/eu_biu_dataout<9>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_9))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_9))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_9))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_9))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_9))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_9))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_9))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_9__))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_1__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_8_ "EU_CORE/eu_biu_dataout<8>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_8))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_8))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_8))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_8))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_8))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_8))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_8))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_8__))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_7_ "EU_CORE/eu_biu_dataout<7>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_7))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_7))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_7))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_7))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_7))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_7))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_7))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_7__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_7__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_6_ "EU_CORE/eu_biu_dataout<6>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_6))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_6))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_6))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_6))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_6))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_6))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_6))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_6__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_6__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_5_ "EU_CORE/eu_biu_dataout<5>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_5))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_5))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_5))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_5))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_5))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_5))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_5))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT122))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_5__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_5__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_4_ "EU_CORE/eu_biu_dataout<4>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_4))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_4))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_4))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_4))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_4))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_4))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_4))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT102))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_4__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_4__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_3_ "EU_CORE/eu_biu_dataout<3>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_3))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_3))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_3))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_3))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_3))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_3))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_3))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT181_renamed_336))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT162))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT22_renamed_355))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_3__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_3__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_2_ "EU_CORE/eu_biu_dataout<2>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_2))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_2))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_2))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_2))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_2))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_2))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_2))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT142_renamed_350))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT161_renamed_351))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_2__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_2__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_1_ "EU_CORE/eu_biu_dataout<1>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_1))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_1))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_1))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_1))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_1))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_1))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_1))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT141_renamed_349))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT121_renamed_353))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_1__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_1__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_biu_dataout_0_ "EU_CORE/eu_biu_dataout<0>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_0))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_0))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_0))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_0))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_0))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_0))
+                (portRef Q (instanceRef EU_CORE_eu_biu_dataout_0))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT101_renamed_352))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT121_renamed_353))
+                (portRef I3 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_0__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0__SW0))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_15_ "EU_CORE/eu_register_r3<15>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_15))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_15))
+                (portRef I1 (instanceRef EU_CORE_mux22_8_renamed_127))
+                (portRef I1 (instanceRef EU_CORE_mux6_8_renamed_217))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_14_ "EU_CORE/eu_register_r3<14>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_14))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_14))
+                (portRef I0 (instanceRef EU_CORE_mux21_8_renamed_131))
+                (portRef I1 (instanceRef EU_CORE_mux5_8_renamed_221))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_13_ "EU_CORE/eu_register_r3<13>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_13))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_13))
+                (portRef I1 (instanceRef EU_CORE_mux20_4_renamed_132))
+                (portRef I2 (instanceRef EU_CORE_mux4_4_renamed_222))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_12_ "EU_CORE/eu_register_r3<12>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_12))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_12))
+                (portRef I0 (instanceRef EU_CORE_mux19_4_renamed_138))
+                (portRef I1 (instanceRef EU_CORE_mux3_4_renamed_228))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_11_ "EU_CORE/eu_register_r3<11>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_11))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_11))
+                (portRef I2 (instanceRef EU_CORE_mux18_4_renamed_144))
+                (portRef I2 (instanceRef EU_CORE_mux2_4_renamed_234))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_10_ "EU_CORE/eu_register_r3<10>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_10))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_10))
+                (portRef I1 (instanceRef EU_CORE_mux17_8_renamed_153))
+                (portRef I1 (instanceRef EU_CORE_mux1_8_renamed_243))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_9_ "EU_CORE/eu_register_r3<9>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_9))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_9))
+                (portRef I1 (instanceRef EU_CORE_mux31_4_renamed_73))
+                (portRef I2 (instanceRef EU_CORE_mux15_4_renamed_172))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_8_ "EU_CORE/eu_register_r3<8>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_8))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_8))
+                (portRef I0 (instanceRef EU_CORE_mux30_4_renamed_91))
+                (portRef I1 (instanceRef EU_CORE_mux14_4_renamed_160))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_7_ "EU_CORE/eu_register_r3<7>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_7))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_7))
+                (portRef I0 (instanceRef EU_CORE_mux29_4_renamed_79))
+                (portRef I0 (instanceRef EU_CORE_mux13_4_renamed_166))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_6_ "EU_CORE/eu_register_r3<6>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_6))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_6))
+                (portRef I0 (instanceRef EU_CORE_mux28_4_renamed_85))
+                (portRef I0 (instanceRef EU_CORE_mux12_4_renamed_178))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_5_ "EU_CORE/eu_register_r3<5>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_5))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_5))
+                (portRef I0 (instanceRef EU_CORE_mux27_8_renamed_100))
+                (portRef I1 (instanceRef EU_CORE_mux11_4_renamed_184))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_4_ "EU_CORE/eu_register_r3<4>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_4))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_4))
+                (portRef I1 (instanceRef EU_CORE_mux26_4_renamed_101))
+                (portRef I1 (instanceRef EU_CORE_mux10_4_renamed_190))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_3_ "EU_CORE/eu_register_r3<3>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_3))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_3))
+                (portRef I1 (instanceRef EU_CORE_mux25_4_renamed_107))
+                (portRef I0 (instanceRef EU_CORE_mux9_4_renamed_196))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_2_ "EU_CORE/eu_register_r3<2>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_2))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_2))
+                (portRef I1 (instanceRef EU_CORE_mux24_4_renamed_113))
+                (portRef I0 (instanceRef EU_CORE_mux8_4_renamed_202))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_1_ "EU_CORE/eu_register_r3<1>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_1))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_1))
+                (portRef I0 (instanceRef EU_CORE_mux7_4_renamed_208))
+                (portRef I1 (instanceRef EU_CORE_mux23_4_renamed_446))
+              )
+            )
+            (net (rename EU_CORE_eu_register_r3_0_ "EU_CORE/eu_register_r3<0>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_register_r3_d_0))
+                (portRef Q (instanceRef EU_CORE_eu_register_r3_0))
+                (portRef I2 (instanceRef EU_CORE_mux16_4_renamed_154))
+                (portRef I1 (instanceRef EU_CORE_mux_4_renamed_244))
+              )
+            )
+            (net (rename EU_CORE_eu_flags_13_ "EU_CORE/eu_flags<13>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_flags_13))
+                (portRef I0 (instanceRef EU_CORE_mux20_5_renamed_133))
+              )
+            )
+            (net (rename EU_CORE_eu_flags_12_ "EU_CORE/eu_flags<12>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_flags_12))
+                (portRef I5 (instanceRef BIU_CORE_nmi_caught_glue_set_renamed_453))
+                (portRef I0 (instanceRef EU_CORE_mux19_5_renamed_139))
+              )
+            )
+            (net t_biu_ad_oe_d2
+              (joined
+                (portRef I (instanceRef BUF2_DIR1_INV_0))
+                (portRef Q (instanceRef t_biu_ad_oe_d2_renamed_464))
+              )
+            )
+            (net (rename t_biu_ad_out_d_19_ "t_biu_ad_out_d<19>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_19))
+                (portRef I (instanceRef A19_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_18_ "t_biu_ad_out_d<18>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_18))
+                (portRef I (instanceRef A18_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_17_ "t_biu_ad_out_d<17>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_17))
+                (portRef I (instanceRef A17_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_16_ "t_biu_ad_out_d<16>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_16))
+                (portRef I (instanceRef A16_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_15_ "t_biu_ad_out_d<15>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_15))
+                (portRef I (instanceRef A15_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_14_ "t_biu_ad_out_d<14>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_14))
+                (portRef I (instanceRef A14_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_13_ "t_biu_ad_out_d<13>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_13))
+                (portRef I (instanceRef A13_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_12_ "t_biu_ad_out_d<12>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_12))
+                (portRef I (instanceRef A12_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_11_ "t_biu_ad_out_d<11>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_11))
+                (portRef I (instanceRef A11_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_10_ "t_biu_ad_out_d<10>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_10))
+                (portRef I (instanceRef A10_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_9_ "t_biu_ad_out_d<9>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_9))
+                (portRef I (instanceRef A9_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_8_ "t_biu_ad_out_d<8>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_8))
+                (portRef I (instanceRef A8_OBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_7_ "t_biu_ad_out_d<7>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_7))
+                (portRef I (instanceRef AD7_IOBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_6_ "t_biu_ad_out_d<6>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_6))
+                (portRef I (instanceRef AD6_IOBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_5_ "t_biu_ad_out_d<5>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_5))
+                (portRef I (instanceRef AD5_IOBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_4_ "t_biu_ad_out_d<4>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_4))
+                (portRef I (instanceRef AD4_IOBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_3_ "t_biu_ad_out_d<3>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_3))
+                (portRef I (instanceRef AD3_IOBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_2_ "t_biu_ad_out_d<2>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_2))
+                (portRef I (instanceRef AD2_IOBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_1_ "t_biu_ad_out_d<1>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_1))
+                (portRef I (instanceRef AD1_IOBUF))
+              )
+            )
+            (net (rename t_biu_ad_out_d_0_ "t_biu_ad_out_d<0>")
+              (joined
+                (portRef Q (instanceRef t_biu_ad_out_d_0))
+                (portRef I (instanceRef AD0_IOBUF))
+              )
+            )
+            (net t_reset_d2
+              (joined
+                (portRef D (instanceRef t_reset_d3_renamed_2))
+                (portRef I0 (instanceRef &_n01121))
+                (portRef Q (instanceRef t_reset_d2_renamed_466))
+              )
+            )
+            (net t_reset_d3
+              (joined
+                (portRef Q (instanceRef t_reset_d3_renamed_2))
+                (portRef I1 (instanceRef &_n01121))
+                (portRef D (instanceRef t_reset_d4_renamed_374))
+              )
+            )
+            (net (rename prescaler_21_ "prescaler<21>")
+              (joined
+                (portRef D (instanceRef prescaler_d_renamed_1))
+                (portRef Q (instanceRef prescaler_21))
+                (portRef I1 (instanceRef prescaler_d_prescaler_21__AND_2_o1))
+                (portRef I2 (instanceRef &_n01121))
+                (portRef I0 (instanceRef Mcount_prescaler_xor_21__rt_renamed_433))
+                (portRef I3 (instanceRef led_go_left_rstpot_renamed_460))
+              )
+            )
+            (net prescaler_d
+              (joined
+                (portRef Q (instanceRef prescaler_d_renamed_1))
+                (portRef I0 (instanceRef prescaler_d_prescaler_21__AND_2_o1))
+                (portRef I3 (instanceRef &_n01121))
+                (portRef I1 (instanceRef led_go_left_rstpot_renamed_460))
+              )
+            )
+            (net t_reset_d4
+              (joined
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_0))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_1))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_2))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_3))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_4))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_5))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_6))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_7))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_8))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_9))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_10))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_11))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_12))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_13))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_14))
+                (portRef R (instanceRef BIU_CORE_biu_register_ss_15))
+                (portRef R (instanceRef BIU_CORE_ad_in_int_0))
+                (portRef R (instanceRef BIU_CORE_ad_in_int_1))
+                (portRef R (instanceRef BIU_CORE_ad_in_int_2))
+                (portRef R (instanceRef BIU_CORE_ad_in_int_3))
+                (portRef R (instanceRef BIU_CORE_ad_in_int_4))
+                (portRef R (instanceRef BIU_CORE_ad_in_int_5))
+                (portRef R (instanceRef BIU_CORE_ad_in_int_6))
+                (portRef R (instanceRef BIU_CORE_ad_in_int_7))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_0))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_1))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_2))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_3))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_4))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_5))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_6))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_7))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_8))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_9))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_10))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_11))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_12))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_13))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_14))
+                (portRef R (instanceRef BIU_CORE_biu_register_es_15))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_0))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_1))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_2))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_3))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_4))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_5))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_6))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_7))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_8))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_9))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_10))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_11))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_12))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_13))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_14))
+                (portRef R (instanceRef BIU_CORE_biu_register_ds_15))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_0))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_1))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_2))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_3))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_4))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_5))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_6))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_7))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_8))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_9))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_10))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_11))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_12))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_13))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_14))
+                (portRef R (instanceRef BIU_CORE_biu_register_rm_15))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_0))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_1))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_2))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_3))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_4))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_5))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_6))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_7))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_8))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_9))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_10))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_11))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_12))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_13))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_14))
+                (portRef R (instanceRef BIU_CORE_eu_register_r3_d_15))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_0))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_1))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_2))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_3))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_4))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_5))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_6))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_7))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_8))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_9))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_10))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_11))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_12))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_13))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_14))
+                (portRef R (instanceRef BIU_CORE_biu_register_reg_15))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_0))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_1))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_2))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_3))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_4))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_5))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_6))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_7))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_8))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_9))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_10))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_11))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_12))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_13))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_14))
+                (portRef S (instanceRef BIU_CORE_biu_register_cs_15))
+                (portRef R (instanceRef BIU_CORE_nmi_d1_renamed_72))
+                (portRef R (instanceRef BIU_CORE_biu_done_int_renamed_71))
+                (portRef R (instanceRef BIU_CORE_pfq_write_renamed_70))
+                (portRef R (instanceRef BIU_CORE_ready_d1_renamed_69))
+                (portRef R (instanceRef BIU_CORE_eu_biu_req_d1_renamed_68))
+                (portRef R (instanceRef BIU_CORE_byte_num_renamed_67))
+                (portRef R (instanceRef BIU_CORE_intr_d1_renamed_66))
+                (portRef R (instanceRef BIU_CORE_AD_OE_renamed_65))
+                (portRef R (instanceRef BIU_CORE_dtr_int_renamed_64))
+                (portRef R (instanceRef BIU_CORE_clk_d1_renamed_63))
+                (portRef S (instanceRef BIU_CORE_inta_n_int_renamed_62))
+                (portRef S (instanceRef BIU_CORE_rd_n_int_renamed_61))
+                (portRef S (instanceRef BIU_CORE_wr_n_int_renamed_60))
+                (portRef S (instanceRef BIU_CORE_den_int_renamed_59))
+                (portRef R (instanceRef BIU_CORE_biu_state_0))
+                (portRef R (instanceRef BIU_CORE_biu_state_1))
+                (portRef R (instanceRef BIU_CORE_biu_state_2))
+                (portRef R (instanceRef BIU_CORE_biu_state_3))
+                (portRef S (instanceRef BIU_CORE_biu_state_4))
+                (portRef R (instanceRef BIU_CORE_biu_state_5))
+                (portRef S (instanceRef BIU_CORE_biu_state_6))
+                (portRef S (instanceRef BIU_CORE_biu_state_7))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_0_renamed_58))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_1_renamed_57))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_2_renamed_56))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_3_renamed_55))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_4_renamed_54))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_5_renamed_53))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_6_renamed_52))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_7_renamed_51))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_8_renamed_50))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_9_renamed_49))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_10_renamed_48))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_11_renamed_47))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_12_renamed_46))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_13_renamed_45))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_14_renamed_44))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_15_renamed_43))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_16_renamed_42))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_17_renamed_41))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_18_renamed_40))
+                (portRef R (instanceRef BIU_CORE_addr_out_temp_19_renamed_39))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_0_renamed_38))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_1_renamed_37))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_2_renamed_36))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_3_renamed_35))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_4_renamed_34))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_5_renamed_33))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_6_renamed_32))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_7_renamed_31))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_8_renamed_30))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_9_renamed_29))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_10_renamed_28))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_11_renamed_27))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_12_renamed_26))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_13_renamed_25))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_14_renamed_24))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_15_renamed_23))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_16_renamed_22))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_17_renamed_21))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_18_renamed_20))
+                (portRef R (instanceRef BIU_CORE_AD_OUT_19_renamed_19))
+                (portRef R (instanceRef BIU_CORE_clk_d2_renamed_18))
+                (portRef R (instanceRef BIU_CORE_nmi_d2_renamed_17))
+                (portRef R (instanceRef BIU_CORE_intr_d2_renamed_16))
+                (portRef R (instanceRef BIU_CORE_IOM_renamed_15))
+                (portRef R (instanceRef BIU_CORE_DTR_renamed_14))
+                (portRef S (instanceRef BIU_CORE_RD_n_renamed_13))
+                (portRef S (instanceRef BIU_CORE_INTA_n_renamed_12))
+                (portRef S (instanceRef BIU_CORE_WR_n_renamed_11))
+                (portRef S (instanceRef BIU_CORE_DEN_renamed_10))
+                (portRef R (instanceRef BIU_CORE_latched_data_in_0))
+                (portRef R (instanceRef BIU_CORE_latched_data_in_1))
+                (portRef R (instanceRef BIU_CORE_latched_data_in_2))
+                (portRef R (instanceRef BIU_CORE_latched_data_in_3))
+                (portRef R (instanceRef BIU_CORE_latched_data_in_4))
+                (portRef R (instanceRef BIU_CORE_latched_data_in_5))
+                (portRef R (instanceRef BIU_CORE_latched_data_in_6))
+                (portRef R (instanceRef BIU_CORE_latched_data_in_7))
+                (portRef R (instanceRef BIU_CORE_clk_d3_renamed_9))
+                (portRef R (instanceRef BIU_CORE_nmi_d3_renamed_8))
+                (portRef R (instanceRef BIU_CORE_intr_d3_renamed_7))
+                (portRef R (instanceRef BIU_CORE_pfq_entry1_0))
+                (portRef R (instanceRef BIU_CORE_pfq_entry1_1))
+                (portRef R (instanceRef BIU_CORE_pfq_entry1_2))
+                (portRef R (instanceRef BIU_CORE_pfq_entry1_3))
+                (portRef R (instanceRef BIU_CORE_pfq_entry1_4))
+                (portRef R (instanceRef BIU_CORE_pfq_entry1_5))
+                (portRef R (instanceRef BIU_CORE_pfq_entry1_6))
+                (portRef R (instanceRef BIU_CORE_pfq_entry1_7))
+                (portRef R (instanceRef BIU_CORE_pfq_entry0_0))
+                (portRef R (instanceRef BIU_CORE_pfq_entry0_1))
+                (portRef R (instanceRef BIU_CORE_pfq_entry0_2))
+                (portRef R (instanceRef BIU_CORE_pfq_entry0_3))
+                (portRef R (instanceRef BIU_CORE_pfq_entry0_4))
+                (portRef R (instanceRef BIU_CORE_pfq_entry0_5))
+                (portRef R (instanceRef BIU_CORE_pfq_entry0_6))
+                (portRef R (instanceRef BIU_CORE_pfq_entry0_7))
+                (portRef R (instanceRef BIU_CORE_pfq_entry2_0))
+                (portRef R (instanceRef BIU_CORE_pfq_entry2_1))
+                (portRef R (instanceRef BIU_CORE_pfq_entry2_2))
+                (portRef R (instanceRef BIU_CORE_pfq_entry2_3))
+                (portRef R (instanceRef BIU_CORE_pfq_entry2_4))
+                (portRef R (instanceRef BIU_CORE_pfq_entry2_5))
+                (portRef R (instanceRef BIU_CORE_pfq_entry2_6))
+                (portRef R (instanceRef BIU_CORE_pfq_entry2_7))
+                (portRef R (instanceRef BIU_CORE_pfq_entry3_0))
+                (portRef R (instanceRef BIU_CORE_pfq_entry3_1))
+                (portRef R (instanceRef BIU_CORE_pfq_entry3_2))
+                (portRef R (instanceRef BIU_CORE_pfq_entry3_3))
+                (portRef R (instanceRef BIU_CORE_pfq_entry3_4))
+                (portRef R (instanceRef BIU_CORE_pfq_entry3_5))
+                (portRef R (instanceRef BIU_CORE_pfq_entry3_6))
+                (portRef R (instanceRef BIU_CORE_pfq_entry3_7))
+                (portRef R (instanceRef BIU_CORE_clk_d4_renamed_6))
+                (portRef R (instanceRef BIU_CORE_nmi_d4_renamed_5))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_0))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_1))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_2))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_3))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_4))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_5))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_6))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_7))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_8))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_9))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_10))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_11))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_12))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_13))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_14))
+                (portRef R (instanceRef BIU_CORE_biu_return_data_int_15))
+                (portRef S (instanceRef BIU_CORE_s_bits_0))
+                (portRef S (instanceRef BIU_CORE_s_bits_1))
+                (portRef S (instanceRef BIU_CORE_s_bits_2))
+                (portRef R (instanceRef BIU_CORE_nmi_d5_renamed_3))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_0))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_1))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_2))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_3))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_4))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_5))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_6))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_7))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_8))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_9))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_10))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_11))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_12))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_13))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_14))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_in_15))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_0))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_1))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_2))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_3))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_4))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_5))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_6))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_7))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_8))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_9))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_10))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_11))
+                (portRef R (instanceRef BIU_CORE_clock_cycle_counter_12))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_0))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_1))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_2))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_3))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_4))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_5))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_6))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_7))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_8))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_9))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_10))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_11))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_12))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_13))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_14))
+                (portRef R (instanceRef BIU_CORE_pfq_addr_out_15))
+                (portRef R (instanceRef EU_CORE_biu_done_d1_renamed_258))
+                (portRef R (instanceRef EU_CORE_eu_stall_pipeline_renamed_257))
+                (portRef R (instanceRef EU_CORE_eu_add_carry_renamed_256))
+                (portRef R (instanceRef EU_CORE_eu_add_carry8_renamed_255))
+                (portRef R (instanceRef EU_CORE_eu_add_aux_carry_renamed_254))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_0))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_1))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_2))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_3))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_4))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_5))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_6))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_7))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_8))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_9))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_10))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_11))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_12))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_13))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_14))
+                (portRef R (instanceRef EU_CORE_eu_register_ax_15))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_0))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_1))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_2))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_3))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_4))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_5))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_6))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_7))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_8))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_9))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_10))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_11))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_12))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_13))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_14))
+                (portRef R (instanceRef EU_CORE_eu_register_bx_15))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_0))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_1))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_2))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_3))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_4))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_5))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_6))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_7))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_8))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_9))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_10))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_11))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_12))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_13))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_14))
+                (portRef R (instanceRef EU_CORE_eu_register_cx_15))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_0))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_1))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_2))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_3))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_4))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_5))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_6))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_7))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_8))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_9))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_10))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_11))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_12))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_13))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_14))
+                (portRef R (instanceRef EU_CORE_eu_register_dx_15))
+                (portRef R (instanceRef EU_CORE_eu_register_si_0))
+                (portRef R (instanceRef EU_CORE_eu_register_si_1))
+                (portRef R (instanceRef EU_CORE_eu_register_si_2))
+                (portRef R (instanceRef EU_CORE_eu_register_si_3))
+                (portRef R (instanceRef EU_CORE_eu_register_si_4))
+                (portRef R (instanceRef EU_CORE_eu_register_si_5))
+                (portRef R (instanceRef EU_CORE_eu_register_si_6))
+                (portRef R (instanceRef EU_CORE_eu_register_si_7))
+                (portRef R (instanceRef EU_CORE_eu_register_si_8))
+                (portRef R (instanceRef EU_CORE_eu_register_si_9))
+                (portRef R (instanceRef EU_CORE_eu_register_si_10))
+                (portRef R (instanceRef EU_CORE_eu_register_si_11))
+                (portRef R (instanceRef EU_CORE_eu_register_si_12))
+                (portRef R (instanceRef EU_CORE_eu_register_si_13))
+                (portRef R (instanceRef EU_CORE_eu_register_si_14))
+                (portRef R (instanceRef EU_CORE_eu_register_si_15))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_0))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_1))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_2))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_3))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_4))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_5))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_6))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_7))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_8))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_9))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_10))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_11))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_12))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_13))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_14))
+                (portRef R (instanceRef EU_CORE_eu_register_sp_15))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_0))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_1))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_2))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_3))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_4))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_5))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_6))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_7))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_8))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_9))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_10))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_11))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_12))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_13))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_14))
+                (portRef R (instanceRef EU_CORE_eu_register_bp_15))
+                (portRef R (instanceRef EU_CORE_eu_register_di_0))
+                (portRef R (instanceRef EU_CORE_eu_register_di_1))
+                (portRef R (instanceRef EU_CORE_eu_register_di_2))
+                (portRef R (instanceRef EU_CORE_eu_register_di_3))
+                (portRef R (instanceRef EU_CORE_eu_register_di_4))
+                (portRef R (instanceRef EU_CORE_eu_register_di_5))
+                (portRef R (instanceRef EU_CORE_eu_register_di_6))
+                (portRef R (instanceRef EU_CORE_eu_register_di_7))
+                (portRef R (instanceRef EU_CORE_eu_register_di_8))
+                (portRef R (instanceRef EU_CORE_eu_register_di_9))
+                (portRef R (instanceRef EU_CORE_eu_register_di_10))
+                (portRef R (instanceRef EU_CORE_eu_register_di_11))
+                (portRef R (instanceRef EU_CORE_eu_register_di_12))
+                (portRef R (instanceRef EU_CORE_eu_register_di_13))
+                (portRef R (instanceRef EU_CORE_eu_register_di_14))
+                (portRef R (instanceRef EU_CORE_eu_register_di_15))
+                (portRef R (instanceRef EU_CORE_eu_flags_0))
+                (portRef R (instanceRef EU_CORE_eu_flags_1))
+                (portRef R (instanceRef EU_CORE_eu_flags_2))
+                (portRef R (instanceRef EU_CORE_eu_flags_3))
+                (portRef R (instanceRef EU_CORE_eu_flags_4))
+                (portRef R (instanceRef EU_CORE_eu_flags_5))
+                (portRef R (instanceRef EU_CORE_eu_flags_6))
+                (portRef R (instanceRef EU_CORE_eu_flags_7))
+                (portRef R (instanceRef EU_CORE_eu_flags_8))
+                (portRef R (instanceRef EU_CORE_eu_flags_9))
+                (portRef R (instanceRef EU_CORE_eu_flags_10))
+                (portRef R (instanceRef EU_CORE_eu_flags_11))
+                (portRef R (instanceRef EU_CORE_eu_flags_12))
+                (portRef R (instanceRef EU_CORE_eu_flags_13))
+                (portRef R (instanceRef EU_CORE_eu_flags_14))
+                (portRef R (instanceRef EU_CORE_eu_flags_15))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_0))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_1))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_2))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_3))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_4))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_5))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_6))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_7))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_8))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_9))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_10))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_11))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_12))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_13))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_14))
+                (portRef R (instanceRef EU_CORE_eu_register_r3_15))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_0))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_1))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_2))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_3))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_4))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_5))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_6))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_7))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_8))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_9))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_10))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_11))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_12))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_13))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_14))
+                (portRef R (instanceRef EU_CORE_eu_register_r1_15))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_0))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_1))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_2))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_3))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_4))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_5))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_6))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_7))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_8))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_9))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_10))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_11))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_12))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_13))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_14))
+                (portRef R (instanceRef EU_CORE_eu_register_r2_15))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_0))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_1))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_2))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_3))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_4))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_5))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_6))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_7))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_8))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_9))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_10))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_11))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_12))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_13))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_14))
+                (portRef R (instanceRef EU_CORE_eu_biu_command_15))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_0))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_1))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_2))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_3))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_4))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_5))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_6))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_7))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_8))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_9))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_10))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_11))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_12))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_13))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_14))
+                (portRef R (instanceRef EU_CORE_eu_biu_dataout_15))
+                (portRef R (instanceRef EU_CORE_biu_done_d2_renamed_253))
+                (portRef R (instanceRef EU_CORE_eu_flag_t_d_renamed_252))
+                (portRef R (instanceRef EU_CORE_eu_add_overflow16_renamed_251))
+                (portRef R (instanceRef EU_CORE_eu_add_overflow8_renamed_250))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_0))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_1))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_2))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_3))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_4))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_5))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_6))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_7))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_8))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_9))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_10))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_11))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_12))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_13))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_14))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_15))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_16))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_17))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_18))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_19))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_20))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_21))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_22))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_23))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_24))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_25))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_26))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_27))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_28))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_29))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_30))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_31))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_32))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_33))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_34))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_35))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_36))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_37))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_38))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_39))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_40))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_41))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_42))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_43))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_44))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_45))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_46))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_47))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_48))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_49))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_50))
+                (portRef R (instanceRef EU_CORE_eu_calling_address_51))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_0))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_1))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_2))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_3))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_4))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_5))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_6))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_7))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_8))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_9))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_10))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_11))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_12))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_13))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_14))
+                (portRef R (instanceRef EU_CORE_eu_alu_last_result_15))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_0))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_1))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_2))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_3))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_4))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_5))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_6))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_7))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_8))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_9))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_10))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_11))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_12))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_13))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_14))
+                (portRef R (instanceRef EU_CORE_eu_register_r0_15))
+                (portRef I0 (instanceRef EU_CORE__n1090_inv1))
+                (portRef I0 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT263))
+                (portRef I0 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT43))
+                (portRef I0 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT63))
+                (portRef I0 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT83))
+                (portRef I0 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT243))
+                (portRef Q (instanceRef t_reset_d4_renamed_374))
+                (portRef R (instanceRef BIU_CORE_eu_biu_req_caught_renamed_375))
+                (portRef R (instanceRef BIU_CORE_nmi_caught_renamed_376))
+                (portRef R (instanceRef EU_CORE_eu_tr_latched_renamed_377))
+                (portRef R (instanceRef EU_CORE_biu_done_caught_renamed_378))
+                (portRef R (instanceRef BIU_CORE_BIU_INTR_renamed_439))
+                (portRef R (instanceRef BIU_CORE_ale_int_renamed_440))
+                (portRef R (instanceRef BIU_CORE_iom_int_renamed_441))
+                (portRef R (instanceRef EU_CORE_intr_enable_delayed_renamed_443))
+                (portRef I0 (instanceRef BIU_CORE_word_cycle_rstpot1_renamed_451))
+                (portRef I (instanceRef BIU_CORE_RESET_INT_inv1_INV_0))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT183))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT203))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT223))
+                (portRef I2 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT143))
+                (portRef I2 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT163))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT103))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT123))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT23))
+              )
+            )
+            (net led_go_left
+              (joined
+                (portRef I0 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT81))
+                (portRef I0 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT71))
+                (portRef I0 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT61))
+                (portRef I0 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT51))
+                (portRef I0 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT41))
+                (portRef I0 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT31))
+                (portRef I0 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT21))
+                (portRef I0 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT11))
+                (portRef Q (instanceRef led_go_left_renamed_444))
+                (portRef I0 (instanceRef led_go_left_rstpot_renamed_460))
+              )
+            )
+            (net (rename led_int_7_ "led_int<7>")
+              (joined
+                (portRef Q (instanceRef led_int_7))
+                (portRef I1 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT71))
+                (portRef I2 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT11))
+                (portRef I (instanceRef LED_7_1_INV_0))
+              )
+            )
+            (net (rename led_int_6_ "led_int<6>")
+              (joined
+                (portRef Q (instanceRef led_int_6))
+                (portRef I2 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT81))
+                (portRef I1 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT61))
+                (portRef I2 (instanceRef led_go_left_rstpot_renamed_460))
+                (portRef I (instanceRef LED_6_1_INV_0))
+              )
+            )
+            (net (rename led_int_5_ "led_int<5>")
+              (joined
+                (portRef Q (instanceRef led_int_5))
+                (portRef I2 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT71))
+                (portRef I1 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT51))
+                (portRef I (instanceRef LED_5_1_INV_0))
+              )
+            )
+            (net (rename led_int_4_ "led_int<4>")
+              (joined
+                (portRef Q (instanceRef led_int_4))
+                (portRef I2 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT61))
+                (portRef I1 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT41))
+                (portRef I (instanceRef LED_4_1_INV_0))
+              )
+            )
+            (net (rename led_int_3_ "led_int<3>")
+              (joined
+                (portRef Q (instanceRef led_int_3))
+                (portRef I2 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT51))
+                (portRef I1 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT31))
+                (portRef I (instanceRef LED_3_1_INV_0))
+              )
+            )
+            (net (rename led_int_2_ "led_int<2>")
+              (joined
+                (portRef Q (instanceRef led_int_2))
+                (portRef I2 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT41))
+                (portRef I1 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT21))
+                (portRef I (instanceRef LED_2_1_INV_0))
+              )
+            )
+            (net (rename led_int_1_ "led_int<1>")
+              (joined
+                (portRef Q (instanceRef led_int_1))
+                (portRef I2 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT31))
+                (portRef I1 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT11))
+                (portRef I4 (instanceRef led_go_left_rstpot_renamed_460))
+                (portRef I (instanceRef &_n01041_INV_0))
+              )
+            )
+            (net (rename led_int_0_ "led_int<0>")
+              (joined
+                (portRef Q (instanceRef led_int_0))
+                (portRef I1 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT81))
+                (portRef I2 (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT21))
+                (portRef I (instanceRef LED_0_1_INV_0))
+              )
+            )
+            (net BUF2_DIR_OBUF
+              (joined
+                (portRef I (instanceRef BUF2_DIR_OBUF_renamed_373))
+                (portRef O (instanceRef BUF2_DIR1_INV_0))
+                (portRef T (instanceRef AD7_IOBUF))
+                (portRef T (instanceRef AD6_IOBUF))
+                (portRef T (instanceRef AD5_IOBUF))
+                (portRef T (instanceRef AD4_IOBUF))
+                (portRef T (instanceRef AD3_IOBUF))
+                (portRef T (instanceRef AD2_IOBUF))
+                (portRef T (instanceRef AD1_IOBUF))
+                (portRef T (instanceRef AD0_IOBUF))
+              )
+            )
+            (net AD7
+              (joined
+                (portRef AD7)
+                (portRef IO (instanceRef AD7_IOBUF))
+              )
+            )
+            (net AD6
+              (joined
+                (portRef AD6)
+                (portRef IO (instanceRef AD6_IOBUF))
+              )
+            )
+            (net AD5
+              (joined
+                (portRef AD5)
+                (portRef IO (instanceRef AD5_IOBUF))
+              )
+            )
+            (net AD4
+              (joined
+                (portRef AD4)
+                (portRef IO (instanceRef AD4_IOBUF))
+              )
+            )
+            (net AD3
+              (joined
+                (portRef AD3)
+                (portRef IO (instanceRef AD3_IOBUF))
+              )
+            )
+            (net AD2
+              (joined
+                (portRef AD2)
+                (portRef IO (instanceRef AD2_IOBUF))
+              )
+            )
+            (net AD1
+              (joined
+                (portRef AD1)
+                (portRef IO (instanceRef AD1_IOBUF))
+              )
+            )
+            (net AD0
+              (joined
+                (portRef AD0)
+                (portRef IO (instanceRef AD0_IOBUF))
+              )
+            )
+            (net (rename &_n0112 "_n0112")
+              (joined
+                (portRef R (instanceRef led_int_0))
+                (portRef R (instanceRef led_int_1))
+                (portRef R (instanceRef led_int_2))
+                (portRef R (instanceRef led_int_3))
+                (portRef R (instanceRef led_int_4))
+                (portRef R (instanceRef led_int_5))
+                (portRef R (instanceRef led_int_6))
+                (portRef S (instanceRef led_int_7))
+                (portRef O (instanceRef &_n01121))
+              )
+            )
+            (net (rename prescaler_d_prescaler_21__AND_2_o "prescaler_d_prescaler[21]_AND_2_o")
+              (joined
+                (portRef CE (instanceRef led_int_0))
+                (portRef CE (instanceRef led_int_1))
+                (portRef CE (instanceRef led_int_2))
+                (portRef CE (instanceRef led_int_3))
+                (portRef CE (instanceRef led_int_4))
+                (portRef CE (instanceRef led_int_5))
+                (portRef CE (instanceRef led_int_6))
+                (portRef CE (instanceRef led_int_7))
+                (portRef O (instanceRef prescaler_d_prescaler_21__AND_2_o1))
+              )
+            )
+            (net (rename led_int_6__led_int_0__mux_29_OUT_7_ "led_int[6]_led_int[0]_mux_29_OUT<7>")
+              (joined
+                (portRef D (instanceRef led_int_7))
+                (portRef O (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT81))
+              )
+            )
+            (net (rename led_int_6__led_int_0__mux_29_OUT_6_ "led_int[6]_led_int[0]_mux_29_OUT<6>")
+              (joined
+                (portRef D (instanceRef led_int_6))
+                (portRef O (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT71))
+              )
+            )
+            (net (rename led_int_6__led_int_0__mux_29_OUT_5_ "led_int[6]_led_int[0]_mux_29_OUT<5>")
+              (joined
+                (portRef D (instanceRef led_int_5))
+                (portRef O (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT61))
+              )
+            )
+            (net (rename led_int_6__led_int_0__mux_29_OUT_4_ "led_int[6]_led_int[0]_mux_29_OUT<4>")
+              (joined
+                (portRef D (instanceRef led_int_4))
+                (portRef O (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT51))
+              )
+            )
+            (net (rename led_int_6__led_int_0__mux_29_OUT_3_ "led_int[6]_led_int[0]_mux_29_OUT<3>")
+              (joined
+                (portRef D (instanceRef led_int_3))
+                (portRef O (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT41))
+              )
+            )
+            (net (rename led_int_6__led_int_0__mux_29_OUT_2_ "led_int[6]_led_int[0]_mux_29_OUT<2>")
+              (joined
+                (portRef D (instanceRef led_int_2))
+                (portRef O (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT31))
+              )
+            )
+            (net (rename led_int_6__led_int_0__mux_29_OUT_1_ "led_int[6]_led_int[0]_mux_29_OUT<1>")
+              (joined
+                (portRef D (instanceRef led_int_1))
+                (portRef O (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT21))
+              )
+            )
+            (net (rename led_int_6__led_int_0__mux_29_OUT_0_ "led_int[6]_led_int[0]_mux_29_OUT<0>")
+              (joined
+                (portRef D (instanceRef led_int_0))
+                (portRef O (instanceRef Mmux_led_int_6__led_int_0__mux_29_OUT11))
+              )
+            )
+            (net LED_7_OBUF
+              (joined
+                (portRef I (instanceRef LED_7_OBUF_renamed_363))
+                (portRef O (instanceRef LED_7_1_INV_0))
+              )
+            )
+            (net LED_6_OBUF
+              (joined
+                (portRef I (instanceRef LED_6_OBUF_renamed_364))
+                (portRef O (instanceRef LED_6_1_INV_0))
+              )
+            )
+            (net LED_5_OBUF
+              (joined
+                (portRef I (instanceRef LED_5_OBUF_renamed_365))
+                (portRef O (instanceRef LED_5_1_INV_0))
+              )
+            )
+            (net LED_4_OBUF
+              (joined
+                (portRef I (instanceRef LED_4_OBUF_renamed_366))
+                (portRef O (instanceRef LED_4_1_INV_0))
+              )
+            )
+            (net LED_3_OBUF
+              (joined
+                (portRef I (instanceRef LED_3_OBUF_renamed_367))
+                (portRef O (instanceRef LED_3_1_INV_0))
+              )
+            )
+            (net LED_2_OBUF
+              (joined
+                (portRef I (instanceRef LED_2_OBUF_renamed_368))
+                (portRef O (instanceRef LED_2_1_INV_0))
+              )
+            )
+            (net LED_1_OBUF
+              (joined
+                (portRef I (instanceRef LED_1_OBUF_renamed_369))
+                (portRef O (instanceRef &_n01041_INV_0))
+              )
+            )
+            (net LED_0_OBUF
+              (joined
+                (portRef I (instanceRef LED_0_OBUF_renamed_370))
+                (portRef O (instanceRef LED_0_1_INV_0))
+              )
+            )
+            (net SRAM_WE_n_OBUF
+              (joined
+                (portRef P (instanceRef XST_VCC))
+                (portRef DI (instanceRef Mcount_prescaler_cy_0__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_0__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_1__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_2__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_3__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_4__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_5__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_6__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_7__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_8__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_9__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_10__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_11__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_0__))
+                (portRef DI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_0__))
+                (portRef I (instanceRef SRAM_CE_n_OBUF))
+                (portRef I (instanceRef SRAM_OE_n_OBUF))
+                (portRef I (instanceRef SRAM_WE_n_OBUF_renamed_371))
+                (portRef CE (instanceRef Mshreg_t_biu_ad_oe_d2_renamed_463))
+                (portRef CE (instanceRef t_biu_ad_oe_d2_renamed_464))
+                (portRef CE (instanceRef Mshreg_t_reset_d2_renamed_465))
+                (portRef CE (instanceRef t_reset_d2_renamed_466))
+              )
+            )
+            (net BUF2_OE_n_OBUF
+              (joined
+                (portRef G (instanceRef XST_GND))
+                (portRef CI (instanceRef Mcount_prescaler_cy_0__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_0__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_1__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_2__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_3__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_4__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_5__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_6__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_7__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_8__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_9__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_10__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_11__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_12__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_13__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_14__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_15__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_16__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_17__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_18__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_19__))
+                (portRef DI (instanceRef Mcount_prescaler_cy_20__))
+                (portRef CLKFB (instanceRef SPARTAN6PLL_dcm_sp_inst))
+                (portRef DSSEN (instanceRef SPARTAN6PLL_dcm_sp_inst))
+                (portRef PSCLK (instanceRef SPARTAN6PLL_dcm_sp_inst))
+                (portRef PSEN (instanceRef SPARTAN6PLL_dcm_sp_inst))
+                (portRef PSINCDEC (instanceRef SPARTAN6PLL_dcm_sp_inst))
+                (portRef RST (instanceRef SPARTAN6PLL_dcm_sp_inst))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_0__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_1__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_2__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_3__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_4__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_5__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_6__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_7__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_8__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_9__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_10__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_11__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_12__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_13__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_14__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_0__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_1__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_2__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_3__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_4__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_5__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_6__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_7__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_8__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_9__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_10__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_11__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_12__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_13__))
+                (portRef DI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_4__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_16__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_17__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_4__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_16__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_17__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_4__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_16__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_17__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_0__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_0__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_1__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_2__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_3__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_4__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_5__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_6__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_7__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_8__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_9__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_10__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_11__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_12__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_13__))
+                (portRef DI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_4__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_16__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_17__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_18__))
+                (portRef CI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_0__))
+                (portRef CI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_0__))
+                (portRef DI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_1__))
+                (portRef DI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_2__))
+                (portRef DI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_3__))
+                (portRef DI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_4__))
+                (portRef DI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_5__))
+                (portRef DI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_6__))
+                (portRef DI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_7__))
+                (portRef DI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_8__))
+                (portRef DI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_9__))
+                (portRef DI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_10__))
+                (portRef DI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_11__))
+                (portRef I (instanceRef SRAM_D_7_OBUF))
+                (portRef I (instanceRef SRAM_D_6_OBUF))
+                (portRef I (instanceRef SRAM_D_5_OBUF))
+                (portRef I (instanceRef SRAM_D_4_OBUF))
+                (portRef I (instanceRef SRAM_D_3_OBUF))
+                (portRef I (instanceRef SRAM_D_2_OBUF))
+                (portRef I (instanceRef SRAM_D_1_OBUF))
+                (portRef I (instanceRef SRAM_D_0_OBUF))
+                (portRef I (instanceRef SRAM_A_18_OBUF))
+                (portRef I (instanceRef SRAM_A_17_OBUF))
+                (portRef I (instanceRef SRAM_A_16_OBUF))
+                (portRef I (instanceRef SRAM_A_15_OBUF))
+                (portRef I (instanceRef SRAM_A_14_OBUF))
+                (portRef I (instanceRef SRAM_A_13_OBUF))
+                (portRef I (instanceRef SRAM_A_12_OBUF))
+                (portRef I (instanceRef SRAM_A_11_OBUF))
+                (portRef I (instanceRef SRAM_A_10_OBUF))
+                (portRef I (instanceRef SRAM_A_9_OBUF))
+                (portRef I (instanceRef SRAM_A_8_OBUF))
+                (portRef I (instanceRef SRAM_A_7_OBUF))
+                (portRef I (instanceRef SRAM_A_6_OBUF))
+                (portRef I (instanceRef SRAM_A_5_OBUF))
+                (portRef I (instanceRef SRAM_A_4_OBUF))
+                (portRef I (instanceRef SRAM_A_3_OBUF))
+                (portRef I (instanceRef SRAM_A_2_OBUF))
+                (portRef I (instanceRef SRAM_A_1_OBUF))
+                (portRef I (instanceRef SRAM_A_0_OBUF))
+                (portRef I (instanceRef BUF1_OE_n_OBUF))
+                (portRef I (instanceRef BUF2_OE_n_OBUF_renamed_372))
+                (portRef A0 (instanceRef Mshreg_t_biu_ad_oe_d2_renamed_463))
+                (portRef A1 (instanceRef Mshreg_t_biu_ad_oe_d2_renamed_463))
+                (portRef A2 (instanceRef Mshreg_t_biu_ad_oe_d2_renamed_463))
+                (portRef A3 (instanceRef Mshreg_t_biu_ad_oe_d2_renamed_463))
+                (portRef A0 (instanceRef Mshreg_t_reset_d2_renamed_465))
+                (portRef A1 (instanceRef Mshreg_t_reset_d2_renamed_465))
+                (portRef A2 (instanceRef Mshreg_t_reset_d2_renamed_465))
+                (portRef A3 (instanceRef Mshreg_t_reset_d2_renamed_465))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_15_renamed_467))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_15_renamed_467))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_15_renamed_467))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_15_renamed_467))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_14_renamed_468))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_14_renamed_468))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_14_renamed_468))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_14_renamed_468))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_13_renamed_469))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_13_renamed_469))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_13_renamed_469))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_13_renamed_469))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_12_renamed_470))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_12_renamed_470))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_12_renamed_470))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_12_renamed_470))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_11_renamed_471))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_11_renamed_471))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_11_renamed_471))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_11_renamed_471))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_10_renamed_472))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_10_renamed_472))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_10_renamed_472))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_10_renamed_472))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_9_renamed_473))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_9_renamed_473))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_9_renamed_473))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_9_renamed_473))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_8_renamed_474))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_8_renamed_474))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_8_renamed_474))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_8_renamed_474))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_7_renamed_475))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_7_renamed_475))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_7_renamed_475))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_7_renamed_475))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_6_renamed_476))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_6_renamed_476))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_6_renamed_476))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_6_renamed_476))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_3_renamed_477))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_3_renamed_477))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_3_renamed_477))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_3_renamed_477))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_5_renamed_478))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_5_renamed_478))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_5_renamed_478))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_5_renamed_478))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_4_renamed_479))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_4_renamed_479))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_4_renamed_479))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_4_renamed_479))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_2_renamed_480))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_2_renamed_480))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_2_renamed_480))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_2_renamed_480))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_1_renamed_481))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_1_renamed_481))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_1_renamed_481))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_1_renamed_481))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_0_renamed_482))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_0_renamed_482))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_0_renamed_482))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_0_renamed_482))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_15_renamed_483))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_15_renamed_483))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_15_renamed_483))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_15_renamed_483))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_12_renamed_484))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_12_renamed_484))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_12_renamed_484))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_12_renamed_484))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_14_renamed_485))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_14_renamed_485))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_14_renamed_485))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_14_renamed_485))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_13_renamed_486))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_13_renamed_486))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_13_renamed_486))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_13_renamed_486))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_11_renamed_487))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_11_renamed_487))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_11_renamed_487))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_11_renamed_487))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_10_renamed_488))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_10_renamed_488))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_10_renamed_488))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_10_renamed_488))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_9_renamed_489))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_9_renamed_489))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_9_renamed_489))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_9_renamed_489))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_8_renamed_490))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_8_renamed_490))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_8_renamed_490))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_8_renamed_490))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_5_renamed_491))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_5_renamed_491))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_5_renamed_491))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_5_renamed_491))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_7_renamed_492))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_7_renamed_492))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_7_renamed_492))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_7_renamed_492))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_6_renamed_493))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_6_renamed_493))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_6_renamed_493))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_6_renamed_493))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_4_renamed_494))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_4_renamed_494))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_4_renamed_494))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_4_renamed_494))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_3_renamed_495))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_3_renamed_495))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_3_renamed_495))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_3_renamed_495))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_2_renamed_496))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_2_renamed_496))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_2_renamed_496))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_2_renamed_496))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_1_renamed_497))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_1_renamed_497))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_1_renamed_497))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_1_renamed_497))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_14_renamed_498))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_14_renamed_498))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_14_renamed_498))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_14_renamed_498))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_0_renamed_499))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_0_renamed_499))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_0_renamed_499))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_0_renamed_499))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_15_renamed_500))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_15_renamed_500))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_15_renamed_500))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_15_renamed_500))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_13_renamed_501))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_13_renamed_501))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_13_renamed_501))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_13_renamed_501))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_12_renamed_502))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_12_renamed_502))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_12_renamed_502))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_12_renamed_502))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_11_renamed_503))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_11_renamed_503))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_11_renamed_503))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_11_renamed_503))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_10_renamed_504))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_10_renamed_504))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_10_renamed_504))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_10_renamed_504))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_7_renamed_505))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_7_renamed_505))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_7_renamed_505))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_7_renamed_505))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_9_renamed_506))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_9_renamed_506))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_9_renamed_506))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_9_renamed_506))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_8_renamed_507))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_8_renamed_507))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_8_renamed_507))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_8_renamed_507))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_6_renamed_508))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_6_renamed_508))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_6_renamed_508))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_6_renamed_508))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_5_renamed_509))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_5_renamed_509))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_5_renamed_509))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_5_renamed_509))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_4_renamed_510))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_4_renamed_510))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_4_renamed_510))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_4_renamed_510))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_3_renamed_511))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_3_renamed_511))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_3_renamed_511))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_3_renamed_511))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_0_renamed_512))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_0_renamed_512))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_0_renamed_512))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_0_renamed_512))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_2_renamed_513))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_2_renamed_513))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_2_renamed_513))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_2_renamed_513))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_1_renamed_514))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_1_renamed_514))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_1_renamed_514))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_1_renamed_514))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_15_renamed_515))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_15_renamed_515))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_15_renamed_515))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_15_renamed_515))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_14_renamed_516))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_14_renamed_516))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_14_renamed_516))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_14_renamed_516))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_13_renamed_517))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_13_renamed_517))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_13_renamed_517))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_13_renamed_517))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_12_renamed_518))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_12_renamed_518))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_12_renamed_518))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_12_renamed_518))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_9_renamed_519))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_9_renamed_519))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_9_renamed_519))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_9_renamed_519))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_11_renamed_520))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_11_renamed_520))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_11_renamed_520))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_11_renamed_520))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_10_renamed_521))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_10_renamed_521))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_10_renamed_521))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_10_renamed_521))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_8_renamed_522))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_8_renamed_522))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_8_renamed_522))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_8_renamed_522))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_7_renamed_523))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_7_renamed_523))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_7_renamed_523))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_7_renamed_523))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_6_renamed_524))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_6_renamed_524))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_6_renamed_524))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_6_renamed_524))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_5_renamed_525))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_5_renamed_525))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_5_renamed_525))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_5_renamed_525))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_4_renamed_526))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_4_renamed_526))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_4_renamed_526))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_4_renamed_526))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_3_renamed_527))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_3_renamed_527))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_3_renamed_527))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_3_renamed_527))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_2_renamed_528))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_2_renamed_528))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_2_renamed_528))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_2_renamed_528))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_1_renamed_529))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_1_renamed_529))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_1_renamed_529))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_1_renamed_529))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_0_renamed_530))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_0_renamed_530))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_0_renamed_530))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_0_renamed_530))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_15_renamed_531))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_15_renamed_531))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_15_renamed_531))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_15_renamed_531))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_14_renamed_532))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_14_renamed_532))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_14_renamed_532))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_14_renamed_532))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_13_renamed_533))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_13_renamed_533))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_13_renamed_533))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_13_renamed_533))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_10_renamed_534))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_10_renamed_534))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_10_renamed_534))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_10_renamed_534))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_12_renamed_535))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_12_renamed_535))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_12_renamed_535))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_12_renamed_535))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_11_renamed_536))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_11_renamed_536))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_11_renamed_536))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_11_renamed_536))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_9_renamed_537))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_9_renamed_537))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_9_renamed_537))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_9_renamed_537))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_8_renamed_538))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_8_renamed_538))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_8_renamed_538))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_8_renamed_538))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_7_renamed_539))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_7_renamed_539))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_7_renamed_539))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_7_renamed_539))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_6_renamed_540))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_6_renamed_540))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_6_renamed_540))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_6_renamed_540))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_3_renamed_541))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_3_renamed_541))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_3_renamed_541))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_3_renamed_541))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_5_renamed_542))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_5_renamed_542))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_5_renamed_542))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_5_renamed_542))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_4_renamed_543))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_4_renamed_543))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_4_renamed_543))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_4_renamed_543))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_2_renamed_544))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_2_renamed_544))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_2_renamed_544))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_2_renamed_544))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_1_renamed_545))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_1_renamed_545))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_1_renamed_545))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_1_renamed_545))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_0_renamed_546))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_0_renamed_546))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_0_renamed_546))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_0_renamed_546))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_15_renamed_547))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_15_renamed_547))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_15_renamed_547))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_15_renamed_547))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_12_renamed_548))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_12_renamed_548))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_12_renamed_548))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_12_renamed_548))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_14_renamed_549))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_14_renamed_549))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_14_renamed_549))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_14_renamed_549))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_13_renamed_550))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_13_renamed_550))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_13_renamed_550))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_13_renamed_550))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_11_renamed_551))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_11_renamed_551))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_11_renamed_551))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_11_renamed_551))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_10_renamed_552))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_10_renamed_552))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_10_renamed_552))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_10_renamed_552))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_9_renamed_553))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_9_renamed_553))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_9_renamed_553))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_9_renamed_553))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_8_renamed_554))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_8_renamed_554))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_8_renamed_554))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_8_renamed_554))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_5_renamed_555))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_5_renamed_555))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_5_renamed_555))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_5_renamed_555))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_7_renamed_556))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_7_renamed_556))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_7_renamed_556))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_7_renamed_556))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_6_renamed_557))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_6_renamed_557))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_6_renamed_557))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_6_renamed_557))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_4_renamed_558))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_4_renamed_558))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_4_renamed_558))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_4_renamed_558))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_3_renamed_559))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_3_renamed_559))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_3_renamed_559))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_3_renamed_559))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_2_renamed_560))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_2_renamed_560))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_2_renamed_560))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_2_renamed_560))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_1_renamed_561))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_1_renamed_561))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_1_renamed_561))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_1_renamed_561))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_14_renamed_562))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_14_renamed_562))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_14_renamed_562))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_14_renamed_562))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_0_renamed_563))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_0_renamed_563))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_0_renamed_563))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_0_renamed_563))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_15_renamed_564))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_15_renamed_564))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_15_renamed_564))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_15_renamed_564))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_13_renamed_565))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_13_renamed_565))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_13_renamed_565))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_13_renamed_565))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_12_renamed_566))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_12_renamed_566))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_12_renamed_566))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_12_renamed_566))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_11_renamed_567))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_11_renamed_567))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_11_renamed_567))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_11_renamed_567))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_10_renamed_568))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_10_renamed_568))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_10_renamed_568))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_10_renamed_568))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_7_renamed_569))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_7_renamed_569))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_7_renamed_569))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_7_renamed_569))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_9_renamed_570))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_9_renamed_570))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_9_renamed_570))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_9_renamed_570))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_8_renamed_571))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_8_renamed_571))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_8_renamed_571))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_8_renamed_571))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_6_renamed_572))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_6_renamed_572))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_6_renamed_572))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_6_renamed_572))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_5_renamed_573))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_5_renamed_573))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_5_renamed_573))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_5_renamed_573))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_4_renamed_574))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_4_renamed_574))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_4_renamed_574))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_4_renamed_574))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_3_renamed_575))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_3_renamed_575))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_3_renamed_575))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_3_renamed_575))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_0_renamed_576))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_0_renamed_576))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_0_renamed_576))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_0_renamed_576))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_2_renamed_577))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_2_renamed_577))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_2_renamed_577))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_2_renamed_577))
+                (portRef A0 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_1_renamed_578))
+                (portRef A1 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_1_renamed_578))
+                (portRef A2 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_1_renamed_578))
+                (portRef A3 (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_1_renamed_578))
+              )
+            )
+            (net (rename SPARTAN6PLL_clkfx "SPARTAN6PLL/clkfx")
+              (joined
+                (portRef I (instanceRef SPARTAN6PLL_clkout1_buf))
+                (portRef CLKFX (instanceRef SPARTAN6PLL_dcm_sp_inst))
+              )
+            )
+            (net (rename SPARTAN6PLL_clkin1 "SPARTAN6PLL/clkin1")
+              (joined
+                (portRef CLKIN (instanceRef SPARTAN6PLL_dcm_sp_inst))
+                (portRef O (instanceRef SPARTAN6PLL_clkin1_buf))
+              )
+            )
+            (net (rename Result_0_ "Result<0>")
+              (joined
+                (portRef D (instanceRef prescaler_0))
+                (portRef O (instanceRef Mcount_prescaler_xor_0__))
+              )
+            )
+            (net (rename Result_1_ "Result<1>")
+              (joined
+                (portRef D (instanceRef prescaler_1))
+                (portRef O (instanceRef Mcount_prescaler_xor_1__))
+              )
+            )
+            (net (rename Result_2_ "Result<2>")
+              (joined
+                (portRef D (instanceRef prescaler_2))
+                (portRef O (instanceRef Mcount_prescaler_xor_2__))
+              )
+            )
+            (net (rename Result_3_ "Result<3>")
+              (joined
+                (portRef D (instanceRef prescaler_3))
+                (portRef O (instanceRef Mcount_prescaler_xor_3__))
+              )
+            )
+            (net (rename Result_4_ "Result<4>")
+              (joined
+                (portRef D (instanceRef prescaler_4))
+                (portRef O (instanceRef Mcount_prescaler_xor_4__))
+              )
+            )
+            (net (rename Result_5_ "Result<5>")
+              (joined
+                (portRef D (instanceRef prescaler_5))
+                (portRef O (instanceRef Mcount_prescaler_xor_5__))
+              )
+            )
+            (net (rename Result_6_ "Result<6>")
+              (joined
+                (portRef D (instanceRef prescaler_6))
+                (portRef O (instanceRef Mcount_prescaler_xor_6__))
+              )
+            )
+            (net (rename Result_7_ "Result<7>")
+              (joined
+                (portRef D (instanceRef prescaler_7))
+                (portRef O (instanceRef Mcount_prescaler_xor_7__))
+              )
+            )
+            (net (rename Result_8_ "Result<8>")
+              (joined
+                (portRef D (instanceRef prescaler_8))
+                (portRef O (instanceRef Mcount_prescaler_xor_8__))
+              )
+            )
+            (net (rename Result_9_ "Result<9>")
+              (joined
+                (portRef D (instanceRef prescaler_9))
+                (portRef O (instanceRef Mcount_prescaler_xor_9__))
+              )
+            )
+            (net (rename Result_10_ "Result<10>")
+              (joined
+                (portRef D (instanceRef prescaler_10))
+                (portRef O (instanceRef Mcount_prescaler_xor_10__))
+              )
+            )
+            (net (rename Result_11_ "Result<11>")
+              (joined
+                (portRef D (instanceRef prescaler_11))
+                (portRef O (instanceRef Mcount_prescaler_xor_11__))
+              )
+            )
+            (net (rename Result_12_ "Result<12>")
+              (joined
+                (portRef D (instanceRef prescaler_12))
+                (portRef O (instanceRef Mcount_prescaler_xor_12__))
+              )
+            )
+            (net (rename Result_13_ "Result<13>")
+              (joined
+                (portRef D (instanceRef prescaler_13))
+                (portRef O (instanceRef Mcount_prescaler_xor_13__))
+              )
+            )
+            (net (rename Result_14_ "Result<14>")
+              (joined
+                (portRef D (instanceRef prescaler_14))
+                (portRef O (instanceRef Mcount_prescaler_xor_14__))
+              )
+            )
+            (net (rename Result_15_ "Result<15>")
+              (joined
+                (portRef D (instanceRef prescaler_15))
+                (portRef O (instanceRef Mcount_prescaler_xor_15__))
+              )
+            )
+            (net (rename Result_16_ "Result<16>")
+              (joined
+                (portRef D (instanceRef prescaler_16))
+                (portRef O (instanceRef Mcount_prescaler_xor_16__))
+              )
+            )
+            (net (rename Result_17_ "Result<17>")
+              (joined
+                (portRef D (instanceRef prescaler_17))
+                (portRef O (instanceRef Mcount_prescaler_xor_17__))
+              )
+            )
+            (net (rename Result_18_ "Result<18>")
+              (joined
+                (portRef D (instanceRef prescaler_18))
+                (portRef O (instanceRef Mcount_prescaler_xor_18__))
+              )
+            )
+            (net (rename Result_19_ "Result<19>")
+              (joined
+                (portRef D (instanceRef prescaler_19))
+                (portRef O (instanceRef Mcount_prescaler_xor_19__))
+              )
+            )
+            (net (rename Result_20_ "Result<20>")
+              (joined
+                (portRef D (instanceRef prescaler_20))
+                (portRef O (instanceRef Mcount_prescaler_xor_20__))
+              )
+            )
+            (net (rename Result_21_ "Result<21>")
+              (joined
+                (portRef D (instanceRef prescaler_21))
+                (portRef O (instanceRef Mcount_prescaler_xor_21__))
+              )
+            )
+            (net (rename prescaler_0_ "prescaler<0>")
+              (joined
+                (portRef Q (instanceRef prescaler_0))
+                (portRef I (instanceRef Mcount_prescaler_lut_0__INV_0))
+              )
+            )
+            (net (rename prescaler_1_ "prescaler<1>")
+              (joined
+                (portRef Q (instanceRef prescaler_1))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_1__rt_renamed_379))
+              )
+            )
+            (net (rename prescaler_2_ "prescaler<2>")
+              (joined
+                (portRef Q (instanceRef prescaler_2))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_2__rt_renamed_380))
+              )
+            )
+            (net (rename prescaler_3_ "prescaler<3>")
+              (joined
+                (portRef Q (instanceRef prescaler_3))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_3__rt_renamed_381))
+              )
+            )
+            (net (rename prescaler_4_ "prescaler<4>")
+              (joined
+                (portRef Q (instanceRef prescaler_4))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_4__rt_renamed_382))
+              )
+            )
+            (net (rename prescaler_5_ "prescaler<5>")
+              (joined
+                (portRef Q (instanceRef prescaler_5))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_5__rt_renamed_383))
+              )
+            )
+            (net (rename prescaler_6_ "prescaler<6>")
+              (joined
+                (portRef Q (instanceRef prescaler_6))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_6__rt_renamed_384))
+              )
+            )
+            (net (rename prescaler_7_ "prescaler<7>")
+              (joined
+                (portRef Q (instanceRef prescaler_7))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_7__rt_renamed_385))
+              )
+            )
+            (net (rename prescaler_8_ "prescaler<8>")
+              (joined
+                (portRef Q (instanceRef prescaler_8))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_8__rt_renamed_386))
+              )
+            )
+            (net (rename prescaler_9_ "prescaler<9>")
+              (joined
+                (portRef Q (instanceRef prescaler_9))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_9__rt_renamed_387))
+              )
+            )
+            (net (rename prescaler_10_ "prescaler<10>")
+              (joined
+                (portRef Q (instanceRef prescaler_10))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_10__rt_renamed_388))
+              )
+            )
+            (net (rename prescaler_11_ "prescaler<11>")
+              (joined
+                (portRef Q (instanceRef prescaler_11))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_11__rt_renamed_389))
+              )
+            )
+            (net (rename prescaler_12_ "prescaler<12>")
+              (joined
+                (portRef Q (instanceRef prescaler_12))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_12__rt_renamed_390))
+              )
+            )
+            (net (rename prescaler_13_ "prescaler<13>")
+              (joined
+                (portRef Q (instanceRef prescaler_13))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_13__rt_renamed_391))
+              )
+            )
+            (net (rename prescaler_14_ "prescaler<14>")
+              (joined
+                (portRef Q (instanceRef prescaler_14))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_14__rt_renamed_392))
+              )
+            )
+            (net (rename prescaler_15_ "prescaler<15>")
+              (joined
+                (portRef Q (instanceRef prescaler_15))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_15__rt_renamed_393))
+              )
+            )
+            (net (rename prescaler_16_ "prescaler<16>")
+              (joined
+                (portRef Q (instanceRef prescaler_16))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_16__rt_renamed_394))
+              )
+            )
+            (net (rename prescaler_17_ "prescaler<17>")
+              (joined
+                (portRef Q (instanceRef prescaler_17))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_17__rt_renamed_395))
+              )
+            )
+            (net (rename prescaler_18_ "prescaler<18>")
+              (joined
+                (portRef Q (instanceRef prescaler_18))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_18__rt_renamed_396))
+              )
+            )
+            (net (rename prescaler_19_ "prescaler<19>")
+              (joined
+                (portRef Q (instanceRef prescaler_19))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_19__rt_renamed_397))
+              )
+            )
+            (net (rename prescaler_20_ "prescaler<20>")
+              (joined
+                (portRef Q (instanceRef prescaler_20))
+                (portRef I0 (instanceRef Mcount_prescaler_cy_20__rt_renamed_398))
+              )
+            )
+            (net (rename Mcount_prescaler_lut_0_ "Mcount_prescaler_lut<0>")
+              (joined
+                (portRef S (instanceRef Mcount_prescaler_cy_0__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_0__))
+                (portRef O (instanceRef Mcount_prescaler_lut_0__INV_0))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_0_ "Mcount_prescaler_cy<0>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_0__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_1__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_1__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_1_ "Mcount_prescaler_cy<1>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_1__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_2__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_2__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_2_ "Mcount_prescaler_cy<2>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_2__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_3__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_3__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_3_ "Mcount_prescaler_cy<3>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_3__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_4__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_4__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_4_ "Mcount_prescaler_cy<4>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_4__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_5__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_5__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_5_ "Mcount_prescaler_cy<5>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_5__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_6__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_6__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_6_ "Mcount_prescaler_cy<6>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_6__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_7__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_7__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_7_ "Mcount_prescaler_cy<7>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_7__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_8__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_8__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_8_ "Mcount_prescaler_cy<8>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_8__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_9__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_9__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_9_ "Mcount_prescaler_cy<9>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_9__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_10__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_10__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_10_ "Mcount_prescaler_cy<10>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_10__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_11__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_11__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_11_ "Mcount_prescaler_cy<11>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_11__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_12__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_12__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_12_ "Mcount_prescaler_cy<12>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_12__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_13__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_13__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_13_ "Mcount_prescaler_cy<13>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_13__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_14__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_14__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_14_ "Mcount_prescaler_cy<14>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_14__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_15__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_15__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_15_ "Mcount_prescaler_cy<15>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_15__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_16__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_16__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_16_ "Mcount_prescaler_cy<16>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_16__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_17__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_17__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_17_ "Mcount_prescaler_cy<17>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_17__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_18__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_18__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_18_ "Mcount_prescaler_cy<18>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_18__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_19__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_19__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_19_ "Mcount_prescaler_cy<19>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_19__))
+                (portRef CI (instanceRef Mcount_prescaler_cy_20__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_20__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_20_ "Mcount_prescaler_cy<20>")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_20__))
+                (portRef CI (instanceRef Mcount_prescaler_xor_21__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_21 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<0>21")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_21_renamed_456))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_22))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_31))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__dtr_int_Select_189_o12 "BIU_CORE/biu_state[7]_dtr_int_Select_189_o12")
+              (joined
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_192_o1))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o121))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_3 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>3")
+              (joined
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_186_o_SW0))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_2_renamed_269))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_3_renamed_457))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3__))
+              )
+            )
+            (net (rename BIU_CORE__n11412 "BIU_CORE/_n11412")
+              (joined
+                (portRef O (instanceRef BIU_CORE__n114121))
+                (portRef I4 (instanceRef BIU_CORE__n11741))
+                (portRef I5 (instanceRef BIU_CORE__n11411))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<0>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_22))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_4))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_4))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_4))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_4_renamed_282))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3_1 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<3>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3_11))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_2_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_7_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_6_1))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_5__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_4__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<10>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_31))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_3))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_3))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_3))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_3))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_4))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_4))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_4))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_4))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_4))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_4))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_4))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_4))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_4))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_4))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_4))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_4_renamed_329))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_equal_176_o_7_2 "BIU_CORE/biu_state[7]_GND_14_o_equal_176_o<7>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_176_o_7_21))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_173_o_7_11))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_111))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_1_SW0))
+                (portRef I1 (instanceRef BIU_CORE__n11521))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_170_o_7_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o113))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_1_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_173_o_7_2))
+                (portRef I2 (instanceRef BIU_CORE__n114121))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_212_renamed_449))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_174_o_7_1))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o112))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_11 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<10>11")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_111))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_22))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_31))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_equal_173_o_7_1 "BIU_CORE/biu_state[7]_GND_14_o_equal_173_o<7>1")
+              (joined
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o2_renamed_265))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_186_o_renamed_268))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o1_renamed_283))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_173_o_7_11))
+                (portRef I4 (instanceRef BIU_CORE__n114121))
+                (portRef I4 (instanceRef BIU_CORE_out21))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o11_renamed_272))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_212_renamed_449))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_equal_176_o_7_1 "BIU_CORE/biu_state[7]_GND_14_o_equal_176_o<7>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_176_o_7_11))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o2_renamed_265))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o3_renamed_266))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o113))
+                (portRef I3 (instanceRef BIU_CORE__n114121))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o11_renamed_272))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_111))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_212_renamed_449))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_11 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>11")
+              (joined
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_186_o_renamed_268))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_4_renamed_270))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_1_renamed_271))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_111))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o11_renamed_272))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__inta_n_int_Select_202_o2 "BIU_CORE/biu_state[7]_inta_n_int_Select_202_o2")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_latched_data_in_0))
+                (portRef CE (instanceRef BIU_CORE_latched_data_in_1))
+                (portRef CE (instanceRef BIU_CORE_latched_data_in_2))
+                (portRef CE (instanceRef BIU_CORE_latched_data_in_3))
+                (portRef CE (instanceRef BIU_CORE_latched_data_in_4))
+                (portRef CE (instanceRef BIU_CORE_latched_data_in_5))
+                (portRef CE (instanceRef BIU_CORE_latched_data_in_6))
+                (portRef CE (instanceRef BIU_CORE_latched_data_in_7))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o21))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_21 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>21")
+              (joined
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_1_renamed_263))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_5))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_213))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_2 "BIU_CORE/biu_state[7]_GND_14_o_equal_166_o<7>2")
+              (joined
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0_11))
+                (portRef I2 (instanceRef BIU_CORE_out21))
+                (portRef I0 (instanceRef BIU_CORE__n11741))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_1_renamed_259))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_172_o_7_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_167_o_7_1))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o1_renamed_283))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o2))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3_11))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o121))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_21))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_21_renamed_456))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_3_renamed_457))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o21))
+                (portRef I0 (instanceRef BIU_CORE__n1076_inv_renamed_458))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_111))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_21))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o3))
+                (portRef I3 (instanceRef BIU_CORE_iom_int_rstpot_renamed_462))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_22))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_10_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_1 "BIU_CORE/biu_state[7]_GND_14_o_equal_166_o<7>1")
+              (joined
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_169_o_7_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o2_renamed_265))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o3_renamed_266))
+                (portRef I0 (instanceRef BIU_CORE__n11411))
+                (portRef I1 (instanceRef BIU_CORE_ale_int_rstpot_renamed_455))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o113_SW0))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<10>2")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_4))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_4))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_3))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_3))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_3))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_3))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_1_renamed_293))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_1_renamed_296))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_1_renamed_299))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_1_renamed_302))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_1_renamed_305))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_1_renamed_308))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_1_renamed_311))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_1_renamed_314))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_1_renamed_317))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_1_renamed_320))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_1_renamed_323))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_1_renamed_326))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_21))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_4))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_4_renamed_282))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__den_int_Select_196_o11 "BIU_CORE/biu_state[7]_den_int_Select_196_o11")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o4))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_186_o_renamed_268))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o113))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__dtr_int_Select_189_o11 "BIU_CORE/biu_state[7]_dtr_int_Select_189_o11")
+              (joined
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_198_o_renamed_267))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o11_renamed_272))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o_renamed_447))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__rd_n_int_Select_200_o_renamed_448))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o121))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_Select_180_o11 "BIU_CORE/biu_state[7]_GND_14_o_Select_180_o11")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_178_o1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o1_renamed_283))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o112))
+                (portRef I3 (instanceRef BIU_CORE_out21))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_1 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>1")
+              (joined
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_5))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3__))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_1_renamed_271))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_3))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_2_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_7_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_6_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_5__))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_4__))
+              )
+            )
+            (net (rename BIU_CORE_eu_biu_req_code_4__GND_14_o_select_117_OUT_0_1 "BIU_CORE/eu_biu_req_code[4]_GND_14_o_select_117_OUT<0>1")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_1_renamed_285))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_1_renamed_287))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_1_renamed_289))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_1_renamed_291))
+                (portRef O (instanceRef BIU_CORE_eu_biu_req_code_4__GND_14_o_select_117_OUT_0_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<0>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0_11))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_7__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_6__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_5__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_4__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_3__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_2__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_1__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_10_1 "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<10>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_10_11))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_8_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_9_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_10_1_renamed_260))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_11_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_12_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_13_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_14_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_15_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_16_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_17_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_18_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_19_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_1 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<0>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_1_renamed_263))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_3))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3_11))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_18_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<18>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_19__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_17_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<17>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_17__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_18__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_16_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<16>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_16__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_17__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_17__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_15_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_15__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_16__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_16__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_15_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_15__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_15__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_14_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_15__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_14_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_14__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_14__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_13_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_13_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_13__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_13__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_12_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_12_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_12__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_12__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_11_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_11_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_11__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_11__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_10_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_10_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_10__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_10__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_9_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_9_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_9__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_9__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_8_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_8_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_8__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_8__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_7_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_7_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_7__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_7__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_6_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_6_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_6__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_6__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_5_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_5_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_5__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_5__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_4_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_cy<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_4_ "BIU_CORE/Madd_biu_muxed_segment[15]_GND_14_o_add_96_OUT_lut<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_4__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_4__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_14_ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_13_ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_12_ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_11_ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_10_ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_9_ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_8_ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_7_ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_6_ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_5_ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_4_ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_3_ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<3>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_3__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_2_ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<2>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_2__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_3__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_3__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_1_ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<1>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_1__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_2__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_2__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_0_ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<0>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_0__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_1__))
+                (portRef CI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_1__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_lut_0_ "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_lut<0>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_0__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_0__))
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_lut_0__INV_0))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_18_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<18>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_19__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_17_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<17>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_17__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_18__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_16_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<16>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_16__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_17__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_17__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_15_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_15__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_16__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_16__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_15_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_15__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_15__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_14_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_15__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_14_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_14__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_14__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_13_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_13_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_13__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_13__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_12_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_12_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_12__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_12__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_11_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_11_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_11__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_11__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_10_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_10_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_10__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_10__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_9_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_9_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_9__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_9__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_8_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_8_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_8__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_8__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_7_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_7_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_7__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_7__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_6_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_6_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_6__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_6__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_5_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_5_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_5__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_5__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_4_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_4_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_lut<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_4__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_4__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_18_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<18>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_19__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_17_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<17>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_17__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_18__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_16_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<16>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_16__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_17__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_17__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_15_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_15__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_16__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_16__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_15_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_15__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_15__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_14_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_15__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_14_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_14__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_14__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_13_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_13_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_13__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_13__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_12_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_12_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_12__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_12__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_11_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_11_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_11__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_11__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_10_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_10_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_10__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_10__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_9_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_9_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_9__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_9__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_8_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_8_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_8__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_8__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_7_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_7_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_7__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_7__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_6_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_6_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_6__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_6__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_5_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_5_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_5__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_5__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_4_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_4_ "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_lut<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_4__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_4__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_18_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<18>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_19__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_17_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<17>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_17__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_18__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_18__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_16_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<16>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_16__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_17__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_17__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_15_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_15__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_16__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_16__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_15_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_15__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_15__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_14_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_15__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_14_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_14__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_14__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_13_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_13_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_13__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_13__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_12_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_12_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_12__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_12__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_11_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_11_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_11__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_11__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_10_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_10_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_10__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_10__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_9_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_9_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_9__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_9__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_8_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_8_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_8__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_8__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_7_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_7_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_7__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_7__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_6_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_6_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_6__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_6__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_5_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_5_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_5__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_5__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_4_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_4_ "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_lut<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_4__))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_4__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7_ "BIU_CORE/biu_state<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_state_7))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_7_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_21))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_11))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o11_SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_176_o_7_21))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_6_ "BIU_CORE/biu_state<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_state_6))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_6_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_176_o_7_21))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_21))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_11))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o11_SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_7_1))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_state_7__GND_14_o_add_93_OUT_cy_5_ "BIU_CORE/Madd_biu_state[7]_GND_14_o_add_93_OUT_cy<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_state_7__GND_14_o_add_93_OUT_cy_5_11))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_7_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_6_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_5_ "BIU_CORE/biu_state<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_state_5))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_state_7__GND_14_o_add_93_OUT_cy_5_11))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_21))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_11))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o11_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_176_o_7_21))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_5__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_4_ "BIU_CORE/biu_state<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_state_4))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_state_7__GND_14_o_add_93_OUT_cy_5_11))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_5__SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_173_o_7_11))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_1_SW0))
+                (portRef I0 (instanceRef BIU_CORE__n11521))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_21))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_170_o_7_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o113))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_1_SW0))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_173_o_7_2))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_11))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o11_SW0))
+                (portRef I0 (instanceRef BIU_CORE__n114121))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_4__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_111))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_212_renamed_449))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_174_o_7_1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o112))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_3_ "BIU_CORE/biu_state<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_state_3))
+                (portRef I2 (instanceRef BIU_CORE_Madd_biu_state_7__GND_14_o_add_93_OUT_cy_5_11))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_169_o_7_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0_11))
+                (portRef I1 (instanceRef BIU_CORE__n11741))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_176_o_7_11))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_1_renamed_259))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_172_o_7_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_167_o_7_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o1_renamed_283))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o2))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o1_renamed_284))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_173_o_7_11))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3_11))
+                (portRef I1 (instanceRef BIU_CORE__n11411))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_1_SW0))
+                (portRef I5 (instanceRef BIU_CORE__n11521))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_170_o_7_1))
+                (portRef I2 (instanceRef BIU_CORE_ale_int_rstpot_renamed_455))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o113_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_21_renamed_456))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_3_renamed_457))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_1_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o21))
+                (portRef I2 (instanceRef BIU_CORE__n1076_inv_renamed_458))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_173_o_7_2))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_111))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_21))
+                (portRef I1 (instanceRef BIU_CORE_iom_int_rstpot_renamed_462))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_22))
+                (portRef I0 (instanceRef BIU_CORE_out21))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_10_11))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_5__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_4__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o121))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_174_o_7_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o3))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o112))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_2_ "BIU_CORE/biu_state<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_state_2))
+                (portRef I3 (instanceRef BIU_CORE_Madd_biu_state_7__GND_14_o_add_93_OUT_cy_5_11))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_169_o_7_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o2_renamed_265))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o3_renamed_266))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_5__SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_4__SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3__SW0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_211_renamed_273))
+                (portRef I4 (instanceRef BIU_CORE__n1063_inv_SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_173_o_7_11))
+                (portRef I4 (instanceRef BIU_CORE__n11411))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_1_SW0))
+                (portRef I3 (instanceRef BIU_CORE__n11521))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_21))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_170_o_7_1))
+                (portRef I1 (instanceRef BIU_CORE_ale_int_rstpot_SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o113))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_1_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_173_o_7_2))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o11_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o112))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_2_1))
+                (portRef I1 (instanceRef BIU_CORE__n114121))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_111))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_174_o_7_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_1_ "BIU_CORE/biu_state<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_state_1))
+                (portRef I4 (instanceRef BIU_CORE_Madd_biu_state_7__GND_14_o_add_93_OUT_cy_5_11))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_169_o_7_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_22))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0_11))
+                (portRef I2 (instanceRef BIU_CORE__n11741))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_176_o_7_11))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_1_renamed_259))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_172_o_7_1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_167_o_7_1))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o2_renamed_265))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_186_o_renamed_268))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_5))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o1_renamed_283))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o2))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o1_renamed_284))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3_11))
+                (portRef I2 (instanceRef BIU_CORE__n11411))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_1_SW0))
+                (portRef I4 (instanceRef BIU_CORE__n11521))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_170_o_7_1))
+                (portRef I3 (instanceRef BIU_CORE_ale_int_rstpot_renamed_455))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o113_SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_21_renamed_456))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_3_renamed_457))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_1_SW0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o21))
+                (portRef I1 (instanceRef BIU_CORE__n1076_inv_renamed_458))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_173_o_7_2))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_111))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_21))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o3))
+                (portRef I2 (instanceRef BIU_CORE_iom_int_rstpot_renamed_462))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_2_1))
+                (portRef I1 (instanceRef BIU_CORE_out21))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_10_11))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_5__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_4__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o121))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_174_o_7_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o112))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_0_ "BIU_CORE/biu_state<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_state_0))
+                (portRef I5 (instanceRef BIU_CORE_Madd_biu_state_7__GND_14_o_add_93_OUT_cy_5_11))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_169_o_7_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_176_o_7_11))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_5))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_5__SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_4__SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3__SW0))
+                (portRef I3 (instanceRef BIU_CORE__n1063_inv_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_2_renamed_330))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_3))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_173_o_7_11))
+                (portRef I3 (instanceRef BIU_CORE__n11411))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_1_SW0))
+                (portRef I2 (instanceRef BIU_CORE__n11521))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_21))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_170_o_7_1))
+                (portRef I0 (instanceRef BIU_CORE_ale_int_rstpot_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o113_SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_1_SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_173_o_7_2))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_2_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_174_o_7_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o112))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_15_ "BIU_CORE/Mcount_pfq_addr_in_lut<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_15__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in15 "BIU_CORE/Mcount_pfq_addr_in15")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_15__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_15))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_14_ "BIU_CORE/Mcount_pfq_addr_in_cy<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_14_ "BIU_CORE/Mcount_pfq_addr_in_lut<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_14__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_14__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in14 "BIU_CORE/Mcount_pfq_addr_in14")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_14__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_14))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_13_ "BIU_CORE/Mcount_pfq_addr_in_cy<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_13_ "BIU_CORE/Mcount_pfq_addr_in_lut<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_13__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_13__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in13 "BIU_CORE/Mcount_pfq_addr_in13")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_13__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_13))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_12_ "BIU_CORE/Mcount_pfq_addr_in_cy<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_12_ "BIU_CORE/Mcount_pfq_addr_in_lut<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_12__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_12__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in12 "BIU_CORE/Mcount_pfq_addr_in12")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_12__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_12))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_11_ "BIU_CORE/Mcount_pfq_addr_in_cy<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_11_ "BIU_CORE/Mcount_pfq_addr_in_lut<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_11__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_11__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in11 "BIU_CORE/Mcount_pfq_addr_in11")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_11__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_11))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_10_ "BIU_CORE/Mcount_pfq_addr_in_cy<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_10_ "BIU_CORE/Mcount_pfq_addr_in_lut<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_10__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_10__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in10 "BIU_CORE/Mcount_pfq_addr_in10")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_10__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_10))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_9_ "BIU_CORE/Mcount_pfq_addr_in_cy<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_9_ "BIU_CORE/Mcount_pfq_addr_in_lut<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_9__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_9__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in9 "BIU_CORE/Mcount_pfq_addr_in9")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_9__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_9))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_8_ "BIU_CORE/Mcount_pfq_addr_in_cy<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_8_ "BIU_CORE/Mcount_pfq_addr_in_lut<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_8__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_8__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in8 "BIU_CORE/Mcount_pfq_addr_in8")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_8__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_8))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_7_ "BIU_CORE/Mcount_pfq_addr_in_cy<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_7_ "BIU_CORE/Mcount_pfq_addr_in_lut<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_7__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_7__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in7 "BIU_CORE/Mcount_pfq_addr_in7")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_7__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_7))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_6_ "BIU_CORE/Mcount_pfq_addr_in_cy<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_6_ "BIU_CORE/Mcount_pfq_addr_in_lut<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_6__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_6__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in6 "BIU_CORE/Mcount_pfq_addr_in6")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_6__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_6))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_5_ "BIU_CORE/Mcount_pfq_addr_in_cy<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_5_ "BIU_CORE/Mcount_pfq_addr_in_lut<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_5__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_5__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in5 "BIU_CORE/Mcount_pfq_addr_in5")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_5__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_5))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_4_ "BIU_CORE/Mcount_pfq_addr_in_cy<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_4_ "BIU_CORE/Mcount_pfq_addr_in_lut<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_4__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_4__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in4 "BIU_CORE/Mcount_pfq_addr_in4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_4__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_4))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_3_ "BIU_CORE/Mcount_pfq_addr_in_cy<3>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_3__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_3_ "BIU_CORE/Mcount_pfq_addr_in_lut<3>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_3__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_3__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_3__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in3 "BIU_CORE/Mcount_pfq_addr_in3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_3__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_3))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_2_ "BIU_CORE/Mcount_pfq_addr_in_cy<2>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_2__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_3__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_3__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_2_ "BIU_CORE/Mcount_pfq_addr_in_lut<2>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_2__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_2__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_2__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in2 "BIU_CORE/Mcount_pfq_addr_in2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_2__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_2))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_1_ "BIU_CORE/Mcount_pfq_addr_in_cy<1>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_1__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_2__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_2__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_1_ "BIU_CORE/Mcount_pfq_addr_in_lut<1>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_1__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_1__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_1__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in1 "BIU_CORE/Mcount_pfq_addr_in1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_1__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_1))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_cy_0_ "BIU_CORE/Mcount_pfq_addr_in_cy<0>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_0__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_1__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_1__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in_lut_0_ "BIU_CORE/Mcount_pfq_addr_in_lut<0>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_0__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_0__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_0__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_in "BIU_CORE/Mcount_pfq_addr_in")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_0__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_in_0))
+              )
+            )
+            (net (rename BIU_CORE__n1036_inv "BIU_CORE/_n1036_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_0))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_1))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_2))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_3))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_4))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_5))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_6))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_7))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_8))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_9))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_10))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_11))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_12))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_13))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_14))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_in_15))
+                (portRef O (instanceRef BIU_CORE__n1036_inv1))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_15_ "BIU_CORE/Mcount_pfq_addr_out_lut<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_15__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out15 "BIU_CORE/Mcount_pfq_addr_out15")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_15__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_15))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_14_ "BIU_CORE/Mcount_pfq_addr_out_cy<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_14_ "BIU_CORE/Mcount_pfq_addr_out_lut<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_14__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_14__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out14 "BIU_CORE/Mcount_pfq_addr_out14")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_14__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_14))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_13_ "BIU_CORE/Mcount_pfq_addr_out_cy<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_14__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_13_ "BIU_CORE/Mcount_pfq_addr_out_lut<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_13__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_13__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out13 "BIU_CORE/Mcount_pfq_addr_out13")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_13__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_13))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_12_ "BIU_CORE/Mcount_pfq_addr_out_cy<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_13__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_12_ "BIU_CORE/Mcount_pfq_addr_out_lut<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_12__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_12__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out12 "BIU_CORE/Mcount_pfq_addr_out12")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_12__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_12))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_11_ "BIU_CORE/Mcount_pfq_addr_out_cy<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_12__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_11_ "BIU_CORE/Mcount_pfq_addr_out_lut<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_11__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_11__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out11 "BIU_CORE/Mcount_pfq_addr_out11")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_11__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_11))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_10_ "BIU_CORE/Mcount_pfq_addr_out_cy<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_10_ "BIU_CORE/Mcount_pfq_addr_out_lut<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_10__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_10__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out10 "BIU_CORE/Mcount_pfq_addr_out10")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_10__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_10))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_9_ "BIU_CORE/Mcount_pfq_addr_out_cy<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_9_ "BIU_CORE/Mcount_pfq_addr_out_lut<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_9__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_9__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out9 "BIU_CORE/Mcount_pfq_addr_out9")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_9__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_9))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_8_ "BIU_CORE/Mcount_pfq_addr_out_cy<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_8_ "BIU_CORE/Mcount_pfq_addr_out_lut<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_8__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_8__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out8 "BIU_CORE/Mcount_pfq_addr_out8")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_8__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_8))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_7_ "BIU_CORE/Mcount_pfq_addr_out_cy<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_7_ "BIU_CORE/Mcount_pfq_addr_out_lut<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_7__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_7__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out7 "BIU_CORE/Mcount_pfq_addr_out7")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_7__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_7))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_6_ "BIU_CORE/Mcount_pfq_addr_out_cy<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_6_ "BIU_CORE/Mcount_pfq_addr_out_lut<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_6__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_6__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out6 "BIU_CORE/Mcount_pfq_addr_out6")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_6__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_6))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_5_ "BIU_CORE/Mcount_pfq_addr_out_cy<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_5_ "BIU_CORE/Mcount_pfq_addr_out_lut<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_5__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_5__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out5 "BIU_CORE/Mcount_pfq_addr_out5")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_5__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_5))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_4_ "BIU_CORE/Mcount_pfq_addr_out_cy<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_4_ "BIU_CORE/Mcount_pfq_addr_out_lut<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_4__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_4__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out4 "BIU_CORE/Mcount_pfq_addr_out4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_4__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_4))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_3_ "BIU_CORE/Mcount_pfq_addr_out_cy<3>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_3__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_3_ "BIU_CORE/Mcount_pfq_addr_out_lut<3>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_3__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_3__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_3__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out3 "BIU_CORE/Mcount_pfq_addr_out3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_3__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_3))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_2_ "BIU_CORE/Mcount_pfq_addr_out_cy<2>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_2__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_3__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_3__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_2_ "BIU_CORE/Mcount_pfq_addr_out_lut<2>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_2__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_2__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_2__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out2 "BIU_CORE/Mcount_pfq_addr_out2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_2__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_2))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_1_ "BIU_CORE/Mcount_pfq_addr_out_cy<1>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_1__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_2__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_2__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_1_ "BIU_CORE/Mcount_pfq_addr_out_lut<1>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_1__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_1__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_1__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out1 "BIU_CORE/Mcount_pfq_addr_out1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_1__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_1))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_cy_0_ "BIU_CORE/Mcount_pfq_addr_out_cy<0>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_0__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_1__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_1__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out_lut_0_ "BIU_CORE/Mcount_pfq_addr_out_lut<0>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_0__))
+                (portRef S (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_0__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_0__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_pfq_addr_out "BIU_CORE/Mcount_pfq_addr_out")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_0__))
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_0))
+              )
+            )
+            (net (rename BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_15_o_inv "BIU_CORE/eu_biu_req_caught_eu_biu_req_code[4]_AND_15_o_inv")
+              (joined
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_cy_0__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_out_xor_0__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_cy_0__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_pfq_addr_in_xor_0__))
+                (portRef O (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_15_o_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n1017_inv "BIU_CORE/_n1017_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_0))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_1))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_2))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_3))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_4))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_5))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_6))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_7))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_8))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_9))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_10))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_11))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_12))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_13))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_14))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_15))
+                (portRef O (instanceRef BIU_CORE__n1017_inv1))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_12_ "BIU_CORE/Mcount_clock_cycle_counter_lut<12>")
+              (joined
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_12__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_12__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter12 "BIU_CORE/Mcount_clock_cycle_counter12")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_12__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_12))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_11_ "BIU_CORE/Mcount_clock_cycle_counter_cy<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_11_ "BIU_CORE/Mcount_clock_cycle_counter_lut<11>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_11__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_11__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_11__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter11 "BIU_CORE/Mcount_clock_cycle_counter11")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_11__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_11))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_10_ "BIU_CORE/Mcount_clock_cycle_counter_cy<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_11__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_10_ "BIU_CORE/Mcount_clock_cycle_counter_lut<10>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_10__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_10__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_10__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter10 "BIU_CORE/Mcount_clock_cycle_counter10")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_10__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_10))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_9_ "BIU_CORE/Mcount_clock_cycle_counter_cy<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_10__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_9_ "BIU_CORE/Mcount_clock_cycle_counter_lut<9>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_9__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_9__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_9__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter9 "BIU_CORE/Mcount_clock_cycle_counter9")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_9__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_9))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_8_ "BIU_CORE/Mcount_clock_cycle_counter_cy<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_9__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_8_ "BIU_CORE/Mcount_clock_cycle_counter_lut<8>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_8__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_8__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_8__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter8 "BIU_CORE/Mcount_clock_cycle_counter8")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_8__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_8))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_7_ "BIU_CORE/Mcount_clock_cycle_counter_cy<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_8__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_7_ "BIU_CORE/Mcount_clock_cycle_counter_lut<7>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_7__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_7__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_7__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter7 "BIU_CORE/Mcount_clock_cycle_counter7")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_7__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_7))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_6_ "BIU_CORE/Mcount_clock_cycle_counter_cy<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_7__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_6_ "BIU_CORE/Mcount_clock_cycle_counter_lut<6>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_6__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_6__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_6__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter6 "BIU_CORE/Mcount_clock_cycle_counter6")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_6__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_6))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_5_ "BIU_CORE/Mcount_clock_cycle_counter_cy<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_6__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_5_ "BIU_CORE/Mcount_clock_cycle_counter_lut<5>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_5__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_5__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_5__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter5 "BIU_CORE/Mcount_clock_cycle_counter5")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_5__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_5))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_4_ "BIU_CORE/Mcount_clock_cycle_counter_cy<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_5__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_4_ "BIU_CORE/Mcount_clock_cycle_counter_lut<4>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_4__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_4__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_4__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter4 "BIU_CORE/Mcount_clock_cycle_counter4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_4__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_4))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_3_ "BIU_CORE/Mcount_clock_cycle_counter_cy<3>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_3__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_4__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_3_ "BIU_CORE/Mcount_clock_cycle_counter_lut<3>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_3__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_3__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_3__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter3 "BIU_CORE/Mcount_clock_cycle_counter3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_3__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_3))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_2_ "BIU_CORE/Mcount_clock_cycle_counter_cy<2>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_2__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_3__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_3__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_2_ "BIU_CORE/Mcount_clock_cycle_counter_lut<2>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_2__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_2__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_2__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter2 "BIU_CORE/Mcount_clock_cycle_counter2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_2__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_2))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_1_ "BIU_CORE/Mcount_clock_cycle_counter_cy<1>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_1__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_2__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_2__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_1_ "BIU_CORE/Mcount_clock_cycle_counter_lut<1>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_1__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_1__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_1__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter1 "BIU_CORE/Mcount_clock_cycle_counter1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_1__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_1))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_cy_0_ "BIU_CORE/Mcount_clock_cycle_counter_cy<0>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_0__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_1__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_1__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter_lut_0_ "BIU_CORE/Mcount_clock_cycle_counter_lut<0>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_0__))
+                (portRef LI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_0__))
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_0__))
+              )
+            )
+            (net (rename BIU_CORE_Mcount_clock_cycle_counter "BIU_CORE/Mcount_clock_cycle_counter")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_0__))
+                (portRef D (instanceRef BIU_CORE_clock_cycle_counter_0))
+              )
+            )
+            (net (rename BIU_CORE__n1014_inv "BIU_CORE/_n1014_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_0))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_1))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_2))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_3))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_4))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_5))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_6))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_7))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_8))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_9))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_10))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_11))
+                (portRef CE (instanceRef BIU_CORE_clock_cycle_counter_12))
+                (portRef O (instanceRef BIU_CORE__n1014_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n1076_inv "BIU_CORE/_n1076_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_s_bits_0))
+                (portRef CE (instanceRef BIU_CORE_s_bits_1))
+                (portRef CE (instanceRef BIU_CORE_s_bits_2))
+                (portRef O (instanceRef BIU_CORE__n1076_inv_renamed_458))
+              )
+            )
+            (net (rename BIU_CORE__n1033_inv "BIU_CORE/_n1033_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_pfq_entry3_0))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry3_1))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry3_2))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry3_3))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry3_4))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry3_5))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry3_6))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry3_7))
+                (portRef O (instanceRef BIU_CORE__n1033_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n1029_inv "BIU_CORE/_n1029_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_pfq_entry2_0))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry2_1))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry2_2))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry2_3))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry2_4))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry2_5))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry2_6))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry2_7))
+                (portRef O (instanceRef BIU_CORE__n1029_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n1021_inv "BIU_CORE/_n1021_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_pfq_entry0_0))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry0_1))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry0_2))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry0_3))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry0_4))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry0_5))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry0_6))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry0_7))
+                (portRef O (instanceRef BIU_CORE__n1021_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n1025_inv "BIU_CORE/_n1025_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_pfq_entry1_0))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry1_1))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry1_2))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry1_3))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry1_4))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry1_5))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry1_6))
+                (portRef CE (instanceRef BIU_CORE_pfq_entry1_7))
+                (portRef O (instanceRef BIU_CORE__n1025_inv1))
+              )
+            )
+            (net (rename BIU_CORE_RESET_INT_inv "BIU_CORE/RESET_INT_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_pfq_top_byte_int_d1_0))
+                (portRef CE (instanceRef BIU_CORE_pfq_top_byte_int_d1_1))
+                (portRef CE (instanceRef BIU_CORE_pfq_top_byte_int_d1_2))
+                (portRef CE (instanceRef BIU_CORE_pfq_top_byte_int_d1_3))
+                (portRef CE (instanceRef BIU_CORE_pfq_top_byte_int_d1_4))
+                (portRef CE (instanceRef BIU_CORE_pfq_top_byte_int_d1_5))
+                (portRef CE (instanceRef BIU_CORE_pfq_top_byte_int_d1_6))
+                (portRef CE (instanceRef BIU_CORE_pfq_top_byte_int_d1_7))
+                (portRef CE (instanceRef BIU_CORE_ALE_renamed_4))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_0))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_1))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_2))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_3))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_4))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_5))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_6))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_7))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_8))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_9))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_10))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_11))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_12))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_13))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_14))
+                (portRef CE (instanceRef BIU_CORE_pfq_addr_out_d1_15))
+                (portRef O (instanceRef BIU_CORE_RESET_INT_inv1_INV_0))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_15_renamed_467))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_15))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_14_renamed_468))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_14))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_13_renamed_469))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_13))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_12_renamed_470))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_12))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_11_renamed_471))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_11))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_10_renamed_472))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_10))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_9_renamed_473))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_9))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_8_renamed_474))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_8))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_7_renamed_475))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_7))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_6_renamed_476))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_6))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_3_renamed_477))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_3))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_5_renamed_478))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_5))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_4_renamed_479))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_4))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_2_renamed_480))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_2))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_1_renamed_481))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_1))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_0_renamed_482))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_d2_0))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_15_renamed_483))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_15))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_12_renamed_484))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_12))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_14_renamed_485))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_14))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_13_renamed_486))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_13))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_11_renamed_487))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_11))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_10_renamed_488))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_10))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_9_renamed_489))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_9))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_8_renamed_490))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_8))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_5_renamed_491))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_5))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_7_renamed_492))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_7))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_6_renamed_493))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_6))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_4_renamed_494))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_4))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_3_renamed_495))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_3))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_2_renamed_496))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_2))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_1_renamed_497))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_1))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_14_renamed_498))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_14))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_0_renamed_499))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_d2_0))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_15_renamed_500))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_15))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_13_renamed_501))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_13))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_12_renamed_502))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_12))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_11_renamed_503))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_11))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_10_renamed_504))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_10))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_7_renamed_505))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_7))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_9_renamed_506))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_9))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_8_renamed_507))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_8))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_6_renamed_508))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_6))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_5_renamed_509))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_5))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_4_renamed_510))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_4))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_3_renamed_511))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_3))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_0_renamed_512))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_0))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_2_renamed_513))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_2))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_1_renamed_514))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_d2_1))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_15_renamed_515))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_15))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_14_renamed_516))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_14))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_13_renamed_517))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_13))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_12_renamed_518))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_12))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_9_renamed_519))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_9))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_11_renamed_520))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_11))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_10_renamed_521))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_10))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_8_renamed_522))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_8))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_7_renamed_523))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_7))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_6_renamed_524))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_6))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_5_renamed_525))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_5))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_4_renamed_526))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_4))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_3_renamed_527))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_3))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_2_renamed_528))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_2))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_1_renamed_529))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_1))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_0_renamed_530))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_d2_0))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_15_renamed_531))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_15))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_14_renamed_532))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_14))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_13_renamed_533))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_13))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_10_renamed_534))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_10))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_12_renamed_535))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_12))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_11_renamed_536))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_11))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_9_renamed_537))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_9))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_8_renamed_538))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_8))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_7_renamed_539))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_7))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_6_renamed_540))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_6))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_3_renamed_541))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_3))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_5_renamed_542))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_5))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_4_renamed_543))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_4))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_2_renamed_544))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_2))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_1_renamed_545))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_1))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_0_renamed_546))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_d2_0))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_15_renamed_547))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_15))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_12_renamed_548))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_12))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_14_renamed_549))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_14))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_13_renamed_550))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_13))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_11_renamed_551))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_11))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_10_renamed_552))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_10))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_9_renamed_553))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_9))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_8_renamed_554))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_8))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_5_renamed_555))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_5))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_7_renamed_556))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_7))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_6_renamed_557))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_6))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_4_renamed_558))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_4))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_3_renamed_559))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_3))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_2_renamed_560))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_2))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_1_renamed_561))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_1))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_14_renamed_562))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_14))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_0_renamed_563))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_d2_0))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_15_renamed_564))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_15))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_13_renamed_565))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_13))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_12_renamed_566))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_12))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_11_renamed_567))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_11))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_10_renamed_568))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_10))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_7_renamed_569))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_7))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_9_renamed_570))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_9))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_8_renamed_571))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_8))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_6_renamed_572))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_6))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_5_renamed_573))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_5))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_4_renamed_574))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_4))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_3_renamed_575))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_3))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_0_renamed_576))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_0))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_2_renamed_577))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_2))
+                (portRef CE (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_1_renamed_578))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_equal_166_o1 "BIU_CORE/biu_state[7]_GND_14_o_equal_166_o1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_166_o_7_1_renamed_259))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_4_renamed_270))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_3_renamed_275))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_3_renamed_277))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_3_renamed_279))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_3_renamed_281))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_2_renamed_286))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_2_renamed_288))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_2_renamed_290))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_2_renamed_292))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_3_renamed_295))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_3_renamed_298))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_3_renamed_301))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_3_renamed_304))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_3_renamed_307))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_3_renamed_310))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_3_renamed_313))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_3_renamed_316))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_3_renamed_319))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_3_renamed_322))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_3_renamed_325))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_3_renamed_328))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_2_renamed_330))
+                (portRef I1 (instanceRef BIU_CORE_word_cycle_rstpot1_renamed_451))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o11_renamed_272))
+              )
+            )
+            (net (rename BIU_CORE__n1071_inv "BIU_CORE/_n1071_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_0))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_1))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_2))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_3))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_4))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_5))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_6))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_7))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_8))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_9))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_10))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_11))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_12))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_13))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_14))
+                (portRef CE (instanceRef BIU_CORE_biu_register_cs_15))
+                (portRef O (instanceRef BIU_CORE__n1071_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n1012_inv "BIU_CORE/_n1012_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_0))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_1))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_2))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_3))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_4))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_5))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_6))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_7))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_8))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_9))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_10))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_11))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_12))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_13))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_14))
+                (portRef CE (instanceRef BIU_CORE_biu_register_reg_15))
+                (portRef O (instanceRef BIU_CORE__n1012_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n1008_inv "BIU_CORE/_n1008_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_0))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_1))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_2))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_3))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_4))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_5))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_6))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_7))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_8))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_9))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_10))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_11))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_12))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_13))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_14))
+                (portRef CE (instanceRef BIU_CORE_biu_register_rm_15))
+                (portRef O (instanceRef BIU_CORE__n1008_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n1004_inv "BIU_CORE/_n1004_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_0))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_1))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_2))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_3))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_4))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_5))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_6))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_7))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_8))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_9))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_10))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_11))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_12))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_13))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_14))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ds_15))
+                (portRef O (instanceRef BIU_CORE__n1004_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n0996_inv "BIU_CORE/_n0996_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_0))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_1))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_2))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_3))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_4))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_5))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_6))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_7))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_8))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_9))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_10))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_11))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_12))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_13))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_14))
+                (portRef CE (instanceRef BIU_CORE_biu_register_es_15))
+                (portRef O (instanceRef BIU_CORE__n0996_inv1))
+              )
+            )
+            (net (rename BIU_CORE__n1000_inv "BIU_CORE/_n1000_inv")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_0))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_1))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_2))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_3))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_4))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_5))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_6))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_7))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_8))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_9))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_10))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_11))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_12))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_13))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_14))
+                (portRef CE (instanceRef BIU_CORE_biu_register_ss_15))
+                (portRef O (instanceRef BIU_CORE__n1000_inv1))
+              )
+            )
+            (net (rename BIU_CORE_eu_biu_req_code_4__INV_33_o "BIU_CORE/eu_biu_req_code[4]_INV_33_o")
+              (joined
+                (portRef O (instanceRef BIU_CORE_eu_biu_req_code_4__INV_33_o1))
+                (portRef I3 (instanceRef BIU_CORE_word_cycle_rstpot1_renamed_451))
+              )
+            )
+            (net (rename BIU_CORE_pfq_full_GND_14_o_equal_124_o "BIU_CORE/pfq_full_GND_14_o_equal_124_o")
+              (joined
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_2_renamed_330))
+                (portRef O (instanceRef BIU_CORE_pfq_full_GND_14_o_equal_124_o1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_111))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_21))
+              )
+            )
+            (net (rename BIU_CORE_n0243 "BIU_CORE/n0243")
+              (joined
+                (portRef O (instanceRef BIU_CORE_out21))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_178_o1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_198_o_renamed_267))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o_renamed_447))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__rd_n_int_Select_200_o_renamed_448))
+                (portRef I5 (instanceRef BIU_CORE__n114121))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_213))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<0>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_0_renamed_38))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_1_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<1>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_1_renamed_37))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_1__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_2_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<2>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_2_renamed_36))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_2__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_3_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<3>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_3_renamed_35))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_3__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_4_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<4>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_4_renamed_34))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_4__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_5_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<5>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_5_renamed_33))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_5__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_6_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<6>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_6_renamed_32))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_6__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_7_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<7>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_7_renamed_31))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_7__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_8_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<8>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_8_renamed_30))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_8_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_9_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<9>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_9_renamed_29))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_9_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_10_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<10>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_10_renamed_28))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_10_1_renamed_260))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_11_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<11>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_11_renamed_27))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_11_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_12_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<12>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_12_renamed_26))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_12_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_13_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<13>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_13_renamed_25))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_13_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_14_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<14>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_14_renamed_24))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_14_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_15_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<15>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_15_renamed_23))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_15_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_16_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<16>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_16_renamed_22))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_16_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_17_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<17>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_17_renamed_21))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_17_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_18_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<18>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_18_renamed_20))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_18_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_19_ "BIU_CORE/biu_state[7]_AD_OUT[19]_select_190_OUT<19>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OUT_19_renamed_19))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_19_1))
+              )
+            )
+            (net (rename BIU_CORE_n0126 "BIU_CORE/n0126")
+              (joined
+                (portRef O (instanceRef BIU_CORE_out1))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT33))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT12))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT22))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_4_renamed_270))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_2_renamed_330))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3_11))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_21_renamed_456))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_14_o_add_159_OUT_0_ "BIU_CORE/addr_out_temp[15]_GND_14_o_add_159_OUT<0>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_0__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_2_renamed_286))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_14_o_add_159_OUT_1_ "BIU_CORE/addr_out_temp[15]_GND_14_o_add_159_OUT<1>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_1__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_2_renamed_288))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_14_o_add_159_OUT_2_ "BIU_CORE/addr_out_temp[15]_GND_14_o_add_159_OUT<2>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_2__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_2_renamed_290))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_14_o_add_159_OUT_3_ "BIU_CORE/addr_out_temp[15]_GND_14_o_add_159_OUT<3>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_3__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_2_renamed_292))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_14_o_add_159_OUT_4_ "BIU_CORE/addr_out_temp[15]_GND_14_o_add_159_OUT<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_4__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_1_renamed_311))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_14_o_add_159_OUT_5_ "BIU_CORE/addr_out_temp[15]_GND_14_o_add_159_OUT<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_5__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_1_renamed_314))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_14_o_add_159_OUT_6_ "BIU_CORE/addr_out_temp[15]_GND_14_o_add_159_OUT<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_6__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_1_renamed_317))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_14_o_add_159_OUT_7_ "BIU_CORE/addr_out_temp[15]_GND_14_o_add_159_OUT<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_7__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_1_renamed_320))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_14_o_add_159_OUT_8_ "BIU_CORE/addr_out_temp[15]_GND_14_o_add_159_OUT<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_8__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_1_renamed_323))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_14_o_add_159_OUT_9_ "BIU_CORE/addr_out_temp[15]_GND_14_o_add_159_OUT<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_9__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_1_renamed_326))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_14_o_add_159_OUT_10_ "BIU_CORE/addr_out_temp[15]_GND_14_o_add_159_OUT<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_10__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_1_renamed_293))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_14_o_add_159_OUT_11_ "BIU_CORE/addr_out_temp[15]_GND_14_o_add_159_OUT<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_11__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_1_renamed_296))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_14_o_add_159_OUT_12_ "BIU_CORE/addr_out_temp[15]_GND_14_o_add_159_OUT<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_12__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_1_renamed_299))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_14_o_add_159_OUT_13_ "BIU_CORE/addr_out_temp[15]_GND_14_o_add_159_OUT<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_13__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_1_renamed_302))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_14_o_add_159_OUT_14_ "BIU_CORE/addr_out_temp[15]_GND_14_o_add_159_OUT<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_14__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_1_renamed_305))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15__GND_14_o_add_159_OUT_15_ "BIU_CORE/addr_out_temp[15]_GND_14_o_add_159_OUT<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_15__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_1_renamed_308))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<0>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_0_renamed_58))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<1>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_1_renamed_57))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<2>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_2_renamed_56))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<3>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_3_renamed_55))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<4>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_4_renamed_54))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<5>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_5_renamed_53))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<6>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_6_renamed_52))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<7>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_7_renamed_51))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<8>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_8_renamed_50))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<9>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_9_renamed_49))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_4_renamed_329))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<10>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_10_renamed_48))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<11>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_11_renamed_47))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<12>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_12_renamed_46))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<13>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_13_renamed_45))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<14>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_14_renamed_44))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<15>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_15_renamed_43))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<16>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_16_renamed_42))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<17>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_17_renamed_41))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<18>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_18_renamed_40))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_ "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<19>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_addr_out_temp_19_renamed_39))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_4_renamed_282))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_ "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<0>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_state_0))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_ "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_state_1))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_2_ "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<2>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_state_2))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_2_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3_ "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<3>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_state_3))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_4_ "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<4>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_state_4))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_4__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_5_ "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<5>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_state_5))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_5__))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_6_ "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<6>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_state_6))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_6_1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_7_ "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<7>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_state_7))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_7_1))
+              )
+            )
+            (net (rename BIU_CORE__n1174 "BIU_CORE/_n1174")
+              (joined
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0_11))
+                (portRef O (instanceRef BIU_CORE__n11741))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_10_11))
+              )
+            )
+            (net (rename BIU_CORE__n1152 "BIU_CORE/_n1152")
+              (joined
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_1_renamed_271))
+                (portRef O (instanceRef BIU_CORE__n11521))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_213))
+              )
+            )
+            (net (rename BIU_CORE__n1141 "BIU_CORE/_n1141")
+              (joined
+                (portRef O (instanceRef BIU_CORE__n11411))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_22))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_31))
+              )
+            )
+            (net (rename BIU_CORE__n1081 "BIU_CORE/_n1081")
+              (joined
+                (portRef O (instanceRef BIU_CORE__n10811))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_3_renamed_275))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_3_renamed_277))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_3_renamed_279))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_3_renamed_281))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_3_renamed_295))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_3_renamed_298))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_3_renamed_301))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_3_renamed_304))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_3_renamed_307))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_3_renamed_310))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_3_renamed_313))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_3_renamed_316))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_3_renamed_319))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_3_renamed_322))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_3_renamed_325))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_3_renamed_328))
+              )
+            )
+            (net (rename BIU_CORE__n1084 "BIU_CORE/_n1084")
+              (joined
+                (portRef O (instanceRef BIU_CORE__n10841))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_2_renamed_294))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_2_renamed_297))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_2_renamed_300))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_2_renamed_303))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_2_renamed_306))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_2_renamed_309))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_2_renamed_312))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_2_renamed_315))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_2_renamed_318))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_2_renamed_321))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_2_renamed_324))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_2_renamed_327))
+              )
+            )
+            (net (rename BIU_CORE__n0798 "BIU_CORE/_n0798")
+              (joined
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_178_o1))
+                (portRef O (instanceRef BIU_CORE__n07981))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_186_o_SW0))
+              )
+            )
+            (net (rename BIU_CORE_GND_14_o_latched_data_in_7__mux_157_OUT_0_ "BIU_CORE/GND_14_o_latched_data_in[7]_mux_157_OUT<0>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_0))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT17))
+              )
+            )
+            (net (rename BIU_CORE_GND_14_o_latched_data_in_7__mux_157_OUT_1_ "BIU_CORE/GND_14_o_latched_data_in[7]_mux_157_OUT<1>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_1))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT81))
+              )
+            )
+            (net (rename BIU_CORE_GND_14_o_latched_data_in_7__mux_157_OUT_2_ "BIU_CORE/GND_14_o_latched_data_in[7]_mux_157_OUT<2>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_2))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT91))
+              )
+            )
+            (net (rename BIU_CORE_GND_14_o_latched_data_in_7__mux_157_OUT_3_ "BIU_CORE/GND_14_o_latched_data_in[7]_mux_157_OUT<3>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_3))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT101))
+              )
+            )
+            (net (rename BIU_CORE_GND_14_o_latched_data_in_7__mux_157_OUT_4_ "BIU_CORE/GND_14_o_latched_data_in[7]_mux_157_OUT<4>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_4))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT111))
+              )
+            )
+            (net (rename BIU_CORE_GND_14_o_latched_data_in_7__mux_157_OUT_5_ "BIU_CORE/GND_14_o_latched_data_in[7]_mux_157_OUT<5>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_5))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT121))
+              )
+            )
+            (net (rename BIU_CORE_GND_14_o_latched_data_in_7__mux_157_OUT_6_ "BIU_CORE/GND_14_o_latched_data_in[7]_mux_157_OUT<6>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_6))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT131))
+              )
+            )
+            (net (rename BIU_CORE_GND_14_o_latched_data_in_7__mux_157_OUT_7_ "BIU_CORE/GND_14_o_latched_data_in[7]_mux_157_OUT<7>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_7))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT141))
+              )
+            )
+            (net (rename BIU_CORE_GND_14_o_latched_data_in_7__mux_157_OUT_8_ "BIU_CORE/GND_14_o_latched_data_in[7]_mux_157_OUT<8>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_8))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT151))
+              )
+            )
+            (net (rename BIU_CORE_GND_14_o_latched_data_in_7__mux_157_OUT_9_ "BIU_CORE/GND_14_o_latched_data_in[7]_mux_157_OUT<9>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_9))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT161))
+              )
+            )
+            (net (rename BIU_CORE_GND_14_o_latched_data_in_7__mux_157_OUT_10_ "BIU_CORE/GND_14_o_latched_data_in[7]_mux_157_OUT<10>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_10))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT21))
+              )
+            )
+            (net (rename BIU_CORE_GND_14_o_latched_data_in_7__mux_157_OUT_11_ "BIU_CORE/GND_14_o_latched_data_in[7]_mux_157_OUT<11>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_11))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT31))
+              )
+            )
+            (net (rename BIU_CORE_GND_14_o_latched_data_in_7__mux_157_OUT_12_ "BIU_CORE/GND_14_o_latched_data_in[7]_mux_157_OUT<12>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_12))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT41))
+              )
+            )
+            (net (rename BIU_CORE_GND_14_o_latched_data_in_7__mux_157_OUT_13_ "BIU_CORE/GND_14_o_latched_data_in[7]_mux_157_OUT<13>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_13))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT51))
+              )
+            )
+            (net (rename BIU_CORE_GND_14_o_latched_data_in_7__mux_157_OUT_14_ "BIU_CORE/GND_14_o_latched_data_in[7]_mux_157_OUT<14>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_14))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT61))
+              )
+            )
+            (net (rename BIU_CORE_GND_14_o_latched_data_in_7__mux_157_OUT_15_ "BIU_CORE/GND_14_o_latched_data_in[7]_mux_157_OUT<15>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_15))
+                (portRef O (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT71))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_equal_172_o "BIU_CORE/biu_state[7]_GND_14_o_equal_172_o")
+              (joined
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_178_o1))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_172_o_7_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o1_renamed_264))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_198_o_renamed_267))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o_renamed_447))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__rd_n_int_Select_200_o_renamed_448))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_equal_173_o "BIU_CORE/biu_state[7]_GND_14_o_equal_173_o")
+              (joined
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_0))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_1))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_2))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_3))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_4))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_5))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_6))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_7))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_8))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_9))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_10))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_11))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_12))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_13))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_14))
+                (portRef CE (instanceRef BIU_CORE_biu_return_data_int_15))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_173_o_7_2))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_equal_174_o "BIU_CORE/biu_state[7]_GND_14_o_equal_174_o")
+              (joined
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_31))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_1_renamed_263))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o1_renamed_264))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_186_o_SW0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_2_renamed_269))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_2_renamed_286))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_2_renamed_288))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_2_renamed_290))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_2_renamed_292))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_1_renamed_293))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_1_renamed_296))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_1_renamed_299))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_1_renamed_302))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_1_renamed_305))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_1_renamed_308))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_1_renamed_311))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_1_renamed_314))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_1_renamed_317))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_1_renamed_320))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_1_renamed_323))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_1_renamed_326))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_174_o_7_1))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_111))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_equal_167_o "BIU_CORE/biu_state[7]_GND_14_o_equal_167_o")
+              (joined
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_192_o1))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_167_o_7_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_8_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_9_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_10_1_renamed_260))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_11_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_12_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_13_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_14_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_15_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_16_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_17_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_18_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_19_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_198_o_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_7__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_6__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_5__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_4__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_3__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_2__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_1__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o_SW0_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__rd_n_int_Select_200_o_SW0_SW0))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_equal_170_o "BIU_CORE/biu_state[7]_GND_14_o_equal_170_o")
+              (joined
+                (portRef I3 (instanceRef BIU_CORE__n11741))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o2_renamed_265))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_170_o_7_1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_111))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_equal_169_o "BIU_CORE/biu_state[7]_GND_14_o_equal_169_o")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_equal_169_o_7_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0_11))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_192_o1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_198_o_SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o_SW0_SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__rd_n_int_Select_200_o_SW0_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o113))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_7__SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_6__SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_5__SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_4__SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_3__SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_2__SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_1__SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0__SW0))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_10_11))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__den_int_Select_196_o "BIU_CORE/biu_state[7]_den_int_Select_196_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_den_int_renamed_59))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__wr_n_int_Select_198_o "BIU_CORE/biu_state[7]_wr_n_int_Select_198_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_wr_n_int_renamed_60))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_198_o_renamed_267))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__rd_n_int_Select_200_o "BIU_CORE/biu_state[7]_rd_n_int_Select_200_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_rd_n_int_renamed_61))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__rd_n_int_Select_200_o_renamed_448))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__inta_n_int_Select_202_o "BIU_CORE/biu_state[7]_inta_n_int_Select_202_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_inta_n_int_renamed_62))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o_renamed_447))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__dtr_int_Select_189_o "BIU_CORE/biu_state[7]_dtr_int_Select_189_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_dtr_int_renamed_64))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__AD_OE_Select_192_o "BIU_CORE/biu_state[7]_AD_OE_Select_192_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_AD_OE_renamed_65))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_192_o1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_Select_180_o "BIU_CORE/biu_state[7]_GND_14_o_Select_180_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_byte_num_renamed_67))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o2))
+              )
+            )
+            (net (rename BIU_CORE_s_bits_2__word_cycle_AND_36_o "BIU_CORE/s_bits[2]_word_cycle_AND_36_o")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT17))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT81))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT91))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT101))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT111))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT121))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT131))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT141))
+                (portRef O (instanceRef BIU_CORE_s_bits_2__word_cycle_AND_36_o1))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__biu_done_int_Select_186_o "BIU_CORE/biu_state[7]_biu_done_int_Select_186_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_biu_done_int_renamed_71))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_186_o_renamed_268))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_Select_178_o "BIU_CORE/biu_state[7]_GND_14_o_Select_178_o")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_write_renamed_70))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_178_o1))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_14_o_add_96_OUT_4_ "BIU_CORE/biu_muxed_segment[15]_GND_14_o_add_96_OUT<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_4__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_3_renamed_313))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_14_o_add_96_OUT_5_ "BIU_CORE/biu_muxed_segment[15]_GND_14_o_add_96_OUT<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_5__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_3_renamed_316))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_14_o_add_96_OUT_6_ "BIU_CORE/biu_muxed_segment[15]_GND_14_o_add_96_OUT<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_6__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_3_renamed_319))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_14_o_add_96_OUT_7_ "BIU_CORE/biu_muxed_segment[15]_GND_14_o_add_96_OUT<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_7__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_3_renamed_322))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_14_o_add_96_OUT_8_ "BIU_CORE/biu_muxed_segment[15]_GND_14_o_add_96_OUT<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_8__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_3_renamed_325))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_14_o_add_96_OUT_9_ "BIU_CORE/biu_muxed_segment[15]_GND_14_o_add_96_OUT<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_9__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_3_renamed_328))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_14_o_add_96_OUT_10_ "BIU_CORE/biu_muxed_segment[15]_GND_14_o_add_96_OUT<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_10__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_3_renamed_295))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_14_o_add_96_OUT_11_ "BIU_CORE/biu_muxed_segment[15]_GND_14_o_add_96_OUT<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_11__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_3_renamed_298))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_14_o_add_96_OUT_12_ "BIU_CORE/biu_muxed_segment[15]_GND_14_o_add_96_OUT<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_12__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_3_renamed_301))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_14_o_add_96_OUT_13_ "BIU_CORE/biu_muxed_segment[15]_GND_14_o_add_96_OUT<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_13__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_3_renamed_304))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_14_o_add_96_OUT_14_ "BIU_CORE/biu_muxed_segment[15]_GND_14_o_add_96_OUT<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_14__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_3_renamed_307))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_14_o_add_96_OUT_15_ "BIU_CORE/biu_muxed_segment[15]_GND_14_o_add_96_OUT<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_15__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_3_renamed_310))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_14_o_add_96_OUT_16_ "BIU_CORE/biu_muxed_segment[15]_GND_14_o_add_96_OUT<16>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_16__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_3_renamed_275))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_14_o_add_96_OUT_17_ "BIU_CORE/biu_muxed_segment[15]_GND_14_o_add_96_OUT<17>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_17__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_3_renamed_277))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_14_o_add_96_OUT_18_ "BIU_CORE/biu_muxed_segment[15]_GND_14_o_add_96_OUT<18>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_18__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_3_renamed_279))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15__GND_14_o_add_96_OUT_19_ "BIU_CORE/biu_muxed_segment[15]_GND_14_o_add_96_OUT<19>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_19__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_3_renamed_281))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_124_OUT_4_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_124_OUT<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_4__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_1_renamed_311))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_124_OUT_5_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_124_OUT<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_5__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_1_renamed_314))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_124_OUT_6_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_124_OUT<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_6__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_1_renamed_317))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_124_OUT_7_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_124_OUT<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_7__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_1_renamed_320))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_124_OUT_8_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_124_OUT<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_8__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_1_renamed_323))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_124_OUT_9_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_124_OUT<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_9__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_1_renamed_326))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_124_OUT_10_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_124_OUT<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_10__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_1_renamed_293))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_124_OUT_11_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_124_OUT<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_11__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_1_renamed_296))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_124_OUT_12_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_124_OUT<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_12__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_1_renamed_299))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_124_OUT_13_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_124_OUT<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_13__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_1_renamed_302))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_124_OUT_14_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_124_OUT<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_14__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_1_renamed_305))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_124_OUT_15_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_124_OUT<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_15__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_1_renamed_308))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_124_OUT_16_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_124_OUT<16>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_16__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_124_OUT_17_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_124_OUT<17>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_17__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_124_OUT_18_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_124_OUT<18>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_18__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_124_OUT_19_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_124_OUT<19>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_19__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_4_renamed_282))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_95_OUT_4_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_95_OUT<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_4__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_2_renamed_312))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_95_OUT_5_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_95_OUT<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_5__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_2_renamed_315))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_95_OUT_6_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_95_OUT<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_6__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_2_renamed_318))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_95_OUT_7_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_95_OUT<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_7__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_2_renamed_321))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_95_OUT_8_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_95_OUT<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_8__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_2_renamed_324))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_95_OUT_9_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_95_OUT<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_9__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_2_renamed_327))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_95_OUT_10_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_95_OUT<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_10__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_2_renamed_294))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_95_OUT_11_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_95_OUT<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_11__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_2_renamed_297))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_95_OUT_12_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_95_OUT<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_12__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_2_renamed_300))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_95_OUT_13_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_95_OUT<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_13__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_2_renamed_303))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_95_OUT_14_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_95_OUT<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_14__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_2_renamed_306))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_95_OUT_15_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_95_OUT<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_15__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_2_renamed_309))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_95_OUT_16_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_95_OUT<16>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_16__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_2_renamed_274))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_95_OUT_17_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_95_OUT<17>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_17__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_2_renamed_276))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_95_OUT_18_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_95_OUT<18>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_18__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_2_renamed_278))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15__GND_14_o_add_95_OUT_19_ "BIU_CORE/biu_register_cs[15]_GND_14_o_add_95_OUT<19>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_19__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_2_renamed_280))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_14_o_add_98_OUT_4_ "BIU_CORE/biu_register_ss[15]_GND_14_o_add_98_OUT<4>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_4__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_2_renamed_312))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_14_o_add_98_OUT_5_ "BIU_CORE/biu_register_ss[15]_GND_14_o_add_98_OUT<5>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_5__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_2_renamed_315))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_14_o_add_98_OUT_6_ "BIU_CORE/biu_register_ss[15]_GND_14_o_add_98_OUT<6>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_6__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_2_renamed_318))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_14_o_add_98_OUT_7_ "BIU_CORE/biu_register_ss[15]_GND_14_o_add_98_OUT<7>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_7__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_2_renamed_321))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_14_o_add_98_OUT_8_ "BIU_CORE/biu_register_ss[15]_GND_14_o_add_98_OUT<8>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_8__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_2_renamed_324))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_14_o_add_98_OUT_9_ "BIU_CORE/biu_register_ss[15]_GND_14_o_add_98_OUT<9>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_9__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_2_renamed_327))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_14_o_add_98_OUT_10_ "BIU_CORE/biu_register_ss[15]_GND_14_o_add_98_OUT<10>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_10__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_2_renamed_294))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_14_o_add_98_OUT_11_ "BIU_CORE/biu_register_ss[15]_GND_14_o_add_98_OUT<11>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_11__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_2_renamed_297))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_14_o_add_98_OUT_12_ "BIU_CORE/biu_register_ss[15]_GND_14_o_add_98_OUT<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_12__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_2_renamed_300))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_14_o_add_98_OUT_13_ "BIU_CORE/biu_register_ss[15]_GND_14_o_add_98_OUT<13>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_13__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_2_renamed_303))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_14_o_add_98_OUT_14_ "BIU_CORE/biu_register_ss[15]_GND_14_o_add_98_OUT<14>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_14__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_2_renamed_306))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_14_o_add_98_OUT_15_ "BIU_CORE/biu_register_ss[15]_GND_14_o_add_98_OUT<15>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_15__))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_2_renamed_309))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_14_o_add_98_OUT_16_ "BIU_CORE/biu_register_ss[15]_GND_14_o_add_98_OUT<16>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_16__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_2_renamed_274))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_14_o_add_98_OUT_17_ "BIU_CORE/biu_register_ss[15]_GND_14_o_add_98_OUT<17>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_17__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_2_renamed_276))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_14_o_add_98_OUT_18_ "BIU_CORE/biu_register_ss[15]_GND_14_o_add_98_OUT<18>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_18__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_2_renamed_278))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15__GND_14_o_add_98_OUT_19_ "BIU_CORE/biu_register_ss[15]_GND_14_o_add_98_OUT<19>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_19__))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_2_renamed_280))
+              )
+            )
+            (net (rename BIU_CORE_eu_biu_req_code_4__PWR_6_o_equal_108_o "BIU_CORE/eu_biu_req_code[4]_PWR_6_o_equal_108_o")
+              (joined
+                (portRef O (instanceRef BIU_CORE_eu_biu_req_code_4__PWR_6_o_equal_108_o_4_1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_2_renamed_274))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_2_renamed_276))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_2_renamed_278))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_2_renamed_280))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_1_renamed_285))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_1_renamed_287))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_1_renamed_289))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_1_renamed_291))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_2_renamed_294))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_2_renamed_297))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_2_renamed_300))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_2_renamed_303))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_2_renamed_306))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_2_renamed_309))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_2_renamed_312))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_2_renamed_315))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_2_renamed_318))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_2_renamed_321))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_2_renamed_324))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_2_renamed_327))
+              )
+            )
+            (net (rename BIU_CORE_eu_biu_strobe_1__PWR_6_o_equal_67_o "BIU_CORE/eu_biu_strobe[1]_PWR_6_o_equal_67_o")
+              (joined
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_cy_0__))
+                (portRef CI (instanceRef BIU_CORE_Mcount_clock_cycle_counter_xor_0__))
+                (portRef O (instanceRef BIU_CORE_eu_biu_strobe_1__PWR_6_o_equal_67_o_1_1))
+              )
+            )
+            (net (rename BIU_CORE_s_bits_2__eu_biu_req_code_4__mux_129_OUT_0_ "BIU_CORE/s_bits[2]_eu_biu_req_code[4]_mux_129_OUT<0>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_s_bits_0))
+                (portRef O (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT12))
+              )
+            )
+            (net (rename BIU_CORE_s_bits_2__eu_biu_req_code_4__mux_129_OUT_1_ "BIU_CORE/s_bits[2]_eu_biu_req_code[4]_mux_129_OUT<1>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_s_bits_1))
+                (portRef O (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT22))
+              )
+            )
+            (net (rename BIU_CORE_s_bits_2__eu_biu_req_code_4__mux_129_OUT_2_ "BIU_CORE/s_bits[2]_eu_biu_req_code[4]_mux_129_OUT<2>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_s_bits_2))
+                (portRef O (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT33))
+              )
+            )
+            (net (rename BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_15_o "BIU_CORE/eu_biu_req_caught_eu_biu_req_code[4]_AND_15_o")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_0__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_1__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_2__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_3__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_4__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_5__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_6__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_7__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_8__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_9__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_10__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_11__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_12__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_13__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_14__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_15__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_0__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_1__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_2__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_3__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_4__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_5__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_6__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_7__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_8__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_9__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_10__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_11__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_12__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_13__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_14__))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_15__))
+                (portRef O (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_15_o1))
+                (portRef I0 (instanceRef BIU_CORE__n1036_inv1))
+                (portRef I3 (instanceRef BIU_CORE__n1017_inv1))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_0_ "BIU_CORE/pfq_top_byte_int<0>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_top_byte_int_d1_0))
+                (portRef O (instanceRef BIU_CORE_Mmux_pfq_top_byte_int11))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_1_ "BIU_CORE/pfq_top_byte_int<1>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_top_byte_int_d1_1))
+                (portRef O (instanceRef BIU_CORE_Mmux_pfq_top_byte_int21))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_2_ "BIU_CORE/pfq_top_byte_int<2>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_top_byte_int_d1_2))
+                (portRef O (instanceRef BIU_CORE_Mmux_pfq_top_byte_int31))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_3_ "BIU_CORE/pfq_top_byte_int<3>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_top_byte_int_d1_3))
+                (portRef O (instanceRef BIU_CORE_Mmux_pfq_top_byte_int41))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_4_ "BIU_CORE/pfq_top_byte_int<4>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_top_byte_int_d1_4))
+                (portRef O (instanceRef BIU_CORE_Mmux_pfq_top_byte_int51))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_5_ "BIU_CORE/pfq_top_byte_int<5>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_top_byte_int_d1_5))
+                (portRef O (instanceRef BIU_CORE_Mmux_pfq_top_byte_int61))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_6_ "BIU_CORE/pfq_top_byte_int<6>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_top_byte_int_d1_6))
+                (portRef O (instanceRef BIU_CORE_Mmux_pfq_top_byte_int71))
+              )
+            )
+            (net (rename BIU_CORE_pfq_top_byte_int_7_ "BIU_CORE/pfq_top_byte_int<7>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_top_byte_int_d1_7))
+                (portRef O (instanceRef BIU_CORE_Mmux_pfq_top_byte_int81))
+              )
+            )
+            (net (rename BIU_CORE_clk_falling_edge "BIU_CORE/clk_falling_edge")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0_11))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_192_o1))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_178_o1))
+                (portRef O (instanceRef BIU_CORE_clk_falling_edge1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o1_renamed_264))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_198_o_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_198_o_renamed_267))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_1_renamed_271))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_7__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_6__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_5__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_4__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_3__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_2__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_1__))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0__))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o_SW0_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o_renamed_447))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__rd_n_int_Select_200_o_SW0_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__rd_n_int_Select_200_o_renamed_448))
+                (portRef I4 (instanceRef BIU_CORE_iom_int_rstpot_renamed_462))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_10_11))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_8_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_9_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_10_1_renamed_260))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_11_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_12_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_13_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_14_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_15_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_16_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_17_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_18_1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_19_1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o121))
+              )
+            )
+            (net (rename BIU_CORE_clk_rising_edge "BIU_CORE/clk_rising_edge")
+              (joined
+                (portRef O (instanceRef BIU_CORE_clk_rising_edge1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_1_renamed_263))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o1_renamed_264))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o3_renamed_266))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_186_o_SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_2_renamed_269))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_4_renamed_270))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_1_renamed_271))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o2))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_2_renamed_286))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_2_renamed_288))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_2_renamed_290))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_2_renamed_292))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_1_renamed_293))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_1_renamed_296))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_1_renamed_299))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_1_renamed_302))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_1_renamed_305))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_1_renamed_308))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_1_renamed_311))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_1_renamed_314))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_1_renamed_317))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_1_renamed_320))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_1_renamed_323))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_1_renamed_326))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_31))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_0_ "BIU_CORE/biu_muxed_segment<0>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_4__))
+                (portRef O (instanceRef BIU_CORE_mux161))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_1_ "BIU_CORE/biu_muxed_segment<1>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_5__))
+                (portRef O (instanceRef BIU_CORE_mux1061))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_2_ "BIU_CORE/biu_muxed_segment<2>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_6__))
+                (portRef O (instanceRef BIU_CORE_mux1071))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_3_ "BIU_CORE/biu_muxed_segment<3>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_7__))
+                (portRef O (instanceRef BIU_CORE_mux1081))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_4_ "BIU_CORE/biu_muxed_segment<4>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_8__))
+                (portRef O (instanceRef BIU_CORE_mux1091))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_5_ "BIU_CORE/biu_muxed_segment<5>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_9__))
+                (portRef O (instanceRef BIU_CORE_mux10111))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_6_ "BIU_CORE/biu_muxed_segment<6>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_10__))
+                (portRef O (instanceRef BIU_CORE_mux10121))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_7_ "BIU_CORE/biu_muxed_segment<7>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_11__))
+                (portRef O (instanceRef BIU_CORE_mux10131))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_8_ "BIU_CORE/biu_muxed_segment<8>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_12__))
+                (portRef O (instanceRef BIU_CORE_mux10141))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_9_ "BIU_CORE/biu_muxed_segment<9>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_13__))
+                (portRef O (instanceRef BIU_CORE_mux10151))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_10_ "BIU_CORE/biu_muxed_segment<10>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_14__))
+                (portRef O (instanceRef BIU_CORE_mux171))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_11_ "BIU_CORE/biu_muxed_segment<11>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_15__))
+                (portRef O (instanceRef BIU_CORE_mux1011))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_12_ "BIU_CORE/biu_muxed_segment<12>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_16__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_16__))
+                (portRef O (instanceRef BIU_CORE_mux1021))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_13_ "BIU_CORE/biu_muxed_segment<13>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_17__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_17__))
+                (portRef O (instanceRef BIU_CORE_mux1031))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_14_ "BIU_CORE/biu_muxed_segment<14>")
+              (joined
+                (portRef S (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_18__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_18__))
+                (portRef O (instanceRef BIU_CORE_mux1041))
+              )
+            )
+            (net (rename BIU_CORE_biu_muxed_segment_15_ "BIU_CORE/biu_muxed_segment<15>")
+              (joined
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_xor_19__))
+                (portRef O (instanceRef BIU_CORE_mux1051))
+              )
+            )
+            (net (rename BIU_CORE_biu_segment_0_ "BIU_CORE/biu_segment<0>")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_mux171))
+                (portRef I0 (instanceRef BIU_CORE_mux161))
+                (portRef I0 (instanceRef BIU_CORE_mux1091))
+                (portRef I0 (instanceRef BIU_CORE_mux1081))
+                (portRef I0 (instanceRef BIU_CORE_mux1071))
+                (portRef I0 (instanceRef BIU_CORE_mux1061))
+                (portRef I0 (instanceRef BIU_CORE_mux1051))
+                (portRef I0 (instanceRef BIU_CORE_mux1041))
+                (portRef I0 (instanceRef BIU_CORE_mux1031))
+                (portRef I0 (instanceRef BIU_CORE_mux1021))
+                (portRef I0 (instanceRef BIU_CORE_mux10151))
+                (portRef I0 (instanceRef BIU_CORE_mux10141))
+                (portRef I0 (instanceRef BIU_CORE_mux10131))
+                (portRef I0 (instanceRef BIU_CORE_mux10121))
+                (portRef I0 (instanceRef BIU_CORE_mux10111))
+                (portRef I0 (instanceRef BIU_CORE_mux1011))
+                (portRef O (instanceRef BIU_CORE_Mmux_biu_segment11))
+              )
+            )
+            (net (rename BIU_CORE_biu_segment_1_ "BIU_CORE/biu_segment<1>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_mux171))
+                (portRef I1 (instanceRef BIU_CORE_mux161))
+                (portRef I1 (instanceRef BIU_CORE_mux1091))
+                (portRef I1 (instanceRef BIU_CORE_mux1081))
+                (portRef I1 (instanceRef BIU_CORE_mux1071))
+                (portRef I1 (instanceRef BIU_CORE_mux1061))
+                (portRef I1 (instanceRef BIU_CORE_mux1051))
+                (portRef I1 (instanceRef BIU_CORE_mux1041))
+                (portRef I1 (instanceRef BIU_CORE_mux1031))
+                (portRef I1 (instanceRef BIU_CORE_mux1021))
+                (portRef I1 (instanceRef BIU_CORE_mux10151))
+                (portRef I1 (instanceRef BIU_CORE_mux10141))
+                (portRef I1 (instanceRef BIU_CORE_mux10131))
+                (portRef I1 (instanceRef BIU_CORE_mux10121))
+                (portRef I1 (instanceRef BIU_CORE_mux10111))
+                (portRef I1 (instanceRef BIU_CORE_mux1011))
+                (portRef O (instanceRef BIU_CORE_Mmux_biu_segment21))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_0 "BIU_CORE/addr_out_temp_0")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_0_renamed_58))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_3))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0__))
+                (portRef I (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_lut_0__INV_0))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_1 "BIU_CORE/addr_out_temp_1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_1_renamed_57))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_3))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_1__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_1__rt_renamed_412))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_2 "BIU_CORE/addr_out_temp_2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_2_renamed_56))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_3))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_2__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_2__rt_renamed_411))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_3 "BIU_CORE/addr_out_temp_3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_3_renamed_55))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_3))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_3__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_3__rt_renamed_410))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_4 "BIU_CORE/addr_out_temp_4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_4_renamed_54))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_4))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_4__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_4__rt_renamed_409))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_5 "BIU_CORE/addr_out_temp_5")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_5_renamed_53))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_4))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_5__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_5__rt_renamed_408))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_6 "BIU_CORE/addr_out_temp_6")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_6_renamed_52))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_4))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_6__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_6__rt_renamed_407))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_7 "BIU_CORE/addr_out_temp_7")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_7_renamed_51))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_4))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_7__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_7__rt_renamed_406))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_8 "BIU_CORE/addr_out_temp_8")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_8_renamed_50))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_4))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_8__rt_renamed_405))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_8_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_9 "BIU_CORE/addr_out_temp_9")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_9_renamed_49))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_4_renamed_329))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_9__rt_renamed_404))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_9_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_10 "BIU_CORE/addr_out_temp_10")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_10_renamed_48))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_4))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_10__rt_renamed_403))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_10_1_renamed_260))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_11 "BIU_CORE/addr_out_temp_11")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_11_renamed_47))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_4))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_11__rt_renamed_402))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_11_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_12 "BIU_CORE/addr_out_temp_12")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_12_renamed_46))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_4))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_12__rt_renamed_401))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_12_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_13 "BIU_CORE/addr_out_temp_13")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_13_renamed_45))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_4))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_13__rt_renamed_400))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_13_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_14 "BIU_CORE/addr_out_temp_14")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_14_renamed_44))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_4))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_14__rt_renamed_399))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_14_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_15 "BIU_CORE/addr_out_temp_15")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_15_renamed_43))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_4))
+                (portRef I0 (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_15__rt_renamed_434))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_15_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_16 "BIU_CORE/addr_out_temp_16")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_16_renamed_42))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_4))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_16_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_17 "BIU_CORE/addr_out_temp_17")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_17_renamed_41))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_4))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_17_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_18 "BIU_CORE/addr_out_temp_18")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_18_renamed_40))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_4))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_18_1))
+              )
+            )
+            (net (rename BIU_CORE_addr_out_temp_19 "BIU_CORE/addr_out_temp_19")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_addr_out_temp_19_renamed_39))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_4_renamed_282))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_19_1))
+              )
+            )
+            (net (rename BIU_CORE_word_cycle "BIU_CORE/word_cycle")
+              (joined
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_1_renamed_263))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_186_o_SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_2_renamed_269))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o2))
+                (portRef Q (instanceRef BIU_CORE_word_cycle_renamed_445))
+                (portRef I2 (instanceRef BIU_CORE_word_cycle_rstpot1_renamed_451))
+                (portRef I0 (instanceRef BIU_CORE_s_bits_2__word_cycle_AND_36_o1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_7__SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_6__SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_5__SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_4__SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_3__SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_2__SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_1__SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0__SW0))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT21))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT31))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT41))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT51))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT61))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT71))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT151))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT161))
+              )
+            )
+            (net (rename BIU_CORE_eu_biu_req_caught "BIU_CORE/eu_biu_req_caught")
+              (joined
+                (portRef I0 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_15_o1))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT32))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT12))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT22))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_4_renamed_270))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_3_renamed_275))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_3_renamed_277))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_3_renamed_279))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_3_renamed_281))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_2_renamed_286))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_2_renamed_288))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_2_renamed_290))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_2_renamed_292))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_3_renamed_295))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_3_renamed_298))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_3_renamed_301))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_3_renamed_304))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_3_renamed_307))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_3_renamed_310))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_3_renamed_313))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_3_renamed_316))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_3_renamed_319))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_3_renamed_322))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_3_renamed_325))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_3_renamed_328))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_2_renamed_330))
+                (portRef Q (instanceRef BIU_CORE_eu_biu_req_caught_renamed_375))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3_11))
+                (portRef I4 (instanceRef BIU_CORE_word_cycle_rstpot1_renamed_451))
+                (portRef I0 (instanceRef BIU_CORE_eu_biu_req_caught_glue_set_renamed_452))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_21_renamed_456))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_3_renamed_457))
+                (portRef I2 (instanceRef BIU_CORE__n1076_inv_SW1))
+                (portRef I0 (instanceRef BIU_CORE_eu_biu_req_caught_eu_biu_req_code_4__AND_15_o_inv1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_111))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_21))
+              )
+            )
+            (net (rename BIU_CORE_s_bits_1_ "BIU_CORE/s_bits<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_s_bits_1))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__AD_OE_Select_192_o1))
+                (portRef I1 (instanceRef BIU_CORE__n07981))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT21))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT22))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o1_renamed_264))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o3_renamed_266))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_198_o_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o1_renamed_284))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o_SW0_SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__rd_n_int_Select_200_o_SW0_SW0))
+                (portRef I3 (instanceRef BIU_CORE_s_bits_2__word_cycle_AND_36_o1))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT21))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT31))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT41))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT51))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT61))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT71))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT151))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT161))
+              )
+            )
+            (net (rename BIU_CORE_s_bits_2_ "BIU_CORE/s_bits<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_s_bits_2))
+                (portRef I0 (instanceRef BIU_CORE__n07981))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT31_renamed_262))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT33))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o_SW0_SW0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__rd_n_int_Select_200_o_SW0_SW0))
+                (portRef I4 (instanceRef BIU_CORE_s_bits_2__word_cycle_AND_36_o1))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT21))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT31))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT41))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT51))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT61))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT71))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT151))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT161))
+                (portRef I5 (instanceRef BIU_CORE_iom_int_rstpot_renamed_462))
+              )
+            )
+            (net (rename BIU_CORE_iom_int "BIU_CORE/iom_int")
+              (joined
+                (portRef D (instanceRef BIU_CORE_IOM_renamed_15))
+                (portRef Q (instanceRef BIU_CORE_iom_int_renamed_441))
+                (portRef I0 (instanceRef BIU_CORE_iom_int_rstpot_renamed_462))
+              )
+            )
+            (net (rename BIU_CORE_ale_int "BIU_CORE/ale_int")
+              (joined
+                (portRef D (instanceRef BIU_CORE_ALE_renamed_4))
+                (portRef Q (instanceRef BIU_CORE_ale_int_renamed_440))
+                (portRef I0 (instanceRef BIU_CORE_ale_int_rstpot_renamed_455))
+              )
+            )
+            (net (rename BIU_CORE_latched_data_in_0_ "BIU_CORE/latched_data_in<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_latched_data_in_0))
+                (portRef D (instanceRef BIU_CORE_pfq_entry1_0))
+                (portRef D (instanceRef BIU_CORE_pfq_entry0_0))
+                (portRef D (instanceRef BIU_CORE_pfq_entry2_0))
+                (portRef D (instanceRef BIU_CORE_pfq_entry3_0))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT17))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT151))
+              )
+            )
+            (net (rename BIU_CORE_latched_data_in_1_ "BIU_CORE/latched_data_in<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_latched_data_in_1))
+                (portRef D (instanceRef BIU_CORE_pfq_entry1_1))
+                (portRef D (instanceRef BIU_CORE_pfq_entry0_1))
+                (portRef D (instanceRef BIU_CORE_pfq_entry2_1))
+                (portRef D (instanceRef BIU_CORE_pfq_entry3_1))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT81))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT161))
+              )
+            )
+            (net (rename BIU_CORE_latched_data_in_2_ "BIU_CORE/latched_data_in<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_latched_data_in_2))
+                (portRef D (instanceRef BIU_CORE_pfq_entry1_2))
+                (portRef D (instanceRef BIU_CORE_pfq_entry0_2))
+                (portRef D (instanceRef BIU_CORE_pfq_entry2_2))
+                (portRef D (instanceRef BIU_CORE_pfq_entry3_2))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT91))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT21))
+              )
+            )
+            (net (rename BIU_CORE_latched_data_in_3_ "BIU_CORE/latched_data_in<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_latched_data_in_3))
+                (portRef D (instanceRef BIU_CORE_pfq_entry1_3))
+                (portRef D (instanceRef BIU_CORE_pfq_entry0_3))
+                (portRef D (instanceRef BIU_CORE_pfq_entry2_3))
+                (portRef D (instanceRef BIU_CORE_pfq_entry3_3))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT101))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT31))
+              )
+            )
+            (net (rename BIU_CORE_latched_data_in_4_ "BIU_CORE/latched_data_in<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_latched_data_in_4))
+                (portRef D (instanceRef BIU_CORE_pfq_entry1_4))
+                (portRef D (instanceRef BIU_CORE_pfq_entry0_4))
+                (portRef D (instanceRef BIU_CORE_pfq_entry2_4))
+                (portRef D (instanceRef BIU_CORE_pfq_entry3_4))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT111))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT41))
+              )
+            )
+            (net (rename BIU_CORE_latched_data_in_5_ "BIU_CORE/latched_data_in<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_latched_data_in_5))
+                (portRef D (instanceRef BIU_CORE_pfq_entry1_5))
+                (portRef D (instanceRef BIU_CORE_pfq_entry0_5))
+                (portRef D (instanceRef BIU_CORE_pfq_entry2_5))
+                (portRef D (instanceRef BIU_CORE_pfq_entry3_5))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT121))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT51))
+              )
+            )
+            (net (rename BIU_CORE_latched_data_in_6_ "BIU_CORE/latched_data_in<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_latched_data_in_6))
+                (portRef D (instanceRef BIU_CORE_pfq_entry1_6))
+                (portRef D (instanceRef BIU_CORE_pfq_entry0_6))
+                (portRef D (instanceRef BIU_CORE_pfq_entry2_6))
+                (portRef D (instanceRef BIU_CORE_pfq_entry3_6))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT131))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT61))
+              )
+            )
+            (net (rename BIU_CORE_latched_data_in_7_ "BIU_CORE/latched_data_in<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_latched_data_in_7))
+                (portRef D (instanceRef BIU_CORE_pfq_entry1_7))
+                (portRef D (instanceRef BIU_CORE_pfq_entry0_7))
+                (portRef D (instanceRef BIU_CORE_pfq_entry2_7))
+                (portRef D (instanceRef BIU_CORE_pfq_entry3_7))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT141))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT71))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_8_ "BIU_CORE/biu_return_data_int<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_8))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_8_renamed_474))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_9_ "BIU_CORE/biu_return_data_int<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_9))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_9_renamed_473))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_10_ "BIU_CORE/biu_return_data_int<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_10))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_10_renamed_472))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_11_ "BIU_CORE/biu_return_data_int<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_11))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_11_renamed_471))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_12_ "BIU_CORE/biu_return_data_int<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_12))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_12_renamed_470))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_13_ "BIU_CORE/biu_return_data_int<13>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_13))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_13_renamed_469))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_14_ "BIU_CORE/biu_return_data_int<14>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_14))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_14_renamed_468))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_15_ "BIU_CORE/biu_return_data_int<15>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_15))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_15_renamed_467))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_0_ "BIU_CORE/biu_return_data_int<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_0))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT17))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_0_renamed_482))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_1_ "BIU_CORE/biu_return_data_int<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_1))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT81))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_1_renamed_481))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_2_ "BIU_CORE/biu_return_data_int<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_2))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT91))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_2_renamed_480))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_3_ "BIU_CORE/biu_return_data_int<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_3))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT101))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_3_renamed_477))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_4_ "BIU_CORE/biu_return_data_int<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_4))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT111))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_4_renamed_479))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_5_ "BIU_CORE/biu_return_data_int<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_5))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT121))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_5_renamed_478))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_6_ "BIU_CORE/biu_return_data_int<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_6))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT131))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_6_renamed_476))
+              )
+            )
+            (net (rename BIU_CORE_biu_return_data_int_7_ "BIU_CORE/biu_return_data_int<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_return_data_int_7))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT141))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_return_data_int_d2_7_renamed_475))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_3_ "BIU_CORE/pfq_addr_in<3>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_3__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_3))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_3))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_4_ "BIU_CORE/pfq_addr_in<4>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_4__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_4))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_4__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_5_ "BIU_CORE/pfq_addr_in<5>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_5__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_5))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_5__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_6_ "BIU_CORE/pfq_addr_in<6>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_6__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_6))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_6__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_7_ "BIU_CORE/pfq_addr_in<7>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_7__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_7))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_7__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_8_ "BIU_CORE/pfq_addr_in<8>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_8__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_8))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_8__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_9_ "BIU_CORE/pfq_addr_in<9>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_9__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_9))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_9__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_10_ "BIU_CORE/pfq_addr_in<10>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_10__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_10))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_10__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_11_ "BIU_CORE/pfq_addr_in<11>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_11__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_11))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_11__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_12_ "BIU_CORE/pfq_addr_in<12>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_12__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_12))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_12__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_13_ "BIU_CORE/pfq_addr_in<13>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_13__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_13))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_13__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_14_ "BIU_CORE/pfq_addr_in<14>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_14__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_14))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_14__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_15_ "BIU_CORE/pfq_addr_in<15>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_15__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_15))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_15__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_0_ "BIU_CORE/pfq_addr_in<0>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_0__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_0))
+                (portRef I2 (instanceRef BIU_CORE__n1033_inv1))
+                (portRef I1 (instanceRef BIU_CORE__n1029_inv1))
+                (portRef I2 (instanceRef BIU_CORE__n1021_inv1))
+                (portRef I2 (instanceRef BIU_CORE__n1025_inv1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_3))
+                (portRef I3 (instanceRef BIU_CORE__n1076_inv_SW1))
+                (portRef I2 (instanceRef BIU_CORE_pfq_full_GND_14_o_equal_124_o1))
+                (portRef I4 (instanceRef BIU_CORE_pfq_empty1))
+                (portRef I3 (instanceRef EU_CORE_system_signals_7_1))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_1_ "BIU_CORE/pfq_addr_in<1>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_1__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_1))
+                (portRef I1 (instanceRef BIU_CORE__n1033_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n1029_inv1))
+                (portRef I1 (instanceRef BIU_CORE__n1021_inv1))
+                (portRef I1 (instanceRef BIU_CORE__n1025_inv1))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_3))
+                (portRef I3 (instanceRef BIU_CORE__n1076_inv_renamed_458))
+                (portRef I0 (instanceRef BIU_CORE_pfq_full_GND_14_o_equal_124_o1))
+                (portRef I2 (instanceRef BIU_CORE_pfq_empty1))
+                (portRef I2 (instanceRef EU_CORE_system_signals_7_1))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_in_2_ "BIU_CORE/pfq_addr_in<2>")
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_2__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_in_2))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_3))
+                (portRef I0 (instanceRef BIU_CORE__n1076_inv_SW1))
+                (portRef I4 (instanceRef BIU_CORE_pfq_full_GND_14_o_equal_124_o1))
+                (portRef I0 (instanceRef BIU_CORE_pfq_empty1))
+                (portRef I0 (instanceRef EU_CORE_system_signals_7_1))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry3_0_ "BIU_CORE/pfq_entry3<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry3_0))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int11))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry3_1_ "BIU_CORE/pfq_entry3<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry3_1))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int21))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry3_2_ "BIU_CORE/pfq_entry3<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry3_2))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int31))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry3_3_ "BIU_CORE/pfq_entry3<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry3_3))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int41))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry3_4_ "BIU_CORE/pfq_entry3<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry3_4))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int51))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry3_5_ "BIU_CORE/pfq_entry3<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry3_5))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int61))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry3_6_ "BIU_CORE/pfq_entry3<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry3_6))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int71))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry3_7_ "BIU_CORE/pfq_entry3<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry3_7))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int81))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry2_0_ "BIU_CORE/pfq_entry2<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry2_0))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int11))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry2_1_ "BIU_CORE/pfq_entry2<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry2_1))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int21))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry2_2_ "BIU_CORE/pfq_entry2<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry2_2))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int31))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry2_3_ "BIU_CORE/pfq_entry2<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry2_3))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int41))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry2_4_ "BIU_CORE/pfq_entry2<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry2_4))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int51))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry2_5_ "BIU_CORE/pfq_entry2<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry2_5))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int61))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry2_6_ "BIU_CORE/pfq_entry2<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry2_6))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int71))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry2_7_ "BIU_CORE/pfq_entry2<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry2_7))
+                (portRef I4 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int81))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry1_0_ "BIU_CORE/pfq_entry1<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry1_0))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int11))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry1_1_ "BIU_CORE/pfq_entry1<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry1_1))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int21))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry1_2_ "BIU_CORE/pfq_entry1<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry1_2))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int31))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry1_3_ "BIU_CORE/pfq_entry1<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry1_3))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int41))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry1_4_ "BIU_CORE/pfq_entry1<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry1_4))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int51))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry1_5_ "BIU_CORE/pfq_entry1<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry1_5))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int61))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry1_6_ "BIU_CORE/pfq_entry1<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry1_6))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int71))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry1_7_ "BIU_CORE/pfq_entry1<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry1_7))
+                (portRef I2 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int81))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry0_0_ "BIU_CORE/pfq_entry0<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry0_0))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int11))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry0_1_ "BIU_CORE/pfq_entry0<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry0_1))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int21))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry0_2_ "BIU_CORE/pfq_entry0<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry0_2))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int31))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry0_3_ "BIU_CORE/pfq_entry0<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry0_3))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int41))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry0_4_ "BIU_CORE/pfq_entry0<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry0_4))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int51))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry0_5_ "BIU_CORE/pfq_entry0<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry0_5))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int61))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry0_6_ "BIU_CORE/pfq_entry0<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry0_6))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int71))
+              )
+            )
+            (net (rename BIU_CORE_pfq_entry0_7_ "BIU_CORE/pfq_entry0<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_entry0_7))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int81))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_3_ "BIU_CORE/pfq_addr_out<3>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_3))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_3__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_3))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_1_renamed_291))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_4_ "BIU_CORE/pfq_addr_out<4>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_4))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_4__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_4))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_4__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_5_ "BIU_CORE/pfq_addr_out<5>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_5))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_5__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_5))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_5__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_6_ "BIU_CORE/pfq_addr_out<6>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_6))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_6__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_6))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_6__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_7_ "BIU_CORE/pfq_addr_out<7>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_7))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_7__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_7))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_7__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_8_ "BIU_CORE/pfq_addr_out<8>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_8))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_8__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_8))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_8__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_9_ "BIU_CORE/pfq_addr_out<9>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_9))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_9__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_9))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_9__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_10_ "BIU_CORE/pfq_addr_out<10>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_10))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_10__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_10))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_10__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_11_ "BIU_CORE/pfq_addr_out<11>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_11))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_11__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_11))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_11__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_12_ "BIU_CORE/pfq_addr_out<12>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_12))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_12__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_12))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_12__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_13_ "BIU_CORE/pfq_addr_out<13>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_13))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_13__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_13))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_13__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_14_ "BIU_CORE/pfq_addr_out<14>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_14))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_14__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_14))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_14__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_15_ "BIU_CORE/pfq_addr_out<15>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_15))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_15__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_15))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_15__))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_2_ "BIU_CORE/pfq_addr_out<2>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_2))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_2__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_2))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_1_renamed_289))
+                (portRef I1 (instanceRef BIU_CORE__n1076_inv_SW1))
+                (portRef I5 (instanceRef BIU_CORE_pfq_full_GND_14_o_equal_124_o1))
+                (portRef I1 (instanceRef BIU_CORE_pfq_empty1))
+                (portRef I1 (instanceRef EU_CORE_system_signals_7_1))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_0_ "BIU_CORE/pfq_addr_out<0>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_0))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_0__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_0))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int81))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int71))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int61))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int51))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int41))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int31))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int21))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int11))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_1_renamed_285))
+                (portRef I4 (instanceRef BIU_CORE__n1076_inv_SW1))
+                (portRef I3 (instanceRef BIU_CORE_pfq_full_GND_14_o_equal_124_o1))
+                (portRef I5 (instanceRef BIU_CORE_pfq_empty1))
+                (portRef I5 (instanceRef EU_CORE_system_signals_7_1))
+              )
+            )
+            (net (rename BIU_CORE_pfq_addr_out_1_ "BIU_CORE/pfq_addr_out<1>")
+              (joined
+                (portRef D (instanceRef BIU_CORE_pfq_addr_out_d1_1))
+                (portRef I1 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_1__))
+                (portRef Q (instanceRef BIU_CORE_pfq_addr_out_1))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int81))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int71))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int61))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int51))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int41))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int31))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int21))
+                (portRef I1 (instanceRef BIU_CORE_Mmux_pfq_top_byte_int11))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_1_renamed_287))
+                (portRef I4 (instanceRef BIU_CORE__n1076_inv_renamed_458))
+                (portRef I1 (instanceRef BIU_CORE_pfq_full_GND_14_o_equal_124_o1))
+                (portRef I3 (instanceRef BIU_CORE_pfq_empty1))
+                (portRef I4 (instanceRef EU_CORE_system_signals_7_1))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_0_ "BIU_CORE/clock_cycle_counter<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_0))
+                (portRef I1 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_1_renamed_331))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_0__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_1_ "BIU_CORE/clock_cycle_counter<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_1))
+                (portRef I0 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_1_renamed_331))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_1__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_2_ "BIU_CORE/clock_cycle_counter<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_2))
+                (portRef I2 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_1_renamed_331))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_2__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_3_ "BIU_CORE/clock_cycle_counter<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_3))
+                (portRef I3 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_1_renamed_331))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_3__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_4_ "BIU_CORE/clock_cycle_counter<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_4))
+                (portRef I4 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_1_renamed_331))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_4__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_5_ "BIU_CORE/clock_cycle_counter<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_5))
+                (portRef I5 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_1_renamed_331))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_5__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_6_ "BIU_CORE/clock_cycle_counter<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_6))
+                (portRef I1 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_2))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_6__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_7_ "BIU_CORE/clock_cycle_counter<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_7))
+                (portRef I0 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_2))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_7__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_8_ "BIU_CORE/clock_cycle_counter<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_8))
+                (portRef I2 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_2))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_8__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_9_ "BIU_CORE/clock_cycle_counter<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_9))
+                (portRef I3 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_2))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_9__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_10_ "BIU_CORE/clock_cycle_counter<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_10))
+                (portRef I4 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_2))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_10__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_11_ "BIU_CORE/clock_cycle_counter<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_11))
+                (portRef I5 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_2))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_11__))
+              )
+            )
+            (net (rename BIU_CORE_clock_cycle_counter_12_ "BIU_CORE/clock_cycle_counter<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clock_cycle_counter_12))
+                (portRef I1 (instanceRef BIU_CORE__n1014_inv1))
+                (portRef I0 (instanceRef BIU_CORE_Mcount_clock_cycle_counter_lut_12__))
+                (portRef I0 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_3))
+              )
+            )
+            (net (rename BIU_CORE_den_int "BIU_CORE/den_int")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_den_int_renamed_59))
+                (portRef D (instanceRef BIU_CORE_DEN_renamed_10))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o4))
+              )
+            )
+            (net (rename BIU_CORE_wr_n_int "BIU_CORE/wr_n_int")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_wr_n_int_renamed_60))
+                (portRef D (instanceRef BIU_CORE_WR_n_renamed_11))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_198_o_renamed_267))
+              )
+            )
+            (net (rename BIU_CORE_rd_n_int "BIU_CORE/rd_n_int")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_rd_n_int_renamed_61))
+                (portRef D (instanceRef BIU_CORE_RD_n_renamed_13))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__rd_n_int_Select_200_o_renamed_448))
+              )
+            )
+            (net (rename BIU_CORE_inta_n_int "BIU_CORE/inta_n_int")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_inta_n_int_renamed_62))
+                (portRef D (instanceRef BIU_CORE_INTA_n_renamed_12))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o_renamed_447))
+              )
+            )
+            (net (rename BIU_CORE_clk_d1 "BIU_CORE/clk_d1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clk_d1_renamed_63))
+                (portRef D (instanceRef BIU_CORE_clk_d2_renamed_18))
+              )
+            )
+            (net (rename BIU_CORE_dtr_int "BIU_CORE/dtr_int")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_dtr_int_renamed_64))
+                (portRef D (instanceRef BIU_CORE_DTR_renamed_14))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o3))
+              )
+            )
+            (net (rename BIU_CORE_intr_d3 "BIU_CORE/intr_d3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_intr_d3_renamed_7))
+                (portRef I4 (instanceRef BIU_CORE_BIU_INTR_rstpot_renamed_459))
+              )
+            )
+            (net (rename BIU_CORE_intr_d2 "BIU_CORE/intr_d2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_intr_d2_renamed_16))
+                (portRef D (instanceRef BIU_CORE_intr_d3_renamed_7))
+              )
+            )
+            (net (rename BIU_CORE_intr_d1 "BIU_CORE/intr_d1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_intr_d1_renamed_66))
+                (portRef D (instanceRef BIU_CORE_intr_d2_renamed_16))
+              )
+            )
+            (net (rename BIU_CORE_byte_num "BIU_CORE/byte_num")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_byte_num_renamed_67))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_1_renamed_263))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_186_o_SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_2_renamed_269))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o1_renamed_283))
+                (portRef I1 (instanceRef BIU_CORE_s_bits_2__word_cycle_AND_36_o1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_7__SW0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_6__SW0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_5__SW0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_4__SW0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_3__SW0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_2__SW0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_1__SW0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0__SW0))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT21))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT31))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT41))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT51))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT61))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT71))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT151))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_GND_14_o_latched_data_in_7__mux_157_OUT161))
+              )
+            )
+            (net (rename BIU_CORE_eu_biu_req_d1 "BIU_CORE/eu_biu_req_d1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_biu_req_d1_renamed_68))
+                (portRef I3 (instanceRef BIU_CORE_eu_biu_req_caught_glue_set_renamed_452))
+                (portRef I2 (instanceRef EU_CORE_biu_done_caught_glue_set_renamed_461))
+              )
+            )
+            (net (rename BIU_CORE_ready_d1 "BIU_CORE/ready_d1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_ready_d1_renamed_69))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_1_renamed_271))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_211_renamed_273))
+                (portRef I5 (instanceRef BIU_CORE__n1063_inv_SW0))
+              )
+            )
+            (net (rename BIU_CORE_pfq_write "BIU_CORE/pfq_write")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_pfq_write_renamed_70))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_178_o1))
+                (portRef I1 (instanceRef BIU_CORE__n1036_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n1033_inv1))
+                (portRef I2 (instanceRef BIU_CORE__n1029_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n1021_inv1))
+                (portRef I0 (instanceRef BIU_CORE__n1025_inv1))
+              )
+            )
+            (net (rename BIU_CORE_nmi_d5 "BIU_CORE/nmi_d5")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_nmi_d5_renamed_3))
+                (portRef I3 (instanceRef BIU_CORE_nmi_caught_glue_set_renamed_453))
+              )
+            )
+            (net (rename BIU_CORE_nmi_d4 "BIU_CORE/nmi_d4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_nmi_d4_renamed_5))
+                (portRef D (instanceRef BIU_CORE_nmi_d5_renamed_3))
+                (portRef I2 (instanceRef BIU_CORE_nmi_caught_glue_set_renamed_453))
+              )
+            )
+            (net (rename BIU_CORE_nmi_d3 "BIU_CORE/nmi_d3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_nmi_d3_renamed_8))
+                (portRef D (instanceRef BIU_CORE_nmi_d4_renamed_5))
+                (portRef I1 (instanceRef BIU_CORE_nmi_caught_glue_set_renamed_453))
+              )
+            )
+            (net (rename BIU_CORE_nmi_d2 "BIU_CORE/nmi_d2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_nmi_d2_renamed_17))
+                (portRef D (instanceRef BIU_CORE_nmi_d3_renamed_8))
+                (portRef I0 (instanceRef BIU_CORE_nmi_caught_glue_set_renamed_453))
+              )
+            )
+            (net (rename BIU_CORE_nmi_d1 "BIU_CORE/nmi_d1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_nmi_d1_renamed_72))
+                (portRef D (instanceRef BIU_CORE_nmi_d2_renamed_17))
+              )
+            )
+            (net (rename BIU_CORE_clk_d4 "BIU_CORE/clk_d4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clk_d4_renamed_6))
+                (portRef I2 (instanceRef BIU_CORE_clk_falling_edge1))
+                (portRef I2 (instanceRef BIU_CORE_clk_rising_edge1))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_211_renamed_273))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o1_renamed_284))
+                (portRef I2 (instanceRef BIU_CORE__n1063_inv_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o21))
+                (portRef I1 (instanceRef BIU_CORE_BIU_INTR_rstpot_renamed_459))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_213))
+              )
+            )
+            (net (rename BIU_CORE_clk_d3 "BIU_CORE/clk_d3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clk_d3_renamed_9))
+                (portRef D (instanceRef BIU_CORE_clk_d4_renamed_6))
+                (portRef I0 (instanceRef BIU_CORE_clk_falling_edge1))
+                (portRef I1 (instanceRef BIU_CORE_clk_rising_edge1))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_211_renamed_273))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_213))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o1_renamed_284))
+                (portRef I1 (instanceRef BIU_CORE__n1063_inv_SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o21))
+                (portRef I2 (instanceRef BIU_CORE_BIU_INTR_rstpot_renamed_459))
+              )
+            )
+            (net (rename BIU_CORE_clk_d2 "BIU_CORE/clk_d2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_clk_d2_renamed_18))
+                (portRef D (instanceRef BIU_CORE_clk_d3_renamed_9))
+                (portRef I1 (instanceRef BIU_CORE_clk_falling_edge1))
+                (portRef I0 (instanceRef BIU_CORE_clk_rising_edge1))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o1_renamed_284))
+                (portRef I0 (instanceRef BIU_CORE__n1063_inv_SW0))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__inta_n_int_Select_202_o21))
+                (portRef I3 (instanceRef BIU_CORE_BIU_INTR_rstpot_renamed_459))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_213))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_212_renamed_449))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_0_ "BIU_CORE/eu_register_r3_d<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_0))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_0__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_0__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_1_renamed_285))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_1_ "BIU_CORE/eu_register_r3_d<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_1))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_1__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_1__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_1_renamed_287))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_2_ "BIU_CORE/eu_register_r3_d<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_2))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_2__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_2__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_1_renamed_289))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_3_ "BIU_CORE/eu_register_r3_d<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_3))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_3__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_3__))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_1_renamed_291))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_4_ "BIU_CORE/eu_register_r3_d<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_4))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_4__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_4__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_4__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_4__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_4__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_2_renamed_312))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_5_ "BIU_CORE/eu_register_r3_d<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_5))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_5__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_5__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_5__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_5__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_5__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_2_renamed_315))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_6_ "BIU_CORE/eu_register_r3_d<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_6))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_6__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_6__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_6__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_6__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_6__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_2_renamed_318))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_7_ "BIU_CORE/eu_register_r3_d<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_7))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_7__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_7__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_7__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_7__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_7__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_2_renamed_321))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_8_ "BIU_CORE/eu_register_r3_d<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_8))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_8__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_8__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_8__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_8__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_8__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_2_renamed_324))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_9_ "BIU_CORE/eu_register_r3_d<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_9))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_9__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_9__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_9__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_9__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_9__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_2_renamed_327))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_10_ "BIU_CORE/eu_register_r3_d<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_10))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_10__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_10__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_10__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_10__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_10__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_2_renamed_294))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_11_ "BIU_CORE/eu_register_r3_d<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_11))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_11__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_11__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_11__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_11__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_11__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_2_renamed_297))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_12_ "BIU_CORE/eu_register_r3_d<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_12))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_12__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_12__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_12__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_12__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_12__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_2_renamed_300))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_13_ "BIU_CORE/eu_register_r3_d<13>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_13))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_13__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_13__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_13__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_13__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_13__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_2_renamed_303))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_14_ "BIU_CORE/eu_register_r3_d<14>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_14))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_14__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_14__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_14__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_14__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_14__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_2_renamed_306))
+              )
+            )
+            (net (rename BIU_CORE_eu_register_r3_d_15_ "BIU_CORE/eu_register_r3_d<15>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_eu_register_r3_d_15))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_out_lut_15__))
+                (portRef I2 (instanceRef BIU_CORE_Mcount_pfq_addr_in_lut_15__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_15__))
+                (portRef I1 (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_lut_15__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_muxed_segment_15__GND_14_o_add_96_OUT_cy_15__))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_2_renamed_309))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_0_ "BIU_CORE/biu_register_cs<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_0))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_4__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_4__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_4__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_4__))
+                (portRef I4 (instanceRef BIU_CORE_mux161))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_0_renamed_576))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_1_ "BIU_CORE/biu_register_cs<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_1))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_5__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_5__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_5__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_5__))
+                (portRef I4 (instanceRef BIU_CORE_mux1061))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_1_renamed_578))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_2_ "BIU_CORE/biu_register_cs<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_2))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_6__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_6__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_6__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_6__))
+                (portRef I4 (instanceRef BIU_CORE_mux1071))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_2_renamed_577))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_3_ "BIU_CORE/biu_register_cs<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_3))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_7__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_7__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_7__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_7__))
+                (portRef I4 (instanceRef BIU_CORE_mux1081))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_3_renamed_575))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_4_ "BIU_CORE/biu_register_cs<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_4))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_8__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_8__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_8__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_8__))
+                (portRef I4 (instanceRef BIU_CORE_mux1091))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_4_renamed_574))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_5_ "BIU_CORE/biu_register_cs<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_5))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_9__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_9__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_9__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_9__))
+                (portRef I4 (instanceRef BIU_CORE_mux10111))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_5_renamed_573))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_6_ "BIU_CORE/biu_register_cs<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_6))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_10__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_10__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_10__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_10__))
+                (portRef I4 (instanceRef BIU_CORE_mux10121))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_6_renamed_572))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_7_ "BIU_CORE/biu_register_cs<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_7))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_11__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_11__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_11__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_11__))
+                (portRef I4 (instanceRef BIU_CORE_mux10131))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_7_renamed_569))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_8_ "BIU_CORE/biu_register_cs<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_8))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_12__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_12__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_12__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_12__))
+                (portRef I4 (instanceRef BIU_CORE_mux10141))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_8_renamed_571))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_9_ "BIU_CORE/biu_register_cs<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_9))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_13__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_13__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_13__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_13__))
+                (portRef I4 (instanceRef BIU_CORE_mux10151))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_9_renamed_570))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_10_ "BIU_CORE/biu_register_cs<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_10))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_14__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_14__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_14__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_14__))
+                (portRef I4 (instanceRef BIU_CORE_mux171))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_10_renamed_568))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_11_ "BIU_CORE/biu_register_cs<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_11))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_lut_15__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_15__))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_lut_15__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_15__))
+                (portRef I4 (instanceRef BIU_CORE_mux1011))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_11_renamed_567))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_12_ "BIU_CORE/biu_register_cs<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_12))
+                (portRef I4 (instanceRef BIU_CORE_mux1021))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_16__rt_renamed_415))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_16__rt_renamed_421))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_12_renamed_566))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_13_ "BIU_CORE/biu_register_cs<13>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_13))
+                (portRef I4 (instanceRef BIU_CORE_mux1031))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_17__rt_renamed_414))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_17__rt_renamed_420))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_13_renamed_565))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_14_ "BIU_CORE/biu_register_cs<14>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_14))
+                (portRef I4 (instanceRef BIU_CORE_mux1041))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_18__rt_renamed_413))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_18__rt_renamed_419))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_14_renamed_562))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_cs_15_ "BIU_CORE/biu_register_cs<15>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_cs_15))
+                (portRef I4 (instanceRef BIU_CORE_mux1051))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_19__rt_renamed_435))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_19__rt_renamed_437))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_15_renamed_564))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_0_ "BIU_CORE/biu_register_reg<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_0))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_0_renamed_499))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_1_ "BIU_CORE/biu_register_reg<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_1))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_1_renamed_497))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_2_ "BIU_CORE/biu_register_reg<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_2))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_2_renamed_496))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_3_ "BIU_CORE/biu_register_reg<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_3))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_3_renamed_495))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_4_ "BIU_CORE/biu_register_reg<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_4))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_4_renamed_494))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_5_ "BIU_CORE/biu_register_reg<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_5))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_5_renamed_491))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_6_ "BIU_CORE/biu_register_reg<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_6))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_6_renamed_493))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_7_ "BIU_CORE/biu_register_reg<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_7))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_7_renamed_492))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_8_ "BIU_CORE/biu_register_reg<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_8))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_8_renamed_490))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_9_ "BIU_CORE/biu_register_reg<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_9))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_9_renamed_489))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_10_ "BIU_CORE/biu_register_reg<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_10))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_10_renamed_488))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_11_ "BIU_CORE/biu_register_reg<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_11))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_11_renamed_487))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_12_ "BIU_CORE/biu_register_reg<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_12))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_12_renamed_484))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_13_ "BIU_CORE/biu_register_reg<13>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_13))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_13_renamed_486))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_14_ "BIU_CORE/biu_register_reg<14>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_14))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_14_renamed_485))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_reg_15_ "BIU_CORE/biu_register_reg<15>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_reg_15))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_15_renamed_483))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_0_ "BIU_CORE/biu_register_rm<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_0))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_0_renamed_512))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_1_ "BIU_CORE/biu_register_rm<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_1))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_1_renamed_514))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_2_ "BIU_CORE/biu_register_rm<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_2))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_2_renamed_513))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_3_ "BIU_CORE/biu_register_rm<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_3))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_3_renamed_511))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_4_ "BIU_CORE/biu_register_rm<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_4))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_4_renamed_510))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_5_ "BIU_CORE/biu_register_rm<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_5))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_5_renamed_509))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_6_ "BIU_CORE/biu_register_rm<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_6))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_6_renamed_508))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_7_ "BIU_CORE/biu_register_rm<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_7))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_7_renamed_505))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_8_ "BIU_CORE/biu_register_rm<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_8))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_8_renamed_507))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_9_ "BIU_CORE/biu_register_rm<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_9))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_9_renamed_506))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_10_ "BIU_CORE/biu_register_rm<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_10))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_10_renamed_504))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_11_ "BIU_CORE/biu_register_rm<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_11))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_11_renamed_503))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_12_ "BIU_CORE/biu_register_rm<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_12))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_12_renamed_502))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_13_ "BIU_CORE/biu_register_rm<13>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_13))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_13_renamed_501))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_14_ "BIU_CORE/biu_register_rm<14>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_14))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_14_renamed_498))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_rm_15_ "BIU_CORE/biu_register_rm<15>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_rm_15))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_15_renamed_500))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_0_ "BIU_CORE/biu_register_ds<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_0))
+                (portRef I3 (instanceRef BIU_CORE_mux161))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_0_renamed_530))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_1_ "BIU_CORE/biu_register_ds<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_1))
+                (portRef I3 (instanceRef BIU_CORE_mux1061))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_1_renamed_529))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_2_ "BIU_CORE/biu_register_ds<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_2))
+                (portRef I3 (instanceRef BIU_CORE_mux1071))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_2_renamed_528))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_3_ "BIU_CORE/biu_register_ds<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_3))
+                (portRef I3 (instanceRef BIU_CORE_mux1081))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_3_renamed_527))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_4_ "BIU_CORE/biu_register_ds<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_4))
+                (portRef I3 (instanceRef BIU_CORE_mux1091))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_4_renamed_526))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_5_ "BIU_CORE/biu_register_ds<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_5))
+                (portRef I3 (instanceRef BIU_CORE_mux10111))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_5_renamed_525))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_6_ "BIU_CORE/biu_register_ds<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_6))
+                (portRef I3 (instanceRef BIU_CORE_mux10121))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_6_renamed_524))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_7_ "BIU_CORE/biu_register_ds<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_7))
+                (portRef I3 (instanceRef BIU_CORE_mux10131))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_7_renamed_523))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_8_ "BIU_CORE/biu_register_ds<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_8))
+                (portRef I3 (instanceRef BIU_CORE_mux10141))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_8_renamed_522))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_9_ "BIU_CORE/biu_register_ds<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_9))
+                (portRef I3 (instanceRef BIU_CORE_mux10151))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_9_renamed_519))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_10_ "BIU_CORE/biu_register_ds<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_10))
+                (portRef I3 (instanceRef BIU_CORE_mux171))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_10_renamed_521))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_11_ "BIU_CORE/biu_register_ds<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_11))
+                (portRef I3 (instanceRef BIU_CORE_mux1011))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_11_renamed_520))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_12_ "BIU_CORE/biu_register_ds<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_12))
+                (portRef I3 (instanceRef BIU_CORE_mux1021))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_12_renamed_518))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_13_ "BIU_CORE/biu_register_ds<13>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_13))
+                (portRef I3 (instanceRef BIU_CORE_mux1031))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_13_renamed_517))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_14_ "BIU_CORE/biu_register_ds<14>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_14))
+                (portRef I3 (instanceRef BIU_CORE_mux1041))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_14_renamed_516))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ds_15_ "BIU_CORE/biu_register_ds<15>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ds_15))
+                (portRef I3 (instanceRef BIU_CORE_mux1051))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_15_renamed_515))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_0_ "BIU_CORE/biu_register_ss<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_0))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_4__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_4__))
+                (portRef I2 (instanceRef BIU_CORE_mux161))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_0_renamed_546))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_1_ "BIU_CORE/biu_register_ss<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_1))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_5__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_5__))
+                (portRef I2 (instanceRef BIU_CORE_mux1061))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_1_renamed_545))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_2_ "BIU_CORE/biu_register_ss<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_2))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_6__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_6__))
+                (portRef I2 (instanceRef BIU_CORE_mux1071))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_2_renamed_544))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_3_ "BIU_CORE/biu_register_ss<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_3))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_7__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_7__))
+                (portRef I2 (instanceRef BIU_CORE_mux1081))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_3_renamed_541))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_4_ "BIU_CORE/biu_register_ss<4>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_4))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_8__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_8__))
+                (portRef I2 (instanceRef BIU_CORE_mux1091))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_4_renamed_543))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_5_ "BIU_CORE/biu_register_ss<5>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_5))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_9__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_9__))
+                (portRef I2 (instanceRef BIU_CORE_mux10111))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_5_renamed_542))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_6_ "BIU_CORE/biu_register_ss<6>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_6))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_10__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_10__))
+                (portRef I2 (instanceRef BIU_CORE_mux10121))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_6_renamed_540))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_7_ "BIU_CORE/biu_register_ss<7>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_7))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_11__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_11__))
+                (portRef I2 (instanceRef BIU_CORE_mux10131))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_7_renamed_539))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_8_ "BIU_CORE/biu_register_ss<8>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_8))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_12__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_12__))
+                (portRef I2 (instanceRef BIU_CORE_mux10141))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_8_renamed_538))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_9_ "BIU_CORE/biu_register_ss<9>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_9))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_13__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_13__))
+                (portRef I2 (instanceRef BIU_CORE_mux10151))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_9_renamed_537))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_10_ "BIU_CORE/biu_register_ss<10>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_10))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_14__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_14__))
+                (portRef I2 (instanceRef BIU_CORE_mux171))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_10_renamed_534))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_11_ "BIU_CORE/biu_register_ss<11>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_11))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_lut_15__))
+                (portRef DI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_15__))
+                (portRef I2 (instanceRef BIU_CORE_mux1011))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_11_renamed_536))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_12_ "BIU_CORE/biu_register_ss<12>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_12))
+                (portRef I2 (instanceRef BIU_CORE_mux1021))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_16__rt_renamed_418))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_12_renamed_535))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_13_ "BIU_CORE/biu_register_ss<13>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_13))
+                (portRef I2 (instanceRef BIU_CORE_mux1031))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_17__rt_renamed_417))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_13_renamed_533))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_14_ "BIU_CORE/biu_register_ss<14>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_14))
+                (portRef I2 (instanceRef BIU_CORE_mux1041))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_18__rt_renamed_416))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_14_renamed_532))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_ss_15_ "BIU_CORE/biu_register_ss<15>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_ss_15))
+                (portRef I2 (instanceRef BIU_CORE_mux1051))
+                (portRef I0 (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_19__rt_renamed_436))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_15_renamed_531))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_0_ "BIU_CORE/biu_register_es<0>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_0))
+                (portRef I5 (instanceRef BIU_CORE_mux161))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_0_renamed_563))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_1_ "BIU_CORE/biu_register_es<1>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_1))
+                (portRef I5 (instanceRef BIU_CORE_mux1061))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_1_renamed_561))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_2_ "BIU_CORE/biu_register_es<2>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_2))
+                (portRef I5 (instanceRef BIU_CORE_mux1071))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_2_renamed_560))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_3_ "BIU_CORE/biu_register_es<3>")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_biu_register_es_3))
+                (portRef I5 (instanceRef BIU_CORE_mux1081))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_3_renamed_559))
+              )
+            )
+            (net (rename BIU_CORE_biu_register_es_4_ "BIU_CORE/biu_register_es<4>")
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+                (portRef I5 (instanceRef BIU_CORE_mux1091))
+                (portRef D (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_4_renamed_558))
+              )
+            )
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+                (portRef I5 (instanceRef BIU_CORE_mux10111))
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+              )
+            )
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+                (portRef I5 (instanceRef BIU_CORE_mux10121))
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+              )
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+                (portRef I5 (instanceRef BIU_CORE_mux10131))
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+                (portRef I5 (instanceRef BIU_CORE_mux10141))
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+              )
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+                (portRef I5 (instanceRef BIU_CORE_mux10151))
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+              )
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+                (portRef I5 (instanceRef BIU_CORE_mux171))
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+              )
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+                (portRef I5 (instanceRef BIU_CORE_mux1011))
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+                (portRef I5 (instanceRef BIU_CORE_mux1021))
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+                (portRef I5 (instanceRef BIU_CORE_mux1031))
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+              )
+            )
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+                (portRef I5 (instanceRef BIU_CORE_mux1041))
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+              )
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+                (portRef I5 (instanceRef BIU_CORE_mux1051))
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+                (portRef D (instanceRef BIU_CORE_latched_data_in_0))
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+                (portRef D (instanceRef BIU_CORE_latched_data_in_1))
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+            )
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+                (portRef D (instanceRef BIU_CORE_latched_data_in_2))
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+                (portRef D (instanceRef BIU_CORE_latched_data_in_3))
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+            (net (rename BIU_CORE_ad_in_int_4_ "BIU_CORE/ad_in_int<4>")
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+                (portRef D (instanceRef BIU_CORE_latched_data_in_4))
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+                (portRef Q (instanceRef EU_CORE_eu_calling_address_45))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o161))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT71))
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_46))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o151))
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_47))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o142))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT91))
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_48))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o131))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT101))
+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_49))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o121))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT111))
+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_50))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o111))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT121))
+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_51))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1411))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_calling_address_51__eu_calling_address_38__mux_145_OUT131))
+              )
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+            (net (rename EU_CORE_eu_calling_address_0_ "EU_CORE/eu_calling_address<0>")
+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_0))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1381))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1251))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT21_renamed_354))
+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_1))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1371))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1241))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT102))
+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_2))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1361))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1231))
+                (portRef I0 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT122))
+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_3))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1351))
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+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_4))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1341))
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+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_5))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1331))
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+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_6))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1321))
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+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT202))
+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_7))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1311))
+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1181))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_rom_address_12__GND_15_o_mux_205_OUT222))
+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_8))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1301))
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+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_9))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1291))
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+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_10))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1281))
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+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_11))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1271))
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+              )
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+                (portRef Q (instanceRef EU_CORE_eu_calling_address_12))
+                (portRef I1 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1261))
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+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_13))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1381))
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+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1121))
+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_14))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1371))
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+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1111))
+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_15))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1361))
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+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1101))
+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_16))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1351))
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+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o191))
+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_17))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1341))
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+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o181))
+              )
+            )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_18))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1331))
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+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o171))
+              )
+            )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_19))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1321))
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+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o161))
+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_20))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1311))
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+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o151))
+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_21))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1301))
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+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_22))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1291))
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+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_23))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1281))
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+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o121))
+              )
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+              (joined
+                (portRef Q (instanceRef EU_CORE_eu_calling_address_24))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1271))
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+                (portRef I3 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o111))
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+                (portRef Q (instanceRef EU_CORE_eu_calling_address_25))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1261))
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+                (portRef Q (instanceRef EU_CORE_eu_calling_address_26))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1251))
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+                (portRef Q (instanceRef EU_CORE_eu_calling_address_27))
+                (portRef I4 (instanceRef EU_CORE_Mmux_eu_opcode_jump_src_2__eu_calling_address_51__Mux_147_o1241))
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+                (portRef Q (instanceRef EU_CORE_eu_calling_address_28))
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+                (portRef I0 (instanceRef EU_CORE_carry_13_1_SW0))
+                (portRef I0 (instanceRef EU_CORE_carry_13_1_SW1))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045763_SW0))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045763_SW1))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045751_SW0))
+                (portRef I3 (instanceRef EU_CORE_carry_13_1_SW2))
+                (portRef I3 (instanceRef EU_CORE_carry_13_1_SW3))
+              )
+            )
+            (net (rename BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT3 "BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_129_OUT3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT31_renamed_262))
+                (portRef I5 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT32))
+              )
+            )
+            (net (rename BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT31 "BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_129_OUT31")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT32))
+                (portRef I0 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT33))
+              )
+            )
+            (net (rename BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT1 "BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_129_OUT1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT11))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT12))
+              )
+            )
+            (net (rename BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT2 "BIU_CORE/Mmux_s_bits[2]_eu_biu_req_code[4]_mux_129_OUT2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT21))
+                (portRef I3 (instanceRef BIU_CORE_Mmux_s_bits_2__eu_biu_req_code_4__mux_129_OUT22))
+              )
+            )
+            (net N2
+              (joined
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_1_renamed_263))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_1_SW0))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__den_int_Select_196_o1 "BIU_CORE/biu_state[7]_den_int_Select_196_o1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o1_renamed_264))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__den_int_Select_196_o2 "BIU_CORE/biu_state[7]_den_int_Select_196_o2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o2_renamed_265))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__den_int_Select_196_o3 "BIU_CORE/biu_state[7]_den_int_Select_196_o3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o3_renamed_266))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__den_int_Select_196_o4))
+              )
+            )
+            (net N4
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_198_o_SW0))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__wr_n_int_Select_198_o_renamed_267))
+              )
+            )
+            (net N6
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_186_o_SW0))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__biu_done_int_Select_186_o_renamed_268))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_2 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_2_renamed_269))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_5))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_4 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_4_renamed_270))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_5))
+              )
+            )
+            (net N12
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_5__SW0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_5__))
+              )
+            )
+            (net N14
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_4__SW0))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_4__))
+              )
+            )
+            (net N16
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3__SW0))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_3__))
+              )
+            )
+            (net N18
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_1_renamed_271))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_1_SW0))
+              )
+            )
+            (net N20
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o11_SW0))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o11_renamed_272))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_211 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>211")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_211_renamed_273))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_212_renamed_449))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_212 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<1>212")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_212_renamed_449))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_1_213))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<3>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_2_renamed_274))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_3_renamed_275))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<3>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_3_renamed_275))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<2>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_2_renamed_276))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_3_renamed_277))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<2>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_3_renamed_277))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<1>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_2_renamed_278))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_3_renamed_279))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<1>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_3_renamed_279))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<0>1")
+              (joined
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_2_renamed_280))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_1_2_renamed_278))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_2_2_renamed_276))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_3_2_renamed_274))
+                (portRef O (instanceRef BIU_CORE__n10921))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_2_renamed_294))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_2_renamed_297))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_2_renamed_300))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_2_renamed_303))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_2_renamed_306))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_2_renamed_309))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_2_renamed_312))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_2_renamed_315))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_2_renamed_318))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_2_renamed_321))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_2_renamed_324))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_2_renamed_327))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<0>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_2_renamed_280))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_3_renamed_281))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<0>4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_3_renamed_281))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_0_4_renamed_282))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_Select_180_o1 "BIU_CORE/biu_state[7]_GND_14_o_Select_180_o1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o1_renamed_283))
+                (portRef I5 (instanceRef BIU_CORE_biu_state_7__GND_14_o_Select_180_o2))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__dtr_int_Select_189_o1 "BIU_CORE/biu_state[7]_dtr_int_Select_189_o1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o1_renamed_284))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__dtr_int_Select_189_o3))
+              )
+            )
+            (net N26
+              (joined
+                (portRef O (instanceRef BIU_CORE__n1063_inv_SW0))
+                (portRef I4 (instanceRef BIU_CORE_ale_int_rstpot_renamed_455))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<19>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_1_renamed_285))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_2_renamed_286))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<19>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_2_renamed_286))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_19_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<18>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_1_renamed_287))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_2_renamed_288))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<18>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_2_renamed_288))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_18_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<17>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_1_renamed_289))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_2_renamed_290))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<17>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_2_renamed_290))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_17_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<16>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_1_renamed_291))
+                (portRef I3 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_2_renamed_292))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<16>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_2_renamed_292))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_16_3))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<9>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_1_renamed_293))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<9>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_2_renamed_294))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_3_renamed_295))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<9>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_3_renamed_295))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_9_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<8>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_1_renamed_296))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<8>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_2_renamed_297))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_3_renamed_298))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<8>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_3_renamed_298))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_8_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<7>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_1_renamed_299))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<7>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_2_renamed_300))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_3_renamed_301))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<7>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_3_renamed_301))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_7_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<6>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_1_renamed_302))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<6>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_2_renamed_303))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_3_renamed_304))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<6>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_3_renamed_304))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_6_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<5>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_1_renamed_305))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<5>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_2_renamed_306))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_3_renamed_307))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<5>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_3_renamed_307))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_5_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<4>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_1_renamed_308))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<4>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_2_renamed_309))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_3_renamed_310))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<4>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_3_renamed_310))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_4_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<15>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_1_renamed_311))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<15>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_2_renamed_312))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_3_renamed_313))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<15>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_3_renamed_313))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_15_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<14>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_1_renamed_314))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<14>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_2_renamed_315))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_3_renamed_316))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<14>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_3_renamed_316))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_14_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<13>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_1_renamed_317))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<13>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_2_renamed_318))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_3_renamed_319))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<13>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_3_renamed_319))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_13_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<12>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_1_renamed_320))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<12>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_2_renamed_321))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_3_renamed_322))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<12>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_3_renamed_322))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_12_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<11>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_1_renamed_323))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_2 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<11>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_2_renamed_324))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_3_renamed_325))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_3 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<11>3")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_3_renamed_325))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_11_4))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_1 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<10>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_1_renamed_326))
+                (portRef I0 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_4_renamed_329))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_4 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<10>4")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_2_renamed_327))
+                (portRef I4 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_3_renamed_328))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_5 "BIU_CORE/biu_state[7]_addr_out_temp[19]_select_182_OUT<10>5")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_3_renamed_328))
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__addr_out_temp_19__select_182_OUT_10_4_renamed_329))
+              )
+            )
+            (net (rename BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_2 "BIU_CORE/biu_state[7]_GND_14_o_select_184_OUT<0>2")
+              (joined
+                (portRef O (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_2_renamed_330))
+                (portRef I2 (instanceRef BIU_CORE_biu_state_7__GND_14_o_select_184_OUT_0_3))
+              )
+            )
+            (net N28
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_7__))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_7__SW0))
+              )
+            )
+            (net N30
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_6__))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_6__SW0))
+              )
+            )
+            (net N32
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_5__))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_5__SW0))
+              )
+            )
+            (net N34
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_4__))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_4__SW0))
+              )
+            )
+            (net N36
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_3__))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_3__SW0))
+              )
+            )
+            (net N38
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_2__))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_2__SW0))
+              )
+            )
+            (net N40
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_1__))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_1__SW0))
+              )
+            )
+            (net N42
+              (joined
+                (portRef I1 (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0__))
+                (portRef O (instanceRef BIU_CORE_biu_state_7__AD_OUT_19__select_190_OUT_0__SW0))
+              )
+            )
+            (net (rename BIU_CORE_BIU_CLK_COUNTER_ZERO_12_ "BIU_CORE/BIU_CLK_COUNTER_ZERO<12>")
+              (joined
+                (portRef O (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_1_renamed_331))
+                (portRef I0 (instanceRef BIU_CORE__n1014_inv1))
+                (portRef I1 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_3))
+              )
+            )
+            (net (rename BIU_CORE_BIU_CLK_COUNTER_ZERO_12_1 "BIU_CORE/BIU_CLK_COUNTER_ZERO<12>1")
+              (joined
+                (portRef O (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_2))
+                (portRef I4 (instanceRef BIU_CORE__n1014_inv1))
+                (portRef I2 (instanceRef BIU_CORE_BIU_CLK_COUNTER_ZERO_12_3))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n04576 "EU_CORE/Mmux_n04576")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045761_renamed_332))
+                (portRef I5 (instanceRef EU_CORE_Mmux_n045762))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n045761 "EU_CORE/Mmux_n045761")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045762))
+                (portRef I2 (instanceRef EU_CORE_Mmux_n045765))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n045763 "EU_CORE/Mmux_n045763")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045764))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045765))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n04572 "EU_CORE/Mmux_n04572")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045721_renamed_333))
+                (portRef I5 (instanceRef EU_CORE_Mmux_n045722))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n045721 "EU_CORE/Mmux_n045721")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045722))
+                (portRef I2 (instanceRef EU_CORE_Mmux_n045725))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n045723 "EU_CORE/Mmux_n045723")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045724))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045725))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n0457132 "EU_CORE/Mmux_n0457132")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n0457133_renamed_450))
+                (portRef I4 (instanceRef EU_CORE_Mmux_n0457136))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n0457133 "EU_CORE/Mmux_n0457133")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n0457134))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n0457136))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n045712 "EU_CORE/Mmux_n045712")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n0457121_renamed_334))
+                (portRef I5 (instanceRef EU_CORE_Mmux_n0457122))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n0457121 "EU_CORE/Mmux_n0457121")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n0457122))
+                (portRef I4 (instanceRef EU_CORE_Mmux_n0457124))
+              )
+            )
+            (net N44
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045714_SW0))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045714))
+              )
+            )
+            (net N45
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045714_SW1))
+                (portRef I4 (instanceRef EU_CORE_Mmux_n045714))
+              )
+            )
+            (net N46
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045714_SW2))
+                (portRef I2 (instanceRef EU_CORE_Mmux_n045714))
+              )
+            )
+            (net N47
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045714_SW3))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045714))
+              )
+            )
+            (net (rename EU_CORE_Mmux_n045751 "EU_CORE/Mmux_n045751")
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045752))
+                (portRef I2 (instanceRef EU_CORE_Mmux_n045754))
+              )
+            )
+            (net N49
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045716_SW0))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045716))
+              )
+            )
+            (net N50
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045716_SW1))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045716))
+              )
+            )
+            (net N51
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045716_SW2))
+                (portRef I4 (instanceRef EU_CORE_Mmux_n045716))
+              )
+            )
+            (net N52
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045716_SW3))
+                (portRef I2 (instanceRef EU_CORE_Mmux_n045716))
+              )
+            )
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+                (portRef I5 (instanceRef EU_CORE_Mmux_n045732))
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+              )
+            )
+            (net (rename SRAM_A_3_ "SRAM_A<3>")
+              (joined
+                (portRef (member SRAM_A 15))
+                (portRef O (instanceRef SRAM_A_3_OBUF))
+              )
+            )
+            (net (rename SRAM_A_2_ "SRAM_A<2>")
+              (joined
+                (portRef (member SRAM_A 16))
+                (portRef O (instanceRef SRAM_A_2_OBUF))
+              )
+            )
+            (net (rename SRAM_A_1_ "SRAM_A<1>")
+              (joined
+                (portRef (member SRAM_A 17))
+                (portRef O (instanceRef SRAM_A_1_OBUF))
+              )
+            )
+            (net (rename SRAM_A_0_ "SRAM_A<0>")
+              (joined
+                (portRef (member SRAM_A 18))
+                (portRef O (instanceRef SRAM_A_0_OBUF))
+              )
+            )
+            (net (rename LED_7_ "LED<7>")
+              (joined
+                (portRef (member LED 0))
+                (portRef O (instanceRef LED_7_OBUF_renamed_363))
+              )
+            )
+            (net (rename LED_6_ "LED<6>")
+              (joined
+                (portRef (member LED 1))
+                (portRef O (instanceRef LED_6_OBUF_renamed_364))
+              )
+            )
+            (net (rename LED_5_ "LED<5>")
+              (joined
+                (portRef (member LED 2))
+                (portRef O (instanceRef LED_5_OBUF_renamed_365))
+              )
+            )
+            (net (rename LED_4_ "LED<4>")
+              (joined
+                (portRef (member LED 3))
+                (portRef O (instanceRef LED_4_OBUF_renamed_366))
+              )
+            )
+            (net (rename LED_3_ "LED<3>")
+              (joined
+                (portRef (member LED 4))
+                (portRef O (instanceRef LED_3_OBUF_renamed_367))
+              )
+            )
+            (net (rename LED_2_ "LED<2>")
+              (joined
+                (portRef (member LED 5))
+                (portRef O (instanceRef LED_2_OBUF_renamed_368))
+              )
+            )
+            (net (rename LED_1_ "LED<1>")
+              (joined
+                (portRef (member LED 6))
+                (portRef O (instanceRef LED_1_OBUF_renamed_369))
+              )
+            )
+            (net (rename LED_0_ "LED<0>")
+              (joined
+                (portRef (member LED 7))
+                (portRef O (instanceRef LED_0_OBUF_renamed_370))
+              )
+            )
+            (net A19
+              (joined
+                (portRef A19)
+                (portRef O (instanceRef A19_OBUF))
+              )
+            )
+            (net A18
+              (joined
+                (portRef A18)
+                (portRef O (instanceRef A18_OBUF))
+              )
+            )
+            (net A17
+              (joined
+                (portRef A17)
+                (portRef O (instanceRef A17_OBUF))
+              )
+            )
+            (net A16
+              (joined
+                (portRef A16)
+                (portRef O (instanceRef A16_OBUF))
+              )
+            )
+            (net A15
+              (joined
+                (portRef A15)
+                (portRef O (instanceRef A15_OBUF))
+              )
+            )
+            (net A14
+              (joined
+                (portRef A14)
+                (portRef O (instanceRef A14_OBUF))
+              )
+            )
+            (net A13
+              (joined
+                (portRef A13)
+                (portRef O (instanceRef A13_OBUF))
+              )
+            )
+            (net A12
+              (joined
+                (portRef A12)
+                (portRef O (instanceRef A12_OBUF))
+              )
+            )
+            (net A11
+              (joined
+                (portRef A11)
+                (portRef O (instanceRef A11_OBUF))
+              )
+            )
+            (net A10
+              (joined
+                (portRef A10)
+                (portRef O (instanceRef A10_OBUF))
+              )
+            )
+            (net A9
+              (joined
+                (portRef A9)
+                (portRef O (instanceRef A9_OBUF))
+              )
+            )
+            (net A8
+              (joined
+                (portRef A8)
+                (portRef O (instanceRef A8_OBUF))
+              )
+            )
+            (net ALE
+              (joined
+                (portRef ALE)
+                (portRef O (instanceRef ALE_OBUF))
+              )
+            )
+            (net INTA_n
+              (joined
+                (portRef INTA_n)
+                (portRef O (instanceRef INTA_n_OBUF))
+              )
+            )
+            (net RD_n
+              (joined
+                (portRef RD_n)
+                (portRef O (instanceRef RD_n_OBUF))
+              )
+            )
+            (net WR_n
+              (joined
+                (portRef WR_n)
+                (portRef O (instanceRef WR_n_OBUF))
+              )
+            )
+            (net IOM
+              (joined
+                (portRef IOM)
+                (portRef O (instanceRef IOM_OBUF))
+              )
+            )
+            (net DTR
+              (joined
+                (portRef DTR)
+                (portRef O (instanceRef DTR_OBUF))
+              )
+            )
+            (net DEN
+              (joined
+                (portRef DEN)
+                (portRef O (instanceRef DEN_OBUF))
+              )
+            )
+            (net SSO_n
+              (joined
+                (portRef SSO_n)
+                (portRef O (instanceRef SSO_n_OBUF))
+              )
+            )
+            (net SRAM_CE_n
+              (joined
+                (portRef SRAM_CE_n)
+                (portRef O (instanceRef SRAM_CE_n_OBUF))
+              )
+            )
+            (net SRAM_OE_n
+              (joined
+                (portRef SRAM_OE_n)
+                (portRef O (instanceRef SRAM_OE_n_OBUF))
+              )
+            )
+            (net SRAM_WE_n
+              (joined
+                (portRef SRAM_WE_n)
+                (portRef O (instanceRef SRAM_WE_n_OBUF_renamed_371))
+              )
+            )
+            (net BUF1_OE_n
+              (joined
+                (portRef BUF1_OE_n)
+                (portRef O (instanceRef BUF1_OE_n_OBUF))
+              )
+            )
+            (net BUF2_OE_n
+              (joined
+                (portRef BUF2_OE_n)
+                (portRef O (instanceRef BUF2_OE_n_OBUF_renamed_372))
+              )
+            )
+            (net BUF2_DIR
+              (joined
+                (portRef BUF2_DIR)
+                (portRef O (instanceRef BUF2_DIR_OBUF_renamed_373))
+              )
+            )
+            (net (rename BIU_CORE_eu_biu_req_caught_glue_set "BIU_CORE/eu_biu_req_caught_glue_set")
+              (joined
+                (portRef D (instanceRef BIU_CORE_eu_biu_req_caught_renamed_375))
+                (portRef O (instanceRef BIU_CORE_eu_biu_req_caught_glue_set_renamed_452))
+              )
+            )
+            (net (rename BIU_CORE_nmi_caught_glue_set "BIU_CORE/nmi_caught_glue_set")
+              (joined
+                (portRef D (instanceRef BIU_CORE_nmi_caught_renamed_376))
+                (portRef O (instanceRef BIU_CORE_nmi_caught_glue_set_renamed_453))
+              )
+            )
+            (net (rename EU_CORE_eu_tr_latched_glue_set "EU_CORE/eu_tr_latched_glue_set")
+              (joined
+                (portRef D (instanceRef EU_CORE_eu_tr_latched_renamed_377))
+                (portRef O (instanceRef EU_CORE_eu_tr_latched_glue_set_renamed_454))
+              )
+            )
+            (net (rename EU_CORE_biu_done_caught_glue_set "EU_CORE/biu_done_caught_glue_set")
+              (joined
+                (portRef D (instanceRef EU_CORE_biu_done_caught_renamed_378))
+                (portRef O (instanceRef EU_CORE_biu_done_caught_glue_set_renamed_461))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_1__rt "Mcount_prescaler_cy<1>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_1__rt_renamed_379))
+                (portRef S (instanceRef Mcount_prescaler_cy_1__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_1__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_2__rt "Mcount_prescaler_cy<2>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_2__rt_renamed_380))
+                (portRef S (instanceRef Mcount_prescaler_cy_2__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_2__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_3__rt "Mcount_prescaler_cy<3>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_3__rt_renamed_381))
+                (portRef S (instanceRef Mcount_prescaler_cy_3__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_3__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_4__rt "Mcount_prescaler_cy<4>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_4__rt_renamed_382))
+                (portRef S (instanceRef Mcount_prescaler_cy_4__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_4__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_5__rt "Mcount_prescaler_cy<5>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_5__rt_renamed_383))
+                (portRef S (instanceRef Mcount_prescaler_cy_5__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_5__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_6__rt "Mcount_prescaler_cy<6>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_6__rt_renamed_384))
+                (portRef S (instanceRef Mcount_prescaler_cy_6__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_6__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_7__rt "Mcount_prescaler_cy<7>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_7__rt_renamed_385))
+                (portRef S (instanceRef Mcount_prescaler_cy_7__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_7__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_8__rt "Mcount_prescaler_cy<8>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_8__rt_renamed_386))
+                (portRef S (instanceRef Mcount_prescaler_cy_8__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_8__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_9__rt "Mcount_prescaler_cy<9>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_9__rt_renamed_387))
+                (portRef S (instanceRef Mcount_prescaler_cy_9__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_9__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_10__rt "Mcount_prescaler_cy<10>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_10__rt_renamed_388))
+                (portRef S (instanceRef Mcount_prescaler_cy_10__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_10__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_11__rt "Mcount_prescaler_cy<11>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_11__rt_renamed_389))
+                (portRef S (instanceRef Mcount_prescaler_cy_11__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_11__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_12__rt "Mcount_prescaler_cy<12>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_12__rt_renamed_390))
+                (portRef S (instanceRef Mcount_prescaler_cy_12__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_12__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_13__rt "Mcount_prescaler_cy<13>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_13__rt_renamed_391))
+                (portRef S (instanceRef Mcount_prescaler_cy_13__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_13__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_14__rt "Mcount_prescaler_cy<14>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_14__rt_renamed_392))
+                (portRef S (instanceRef Mcount_prescaler_cy_14__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_14__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_15__rt "Mcount_prescaler_cy<15>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_15__rt_renamed_393))
+                (portRef S (instanceRef Mcount_prescaler_cy_15__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_15__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_16__rt "Mcount_prescaler_cy<16>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_16__rt_renamed_394))
+                (portRef S (instanceRef Mcount_prescaler_cy_16__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_16__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_17__rt "Mcount_prescaler_cy<17>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_17__rt_renamed_395))
+                (portRef S (instanceRef Mcount_prescaler_cy_17__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_17__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_18__rt "Mcount_prescaler_cy<18>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_18__rt_renamed_396))
+                (portRef S (instanceRef Mcount_prescaler_cy_18__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_18__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_19__rt "Mcount_prescaler_cy<19>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_19__rt_renamed_397))
+                (portRef S (instanceRef Mcount_prescaler_cy_19__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_19__))
+              )
+            )
+            (net (rename Mcount_prescaler_cy_20__rt "Mcount_prescaler_cy<20>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_cy_20__rt_renamed_398))
+                (portRef S (instanceRef Mcount_prescaler_cy_20__))
+                (portRef LI (instanceRef Mcount_prescaler_xor_20__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_14__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<14>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_14__rt_renamed_399))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_14__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_14__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_13__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<13>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_13__rt_renamed_400))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_13__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_13__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_12__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<12>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_12__rt_renamed_401))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_12__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_11__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<11>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_11__rt_renamed_402))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_11__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_11__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_10__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<10>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_10__rt_renamed_403))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_10__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_10__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_9__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<9>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_9__rt_renamed_404))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_9__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_9__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_8__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<8>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_8__rt_renamed_405))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_8__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_8__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_7__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<7>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_7__rt_renamed_406))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_7__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_7__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_6__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<6>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_6__rt_renamed_407))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_6__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_6__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_5__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<5>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_5__rt_renamed_408))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_5__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_5__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_4__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<4>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_4__rt_renamed_409))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_4__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_4__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_3__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<3>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_3__rt_renamed_410))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_3__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_3__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_2__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<2>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_2__rt_renamed_411))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_2__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_2__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_1__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_cy<1>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_1__rt_renamed_412))
+                (portRef S (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_cy_1__))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_1__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_18__rt "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<18>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_18__rt_renamed_413))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_18__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_18__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_17__rt "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<17>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_17__rt_renamed_414))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_17__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_17__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_16__rt "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_cy<16>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_16__rt_renamed_415))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_cy_16__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_16__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_18__rt "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<18>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_18__rt_renamed_416))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_18__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_18__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_17__rt "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<17>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_17__rt_renamed_417))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_17__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_17__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_16__rt "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_cy<16>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_16__rt_renamed_418))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_cy_16__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_16__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_18__rt "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<18>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_18__rt_renamed_419))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_18__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_18__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_17__rt "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<17>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_17__rt_renamed_420))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_17__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_17__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_16__rt "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_cy<16>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_16__rt_renamed_421))
+                (portRef S (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_cy_16__))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_16__))
+              )
+            )
+            (net (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_11__rt "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<11>_rt")
+              (joined
+                (portRef O (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_11__rt_renamed_422))
+                (portRef S (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_11__))
+                (portRef LI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_11__))
+              )
+            )
+            (net (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_10__rt "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<10>_rt")
+              (joined
+                (portRef O (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_10__rt_renamed_423))
+                (portRef S (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_10__))
+                (portRef LI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_10__))
+              )
+            )
+            (net (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_9__rt "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<9>_rt")
+              (joined
+                (portRef O (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_9__rt_renamed_424))
+                (portRef S (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_9__))
+                (portRef LI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_9__))
+              )
+            )
+            (net (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_8__rt "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<8>_rt")
+              (joined
+                (portRef O (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_8__rt_renamed_425))
+                (portRef S (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_8__))
+                (portRef LI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_8__))
+              )
+            )
+            (net (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_7__rt "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<7>_rt")
+              (joined
+                (portRef O (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_7__rt_renamed_426))
+                (portRef S (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_7__))
+                (portRef LI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_7__))
+              )
+            )
+            (net (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_6__rt "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<6>_rt")
+              (joined
+                (portRef O (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_6__rt_renamed_427))
+                (portRef S (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_6__))
+                (portRef LI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_6__))
+              )
+            )
+            (net (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_5__rt "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<5>_rt")
+              (joined
+                (portRef O (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_5__rt_renamed_428))
+                (portRef S (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_5__))
+                (portRef LI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_5__))
+              )
+            )
+            (net (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_4__rt "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<4>_rt")
+              (joined
+                (portRef O (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_4__rt_renamed_429))
+                (portRef S (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_4__))
+                (portRef LI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_4__))
+              )
+            )
+            (net (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_3__rt "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<3>_rt")
+              (joined
+                (portRef O (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_3__rt_renamed_430))
+                (portRef S (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_3__))
+                (portRef LI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_3__))
+              )
+            )
+            (net (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_2__rt "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<2>_rt")
+              (joined
+                (portRef O (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_2__rt_renamed_431))
+                (portRef S (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_2__))
+                (portRef LI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_2__))
+              )
+            )
+            (net (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_1__rt "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_cy<1>_rt")
+              (joined
+                (portRef O (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_1__rt_renamed_432))
+                (portRef S (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_cy_1__))
+                (portRef LI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_1__))
+              )
+            )
+            (net (rename Mcount_prescaler_xor_21__rt "Mcount_prescaler_xor<21>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_prescaler_xor_21__rt_renamed_433))
+                (portRef LI (instanceRef Mcount_prescaler_xor_21__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_15__rt "BIU_CORE/Madd_addr_out_temp[15]_GND_14_o_add_159_OUT_xor<15>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_15__rt_renamed_434))
+                (portRef LI (instanceRef BIU_CORE_Madd_addr_out_temp_15__GND_14_o_add_159_OUT_xor_15__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_19__rt "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_124_OUT_xor<19>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_19__rt_renamed_435))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_124_OUT_xor_19__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_19__rt "BIU_CORE/Madd_biu_register_ss[15]_GND_14_o_add_98_OUT_xor<19>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_19__rt_renamed_436))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_ss_15__GND_14_o_add_98_OUT_xor_19__))
+              )
+            )
+            (net (rename BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_19__rt "BIU_CORE/Madd_biu_register_cs[15]_GND_14_o_add_95_OUT_xor<19>_rt")
+              (joined
+                (portRef O (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_19__rt_renamed_437))
+                (portRef LI (instanceRef BIU_CORE_Madd_biu_register_cs_15__GND_14_o_add_95_OUT_xor_19__))
+              )
+            )
+            (net (rename EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_12__rt "EU_CORE/Madd_eu_rom_address[12]_GND_15_o_add_186_OUT_xor<12>_rt")
+              (joined
+                (portRef O (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_12__rt_renamed_438))
+                (portRef LI (instanceRef EU_CORE_Madd_eu_rom_address_12__GND_15_o_add_186_OUT_xor_12__))
+              )
+            )
+            (net (rename BIU_CORE_BIU_INTR_rstpot "BIU_CORE/BIU_INTR_rstpot")
+              (joined
+                (portRef D (instanceRef BIU_CORE_BIU_INTR_renamed_439))
+                (portRef O (instanceRef BIU_CORE_BIU_INTR_rstpot_renamed_459))
+              )
+            )
+            (net (rename BIU_CORE_ale_int_rstpot "BIU_CORE/ale_int_rstpot")
+              (joined
+                (portRef D (instanceRef BIU_CORE_ale_int_renamed_440))
+                (portRef O (instanceRef BIU_CORE_ale_int_rstpot_renamed_455))
+              )
+            )
+            (net (rename BIU_CORE_iom_int_rstpot "BIU_CORE/iom_int_rstpot")
+              (joined
+                (portRef D (instanceRef BIU_CORE_iom_int_renamed_441))
+                (portRef O (instanceRef BIU_CORE_iom_int_rstpot_renamed_462))
+              )
+            )
+            (net (rename EU_CORE_intr_enable_delayed_rstpot "EU_CORE/intr_enable_delayed_rstpot")
+              (joined
+                (portRef O (instanceRef EU_CORE_intr_enable_delayed_rstpot_renamed_442))
+                (portRef D (instanceRef EU_CORE_intr_enable_delayed_renamed_443))
+              )
+            )
+            (net led_go_left_rstpot
+              (joined
+                (portRef D (instanceRef led_go_left_renamed_444))
+                (portRef O (instanceRef led_go_left_rstpot_renamed_460))
+              )
+            )
+            (net (rename BIU_CORE_word_cycle_rstpot1 "BIU_CORE/word_cycle_rstpot1")
+              (joined
+                (portRef D (instanceRef BIU_CORE_word_cycle_renamed_445))
+                (portRef O (instanceRef BIU_CORE_word_cycle_rstpot1_renamed_451))
+              )
+            )
+            (net N90
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045771_SW1))
+                (portRef I1 (instanceRef EU_CORE_Mmux_n045772))
+              )
+            )
+            (net N93
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_13_1_SW0))
+                (portRef I3 (instanceRef EU_CORE_carry_15_1_SW4_F))
+                (portRef I0 (instanceRef EU_CORE_Mxor_carry_16__carry_15__XOR_141_o_xo_0_1))
+                (portRef I0 (instanceRef EU_CORE_carry_16_1))
+              )
+            )
+            (net N94
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_13_1_SW1))
+                (portRef I1 (instanceRef EU_CORE_Mxor_carry_16__carry_15__XOR_141_o_xo_0_1))
+                (portRef I1 (instanceRef EU_CORE_carry_16_1))
+                (portRef I4 (instanceRef EU_CORE_carry_15_1_SW5_F))
+              )
+            )
+            (net N96
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045733_SW0))
+                (portRef I3 (instanceRef EU_CORE_Mmux_n045734))
+              )
+            )
+            (net N98
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045763_SW0))
+                (portRef I4 (instanceRef EU_CORE_carry_13_1_SW4))
+                (portRef I4 (instanceRef EU_CORE_carry_13_1_SW5))
+              )
+            )
+            (net N99
+              (joined
+                (portRef O (instanceRef EU_CORE_Mmux_n045763_SW1))
+                (portRef I5 (instanceRef EU_CORE_carry_13_1_SW4))
+                (portRef I5 (instanceRef EU_CORE_carry_13_1_SW5))
+              )
+            )
+            (net N101
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_11_1_SW0))
+                (portRef I3 (instanceRef EU_CORE_carry_13_1_SW4))
+                (portRef I2 (instanceRef EU_CORE_carry_13_1_SW5))
+                (portRef I5 (instanceRef EU_CORE_carry_13_1_SW2))
+              )
+            )
+            (net N102
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_11_1_SW1))
+                (portRef I2 (instanceRef EU_CORE_carry_13_1_SW4))
+                (portRef I3 (instanceRef EU_CORE_carry_13_1_SW5))
+                (portRef I5 (instanceRef EU_CORE_carry_13_1_SW3))
+              )
+            )
+            (net N104
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_7_1_SW0))
+                (portRef I4 (instanceRef EU_CORE_carry_9_1_SW0))
+                (portRef I1 (instanceRef EU_CORE_carry_9_1))
+              )
+            )
+            (net N105
+              (joined
+                (portRef O (instanceRef EU_CORE_carry_7_1_SW1))
+                (portRef I4 (instanceRef EU_CORE_carry_9_1_SW1))
+                (portRef I2 (instanceRef EU_CORE_carry_9_1))
+              )
+            )
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+            (net Mshreg_t_biu_ad_oe_d2
+              (joined
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+                (portRef D (instanceRef t_biu_ad_oe_d2_renamed_464))
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+              (joined
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+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_15))
+              )
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+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_14))
+              )
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+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_13))
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+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_12))
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+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_11))
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+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_10))
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+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_9))
+              )
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+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_8))
+              )
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+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_7))
+              )
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+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_6 "BIU_CORE/Mshreg_biu_return_data_int_d2_6")
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+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_6))
+              )
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+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_3 "BIU_CORE/Mshreg_biu_return_data_int_d2_3")
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+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_3))
+              )
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+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_5 "BIU_CORE/Mshreg_biu_return_data_int_d2_5")
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+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_5))
+              )
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+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_4 "BIU_CORE/Mshreg_biu_return_data_int_d2_4")
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+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_2 "BIU_CORE/Mshreg_biu_return_data_int_d2_2")
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+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_1 "BIU_CORE/Mshreg_biu_return_data_int_d2_1")
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+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_1))
+              )
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+            (net (rename BIU_CORE_Mshreg_biu_return_data_int_d2_0 "BIU_CORE/Mshreg_biu_return_data_int_d2_0")
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+                (portRef D (instanceRef BIU_CORE_biu_return_data_int_d2_0))
+              )
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+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_15 "BIU_CORE/Mshreg_biu_register_reg_d2_15")
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+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_15))
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+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_6_renamed_493))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_4 "BIU_CORE/Mshreg_biu_register_reg_d2_4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_4_renamed_494))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_3 "BIU_CORE/Mshreg_biu_register_reg_d2_3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_3_renamed_495))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_2 "BIU_CORE/Mshreg_biu_register_reg_d2_2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_2_renamed_496))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_1 "BIU_CORE/Mshreg_biu_register_reg_d2_1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_1_renamed_497))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_14 "BIU_CORE/Mshreg_biu_register_rm_d2_14")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_14_renamed_498))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_reg_d2_0 "BIU_CORE/Mshreg_biu_register_reg_d2_0")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_reg_d2_0_renamed_499))
+                (portRef D (instanceRef BIU_CORE_biu_register_reg_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_15 "BIU_CORE/Mshreg_biu_register_rm_d2_15")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_15_renamed_500))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_13 "BIU_CORE/Mshreg_biu_register_rm_d2_13")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_13_renamed_501))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_12 "BIU_CORE/Mshreg_biu_register_rm_d2_12")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_12_renamed_502))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_11 "BIU_CORE/Mshreg_biu_register_rm_d2_11")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_11_renamed_503))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_10 "BIU_CORE/Mshreg_biu_register_rm_d2_10")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_10_renamed_504))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_7 "BIU_CORE/Mshreg_biu_register_rm_d2_7")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_7_renamed_505))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_9 "BIU_CORE/Mshreg_biu_register_rm_d2_9")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_9_renamed_506))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_8 "BIU_CORE/Mshreg_biu_register_rm_d2_8")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_8_renamed_507))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_6 "BIU_CORE/Mshreg_biu_register_rm_d2_6")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_6_renamed_508))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_5 "BIU_CORE/Mshreg_biu_register_rm_d2_5")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_5_renamed_509))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_4 "BIU_CORE/Mshreg_biu_register_rm_d2_4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_4_renamed_510))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_3 "BIU_CORE/Mshreg_biu_register_rm_d2_3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_3_renamed_511))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_0 "BIU_CORE/Mshreg_biu_register_rm_d2_0")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_0_renamed_512))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_2 "BIU_CORE/Mshreg_biu_register_rm_d2_2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_2_renamed_513))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_rm_d2_1 "BIU_CORE/Mshreg_biu_register_rm_d2_1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_rm_d2_1_renamed_514))
+                (portRef D (instanceRef BIU_CORE_biu_register_rm_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_15 "BIU_CORE/Mshreg_biu_register_ds_d2_15")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_15_renamed_515))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_14 "BIU_CORE/Mshreg_biu_register_ds_d2_14")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_14_renamed_516))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_13 "BIU_CORE/Mshreg_biu_register_ds_d2_13")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_13_renamed_517))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_12 "BIU_CORE/Mshreg_biu_register_ds_d2_12")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_12_renamed_518))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_9 "BIU_CORE/Mshreg_biu_register_ds_d2_9")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_9_renamed_519))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_11 "BIU_CORE/Mshreg_biu_register_ds_d2_11")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_11_renamed_520))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_10 "BIU_CORE/Mshreg_biu_register_ds_d2_10")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_10_renamed_521))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_8 "BIU_CORE/Mshreg_biu_register_ds_d2_8")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_8_renamed_522))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_7 "BIU_CORE/Mshreg_biu_register_ds_d2_7")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_7_renamed_523))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_6 "BIU_CORE/Mshreg_biu_register_ds_d2_6")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_6_renamed_524))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_5 "BIU_CORE/Mshreg_biu_register_ds_d2_5")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_5_renamed_525))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_4 "BIU_CORE/Mshreg_biu_register_ds_d2_4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_4_renamed_526))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_3 "BIU_CORE/Mshreg_biu_register_ds_d2_3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_3_renamed_527))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_2 "BIU_CORE/Mshreg_biu_register_ds_d2_2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_2_renamed_528))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_1 "BIU_CORE/Mshreg_biu_register_ds_d2_1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_1_renamed_529))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ds_d2_0 "BIU_CORE/Mshreg_biu_register_ds_d2_0")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ds_d2_0_renamed_530))
+                (portRef D (instanceRef BIU_CORE_biu_register_ds_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_15 "BIU_CORE/Mshreg_biu_register_ss_d2_15")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_15_renamed_531))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_14 "BIU_CORE/Mshreg_biu_register_ss_d2_14")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_14_renamed_532))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_13 "BIU_CORE/Mshreg_biu_register_ss_d2_13")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_13_renamed_533))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_10 "BIU_CORE/Mshreg_biu_register_ss_d2_10")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_10_renamed_534))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_12 "BIU_CORE/Mshreg_biu_register_ss_d2_12")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_12_renamed_535))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_11 "BIU_CORE/Mshreg_biu_register_ss_d2_11")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_11_renamed_536))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_9 "BIU_CORE/Mshreg_biu_register_ss_d2_9")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_9_renamed_537))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_8 "BIU_CORE/Mshreg_biu_register_ss_d2_8")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_8_renamed_538))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_7 "BIU_CORE/Mshreg_biu_register_ss_d2_7")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_7_renamed_539))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_6 "BIU_CORE/Mshreg_biu_register_ss_d2_6")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_6_renamed_540))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_3 "BIU_CORE/Mshreg_biu_register_ss_d2_3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_3_renamed_541))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_5 "BIU_CORE/Mshreg_biu_register_ss_d2_5")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_5_renamed_542))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_4 "BIU_CORE/Mshreg_biu_register_ss_d2_4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_4_renamed_543))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_2 "BIU_CORE/Mshreg_biu_register_ss_d2_2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_2_renamed_544))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_1 "BIU_CORE/Mshreg_biu_register_ss_d2_1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_1_renamed_545))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_ss_d2_0 "BIU_CORE/Mshreg_biu_register_ss_d2_0")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_ss_d2_0_renamed_546))
+                (portRef D (instanceRef BIU_CORE_biu_register_ss_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_15 "BIU_CORE/Mshreg_biu_register_es_d2_15")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_15_renamed_547))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_12 "BIU_CORE/Mshreg_biu_register_es_d2_12")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_12_renamed_548))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_14 "BIU_CORE/Mshreg_biu_register_es_d2_14")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_14_renamed_549))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_13 "BIU_CORE/Mshreg_biu_register_es_d2_13")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_13_renamed_550))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_11 "BIU_CORE/Mshreg_biu_register_es_d2_11")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_11_renamed_551))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_10 "BIU_CORE/Mshreg_biu_register_es_d2_10")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_10_renamed_552))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_9 "BIU_CORE/Mshreg_biu_register_es_d2_9")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_9_renamed_553))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_8 "BIU_CORE/Mshreg_biu_register_es_d2_8")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_8_renamed_554))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_5 "BIU_CORE/Mshreg_biu_register_es_d2_5")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_5_renamed_555))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_7 "BIU_CORE/Mshreg_biu_register_es_d2_7")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_7_renamed_556))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_6 "BIU_CORE/Mshreg_biu_register_es_d2_6")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_6_renamed_557))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_4 "BIU_CORE/Mshreg_biu_register_es_d2_4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_4_renamed_558))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_3 "BIU_CORE/Mshreg_biu_register_es_d2_3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_3_renamed_559))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_2 "BIU_CORE/Mshreg_biu_register_es_d2_2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_2_renamed_560))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_1 "BIU_CORE/Mshreg_biu_register_es_d2_1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_1_renamed_561))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_1))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_14 "BIU_CORE/Mshreg_biu_register_cs_d2_14")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_14_renamed_562))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_14))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_es_d2_0 "BIU_CORE/Mshreg_biu_register_es_d2_0")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_es_d2_0_renamed_563))
+                (portRef D (instanceRef BIU_CORE_biu_register_es_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_15 "BIU_CORE/Mshreg_biu_register_cs_d2_15")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_15_renamed_564))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_15))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_13 "BIU_CORE/Mshreg_biu_register_cs_d2_13")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_13_renamed_565))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_13))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_12 "BIU_CORE/Mshreg_biu_register_cs_d2_12")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_12_renamed_566))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_12))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_11 "BIU_CORE/Mshreg_biu_register_cs_d2_11")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_11_renamed_567))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_11))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_10 "BIU_CORE/Mshreg_biu_register_cs_d2_10")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_10_renamed_568))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_10))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_7 "BIU_CORE/Mshreg_biu_register_cs_d2_7")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_7_renamed_569))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_7))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_9 "BIU_CORE/Mshreg_biu_register_cs_d2_9")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_9_renamed_570))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_9))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_8 "BIU_CORE/Mshreg_biu_register_cs_d2_8")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_8_renamed_571))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_8))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_6 "BIU_CORE/Mshreg_biu_register_cs_d2_6")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_6_renamed_572))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_6))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_5 "BIU_CORE/Mshreg_biu_register_cs_d2_5")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_5_renamed_573))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_5))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_4 "BIU_CORE/Mshreg_biu_register_cs_d2_4")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_4_renamed_574))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_4))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_3 "BIU_CORE/Mshreg_biu_register_cs_d2_3")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_3_renamed_575))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_3))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_0 "BIU_CORE/Mshreg_biu_register_cs_d2_0")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_0_renamed_576))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_0))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_2 "BIU_CORE/Mshreg_biu_register_cs_d2_2")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_2_renamed_577))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_2))
+              )
+            )
+            (net (rename BIU_CORE_Mshreg_biu_register_cs_d2_1 "BIU_CORE/Mshreg_biu_register_cs_d2_1")
+              (joined
+                (portRef Q (instanceRef BIU_CORE_Mshreg_biu_register_cs_d2_1_renamed_578))
+                (portRef D (instanceRef BIU_CORE_biu_register_cs_d2_1))
+              )
+            )
+          )
+      )
+    )
+  )
+
+  (design MCL86jr
+    (cellRef MCL86jr
+      (libraryRef MCL86jr_lib)
+    )
+    (property PART (string "xc6slx9-3-tqg144") (owner "Xilinx"))
+  )
+)
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/constrs_1/designprops.xml b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/constrs_1/designprops.xml
new file mode 100644
index 0000000..26d0f5a
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/constrs_1/designprops.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0"?>
+<Compat Version="1" Minor="4">
+	<CompatParts>
+	</CompatParts>
+	<ConfigModes>
+		<Mode Id="JTAG"/>
+	</ConfigModes>
+	<PortProps>
+	</PortProps>
+</Compat>
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/constrs_1/fileset.xml b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/constrs_1/fileset.xml
new file mode 100644
index 0000000..90260d6
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/constrs_1/fileset.xml
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PPRDIR/../ipcore_dir/EU4Kx32.ncf">
+      <FileInfo>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../MCL86jr.ucf">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <File Path="$PDATADIR/constrs_1/designprops.xml">
+      <FileInfo SFType="CompatPartsDb"/>
+    </File>
+    <File Path="$PDATADIR/constrs_1/usercols.xml">
+      <FileInfo SFType="UserColsDb"/>
+    </File>
+    <Config>
+      <Option Name="TargetConstrsFile" Val="$PPRDIR/../MCL86jr.ucf"/>
+      <Option Name="ConstrsType" Val="UCF"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/constrs_1/usercols.xml b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/constrs_1/usercols.xml
new file mode 100644
index 0000000..eb20735
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/constrs_1/usercols.xml
@@ -0,0 +1,4 @@
+<?xml version="1.0"?>
+<UserColInfo Version="1" Minor="0">
+</UserColInfo>
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/runs/impl_1.psg b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/runs/impl_1.psg
new file mode 100644
index 0000000..147f3a9
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/runs/impl_1.psg
@@ -0,0 +1,20 @@
+<?xml version="1.0"?>
+<Strategy Version="1" Minor="2">
+	<StratHandle Name="ISE Defaults" Flow="ISE14">
+		<Desc>ISE Defaults, including packing registers in IOs off</Desc>
+	</StratHandle>
+	<Step Id="ngdbuild">
+	</Step>
+	<Step Id="map">
+		<Option Id="FFPackEnum">3</Option>
+	</Step>
+	<Step Id="par">
+	</Step>
+	<Step Id="trce">
+	</Step>
+	<Step Id="xdl">
+	</Step>
+	<Step Id="bitgen">
+	</Step>
+</Strategy>
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/runs/runs.xml b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/runs/runs.xml
new file mode 100644
index 0000000..389cab4
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/runs/runs.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="8">
+	<Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc6slx9tqg144-3" ConstrsSet="constrs_1" Description="ISE Defaults, including packing registers in IOs off" State="current"/>
+</Runs>
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/sim_1/fileset.xml b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/sim_1/fileset.xml
new file mode 100644
index 0000000..65babe3
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/sim_1/fileset.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+      <Option Name="SrcSet" Val="sources_1"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/sources_1/chipscope.xml b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/sources_1/chipscope.xml
new file mode 100644
index 0000000..3fd9702
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/sources_1/chipscope.xml
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<ChipScope Version="1" Minor="3">
+	<UnassignedNets>
+	</UnassignedNets>
+</ChipScope>
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/sources_1/fileset.xml b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/sources_1/fileset.xml
new file mode 100644
index 0000000..9ad22cd
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/sources_1/fileset.xml
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+    <Filter Type="EDIFSrcs"/>
+    <File Path="$PPRDIR/../MCL86jr.ngc">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../ipcore_dir/EU4Kx32.ngc">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <File Path="$PDATADIR/sources_1/ports.xml">
+      <FileInfo SFType="PortsDb"/>
+    </File>
+    <File Path="$PDATADIR/sources_1/chipscope.xml">
+      <FileInfo SFType="ChipscopeDb"/>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="GateLvl"/>
+      <Option Name="GateLvlMode" Val="EDIF"/>
+      <Option Name="TopFile" Val="$PPRDIR/../MCL86jr.ngc"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/sources_1/ports.xml b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/sources_1/ports.xml
new file mode 100644
index 0000000..ea12bf4
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/sources_1/ports.xml
@@ -0,0 +1,87 @@
+<?xml version="1.0"?>
+<Interface Version="1" Minor="1">
+	<Ifc Id="ROOT" Top="1">
+		<Bus Id="SRAM_A">
+			<Port Id="18" Dir="OUT"/>
+			<Port Id="17" Dir="OUT"/>
+			<Port Id="16" Dir="OUT"/>
+			<Port Id="15" Dir="OUT"/>
+			<Port Id="14" Dir="OUT"/>
+			<Port Id="13" Dir="OUT"/>
+			<Port Id="12" Dir="OUT"/>
+			<Port Id="11" Dir="OUT"/>
+			<Port Id="10" Dir="OUT"/>
+			<Port Id="9" Dir="OUT"/>
+			<Port Id="8" Dir="OUT"/>
+			<Port Id="7" Dir="OUT"/>
+			<Port Id="6" Dir="OUT"/>
+			<Port Id="5" Dir="OUT"/>
+			<Port Id="4" Dir="OUT"/>
+			<Port Id="3" Dir="OUT"/>
+			<Port Id="2" Dir="OUT"/>
+			<Port Id="1" Dir="OUT"/>
+			<Port Id="0" Dir="OUT"/>
+		</Bus>
+		<Bus Id="SRAM_D">
+			<Port Id="7" Dir="INOUT"/>
+			<Port Id="6" Dir="INOUT"/>
+			<Port Id="5" Dir="INOUT"/>
+			<Port Id="4" Dir="INOUT"/>
+			<Port Id="3" Dir="INOUT"/>
+			<Port Id="2" Dir="INOUT"/>
+			<Port Id="1" Dir="INOUT"/>
+			<Port Id="0" Dir="INOUT"/>
+		</Bus>
+		<Bus Id="LED">
+			<Port Id="7" Dir="OUT"/>
+			<Port Id="6" Dir="OUT"/>
+			<Port Id="5" Dir="OUT"/>
+			<Port Id="4" Dir="OUT"/>
+			<Port Id="3" Dir="OUT"/>
+			<Port Id="2" Dir="OUT"/>
+			<Port Id="1" Dir="OUT"/>
+			<Port Id="0" Dir="OUT"/>
+		</Bus>
+		<Port Id="CORE_CLK" Dir="IN"/>
+		<Port Id="CLK" Dir="IN"/>
+		<Port Id="RESET" Dir="IN"/>
+		<Port Id="READY" Dir="IN"/>
+		<Port Id="INTR" Dir="IN"/>
+		<Port Id="NMI" Dir="IN"/>
+		<Port Id="A19" Dir="OUT"/>
+		<Port Id="A18" Dir="OUT"/>
+		<Port Id="A17" Dir="OUT"/>
+		<Port Id="A16" Dir="OUT"/>
+		<Port Id="A15" Dir="OUT"/>
+		<Port Id="A14" Dir="OUT"/>
+		<Port Id="A13" Dir="OUT"/>
+		<Port Id="A12" Dir="OUT"/>
+		<Port Id="A11" Dir="OUT"/>
+		<Port Id="A10" Dir="OUT"/>
+		<Port Id="A9" Dir="OUT"/>
+		<Port Id="A8" Dir="OUT"/>
+		<Port Id="AD7" Dir="INOUT"/>
+		<Port Id="AD6" Dir="INOUT"/>
+		<Port Id="AD5" Dir="INOUT"/>
+		<Port Id="AD4" Dir="INOUT"/>
+		<Port Id="AD3" Dir="INOUT"/>
+		<Port Id="AD2" Dir="INOUT"/>
+		<Port Id="AD1" Dir="INOUT"/>
+		<Port Id="AD0" Dir="INOUT"/>
+		<Port Id="ALE" Dir="OUT"/>
+		<Port Id="INTA_n" Dir="OUT"/>
+		<Port Id="RD_n" Dir="OUT"/>
+		<Port Id="WR_n" Dir="OUT"/>
+		<Port Id="IOM" Dir="OUT"/>
+		<Port Id="DTR" Dir="OUT"/>
+		<Port Id="DEN" Dir="OUT"/>
+		<Port Id="SSO_n" Dir="OUT"/>
+		<Port Id="SRAM_CE_n" Dir="OUT"/>
+		<Port Id="SRAM_OE_n" Dir="OUT"/>
+		<Port Id="SRAM_WE_n" Dir="OUT"/>
+		<Port Id="BUF1_OE_n" Dir="OUT"/>
+		<Port Id="BUF2_OE_n" Dir="OUT"/>
+		<Port Id="BUF2_DIR" Dir="OUT"/>
+	</Ifc>
+</Interface>
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/wt/java_command_handlers.wdf b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/wt/java_command_handlers.wdf
new file mode 100644
index 0000000..9880428
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/wt/java_command_handlers.wdf
@@ -0,0 +1,3 @@
+version:1
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766564657369676e:31:00:00
+eof:3611541694
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/wt/project.wpc b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/wt/project.wpc
new file mode 100644
index 0000000..5fed558
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/wt/project.wpc
@@ -0,0 +1,4 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+6d6f64655f636f756e7465727c4953454d6f6465:1
+eof:
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/wt/webtalk_pa.xml b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/wt/webtalk_pa.xml
new file mode 100644
index 0000000..b1a31f9
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.data/wt/webtalk_pa.xml
@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Sun Nov 08 20:42:30 2020">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="d73e51136f3d4e40a8c7b29f1950f477" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="GateLvl" type="DesignMode"/>
+<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="SaveDesign" value="1" type="JavaHandler"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="0" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="0" type="TclMode"/>
+<property name="ISEMode" value="18" type="ISEMode"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.ppr b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.ppr
new file mode 100644
index 0000000..e93966f
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/MCL86jr.ppr
@@ -0,0 +1,28 @@
+<?xml version="1.0"?>
+<!--Product Version: PlanAhead v14.7 (64-bit)-->
+<Project Version="4" Minor="36">
+	<FileSet Dir="sources_1" File="fileset.xml"/>
+	<FileSet Dir="constrs_1" File="fileset.xml"/>
+	<FileSet Dir="sim_1" File="fileset.xml"/>
+	<RunSet Dir="runs" File="runs.xml"/>
+	<DefaultLaunch Dir="$PRUNDIR"/>
+	<DefaultPromote Dir="$PROMOTEDIR"/>
+	<Config>
+		<Option Name="Id" Val="c0aadb5dc56a4d238ba815b3a309c7df"/>
+		<Option Name="Part" Val="xc6slx9tqg144-3"/>
+		<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+		<Option Name="TargetLanguage" Val="Verilog"/>
+		<Option Name="TargetSimulator" Val="ISim"/>
+		<Option Name="Board" Val=""/>
+		<Option Name="SourceMgmtMode" Val="All"/>
+		<Option Name="ActiveSimSet" Val="sim_1"/>
+		<Option Name="CxlOverwriteLibs" Val="1"/>
+		<Option Name="CxlFuncsim" Val="1"/>
+		<Option Name="CxlTimesim" Val="1"/>
+		<Option Name="CxlCore" Val="1"/>
+		<Option Name="CxlEdk" Val="0"/>
+		<Option Name="CxlExcludeCores" Val="1"/>
+		<Option Name="CxlExcludeSubLibs" Val="0"/>
+	</Config>
+</Project>
+
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_3/planAhead.jou b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/planAhead.jou
new file mode 100644
index 0000000..90ae010
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/planAhead.jou
@@ -0,0 +1,13 @@
+#-----------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013
+# Start of session at: Sun Nov 08 20:36:55 2020
+# Process ID: 2800
+# Log file: C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_3/planAhead.log
+# Journal file: C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_3/planAhead.jou
+#-----------------------------------------------------------
+start_gui
+source C:/MCL/MCL86/MCL86jr/MCL86jr/pa.fromNetlist.tcl
+set_property iostandard LVCMOS33 [get_ports [list NMI]]
+set_property pulltype PULLDOWN [get_ports [list NMI]]
+save_constraints
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_3/planAhead.log b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/planAhead.log
new file mode 100644
index 0000000..1052530
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/planAhead.log
@@ -0,0 +1,94 @@
+#-----------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013
+# Start of session at: Sun Nov 08 20:36:55 2020
+# Process ID: 2800
+# Log file: C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_3/planAhead.log
+# Journal file: C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_3/planAhead.jou
+#-----------------------------------------------------------
+INFO: [Common 17-78] Attempting to get a license: PlanAhead
+INFO: [Common 17-290] Got license for PlanAhead
+INFO: [Common 17-86] Your PlanAhead license expires in -1318 day(s)
+INFO: [Device 21-36] Loading parts and site information from C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
+Parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+Finished parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+start_gui
+source C:/MCL/MCL86/MCL86jr/MCL86jr/pa.fromNetlist.tcl
+# create_project -name MCL86jr -dir "C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_3" -part xc6slx9tqg144-3
+create_project: Time (s): elapsed = 00:00:05 . Memory (MB): peak = 421.867 ; gain = 68.078
+# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+# set_property edif_top_file "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {C:/MCL/MCL86/MCL86jr/MCL86jr} {ipcore_dir} }
+# add_files [list {ipcore_dir/EU4Kx32.ncf}] -fileset [get_property constrset [current_run]]
+# set_param project.pinAheadLayout  yes
+# set_property target_constrs_file "MCL86jr.ucf" [current_fileset -constrset]
+Adding file 'C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ucf' to fileset 'constrs_1'
+# add_files [list {MCL86jr.ucf}] -fileset [get_property constrset [current_run]]
+# link_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to project part: xc6slx9tqg144-3
+Release 14.7 - ngc2edif P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design MCL86jr.ngc ...
+WARNING:NetListWriters:298 - No output is written to MCL86jr.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+WARNING:NetListWriters:306 - Signal bus EU_CORE/carry<16 : 3> on block MCL86jr
+   is not reconstructed, because there are some missing bus signals.
+WARNING:NetListWriters:306 - Signal bus EU_CORE/eu_operand0<15 : 5> on block
+   MCL86jr is not reconstructed, because there are some missing bus signals.
+  finished :Prep
+Writing EDIF netlist file MCL86jr.edif ...
+ngc2edif: Total memory usage is 82840 kilobytes
+
+Parsing EDIF File [./planAhead_run_3/MCL86jr.data/cache/MCL86jr_ngc_zx.edif]
+Finished Parsing EDIF File [./planAhead_run_3/MCL86jr.data/cache/MCL86jr_ngc_zx.edif]
+Release 14.7 - ngc2edif P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design EU4Kx32.ngc ...
+WARNING:NetListWriters:298 - No output is written to EU4Kx32.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file EU4Kx32.edif ...
+ngc2edif: Total memory usage is 78744 kilobytes
+
+Reading core file 'C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/EU4Kx32.ngc' for (cell view 'EU4Kx32', library 'MCL86jr_lib', file 'MCL86jr.ngc')
+Parsing EDIF File [./planAhead_run_3/MCL86jr.data/cache/EU4Kx32_ngc_zx.edif]
+Finished Parsing EDIF File [./planAhead_run_3/MCL86jr.data/cache/EU4Kx32_ngc_zx.edif]
+INFO: [Netlist 29-17] Analyzing 8 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+WARNING: [Netlist 29-43] Netlist 'MCL86jr' is not ideal for floorplanning, since the cellview 'MCL86jr' defined in file 'MCL86jr.ngc' contains large number of primitives.  Please consider enabling hierarchy in synthesis if you want to do floorplanning.
+Loading clock regions from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/tqg144/Package.xml
+Loading io standards from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan6/IOStandards.xml
+Loading device configuration modes from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/ConfigModes.xml
+Loading list of drcs for the architecture : C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/EU4Kx32.ncf]
+Finished Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/EU4Kx32.ncf]
+Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ucf]
+Finished Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ucf]
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 8 instances were transformed.
+  IOBUF => IOBUF (OBUFT, IBUF): 8 instances
+
+Phase 0 | Netlist Checksum: c843b018
+link_design: Time (s): elapsed = 00:00:23 . Memory (MB): peak = 572.395 ; gain = 144.965
+set_property iostandard LVCMOS33 [get_ports [list NMI]]
+set_property pulltype PULLDOWN [get_ports [list NMI]]
+save_constraints
+exit
+ERROR: [PlanAhead 12-106] *** Exception: ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
+HTclEvent: DEBUG_PORT_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: SIGNAL_MODIFY   Classes: ui.views.aR 
+HTclEvent: DEBUG_CORE_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: SIGNAL_BUS_MODIFY   Classes: ui.views.aR 
+ (See C:/MCL/MCL86/MCL86jr/MCL86jr\planAhead_pid2800.debug)
+ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
+INFO: [Common 17-206] Exiting PlanAhead at Sun Nov 08 20:42:32 2020...
+INFO: [Common 17-83] Releasing license: PlanAhead
diff --git a/MCL86jr/FPGA/MCL86jr/planAhead_run_3/planAhead_run.log b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/planAhead_run.log
new file mode 100644
index 0000000..0643c57
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/planAhead_run_3/planAhead_run.log
@@ -0,0 +1,85 @@
+
+****** PlanAhead v14.7 (64-bit)
+  **** Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013
+    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
+
+INFO: [Common 17-78] Attempting to get a license: PlanAhead
+INFO: [Common 17-290] Got license for PlanAhead
+INFO: [Common 17-86] Your PlanAhead license expires in -1318 day(s)
+INFO: [Device 21-36] Loading parts and site information from C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
+Parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+Finished parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+start_gui
+source C:/MCL/MCL86/MCL86jr/MCL86jr/pa.fromNetlist.tcl
+# create_project -name MCL86jr -dir "C:/MCL/MCL86/MCL86jr/MCL86jr/planAhead_run_3" -part xc6slx9tqg144-3
+create_project: Time (s): elapsed = 00:00:05 . Memory (MB): peak = 421.867 ; gain = 68.078
+# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+# set_property edif_top_file "C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {C:/MCL/MCL86/MCL86jr/MCL86jr} {ipcore_dir} }
+# add_files [list {ipcore_dir/EU4Kx32.ncf}] -fileset [get_property constrset [current_run]]
+# set_param project.pinAheadLayout  yes
+# set_property target_constrs_file "MCL86jr.ucf" [current_fileset -constrset]
+Adding file 'C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ucf' to fileset 'constrs_1'
+# add_files [list {MCL86jr.ucf}] -fileset [get_property constrset [current_run]]
+# link_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to project part: xc6slx9tqg144-3
+Release 14.7 - ngc2edif P.20131013 (nt64)

+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

+Reading design MCL86jr.ngc ...

+WARNING:NetListWriters:298 - No output is written to MCL86jr.xncf, ignored.

+Processing design ...

+   Preping design's networks ...

+   Preping design's macros ...

+WARNING:NetListWriters:306 - Signal bus EU_CORE/carry<16 : 3> on block MCL86jr

+   is not reconstructed, because there are some missing bus signals.

+WARNING:NetListWriters:306 - Signal bus EU_CORE/eu_operand0<15 : 5> on block

+   MCL86jr is not reconstructed, because there are some missing bus signals.

+  finished :Prep

+Writing EDIF netlist file MCL86jr.edif ...

+ngc2edif: Total memory usage is 82840 kilobytes

+

+Parsing EDIF File [./planAhead_run_3/MCL86jr.data/cache/MCL86jr_ngc_zx.edif]
+Finished Parsing EDIF File [./planAhead_run_3/MCL86jr.data/cache/MCL86jr_ngc_zx.edif]
+Release 14.7 - ngc2edif P.20131013 (nt64)

+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

+Reading design EU4Kx32.ngc ...

+WARNING:NetListWriters:298 - No output is written to EU4Kx32.xncf, ignored.

+Processing design ...

+   Preping design's networks ...

+   Preping design's macros ...

+  finished :Prep

+Writing EDIF netlist file EU4Kx32.edif ...

+ngc2edif: Total memory usage is 78744 kilobytes

+

+Reading core file 'C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/EU4Kx32.ngc' for (cell view 'EU4Kx32', library 'MCL86jr_lib', file 'MCL86jr.ngc')
+Parsing EDIF File [./planAhead_run_3/MCL86jr.data/cache/EU4Kx32_ngc_zx.edif]
+Finished Parsing EDIF File [./planAhead_run_3/MCL86jr.data/cache/EU4Kx32_ngc_zx.edif]
+INFO: [Netlist 29-17] Analyzing 8 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+WARNING: [Netlist 29-43] Netlist 'MCL86jr' is not ideal for floorplanning, since the cellview 'MCL86jr' defined in file 'MCL86jr.ngc' contains large number of primitives.  Please consider enabling hierarchy in synthesis if you want to do floorplanning.
+Loading clock regions from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/tqg144/Package.xml
+Loading io standards from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan6/IOStandards.xml
+Loading device configuration modes from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/ConfigModes.xml
+Loading list of drcs for the architecture : C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/EU4Kx32.ncf]
+Finished Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/ipcore_dir/EU4Kx32.ncf]
+Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ucf]
+Finished Parsing UCF File [C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.ucf]
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 8 instances were transformed.
+  IOBUF => IOBUF (OBUFT, IBUF): 8 instances
+
+Phase 0 | Netlist Checksum: c843b018
+link_design: Time (s): elapsed = 00:00:23 . Memory (MB): peak = 572.395 ; gain = 144.965
+set_property iostandard LVCMOS33 [get_ports [list NMI]]
+set_property pulltype PULLDOWN [get_ports [list NMI]]
+save_constraints
+exit
+ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
+INFO: [Common 17-206] Exiting PlanAhead at Sun Nov 08 20:42:32 2020...
+INFO: [Common 17-83] Releasing license: PlanAhead
diff --git a/MCL86jr/FPGA/MCL86jr/usage_statistics_webtalk.html b/MCL86jr/FPGA/MCL86jr/usage_statistics_webtalk.html
new file mode 100644
index 0000000..068d919
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/usage_statistics_webtalk.html
@@ -0,0 +1,2562 @@
+<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>&nbsp;<BR><HR>&nbsp;<BR>
+<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>Software Version and Target Device</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD>
+<TD><xtag-property name="ProductVersion">ISE:14.7</xtag-property><xtag-property name="ProductConfiguration"> (WebPack)</xtag-property><xtag-property name="BuildVersion"> - P.20131013</xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B>Target Family:</B></TD>
+<TD><xtag-property name="TargetFamily">Spartan6</xtag-property></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>OS Platform:</B></TD>
+<TD><xtag-property name="OSPlatform">NT64</xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD><xtag-property name="TargetDevice">xc6slx9</xtag-property></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
+<TD><xtag-property name="RandomID">6f5550ea45af4678971d9a741e8cb7b1</xtag-property>.<xtag-property name="ProjectID">0F0A51A7D06B470287A989EDCA362445</xtag-property>.<xtag-property name="ProjectIteration">114</xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
+<TD><xtag-property name="TargetPackage">tqg144</xtag-property></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Registration ID</B></TD>
+<TD><xtag-property name="RegistrationID">174191283_174191284_0_212</xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B>Target Speed:</B></TD>
+<TD><xtag-property name="TargetSpeed">-3</xtag-property></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
+<TD><xtag-property name="Date Generated">2020-11-11T19:11:55</xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
+<TD><xtag-property name="ToolFlow">ISE</xtag-property></TD>
+</TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<xtag-section name="UserEnvironment">
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>User Environment</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Name</xtag-env-param-name></B></TD>
+<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft Windows 7 , 64-bit</xtag-env-param-value></xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Release</xtag-env-param-name></B></TD>
+<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>Service Pack 1  (build 7601)</xtag-env-param-value></xtag-property></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Name</xtag-env-param-name></B></TD>
+<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value>Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz</xtag-env-param-value></xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Speed</xtag-env-param-name></B></TD>
+<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>2492 MHz</xtag-env-param-value></xtag-property></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Name</xtag-env-param-name></B></TD>
+<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft Windows 7 , 64-bit</xtag-env-param-value></xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Release</xtag-env-param-name></B></TD>
+<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>Service Pack 1  (build 7601)</xtag-env-param-value></xtag-property></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Name</xtag-env-param-name></B></TD>
+<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value>Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz</xtag-env-param-value></xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Speed</xtag-env-param-name></B></TD>
+<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>2492 MHz</xtag-env-param-value></xtag-property></TD>
+</TR>
+</xtag-section></TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Device Usage Statistics</B></TD></TR>
+<TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Macro Statistics</B></TD><TD><B>Miscellaneous Statistics</B></TD><TD><B>Net Statistics</B></TD><TD><B>Site Usage</B></TD></TR><TR VALIGN=TOP>
+<xtag-section name="MacroStatistics">
+<TD>
+<xtag-group><xtag-group-name name="Adders/Subtractors=7">Adders/Subtractors=7</xtag-group-name>
+<UL>
+<LI><xtag-item1>13-bit adder=1</xtag-item1></LI>
+<LI><xtag-item1>16-bit adder=1</xtag-item1></LI>
+<LI><xtag-item1>20-bit adder=4</xtag-item1></LI>
+<LI><xtag-item1>8-bit adder=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="Comparators=4">Comparators=4</xtag-group-name>
+<UL>
+<LI><xtag-item1>1-bit comparator equal=1</xtag-item1></LI>
+<LI><xtag-item1>2-bit comparator equal=1</xtag-item1></LI>
+<LI><xtag-item1>4-bit comparator greater=2</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="Counters=5">Counters=5</xtag-group-name>
+<UL>
+<LI><xtag-item1>13-bit down counter=1</xtag-item1></LI>
+<LI><xtag-item1>16-bit up counter=2</xtag-item1></LI>
+<LI><xtag-item1>26-bit up counter=1</xtag-item1></LI>
+<LI><xtag-item1>27-bit up counter=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="Multiplexers=209">Multiplexers=209</xtag-group-name>
+<UL>
+<LI><xtag-item1>1-bit 16-to-1 multiplexer=32</xtag-item1></LI>
+<LI><xtag-item1>1-bit 2-to-1 multiplexer=131</xtag-item1></LI>
+<LI><xtag-item1>1-bit 4-to-1 multiplexer=16</xtag-item1></LI>
+<LI><xtag-item1>13-bit 2-to-1 multiplexer=7</xtag-item1></LI>
+<LI><xtag-item1>16-bit 2-to-1 multiplexer=1</xtag-item1></LI>
+<LI><xtag-item1>2-bit 2-to-1 multiplexer=1</xtag-item1></LI>
+<LI><xtag-item1>20-bit 2-to-1 multiplexer=3</xtag-item1></LI>
+<LI><xtag-item1>20-bit 7-to-1 multiplexer=1</xtag-item1></LI>
+<LI><xtag-item1>3-bit 2-to-1 multiplexer=1</xtag-item1></LI>
+<LI><xtag-item1>52-bit 2-to-1 multiplexer=1</xtag-item1></LI>
+<LI><xtag-item1>8-bit 2-to-1 multiplexer=14</xtag-item1></LI>
+<LI><xtag-item1>8-bit 4-to-1 multiplexer=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="Registers=913">Registers=913</xtag-group-name>
+<UL>
+<LI><xtag-item1>Flip-Flops=913</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="Xors=20">Xors=20</xtag-group-name>
+<UL>
+<LI><xtag-item1>1-bit xor2=2</xtag-item1></LI>
+<LI><xtag-item1>1-bit xor3=16</xtag-item1></LI>
+<LI><xtag-item1>1-bit xor8=1</xtag-item1></LI>
+<LI><xtag-item1>16-bit xor2=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+</TD>
+</xtag-section>
+<xtag-section name="DesignStatistics">
+<TD>
+<xtag-group><xtag-group-name name="MiscellaneousStatistics">MiscellaneousStatistics</xtag-group-name>
+<UL>
+<LI><xtag-item1>AGG_BONDED_IO=75</xtag-item1></LI>
+<LI><xtag-item1>AGG_IO=75</xtag-item1></LI>
+<LI><xtag-item1>AGG_LOCED_IO=75</xtag-item1></LI>
+<LI><xtag-item1>AGG_SLICE=381</xtag-item1></LI>
+<LI><xtag-item1>NUM_BONDED_IOB=75</xtag-item1></LI>
+<LI><xtag-item1>NUM_BSFULL=522</xtag-item1></LI>
+<LI><xtag-item1>NUM_BSLUTONLY=437</xtag-item1></LI>
+<LI><xtag-item1>NUM_BSREGONLY=238</xtag-item1></LI>
+<LI><xtag-item1>NUM_BSUSED=1197</xtag-item1></LI>
+<LI><xtag-item1>NUM_BUFG=1</xtag-item1></LI>
+<LI><xtag-item1>NUM_BUFIO2=1</xtag-item1></LI>
+<LI><xtag-item1>NUM_DCM=1</xtag-item1></LI>
+<LI><xtag-item1>NUM_ILOGIC2=12</xtag-item1></LI>
+<LI><xtag-item1>NUM_IOB_FF=39</xtag-item1></LI>
+<LI><xtag-item1>NUM_LOCED_IOB=75</xtag-item1></LI>
+<LI><xtag-item1>NUM_LOGIC_O5ANDO6=152</xtag-item1></LI>
+<LI><xtag-item1>NUM_LOGIC_O5ONLY=54</xtag-item1></LI>
+<LI><xtag-item1>NUM_LOGIC_O6ONLY=681</xtag-item1></LI>
+<LI><xtag-item1>NUM_LUT_RT_DRIVES_CARRY4=6</xtag-item1></LI>
+<LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=8</xtag-item1></LI>
+<LI><xtag-item1>NUM_LUT_RT_EXO5=8</xtag-item1></LI>
+<LI><xtag-item1>NUM_LUT_RT_EXO6=6</xtag-item1></LI>
+<LI><xtag-item1>NUM_LUT_RT_O5=12</xtag-item1></LI>
+<LI><xtag-item1>NUM_LUT_RT_O6=54</xtag-item1></LI>
+<LI><xtag-item1>NUM_OLOGIC2=27</xtag-item1></LI>
+<LI><xtag-item1>NUM_RAMB16BWER=7</xtag-item1></LI>
+<LI><xtag-item1>NUM_RAMB8BWER=1</xtag-item1></LI>
+<LI><xtag-item1>NUM_SLICEL=83</xtag-item1></LI>
+<LI><xtag-item1>NUM_SLICEM=15</xtag-item1></LI>
+<LI><xtag-item1>NUM_SLICEX=283</xtag-item1></LI>
+<LI><xtag-item1>NUM_SLICE_CARRY4=49</xtag-item1></LI>
+<LI><xtag-item1>NUM_SLICE_CONTROLSET=40</xtag-item1></LI>
+<LI><xtag-item1>NUM_SLICE_CYINIT=1240</xtag-item1></LI>
+<LI><xtag-item1>NUM_SLICE_F7MUX=59</xtag-item1></LI>
+<LI><xtag-item1>NUM_SLICE_F8MUX=25</xtag-item1></LI>
+<LI><xtag-item1>NUM_SLICE_FF=853</xtag-item1></LI>
+<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=107</xtag-item1></LI>
+<LI><xtag-item1>NUM_SRL_O5ANDO6=56</xtag-item1></LI>
+<LI><xtag-item1>NUM_SRL_O6ONLY=2</xtag-item1></LI>
+<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=41</xtag-item1></LI>
+<LI><xtag-item1>Xilinx Core blk_mem_gen_v7_3, Xilinx CORE Generator 14.7=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+</TD>
+<TD>
+<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name>
+<UL>
+<LI><xtag-item1>NumNets_Active=1664</xtag-item1></LI>
+<LI><xtag-item1>NumNets_Gnd=1</xtag-item1></LI>
+<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=107</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=218</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=1</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=8</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_BUFIOINP=1</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=301</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=12</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=454</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=3302</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_GENERIC=126</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=84</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_INPUT=202</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=115</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=103</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=4151</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=1588</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=1565</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=82</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=22</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=1388</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_PINFEED=4915</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_PINFEED2=31</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_QUAD=2838</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=595</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_SINGLE=3576</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Gnd_BOUNCEIN=127</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Gnd_CLKPIN=1</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Gnd_CNTRLPIN=3</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Gnd_DOUBLE=23</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Gnd_GENERIC=3</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Gnd_HGNDOUT=48</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Gnd_INPUT=779</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Gnd_IOBIN2OUT=3</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Gnd_IOBOUTPUT=3</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Gnd_LUTINPUT=232</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Gnd_OUTBOUND=50</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Gnd_OUTPUT=57</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Gnd_PADINPUT=3</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Gnd_PINBOUNCE=202</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Gnd_PINFEED=937</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Gnd_REGINPUT=3</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Gnd_SINGLE=50</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Vcc_CNTRLPIN=1</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=106</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Vcc_INPUT=4</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Vcc_KVCCOUT=15</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=334</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Vcc_PINBOUNCE=1</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=338</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SiteStatistics">SiteStatistics</xtag-group-name>
+<UL>
+<LI><xtag-item1>BUFG-BUFGMUX=1</xtag-item1></LI>
+<LI><xtag-item1>IOB-IOBM=36</xtag-item1></LI>
+<LI><xtag-item1>IOB-IOBS=39</xtag-item1></LI>
+<LI><xtag-item1>SLICEL-SLICEM=41</xtag-item1></LI>
+<LI><xtag-item1>SLICEX-SLICEL=53</xtag-item1></LI>
+<LI><xtag-item1>SLICEX-SLICEM=57</xtag-item1></LI>
+</UL>
+</xtag-group>
+</TD>
+</xtag-section>
+<xtag-section name="DeviceUsage">
+<TD>
+<xtag-group><xtag-group-name name="SiteSummary">SiteSummary</xtag-group-name>
+<UL>
+<LI><xtag-item2>BUFG=1</xtag-item2></LI>
+<LI><xtag-item2>BUFG_BUFG=1</xtag-item2></LI>
+<LI><xtag-item2>BUFIO2=1</xtag-item2></LI>
+<LI><xtag-item2>BUFIO2_BUFIO2=1</xtag-item2></LI>
+<LI><xtag-item2>CARRY4=49</xtag-item2></LI>
+<LI><xtag-item2>DCM=1</xtag-item2></LI>
+<LI><xtag-item2>DCM_DCM=1</xtag-item2></LI>
+<LI><xtag-item2>FF_SR=96</xtag-item2></LI>
+<LI><xtag-item2>HARD0=19</xtag-item2></LI>
+<LI><xtag-item2>ILOGIC2=12</xtag-item2></LI>
+<LI><xtag-item2>ILOGIC2_IFF=12</xtag-item2></LI>
+<LI><xtag-item2>IOB=75</xtag-item2></LI>
+<LI><xtag-item2>IOB_IMUX=22</xtag-item2></LI>
+<LI><xtag-item2>IOB_INBUF=22</xtag-item2></LI>
+<LI><xtag-item2>IOB_OUTBUF=69</xtag-item2></LI>
+<LI><xtag-item2>LUT5=226</xtag-item2></LI>
+<LI><xtag-item2>LUT6=893</xtag-item2></LI>
+<LI><xtag-item2>LUT_OR_MEM5=56</xtag-item2></LI>
+<LI><xtag-item2>LUT_OR_MEM6=58</xtag-item2></LI>
+<LI><xtag-item2>OLOGIC2=27</xtag-item2></LI>
+<LI><xtag-item2>OLOGIC2_OUTFF=27</xtag-item2></LI>
+<LI><xtag-item2>PAD=75</xtag-item2></LI>
+<LI><xtag-item2>PULL_OR_KEEP1=1</xtag-item2></LI>
+<LI><xtag-item2>RAMB16BWER=7</xtag-item2></LI>
+<LI><xtag-item2>RAMB16BWER_RAMB16BWER=7</xtag-item2></LI>
+<LI><xtag-item2>RAMB8BWER=1</xtag-item2></LI>
+<LI><xtag-item2>RAMB8BWER_RAMB8BWER=1</xtag-item2></LI>
+<LI><xtag-item2>REG_SR=757</xtag-item2></LI>
+<LI><xtag-item2>SELMUX2_1=96</xtag-item2></LI>
+<LI><xtag-item2>SLICEL=83</xtag-item2></LI>
+<LI><xtag-item2>SLICEM=15</xtag-item2></LI>
+<LI><xtag-item2>SLICEX=283</xtag-item2></LI>
+</UL>
+</xtag-group>
+</TD>
+</xtag-section>
+</TR></TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Configuration Data</B></TD></TR><TR VALIGN=TOP>
+<xtag-section name="ReportConfigData">
+<TD>
+<xtag-group><xtag-group-name name="BUFIO2_BUFIO2">BUFIO2_BUFIO2</xtag-group-name>
+<UL>
+<LI><xtag-item3>DIVIDE=[1:1]</xtag-item3></LI>
+<LI><xtag-item3>DIVIDE_BYPASS=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>I_INVERT=[FALSE:1]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="DCM">DCM</xtag-group-name>
+<UL>
+<LI><xtag-item3>PSCLK=[PSCLK_INV:0] [PSCLK:1]</xtag-item3></LI>
+<LI><xtag-item3>PSEN=[PSEN_INV:0] [PSEN:1]</xtag-item3></LI>
+<LI><xtag-item3>PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>RST=[RST:1] [RST_INV:0]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="DCM_DCM">DCM_DCM</xtag-group-name>
+<UL>
+<LI><xtag-item3>CLKDV_DIVIDE=[2.0:1]</xtag-item3></LI>
+<LI><xtag-item3>CLKIN_DIVIDE_BY_2=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>CLKOUT_PHASE_SHIFT=[NONE:1]</xtag-item3></LI>
+<LI><xtag-item3>CLK_FEEDBACK=[NONE:1]</xtag-item3></LI>
+<LI><xtag-item3>DESKEW_ADJUST=[5:1]</xtag-item3></LI>
+<LI><xtag-item3>DFS_FREQUENCY_MODE=[LOW:1]</xtag-item3></LI>
+<LI><xtag-item3>DLL_FREQUENCY_MODE=[LOW:1]</xtag-item3></LI>
+<LI><xtag-item3>DSS_MODE=[NONE:1]</xtag-item3></LI>
+<LI><xtag-item3>DUTY_CYCLE_CORRECTION=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PSCLK=[PSCLK_INV:0] [PSCLK:1]</xtag-item3></LI>
+<LI><xtag-item3>PSEN=[PSEN_INV:0] [PSEN:1]</xtag-item3></LI>
+<LI><xtag-item3>PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>RST=[RST:1] [RST_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>STARTUP_WAIT=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>VERY_HIGH_FREQUENCY=[FALSE:1]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
+<UL>
+<LI><xtag-item3>CK=[CK:96] [CK_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>SRINIT=[SRINIT0:95] [SRINIT1:1]</xtag-item3></LI>
+<LI><xtag-item3>SYNC_ATTR=[ASYNC:57] [SYNC:39]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="ILOGIC2">ILOGIC2</xtag-group-name>
+<UL>
+<LI><xtag-item3>CLK0=[CLK0_INV:0] [CLK0:12]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="ILOGIC2_IFF">ILOGIC2_IFF</xtag-group-name>
+<UL>
+<LI><xtag-item3>CLK0=[CLK0_INV:0] [CLK0:12]</xtag-item3></LI>
+<LI><xtag-item3>IFFTYPE=[FF:12]</xtag-item3></LI>
+<LI><xtag-item3>SRINIT_Q=[0:12]</xtag-item3></LI>
+<LI><xtag-item3>SRTYPE_Q=[SYNC:12]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name>
+<UL>
+<LI><xtag-item3>SUSPEND=[3STATE:69]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="LUT_OR_MEM5">LUT_OR_MEM5</xtag-group-name>
+<UL>
+<LI><xtag-item3>CLK=[CLK:56] [CLK_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>LUT_OR_MEM=[RAM:56]</xtag-item3></LI>
+<LI><xtag-item3>RAMMODE=[SRL16:56]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="LUT_OR_MEM6">LUT_OR_MEM6</xtag-group-name>
+<UL>
+<LI><xtag-item3>CLK=[CLK:58] [CLK_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>LUT_OR_MEM=[RAM:58]</xtag-item3></LI>
+<LI><xtag-item3>RAMMODE=[SRL16:58]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="OLOGIC2">OLOGIC2</xtag-group-name>
+<UL>
+<LI><xtag-item3>CLK0=[CLK0_INV:0] [CLK0:27]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="OLOGIC2_OUTFF">OLOGIC2_OUTFF</xtag-group-name>
+<UL>
+<LI><xtag-item3>CK0=[CK0_INV:0] [CK0:27]</xtag-item3></LI>
+<LI><xtag-item3>OUTFFTYPE=[FF:27]</xtag-item3></LI>
+<LI><xtag-item3>SRINIT_OQ=[0:23] [1:4]</xtag-item3></LI>
+<LI><xtag-item3>SRTYPE_OQ=[SYNC:6]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="PLL_ADV">PLL_ADV</xtag-group-name>
+<UL>
+<LI><xtag-item3>RST=[RST:1] [RST_INV:0]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="PLL_ADV_PLL_ADV">PLL_ADV_PLL_ADV</xtag-group-name>
+<UL>
+<LI><xtag-item3>BANDWIDTH=[OPTIMIZED:1]</xtag-item3></LI>
+<LI><xtag-item3>CLK_FEEDBACK=[CLKFBOUT:1]</xtag-item3></LI>
+<LI><xtag-item3>COMPENSATION=[INTERNAL:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_ADD_LEAKAGE=[2:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_AVDD_COMP_SET=[2:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLAMP_BYPASS=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLAMP_REF_SEL=[1:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLK0MX=[0:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLK1MX=[0:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLK2MX=[0:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLK3MX=[0:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLK4MX=[0:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLK5MX=[0:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKBURST_CNT=[0:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKBURST_ENABLE=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKCNTRL=[0:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKFBMX=[0:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKFBOUT2_EDGE=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKFBOUT2_NOCOUNT=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKFBOUT_EDGE=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKFBOUT_EN=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKFBOUT_NOCOUNT=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKOUT0_EDGE=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKOUT0_EN=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKOUT0_NOCOUNT=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKOUT1_EDGE=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKOUT1_EN=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKOUT1_NOCOUNT=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKOUT2_EDGE=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKOUT2_EN=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKOUT2_NOCOUNT=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKOUT3_EDGE=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKOUT3_EN=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKOUT3_NOCOUNT=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKOUT4_EDGE=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKOUT4_EN=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKOUT4_NOCOUNT=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKOUT5_EDGE=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKOUT5_EN=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLKOUT5_NOCOUNT=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CLK_LOST_DETECT=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CP=[1:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CP_BIAS_TRIP_SHIFT=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CP_REPL=[1:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_CP_RES=[0:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_DIRECT_PATH_CNTRL=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_DIVCLK_EDGE=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_DIVCLK_NOCOUNT=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_DVDD_COMP_SET=[2:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_EN=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_EN_DLY=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_EN_LEAKAGE=[2:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_EN_TCLK0=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_EN_TCLK1=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_EN_TCLK2=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_EN_TCLK3=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_EN_VCO0=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_EN_VCO1=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_EN_VCO2=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_EN_VCO3=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_EN_VCO4=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_EN_VCO5=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_EN_VCO6=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_EN_VCO7=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_EN_VCO_DIV1=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_EN_VCO_DIV6=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_INTFB=[0:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_IO_CLKSRC=[0:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_LFHF=[3:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_LOCK_FB_DLY=[3:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_LOCK_REF_DLY=[5:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_MAN_LF_EN=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_NBTI_EN=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_PFD_CNTRL=[8:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_PFD_DLY=[1:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_PWRD_CFG=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_REG_INPUT=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_RES=[1:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_SEL_SLIPD=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_SKEW_CNTRL=[0:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_TEST_IN_WINDOW=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_VDD_SEL=[0:1]</xtag-item3></LI>
+<LI><xtag-item3>PLL_VLFHIGH_DIS=[TRUE:1]</xtag-item3></LI>
+<LI><xtag-item3>RST=[RST:1] [RST_INV:0]</xtag-item3></LI>
+</UL>
+</TD>
+<TD>
+</xtag-group>
+<xtag-group><xtag-group-name name="PULL_OR_KEEP1">PULL_OR_KEEP1</xtag-group-name>
+<UL>
+<LI><xtag-item3>PULLTYPE=[PULLDOWN:1]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="RAMB16BWER">RAMB16BWER</xtag-group-name>
+<UL>
+<LI><xtag-item3>CLKA=[CLKA_INV:0] [CLKA:7]</xtag-item3></LI>
+<LI><xtag-item3>CLKB=[CLKB_INV:0] [CLKB:7]</xtag-item3></LI>
+<LI><xtag-item3>ENA=[ENA_INV:2] [ENA:5]</xtag-item3></LI>
+<LI><xtag-item3>ENB=[ENB_INV:0] [ENB:7]</xtag-item3></LI>
+<LI><xtag-item3>REGCEA=[REGCEA_INV:0] [REGCEA:7]</xtag-item3></LI>
+<LI><xtag-item3>REGCEB=[REGCEB_INV:0] [REGCEB:7]</xtag-item3></LI>
+<LI><xtag-item3>RSTA=[RSTA:7] [RSTA_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>RSTB=[RSTB:7] [RSTB_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>WEA0=[WEA0:7] [WEA0_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>WEA1=[WEA1:7] [WEA1_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>WEA2=[WEA2:7] [WEA2_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>WEA3=[WEA3_INV:0] [WEA3:7]</xtag-item3></LI>
+<LI><xtag-item3>WEB0=[WEB0:7] [WEB0_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>WEB1=[WEB1:7] [WEB1_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>WEB2=[WEB2_INV:0] [WEB2:7]</xtag-item3></LI>
+<LI><xtag-item3>WEB3=[WEB3:7] [WEB3_INV:0]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="RAMB16BWER_RAMB16BWER">RAMB16BWER_RAMB16BWER</xtag-group-name>
+<UL>
+<LI><xtag-item3>CLKA=[CLKA_INV:0] [CLKA:7]</xtag-item3></LI>
+<LI><xtag-item3>CLKB=[CLKB_INV:0] [CLKB:7]</xtag-item3></LI>
+<LI><xtag-item3>DATA_WIDTH_A=[4:3] [9:4]</xtag-item3></LI>
+<LI><xtag-item3>DATA_WIDTH_B=[4:3] [9:4]</xtag-item3></LI>
+<LI><xtag-item3>DOA_REG=[0:7]</xtag-item3></LI>
+<LI><xtag-item3>DOB_REG=[0:7]</xtag-item3></LI>
+<LI><xtag-item3>ENA=[ENA_INV:2] [ENA:5]</xtag-item3></LI>
+<LI><xtag-item3>ENB=[ENB_INV:0] [ENB:7]</xtag-item3></LI>
+<LI><xtag-item3>EN_RSTRAM_A=[FALSE:7]</xtag-item3></LI>
+<LI><xtag-item3>EN_RSTRAM_B=[FALSE:7]</xtag-item3></LI>
+<LI><xtag-item3>RAM_MODE=[TDP:7]</xtag-item3></LI>
+<LI><xtag-item3>REGCEA=[REGCEA_INV:0] [REGCEA:7]</xtag-item3></LI>
+<LI><xtag-item3>REGCEB=[REGCEB_INV:0] [REGCEB:7]</xtag-item3></LI>
+<LI><xtag-item3>RSTA=[RSTA:7] [RSTA_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>RSTB=[RSTB:7] [RSTB_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>RSTTYPE=[SYNC:7]</xtag-item3></LI>
+<LI><xtag-item3>RST_PRIORITY_A=[CE:7]</xtag-item3></LI>
+<LI><xtag-item3>RST_PRIORITY_B=[CE:7]</xtag-item3></LI>
+<LI><xtag-item3>WEA0=[WEA0:7] [WEA0_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>WEA1=[WEA1:7] [WEA1_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>WEA2=[WEA2:7] [WEA2_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>WEA3=[WEA3_INV:0] [WEA3:7]</xtag-item3></LI>
+<LI><xtag-item3>WEB0=[WEB0:7] [WEB0_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>WEB1=[WEB1:7] [WEB1_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>WEB2=[WEB2_INV:0] [WEB2:7]</xtag-item3></LI>
+<LI><xtag-item3>WEB3=[WEB3:7] [WEB3_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>WRITE_MODE_A=[WRITE_FIRST:7]</xtag-item3></LI>
+<LI><xtag-item3>WRITE_MODE_B=[WRITE_FIRST:7]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="RAMB8BWER">RAMB8BWER</xtag-group-name>
+<UL>
+<LI><xtag-item3>CLKAWRCLK=[CLKAWRCLK:1] [CLKAWRCLK_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:1]</xtag-item3></LI>
+<LI><xtag-item3>ENAWREN=[ENAWREN:1] [ENAWREN_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:1]</xtag-item3></LI>
+<LI><xtag-item3>REGCEA=[REGCEA_INV:0] [REGCEA:1]</xtag-item3></LI>
+<LI><xtag-item3>REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:1]</xtag-item3></LI>
+<LI><xtag-item3>RSTA=[RSTA:1] [RSTA_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>RSTBRST=[RSTBRST:1] [RSTBRST_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>WEAWEL0=[WEAWEL0:1] [WEAWEL0_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:1]</xtag-item3></LI>
+<LI><xtag-item3>WEBWEU0=[WEBWEU0:1] [WEBWEU0_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>WEBWEU1=[WEBWEU1:1] [WEBWEU1_INV:0]</xtag-item3></LI>
+</UL>
+</TD>
+<TD>
+</xtag-group>
+<xtag-group><xtag-group-name name="RAMB8BWER_RAMB8BWER">RAMB8BWER_RAMB8BWER</xtag-group-name>
+<UL>
+<LI><xtag-item3>CLKAWRCLK=[CLKAWRCLK:1] [CLKAWRCLK_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:1]</xtag-item3></LI>
+<LI><xtag-item3>DATA_WIDTH_A=[2:1]</xtag-item3></LI>
+<LI><xtag-item3>DATA_WIDTH_B=[2:1]</xtag-item3></LI>
+<LI><xtag-item3>DOA_REG=[0:1]</xtag-item3></LI>
+<LI><xtag-item3>DOB_REG=[0:1]</xtag-item3></LI>
+<LI><xtag-item3>ENAWREN=[ENAWREN:1] [ENAWREN_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:1]</xtag-item3></LI>
+<LI><xtag-item3>EN_RSTRAM_A=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>EN_RSTRAM_B=[FALSE:1]</xtag-item3></LI>
+<LI><xtag-item3>RAM_MODE=[TDP:1]</xtag-item3></LI>
+<LI><xtag-item3>REGCEA=[REGCEA_INV:0] [REGCEA:1]</xtag-item3></LI>
+<LI><xtag-item3>REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:1]</xtag-item3></LI>
+<LI><xtag-item3>RSTA=[RSTA:1] [RSTA_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>RSTBRST=[RSTBRST:1] [RSTBRST_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>RSTTYPE=[SYNC:1]</xtag-item3></LI>
+<LI><xtag-item3>RST_PRIORITY_A=[CE:1]</xtag-item3></LI>
+<LI><xtag-item3>RST_PRIORITY_B=[CE:1]</xtag-item3></LI>
+<LI><xtag-item3>WEAWEL0=[WEAWEL0:1] [WEAWEL0_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:1]</xtag-item3></LI>
+<LI><xtag-item3>WEBWEU0=[WEBWEU0:1] [WEBWEU0_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>WEBWEU1=[WEBWEU1:1] [WEBWEU1_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>WRITE_MODE_A=[WRITE_FIRST:1]</xtag-item3></LI>
+<LI><xtag-item3>WRITE_MODE_B=[WRITE_FIRST:1]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
+<UL>
+<LI><xtag-item3>CK=[CK:757] [CK_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>LATCH_OR_FF=[FF:757]</xtag-item3></LI>
+<LI><xtag-item3>SRINIT=[SRINIT0:729] [SRINIT1:28]</xtag-item3></LI>
+<LI><xtag-item3>SYNC_ATTR=[ASYNC:153] [SYNC:604]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
+<UL>
+<LI><xtag-item3>CLK=[CLK:54] [CLK_INV:0]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name>
+<UL>
+<LI><xtag-item3>CLK=[CLK:15] [CLK_INV:0]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
+<UL>
+<LI><xtag-item3>CLK=[CLK:205] [CLK_INV:0]</xtag-item3></LI>
+</UL>
+</xtag-group>
+</TD>
+</xtag-section>
+</TR></TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Pin Data</B></TD></TR><TR VALIGN=TOP>
+<xtag-section name="ReportConfigData">
+<TD>
+<xtag-group><xtag-group-name name="BUFG">BUFG</xtag-group-name>
+<UL>
+<LI><xtag-item1>I0=1</xtag-item1></LI>
+<LI><xtag-item1>O=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="BUFG_BUFG">BUFG_BUFG</xtag-group-name>
+<UL>
+<LI><xtag-item1>I0=1</xtag-item1></LI>
+<LI><xtag-item1>O=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="BUFIO2">BUFIO2</xtag-group-name>
+<UL>
+<LI><xtag-item1>DIVCLK=1</xtag-item1></LI>
+<LI><xtag-item1>I=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="BUFIO2_BUFIO2">BUFIO2_BUFIO2</xtag-group-name>
+<UL>
+<LI><xtag-item1>DIVCLK=1</xtag-item1></LI>
+<LI><xtag-item1>I=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="CARRY4">CARRY4</xtag-group-name>
+<UL>
+<LI><xtag-item1>CIN=38</xtag-item1></LI>
+<LI><xtag-item1>CO3=38</xtag-item1></LI>
+<LI><xtag-item1>CYINIT=11</xtag-item1></LI>
+<LI><xtag-item1>DI0=47</xtag-item1></LI>
+<LI><xtag-item1>DI1=45</xtag-item1></LI>
+<LI><xtag-item1>DI2=45</xtag-item1></LI>
+<LI><xtag-item1>DI3=38</xtag-item1></LI>
+<LI><xtag-item1>O0=49</xtag-item1></LI>
+<LI><xtag-item1>O1=47</xtag-item1></LI>
+<LI><xtag-item1>O2=45</xtag-item1></LI>
+<LI><xtag-item1>O3=45</xtag-item1></LI>
+<LI><xtag-item1>S0=49</xtag-item1></LI>
+<LI><xtag-item1>S1=47</xtag-item1></LI>
+<LI><xtag-item1>S2=45</xtag-item1></LI>
+<LI><xtag-item1>S3=45</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="DCM">DCM</xtag-group-name>
+<UL>
+<LI><xtag-item1>CLKFB=1</xtag-item1></LI>
+<LI><xtag-item1>CLKFX=1</xtag-item1></LI>
+<LI><xtag-item1>CLKIN=1</xtag-item1></LI>
+<LI><xtag-item1>PSCLK=1</xtag-item1></LI>
+<LI><xtag-item1>PSEN=1</xtag-item1></LI>
+<LI><xtag-item1>PSINCDEC=1</xtag-item1></LI>
+<LI><xtag-item1>RST=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="DCM_DCM">DCM_DCM</xtag-group-name>
+<UL>
+<LI><xtag-item1>CLKFB=1</xtag-item1></LI>
+<LI><xtag-item1>CLKFX=1</xtag-item1></LI>
+<LI><xtag-item1>CLKIN=1</xtag-item1></LI>
+<LI><xtag-item1>PSCLK=1</xtag-item1></LI>
+<LI><xtag-item1>PSEN=1</xtag-item1></LI>
+<LI><xtag-item1>PSINCDEC=1</xtag-item1></LI>
+<LI><xtag-item1>RST=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
+<UL>
+<LI><xtag-item1>CE=83</xtag-item1></LI>
+<LI><xtag-item1>CK=96</xtag-item1></LI>
+<LI><xtag-item1>D=96</xtag-item1></LI>
+<LI><xtag-item1>Q=96</xtag-item1></LI>
+<LI><xtag-item1>SR=39</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="HARD0">HARD0</xtag-group-name>
+<UL>
+<LI><xtag-item1>0=19</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="ILOGIC2">ILOGIC2</xtag-group-name>
+<UL>
+<LI><xtag-item1>CLK0=12</xtag-item1></LI>
+<LI><xtag-item1>D=12</xtag-item1></LI>
+<LI><xtag-item1>Q4=12</xtag-item1></LI>
+<LI><xtag-item1>SR=12</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="ILOGIC2_IFF">ILOGIC2_IFF</xtag-group-name>
+<UL>
+<LI><xtag-item1>CLK0=12</xtag-item1></LI>
+<LI><xtag-item1>D=12</xtag-item1></LI>
+<LI><xtag-item1>Q1=12</xtag-item1></LI>
+<LI><xtag-item1>SR=12</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="IOB">IOB</xtag-group-name>
+<UL>
+<LI><xtag-item1>I=22</xtag-item1></LI>
+<LI><xtag-item1>O=69</xtag-item1></LI>
+<LI><xtag-item1>PAD=75</xtag-item1></LI>
+<LI><xtag-item1>T=16</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="IOB_IMUX">IOB_IMUX</xtag-group-name>
+<UL>
+<LI><xtag-item1>I=22</xtag-item1></LI>
+<LI><xtag-item1>OUT=22</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="IOB_INBUF">IOB_INBUF</xtag-group-name>
+<UL>
+<LI><xtag-item1>OUT=22</xtag-item1></LI>
+<LI><xtag-item1>PAD=22</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name>
+<UL>
+<LI><xtag-item1>IN=69</xtag-item1></LI>
+<LI><xtag-item1>OUT=69</xtag-item1></LI>
+<LI><xtag-item1>TRI=16</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="LUT5">LUT5</xtag-group-name>
+<UL>
+<LI><xtag-item1>A1=46</xtag-item1></LI>
+<LI><xtag-item1>A2=77</xtag-item1></LI>
+<LI><xtag-item1>A3=67</xtag-item1></LI>
+<LI><xtag-item1>A4=56</xtag-item1></LI>
+<LI><xtag-item1>A5=77</xtag-item1></LI>
+<LI><xtag-item1>O5=226</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="LUT6">LUT6</xtag-group-name>
+<UL>
+<LI><xtag-item1>A1=419</xtag-item1></LI>
+<LI><xtag-item1>A2=613</xtag-item1></LI>
+<LI><xtag-item1>A3=712</xtag-item1></LI>
+<LI><xtag-item1>A4=796</xtag-item1></LI>
+<LI><xtag-item1>A5=854</xtag-item1></LI>
+<LI><xtag-item1>A6=892</xtag-item1></LI>
+<LI><xtag-item1>O6=893</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="LUT_OR_MEM5">LUT_OR_MEM5</xtag-group-name>
+<UL>
+<LI><xtag-item1>A1=56</xtag-item1></LI>
+<LI><xtag-item1>A2=56</xtag-item1></LI>
+<LI><xtag-item1>A3=56</xtag-item1></LI>
+<LI><xtag-item1>A4=56</xtag-item1></LI>
+<LI><xtag-item1>A5=56</xtag-item1></LI>
+<LI><xtag-item1>CLK=56</xtag-item1></LI>
+<LI><xtag-item1>DI1=56</xtag-item1></LI>
+<LI><xtag-item1>O5=56</xtag-item1></LI>
+<LI><xtag-item1>WE=56</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="LUT_OR_MEM6">LUT_OR_MEM6</xtag-group-name>
+<UL>
+<LI><xtag-item1>A1=58</xtag-item1></LI>
+<LI><xtag-item1>A2=58</xtag-item1></LI>
+<LI><xtag-item1>A3=58</xtag-item1></LI>
+<LI><xtag-item1>A4=58</xtag-item1></LI>
+<LI><xtag-item1>A5=58</xtag-item1></LI>
+<LI><xtag-item1>A6=58</xtag-item1></LI>
+<LI><xtag-item1>CLK=58</xtag-item1></LI>
+<LI><xtag-item1>DI2=58</xtag-item1></LI>
+<LI><xtag-item1>O6=58</xtag-item1></LI>
+<LI><xtag-item1>WE=58</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="OLOGIC2">OLOGIC2</xtag-group-name>
+<UL>
+<LI><xtag-item1>CLK0=27</xtag-item1></LI>
+<LI><xtag-item1>D1=27</xtag-item1></LI>
+<LI><xtag-item1>OCE=1</xtag-item1></LI>
+<LI><xtag-item1>OQ=27</xtag-item1></LI>
+<LI><xtag-item1>SR=6</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="OLOGIC2_OUTFF">OLOGIC2_OUTFF</xtag-group-name>
+<UL>
+<LI><xtag-item1>CE=1</xtag-item1></LI>
+<LI><xtag-item1>CK0=27</xtag-item1></LI>
+<LI><xtag-item1>D1=27</xtag-item1></LI>
+<LI><xtag-item1>Q=27</xtag-item1></LI>
+<LI><xtag-item1>SR=6</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="PAD">PAD</xtag-group-name>
+<UL>
+<LI><xtag-item1>PAD=75</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="PLL_ADV">PLL_ADV</xtag-group-name>
+<UL>
+<LI><xtag-item1>CLKFBIN=1</xtag-item1></LI>
+<LI><xtag-item1>CLKFBOUT=1</xtag-item1></LI>
+<LI><xtag-item1>CLKIN1=1</xtag-item1></LI>
+<LI><xtag-item1>CLKOUT0=1</xtag-item1></LI>
+<LI><xtag-item1>RST=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="PLL_ADV_PLL_ADV">PLL_ADV_PLL_ADV</xtag-group-name>
+<UL>
+<LI><xtag-item1>CLKFBIN=1</xtag-item1></LI>
+<LI><xtag-item1>CLKFBOUT=1</xtag-item1></LI>
+<LI><xtag-item1>CLKIN1=1</xtag-item1></LI>
+<LI><xtag-item1>CLKOUT0=1</xtag-item1></LI>
+<LI><xtag-item1>RST=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="PULL_OR_KEEP1">PULL_OR_KEEP1</xtag-group-name>
+<UL>
+<LI><xtag-item1>PAD=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="RAMB16BWER">RAMB16BWER</xtag-group-name>
+<UL>
+<LI><xtag-item1>ADDRA0=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA1=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA10=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA11=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA12=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA13=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA2=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA3=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA4=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA5=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA6=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA7=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA8=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA9=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB0=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB1=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB10=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB11=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB12=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB13=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB2=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB3=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB4=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB5=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB6=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB7=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB8=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB9=7</xtag-item1></LI>
+<LI><xtag-item1>CLKA=7</xtag-item1></LI>
+<LI><xtag-item1>CLKB=7</xtag-item1></LI>
+<LI><xtag-item1>DIA0=7</xtag-item1></LI>
+<LI><xtag-item1>DIA1=7</xtag-item1></LI>
+<LI><xtag-item1>DIA10=7</xtag-item1></LI>
+<LI><xtag-item1>DIA11=7</xtag-item1></LI>
+<LI><xtag-item1>DIA12=7</xtag-item1></LI>
+<LI><xtag-item1>DIA13=7</xtag-item1></LI>
+<LI><xtag-item1>DIA14=7</xtag-item1></LI>
+<LI><xtag-item1>DIA15=7</xtag-item1></LI>
+<LI><xtag-item1>DIA16=7</xtag-item1></LI>
+<LI><xtag-item1>DIA17=7</xtag-item1></LI>
+<LI><xtag-item1>DIA18=7</xtag-item1></LI>
+<LI><xtag-item1>DIA19=7</xtag-item1></LI>
+<LI><xtag-item1>DIA2=7</xtag-item1></LI>
+<LI><xtag-item1>DIA20=7</xtag-item1></LI>
+<LI><xtag-item1>DIA21=7</xtag-item1></LI>
+<LI><xtag-item1>DIA22=7</xtag-item1></LI>
+<LI><xtag-item1>DIA23=7</xtag-item1></LI>
+<LI><xtag-item1>DIA24=7</xtag-item1></LI>
+<LI><xtag-item1>DIA25=7</xtag-item1></LI>
+<LI><xtag-item1>DIA26=7</xtag-item1></LI>
+<LI><xtag-item1>DIA27=7</xtag-item1></LI>
+<LI><xtag-item1>DIA28=7</xtag-item1></LI>
+<LI><xtag-item1>DIA29=7</xtag-item1></LI>
+<LI><xtag-item1>DIA3=7</xtag-item1></LI>
+<LI><xtag-item1>DIA30=7</xtag-item1></LI>
+<LI><xtag-item1>DIA31=7</xtag-item1></LI>
+<LI><xtag-item1>DIA4=7</xtag-item1></LI>
+<LI><xtag-item1>DIA5=7</xtag-item1></LI>
+<LI><xtag-item1>DIA6=7</xtag-item1></LI>
+<LI><xtag-item1>DIA7=7</xtag-item1></LI>
+<LI><xtag-item1>DIA8=7</xtag-item1></LI>
+<LI><xtag-item1>DIA9=7</xtag-item1></LI>
+<LI><xtag-item1>DIB0=7</xtag-item1></LI>
+<LI><xtag-item1>DIB1=7</xtag-item1></LI>
+<LI><xtag-item1>DIB10=7</xtag-item1></LI>
+<LI><xtag-item1>DIB11=7</xtag-item1></LI>
+<LI><xtag-item1>DIB12=7</xtag-item1></LI>
+<LI><xtag-item1>DIB13=7</xtag-item1></LI>
+<LI><xtag-item1>DIB14=7</xtag-item1></LI>
+<LI><xtag-item1>DIB15=7</xtag-item1></LI>
+<LI><xtag-item1>DIB16=7</xtag-item1></LI>
+<LI><xtag-item1>DIB17=7</xtag-item1></LI>
+<LI><xtag-item1>DIB18=7</xtag-item1></LI>
+<LI><xtag-item1>DIB19=7</xtag-item1></LI>
+<LI><xtag-item1>DIB2=7</xtag-item1></LI>
+<LI><xtag-item1>DIB20=7</xtag-item1></LI>
+<LI><xtag-item1>DIB21=7</xtag-item1></LI>
+<LI><xtag-item1>DIB22=7</xtag-item1></LI>
+<LI><xtag-item1>DIB23=7</xtag-item1></LI>
+<LI><xtag-item1>DIB24=7</xtag-item1></LI>
+<LI><xtag-item1>DIB25=7</xtag-item1></LI>
+<LI><xtag-item1>DIB26=7</xtag-item1></LI>
+<LI><xtag-item1>DIB27=7</xtag-item1></LI>
+<LI><xtag-item1>DIB28=7</xtag-item1></LI>
+<LI><xtag-item1>DIB29=7</xtag-item1></LI>
+<LI><xtag-item1>DIB3=7</xtag-item1></LI>
+<LI><xtag-item1>DIB30=7</xtag-item1></LI>
+<LI><xtag-item1>DIB31=7</xtag-item1></LI>
+<LI><xtag-item1>DIB4=7</xtag-item1></LI>
+<LI><xtag-item1>DIB5=7</xtag-item1></LI>
+<LI><xtag-item1>DIB6=7</xtag-item1></LI>
+<LI><xtag-item1>DIB7=7</xtag-item1></LI>
+<LI><xtag-item1>DIB8=7</xtag-item1></LI>
+<LI><xtag-item1>DIB9=7</xtag-item1></LI>
+<LI><xtag-item1>DIPA0=7</xtag-item1></LI>
+<LI><xtag-item1>DIPA1=7</xtag-item1></LI>
+<LI><xtag-item1>DIPA2=7</xtag-item1></LI>
+<LI><xtag-item1>DIPA3=7</xtag-item1></LI>
+<LI><xtag-item1>DIPB0=7</xtag-item1></LI>
+<LI><xtag-item1>DIPB1=7</xtag-item1></LI>
+<LI><xtag-item1>DIPB2=7</xtag-item1></LI>
+<LI><xtag-item1>DIPB3=7</xtag-item1></LI>
+<LI><xtag-item1>DOA0=7</xtag-item1></LI>
+<LI><xtag-item1>DOA1=7</xtag-item1></LI>
+<LI><xtag-item1>DOA2=7</xtag-item1></LI>
+<LI><xtag-item1>DOA3=7</xtag-item1></LI>
+<LI><xtag-item1>DOA4=4</xtag-item1></LI>
+<LI><xtag-item1>DOA5=4</xtag-item1></LI>
+<LI><xtag-item1>DOA6=4</xtag-item1></LI>
+<LI><xtag-item1>DOA7=4</xtag-item1></LI>
+<LI><xtag-item1>DOPA0=2</xtag-item1></LI>
+<LI><xtag-item1>ENA=7</xtag-item1></LI>
+<LI><xtag-item1>ENB=7</xtag-item1></LI>
+<LI><xtag-item1>REGCEA=7</xtag-item1></LI>
+<LI><xtag-item1>REGCEB=7</xtag-item1></LI>
+<LI><xtag-item1>RSTA=7</xtag-item1></LI>
+<LI><xtag-item1>RSTB=7</xtag-item1></LI>
+<LI><xtag-item1>WEA0=7</xtag-item1></LI>
+<LI><xtag-item1>WEA1=7</xtag-item1></LI>
+<LI><xtag-item1>WEA2=7</xtag-item1></LI>
+<LI><xtag-item1>WEA3=7</xtag-item1></LI>
+<LI><xtag-item1>WEB0=7</xtag-item1></LI>
+<LI><xtag-item1>WEB1=7</xtag-item1></LI>
+<LI><xtag-item1>WEB2=7</xtag-item1></LI>
+<LI><xtag-item1>WEB3=7</xtag-item1></LI>
+</UL>
+</TD>
+<TD>
+</xtag-group>
+<xtag-group><xtag-group-name name="RAMB16BWER_RAMB16BWER">RAMB16BWER_RAMB16BWER</xtag-group-name>
+<UL>
+<LI><xtag-item1>ADDRA0=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA1=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA10=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA11=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA12=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA13=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA2=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA3=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA4=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA5=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA6=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA7=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA8=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRA9=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB0=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB1=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB10=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB11=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB12=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB13=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB2=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB3=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB4=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB5=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB6=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB7=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB8=7</xtag-item1></LI>
+<LI><xtag-item1>ADDRB9=7</xtag-item1></LI>
+<LI><xtag-item1>CLKA=7</xtag-item1></LI>
+<LI><xtag-item1>CLKB=7</xtag-item1></LI>
+<LI><xtag-item1>DIA0=7</xtag-item1></LI>
+<LI><xtag-item1>DIA1=7</xtag-item1></LI>
+<LI><xtag-item1>DIA10=7</xtag-item1></LI>
+<LI><xtag-item1>DIA11=7</xtag-item1></LI>
+<LI><xtag-item1>DIA12=7</xtag-item1></LI>
+<LI><xtag-item1>DIA13=7</xtag-item1></LI>
+<LI><xtag-item1>DIA14=7</xtag-item1></LI>
+<LI><xtag-item1>DIA15=7</xtag-item1></LI>
+<LI><xtag-item1>DIA16=7</xtag-item1></LI>
+<LI><xtag-item1>DIA17=7</xtag-item1></LI>
+<LI><xtag-item1>DIA18=7</xtag-item1></LI>
+<LI><xtag-item1>DIA19=7</xtag-item1></LI>
+<LI><xtag-item1>DIA2=7</xtag-item1></LI>
+<LI><xtag-item1>DIA20=7</xtag-item1></LI>
+<LI><xtag-item1>DIA21=7</xtag-item1></LI>
+<LI><xtag-item1>DIA22=7</xtag-item1></LI>
+<LI><xtag-item1>DIA23=7</xtag-item1></LI>
+<LI><xtag-item1>DIA24=7</xtag-item1></LI>
+<LI><xtag-item1>DIA25=7</xtag-item1></LI>
+<LI><xtag-item1>DIA26=7</xtag-item1></LI>
+<LI><xtag-item1>DIA27=7</xtag-item1></LI>
+<LI><xtag-item1>DIA28=7</xtag-item1></LI>
+<LI><xtag-item1>DIA29=7</xtag-item1></LI>
+<LI><xtag-item1>DIA3=7</xtag-item1></LI>
+<LI><xtag-item1>DIA30=7</xtag-item1></LI>
+<LI><xtag-item1>DIA31=7</xtag-item1></LI>
+<LI><xtag-item1>DIA4=7</xtag-item1></LI>
+<LI><xtag-item1>DIA5=7</xtag-item1></LI>
+<LI><xtag-item1>DIA6=7</xtag-item1></LI>
+<LI><xtag-item1>DIA7=7</xtag-item1></LI>
+<LI><xtag-item1>DIA8=7</xtag-item1></LI>
+<LI><xtag-item1>DIA9=7</xtag-item1></LI>
+<LI><xtag-item1>DIB0=7</xtag-item1></LI>
+<LI><xtag-item1>DIB1=7</xtag-item1></LI>
+<LI><xtag-item1>DIB10=7</xtag-item1></LI>
+<LI><xtag-item1>DIB11=7</xtag-item1></LI>
+<LI><xtag-item1>DIB12=7</xtag-item1></LI>
+<LI><xtag-item1>DIB13=7</xtag-item1></LI>
+<LI><xtag-item1>DIB14=7</xtag-item1></LI>
+<LI><xtag-item1>DIB15=7</xtag-item1></LI>
+<LI><xtag-item1>DIB16=7</xtag-item1></LI>
+<LI><xtag-item1>DIB17=7</xtag-item1></LI>
+<LI><xtag-item1>DIB18=7</xtag-item1></LI>
+<LI><xtag-item1>DIB19=7</xtag-item1></LI>
+<LI><xtag-item1>DIB2=7</xtag-item1></LI>
+<LI><xtag-item1>DIB20=7</xtag-item1></LI>
+<LI><xtag-item1>DIB21=7</xtag-item1></LI>
+<LI><xtag-item1>DIB22=7</xtag-item1></LI>
+<LI><xtag-item1>DIB23=7</xtag-item1></LI>
+<LI><xtag-item1>DIB24=7</xtag-item1></LI>
+<LI><xtag-item1>DIB25=7</xtag-item1></LI>
+<LI><xtag-item1>DIB26=7</xtag-item1></LI>
+<LI><xtag-item1>DIB27=7</xtag-item1></LI>
+<LI><xtag-item1>DIB28=7</xtag-item1></LI>
+<LI><xtag-item1>DIB29=7</xtag-item1></LI>
+<LI><xtag-item1>DIB3=7</xtag-item1></LI>
+<LI><xtag-item1>DIB30=7</xtag-item1></LI>
+<LI><xtag-item1>DIB31=7</xtag-item1></LI>
+<LI><xtag-item1>DIB4=7</xtag-item1></LI>
+<LI><xtag-item1>DIB5=7</xtag-item1></LI>
+<LI><xtag-item1>DIB6=7</xtag-item1></LI>
+<LI><xtag-item1>DIB7=7</xtag-item1></LI>
+<LI><xtag-item1>DIB8=7</xtag-item1></LI>
+<LI><xtag-item1>DIB9=7</xtag-item1></LI>
+<LI><xtag-item1>DIPA0=7</xtag-item1></LI>
+<LI><xtag-item1>DIPA1=7</xtag-item1></LI>
+<LI><xtag-item1>DIPA2=7</xtag-item1></LI>
+<LI><xtag-item1>DIPA3=7</xtag-item1></LI>
+<LI><xtag-item1>DIPB0=7</xtag-item1></LI>
+<LI><xtag-item1>DIPB1=7</xtag-item1></LI>
+<LI><xtag-item1>DIPB2=7</xtag-item1></LI>
+<LI><xtag-item1>DIPB3=7</xtag-item1></LI>
+<LI><xtag-item1>DOA0=7</xtag-item1></LI>
+<LI><xtag-item1>DOA1=7</xtag-item1></LI>
+<LI><xtag-item1>DOA2=7</xtag-item1></LI>
+<LI><xtag-item1>DOA3=7</xtag-item1></LI>
+<LI><xtag-item1>DOA4=4</xtag-item1></LI>
+<LI><xtag-item1>DOA5=4</xtag-item1></LI>
+<LI><xtag-item1>DOA6=4</xtag-item1></LI>
+<LI><xtag-item1>DOA7=4</xtag-item1></LI>
+<LI><xtag-item1>DOPA0=2</xtag-item1></LI>
+<LI><xtag-item1>ENA=7</xtag-item1></LI>
+<LI><xtag-item1>ENB=7</xtag-item1></LI>
+<LI><xtag-item1>REGCEA=7</xtag-item1></LI>
+<LI><xtag-item1>REGCEB=7</xtag-item1></LI>
+<LI><xtag-item1>RSTA=7</xtag-item1></LI>
+<LI><xtag-item1>RSTB=7</xtag-item1></LI>
+<LI><xtag-item1>WEA0=7</xtag-item1></LI>
+<LI><xtag-item1>WEA1=7</xtag-item1></LI>
+<LI><xtag-item1>WEA2=7</xtag-item1></LI>
+<LI><xtag-item1>WEA3=7</xtag-item1></LI>
+<LI><xtag-item1>WEB0=7</xtag-item1></LI>
+<LI><xtag-item1>WEB1=7</xtag-item1></LI>
+<LI><xtag-item1>WEB2=7</xtag-item1></LI>
+<LI><xtag-item1>WEB3=7</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="RAMB8BWER">RAMB8BWER</xtag-group-name>
+<UL>
+<LI><xtag-item1>ADDRAWRADDR0=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR1=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR10=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR11=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR12=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR2=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR3=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR4=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR5=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR6=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR7=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR8=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR9=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR0=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR1=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR10=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR11=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR12=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR2=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR3=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR4=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR5=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR6=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR7=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR8=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR9=1</xtag-item1></LI>
+<LI><xtag-item1>CLKAWRCLK=1</xtag-item1></LI>
+<LI><xtag-item1>CLKBRDCLK=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI0=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI1=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI10=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI11=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI12=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI13=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI14=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI15=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI2=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI3=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI4=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI5=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI6=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI7=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI8=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI9=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI0=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI1=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI10=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI11=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI12=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI13=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI14=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI15=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI2=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI3=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI4=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI5=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI6=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI7=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI8=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI9=1</xtag-item1></LI>
+<LI><xtag-item1>DIPADIP0=1</xtag-item1></LI>
+<LI><xtag-item1>DIPADIP1=1</xtag-item1></LI>
+<LI><xtag-item1>DIPBDIP0=1</xtag-item1></LI>
+<LI><xtag-item1>DIPBDIP1=1</xtag-item1></LI>
+<LI><xtag-item1>DOADO0=1</xtag-item1></LI>
+<LI><xtag-item1>DOADO1=1</xtag-item1></LI>
+<LI><xtag-item1>ENAWREN=1</xtag-item1></LI>
+<LI><xtag-item1>ENBRDEN=1</xtag-item1></LI>
+<LI><xtag-item1>REGCEA=1</xtag-item1></LI>
+<LI><xtag-item1>REGCEBREGCE=1</xtag-item1></LI>
+<LI><xtag-item1>RSTA=1</xtag-item1></LI>
+<LI><xtag-item1>RSTBRST=1</xtag-item1></LI>
+<LI><xtag-item1>WEAWEL0=1</xtag-item1></LI>
+<LI><xtag-item1>WEAWEL1=1</xtag-item1></LI>
+<LI><xtag-item1>WEBWEU0=1</xtag-item1></LI>
+<LI><xtag-item1>WEBWEU1=1</xtag-item1></LI>
+</UL>
+</TD>
+<TD>
+</xtag-group>
+<xtag-group><xtag-group-name name="RAMB8BWER_RAMB8BWER">RAMB8BWER_RAMB8BWER</xtag-group-name>
+<UL>
+<LI><xtag-item1>ADDRAWRADDR0=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR1=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR10=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR11=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR12=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR2=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR3=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR4=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR5=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR6=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR7=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR8=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRAWRADDR9=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR0=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR1=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR10=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR11=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR12=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR2=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR3=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR4=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR5=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR6=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR7=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR8=1</xtag-item1></LI>
+<LI><xtag-item1>ADDRBRDADDR9=1</xtag-item1></LI>
+<LI><xtag-item1>CLKAWRCLK=1</xtag-item1></LI>
+<LI><xtag-item1>CLKBRDCLK=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI0=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI1=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI10=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI11=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI12=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI13=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI14=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI15=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI2=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI3=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI4=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI5=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI6=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI7=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI8=1</xtag-item1></LI>
+<LI><xtag-item1>DIADI9=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI0=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI1=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI10=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI11=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI12=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI13=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI14=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI15=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI2=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI3=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI4=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI5=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI6=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI7=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI8=1</xtag-item1></LI>
+<LI><xtag-item1>DIBDI9=1</xtag-item1></LI>
+<LI><xtag-item1>DIPADIP0=1</xtag-item1></LI>
+<LI><xtag-item1>DIPADIP1=1</xtag-item1></LI>
+<LI><xtag-item1>DIPBDIP0=1</xtag-item1></LI>
+<LI><xtag-item1>DIPBDIP1=1</xtag-item1></LI>
+<LI><xtag-item1>DOADO0=1</xtag-item1></LI>
+<LI><xtag-item1>DOADO1=1</xtag-item1></LI>
+<LI><xtag-item1>ENAWREN=1</xtag-item1></LI>
+<LI><xtag-item1>ENBRDEN=1</xtag-item1></LI>
+<LI><xtag-item1>REGCEA=1</xtag-item1></LI>
+<LI><xtag-item1>REGCEBREGCE=1</xtag-item1></LI>
+<LI><xtag-item1>RSTA=1</xtag-item1></LI>
+<LI><xtag-item1>RSTBRST=1</xtag-item1></LI>
+<LI><xtag-item1>WEAWEL0=1</xtag-item1></LI>
+<LI><xtag-item1>WEAWEL1=1</xtag-item1></LI>
+<LI><xtag-item1>WEBWEU0=1</xtag-item1></LI>
+<LI><xtag-item1>WEBWEU1=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
+<UL>
+<LI><xtag-item1>CE=619</xtag-item1></LI>
+<LI><xtag-item1>CK=757</xtag-item1></LI>
+<LI><xtag-item1>D=757</xtag-item1></LI>
+<LI><xtag-item1>Q=757</xtag-item1></LI>
+<LI><xtag-item1>SR=604</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SELMUX2_1">SELMUX2_1</xtag-group-name>
+<UL>
+<LI><xtag-item1>0=96</xtag-item1></LI>
+<LI><xtag-item1>1=84</xtag-item1></LI>
+<LI><xtag-item1>OUT=96</xtag-item1></LI>
+<LI><xtag-item1>S0=96</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
+<UL>
+<LI><xtag-item1>A=3</xtag-item1></LI>
+<LI><xtag-item1>A1=15</xtag-item1></LI>
+<LI><xtag-item1>A2=32</xtag-item1></LI>
+<LI><xtag-item1>A3=44</xtag-item1></LI>
+<LI><xtag-item1>A4=57</xtag-item1></LI>
+<LI><xtag-item1>A5=71</xtag-item1></LI>
+<LI><xtag-item1>A6=78</xtag-item1></LI>
+<LI><xtag-item1>AMUX=25</xtag-item1></LI>
+<LI><xtag-item1>AQ=33</xtag-item1></LI>
+<LI><xtag-item1>AX=47</xtag-item1></LI>
+<LI><xtag-item1>B=1</xtag-item1></LI>
+<LI><xtag-item1>B1=26</xtag-item1></LI>
+<LI><xtag-item1>B2=29</xtag-item1></LI>
+<LI><xtag-item1>B3=39</xtag-item1></LI>
+<LI><xtag-item1>B4=53</xtag-item1></LI>
+<LI><xtag-item1>B5=66</xtag-item1></LI>
+<LI><xtag-item1>B6=72</xtag-item1></LI>
+<LI><xtag-item1>BMUX=48</xtag-item1></LI>
+<LI><xtag-item1>BQ=31</xtag-item1></LI>
+<LI><xtag-item1>BX=43</xtag-item1></LI>
+<LI><xtag-item1>C1=27</xtag-item1></LI>
+<LI><xtag-item1>C2=36</xtag-item1></LI>
+<LI><xtag-item1>C3=47</xtag-item1></LI>
+<LI><xtag-item1>C4=58</xtag-item1></LI>
+<LI><xtag-item1>C5=74</xtag-item1></LI>
+<LI><xtag-item1>C6=79</xtag-item1></LI>
+<LI><xtag-item1>CE=48</xtag-item1></LI>
+<LI><xtag-item1>CIN=38</xtag-item1></LI>
+<LI><xtag-item1>CLK=54</xtag-item1></LI>
+<LI><xtag-item1>CMUX=32</xtag-item1></LI>
+<LI><xtag-item1>COUT=38</xtag-item1></LI>
+<LI><xtag-item1>CQ=25</xtag-item1></LI>
+<LI><xtag-item1>CX=47</xtag-item1></LI>
+<LI><xtag-item1>D=1</xtag-item1></LI>
+<LI><xtag-item1>D1=35</xtag-item1></LI>
+<LI><xtag-item1>D2=39</xtag-item1></LI>
+<LI><xtag-item1>D3=47</xtag-item1></LI>
+<LI><xtag-item1>D4=60</xtag-item1></LI>
+<LI><xtag-item1>D5=71</xtag-item1></LI>
+<LI><xtag-item1>D6=80</xtag-item1></LI>
+<LI><xtag-item1>DMUX=23</xtag-item1></LI>
+<LI><xtag-item1>DQ=47</xtag-item1></LI>
+<LI><xtag-item1>DX=35</xtag-item1></LI>
+<LI><xtag-item1>SR=48</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name>
+<UL>
+<LI><xtag-item1>A1=14</xtag-item1></LI>
+<LI><xtag-item1>A2=14</xtag-item1></LI>
+<LI><xtag-item1>A3=14</xtag-item1></LI>
+<LI><xtag-item1>A4=14</xtag-item1></LI>
+<LI><xtag-item1>A5=14</xtag-item1></LI>
+<LI><xtag-item1>A6=14</xtag-item1></LI>
+<LI><xtag-item1>AI=14</xtag-item1></LI>
+<LI><xtag-item1>AMUX=14</xtag-item1></LI>
+<LI><xtag-item1>AQ=14</xtag-item1></LI>
+<LI><xtag-item1>AX=14</xtag-item1></LI>
+<LI><xtag-item1>B1=14</xtag-item1></LI>
+<LI><xtag-item1>B2=14</xtag-item1></LI>
+<LI><xtag-item1>B3=14</xtag-item1></LI>
+<LI><xtag-item1>B4=14</xtag-item1></LI>
+<LI><xtag-item1>B5=14</xtag-item1></LI>
+<LI><xtag-item1>B6=14</xtag-item1></LI>
+<LI><xtag-item1>BI=14</xtag-item1></LI>
+<LI><xtag-item1>BMUX=14</xtag-item1></LI>
+<LI><xtag-item1>BQ=14</xtag-item1></LI>
+<LI><xtag-item1>BX=14</xtag-item1></LI>
+<LI><xtag-item1>C1=15</xtag-item1></LI>
+<LI><xtag-item1>C2=15</xtag-item1></LI>
+<LI><xtag-item1>C3=15</xtag-item1></LI>
+<LI><xtag-item1>C4=15</xtag-item1></LI>
+<LI><xtag-item1>C5=15</xtag-item1></LI>
+<LI><xtag-item1>C6=15</xtag-item1></LI>
+<LI><xtag-item1>CE=15</xtag-item1></LI>
+<LI><xtag-item1>CI=15</xtag-item1></LI>
+<LI><xtag-item1>CLK=15</xtag-item1></LI>
+<LI><xtag-item1>CMUX=14</xtag-item1></LI>
+<LI><xtag-item1>CQ=15</xtag-item1></LI>
+<LI><xtag-item1>CX=14</xtag-item1></LI>
+<LI><xtag-item1>D1=15</xtag-item1></LI>
+<LI><xtag-item1>D2=15</xtag-item1></LI>
+<LI><xtag-item1>D3=15</xtag-item1></LI>
+<LI><xtag-item1>D4=15</xtag-item1></LI>
+<LI><xtag-item1>D5=15</xtag-item1></LI>
+<LI><xtag-item1>D6=15</xtag-item1></LI>
+<LI><xtag-item1>DI=15</xtag-item1></LI>
+<LI><xtag-item1>DMUX=14</xtag-item1></LI>
+<LI><xtag-item1>DQ=15</xtag-item1></LI>
+<LI><xtag-item1>DX=14</xtag-item1></LI>
+</UL>
+</TD>
+<TD>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
+<UL>
+<LI><xtag-item1>A=117</xtag-item1></LI>
+<LI><xtag-item1>A1=100</xtag-item1></LI>
+<LI><xtag-item1>A2=148</xtag-item1></LI>
+<LI><xtag-item1>A3=160</xtag-item1></LI>
+<LI><xtag-item1>A4=167</xtag-item1></LI>
+<LI><xtag-item1>A5=169</xtag-item1></LI>
+<LI><xtag-item1>A6=172</xtag-item1></LI>
+<LI><xtag-item1>AMUX=25</xtag-item1></LI>
+<LI><xtag-item1>AQ=164</xtag-item1></LI>
+<LI><xtag-item1>AX=106</xtag-item1></LI>
+<LI><xtag-item1>B=91</xtag-item1></LI>
+<LI><xtag-item1>B1=85</xtag-item1></LI>
+<LI><xtag-item1>B2=126</xtag-item1></LI>
+<LI><xtag-item1>B3=133</xtag-item1></LI>
+<LI><xtag-item1>B4=135</xtag-item1></LI>
+<LI><xtag-item1>B5=139</xtag-item1></LI>
+<LI><xtag-item1>B6=137</xtag-item1></LI>
+<LI><xtag-item1>BMUX=22</xtag-item1></LI>
+<LI><xtag-item1>BQ=141</xtag-item1></LI>
+<LI><xtag-item1>BX=93</xtag-item1></LI>
+<LI><xtag-item1>C=93</xtag-item1></LI>
+<LI><xtag-item1>C1=90</xtag-item1></LI>
+<LI><xtag-item1>C2=126</xtag-item1></LI>
+<LI><xtag-item1>C3=135</xtag-item1></LI>
+<LI><xtag-item1>C4=138</xtag-item1></LI>
+<LI><xtag-item1>C5=140</xtag-item1></LI>
+<LI><xtag-item1>C6=139</xtag-item1></LI>
+<LI><xtag-item1>CE=147</xtag-item1></LI>
+<LI><xtag-item1>CLK=205</xtag-item1></LI>
+<LI><xtag-item1>CMUX=23</xtag-item1></LI>
+<LI><xtag-item1>CQ=140</xtag-item1></LI>
+<LI><xtag-item1>CX=90</xtag-item1></LI>
+<LI><xtag-item1>D=100</xtag-item1></LI>
+<LI><xtag-item1>D1=69</xtag-item1></LI>
+<LI><xtag-item1>D2=111</xtag-item1></LI>
+<LI><xtag-item1>D3=120</xtag-item1></LI>
+<LI><xtag-item1>D4=128</xtag-item1></LI>
+<LI><xtag-item1>D5=132</xtag-item1></LI>
+<LI><xtag-item1>D6=135</xtag-item1></LI>
+<LI><xtag-item1>DMUX=22</xtag-item1></LI>
+<LI><xtag-item1>DQ=118</xtag-item1></LI>
+<LI><xtag-item1>DX=81</xtag-item1></LI>
+<LI><xtag-item1>SR=178</xtag-item1></LI>
+</UL>
+</xtag-group>
+</TD>
+</xtag-section>
+</TR></TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD><B>Tool Usage</B></TD></TR>
+<TR VALIGN=TOP><TD ALIGN=LEFT>Command Line History<xtag-section name="CommandLineLog"><UL>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -sd &lt;dname&gt; -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -xe n -t 2 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+</xtag-section></UL></TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR><TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Program Name</B></TD><TD><B>Runs Started</B></TD><TD><B>Runs Finished</B></TD><TD><B>Errors</B></TD><TD><B>Fatal Errors</B></TD><TD><B>Internal Errors</B></TD><TD><B>Exceptions</B></TD><TD><B>Core Dumps</B></TD></TR>
+
+<tr>
+  <td><xtag-program-name>XSLTProcess</xtag-program-name></td>
+  <td><xtag-total-run-started>179</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>179</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>_impact</xtag-program-name></td>
+  <td><xtag-total-run-started>31</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>25</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>bitgen</xtag-program-name></td>
+  <td><xtag-total-run-started>124</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>124</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>cpldfit</xtag-program-name></td>
+  <td><xtag-total-run-started>180</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>178</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>hprep6</xtag-program-name></td>
+  <td><xtag-total-run-started>150</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>150</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>map</xtag-program-name></td>
+  <td><xtag-total-run-started>192</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>169</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>ngc2edif</xtag-program-name></td>
+  <td><xtag-total-run-started>12</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>12</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>ngcbuild</xtag-program-name></td>
+  <td><xtag-total-run-started>18</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>18</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>ngdbuild</xtag-program-name></td>
+  <td><xtag-total-run-started>384</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>384</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>par</xtag-program-name></td>
+  <td><xtag-total-run-started>170</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>169</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>taengine</xtag-program-name></td>
+  <td><xtag-total-run-started>5</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>5</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>trce</xtag-program-name></td>
+  <td><xtag-total-run-started>166</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>166</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>tsim</xtag-program-name></td>
+  <td><xtag-total-run-started>150</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>150</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>xst</xtag-program-name></td>
+  <td><xtag-total-run-started>404</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>403</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+</xtag-section></TABLE>
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<xtag-section name="Project Statistics">
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=2><B>Project Statistics</B></TD></TR>
+<TR>
+<TD><xtag-process-property-name>PROPEXT_xilxMapPackRegInto_spartan6</xtag-process-property-name>=<xtag-process-property-value>For Inputs and Outputs</xtag-process-property-value></TD>
+<TD><xtag-design-property-name>PROP_Enable_Message_Filtering</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-process-property-name>PROP_FitterReportFormat</xtag-process-property-name>=<xtag-process-property-value>HTML</xtag-process-property-value></TD>
+<TD><xtag-design-property-name>PROP_LastAppliedGoal</xtag-design-property-name>=<xtag-design-property-value>Balanced</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-design-property-name>PROP_LastAppliedStrategy</xtag-design-property-name>=<xtag-design-property-value>Xilinx Default (unlocked)</xtag-design-property-value></TD>
+<TD><xtag-design-property-name>PROP_ManualCompileOrderImp</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-process-property-name>PROP_MapPlacerCostTable_spartan6</xtag-process-property-name>=<xtag-process-property-value>2</xtag-process-property-value></TD>
+<TD><xtag-design-property-name>PROP_PropSpecInProjFile</xtag-design-property-name>=<xtag-design-property-value>Store all values</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-design-property-name>PROP_Simulator</xtag-design-property-name>=<xtag-design-property-value>ISim (VHDL/Verilog)</xtag-design-property-value></TD>
+<TD><xtag-process-property-name>PROP_SynthTopFile</xtag-process-property-name>=<xtag-process-property-value>changed</xtag-process-property-value></TD>
+
+</TR><TR><TD><xtag-design-property-name>PROP_Top_Level_Module_Type</xtag-design-property-name>=<xtag-design-property-value>HDL</xtag-design-property-value></TD>
+<TD><xtag-design-property-name>PROP_UseSmartGuide</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-process-property-name>PROP_UserConstraintEditorPreference</xtag-process-property-name>=<xtag-process-property-value>Text Editor</xtag-process-property-value></TD>
+<TD><xtag-process-property-name>PROP_bitgen_otherCmdLineOptions_spartan6</xtag-process-property-name>=<xtag-process-property-value>-g INIT_9K:Yes</xtag-process-property-value></TD>
+
+</TR><TR><TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2020-09-12T20:32:34</xtag-design-property-value></TD>
+<TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>0F0A51A7D06B470287A989EDCA362445</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>114</xtag-process-property-value></TD>
+<TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD>
+<TD><xtag-process-property-name>PROP_xilxBitgCfg_Rate_spartan6</xtag-process-property-name>=<xtag-process-property-value>10</xtag-process-property-value></TD>
+
+</TR><TR><TD><xtag-process-property-name>PROP_xilxBitgStart_IntDone</xtag-process-property-name>=<xtag-process-property-value>true</xtag-process-property-value></TD>
+<TD><xtag-design-property-name>PROP_AutoTop</xtag-design-property-name>=<xtag-design-property-value>true</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-design-property-name>PROP_DevFamily</xtag-design-property-name>=<xtag-design-property-value>Spartan6</xtag-design-property-value></TD>
+<TD><xtag-process-property-name>PROP_MapExtraEffort_spartan6</xtag-process-property-name>=<xtag-process-property-value>Normal</xtag-process-property-value></TD>
+
+</TR><TR><TD><xtag-process-property-name>PROP_MapRegDuplication_spartan6</xtag-process-property-name>=<xtag-process-property-value>On</xtag-process-property-value></TD>
+<TD><xtag-process-property-name>PROPEXT_xilxPARextraEffortLevel_spartan6</xtag-process-property-name>=<xtag-process-property-value>Normal</xtag-process-property-value></TD>
+
+</TR><TR><TD><xtag-design-property-name>PROP_DevDevice</xtag-design-property-name>=<xtag-design-property-value>xc6slx9</xtag-design-property-value></TD>
+<TD><xtag-design-property-name>PROP_DevFamilyPMName</xtag-design-property-name>=<xtag-design-property-value>spartan6</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-design-property-name>PROP_DevPackage</xtag-design-property-name>=<xtag-design-property-value>tqg144</xtag-design-property-value></TD>
+<TD><xtag-design-property-name>PROP_Synthesis_Tool</xtag-design-property-name>=<xtag-design-property-value>XST (VHDL/Verilog)</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-design-property-name>PROP_DevSpeed</xtag-design-property-name>=<xtag-design-property-value>-3</xtag-design-property-value></TD>
+<TD><xtag-design-property-name>PROP_PreferredLanguage</xtag-design-property-name>=<xtag-design-property-value>Verilog</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-source-property-name>FILE_COREGEN</xtag-source-property-name>=<xtag-source-property-value>2</xtag-source-property-value></TD>
+<TD><xtag-source-property-name>FILE_UCF</xtag-source-property-name>=<xtag-source-property-value>1</xtag-source-property-value></TD>
+
+</TR><TR><TD><xtag-source-property-name>FILE_VERILOG</xtag-source-property-name>=<xtag-source-property-value>3</xtag-source-property-value></TD>
+</TR></xtag-section></TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<xtag-section name="CoregenStatistics">
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Core Statistics</B></TD></TR>
+<TR ALIGN=CENTER><TD COLSPAN=4><B>Core Type=<xtag-core-type-name>blk_mem_gen_v7_3</xtag-core-type-name></B></TD></TR>
+<TR>
+<TD><xtag-core-param-name>c_addra_width</xtag-core-param-name>=<xtag-core-param-value>12</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_addrb_width</xtag-core-param-name>=<xtag-core-param-value>12</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_algorithm</xtag-core-param-name>=<xtag-core-param-value>1</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_axi_id_width</xtag-core-param-name>=<xtag-core-param-value>4</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>c_axi_slave_type</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_axi_type</xtag-core-param-name>=<xtag-core-param-value>1</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_byte_size</xtag-core-param-name>=<xtag-core-param-value>9</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_common_clk</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>c_default_data</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_disable_warn_bhv_coll</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_disable_warn_bhv_range</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_elaboration_dir</xtag-core-param-name>=<xtag-core-param-value>masked_value</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>c_enable_32bit_address</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_family</xtag-core-param-name>=<xtag-core-param-value>spartan6</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_has_axi_id</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_has_ena</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>c_has_enb</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_has_injecterr</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_has_mem_output_regs_a</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_has_mem_output_regs_b</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>c_has_mux_output_regs_a</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_has_mux_output_regs_b</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_has_regcea</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_has_regceb</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>c_has_rsta</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_has_rstb</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_has_softecc_input_regs_a</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_has_softecc_output_regs_b</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>c_init_file</xtag-core-param-name>=<xtag-core-param-value>BlankString</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_init_file_name</xtag-core-param-name>=<xtag-core-param-value>fname.mif</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_inita_val</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_initb_val</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>c_interface_type</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_load_init_file</xtag-core-param-name>=<xtag-core-param-value>1</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_mem_type</xtag-core-param-name>=<xtag-core-param-value>3</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_mux_pipeline_stages</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>c_prim_type</xtag-core-param-name>=<xtag-core-param-value>1</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_read_depth_a</xtag-core-param-name>=<xtag-core-param-value>4096</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_read_depth_b</xtag-core-param-name>=<xtag-core-param-value>4096</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_read_width_a</xtag-core-param-name>=<xtag-core-param-value>32</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>c_read_width_b</xtag-core-param-name>=<xtag-core-param-value>32</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_rst_priority_a</xtag-core-param-name>=<xtag-core-param-value>CE</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_rst_priority_b</xtag-core-param-name>=<xtag-core-param-value>CE</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_rst_type</xtag-core-param-name>=<xtag-core-param-value>SYNC</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>c_rstram_a</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_rstram_b</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_sim_collision_check</xtag-core-param-name>=<xtag-core-param-value>ALL</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_use_bram_block</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>c_use_byte_wea</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_use_byte_web</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_use_default_data</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_use_ecc</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>c_use_softecc</xtag-core-param-name>=<xtag-core-param-value>0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_wea_width</xtag-core-param-name>=<xtag-core-param-value>1</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_web_width</xtag-core-param-name>=<xtag-core-param-value>1</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_write_depth_a</xtag-core-param-name>=<xtag-core-param-value>4096</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>c_write_depth_b</xtag-core-param-name>=<xtag-core-param-value>4096</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_write_mode_a</xtag-core-param-name>=<xtag-core-param-value>WRITE_FIRST</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_write_mode_b</xtag-core-param-name>=<xtag-core-param-value>WRITE_FIRST</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_write_width_a</xtag-core-param-name>=<xtag-core-param-value>32</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>c_write_width_b</xtag-core-param-name>=<xtag-core-param-value>32</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>c_xdevicefamily</xtag-core-param-name>=<xtag-core-param-value>spartan6</xtag-core-param-value></TD>
+<TR ALIGN=CENTER><TD COLSPAN=4><B>Core Type=<xtag-core-type-name>clk_wiz_v3_6</xtag-core-type-name></B></TD></TR>
+<TR>
+<TD><xtag-core-param-name>clkin1_period</xtag-core-param-name>=<xtag-core-param-value>20.0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>clkin2_period</xtag-core-param-name>=<xtag-core-param-value>20.0</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>clock_mgr_type</xtag-core-param-name>=<xtag-core-param-value>AUTO</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>feedback_source</xtag-core-param-name>=<xtag-core-param-value>FDBK_AUTO</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>feedback_type</xtag-core-param-name>=<xtag-core-param-value>SINGLE</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>manual_override</xtag-core-param-name>=<xtag-core-param-value>false</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>num_out_clk</xtag-core-param-name>=<xtag-core-param-value>1</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>primtype_sel</xtag-core-param-name>=<xtag-core-param-value>DCM_SP</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>use_clk_valid</xtag-core-param-name>=<xtag-core-param-value>false</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>use_dyn_phase_shift</xtag-core-param-name>=<xtag-core-param-value>false</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>use_dyn_reconfig</xtag-core-param-name>=<xtag-core-param-value>false</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>use_freeze</xtag-core-param-name>=<xtag-core-param-value>false</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>use_inclk_stopped</xtag-core-param-name>=<xtag-core-param-value>false</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>use_inclk_switchover</xtag-core-param-name>=<xtag-core-param-value>false</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>use_locked</xtag-core-param-name>=<xtag-core-param-value>false</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>use_max_i_jitter</xtag-core-param-name>=<xtag-core-param-value>false</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>use_min_o_jitter</xtag-core-param-name>=<xtag-core-param-value>false</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>use_phase_alignment</xtag-core-param-name>=<xtag-core-param-value>false</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>use_power_down</xtag-core-param-name>=<xtag-core-param-value>false</xtag-core-param-value></TD>
+<TD><xtag-core-param-name>use_reset</xtag-core-param-name>=<xtag-core-param-value>false</xtag-core-param-value></TD>
+
+</TR><TR><TD><xtag-core-param-name>use_status</xtag-core-param-name>=<xtag-core-param-value>false</xtag-core-param-value></TD>
+</TR></xtag-section></TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<xtag-section name="UnisimStatistics">
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Unisim Statistics</B></TD></TR>
+<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>XST_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
+<TD><xtag-xstunisim-param-name>XST_NUM_BUFG</xtag-xstunisim-param-name>=<xtag-xstunisim-param-value>1</xtag-xstunisim-param-value></TD>
+<TD><xtag-xstunisim-param-name>XST_NUM_IBUFG</xtag-xstunisim-param-name>=<xtag-xstunisim-param-value>1</xtag-xstunisim-param-value></TD>
+<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_PRE_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFG</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_DCM_SP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>48</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>183</xtag-preunisim-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDR</xtag-preunisim-param-name>=<xtag-preunisim-param-value>125</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDRE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>503</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>13</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDSE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>20</xtag-preunisim-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_GND</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>5</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUFG</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_INV</xtag-preunisim-param-name>=<xtag-preunisim-param-value>15</xtag-preunisim-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IOBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>16</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>60</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT2</xtag-preunisim-param-name>=<xtag-preunisim-param-value>87</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>116</xtag-preunisim-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>73</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>223</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>384</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>175</xtag-preunisim-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-preunisim-param-name>=<xtag-preunisim-param-value>59</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXF8</xtag-preunisim-param-name>=<xtag-preunisim-param-value>25</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>53</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_RAMB16BWER</xtag-preunisim-param-name>=<xtag-preunisim-param-value>7</xtag-preunisim-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_RAMB8BWER</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_SRLC16E</xtag-preunisim-param-name>=<xtag-preunisim-param-value>114</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_VCC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>186</xtag-preunisim-param-value></TD>
+</TR>
+<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_POST_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_DCM_SP</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>48</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>183</xtag-postunisim-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDR</xtag-postunisim-param-name>=<xtag-postunisim-param-value>125</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDRE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>503</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>13</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDSE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>20</xtag-postunisim-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_GND</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>21</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_INV</xtag-postunisim-param-name>=<xtag-postunisim-param-value>15</xtag-postunisim-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>60</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT2</xtag-postunisim-param-name>=<xtag-postunisim-param-value>87</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>116</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>73</xtag-postunisim-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>223</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>384</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>175</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-postunisim-param-name>=<xtag-postunisim-param-value>59</xtag-postunisim-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXF8</xtag-postunisim-param-name>=<xtag-postunisim-param-value>25</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>53</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-postunisim-param-name>=<xtag-postunisim-param-value>16</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_PULLDOWN</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_RAMB16BWER</xtag-postunisim-param-name>=<xtag-postunisim-param-value>7</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_RAMB8BWER</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_SRLC16E</xtag-postunisim-param-name>=<xtag-postunisim-param-value>114</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_TS_TIMESPEC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_VCC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>186</xtag-postunisim-param-value></TD>
+</xtag-section></TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<xtag-section name="XstCommandLineOptions">
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>XST Command Line Options</B></TD></TR>
+<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-xstoption-type-name>XST_OPTION_SUMMARY</xtag-xstoption-type-name></B></TD></TR><TR>
+<TD><xtag-xstoptions-param-name>-ifn</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>&lt;fname&gt;.prj</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-ofn</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>&lt;design_top&gt;</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-ofmt</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NGC</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-p</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>xc6slx9-3-tqg144</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-top</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>&lt;design_top&gt;</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-opt_mode</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Speed</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-opt_level</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>1</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-power</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NO</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-iuc</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NO</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-keep_hierarchy</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>No</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-netlist_hierarchy</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>As_Optimized</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-rtlview</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Yes</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-glob_opt</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>AllClockNets</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-read_cores</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>YES</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-sd</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>&lt;No customer specific name&gt;</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-write_timing_constraints</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NO</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-cross_clock_analysis</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NO</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-bus_delimiter</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value><></xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-slice_utilization_ratio</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>100</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-bram_utilization_ratio</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>100</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-dsp_utilization_ratio</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>100</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-reduce_control_sets</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-fsm_extract</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>YES</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-fsm_encoding</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-safe_implementation</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>No</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-fsm_style</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>LUT</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-ram_extract</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Yes</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-ram_style</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-rom_extract</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Yes</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-shreg_extract</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>YES</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-rom_style</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-auto_bram_packing</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NO</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-resource_sharing</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>YES</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-async_to_sync</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NO</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-use_dsp48</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-iobuf</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>YES</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-max_fanout</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>100000</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-bufg</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>16</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-register_duplication</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>YES</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-register_balancing</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>No</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-optimize_primitives</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NO</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-use_clock_enable</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-use_sync_set</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-use_sync_reset</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-iob</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-equivalent_register_removal</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>YES</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-slice_utilization_ratio_maxmargin</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>5</xtag-xstoptions-param-value></TD>
+</xtag-section></TABLE>
+&nbsp;<BR></BODY></HTML>
diff --git a/MCL86jr/FPGA/MCL86jr/webtalk.log b/MCL86jr/FPGA/MCL86jr/webtalk.log
new file mode 100644
index 0000000..fe6b3d0
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/webtalk.log
@@ -0,0 +1,16 @@
+Release 14.7 - WebTalk (P.20131013)
+Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
+
+Project Information
+--------------------
+ProjectID=0F0A51A7D06B470287A989EDCA362445
+ProjectIteration=114
+
+WebTalk Summary
+----------------
+INFO:WebTalk:1 - WebTalk is enabled because you are using a WebPACK license.
+
+INFO:WebTalk:8 - WebTalk Install setting is ON.
+INFO:WebTalk:6 - WebTalk User setting is ON.
+
+INFO:WebTalk:5 - C:/MCL/MCL86/MCL86jr/MCL86jr/usage_statistics_webtalk.html WebTalk report has not been sent to Xilinx.  Please check your network and proxy settings.  For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/14.7/ISE_DS/ISE/data/reports/webtalk_introduction.html
diff --git a/MCL86jr/FPGA/MCL86jr/webtalk_pn.xml b/MCL86jr/FPGA/MCL86jr/webtalk_pn.xml
new file mode 100644
index 0000000..5d215f2
--- /dev/null
+++ b/MCL86jr/FPGA/MCL86jr/webtalk_pn.xml
@@ -0,0 +1,51 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pn" timeStamp="Wed Nov 11 19:10:58 2020">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="0F0A51A7D06B470287A989EDCA362445" type="project"/>
+<property name="ProjectIteration" value="114" type="project"/>
+<property name="ProjectFile" value="C:/MCL/MCL86/MCL86jr/MCL86jr/MCL86jr.xise" type="project"/>
+<property name="ProjectCreationTimestamp" value="2020-09-12T20:32:34" type="project"/>
+</section>
+<section name="Project Statistics" visible="true">
+<property name="PROPEXT_xilxMapPackRegInto_spartan6" value="For Inputs and Outputs" type="process"/>
+<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
+<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
+<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
+<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
+<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
+<property name="PROP_MapPlacerCostTable_spartan6" value="2" type="process"/>
+<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
+<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
+<property name="PROP_SynthTopFile" value="changed" type="process"/>
+<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
+<property name="PROP_UseSmartGuide" value="false" type="design"/>
+<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
+<property name="PROP_bitgen_otherCmdLineOptions_spartan6" value="-g INIT_9K:Yes" type="process"/>
+<property name="PROP_intProjectCreationTimestamp" value="2020-09-12T20:32:34" type="design"/>
+<property name="PROP_intWbtProjectID" value="0F0A51A7D06B470287A989EDCA362445" type="design"/>
+<property name="PROP_intWbtProjectIteration" value="114" type="process"/>
+<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
+<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
+<property name="PROP_xilxBitgCfg_Rate_spartan6" value="10" type="process"/>
+<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
+<property name="PROP_AutoTop" value="true" type="design"/>
+<property name="PROP_DevFamily" value="Spartan6" type="design"/>
+<property name="PROP_MapExtraEffort_spartan6" value="Normal" type="process"/>
+<property name="PROP_MapRegDuplication_spartan6" value="On" type="process"/>
+<property name="PROPEXT_xilxPARextraEffortLevel_spartan6" value="Normal" type="process"/>
+<property name="PROP_DevDevice" value="xc6slx9" type="design"/>
+<property name="PROP_DevFamilyPMName" value="spartan6" type="design"/>
+<property name="PROP_DevPackage" value="tqg144" type="design"/>
+<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
+<property name="PROP_DevSpeed" value="-3" type="design"/>
+<property name="PROP_PreferredLanguage" value="Verilog" type="design"/>
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+</section>
+</application>
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diff --git a/MCL86jr/FPGA/MCL86jr/xst/work/work.sdbx b/MCL86jr/FPGA/MCL86jr/xst/work/work.sdbx
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index 0000000..cdc0c5d
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+++ b/MCL86jr/FPGA/Untitled.cfi
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+# PROMGEN: Xilinx Prom Generator P.20131013
+# Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+SOFTWARE_VERSION P.20131013
+DATE            11/11/2020 - 19:13
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diff --git a/MCL86jr/FPGA/Untitled.mcs b/MCL86jr/FPGA/Untitled.mcs
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diff --git a/MCL86jr/FPGA/Untitled.prm b/MCL86jr/FPGA/Untitled.prm
new file mode 100644
index 0000000..d28ece1
--- /dev/null
+++ b/MCL86jr/FPGA/Untitled.prm
@@ -0,0 +1,17 @@
+PROMGEN: Xilinx Prom Generator P.20131013
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+promgen -w -p mcs -c FF -o C:\MCL\MCL86\MCL86jr//Untitled -s 16384 -u 0 C:\MCL\MCL86\MCL86jr\MCL86jr\mcl86jr.bit -spi 
+
+PROM C:\MCL\MCL86\MCL86jr\Untitled.prm map: Wed Nov 11 19:13:13 2020
+
+Calculating PROM checksum with fill value ff
+
+Format        Mcs86 (32-bit)
+Size          16384K
+PROM start    0000:0000
+PROM end      00ff:ffff
+PROM checksum fa0a0362
+
+        Addr1        Addr2                     Date File(s)
+    0000:0000    0005:3393     Nov 11 19:11:54 2020 C:/MCL/MCL86/MCL86jr/MCL86jr/mcl86jr.bit
diff --git a/MCL86jr/FPGA/impact.xsl b/MCL86jr/FPGA/impact.xsl
new file mode 100644
index 0000000..3baed9b
--- /dev/null
+++ b/MCL86jr/FPGA/impact.xsl
@@ -0,0 +1,55 @@
+<xsl:stylesheet
+  xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
+  version="1.0">
+  
+  <xsl:output method="html"/>
+  
+  <xsl:template match="/">
+<b>
+  <xsl:text>Current iMPACT Usage Statistics.</xsl:text>
+  <br></br>
+  <xsl:text>Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.</xsl:text>
+</b>
+  <br></br>
+  <br></br>
+  <xsl:text>This page displays the current iMPACT device usage statistics that will be sent to Xilinx using WebTalk.</xsl:text>
+
+<table width = "100%" border="1" CELLSPACING="0" cols="50% 50%">
+    <xsl:for-each select="document/application/section">
+<tr>
+<th COLSPAN="2" BGCOLOR="#99CCFF"><xsl:value-of select="@name"/></th>
+      
+</tr>
+    		<xsl:for-each select="property">
+<tr>
+	<td><xsl:value-of select="@name"/></td>
+
+	<td><xsl:value-of select="@value"/></td>
+</tr>
+
+        
+        </xsl:for-each>
+
+        <xsl:for-each select="item">
+<tr>
+          <td COLSPAN="2" BGCOLOR="#FFFF99"><b><xsl:value-of select="@name"/></b></td>
+</tr>
+          <xsl:value-of select="@value"/>
+          <xsl:for-each select="property">    
+<tr>
+      			<td><xsl:value-of select="@name"/></td>
+      			<td><xsl:value-of select="@value"/>&#x20;</td>
+</tr>
+      			 
+    			</xsl:for-each>
+          
+    		</xsl:for-each>
+    </xsl:for-each>
+</table>
+  </xsl:template>
+
+</xsl:stylesheet>
+      
+      <!--
+      <xsl:if test="position() != last()"> <h1><xsl:text> </xsl:text></h1></xsl:if>
+      -->
diff --git a/MCL86jr/FPGA/impact_impact.xwbt b/MCL86jr/FPGA/impact_impact.xwbt
new file mode 100644
index 0000000..611edd3
--- /dev/null
+++ b/MCL86jr/FPGA/impact_impact.xwbt
@@ -0,0 +1,8 @@
+INTSTYLE=impact
+INFILE=C:\MCL\MCL86\MCL86jr\impact.xsl
+OUTFILE=C:\MCL\MCL86\MCL86jr\impact.xsl
+FAMILY=Single
+PART=Single
+WORKINGDIR=C:\MCL\MCL86\MCL86jr
+LICENSE=iMPACT
+USER_INFO=iMPACT
diff --git a/MCL86jr/FPGA/src4synth/MCL86_Microcode_Xilinx.coe b/MCL86jr/FPGA/src4synth/MCL86_Microcode_Xilinx.coe
new file mode 100644
index 0000000..eb6c29e
--- /dev/null
+++ b/MCL86jr/FPGA/src4synth/MCL86_Microcode_Xilinx.coe
@@ -0,0 +1,2 @@
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diff --git a/MCL86jr/FPGA/src4synth/MCL86jr.v b/MCL86jr/FPGA/src4synth/MCL86jr.v
new file mode 100644
index 0000000..59bb36d
--- /dev/null
+++ b/MCL86jr/FPGA/src4synth/MCL86jr.v
@@ -0,0 +1,354 @@
+//
+//
+//  File Name   :  MCL86jr.v
+//  Used on     :  MCL86jr Board
+//  Author      :  Ted Fried, MicroCore Labs
+//  Creation    :  10/8/2015
+//  Code Type   :  Synthesizable
+//
+//   Description:
+//   ============
+//   
+//  Top level for the MCL86 8088 CPU core running with minimum mode BIU
+//
+//------------------------------------------------------------------------
+//
+// Modification History:
+// =====================
+//
+// Revision 1.0 10/8/15 
+// Initial revision
+//
+//
+//------------------------------------------------------------------------
+//
+// Copyright (c) 2020 Ted Fried
+// 
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+// 
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+// 
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+//------------------------------------------------------------------------
+
+module MCL86jr
+  (  
+    input				CORE_CLK,
+
+    input				CLK,
+    input				RESET,
+
+    input				READY,
+    input				INTR,
+    input				NMI,
+
+	
+    output        		A19,
+    output        		A18,
+    output        		A17,
+    output        		A16,
+    output        		A15,
+    output        		A14,
+    output        		A13,
+    output        		A12,
+    output        		A11,
+    output        		A10,
+    output        		A9,
+    output        		A8,
+    inout        		AD7,
+    inout        		AD6,
+    inout        		AD5,
+    inout        		AD4,
+    inout        		AD3,
+    inout        		AD2,
+    inout        		AD1,
+    inout        		AD0,
+
+    output				ALE,
+    output				INTA_n,
+    output				RD_n,
+    output				WR_n,
+    output				IOM,
+    output				DTR,
+    output				DEN,
+    output				SSO_n,
+	
+    output [18:0]		SRAM_A,
+    inout  [7:0]		SRAM_D,
+    output				SRAM_CE_n,
+    output				SRAM_OE_n,
+    output				SRAM_WE_n,
+
+    output [7:0]		LED,
+	
+	output 		 		BUF1_OE_n,
+	output 		 		BUF2_OE_n,
+	output 		 		BUF2_DIR
+	
+
+  );
+
+//------------------------------------------------------------------------
+ 	  
+
+// Internal Signals
+
+reg  t_reset_d1='h0;   
+reg  t_reset_d2='h0;   
+reg  t_reset_d3='h0;   
+reg  t_reset_d4='h0;   
+reg  t_eu_flag_i_d;
+reg  t_biu_ad_oe_d1;
+reg  t_biu_ad_oe_d2;
+reg  t_biu_lock_n_d;
+reg  prescaler_d;
+reg  led_go_left;
+reg  fpga_config_done;
+wire core_clk_int;
+wire t_eu_prefix_lock;
+wire t_eu_flag_i;
+wire t_biu_lock_n;
+wire t_pfq_empty;
+wire t_biu_done;
+wire t_biu_clk_counter_zero;
+wire t_biu_ad_oe;
+wire t_biu_nmi_caught;
+wire t_biu_nmi_debounce;
+wire t_sram_d_oe;  
+wire t_biu_intr;
+reg  [26:0] prescaler;  
+reg  [7:0]  led_int; 
+reg  [19:0] trigger_address;
+reg  [19:0] t_biu_ad_out_d;
+wire [19:0] t_biu_ad_out;
+wire [7:0]  t_biu_ad_in;
+wire [2:0]  t_s2_s0_out;
+wire [15:0] t_eu_biu_command;
+wire [15:0] t_eu_biu_dataout;
+wire [15:0] t_eu_register_r3;
+wire [7:0]  t_pfq_top_byte;
+wire [15:0] t_pfq_addr_out;
+wire [15:0] t_biu_register_es;
+wire [15:0] t_biu_register_ss;
+wire [15:0] t_biu_register_cs;
+wire [15:0] t_biu_register_ds;
+wire [15:0] t_biu_register_rm;
+wire [15:0] t_biu_register_reg;
+wire [15:0] t_biu_return_data;
+wire [7:0] t_sram_d_out;  
+
+	
+
+  spartan6_pll SPARTAN6PLL
+  (
+    .CLK_IN1	(CORE_CLK), 
+    .CLK_OUT1	(core_clk_int) 
+  ); 
+  
+
+
+//------------------------------------------------------------------------
+//
+// CPU Bus Combinationals
+//
+//------------------------------------------------------------------------
+
+assign A19      = t_biu_ad_out_d[19];
+assign A18      = t_biu_ad_out_d[18];
+assign A17      = t_biu_ad_out_d[17];
+assign A16      = t_biu_ad_out_d[16];
+assign A15      = t_biu_ad_out_d[15];
+assign A14      = t_biu_ad_out_d[14];
+assign A13      = t_biu_ad_out_d[13];
+assign A12      = t_biu_ad_out_d[12];
+assign A11      = t_biu_ad_out_d[11];
+assign A10      = t_biu_ad_out_d[10];
+assign A9       = t_biu_ad_out_d[9];
+assign A8       = t_biu_ad_out_d[8];
+
+assign AD7      = (t_biu_ad_oe_d2==1'b1) ?  t_biu_ad_out_d[7] : 'hZ; 
+assign AD6      = (t_biu_ad_oe_d2==1'b1) ?  t_biu_ad_out_d[6] : 'hZ; 
+assign AD5      = (t_biu_ad_oe_d2==1'b1) ?  t_biu_ad_out_d[5] : 'hZ; 
+assign AD4      = (t_biu_ad_oe_d2==1'b1) ?  t_biu_ad_out_d[4] : 'hZ; 
+assign AD3      = (t_biu_ad_oe_d2==1'b1) ?  t_biu_ad_out_d[3] : 'hZ; 
+assign AD2      = (t_biu_ad_oe_d2==1'b1) ?  t_biu_ad_out_d[2] : 'hZ; 
+assign AD1      = (t_biu_ad_oe_d2==1'b1) ?  t_biu_ad_out_d[1] : 'hZ; 
+assign AD0      = (t_biu_ad_oe_d2==1'b1) ?  t_biu_ad_out_d[0] : 'hZ; 
+
+assign t_biu_ad_in[7:0] = { AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0 };
+
+
+assign BUF1_OE_n =  1'b0; // Always enabled for now, but fix when HLD/HLDA is added
+assign BUF2_OE_n =  1'b0; // ~ t_biu_ad_oe_d2;
+assign BUF2_DIR =   ~ t_biu_ad_oe_d2;
+
+assign SRAM_CE_n = 1'b0;
+assign SRAM_D = (t_sram_d_oe==1'b1) ? t_sram_d_out : 8'hZ;
+
+assign LED[7] = ~led_int[7];
+assign LED[6] = ~led_int[6];
+assign LED[5] = ~led_int[5];
+assign LED[4] = ~led_int[4];
+assign LED[3] = ~led_int[3];
+assign LED[2] = ~led_int[2];
+assign LED[1] = ~led_int[1];
+assign LED[0] = ~led_int[0];
+
+	
+//------------------------------------------------------------------------
+
+always @(posedge core_clk_int)
+begin : REGISTER_IOS
+	
+    t_biu_ad_oe_d1 <= t_biu_ad_oe;
+    t_biu_ad_oe_d2 <= t_biu_ad_oe_d1;
+  
+    t_biu_ad_out_d <= t_biu_ad_out;
+    
+    t_eu_flag_i_d <= t_eu_flag_i;
+  
+    t_biu_lock_n_d <= t_biu_lock_n;
+  
+    t_reset_d1 <= RESET;
+    t_reset_d2 <= t_reset_d1;
+    t_reset_d3 <= t_reset_d2;
+	
+	// Use either the PCjr board reset or an internal timer for a reset 
+	if ( (t_reset_d3==1'b1 && t_reset_d2==1'b1) || (fpga_config_done==1'b0) )
+	  begin
+	    t_reset_d4 <= 1'b1;
+	    led_int <= 8'b10000000;
+      end	
+	else
+	  begin
+	    t_reset_d4 <= t_reset_d3;
+      end
+	  
+  
+    prescaler <= prescaler + 1'b1;
+	prescaler_d <= prescaler[21];
+
+	if (prescaler[26]==1'b1) fpga_config_done <= 1'b1;
+
+	
+	// Blink the sweeping LEDs
+	if (prescaler_d==1'b0 && prescaler[21]==1'b1)
+	  begin	  
+
+  	    if (led_go_left==1'b0)
+		  led_int[7:0] <= {led_int[0] , led_int[7:1] };
+		else
+		  led_int[7:0] <= {led_int[6:0] , led_int[7] };
+		  
+	    if (led_int[6]==1'b1)  led_go_left <= 1'b0;
+	    if (led_int[1]==1'b1)  led_go_left <= 1'b1;
+		
+      end
+
+  
+end
+
+
+//------------------------------------------------------------------------
+// BIU Core 
+//------------------------------------------------------------------------
+
+biu_min						BIU_CORE
+  (
+	.CORE_CLK_INT			(core_clk_int),
+	.RESET_INT				(t_reset_d4),
+	.CLK					(CLK),
+	.READY_IN 				(READY),
+	.NMI					(NMI),
+	.INTR					(INTR),
+	.INTA_n					(INTA_n),
+	.ALE					(ALE),
+	.RD_n					(RD_n),
+	.WR_n					(WR_n),
+	.SSO_n					(SSO_n),
+	.IOM					(IOM),
+	.DTR					(DTR),
+	.DEN					(DEN),
+	.AD_OE					(t_biu_ad_oe),
+	.AD_OUT					(t_biu_ad_out),
+	.AD_IN					(t_biu_ad_in),
+	.EU_BIU_COMMAND			(t_eu_biu_command),
+	.EU_BIU_DATAOUT			(t_eu_biu_dataout),
+	.EU_REGISTER_R3			(t_eu_register_r3),
+	.EU_PREFIX_LOCK			(t_eu_prefix_lock),
+	.BIU_DONE				(t_biu_done),
+	.BIU_CLK_COUNTER_ZERO	(t_biu_clk_counter_zero), 
+	.BIU_SEGMENT			( ),	
+	.BIU_NMI_CAUGHT			(t_biu_nmi_caught),
+	.BIU_NMI_DEBOUNCE		(t_biu_nmi_debounce),
+	.BIU_INTR				(t_biu_intr),
+	.PFQ_TOP_BYTE			(t_pfq_top_byte),
+	.PFQ_EMPTY				(t_pfq_empty),
+	.PFQ_ADDR_OUT			(t_pfq_addr_out),
+	.BIU_REGISTER_ES		(t_biu_register_es),
+	.BIU_REGISTER_SS		(t_biu_register_ss),
+	.BIU_REGISTER_CS		(t_biu_register_cs),
+	.BIU_REGISTER_DS		(t_biu_register_ds),
+	.BIU_REGISTER_RM		(t_biu_register_rm),
+	.BIU_REGISTER_REG		(t_biu_register_reg),
+	.BIU_RETURN_DATA		(t_biu_return_data),
+	.SRAM_A					(SRAM_A),
+	.SRAM_D_OE				(t_sram_d_oe),
+	.SRAM_D_OUT				(t_sram_d_out),
+	.SRAM_D_IN				(SRAM_D),
+	.SRAM_OE_n				(SRAM_OE_n),
+	.SRAM_WE_n				(SRAM_WE_n)
+
+  );	
+
+
+//------------------------------------------------------------------------
+// EU Core 
+//------------------------------------------------------------------------
+
+mcl86_eu_core				EU_CORE
+  (
+	.CORE_CLK_INT			(core_clk_int),
+	.RESET_INT				(t_reset_d4),
+	.TEST_N_INT				(1'b1),
+	.EU_BIU_COMMAND			(t_eu_biu_command),
+	.EU_BIU_DATAOUT			(t_eu_biu_dataout),
+	.EU_REGISTER_R3			(t_eu_register_r3),
+	.EU_PREFIX_LOCK			(t_eu_prefix_lock),
+	.EU_FLAG_I				(t_eu_flag_i),
+	.BIU_DONE				(t_biu_done),
+	.BIU_CLK_COUNTER_ZERO	(t_biu_clk_counter_zero),
+	.BIU_NMI_CAUGHT			(t_biu_nmi_caught),
+	.BIU_NMI_DEBOUNCE		(t_biu_nmi_debounce),
+	.BIU_INTR				(t_biu_intr),
+	.PFQ_TOP_BYTE			(t_pfq_top_byte),
+	.PFQ_EMPTY				(t_pfq_empty),
+	.PFQ_ADDR_OUT			(t_pfq_addr_out),
+	.BIU_REGISTER_ES		(t_biu_register_es),
+	.BIU_REGISTER_SS		(t_biu_register_ss),
+	.BIU_REGISTER_CS		(t_biu_register_cs),
+	.BIU_REGISTER_DS		(t_biu_register_ds),
+	.BIU_REGISTER_RM		(t_biu_register_rm),
+	.BIU_REGISTER_REG		(t_biu_register_reg),
+	.BIU_RETURN_DATA		(t_biu_return_data)
+  );	
+	
+
+  
+endmodule
+
+
+//------------------------------------------------------------------------
diff --git a/MCL86jr/FPGA/src4synth/biu_min.v b/MCL86jr/FPGA/src4synth/biu_min.v
new file mode 100644
index 0000000..38f9ca8
--- /dev/null
+++ b/MCL86jr/FPGA/src4synth/biu_min.v
@@ -0,0 +1,924 @@
+//
+//
+//  File Name   :  biu_min.v
+//  Used on     :  MCL86jr Board
+//  Author      :  Ted Fried, MicroCore Labs
+//  Creation    :  10/8/2015
+//  Code Type   :  Synthesizable
+//
+//   Description:
+//   ============
+//   
+//  Bus Interface Unit of the i8088 processor - Minimum Mode
+//
+//------------------------------------------------------------------------
+//
+// Modification History:
+// =====================
+//
+// Revision 1.0 10/8/15 
+// Initial revision
+//
+//
+//------------------------------------------------------------------------
+//
+// Copyright (c) 2020 Ted Fried
+// 
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+// 
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+// 
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+//------------------------------------------------------------------------
+
+
+module biu_min
+  (  
+    input				CORE_CLK_INT,			// Core Clock
+
+	
+    input				CLK,					// 8088 Pins
+    input				RESET_INT,
+    input				READY_IN,
+    input				NMI,
+    input				INTR,
+    output reg			INTA_n,
+    output reg			ALE,
+    output reg			RD_n,
+    output reg			WR_n,
+    output  			SSO_n,
+    output reg			IOM,
+    output reg			DTR,
+    output reg			DEN,
+    output reg      	AD_OE,
+    output reg [19:0]	AD_OUT,
+    input  [7:0]		AD_IN,
+
+	
+    input  [15:0]		EU_BIU_COMMAND,			// EU to BIU Signals
+    input  [15:0]		EU_BIU_DATAOUT,
+    input  [15:0]		EU_REGISTER_R3,
+    input           	EU_PREFIX_LOCK,
+	
+	
+	output				BIU_DONE,				// BIU to EU Signals
+	output				BIU_CLK_COUNTER_ZERO,
+	output [1:0]		BIU_SEGMENT,
+    output				BIU_NMI_CAUGHT,
+    input				BIU_NMI_DEBOUNCE,
+    output reg			BIU_INTR,
+
+	output [7:0]		PFQ_TOP_BYTE,
+    output				PFQ_EMPTY,
+    output[15:0] 		PFQ_ADDR_OUT,
+
+    output [15:0]		BIU_REGISTER_ES,
+    output [15:0]		BIU_REGISTER_SS,
+    output [15:0]		BIU_REGISTER_CS,
+    output [15:0]		BIU_REGISTER_DS,
+    output [15:0]		BIU_REGISTER_RM,
+    output [15:0]		BIU_REGISTER_REG,
+    output [15:0]		BIU_RETURN_DATA,
+		
+    output reg [18:0]	SRAM_A,
+    output reg      	SRAM_D_OE,
+    output reg [7:0]	SRAM_D_OUT,
+    input [7:0]	        SRAM_D_IN,
+    output reg			SRAM_OE_n,
+    output reg			SRAM_WE_n	
+
+  );
+
+//------------------------------------------------------------------------
+ 	  
+
+// Internal Signals
+
+reg   biu_done_int;
+reg   byte_num;
+reg   clk_d1;
+reg   clk_d2;
+reg   clk_d3;
+reg   clk_d4;
+reg   eu_biu_req_caught;
+reg   eu_biu_req_d1;
+reg   eu_prefix_lock_d1;
+reg   eu_prefix_lock_d2;
+reg   intr_d1;
+reg   intr_d2;
+reg   intr_d3;
+reg   nmi_caught;
+reg   nmi_d1;
+reg   nmi_d2;
+reg   nmi_d3;
+reg   nmi_d4;
+reg   nmi_d5;
+reg   pfq_write;
+reg   ready_d1;
+reg   ready_d2;
+reg   ready_d3;
+reg   word_cycle;
+reg   inta_n_int;
+reg   ale_int;
+reg   rd_n_int;
+reg   wr_n_int;
+reg   iom_int;
+reg   dtr_int;
+reg   den_int;
+reg   sram_select;
+
+wire  eu_biu_req;
+wire  eu_prefix_seg;
+wire  pfq_full;
+wire  pfq_empty;
+wire clk_rising_edge;
+wire clk_falling_edge;
+
+reg  [7:0]  ad_in_int;
+reg  [19:0] addr_out_temp;
+reg  [7:0]  biu_state;
+reg  [15:0] biu_register_cs;
+reg  [15:0] biu_register_es;
+reg  [15:0] biu_register_ss;
+reg  [15:0] biu_register_ds;
+reg  [15:0] biu_register_rm;
+reg  [15:0] biu_register_reg;
+reg  [15:0] biu_register_cs_d1;
+reg  [15:0] biu_register_es_d1;
+reg  [15:0] biu_register_ss_d1;
+reg  [15:0] biu_register_ds_d1;
+reg  [15:0] biu_register_rm_d1;
+reg  [15:0] biu_register_reg_d1;
+reg  [15:0] biu_register_cs_d2;
+reg  [15:0] biu_register_es_d2;
+reg  [15:0] biu_register_ss_d2;
+reg  [15:0] biu_register_ds_d2;
+reg  [15:0] biu_register_rm_d2;
+reg  [15:0] biu_register_reg_d2;
+reg  [15:0] biu_return_data_int;
+reg  [15:0] biu_return_data_int_d1;
+reg  [15:0] biu_return_data_int_d2;
+reg  [12:0] clock_cycle_counter;
+reg  [15:0] eu_register_r3_d;
+reg  [7:0]  latched_data_in;
+reg  [15:0] pfq_addr_out;
+reg  [7:0]  pfq_entry0;
+reg  [7:0]  pfq_entry1;
+reg  [7:0]  pfq_entry2;
+reg  [7:0]  pfq_entry3;
+reg  [15:0] pfq_addr_in;
+reg  [7:0]  pfq_top_byte_int_d1;
+reg  [15:0] pfq_addr_out_d1;
+reg  [2:0]  s_bits;
+reg  [25:0] nmi_counter;
+reg  [7:0]  mcl6_feature;
+
+wire [15:0] biu_muxed_segment;	 
+wire [1:0]  biu_segment;	
+wire [1:0]  eu_biu_strobe;
+wire [1:0]  eu_biu_segment;
+wire [4:0]  eu_biu_req_code;
+wire [1:0]  eu_qs_out;
+wire [1:0]  eu_segment_override_value; 
+wire [7:0]  pfq_top_byte_int;
+	  
+  
+//------------------------------------------------------------------------
+//
+// BIU  Combinationals
+//
+//------------------------------------------------------------------------
+
+// Outputs to the EU
+//
+assign BIU_DONE                 = biu_done_int;
+assign PFQ_EMPTY                = pfq_empty;
+assign PFQ_ADDR_OUT             = pfq_addr_out_d1; 
+assign BIU_SEGMENT				= biu_segment;
+assign BIU_REGISTER_ES          = biu_register_es_d2;
+assign BIU_REGISTER_SS          = biu_register_ss_d2;
+assign BIU_REGISTER_CS          = biu_register_cs_d2;
+assign BIU_REGISTER_DS          = biu_register_ds_d2;
+assign BIU_REGISTER_RM          = biu_register_rm_d2;
+assign BIU_REGISTER_REG         = biu_register_reg_d2;
+assign BIU_RETURN_DATA          = biu_return_data_int_d2;
+assign BIU_NMI_CAUGHT			= nmi_caught;
+
+
+
+// Input signals from the EU requesting BIU processing.
+//  eu_biu_strobe[1:0] are available for only one clock cycle and cause BIU to take immediate action.
+//  eu_biu_req stays asserted until the BIU is available to service the request.
+//  
+assign eu_prefix_seg		           = EU_BIU_COMMAND[14];
+assign eu_biu_strobe[1:0]              = EU_BIU_COMMAND[13:12]; // 01=opcode fetch 10=clock load 11=load segment register(eu_biu_req_code has the regiter#)
+assign eu_biu_segment[1:0]             = EU_BIU_COMMAND[11:10];
+assign eu_biu_req                      = EU_BIU_COMMAND[9];
+assign eu_biu_req_code                 = EU_BIU_COMMAND[8:4];
+assign eu_qs_out[1:0]                  = EU_BIU_COMMAND[3:2];  // Updated for every opcode fetch using biu_strobe and Jump request using eu_biu_rq
+assign eu_segment_override_value[1:0]  = EU_BIU_COMMAND[1:0];
+
+
+
+// Select either the current EU Segment or the Segment Override value.
+assign biu_segment =  (eu_prefix_seg==1'b1) ? eu_segment_override_value  : eu_biu_segment;  
+
+												   
+assign biu_muxed_segment = (biu_segment==2'b00) ? biu_register_es :
+                           (biu_segment==2'b01) ? biu_register_ss :
+                           (biu_segment==2'b10) ? biu_register_cs :
+                                                  biu_register_ds ;
+
+															
+// Steer the Prefetch Queue to the EU
+assign pfq_top_byte_int = (pfq_addr_out[1:0]==2'b00) ? pfq_entry0 : 
+                          (pfq_addr_out[1:0]==2'b01) ? pfq_entry1 : 
+                          (pfq_addr_out[1:0]==2'b10) ? pfq_entry2 : 
+					                                   pfq_entry3 ;
+  
+assign PFQ_TOP_BYTE = pfq_top_byte_int_d1;  
+
+// Generate the Prefetch Queue Flags
+assign pfq_full  = ( (pfq_addr_in[2]!=pfq_addr_out[2]) && (pfq_addr_in[1:0]==pfq_addr_out[1:0]) ) ?  1'b1 : 1'b0;
+assign pfq_empty = ( (pfq_addr_in[2]==pfq_addr_out[2]) && (pfq_addr_in[1:0]==pfq_addr_out[1:0]) ) ?  1'b1 : 1'b0;
+
+
+// Instruction cycle accuracy counter
+assign BIU_CLK_COUNTER_ZERO = (clock_cycle_counter==13'h0000 || mcl6_feature[0]==1'b1) ? 1'b1 : 1'b0;
+
+assign SSO_n = s_bits[0];
+
+assign clk_rising_edge  = (clk_d4==1'b0 && clk_d3==1'b0 && clk_d2==1'b1) ? 1'b1 : 1'b0;	  
+assign clk_falling_edge = (clk_d4==1'b1 && clk_d3==1'b1 && clk_d2==1'b0) ? 1'b1 : 1'b0;	  
+
+		
+														
+//------------------------------------------------------------------------
+//
+// BIU State Machine
+//
+//------------------------------------------------------------------------
+//
+
+always @(posedge CORE_CLK_INT)
+begin : BIU_STATE_MACHINE
+
+  if (RESET_INT==1'b1)
+    begin
+      clk_d1 <= 'h0;
+      clk_d2 <= 'h0;
+      clk_d3 <= 'h0;
+      clk_d4 <= 'h0;
+	  nmi_d1 <= 'h0;
+      nmi_d2 <= 'h0;
+      nmi_d3 <= 'h0;
+      nmi_d4 <= 'h0;
+      nmi_d5 <= 'h0;
+	  nmi_caught <= 'h0;
+      eu_register_r3_d <= 'h0;
+      eu_biu_req_caught <= 'h0;
+      biu_register_cs <= 16'hFFFF;
+      biu_register_es <= 'h0;
+      biu_register_ss <= 'h0;
+      biu_register_ds <= 'h0;
+      biu_register_rm <= 'h0;
+      biu_register_reg <= 'h0;
+      clock_cycle_counter <= 'h0;
+      pfq_addr_out <= 'h0;
+      pfq_entry0 <= 'h0;
+      pfq_entry1 <= 'h0;
+      pfq_entry2 <= 'h0;
+      pfq_entry3 <= 'h0;
+      biu_state <= 8'hD0;
+      pfq_write <= 'h0;
+      pfq_addr_in <= 'h0;
+	  biu_return_data_int <= 'h0;
+	  biu_done_int <= 'h0;
+	  ready_d1 <= 'h0;
+      ready_d2 <= 'h0;
+      ready_d3 <= 'h0;
+	  eu_biu_req_d1 <= 'h0;
+	  latched_data_in <= 'h0;
+	  addr_out_temp <= 'h0;
+	  s_bits <= 3'b111;
+	  AD_OUT <= 'h0;
+	  word_cycle <= 1'b0;
+	  byte_num <= 1'b0;
+	  ad_in_int <= 'h0;
+	  BIU_INTR <= 'h0;
+	  eu_prefix_lock_d1 <= 'h0;
+      eu_prefix_lock_d2 <= 'h0;
+	  intr_d1 <= 'h0;
+	  intr_d2 <= 'h0;
+	  intr_d3 <= 'h0;	 
+	  AD_OE <= 'h0;
+	  RD_n <= 1'b1;
+	  WR_n <= 1'b1;
+	  IOM <= 'h0;
+	  DTR <= 'h0;
+	  DEN <= 1'b1;	 
+	  INTA_n <= 1'b1;
+	  inta_n_int <= 1'b1;
+	  ale_int <= 1'b0;
+	  rd_n_int <= 1'b1;
+	  wr_n_int <= 1'b1;
+	  iom_int <= 1'b0;
+	  dtr_int <= 1'b0;
+	  den_int <= 1'b1;
+	  SRAM_OE_n <= 1'b1;
+	  SRAM_WE_n <= 1'b1;
+	  SRAM_D_OE <= 1'b0;
+    end
+    
+else    
+  begin     
+  
+    // Register pipelining
+    clk_d1 <= CLK;
+	clk_d2 <= clk_d1;
+	clk_d3 <= clk_d2;
+	clk_d4 <= clk_d3;
+    
+	ready_d1 <= READY_IN;
+	ready_d2 <= ready_d1;
+	ready_d3 <= ready_d2;
+	
+	intr_d1 <= INTR;
+	intr_d2 <= intr_d1;
+	intr_d3 <= intr_d2;
+	
+	
+	// These signals may be pipelined from zero to two clocks.
+	// They are currently pipelined by two clocks.
+	biu_register_es_d1   <= biu_register_es;
+    biu_register_ss_d1   <= biu_register_ss; 	  
+    biu_register_cs_d1   <= biu_register_cs; 	  
+    biu_register_ds_d1   <= biu_register_ds; 
+    biu_register_rm_d1   <= biu_register_rm; 
+    biu_register_reg_d1  <= biu_register_reg;
+    biu_register_es_d2   <= biu_register_es_d1;
+    biu_register_ss_d2   <= biu_register_ss_d1; 	  
+    biu_register_cs_d2   <= biu_register_cs_d1; 	  
+    biu_register_ds_d2   <= biu_register_ds_d1; 
+    biu_register_rm_d2   <= biu_register_rm_d1; 
+    biu_register_reg_d2  <= biu_register_reg_d1;
+		
+
+	// These signals may be pipelined from zero to one clock.
+	// They are currently pipelined by one clock.
+    pfq_top_byte_int_d1 <= pfq_top_byte_int;	 
+    pfq_addr_out_d1 <= pfq_addr_out;
+
+	
+	// This signal may be pipelined any number of clocks as 
+	// long as is stable before BIU_DONE is asserted.
+    biu_return_data_int_d1 <= biu_return_data_int;
+    biu_return_data_int_d2 <= biu_return_data_int_d1;
+
+	
+	nmi_d1 <= NMI;
+	nmi_d2 <= nmi_d1;
+	nmi_d3 <= nmi_d2;
+	nmi_d4 <= nmi_d3;
+	nmi_d5 <= nmi_d4; 
+	
+	
+	// If NMI hardware signal is high for 400ms, then we missed the rising edge.
+	// The solution is to add a '0' in the input pipeline so that a rising edge is seen.
+	//
+	if (nmi_d5==1'b1) nmi_counter <= nmi_counter + 1'b1;
+	else nmi_counter <= 'h0;
+	
+	if (nmi_counter==26'h2625a00) 
+	  begin
+	    nmi_d2 <= 1'b0;
+		nmi_counter <= 'h0;
+	  end
+	
+	// NMI is caught on it's rising edge 
+	if (BIU_NMI_DEBOUNCE==1'b1)
+	  begin
+	    nmi_caught <= 1'b0;
+	  end
+	else if (nmi_d5==1'b0 && nmi_d4==1'b1)
+	  begin
+	    nmi_caught <= 1'b1;
+	  end
+	  
+	// INTR sampled on the rising edge of the CLK
+ 	if (clk_d4==1'b0 && clk_d3==1'b0 && clk_d2==1'b1)
+	  begin
+	    BIU_INTR <= intr_d3;
+      end
+	
+	eu_prefix_lock_d1 <= EU_PREFIX_LOCK;
+    eu_prefix_lock_d2 <= eu_prefix_lock_d1;	  			  
+
+	
+	// Register pipelining in and out of the BIU.
+	eu_register_r3_d <= EU_REGISTER_R3;
+	ad_in_int <= AD_IN;
+	
+	INTA_n	<= inta_n_int;
+    ALE		<= ale_int;
+    RD_n	<= rd_n_int;
+    WR_n	<= wr_n_int;
+    IOM		<= iom_int;
+    DTR		<= dtr_int;
+    DEN		<= den_int;
+	    
+
+	// Capture a bus request from the EU
+	eu_biu_req_d1 <= eu_biu_req;
+	if (eu_biu_req_d1==1'b0 && eu_biu_req==1'b1)
+	  begin
+	    eu_biu_req_caught <= 1'b1;
+      end
+	else if (biu_done_int==1'b1)
+	  begin
+	    eu_biu_req_caught <= 1'b0;
+	  end
+					
+	
+	// Strobe from EU to update the segment and addressing registers
+	if (eu_biu_strobe==2'b11)
+	  begin
+	    case (eu_biu_req_code[2:0])  // synthesis parallel_case
+		  3'h0 : biu_register_es      <= EU_BIU_DATAOUT[15:0];
+      	  3'h1 : biu_register_ss      <= EU_BIU_DATAOUT[15:0];
+  	      3'h2 : biu_register_cs      <= EU_BIU_DATAOUT[15:0];
+  	      3'h3 : biu_register_ds      <= EU_BIU_DATAOUT[15:0];
+  	      3'h4 : biu_register_rm      <= EU_BIU_DATAOUT[15:0];
+  	      3'h5 : biu_register_reg     <= EU_BIU_DATAOUT[15:0];
+  	  	  default :  ;
+  	    endcase
+      end  	
+
+    // Strobe from EU to set the 8088 clock cycle counter
+    if (eu_biu_strobe==2'b10)
+      begin
+  	    clock_cycle_counter <= EU_BIU_DATAOUT[12:0];
+  	  end
+    else if (clock_cycle_counter!=13'h0000)
+      begin
+  	    clock_cycle_counter <= clock_cycle_counter - 1;
+  	  end
+    
+
+    // Prefetch Queue 
+	// --------------
+	// Increment the output address of the queue upon EU fetch request strobe.
+	// Update/flush the Prefetch Queue when the EU asserts the Jump request.
+	// Increment the input address during prefetch queue fetches.
+    //---------------------------------------------------------------------------------
+    if (eu_biu_req_caught==1'b1 && eu_biu_req_code==5'h19) 
+      begin
+        pfq_addr_out <= eu_register_r3_d; // Update the prefetch queue to the new address.
+      end    
+	else if (eu_biu_strobe==2'b01 && pfq_empty==1'b0)
+      begin  
+    	pfq_addr_out <= pfq_addr_out + 1;  // Increment the current IP - Instruction Pointer
+      end      	                  
+  	    
+		
+    if (eu_biu_req_caught==1'b1 && eu_biu_req_code==5'h19) 
+      begin
+        pfq_addr_in <= eu_register_r3_d; // Update the prefetch queue to the new address.
+      end    
+	else if (pfq_write==1'b1)
+      begin  
+	    pfq_addr_in <= pfq_addr_in + 1;
+      end      	                  
+  	    
+	  
+	// Write to the selected prefetch queue entry.
+	if (pfq_write==1'b1)
+      begin
+	    case (pfq_addr_in[1:0])  // synthesis parallel_case
+          2'b00 : pfq_entry0 <= latched_data_in[7:0];
+          2'b01 : pfq_entry1 <= latched_data_in[7:0];
+          2'b10 : pfq_entry2 <= latched_data_in[7:0];
+          2'b11 : pfq_entry3 <= latched_data_in[7:0];
+          default :  ;
+          endcase    
+      end       
+	  
+
+	// 8088 BIU State Machine
+	// ----------------------
+	
+	biu_state <= biu_state + 1'b1;
+  	case (biu_state) // synthesis parallel_case
+	  
+	  8'h00 : begin
+	            // Debounce signals
+				pfq_write <= 1'b0;
+				byte_num <= 1'b0;	
+				word_cycle <= 1'b0;
+				sram_select <= 1'b0;				
+				
+
+				if (eu_biu_req_caught==1'b1)
+				  begin				  	
+						
+				    case (eu_biu_req_code)  // synthesis parallel_case
+					  					
+					  // Interrupt ACK Cycle 
+					  8'h16 : begin					  
+					            addr_out_temp <= { 4'h0 , eu_register_r3_d[15:0] };
+					            word_cycle <= 1'b1;
+								s_bits <= 3'b000;
+								biu_state <= 8'h01;
+						      end
+								  
+					  // IO Byte Read 
+					  8'h08 : begin
+					            addr_out_temp <= { 4'h0 , eu_register_r3_d[15:0] };
+								s_bits <= 3'b001;
+								biu_state <= 8'h01;
+						      end
+								 
+					  // IO Word Read 
+					  8'h1A : begin
+					            addr_out_temp <= { 4'h0 , eu_register_r3_d[15:0] };
+					            word_cycle <= 1'b1; 
+								s_bits <= 3'b001;
+								biu_state <= 8'h01;
+						      end
+												
+					  // IO Byte Write 
+					  8'h0A : begin
+					            addr_out_temp <= { 4'h0 , eu_register_r3_d[15:0] };
+								s_bits <= 3'b010;
+								biu_state <= 8'h01;
+						      end
+							  					
+					  // IO Word Write 
+					  8'h1C : begin
+					            addr_out_temp <= { 4'h0 , eu_register_r3_d[15:0] };
+					            word_cycle <= 1'b1; 
+								s_bits <= 3'b010;
+								biu_state <= 8'h01;
+						      end
+							  					
+					  // Halt Request 
+					  8'h18 : begin
+					            addr_out_temp <= { biu_register_cs[15:0] , 4'h0 } + pfq_addr_out[15:0] ;
+								s_bits <= 3'b011;
+								biu_state <= 8'h01;
+						      end
+											
+					  // Memory Byte Read 
+					  8'h0C : begin
+					            addr_out_temp <= { biu_muxed_segment[15:0] , 4'h0 } + eu_register_r3_d[15:0];
+								s_bits <= 3'b101;
+								biu_state <= 8'h01;
+						      end
+												
+					  // Memory Word Read 
+					  8'h10 : begin
+					            addr_out_temp <= { biu_muxed_segment[15:0] , 4'h0 } + eu_register_r3_d[15:0];
+					            word_cycle <= 1'b1; 
+								s_bits <= 3'b101;
+								biu_state <= 8'h01;
+						      end
+												
+					  // Memory Word Read from Stack Segment
+					  8'h11 : begin
+								addr_out_temp <= { biu_register_ss[15:0] , 4'h0 } + eu_register_r3_d[15:0];
+					            word_cycle <= 1'b1; 
+								s_bits <= 3'b101;
+								biu_state <= 8'h01;
+						      end
+												
+					  // Memory Word Read from Segment 0x0000 - Used for interrupt vector fetches
+					  8'h12 : begin
+					            addr_out_temp <= { 4'h0 , eu_register_r3_d[15:0] };
+					            word_cycle <= 1'b1; 
+								s_bits <= 3'b101;
+								biu_state <= 8'h01;
+						      end
+												
+					  // Memory Byte Write 
+					  8'h0E : begin
+					            addr_out_temp <= { biu_muxed_segment[15:0] , 4'h0 } + eu_register_r3_d[15:0];
+								s_bits <= 3'b110;
+								biu_state <= 8'h01;
+						      end
+							 					
+					  // Memory Word Write 
+					  8'h13 : begin
+					            addr_out_temp <= { biu_muxed_segment[15:0] , 4'h0 } + eu_register_r3_d[15:0];
+					            word_cycle <= 1'b1; 
+								s_bits <= 3'b110;
+								biu_state <= 8'h01;
+						      end
+							  					
+					  // Memory Word Write to Stack Segment
+					  8'h14 : begin
+								addr_out_temp <= { biu_register_ss[15:0] , 4'h0 } + eu_register_r3_d[15:0];
+					            word_cycle <= 1'b1; 
+								s_bits <= 3'b110;
+								biu_state <= 8'h01;
+						      end
+							  	  					
+					  // Jump Request
+					  8'h19 : begin
+					            biu_done_int <= 1'b1;
+								biu_state <= 8'h0B;
+						      end
+								
+					  default : ;			  
+					endcase
+			      end
+				  
+				  
+				else if (pfq_full==1'b0)
+				  begin
+				  	addr_out_temp <= { biu_register_cs[15:0] , 4'h0 } + pfq_addr_in[15:0] ;
+					s_bits <= 3'b100;
+					biu_state <= 8'h01;
+				  end
+				  
+				else
+				  begin
+				    biu_state <= 8'h00;
+				  end
+				  
+		      end
+
+	    
+	  // Feature checks 
+      8'h01 : begin 				 
+                // Snoop memory writes to certain addresses within the PCjr's ROM
+	  	        if (s_bits[2:0]==3'b110 && addr_out_temp==20'hFFFF0) mcl6_feature <= EU_BIU_DATAOUT[7:0];
+				
+				SRAM_A[18:0] <= addr_out_temp[18:0];
+				
+	  	        if (s_bits[2]==1'b1 && addr_out_temp[19:16]>4'h1 && addr_out_temp[19:16]<4'hA)  
+				  begin
+				    sram_select <= 1'b1;
+					
+					// Fast SRAM controller
+					if (mcl6_feature[1]==1'b1) 
+					  begin
+					    biu_state <= 8'h10;
+						if (s_bits[2:0]==3'b110) biu_done_int <= 1'b1;	// Posted write, so send done back to EU				  
+					  end
+					  
+				  end
+			  end
+
+	    
+	  // 2 Wait for the next falling edge of CLK 
+      8'h02 : begin 				  
+	            if (clk_falling_edge==1'b1) 
+				  begin
+					iom_int <= ~s_bits[2]; // Memory cycles
+					dtr_int <=  s_bits[1]; // Read cycles
+				    AD_OUT[19:0] <= addr_out_temp[19:0];
+	  			    AD_OE <= 1'b1;
+				    ale_int <= 1'b1;
+			      end
+				else
+				  begin
+				    biu_state <= biu_state;
+				  end
+			  end
+
+	    
+	  // 3 Wait for the next rising edge of CLK 
+      8'h03 : begin 				  
+	            if (clk_rising_edge==1'b1) 
+				  begin
+				    ale_int <= 1'b0;
+				    if (s_bits[1:0]==2'b10) // Assert DEN_n early for write cycles
+				      begin
+				        den_int <= 1'b0;
+				      end
+			      end
+				else
+				  begin
+				    biu_state <= biu_state;
+				  end
+			  end
+		
+	    
+	  // 4 Wait for the next falling edge of CLK 
+      8'h04 : begin 				  
+	            if (clk_falling_edge==1'b1) 
+				  begin
+				    AD_OE <= s_bits[1];      // Turn off bus drivers for read and inta cycles
+					
+					case (s_bits[2:0])
+					  3'b000: inta_n_int <= 1'b0;  // Interrupt Acknowledge
+					  3'b001: rd_n_int   <= 1'b0;  // Read IO Port
+					  3'b010: wr_n_int   <= 1'b0;  // Write IO Port
+					  
+					  3'b100: rd_n_int   <= 1'b0;  // Code Access
+					  3'b101: rd_n_int   <= 1'b0;  // Read Memory
+					  3'b110: wr_n_int   <= 1'b0;  // Write Memory
+					  default: ;
+					endcase
+				
+				    if (word_cycle==1'b1 && byte_num==1'b1)
+				      begin
+				        AD_OUT[7:0] <= EU_BIU_DATAOUT[15:8];
+						SRAM_D_OUT[7:0] <= EU_BIU_DATAOUT[15:8];
+				      end
+				    else
+				      begin
+				        AD_OUT[7:0] <= EU_BIU_DATAOUT[7:0];
+						SRAM_D_OUT[7:0] <= EU_BIU_DATAOUT[7:0];
+				      end	
+  		          end
+				else
+				  begin
+				    biu_state <= biu_state;
+				  end
+			  end
+
+
+	    
+	  // 5 Wait for the next rising edge of CLK 
+      8'h05 : begin 			
+                SRAM_OE_n <= rd_n_int;	  
+                if (sram_select==1'b1) 
+				  begin
+				    SRAM_WE_n <= wr_n_int;	 
+					SRAM_D_OE <= ~wr_n_int;
+				  end
+				
+	            if (clk_rising_edge==1'b1) 
+				  begin
+				    den_int <= 1'b0; // Assert late DEN_n for read and inta cycles
+			      end
+				else
+				  begin
+				    biu_state <= biu_state;
+				  end
+			  end
+				  
+ 		
+	  // 6 Wait for the next falling edge of CLK   ** Nothing to do on this clock edge
+
+	  
+	  // 7 Wait for the next rising edge of CLK 
+      8'h07 : begin 				  
+	            if (clk_rising_edge==1'b1 && ready_d1==1'b1) 
+				  begin
+	                ale_int <= 1'b0;		 
+				  end
+				else
+				  begin
+				    biu_state <= biu_state;
+				  end
+			  end
+		
+		
+	  // 8 Wait for the next falling edge of CLK 
+      8'h08 : begin 				  
+	            if (clk_falling_edge==1'b1) 
+				  begin
+				    if (sram_select==1'b1) latched_data_in <= SRAM_D_IN; else latched_data_in <= ad_in_int;
+	                wr_n_int <= 1'b1;
+	                rd_n_int <= 1'b1;
+					SRAM_OE_n <= 1'b1;	  
+                    SRAM_WE_n <= 1'b1;
+				    inta_n_int <= 1'b1;	
+					
+	                if (s_bits[2:0]==3'b100)  pfq_write <= 1'b1;   // If a code fetch, then strobe the prefetch queue
+	                if (s_bits[1:0]!=2'b10)   den_int <= 1'b1; 
+
+				  end
+				else
+				  begin
+				    biu_state <= biu_state;
+				  end
+			  end 
+			  
+
+      //  8 Steer the data
+      8'h09 : begin
+	            SRAM_D_OE <= 1'b0;
+	            pfq_write <= 1'b0;  //  Debounce the prefetch queue write pulse and increment the prefetch queue address.
+	            if (s_bits!=3'b000 && (word_cycle==1'b1 && byte_num==1'b1))
+				  begin
+				    biu_return_data_int[15:8] <= latched_data_in[7:0];
+				  end
+				else
+				  begin
+				    biu_return_data_int[15:0] <= { 8'h00 , latched_data_in[7:0] };
+			      end
+			  end
+	          	
+				
+	  // 9 Wait for the next rising edge of CLK to complete the bus cycle
+      8'h0A : begin 				  
+	            if (clk_rising_edge==1'b1) 
+				  begin
+	                den_int <= 1'b1;
+					dtr_int <= 1'b1;
+	                addr_out_temp[15:0] <=  addr_out_temp[15:0] + 1;
+					
+				    if (word_cycle==1'b1 && byte_num==1'b0)
+				      begin		
+				        byte_num <= 1'b1;					 
+				        biu_state <= 8'h01;
+				      end
+				    else
+				      begin
+					    if (s_bits!=3'b100)
+					      begin
+					        biu_done_int <= 1'b1;
+					      end
+				        end
+				  end
+				else
+				  begin
+				    biu_state <= biu_state;
+				  end
+			  end
+						
+						
+      8'h0B : begin 
+	            biu_done_int <= 1'b0;
+				pfq_write <= 1'b0;
+				SRAM_D_OE <= 1'b0;
+				biu_state <= 8'h00;				
+		      end
+
+			  
+
+	  // Fast SRAM controller 
+      8'h10 : begin 	
+                biu_done_int <= 1'b0;	  
+                SRAM_D_OUT[7:0] <= EU_BIU_DATAOUT[7:0];	  
+				if (s_bits[2:1]==2'b10) SRAM_OE_n <= 1'b0; else SRAM_WE_n <= 1'b0; 
+				if (s_bits[2:1]==2'b11) SRAM_D_OE <= 1'b1;
+			  end
+
+      8'h16 : begin 		
+				SRAM_A[15:0] <= addr_out_temp[15:0] + 1'b1;
+	            SRAM_OE_n <= 1'b1;
+	            SRAM_WE_n <= 1'b1;
+                biu_return_data_int[15:0] <= { 8'h00 , SRAM_D_IN[7:0] };
+				latched_data_in <= SRAM_D_IN;
+				if (word_cycle==1'b0) 
+				  begin
+	                if (s_bits[2:0]==3'b100)
+					  begin
+					    pfq_write <= 1'b1;
+					  end
+					else
+					  begin
+						if (s_bits[2:0]!=3'b110) biu_done_int <= 1'b1;
+					  end
+				    biu_state <= 8'h0B;
+				  end
+			  end
+
+      8'h17 : begin 		
+                SRAM_D_OUT[7:0] <= EU_BIU_DATAOUT[15:8];	  
+				if (s_bits[2:1]==2'b10) SRAM_OE_n <= 1'b0; else SRAM_WE_n <= 1'b0;
+				if (s_bits[2:1]==2'b11) SRAM_D_OE <= 1'b1;
+			  end
+
+      8'h1D : begin 		
+				SRAM_OE_n <= 1'b1;
+				SRAM_WE_n <= 1'b1;
+                biu_return_data_int[15:8] <= SRAM_D_IN[7:0];
+				if (s_bits[2:0]!=3'b110) biu_done_int <= 1'b1;
+				biu_state <= 8'h0B;
+			  end
+			 
+			 
+	  default : ;			  
+    endcase
+
+
+	
+end
+
+end  // BIU
+
+ 
+endmodule // biu_min.v
+		
+		
+		
+		
+		
\ No newline at end of file
diff --git a/MCL86jr/FPGA/src4synth/eu.v b/MCL86jr/FPGA/src4synth/eu.v
new file mode 100644
index 0000000..dbde2f8
--- /dev/null
+++ b/MCL86jr/FPGA/src4synth/eu.v
@@ -0,0 +1,492 @@
+//
+//
+//  File Name   :  eu.v
+//  Used on     :  MCL86jr Board
+//  Author      :  Ted Fried, MicroCore Labs
+//  Creation    :  10/8/2015
+//  Code Type   :  Synthesizable
+//
+//   Description:
+//   ============
+//   
+//  Execution Unit of the i8088 processor - Microsequencer
+//
+//------------------------------------------------------------------------
+//
+// Modification History:
+// =====================
+//
+// Revision 1.0 10/8/15 
+// Initial revision
+//
+//
+//------------------------------------------------------------------------
+//
+// Copyright (c) 2020 Ted Fried
+// 
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+// 
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+// 
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+//------------------------------------------------------------------------
+
+
+module mcl86_eu_core
+  (  
+    input               CORE_CLK_INT,           // Core Clock
+    input               RESET_INT,              // Pipelined 8088 RESET pin
+    input               TEST_N_INT,             // Pipelined 8088 TEST_n pin
+
+    
+    output [15:0]       EU_BIU_COMMAND,         // EU to BIU Signals
+    output [15:0]       EU_BIU_DATAOUT,         
+    output [15:0]       EU_REGISTER_R3, 
+    output              EU_PREFIX_LOCK,
+    output              EU_FLAG_I,          
+    
+    
+    input               BIU_DONE,               // BIU to EU Signals
+    input               BIU_CLK_COUNTER_ZERO,
+    input               BIU_NMI_CAUGHT,
+    output              BIU_NMI_DEBOUNCE,
+    input               BIU_INTR,
+
+    
+    input [7:0]         PFQ_TOP_BYTE,
+    input               PFQ_EMPTY,
+    input[15:0]         PFQ_ADDR_OUT,
+
+    
+    input [15:0]        BIU_REGISTER_ES,
+    input [15:0]        BIU_REGISTER_SS,
+    input [15:0]        BIU_REGISTER_CS,
+    input [15:0]        BIU_REGISTER_DS,
+    input [15:0]        BIU_REGISTER_RM,
+    input [15:0]        BIU_REGISTER_REG,
+    input [15:0]        BIU_RETURN_DATA
+
+  );
+
+//------------------------------------------------------------------------
+      
+
+// Internal Signals
+
+reg  eu_add_carry;
+reg  eu_add_carry8;
+reg  eu_add_aux_carry;
+reg  eu_add_overflow16;
+reg  eu_add_overflow8;
+reg  eu_stall_pipeline;
+reg  eu_flag_t_d;
+reg  biu_done_d1;
+reg  biu_done_d2;
+reg  eu_tr_latched;
+reg  biu_done_caught;
+reg  eu_biu_req_d1;
+reg  intr_enable_delayed;
+wire eu_prefix_rep;
+wire eu_prefix_repnz;
+wire eu_tf_debounce;
+wire eu_prefix_lock ;
+wire eu_biu_req;
+wire eu_parity;
+wire eu_flag_o;
+wire eu_flag_d;
+wire eu_flag_i;
+wire eu_flag_t; 
+wire eu_flag_s;
+wire eu_flag_z;
+wire eu_flag_a;
+wire eu_flag_p;
+wire eu_flag_c;
+wire eu_opcode_jump_call;
+wire intr_asserted;
+wire eu_jump_boolean;
+reg  [12:0] eu_rom_address;
+reg  [51:0] eu_calling_address;
+reg  [15:0] eu_register_ax;
+reg  [15:0] eu_register_bx;
+reg  [15:0] eu_register_cx;
+reg  [15:0] eu_register_dx;
+reg  [15:0] eu_register_sp;
+reg  [15:0] eu_register_bp;
+reg  [15:0] eu_register_si;
+reg  [15:0] eu_register_di;
+reg  [15:0] eu_flags;
+reg  [15:0] eu_register_r0;
+reg  [15:0] eu_register_r1;
+reg  [15:0] eu_register_r2;
+reg  [15:0] eu_register_r3;
+reg  [15:0] eu_biu_command;
+reg  [15:0] eu_biu_dataout;
+reg  [15:0] eu_alu_last_result;
+wire [15:0] adder_out;
+wire [16:0] carry;
+wire [2:0]  eu_opcode_type;
+wire [3:0]  eu_opcode_dst_sel;
+wire [3:0]  eu_opcode_op0_sel;
+wire [3:0]  eu_opcode_op1_sel;
+wire [15:0] eu_opcode_immediate;
+wire [2:0]  eu_opcode_jump_src;
+wire [3:0]  eu_opcode_jump_cond;
+wire [15:0] system_signals;
+wire [15:0] eu_alu2;
+wire [15:0] eu_alu3;
+wire [15:0] eu_alu4;
+wire [15:0] eu_alu5;
+wire [15:0] eu_alu6;
+wire [15:0] eu_alu7;
+wire [15:0] eu_alu_out;
+wire [15:0] eu_operand0;
+wire [15:0] eu_operand1;
+wire [31:0] eu_rom_data;
+
+
+
+//------------------------------------------------------------------------
+//
+// EU Microcode RAM.  4Kx32 DPRAM
+//
+//------------------------------------------------------------------------                                    
+
+EU4Kx32      EU4Kx32_i (
+  
+  .clka     (CORE_CLK_INT),
+  .addra    (eu_rom_address[11:0]),
+  .douta    (eu_rom_data)
+  
+  );
+
+  
+  
+//------------------------------------------------------------------------
+//
+// Combinationals
+//
+//------------------------------------------------------------------------
+
+assign EU_BIU_COMMAND       = eu_biu_command;
+assign EU_BIU_DATAOUT       = eu_biu_dataout;
+assign EU_REGISTER_R3       = eu_register_r3;
+assign EU_FLAG_I            = intr_enable_delayed;
+assign EU_PREFIX_LOCK       = eu_prefix_lock;
+
+
+// EU ROM opcode decoder
+assign eu_opcode_type       = eu_rom_data[30:28];
+assign eu_opcode_dst_sel    = eu_rom_data[27:24];
+assign eu_opcode_op0_sel    = eu_rom_data[23:20];
+assign eu_opcode_op1_sel    = eu_rom_data[19:16];
+assign eu_opcode_immediate  = eu_rom_data[15:0];
+
+assign eu_opcode_jump_call  = eu_rom_data[24];
+assign eu_opcode_jump_src   = eu_rom_data[22:20];
+assign eu_opcode_jump_cond  = eu_rom_data[19:16];
+
+
+
+assign  eu_operand0 = (eu_opcode_op0_sel==4'h0) ? eu_register_ax  :
+                      (eu_opcode_op0_sel==4'h1) ? eu_register_bx  :
+                      (eu_opcode_op0_sel==4'h2) ? eu_register_cx  :
+                      (eu_opcode_op0_sel==4'h3) ? eu_register_dx  :
+                      (eu_opcode_op0_sel==4'h4) ? eu_register_sp  :
+                      (eu_opcode_op0_sel==4'h5) ? eu_register_bp  :
+                      (eu_opcode_op0_sel==4'h6) ? eu_register_si  :
+                      (eu_opcode_op0_sel==4'h7) ? eu_register_di  :
+                      (eu_opcode_op0_sel==4'h8) ? eu_flags        :
+                      (eu_opcode_op0_sel==4'h9) ? eu_register_r0  :
+                      (eu_opcode_op0_sel==4'hA) ? eu_register_r1  :
+                      (eu_opcode_op0_sel==4'hB) ? eu_register_r2  :
+                      (eu_opcode_op0_sel==4'hC) ? eu_register_r3  :
+                      (eu_opcode_op0_sel==4'hD) ? eu_biu_command  :
+                      (eu_opcode_op0_sel==4'hE) ? system_signals  :
+                                                  16'h0           ;
+
+                                                 
+assign  eu_operand1 = (eu_opcode_op1_sel==4'h0) ? BIU_REGISTER_ES     :
+                      (eu_opcode_op1_sel==4'h1) ? BIU_REGISTER_SS     :
+                      (eu_opcode_op1_sel==4'h2) ? BIU_REGISTER_CS     :
+                      (eu_opcode_op1_sel==4'h3) ? BIU_REGISTER_DS     :
+                      (eu_opcode_op1_sel==4'h4) ? { 8'h00 , PFQ_TOP_BYTE }  :
+                      (eu_opcode_op1_sel==4'h5) ? BIU_REGISTER_RM     :
+                      (eu_opcode_op1_sel==4'h6) ? BIU_REGISTER_REG    :
+                      (eu_opcode_op1_sel==4'h7) ? BIU_RETURN_DATA     :
+                      (eu_opcode_op1_sel==4'h8) ? PFQ_ADDR_OUT        :
+                      (eu_opcode_op1_sel==4'h9) ? eu_register_r0      :
+                      (eu_opcode_op1_sel==4'hA) ? eu_register_r1      :
+                      (eu_opcode_op1_sel==4'hB) ? eu_register_r2      :
+                      (eu_opcode_op1_sel==4'hC) ? eu_register_r3      :
+                      (eu_opcode_op1_sel==4'hD) ? eu_alu_last_result  :  
+                      (eu_opcode_op1_sel==4'hE) ? system_signals      :
+                                                  eu_opcode_immediate ;
+
+
+
+// JUMP condition codes
+assign eu_jump_boolean = (eu_opcode_jump_cond==4'h0)                               ? 1'b1 : // unconditional jump
+                         (eu_opcode_jump_cond==4'h1 && eu_alu_last_result!=16'h0)  ? 1'b1 : 
+                         (eu_opcode_jump_cond==4'h2 && eu_alu_last_result==16'h0)  ? 1'b1 : 
+                                                                                     1'b0 ;
+
+
+                                                  
+// Consolidated system signals
+assign system_signals[13]   = eu_add_carry8;      
+assign system_signals[12]   = BIU_CLK_COUNTER_ZERO;   
+assign system_signals[11]   = eu_add_overflow16;      
+assign system_signals[9]    = eu_add_overflow8;   
+assign system_signals[8]    = eu_tr_latched;
+assign system_signals[7]    = ~PFQ_EMPTY;     
+assign system_signals[6]    = biu_done_caught;    
+assign system_signals[5]    = TEST_N_INT;     
+assign system_signals[4]    = eu_add_aux_carry;   
+assign system_signals[3]    = BIU_NMI_CAUGHT;     
+assign system_signals[2]    = eu_parity;      
+assign system_signals[1]    = intr_asserted;      
+assign system_signals[0]    = eu_add_carry;   
+
+
+assign eu_prefix_repnz      = eu_flags[15];
+assign eu_prefix_rep        = eu_flags[14];
+assign eu_prefix_lock       = eu_flags[13];
+assign BIU_NMI_DEBOUNCE     = eu_flags[12];
+assign eu_flag_o            = eu_flags[11];
+assign eu_flag_d            = eu_flags[10];
+assign eu_flag_i            = eu_flags[9];
+assign eu_flag_t            = eu_flags[8];
+assign eu_flag_s            = eu_flags[7];
+assign eu_flag_z            = eu_flags[6];
+assign eu_tf_debounce       = eu_flags[5];
+assign eu_flag_a            = eu_flags[4];
+assign eu_nmi_pending       = eu_flags[3];
+assign eu_flag_p            = eu_flags[2];
+assign eu_flag_temp         = eu_flags[1];
+assign eu_flag_c            = eu_flags[0];
+
+
+
+// EU ALU Operations
+// ------------------------------------------
+//     eu_alu0 = NOP
+//     eu_alu1 = JUMP
+assign eu_alu2 = adder_out;                                     // ADD
+assign eu_alu3 = { eu_operand0[7:0] , eu_operand0[15:8] };      // BYTESWAP
+assign eu_alu4 = eu_operand0 & eu_operand1;                     // AND
+assign eu_alu5 = eu_operand0 | eu_operand1;                     // OR
+assign eu_alu6 = eu_operand0 ^ eu_operand1;                     // XOR
+assign eu_alu7 = { 1'b0 , eu_operand0[15:1] };                  // SHR
+
+
+
+
+// Mux the ALU operations
+assign eu_alu_out = (eu_opcode_type==3'h2) ? eu_alu2 :   
+                    (eu_opcode_type==3'h3) ? eu_alu3 :
+                    (eu_opcode_type==3'h4) ? eu_alu4 :
+                    (eu_opcode_type==3'h5) ? eu_alu5 :
+                    (eu_opcode_type==3'h6) ? eu_alu6 :
+                    (eu_opcode_type==3'h7) ? eu_alu7 :
+                                             20'hEEEEE;
+
+    
+  
+
+
+// Generate 16-bit full adder for the EU
+assign carry[0] = 1'b0;
+genvar i;
+generate
+  for (i=0; i < 16; i=i+1) 
+    begin : GEN_ADDER
+      assign adder_out[i] =  eu_operand0[i] ^ eu_operand1[i] ^ carry[i];     
+      assign carry[i+1]   = (eu_operand0[i] & eu_operand1[i]) | (eu_operand0[i] & carry[i]) | (eu_operand1[i] & carry[i]);  
+    end
+endgenerate
+
+assign eu_parity = ~(eu_alu_last_result[0]^eu_alu_last_result[1]^eu_alu_last_result[2]^eu_alu_last_result[3]^eu_alu_last_result[4]^eu_alu_last_result[5]^eu_alu_last_result[6]^eu_alu_last_result[7]);
+
+
+assign eu_biu_req                      = eu_biu_command[9];
+
+assign intr_asserted = BIU_INTR & intr_enable_delayed;
+
+
+assign new_instruction = (eu_rom_address[12:8]==5'h01) ? 1'b1 : 1'b0;   
+
+        
+//------------------------------------------------------------------------------------------  
+//
+// EU Microsequencer
+//
+//------------------------------------------------------------------------------------------
+
+always @(posedge CORE_CLK_INT)
+begin : EU_MICROSEQUENCER
+
+  if (RESET_INT==1'b1)
+    begin
+      biu_done_d1 <= 'h0;
+      biu_done_d2 <= 'h0;
+      eu_biu_req_d1 <= 'h0;
+      biu_done_caught <= 'h0;
+      eu_flag_t_d <= 'h0;
+      eu_tr_latched <= 'h0;
+      eu_add_carry <= 'h0;
+      eu_add_carry8 <= 'h0;
+      eu_add_aux_carry <= 'h0;
+      eu_add_overflow16 <= 'h0;
+      eu_add_overflow8 <= 'h0;
+      eu_alu_last_result <= 'h0;
+      eu_register_ax  <= 'h0;
+      eu_register_bx  <= 'h0;
+      eu_register_cx  <= 'h0;
+      eu_register_dx  <= 'h0;
+      eu_register_sp  <= 'h0;
+      eu_register_bp  <= 'h0;
+      eu_register_si  <= 'h0;
+      eu_register_di  <= 'h0;
+      eu_flags <= 'h0;
+      eu_register_r0 <= 'h0;
+      eu_register_r1 <= 'h0;
+      eu_register_r2 <= 'h0;
+      eu_register_r3 <= 'h0;
+      eu_biu_command <= 'h0;
+      eu_biu_dataout <= 'h0;
+      eu_stall_pipeline <= 'h0;
+      eu_rom_address <= 13'h0020;
+      eu_calling_address <= 'h0;
+      intr_enable_delayed <= 1'b0;
+    end
+    
+else    
+  begin     
+  
+    // Delay the INTR enable flag until after the next instruction begins.
+    // No delay when it is disabled.
+    if (eu_flag_i==1'b0)
+      begin
+        intr_enable_delayed <= 1'b0;
+      end
+    else
+    if (new_instruction==1'b1)
+      begin
+        intr_enable_delayed <= eu_flag_i;
+      end
+      
+    // Latch the TF flag on its rising edge.
+    eu_flag_t_d <= eu_flag_t;
+    if (eu_flag_t_d==1'b0 && eu_flag_t==1'b1) 
+      begin
+        eu_tr_latched <= 1'b1;
+      end
+    else if (eu_tf_debounce==1'b1)
+      begin
+        eu_tr_latched <= 1'b0;
+      end
+        
+        
+        
+    // Latch the done bit from the biu.
+    // Debounce it when the request is released.
+    biu_done_d1 <= BIU_DONE;
+    biu_done_d2 <= biu_done_d1;
+    eu_biu_req_d1 <= eu_biu_req;    
+    if (biu_done_d1==1'b0 && BIU_DONE==1'b1)
+      biu_done_caught <= 1'b1;
+    else if (eu_biu_req_d1==1'b1 && eu_biu_req==1'b0)
+      biu_done_caught <= 1'b0;
+            
+
+            
+    // Generate and store flags for addition
+    if (eu_stall_pipeline==1'b0 && eu_opcode_type==3'h2)
+      begin
+        eu_add_carry       <= carry[16];
+        eu_add_carry8      <= carry[8];
+        eu_add_aux_carry   <= carry[4];
+        eu_add_overflow16  <= carry[16] ^ carry[15];
+        eu_add_overflow8   <= carry[8]  ^ carry[7];          
+      end
+
+    
+    // Register writeback   
+    if (eu_stall_pipeline==1'b0 && eu_opcode_type!=3'h0 && eu_opcode_type!=3'h1) 
+      begin       
+        eu_alu_last_result <= eu_alu_out[15:0];
+        case (eu_opcode_dst_sel)  // synthesis parallel_case
+          4'h0 : eu_register_ax   <= eu_alu_out[15:0];
+          4'h1 : eu_register_bx   <= eu_alu_out[15:0];
+          4'h2 : eu_register_cx   <= eu_alu_out[15:0];
+          4'h3 : eu_register_dx   <= eu_alu_out[15:0];
+          4'h4 : eu_register_sp   <= eu_alu_out[15:0];
+          4'h5 : eu_register_bp   <= eu_alu_out[15:0];
+          4'h6 : eu_register_si   <= eu_alu_out[15:0];
+          4'h7 : eu_register_di   <= eu_alu_out[15:0];
+          4'h8 : eu_flags         <= eu_alu_out[15:0];
+          4'h9 : eu_register_r0   <= eu_alu_out[15:0];
+          4'hA : eu_register_r1   <= eu_alu_out[15:0];
+          4'hB : eu_register_r2   <= eu_alu_out[15:0];
+          4'hC : eu_register_r3   <= eu_alu_out[15:0];
+          4'hD : eu_biu_command   <= eu_alu_out[15:0];
+          //4'hE : ;             
+          4'hF : eu_biu_dataout   <= eu_alu_out[15:0];
+          default :  ;
+        endcase
+    end
+
+
+    // JUMP Opcode
+    if (eu_stall_pipeline==1'b0 && eu_opcode_type==3'h1 && eu_jump_boolean==1'b1)
+      begin
+        eu_stall_pipeline <= 1'b1;
+          
+         // For subroutine CALLs, store next opcode address
+        if (eu_opcode_jump_call==1'b1)
+          begin
+            eu_calling_address[51:0] <= {eu_calling_address[38:0] , eu_rom_address[12:0] };  // 4 deep calling addresses
+          end           
+
+        case (eu_opcode_jump_src)  // synthesis parallel_case
+          3'h0 : eu_rom_address <= eu_opcode_immediate[12:0];
+          3'h1 : eu_rom_address <= { 4'b0 , 1'b1 , PFQ_TOP_BYTE }; // If only used for primary opcode jump, maybe make fixed prepend rather than immediate value prepend?
+          3'h2 : eu_rom_address <= { eu_opcode_immediate[4:0], PFQ_TOP_BYTE[7:6] , PFQ_TOP_BYTE[2:0] , 3'b000 }; // Rearranged mod_reg_rm byte - imm,MOD,RM,000
+          3'h3 : begin
+                   eu_rom_address <= eu_calling_address[12:0];
+                   eu_calling_address[38:0] <= eu_calling_address[51:13];
+                 end
+          3'h4 : eu_rom_address <= { eu_opcode_immediate[7:0],  eu_biu_dataout[3:0] , 1'b0 };  // Jump table for EA register fetch decoding.  Jump Addresses decoded from biu_dataout.
+          3'h5 : eu_rom_address <= { eu_opcode_immediate[6:0],  eu_biu_dataout[3:0] , 2'b00 }; // Jump table for EA register writeback decoding.  Jump Addresses decoded from biu_dataout.
+          3'h6 : eu_rom_address <= { eu_opcode_immediate[12:3], eu_biu_dataout[5:3] };         // Jump table for instructions that share same opcode and decode using the REG field.
+                     
+          default :  ;
+        endcase 
+      end
+                
+    else
+      begin
+        eu_stall_pipeline <= 1'b0; // Debounce the pipeline stall
+        eu_rom_address <= eu_rom_address + 1'b1; 
+      end
+   
+end
+end // EU Microsequencer
+
+
+
+ 
+endmodule // eu.v
diff --git a/MCL86jr/FPGA/usage_statistics_webtalk.html b/MCL86jr/FPGA/usage_statistics_webtalk.html
new file mode 100644
index 0000000..d7f96a6
--- /dev/null
+++ b/MCL86jr/FPGA/usage_statistics_webtalk.html
@@ -0,0 +1,98 @@
+<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>&nbsp;<BR><HR>&nbsp;<BR>
+<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>Software Version and Target Device</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD>
+<TD><xtag-property name="ProductVersion">ISE:14.7</xtag-property><xtag-property name="ProductConfiguration"> (iMPACT)</xtag-property><xtag-property name="BuildVersion"> - P.20131013</xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B>Target Family:</B></TD>
+<TD><xtag-property name="TargetFamily">Single</xtag-property></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>OS Platform:</B></TD>
+<TD><xtag-property name="OSPlatform">NT64</xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD><xtag-property name="TargetDevice">Single</xtag-property></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
+<TD><xtag-property name="RandomID">6f5550ea45af4678971d9a741e8cb7b1</xtag-property>.<xtag-property name="ProjectID">217ed4b88cbc473995cacfa1d22a759f</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
+<TD><xtag-property name="TargetPackage"></xtag-property></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Registration ID</B></TD>
+<TD><xtag-property name="RegistrationID">iMPACT</xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B>Target Speed:</B></TD>
+<TD><xtag-property name="TargetSpeed"></xtag-property></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
+<TD><xtag-property name="Date Generated">2020-11-07T22:26:24</xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
+<TD><xtag-property name="ToolFlow">IMPACT</xtag-property></TD>
+</TR>
+</TABLE>
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<xtag-section name="iMPACT Boundary Scan Mode">
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>iMPACT Boundary Scan Mode</B></TD></TR>
+<TR ALIGN=CENTER><TD COLSPAN=4><B>Chain Summary</B></TD></TR>
+<TR>
+<TD><xtag-property-name>Number of device</xtag-property-name>=<xtag-property-value>1</xtag-property-value></TD>
+<TD><xtag-property-name>Number of Xilinx device</xtag-property-name>=<xtag-property-value>1</xtag-property-value></TD>
+<TD><xtag-property-name>Number of Non-Xilinx device</xtag-property-name>=<xtag-property-value>0</xtag-property-value></TD>
+<TR ALIGN=CENTER><TD COLSPAN=4><B>Chain Description</B></TD></TR>
+<TR>
+<TD><xtag-property-name>Device1</xtag-property-name>=<xtag-property-value>spartan6</xtag-property-value></TD>
+<TD><xtag-property-name>Part1</xtag-property-name>=<xtag-property-value>xc6slx9</xtag-property-value></TD>
+<TD><xtag-property-name>Device1</xtag-property-name>=<xtag-property-value>SPI FLASH</xtag-property-value></TD>
+<TD><xtag-property-name>Part1</xtag-property-name>=<xtag-property-value>W25Q128FV</xtag-property-value></TD>
+
+</TR><TR><TD><xtag-property-name>Data Width</xtag-property-name>=<xtag-property-value>x1</xtag-property-value></TD>
+<TR ALIGN=CENTER><TD COLSPAN=4><B>Boundary Scan Operations Statistics</B></TD></TR>
+<TR>
+<TD><xtag-property-name>BSCAN Operation</xtag-property-name>=<xtag-property-value>Program -p 0 </xtag-property-value></TD>
+<TD><xtag-property-name>BSCAN Operation</xtag-property-name>=<xtag-property-value>Program -p 0 -dataWidth 1 -spionly -e -v -loadfpga </xtag-property-value></TD>
+<TR ALIGN=CENTER><TD COLSPAN=4><B>Cable Summary</B></TD></TR>
+<TR>
+<TD><xtag-property-name>Cable Type</xtag-property-name>=<xtag-property-value>Platform Cable USB II</xtag-property-value></TD>
+<TD><xtag-property-name>Cable Speed</xtag-property-name>=<xtag-property-value>6 MHz</xtag-property-value></TD>
+<TD><xtag-property-name>Port</xtag-property-name>=<xtag-property-value>usb-hs</xtag-property-value></TD>
+<TD><xtag-property-name>Local_Server_Mode</xtag-property-name>=<xtag-property-value>Local</xtag-property-value></TD>
+<TR>
+</TR></xtag-section></TABLE>
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<xtag-section name="iMPACT Project Info">
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=2><B>iMPACT Project Info</B></TD></TR>
+<TR>
+<TD><xtag-property-name>Use Project File</xtag-property-name>=<xtag-property-value>Yes</xtag-property-value></TD>
+<TD><xtag-property-name>Project Entry</xtag-property-name>=<xtag-property-value>ise</xtag-property-value></TD>
+
+</TR><TR><TD><xtag-property-name>OS Name</xtag-property-name>=<xtag-property-value>Microsoft Windows 7 (64 Bit)</xtag-property-value></TD>
+<TD><xtag-property-name>User Lic. Info</xtag-property-name>=<xtag-property-value>174191283_174191284_0_212</xtag-property-value></TD>
+</TR></xtag-section></TABLE>
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<xtag-section name="iMPACT SPI FLASH File Generation Mode">
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>iMPACT SPI FLASH File Generation Mode</B></TD></TR>
+<TR ALIGN=CENTER><TD COLSPAN=4><B>FLASH File Summary</B></TD></TR>
+<TR>
+<TD><xtag-property-name>Number of FLASH</xtag-property-name>=<xtag-property-value>1</xtag-property-value></TD>
+<TD><xtag-property-name>FLASH Data Width</xtag-property-name>=<xtag-property-value>8</xtag-property-value></TD>
+<TD><xtag-property-name>FLASH</xtag-property-name>=<xtag-property-value>1</xtag-property-value></TD>
+<TD><xtag-property-name>FLASH Size</xtag-property-name>=<xtag-property-value>16M Byte</xtag-property-value></TD>
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diff --git a/MCL86jr/FPGA/webtalk.log b/MCL86jr/FPGA/webtalk.log
new file mode 100644
index 0000000..23e4301
--- /dev/null
+++ b/MCL86jr/FPGA/webtalk.log
@@ -0,0 +1,16 @@
+Release 14.7 - WebTalk (P.20131013)
+Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
+
+Project Information
+--------------------
+ProjectID=217ed4b88cbc473995cacfa1d22a759f
+ProjectIteration=1
+
+WebTalk Summary
+----------------
+INFO:WebTalk:2 - WebTalk is enabled.
+
+INFO:WebTalk:8 - WebTalk Install setting is ON.
+INFO:WebTalk:6 - WebTalk User setting is ON.
+
+INFO:WebTalk:5 - C:/MCL/MCL86/MCL86jr/usage_statistics_webtalk.html WebTalk report has not been sent to Xilinx.  Please check your network and proxy settings.  For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/14.7/ISE_DS/ISE/data/reports/webtalk_introduction.html
diff --git a/MCL86jr/FPGA/webtalk_impact.xml b/MCL86jr/FPGA/webtalk_impact.xml
new file mode 100644
index 0000000..9aea83e
--- /dev/null
+++ b/MCL86jr/FPGA/webtalk_impact.xml
@@ -0,0 +1,61 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="impact" timeStamp="Sat Nov 07 22:26:22 2020">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="217ed4b88cbc473995cacfa1d22a759f"/>
+<property name="ProjectIteration" value="1"/>
+</section>
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+<property name="Use Project File" value="Yes"/>
+<property name="Project Entry" value="ise"/>
+<property name="OS Name" value="Microsoft Windows 7 (64 Bit)"/>
+<property name="User Lic. Info" value="174191283_174191284_0_212"/>
+</section>
+<section name="iMPACT Boundary Scan Mode" visible="true">
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+<property name="Number of Xilinx device" value="1"/>
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+<property name="Part1" value="xc6slx9"/>
+<property name="Device1" value="SPI FLASH"/>
+<property name="Part1" value="W25Q128FV"/>
+<property name="Data Width" value="x1"/>
+</item>
+<item name="Boundary Scan Operations Statistics">
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0 -dataWidth 1 -spionly -e -v -loadfpga
+"/>
+</item>
+<item name="Cable Summary">
+<property name="Cable Type" value="Platform Cable USB II"/>
+<property name="Cable Speed" value="6 MHz"/>
+<property name="Port" value="usb-hs"/>
+<property name="Local_Server_Mode" value="Local"/>
+</item>
+</section>
+<section name="iMPACT SPI FLASH File Generation Mode" visible="true">
+<item name="FLASH File Summary">
+<property name="Number of FLASH" value="1"/>
+<property name="FLASH Data Width" value="8"/>
+<property name="FLASH" value="1"/>
+<property name="FLASH Size" value="16M Byte"/>
+</item>
+<item name="Revision_Data File Summary">
+<property name="Number of Revision" value="1"/>
+<property name="Number of Data File" value="0"/>
+</item>
+<item name="Revision 1">
+<property name="Number of device" value="1"/>
+<property name="Device1" value="spartan6"/>
+<property name="Part1" value="xc6slx9"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-B_Cu.gbr b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-B_Cu.gbr
new file mode 100644
index 0000000..4108218
--- /dev/null
+++ b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-B_Cu.gbr
@@ -0,0 +1,8586 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5)-3*
+G04 #@! TF.CreationDate,2020-10-03T21:18:42-07:00*
+G04 #@! TF.ProjectId,MCL86jr,4d434c38-366a-4722-9e6b-696361645f70,rev?*
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+%FSLAX46Y46*%
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+X49631500Y-6944400D01*
+X49645958Y-6945110D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X48675958Y-6945110D02*
+G01*
+X48690276Y-6947234D01*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X32876758Y-22669710D02*
+G01*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X32876758Y-21699710D02*
+G01*
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+X32862300Y-21699000D01*
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+G37*
+G04 #@! TD.AperFunction*
+D13*
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+X3545600Y-51931600D03*
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+X3545600Y-8751600D03*
+X18785600Y-54471600D03*
+D14*
+X3545600Y-6211600D03*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+D12*
+G36*
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+G01*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
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+G01*
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+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X44001958Y-33058310D02*
+G01*
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+G04 #@! TD.AperFunction*
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+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
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+X50460642Y-10726910D01*
+X50475100Y-10726200D01*
+X50820100Y-10726200D01*
+X50834558Y-10726910D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X50834558Y-11696910D02*
+G01*
+X50848876Y-11699034D01*
+X50862917Y-11702551D01*
+X50876546Y-11707428D01*
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+X50924398Y-11739402D01*
+X50934119Y-11750127D01*
+X50942742Y-11761753D01*
+X50950183Y-11774169D01*
+X50956372Y-11787254D01*
+X50961249Y-11800883D01*
+X50964766Y-11814924D01*
+X50966890Y-11829242D01*
+X50967600Y-11843700D01*
+X50967600Y-12138700D01*
+X50966890Y-12153158D01*
+X50964766Y-12167476D01*
+X50961249Y-12181517D01*
+X50956372Y-12195146D01*
+X50950183Y-12208231D01*
+X50942742Y-12220647D01*
+X50934119Y-12232273D01*
+X50924398Y-12242998D01*
+X50913673Y-12252719D01*
+X50902047Y-12261342D01*
+X50889631Y-12268783D01*
+X50876546Y-12274972D01*
+X50862917Y-12279849D01*
+X50848876Y-12283366D01*
+X50834558Y-12285490D01*
+X50820100Y-12286200D01*
+X50475100Y-12286200D01*
+X50460642Y-12285490D01*
+X50446324Y-12283366D01*
+X50432283Y-12279849D01*
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+X50393153Y-12261342D01*
+X50381527Y-12252719D01*
+X50370802Y-12242998D01*
+X50361081Y-12232273D01*
+X50352458Y-12220647D01*
+X50345017Y-12208231D01*
+X50338828Y-12195146D01*
+X50333951Y-12181517D01*
+X50330434Y-12167476D01*
+X50328310Y-12153158D01*
+X50327600Y-12138700D01*
+X50327600Y-11843700D01*
+X50328310Y-11829242D01*
+X50330434Y-11814924D01*
+X50333951Y-11800883D01*
+X50338828Y-11787254D01*
+X50345017Y-11774169D01*
+X50352458Y-11761753D01*
+X50361081Y-11750127D01*
+X50370802Y-11739402D01*
+X50381527Y-11729681D01*
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+X50418654Y-11707428D01*
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+X50446324Y-11699034D01*
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+X50475100Y-11696200D01*
+X50820100Y-11696200D01*
+X50834558Y-11696910D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X23224758Y-13063710D02*
+G01*
+X23239076Y-13065834D01*
+X23253117Y-13069351D01*
+X23266746Y-13074228D01*
+X23279831Y-13080417D01*
+X23292247Y-13087858D01*
+X23303873Y-13096481D01*
+X23314598Y-13106202D01*
+X23324319Y-13116927D01*
+X23332942Y-13128553D01*
+X23340383Y-13140969D01*
+X23346572Y-13154054D01*
+X23351449Y-13167683D01*
+X23354966Y-13181724D01*
+X23357090Y-13196042D01*
+X23357800Y-13210500D01*
+X23357800Y-13505500D01*
+X23357090Y-13519958D01*
+X23354966Y-13534276D01*
+X23351449Y-13548317D01*
+X23346572Y-13561946D01*
+X23340383Y-13575031D01*
+X23332942Y-13587447D01*
+X23324319Y-13599073D01*
+X23314598Y-13609798D01*
+X23303873Y-13619519D01*
+X23292247Y-13628142D01*
+X23279831Y-13635583D01*
+X23266746Y-13641772D01*
+X23253117Y-13646649D01*
+X23239076Y-13650166D01*
+X23224758Y-13652290D01*
+X23210300Y-13653000D01*
+X22865300Y-13653000D01*
+X22850842Y-13652290D01*
+X22836524Y-13650166D01*
+X22822483Y-13646649D01*
+X22808854Y-13641772D01*
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+X22783353Y-13628142D01*
+X22771727Y-13619519D01*
+X22761002Y-13609798D01*
+X22751281Y-13599073D01*
+X22742658Y-13587447D01*
+X22735217Y-13575031D01*
+X22729028Y-13561946D01*
+X22724151Y-13548317D01*
+X22720634Y-13534276D01*
+X22718510Y-13519958D01*
+X22717800Y-13505500D01*
+X22717800Y-13210500D01*
+X22718510Y-13196042D01*
+X22720634Y-13181724D01*
+X22724151Y-13167683D01*
+X22729028Y-13154054D01*
+X22735217Y-13140969D01*
+X22742658Y-13128553D01*
+X22751281Y-13116927D01*
+X22761002Y-13106202D01*
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+X22808854Y-13074228D01*
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+X22865300Y-13063000D01*
+X23210300Y-13063000D01*
+X23224758Y-13063710D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X23224758Y-14033710D02*
+G01*
+X23239076Y-14035834D01*
+X23253117Y-14039351D01*
+X23266746Y-14044228D01*
+X23279831Y-14050417D01*
+X23292247Y-14057858D01*
+X23303873Y-14066481D01*
+X23314598Y-14076202D01*
+X23324319Y-14086927D01*
+X23332942Y-14098553D01*
+X23340383Y-14110969D01*
+X23346572Y-14124054D01*
+X23351449Y-14137683D01*
+X23354966Y-14151724D01*
+X23357090Y-14166042D01*
+X23357800Y-14180500D01*
+X23357800Y-14475500D01*
+X23357090Y-14489958D01*
+X23354966Y-14504276D01*
+X23351449Y-14518317D01*
+X23346572Y-14531946D01*
+X23340383Y-14545031D01*
+X23332942Y-14557447D01*
+X23324319Y-14569073D01*
+X23314598Y-14579798D01*
+X23303873Y-14589519D01*
+X23292247Y-14598142D01*
+X23279831Y-14605583D01*
+X23266746Y-14611772D01*
+X23253117Y-14616649D01*
+X23239076Y-14620166D01*
+X23224758Y-14622290D01*
+X23210300Y-14623000D01*
+X22865300Y-14623000D01*
+X22850842Y-14622290D01*
+X22836524Y-14620166D01*
+X22822483Y-14616649D01*
+X22808854Y-14611772D01*
+X22795769Y-14605583D01*
+X22783353Y-14598142D01*
+X22771727Y-14589519D01*
+X22761002Y-14579798D01*
+X22751281Y-14569073D01*
+X22742658Y-14557447D01*
+X22735217Y-14545031D01*
+X22729028Y-14531946D01*
+X22724151Y-14518317D01*
+X22720634Y-14504276D01*
+X22718510Y-14489958D01*
+X22717800Y-14475500D01*
+X22717800Y-14180500D01*
+X22718510Y-14166042D01*
+X22720634Y-14151724D01*
+X22724151Y-14137683D01*
+X22729028Y-14124054D01*
+X22735217Y-14110969D01*
+X22742658Y-14098553D01*
+X22751281Y-14086927D01*
+X22761002Y-14076202D01*
+X22771727Y-14066481D01*
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+X22795769Y-14050417D01*
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+X22865300Y-14033000D01*
+X23210300Y-14033000D01*
+X23224758Y-14033710D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X48446958Y-32342310D02*
+G01*
+X48461276Y-32344434D01*
+X48475317Y-32347951D01*
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+X48502031Y-32359017D01*
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+X48526073Y-32375081D01*
+X48536798Y-32384802D01*
+X48546519Y-32395527D01*
+X48555142Y-32407153D01*
+X48562583Y-32419569D01*
+X48568772Y-32432654D01*
+X48573649Y-32446283D01*
+X48577166Y-32460324D01*
+X48579290Y-32474642D01*
+X48580000Y-32489100D01*
+X48580000Y-32784100D01*
+X48579290Y-32798558D01*
+X48577166Y-32812876D01*
+X48573649Y-32826917D01*
+X48568772Y-32840546D01*
+X48562583Y-32853631D01*
+X48555142Y-32866047D01*
+X48546519Y-32877673D01*
+X48536798Y-32888398D01*
+X48526073Y-32898119D01*
+X48514447Y-32906742D01*
+X48502031Y-32914183D01*
+X48488946Y-32920372D01*
+X48475317Y-32925249D01*
+X48461276Y-32928766D01*
+X48446958Y-32930890D01*
+X48432500Y-32931600D01*
+X48087500Y-32931600D01*
+X48073042Y-32930890D01*
+X48058724Y-32928766D01*
+X48044683Y-32925249D01*
+X48031054Y-32920372D01*
+X48017969Y-32914183D01*
+X48005553Y-32906742D01*
+X47993927Y-32898119D01*
+X47983202Y-32888398D01*
+X47973481Y-32877673D01*
+X47964858Y-32866047D01*
+X47957417Y-32853631D01*
+X47951228Y-32840546D01*
+X47946351Y-32826917D01*
+X47942834Y-32812876D01*
+X47940710Y-32798558D01*
+X47940000Y-32784100D01*
+X47940000Y-32489100D01*
+X47940710Y-32474642D01*
+X47942834Y-32460324D01*
+X47946351Y-32446283D01*
+X47951228Y-32432654D01*
+X47957417Y-32419569D01*
+X47964858Y-32407153D01*
+X47973481Y-32395527D01*
+X47983202Y-32384802D01*
+X47993927Y-32375081D01*
+X48005553Y-32366458D01*
+X48017969Y-32359017D01*
+X48031054Y-32352828D01*
+X48044683Y-32347951D01*
+X48058724Y-32344434D01*
+X48073042Y-32342310D01*
+X48087500Y-32341600D01*
+X48432500Y-32341600D01*
+X48446958Y-32342310D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X48446958Y-33312310D02*
+G01*
+X48461276Y-33314434D01*
+X48475317Y-33317951D01*
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+X48514447Y-33336458D01*
+X48526073Y-33345081D01*
+X48536798Y-33354802D01*
+X48546519Y-33365527D01*
+X48555142Y-33377153D01*
+X48562583Y-33389569D01*
+X48568772Y-33402654D01*
+X48573649Y-33416283D01*
+X48577166Y-33430324D01*
+X48579290Y-33444642D01*
+X48580000Y-33459100D01*
+X48580000Y-33754100D01*
+X48579290Y-33768558D01*
+X48577166Y-33782876D01*
+X48573649Y-33796917D01*
+X48568772Y-33810546D01*
+X48562583Y-33823631D01*
+X48555142Y-33836047D01*
+X48546519Y-33847673D01*
+X48536798Y-33858398D01*
+X48526073Y-33868119D01*
+X48514447Y-33876742D01*
+X48502031Y-33884183D01*
+X48488946Y-33890372D01*
+X48475317Y-33895249D01*
+X48461276Y-33898766D01*
+X48446958Y-33900890D01*
+X48432500Y-33901600D01*
+X48087500Y-33901600D01*
+X48073042Y-33900890D01*
+X48058724Y-33898766D01*
+X48044683Y-33895249D01*
+X48031054Y-33890372D01*
+X48017969Y-33884183D01*
+X48005553Y-33876742D01*
+X47993927Y-33868119D01*
+X47983202Y-33858398D01*
+X47973481Y-33847673D01*
+X47964858Y-33836047D01*
+X47957417Y-33823631D01*
+X47951228Y-33810546D01*
+X47946351Y-33796917D01*
+X47942834Y-33782876D01*
+X47940710Y-33768558D01*
+X47940000Y-33754100D01*
+X47940000Y-33459100D01*
+X47940710Y-33444642D01*
+X47942834Y-33430324D01*
+X47946351Y-33416283D01*
+X47951228Y-33402654D01*
+X47957417Y-33389569D01*
+X47964858Y-33377153D01*
+X47973481Y-33365527D01*
+X47983202Y-33354802D01*
+X47993927Y-33345081D01*
+X48005553Y-33336458D01*
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+X48087500Y-33311600D01*
+X48432500Y-33311600D01*
+X48446958Y-33312310D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X24187958Y-29119310D02*
+G01*
+X24202276Y-29121434D01*
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+X24296142Y-29184153D01*
+X24303583Y-29196569D01*
+X24309772Y-29209654D01*
+X24314649Y-29223283D01*
+X24318166Y-29237324D01*
+X24320290Y-29251642D01*
+X24321000Y-29266100D01*
+X24321000Y-29611100D01*
+X24320290Y-29625558D01*
+X24318166Y-29639876D01*
+X24314649Y-29653917D01*
+X24309772Y-29667546D01*
+X24303583Y-29680631D01*
+X24296142Y-29693047D01*
+X24287519Y-29704673D01*
+X24277798Y-29715398D01*
+X24267073Y-29725119D01*
+X24255447Y-29733742D01*
+X24243031Y-29741183D01*
+X24229946Y-29747372D01*
+X24216317Y-29752249D01*
+X24202276Y-29755766D01*
+X24187958Y-29757890D01*
+X24173500Y-29758600D01*
+X23878500Y-29758600D01*
+X23864042Y-29757890D01*
+X23849724Y-29755766D01*
+X23835683Y-29752249D01*
+X23822054Y-29747372D01*
+X23808969Y-29741183D01*
+X23796553Y-29733742D01*
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+X23774202Y-29715398D01*
+X23764481Y-29704673D01*
+X23755858Y-29693047D01*
+X23748417Y-29680631D01*
+X23742228Y-29667546D01*
+X23737351Y-29653917D01*
+X23733834Y-29639876D01*
+X23731710Y-29625558D01*
+X23731000Y-29611100D01*
+X23731000Y-29266100D01*
+X23731710Y-29251642D01*
+X23733834Y-29237324D01*
+X23737351Y-29223283D01*
+X23742228Y-29209654D01*
+X23748417Y-29196569D01*
+X23755858Y-29184153D01*
+X23764481Y-29172527D01*
+X23774202Y-29161802D01*
+X23784927Y-29152081D01*
+X23796553Y-29143458D01*
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+X23878500Y-29118600D01*
+X24173500Y-29118600D01*
+X24187958Y-29119310D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X25157958Y-29119310D02*
+G01*
+X25172276Y-29121434D01*
+X25186317Y-29124951D01*
+X25199946Y-29129828D01*
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+X25237073Y-29152081D01*
+X25247798Y-29161802D01*
+X25257519Y-29172527D01*
+X25266142Y-29184153D01*
+X25273583Y-29196569D01*
+X25279772Y-29209654D01*
+X25284649Y-29223283D01*
+X25288166Y-29237324D01*
+X25290290Y-29251642D01*
+X25291000Y-29266100D01*
+X25291000Y-29611100D01*
+X25290290Y-29625558D01*
+X25288166Y-29639876D01*
+X25284649Y-29653917D01*
+X25279772Y-29667546D01*
+X25273583Y-29680631D01*
+X25266142Y-29693047D01*
+X25257519Y-29704673D01*
+X25247798Y-29715398D01*
+X25237073Y-29725119D01*
+X25225447Y-29733742D01*
+X25213031Y-29741183D01*
+X25199946Y-29747372D01*
+X25186317Y-29752249D01*
+X25172276Y-29755766D01*
+X25157958Y-29757890D01*
+X25143500Y-29758600D01*
+X24848500Y-29758600D01*
+X24834042Y-29757890D01*
+X24819724Y-29755766D01*
+X24805683Y-29752249D01*
+X24792054Y-29747372D01*
+X24778969Y-29741183D01*
+X24766553Y-29733742D01*
+X24754927Y-29725119D01*
+X24744202Y-29715398D01*
+X24734481Y-29704673D01*
+X24725858Y-29693047D01*
+X24718417Y-29680631D01*
+X24712228Y-29667546D01*
+X24707351Y-29653917D01*
+X24703834Y-29639876D01*
+X24701710Y-29625558D01*
+X24701000Y-29611100D01*
+X24701000Y-29266100D01*
+X24701710Y-29251642D01*
+X24703834Y-29237324D01*
+X24707351Y-29223283D01*
+X24712228Y-29209654D01*
+X24718417Y-29196569D01*
+X24725858Y-29184153D01*
+X24734481Y-29172527D01*
+X24744202Y-29161802D01*
+X24754927Y-29152081D01*
+X24766553Y-29143458D01*
+X24778969Y-29136017D01*
+X24792054Y-29129828D01*
+X24805683Y-29124951D01*
+X24819724Y-29121434D01*
+X24834042Y-29119310D01*
+X24848500Y-29118600D01*
+X25143500Y-29118600D01*
+X25157958Y-29119310D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X37550358Y-1379710D02*
+G01*
+X37564676Y-1381834D01*
+X37578717Y-1385351D01*
+X37592346Y-1390228D01*
+X37605431Y-1396417D01*
+X37617847Y-1403858D01*
+X37629473Y-1412481D01*
+X37640198Y-1422202D01*
+X37649919Y-1432927D01*
+X37658542Y-1444553D01*
+X37665983Y-1456969D01*
+X37672172Y-1470054D01*
+X37677049Y-1483683D01*
+X37680566Y-1497724D01*
+X37682690Y-1512042D01*
+X37683400Y-1526500D01*
+X37683400Y-1821500D01*
+X37682690Y-1835958D01*
+X37680566Y-1850276D01*
+X37677049Y-1864317D01*
+X37672172Y-1877946D01*
+X37665983Y-1891031D01*
+X37658542Y-1903447D01*
+X37649919Y-1915073D01*
+X37640198Y-1925798D01*
+X37629473Y-1935519D01*
+X37617847Y-1944142D01*
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+X37550358Y-1379710D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X37550358Y-2349710D02*
+G01*
+X37564676Y-2351834D01*
+X37578717Y-2355351D01*
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+X37629473Y-2382481D01*
+X37640198Y-2392202D01*
+X37649919Y-2402927D01*
+X37658542Y-2414553D01*
+X37665983Y-2426969D01*
+X37672172Y-2440054D01*
+X37677049Y-2453683D01*
+X37680566Y-2467724D01*
+X37682690Y-2482042D01*
+X37683400Y-2496500D01*
+X37683400Y-2791500D01*
+X37682690Y-2805958D01*
+X37680566Y-2820276D01*
+X37677049Y-2834317D01*
+X37672172Y-2847946D01*
+X37665983Y-2861031D01*
+X37658542Y-2873447D01*
+X37649919Y-2885073D01*
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+X37535900Y-2349000D01*
+X37550358Y-2349710D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X38515558Y-1379710D02*
+G01*
+X38529876Y-1381834D01*
+X38543917Y-1385351D01*
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+X38583047Y-1403858D01*
+X38594673Y-1412481D01*
+X38605398Y-1422202D01*
+X38615119Y-1432927D01*
+X38623742Y-1444553D01*
+X38631183Y-1456969D01*
+X38637372Y-1470054D01*
+X38642249Y-1483683D01*
+X38645766Y-1497724D01*
+X38647890Y-1512042D01*
+X38648600Y-1526500D01*
+X38648600Y-1821500D01*
+X38647890Y-1835958D01*
+X38645766Y-1850276D01*
+X38642249Y-1864317D01*
+X38637372Y-1877946D01*
+X38631183Y-1891031D01*
+X38623742Y-1903447D01*
+X38615119Y-1915073D01*
+X38605398Y-1925798D01*
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+X38501100Y-1379000D01*
+X38515558Y-1379710D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X38515558Y-2349710D02*
+G01*
+X38529876Y-2351834D01*
+X38543917Y-2355351D01*
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+X38615119Y-2402927D01*
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+X38631183Y-2426969D01*
+X38637372Y-2440054D01*
+X38642249Y-2453683D01*
+X38645766Y-2467724D01*
+X38647890Y-2482042D01*
+X38648600Y-2496500D01*
+X38648600Y-2791500D01*
+X38647890Y-2805958D01*
+X38645766Y-2820276D01*
+X38642249Y-2834317D01*
+X38637372Y-2847946D01*
+X38631183Y-2861031D01*
+X38623742Y-2873447D01*
+X38615119Y-2885073D01*
+X38605398Y-2895798D01*
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+X38501100Y-2349000D01*
+X38515558Y-2349710D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X39506158Y-1379710D02*
+G01*
+X39520476Y-1381834D01*
+X39534517Y-1385351D01*
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+X39573647Y-1403858D01*
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+X39595998Y-1422202D01*
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+X39627972Y-1470054D01*
+X39632849Y-1483683D01*
+X39636366Y-1497724D01*
+X39638490Y-1512042D01*
+X39639200Y-1526500D01*
+X39639200Y-1821500D01*
+X39638490Y-1835958D01*
+X39636366Y-1850276D01*
+X39632849Y-1864317D01*
+X39627972Y-1877946D01*
+X39621783Y-1891031D01*
+X39614342Y-1903447D01*
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+X39146700Y-1379000D01*
+X39491700Y-1379000D01*
+X39506158Y-1379710D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X39506158Y-2349710D02*
+G01*
+X39520476Y-2351834D01*
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+X39614342Y-2873447D01*
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+X39491700Y-2349000D01*
+X39506158Y-2349710D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X40471358Y-1379710D02*
+G01*
+X40485676Y-1381834D01*
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+X40111900Y-1379000D01*
+X40456900Y-1379000D01*
+X40471358Y-1379710D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X40471358Y-2349710D02*
+G01*
+X40485676Y-2351834D01*
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+X40603690Y-2805958D01*
+X40601566Y-2820276D01*
+X40598049Y-2834317D01*
+X40593172Y-2847946D01*
+X40586983Y-2861031D01*
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+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
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+G01*
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+G04 #@! TD.AperFunction*
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+G36*
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+G01*
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+G04 #@! TD.AperFunction*
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+G36*
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+G01*
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+G04 #@! TD.AperFunction*
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+G04 #@! TD.AperFunction*
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+G36*
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+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
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+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
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diff --git a/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-B_Mask.gbr b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-B_Mask.gbr
new file mode 100644
index 0000000..0429f86
--- /dev/null
+++ b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-B_Mask.gbr
@@ -0,0 +1,6008 @@
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diff --git a/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-B_Paste.gbr b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-B_Paste.gbr
new file mode 100644
index 0000000..8516265
--- /dev/null
+++ b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-B_Paste.gbr
@@ -0,0 +1,7251 @@
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diff --git a/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-B_SilkS.gbr b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-B_SilkS.gbr
new file mode 100644
index 0000000..6769a1f
--- /dev/null
+++ b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-B_SilkS.gbr
@@ -0,0 +1,1780 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5)-3*
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diff --git a/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-Edge_Cuts.gbr b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-Edge_Cuts.gbr
new file mode 100644
index 0000000..de885cf
--- /dev/null
+++ b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-Edge_Cuts.gbr
@@ -0,0 +1,23 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5)-3*
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+G04 Created by KiCad (PCBNEW (5.1.5)-3) date 2020-10-03 21:18:42*
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diff --git a/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-F_Cu.gbr b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-F_Cu.gbr
new file mode 100644
index 0000000..f5ce304
--- /dev/null
+++ b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-F_Cu.gbr
@@ -0,0 +1,14070 @@
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+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
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+G01*
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+G04 #@! TD.AperFunction*
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+G36*
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+G01*
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+G04 #@! TD.AperFunction*
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+G36*
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+G01*
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+G36*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
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+G01*
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+G04 #@! TD.AperFunction*
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+G36*
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+G01*
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+G01*
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+G04 #@! TD.AperFunction*
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+G04 #@! TD.AperFunction*
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+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
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+G01*
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+G36*
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+G01*
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+G36*
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+G04 #@! TD.AperFunction*
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+G04 #@! TD.AperFunction*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X48467151Y-14150361D02*
+G01*
+X48474432Y-14151441D01*
+X48481571Y-14153229D01*
+X48488501Y-14155709D01*
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+X48525944Y-14189645D01*
+X48529091Y-14196299D01*
+X48531571Y-14203229D01*
+X48533359Y-14210368D01*
+X48534439Y-14217649D01*
+X48534800Y-14225000D01*
+X48534800Y-14375000D01*
+X48534439Y-14382351D01*
+X48533359Y-14389632D01*
+X48531571Y-14396771D01*
+X48529091Y-14403701D01*
+X48525944Y-14410355D01*
+X48522160Y-14416668D01*
+X48517776Y-14422579D01*
+X48512833Y-14428033D01*
+X48507379Y-14432976D01*
+X48501468Y-14437360D01*
+X48495155Y-14441144D01*
+X48488501Y-14444291D01*
+X48481571Y-14446771D01*
+X48474432Y-14448559D01*
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+X48459800Y-14450000D01*
+X47134800Y-14450000D01*
+X47127449Y-14449639D01*
+X47120168Y-14448559D01*
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+X48459800Y-14150000D01*
+X48467151Y-14150361D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X48467151Y-14650361D02*
+G01*
+X48474432Y-14651441D01*
+X48481571Y-14653229D01*
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+X48522160Y-14683332D01*
+X48525944Y-14689645D01*
+X48529091Y-14696299D01*
+X48531571Y-14703229D01*
+X48533359Y-14710368D01*
+X48534439Y-14717649D01*
+X48534800Y-14725000D01*
+X48534800Y-14875000D01*
+X48534439Y-14882351D01*
+X48533359Y-14889632D01*
+X48531571Y-14896771D01*
+X48529091Y-14903701D01*
+X48525944Y-14910355D01*
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+X47127449Y-14949639D01*
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+X48459800Y-14650000D01*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X48467151Y-15150361D02*
+G01*
+X48474432Y-15151441D01*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X48467151Y-15650361D02*
+G01*
+X48474432Y-15651441D01*
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+X48525944Y-15689645D01*
+X48529091Y-15696299D01*
+X48531571Y-15703229D01*
+X48533359Y-15710368D01*
+X48534439Y-15717649D01*
+X48534800Y-15725000D01*
+X48534800Y-15875000D01*
+X48534439Y-15882351D01*
+X48533359Y-15889632D01*
+X48531571Y-15896771D01*
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+X48525944Y-15910355D01*
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+X48474432Y-15948559D01*
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+X47127449Y-15949639D01*
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+X48467151Y-15650361D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X48467151Y-16150361D02*
+G01*
+X48474432Y-16151441D01*
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+X48459800Y-16150000D01*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X48467151Y-16650361D02*
+G01*
+X48474432Y-16651441D01*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X48467151Y-17150361D02*
+G01*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X48467151Y-17650361D02*
+G01*
+X48474432Y-17651441D01*
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+G04 #@! TD.AperFunction*
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+G36*
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+G04 #@! TD.AperFunction*
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+G04 #@! TD.AperFunction*
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+G04 #@! TD.AperFunction*
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+G04 #@! TD.AperFunction*
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+G04 #@! TD.AperFunction*
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+G04 #@! TD.AperFunction*
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+G36*
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+G01*
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+G04 #@! TD.AperFunction*
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+G04 #@! TD.AperFunction*
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+G04 #@! TD.AperFunction*
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+G04 #@! TD.AperFunction*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X40420558Y-1354310D02*
+G01*
+X40434876Y-1356434D01*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X41411158Y-2324310D02*
+G01*
+X41425476Y-2326434D01*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X41411158Y-1354310D02*
+G01*
+X41425476Y-1356434D01*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
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+G01*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X42401758Y-1354310D02*
+G01*
+X42416076Y-1356434D01*
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+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X43417758Y-2324310D02*
+G01*
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+X43403300Y-2323600D01*
+X43417758Y-2324310D01*
+G37*
+G04 #@! TD.AperFunction*
+G04 #@! TA.AperFunction,SMDPad,CuDef*
+G36*
+X43417758Y-1354310D02*
+G01*
+X43432076Y-1356434D01*
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+X43472831Y-1926183D01*
+X43459746Y-1932372D01*
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diff --git a/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-F_Mask.gbr b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-F_Mask.gbr
new file mode 100644
index 0000000..8ce23f8
--- /dev/null
+++ b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-F_Mask.gbr
@@ -0,0 +1,6492 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5)-3*
+G04 #@! TF.CreationDate,2020-10-03T21:18:42-07:00*
+G04 #@! TF.ProjectId,MCL86jr,4d434c38-366a-4722-9e6b-696361645f70,rev?*
+G04 #@! TF.SameCoordinates,PX6b9fce8PY20f1980*
+G04 #@! TF.FileFunction,Soldermask,Top*
+G04 #@! TF.FilePolarity,Negative*
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW (5.1.5)-3) date 2020-10-03 21:18:42*
+%MOMM*%
+%LPD*%
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diff --git a/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-F_Paste.gbr b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-F_Paste.gbr
new file mode 100644
index 0000000..5a3645a
--- /dev/null
+++ b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-F_Paste.gbr
@@ -0,0 +1,11762 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5)-3*
+G04 #@! TF.CreationDate,2020-10-03T21:18:42-07:00*
+G04 #@! TF.ProjectId,MCL86jr,4d434c38-366a-4722-9e6b-696361645f70,rev?*
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+G04 #@! TF.FileFunction,Paste,Top*
+G04 #@! TF.FilePolarity,Positive*
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+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
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diff --git a/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-F_SilkS.gbr b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-F_SilkS.gbr
new file mode 100644
index 0000000..46b9710
--- /dev/null
+++ b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-F_SilkS.gbr
@@ -0,0 +1,599 @@
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diff --git a/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-In1_Cu.gbr b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-In1_Cu.gbr
new file mode 100644
index 0000000..f9544d6
--- /dev/null
+++ b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-In1_Cu.gbr
@@ -0,0 +1,7681 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5)-3*
+G04 #@! TF.CreationDate,2020-10-03T21:18:42-07:00*
+G04 #@! TF.ProjectId,MCL86jr,4d434c38-366a-4722-9e6b-696361645f70,rev?*
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+G04 #@! TF.FileFunction,Copper,L2,Inr*
+G04 #@! TF.FilePolarity,Positive*
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+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
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diff --git a/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-In2_Cu.gbr b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-In2_Cu.gbr
new file mode 100644
index 0000000..033c9bf
--- /dev/null
+++ b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-In2_Cu.gbr
@@ -0,0 +1,7482 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5)-3*
+G04 #@! TF.CreationDate,2020-10-03T21:18:42-07:00*
+G04 #@! TF.ProjectId,MCL86jr,4d434c38-366a-4722-9e6b-696361645f70,rev?*
+G04 #@! TF.SameCoordinates,PX6b9fce8PY20f1980*
+G04 #@! TF.FileFunction,Copper,L3,Inr*
+G04 #@! TF.FilePolarity,Positive*
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW (5.1.5)-3) date 2020-10-03 21:18:42*
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index 0000000..53ccd72
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+X29794Y-15697
+X29972Y-17424
+X30074Y-27762
+X30150Y-9906
+X30709Y-41402
+X30901Y-31257
+X31166Y-19304
+X31267Y-14986
+X31293Y-16724
+X31616Y-37763
+X32055Y-41148
+X32055Y-45212
+X32207Y-36957
+X32360Y-9855
+X32563Y-5842
+X32588Y-35992
+X32664Y-23952
+X32715Y-21057
+X32868Y-6960
+X32893Y-35001
+X33350Y-41072
+X33477Y-33909
+X33934Y-5639
+X34344Y-28156
+X34722Y-32193
+X34747Y-41072
+X34823Y-11176
+X34849Y-31201
+X35255Y-9677
+X35865Y-6858
+X35865Y-24130
+X35966Y-27407
+X36093Y-18999
+X36093Y-21844
+X36119Y-2667
+X36323Y-40869
+X36373Y-10414
+X36373Y-13589
+X36373Y-31369
+X36855Y-5639
+X37003Y-34505
+X37063Y-762
+X37270Y-28330
+X37425Y-11227
+X37901Y-6863
+X37948Y-37414
+X38063Y-762
+X38125Y-10312
+X38659Y-49301
+X39063Y-762
+X39185Y-6858
+X39243Y-37516
+X39395Y-10287
+X39776Y-49301
+X39929Y-24892
+X39929Y-28194
+X40063Y-762
+X40710Y-10330
+X40894Y-49352
+X41190Y-787
+X41213Y-32080
+X41569Y-11060
+X42164Y-49378
+X42266Y-737
+X42393Y-10211
+X42850Y-19812
+X42901Y-27076
+X43434Y-49327
+X43501Y-27991
+X43573Y-814
+X43612Y-5842
+X43661Y-45468
+X43866Y-9906
+X43895Y-31365
+X43949Y-34348
+X44422Y-28381
+X44572Y-753
+X44886Y-45430
+X44890Y-31468
+X45263Y-2667
+X45415Y-34798
+X45420Y-28323
+X46017Y-19850
+X46177Y-16815
+X46304Y-18796
+X46406Y-25273
+X46406Y-26289
+X46660Y-5842
+X47549Y-7264
+X48362Y-31013
+X48946Y-36678
+X49098Y-49276
+X49301Y-28473
+X49321Y-21347
+X49389Y-26111
+X49448Y-19521
+X49519Y-16400
+X49530Y-50698
+X49708Y-10287
+X49708Y-12827
+X49779Y-17920
+X50145Y-22625
+X50419Y-7264
+X50557Y-16879
+X50673Y-19279
+X50712Y-18279
+X50775Y-15479
+T2
+X3546Y-6212
+X3546Y-8752
+X3546Y-11292
+X3546Y-13832
+X3546Y-16372
+X3546Y-18912
+X3546Y-21452
+X3546Y-23992
+X3546Y-26532
+X3546Y-29072
+X3546Y-31612
+X3546Y-34152
+X3546Y-36692
+X3546Y-39232
+X3546Y-41772
+X3546Y-44312
+X3546Y-46852
+X3546Y-49392
+X3546Y-51932
+X3546Y-54472
+X18786Y-6212
+X18786Y-8752
+X18786Y-11292
+X18786Y-13832
+X18786Y-16372
+X18786Y-18912
+X18786Y-21452
+X18786Y-23992
+X18786Y-26532
+X18786Y-29072
+X18786Y-31612
+X18786Y-34152
+X18786Y-36692
+X18786Y-39232
+X18786Y-41772
+X18786Y-44312
+X18786Y-46852
+X18786Y-49392
+X18786Y-51932
+X18786Y-54472
+T3
+X11201Y-7696
+X11201Y-10236
+X11201Y-12776
+X11201Y-15316
+X11201Y-17856
+X11201Y-20396
+T0
+M30
diff --git a/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-bottom.pos b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-bottom.pos
new file mode 100644
index 0000000..e0b12de
--- /dev/null
+++ b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-bottom.pos
@@ -0,0 +1,56 @@
+### Module positions - created on 10/3/2020 9:18:58 PM ###
+### Printed by Pcbnew version kicad (5.1.5)-3
+## Unit = mm, Angle = deg.
+## Side : bottom
+# Ref     Val                Package                          PosX       PosY       Rot  Side
+C1        4.7uF              C_0402_1005Metric            -24.5110   -29.4386  180.0000  bottom
+C2        4.7uF              C_0402_1005Metric            -48.2600   -33.1216   90.0000  bottom
+C3        4.7uF              C_0402_1005Metric            -23.0378   -13.8430   90.0000  bottom
+C4        4.7uF              C_0402_1005Metric            -50.6476   -11.5062   90.0000  bottom
+C5        4.7uF              C_0402_1005Metric            -26.6470   -31.4198    0.0000  bottom
+C6        4.7uF              C_0402_1005Metric            -23.7744   -20.1168  270.0000  bottom
+C7        4.7uF              C_0402_1005Metric            -35.4584    -5.6388  180.0000  bottom
+C8        4.7uF              C_0402_1005Metric            -36.3474   -32.8676  270.0000  bottom
+C9        4.7uF              C_0402_1005Metric            -50.7238   -20.7010  270.0000  bottom
+C10       4.7uF              C_0402_1005Metric            -41.7322   -44.5516  270.0000  bottom
+C11       4.7uF              C_0402_1005Metric            -29.6418   -19.3040    0.0000  bottom
+C12       4.7uF              C_0402_1005Metric            -36.3728   -11.9380  270.0000  bottom
+C13       4.7uF              C_0402_1005Metric            -44.3738   -19.8120  180.0000  bottom
+C14       4.7uF              C_0402_1005Metric            -50.5206   -27.0510  270.0000  bottom
+C15       4.7uF              C_0402_1005Metric            -35.8648   -25.9080   90.0000  bottom
+C16       4.7uF              C_0402_1005Metric            -21.5138    -6.7310    0.0000  bottom
+C17       4.7uF              C_0402_1005Metric            -26.7208    -4.5720    0.0000  bottom
+C18       4.7uF              C_0402_1005Metric            -26.7208    -5.8420    0.0000  bottom
+C19       4.7uF              C_0402_1005Metric            -29.8196   -12.6492  270.0000  bottom
+C20       4.7uF              C_0402_1005Metric            -50.0634   -49.3268   90.0000  bottom
+C21       4.7uF              C_0402_1005Metric            -25.0698   -43.5610    0.0000  bottom
+C22       4.7uF              C_0402_1005Metric            -11.1252   -26.0350  270.0000  bottom
+C23       4.7uF              C_0402_1005Metric            -13.6144   -41.4274   90.0000  bottom
+C24       4.7uF              C_0402_1005Metric            -28.2702   -42.3926  270.0000  bottom
+C25       4.7uF              C_0402_1005Metric            -31.1658    -5.8420    0.0000  bottom
+C26       4.7uF              C_0402_1005Metric            -45.1358    -5.8420    0.0000  bottom
+C27       4.7uF              C_0402_1005Metric            -43.8150   -32.8676   90.0000  bottom
+C28       4.7uF              C_0402_1005Metric            -32.6898   -22.4790  270.0000  bottom
+C29       4.7uF              C_0402_1005Metric            -48.9990    -7.2644    0.0000  bottom
+C30       4.7uF              C_0402_1005Metric            -30.5816   -45.1866    0.0000  bottom
+C31       4.7uF              C_0402_1005Metric            -36.1188   -20.4470  270.0000  bottom
+R2        330                R_0402_1005Metric            -44.2468    -2.1590  270.0000  bottom
+R3        330                R_0402_1005Metric            -43.2562    -2.1590  270.0000  bottom
+R4        330                R_0402_1005Metric            -42.2656    -2.1590  270.0000  bottom
+R5        330                R_0402_1005Metric            -41.2750    -2.1590  270.0000  bottom
+R6        330                R_0402_1005Metric            -40.2844    -2.1590  270.0000  bottom
+R7        330                R_0402_1005Metric            -39.3192    -2.1590  270.0000  bottom
+R8        330                R_0402_1005Metric            -38.3286    -2.1590  270.0000  bottom
+R9        330                R_0402_1005Metric            -37.3634    -2.1590  270.0000  bottom
+R10       4.7k               R_0402_1005Metric            -44.3738   -26.6700  270.0000  bottom
+R11       4.7k               R_0402_1005Metric            -39.9288   -26.6700  270.0000  bottom
+R12       4.7k               R_0402_1005Metric            -45.5168   -26.6700  270.0000  bottom
+R13       4.7k               R_0402_1005Metric            -28.2448   -26.6700  270.0000  bottom
+R14       4.7k               R_0402_1005Metric            -29.7180   -26.2128  270.0000  bottom
+R15       4.7k               R_0402_1005Metric            -22.5806   -45.6184    0.0000  bottom
+R16       33                 R_0402_1005Metric            -44.9326   -33.2232  270.0000  bottom
+U2        W25Q128JVS         SOIC-8_5.23x5.23mm_P1.27mm   -45.5168   -40.2844   90.0000  bottom
+U3        MIC5504-3.3YM5-TR  SOT23-5P95_280X145XL45X37N   -22.5298    -4.5720    0.0000  bottom
+U5        SN74LVC245APW      SOP65P640X120-20N            -25.3238   -37.6428    0.0000  bottom
+U7        MIC5504-1.2YM5-TR  SOT23-5P95_280X145XL45X37N   -27.3304    -8.9662    0.0000  bottom
+## End
diff --git a/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-top.pos b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-top.pos
new file mode 100644
index 0000000..99aad70
--- /dev/null
+++ b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr-top.pos
@@ -0,0 +1,20 @@
+### Module positions - created on 10/3/2020 9:18:58 PM ###
+### Printed by Pcbnew version kicad (5.1.5)-3
+## Unit = mm, Angle = deg.
+## Side : top
+# Ref     Val               Package                               PosX       PosY       Rot  Side
+D1        LED               LED_0402_1005Metric                44.2214    -2.1336   90.0000  top
+D2        LED               LED_0402_1005Metric                43.2308    -2.1336   90.0000  top
+D3        LED               LED_0402_1005Metric                42.2148    -2.1336   90.0000  top
+D4        LED               LED_0402_1005Metric                41.2242    -2.1336   90.0000  top
+D5        LED               LED_0402_1005Metric                40.2336    -2.1336   90.0000  top
+D6        LED               LED_0402_1005Metric                39.2430    -2.1336   90.0000  top
+D7        LED               LED_0402_1005Metric                38.2524    -2.1336   90.0000  top
+D8        LED               LED_0402_1005Metric                37.2618    -2.1336   90.0000  top
+R1        33                R_0402_1005Metric                  47.2694   -30.3530  270.0000  top
+U1        XC6SLX9-TQG144    TQFP-144_20x20mm_P0.5mm            37.1348   -19.0500    0.0000  top
+U4        SN74LVC245APW     SOP65P640X120-20N                  10.8204   -47.1678    0.0000  top
+U6        SN74LVC245APW     SOP65P640X120-20N                  10.9728   -28.2194    0.0000  top
+U8        CY62148GN-45ZSXI  SOIC127P1176X120-32N               38.9890   -45.0596  270.0000  top
+Y1        100Mhz            OSC_SIT8008BI-13-33E-33.333330E    47.4218   -33.2486   90.0000  top
+## End
diff --git a/MCL86jr/PCBA/Fabrication_Products2/MCL86jr.d356 b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr.d356
new file mode 100644
index 0000000..33e50cd
--- /dev/null
+++ b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr.d356
@@ -0,0 +1,574 @@
+P  CODE 00
+P  UNITS CUST 0
+P  arrayDim   N
+317GND              VIA        MD0157PA00X+019040Y-012210X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+007770Y-001550X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+013360Y-002220X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+018370Y-002300X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+016870Y-007800X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+012820Y-002300X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+011100Y-012370X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+009070Y-004850X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+012270Y-007600X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+014120Y-009500X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+014320Y-005350X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+015720Y-009800X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+011020Y-004450X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+017270Y-003900X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+019570Y-004050X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+018270Y-009950X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+011070Y-001800X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+011080Y-008780X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+011030Y-006410X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+004390Y-010820X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+003180Y-012780X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+009335Y-008445X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+004710Y-017670X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+003120Y-020090X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+008870Y-013210X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+005754Y-016080X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+009468Y-015727X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+011720Y-005560X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+019742Y-008908X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+017189Y-017901X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+019496Y-006457X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+014568Y-013584X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+014673Y-011153X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+017281Y-012348X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+011680Y-016340X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+012740Y-003880X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+013880Y-003810X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+013521Y-011085X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+009092Y-011522X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+019410Y-011210X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+012860Y-009430X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+019850Y-002860X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+012620Y-017800X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+010570Y-017150X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+018230Y-007400X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+019330Y-019400X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+011070Y-002284X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+009797Y-003564X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+009070Y-002836X0315Y0000R000S3
+317GND              VIA        MD0157PA00X+014210Y-008600X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+009920Y-001800X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+017170Y-002300X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+011670Y-002300X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+009850Y-012370X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+018270Y-010350X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+009220Y-017150X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+005370Y-016900X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+014120Y-002700X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+019570Y-005050X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+014320Y-012350X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+009920Y-002150X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+009060Y-006140X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+009740Y-007420X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+004800Y-010050X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+009950Y-011200X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+003130Y-016970X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+019270Y-014440X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+011100Y-009920X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+008470Y-018315X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+019444Y-010280X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+019468Y-007685X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+019950Y-007590X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+017820Y-001050X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+014220Y-001050X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+014510Y-002220X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+014922Y-002702X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+019500Y-019960X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+017672Y-017886X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+012940Y-002740X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+009841Y-009882X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+018720Y-002860X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+011450Y-017780X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+010640Y-016420X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+015427Y-002700X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+019418Y-008404X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+017880Y-013700X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+016226Y-012630X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+017303Y-013523X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+012166Y-012306X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+009780Y-003090X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+009648Y-004801X0315Y0000R000S3
+317+3V3             VIA        MD0157PA00X+009750Y-004160X0315Y0000R000S3
+317+1V2             VIA        MD0157PA00X+011070Y-007598X0315Y0000R000S3
+317+1V2             VIA        MD0157PA00X+011720Y-004400X0315Y0000R000S3
+317+1V2             VIA        MD0157PA00X+014320Y-004100X0315Y0000R000S3
+317+1V2             VIA        MD0157PA00X+011220Y-009400X0315Y0000R000S3
+317+1V2             VIA        MD0157PA00X+011870Y-003900X0315Y0000R000S3
+317+1V2             VIA        MD0157PA00X+014160Y-010790X0315Y0000R000S3
+317+1V2             VIA        MD0157PA00X+012880Y-008290X0315Y0000R000S3
+317+1V2             VIA        MD0157PA00X+018117Y-007815X0315Y0000R000S3
+317+1V2             VIA        MD0157PA00X+014210Y-007480X0315Y0000R000S3
+317HOLD_5V          VIA        MD0157PA00X+002370Y-017930X0315Y0000R000S3
+317HLDA_5V          VIA        MD0157PA00X+005984Y-017510X0315Y0000R000S3
+317ALE_5V           VIA        MD0157PA00X+004791Y-019510X0315Y0000R000S3
+317SRAM_A13         VIA        MD0157PA00X+017100Y-019420X0315Y0000R000S3
+317SRAM_A13         VIA        MD0157PA00X+019990Y-006094X0315Y0000R000S3
+317SRAM_A8          VIA        MD0157PA00X+016600Y-019440X0315Y0000R000S3
+317SRAM_A8          VIA        MD0157PA00X+018180Y-006620X0315Y0000R000S3
+317SRAM_A9          VIA        MD0157PA00X+016100Y-019430X0315Y0000R000S3
+317SRAM_A9          VIA        MD0157PA00X+019904Y-006645X0315Y0000R000S3
+317SRAM_A11         VIA        MD0157PA00X+015660Y-019410X0315Y0000R000S3
+317SRAM_A11         VIA        MD0157PA00X+019598Y-007055X0315Y0000R000S3
+317SRAM_OE_N        VIA        MD0157PA00X+015220Y-019410X0315Y0000R000S3
+317SRAM_OE_N        VIA        MD0157PA00X+019965Y-007197X0315Y0000R000S3
+317SRAM_D2          VIA        MD0157PA00X+012090Y-016300X0315Y0000R000S3
+317SRAM_D2          VIA        MD0157PA00X+016690Y-004020X0315Y0000R000S3
+317SRAM_D1          VIA        MD0157PA00X+016366Y-004354X0315Y0000R000S3
+317SRAM_D1          VIA        MD0157PA00X+012620Y-016200X0315Y0000R000S3
+317SRAM_D0          VIA        MD0157PA00X+013130Y-016170X0315Y0000R000S3
+317SRAM_D0          VIA        MD0157PA00X+016028Y-004067X0315Y0000R000S3
+317SRAM_A0          VIA        MD0157PA00X+013680Y-016170X0315Y0000R000S3
+317SRAM_A0          VIA        MD0157PA00X+013710Y-004400X0315Y0000R000S3
+317SRAM_A1          VIA        MD0157PA00X+014300Y-016090X0315Y0000R000S3
+317SRAM_A1          VIA        MD0157PA00X+014734Y-004420X0315Y0000R000S3
+317SRAM_A2          VIA        MD0157PA00X+015010Y-004060X0315Y0000R000S3
+317SRAM_A2          VIA        MD0157PA00X+014940Y-014730X0315Y0000R000S3
+317SRAM_A3          VIA        MD0157PA00X+015450Y-014770X0315Y0000R000S3
+317SRAM_A3          VIA        MD0157PA00X+015510Y-004050X0315Y0000R000S3
+317BUF1_OE__N       VIA        MD0157PA00X+012447Y-014867X0315Y0000R000S3
+317NET-(J1-PAD5)    VIA        MD0157PA00X+011800Y-006860X0315Y0000R000S3
+317NET-(J1-PAD4)    VIA        MD0157PA00X+012320Y-006584X0315Y0000R000S3
+317NET-(J1-PAD3)    VIA        MD0157PA00X+011730Y-006180X0315Y0000R000S3
+317NET-(J1-PAD2)    VIA        MD0157PA00X+012310Y-005900X0315Y0000R000S3
+317SPI_DOUT         VIA        MD0157PA00X+017126Y-011020X0315Y0000R000S3
+317SPI_DIN          VIA        MD0157PA00X+016890Y-010660X0315Y0000R000S3
+317SPI_CS_N         VIA        MD0157PA00X+011440Y-011060X0315Y0000R000S3
+317NET-(D1-PAD2)    VIA        MD0157PA00X+017548Y-000296X0315Y0000R000S3
+317NET-(D2-PAD2)    VIA        MD0157PA00X+017155Y-000320X0315Y0000R000S3
+317NET-(D3-PAD2)    VIA        MD0157PA00X+016640Y-000290X0315Y0000R000S3
+317NET-(D4-PAD2)    VIA        MD0157PA00X+016216Y-000310X0315Y0000R000S3
+317NET-(D5-PAD2)    VIA        MD0157PA00X+015773Y-000300X0315Y0000R000S3
+317NET-(D6-PAD2)    VIA        MD0157PA00X+015379Y-000300X0315Y0000R000S3
+317NET-(D7-PAD2)    VIA        MD0157PA00X+014985Y-000300X0315Y0000R000S3
+317NET-(D8-PAD2)    VIA        MD0157PA00X+014592Y-000300X0315Y0000R000S3
+317FPGA_M0          VIA        MD0157PA00X+017489Y-011173X0315Y0000R000S3
+317FPGA_M1          VIA        MD0157PA00X+015720Y-011100X0315Y0000R000S3
+317FPGA_DONE        VIA        MD0157PA00X+017882Y-011151X0315Y0000R000S3
+317FPGA_PROGRAM_N   VIA        MD0157PA00X+011006Y-011065X0315Y0000R000S3
+317FPGA_INIT        VIA        MD0157PA00X+011840Y-010930X0315Y0000R000S3
+317NET-(R16-PAD1)   VIA        MD0157PA00X+017673Y-012389X0315Y0000R000S3
+317RD_3V            VIA        MD0157PA00X+013720Y-012284X0315Y0000R000S3
+317INTA_N_3V        VIA        MD0157PA00X+012680Y-014550X0315Y0000R000S3
+317DEN_3V           VIA        MD0157PA00X+012830Y-014170X0315Y0000R000S3
+317DTR_3V           VIA        MD0157PA00X+012950Y-013780X0315Y0000R000S3
+317IOM_3V           VIA        MD0157PA00X+013180Y-013350X0315Y0000R000S3
+317WR_3V            VIA        MD0157PA00X+013670Y-012674X0315Y0000R000S3
+327+3V3             Y1    -4          A01X+018375Y-013464X0433Y0394R270S2
+327NET-(R1-PAD2)    Y1    -3          A01X+018375Y-012716X0433Y0394R270S2
+327GND              Y1    -2          A01X+018965Y-012716X0433Y0394R270S2
+327+3V3             Y1    -1          A01X+018965Y-013464X0433Y0394R270S2
+327+3V3             U8    -32         A01X+019100Y-019953X0567Y0240R090S2
+327SRAM_A15         U8    -31         A01X+018600Y-019953X0567Y0240R090S2
+327SRAM_A18         U8    -30         A01X+018100Y-019953X0567Y0240R090S2
+327SRAM_WE_N        U8    -29         A01X+017600Y-019953X0567Y0240R090S2
+327SRAM_A13         U8    -28         A01X+017100Y-019953X0567Y0240R090S2
+327SRAM_A8          U8    -27         A01X+016600Y-019953X0567Y0240R090S2
+327SRAM_A9          U8    -26         A01X+016100Y-019953X0567Y0240R090S2
+327SRAM_A11         U8    -25         A01X+015600Y-019953X0567Y0240R090S2
+327SRAM_OE_N        U8    -24         A01X+015100Y-019953X0567Y0240R090S2
+327SRAM_A10         U8    -23         A01X+014600Y-019953X0567Y0240R090S2
+327SRAM_CE_N        U8    -22         A01X+014100Y-019953X0567Y0240R090S2
+327SRAM_D7          U8    -21         A01X+013600Y-019953X0567Y0240R090S2
+327SRAM_D6          U8    -20         A01X+013100Y-019953X0567Y0240R090S2
+327SRAM_D5          U8    -19         A01X+012600Y-019953X0567Y0240R090S2
+327SRAM_D4          U8    -18         A01X+012100Y-019953X0567Y0240R090S2
+327SRAM_D3          U8    -17         A01X+011600Y-019953X0567Y0240R090S2
+327GND              U8    -16         A01X+011600Y-015527X0567Y0240R090S2
+327SRAM_D2          U8    -15         A01X+012100Y-015527X0567Y0240R090S2
+327SRAM_D1          U8    -14         A01X+012600Y-015527X0567Y0240R090S2
+327SRAM_D0          U8    -13         A01X+013100Y-015527X0567Y0240R090S2
+327SRAM_A0          U8    -12         A01X+013600Y-015527X0567Y0240R090S2
+327SRAM_A1          U8    -11         A01X+014100Y-015527X0567Y0240R090S2
+327SRAM_A2          U8    -10         A01X+014600Y-015527X0567Y0240R090S2
+327SRAM_A3          U8    -9          A01X+015100Y-015527X0567Y0240R090S2
+327SRAM_A4          U8    -8          A01X+015600Y-015527X0567Y0240R090S2
+327SRAM_A5          U8    -7          A01X+016100Y-015527X0567Y0240R090S2
+327SRAM_A6          U8    -6          A01X+016600Y-015527X0567Y0240R090S2
+327SRAM_A7          U8    -5          A01X+017100Y-015527X0567Y0240R090S2
+327SRAM_A12         U8    -4          A01X+017600Y-015527X0567Y0240R090S2
+327SRAM_A14         U8    -3          A01X+018100Y-015527X0567Y0240R090S2
+327SRAM_A16         U8    -2          A01X+018600Y-015527X0567Y0240R090S2
+327SRAM_A17         U8    -1          A01X+019100Y-015527X0567Y0240R090S2
+327+1V2             U7    -5          A04X+011209Y-003904X0449Y0236R000S1
+327N/C              U7    -4          A04X+011209Y-003156X0449Y0236R000S1
+327+3V3             U7    -3          A04X+010311Y-003156X0449Y0236R000S1
+327GND              U7    -2          A04X+010311Y-003530X0449Y0236R000S1
+327+3V3             U7    -1          A04X+010311Y-003904X0449Y0236R000S1
+327+3V3             U6    -20         A01X+005450Y-009958X0618Y0161R000S2
+327BUF2_OE__N       U6    -19         A01X+005450Y-010214X0618Y0161R000S2
+327AD7_3V           U6    -18         A01X+005450Y-010470X0618Y0161R000S2
+327AD6_3V           U6    -17         A01X+005450Y-010726X0618Y0161R000S2
+327AD5_3V           U6    -16         A01X+005450Y-010982X0618Y0161R000S2
+327AD4_3V           U6    -15         A01X+005450Y-011238X0618Y0161R000S2
+327AD3_3V           U6    -14         A01X+005450Y-011494X0618Y0161R000S2
+327AD2_3V           U6    -13         A01X+005450Y-011750X0618Y0161R000S2
+327AD1_3V           U6    -12         A01X+005450Y-012006X0618Y0161R000S2
+327AD0_3V           U6    -11         A01X+005450Y-012262X0618Y0161R000S2
+327GND              U6    -10         A01X+003190Y-012262X0618Y0161R000S2
+327AD0_5V           U6    -9          A01X+003190Y-012006X0618Y0161R000S2
+327AD1_5V           U6    -8          A01X+003190Y-011750X0618Y0161R000S2
+327AD2_5V           U6    -7          A01X+003190Y-011494X0618Y0161R000S2
+327AD3_5V           U6    -6          A01X+003190Y-011238X0618Y0161R000S2
+327AD4_5V           U6    -5          A01X+003190Y-010982X0618Y0161R000S2
+327AD5_5V           U6    -4          A01X+003190Y-010726X0618Y0161R000S2
+327AD6_5V           U6    -3          A01X+003190Y-010470X0618Y0161R000S2
+327AD7_5V           U6    -2          A01X+003190Y-010214X0618Y0161R000S2
+327BUF2_DIR         U6    -1          A01X+003190Y-009958X0618Y0161R000S2
+327+3V3             U5    -20         A04X+011100Y-015972X0618Y0161R000S1
+327BUF1_OE__N       U5    -19         A04X+011100Y-015716X0618Y0161R000S1
+327INTA_N_3V        U5    -18         A04X+011100Y-015460X0618Y0161R000S1
+327DEN_3V           U5    -17         A04X+011100Y-015204X0618Y0161R000S1
+327DTR_3V           U5    -16         A04X+011100Y-014948X0618Y0161R000S1
+327IOM_3V           U5    -15         A04X+011100Y-014692X0618Y0161R000S1
+327WR_3V            U5    -14         A04X+011100Y-014436X0618Y0161R000S1
+327RD_3V            U5    -13         A04X+011100Y-014180X0618Y0161R000S1
+327N/C              U5    -12         A04X+011100Y-013924X0618Y0161R000S1
+327N/C              U5    -11         A04X+011100Y-013668X0618Y0161R000S1
+327GND              U5    -10         A04X+008840Y-013668X0618Y0161R000S1
+327N/C              U5    -9          A04X+008840Y-013924X0618Y0161R000S1
+327N/C              U5    -8          A04X+008840Y-014180X0618Y0161R000S1
+327RD_5V            U5    -7          A04X+008840Y-014436X0618Y0161R000S1
+327WR_5V            U5    -6          A04X+008840Y-014692X0618Y0161R000S1
+327IOM_5V           U5    -5          A04X+008840Y-014948X0618Y0161R000S1
+327DTR_5V           U5    -4          A04X+008840Y-015204X0618Y0161R000S1
+327DEN_5V           U5    -3          A04X+008840Y-015460X0618Y0161R000S1
+327INTA_N_5V        U5    -2          A04X+008840Y-015716X0618Y0161R000S1
+327GND              U5    -1          A04X+008840Y-015972X0618Y0161R000S1
+327+3V3             U4    -20         A01X+005390Y-017418X0618Y0161R000S2
+327GND              U4    -19         A01X+005390Y-017674X0618Y0161R000S2
+327HLDA_5V          U4    -18         A01X+005390Y-017930X0618Y0161R000S2
+327HOLD_3V          U4    -17         A01X+005390Y-018186X0618Y0161R000S2
+327NMI_3V           U4    -16         A01X+005390Y-018442X0618Y0161R000S2
+327INTR_3V          U4    -15         A01X+005390Y-018698X0618Y0161R000S2
+327CLK_3V           U4    -14         A01X+005390Y-018954X0618Y0161R000S2
+327RESET_3V         U4    -13         A01X+005390Y-019210X0618Y0161R000S2
+327READY_3V         U4    -12         A01X+005390Y-019466X0618Y0161R000S2
+327ALE_5V           U4    -11         A01X+005390Y-019722X0618Y0161R000S2
+327GND              U4    -10         A01X+003130Y-019722X0618Y0161R000S2
+327ALE_3V           U4    -9          A01X+003130Y-019466X0618Y0161R000S2
+327READY_5V         U4    -8          A01X+003130Y-019210X0618Y0161R000S2
+327RESET_5V         U4    -7          A01X+003130Y-018954X0618Y0161R000S2
+327CLK_5V           U4    -6          A01X+003130Y-018698X0618Y0161R000S2
+327INTR_5V          U4    -5          A01X+003130Y-018442X0618Y0161R000S2
+327NMI_5V           U4    -4          A01X+003130Y-018186X0618Y0161R000S2
+327HOLD_5V          U4    -3          A01X+003130Y-017930X0618Y0161R000S2
+327HLDA_3V          U4    -2          A01X+003130Y-017674X0618Y0161R000S2
+327+3V3             U4    -1          A01X+003130Y-017418X0618Y0161R000S2
+327+3V3             U3    -5          A04X+009319Y-002174X0449Y0236R000S1
+327N/C              U3    -4          A04X+009319Y-001426X0449Y0236R000S1
+327+5V              U3    -3          A04X+008421Y-001426X0449Y0236R000S1
+327GND              U3    -2          A04X+008421Y-001800X0449Y0236R000S1
+327+5V              U3    -1          A04X+008421Y-002174X0449Y0236R000S1
+327GND              C31   -2          A04X+014220Y-008241X0232Y0252R090S1
+327+1V2             C31   -1          A04X+014220Y-007859X0232Y0252R090S1
+327GND              C30   -2          A04X+012231Y-017790X0232Y0252R000S1
+327+3V3             C30   -1          A04X+011849Y-017790X0232Y0252R000S1
+327GND              C29   -2          A04X+019482Y-002860X0232Y0252R000S1
+327+3V3             C29   -1          A04X+019100Y-002860X0232Y0252R000S1
+327GND              C28   -2          A04X+012870Y-009041X0232Y0252R090S1
+327+1V2             C28   -1          A04X+012870Y-008659X0232Y0252R090S1
+317+5V              U9    -40   D0315PA00X+007396Y-002446X0630Y0630R000S0
+317GND              U9    -20   D0315PA00X+001396Y-021446X0630Y0630R000S0
+317A15_5V           U9    -39   D0315PA00X+007396Y-003446X0630Y0630R000S0
+317CLK_5V           U9    -19   D0315PA00X+001396Y-020446X0630Y0630R000S0
+317A16_5V           U9    -38   D0315PA00X+007396Y-004446X0630Y0630R000S0
+317INTR_5V          U9    -18   D0315PA00X+001396Y-019446X0630Y0630R000S0
+317A17_5V           U9    -37   D0315PA00X+007396Y-005446X0630Y0630R000S0
+317NMI_5V           U9    -17   D0315PA00X+001396Y-018446X0630Y0630R000S0
+317A18_5V           U9    -36   D0315PA00X+007396Y-006446X0630Y0630R000S0
+317AD0_5V           U9    -16   D0315PA00X+001396Y-017446X0630Y0630R000S0
+317A19_5V           U9    -35   D0315PA00X+007396Y-007446X0630Y0630R000S0
+317AD1_5V           U9    -15   D0315PA00X+001396Y-016446X0630Y0630R000S0
+317SSO_5V           U9    -34   D0315PA00X+007396Y-008446X0630Y0630R000S0
+317AD2_5V           U9    -14   D0315PA00X+001396Y-015446X0630Y0630R000S0
+317N/C              U9    -33   D0315PA00X+007396Y-009446X0630Y0630R000S0
+317AD3_5V           U9    -13   D0315PA00X+001396Y-014446X0630Y0630R000S0
+317RD_5V            U9    -32   D0315PA00X+007396Y-010446X0630Y0630R000S0
+317AD4_5V           U9    -12   D0315PA00X+001396Y-013446X0630Y0630R000S0
+317HOLD_5V          U9    -31   D0315PA00X+007396Y-011446X0630Y0630R000S0
+317AD5_5V           U9    -11   D0315PA00X+001396Y-012446X0630Y0630R000S0
+317HLDA_5V          U9    -30   D0315PA00X+007396Y-012446X0630Y0630R000S0
+317AD6_5V           U9    -10   D0315PA00X+001396Y-011446X0630Y0630R000S0
+317WR_5V            U9    -29   D0315PA00X+007396Y-013446X0630Y0630R000S0
+317AD7_5V           U9    -9    D0315PA00X+001396Y-010446X0630Y0630R000S0
+317IOM_5V           U9    -28   D0315PA00X+007396Y-014446X0630Y0630R000S0
+317A8_5V            U9    -8    D0315PA00X+001396Y-009446X0630Y0630R000S0
+317DTR_5V           U9    -27   D0315PA00X+007396Y-015446X0630Y0630R000S0
+317A9_5V            U9    -7    D0315PA00X+001396Y-008446X0630Y0630R000S0
+317DEN_5V           U9    -26   D0315PA00X+007396Y-016446X0630Y0630R000S0
+317A10_5V           U9    -6    D0315PA00X+001396Y-007446X0630Y0630R000S0
+317ALE_5V           U9    -25   D0315PA00X+007396Y-017446X0630Y0630R000S0
+317A11_5V           U9    -5    D0315PA00X+001396Y-006446X0630Y0630R000S0
+317INTA_N_5V        U9    -24   D0315PA00X+007396Y-018446X0630Y0630R000S0
+317A12_5V           U9    -4    D0315PA00X+001396Y-005446X0630Y0630R000S0
+317N/C              U9    -23   D0315PA00X+007396Y-019446X0630Y0630R000S0
+317A13_5V           U9    -3    D0315PA00X+001396Y-004446X0630Y0630R000S0
+317READY_5V         U9    -22   D0315PA00X+007396Y-020446X0630Y0630R000S0
+317A14_5V           U9    -2    D0315PA00X+001396Y-003446X0630Y0630R000S0
+317RESET_5V         U9    -21   D0315PA00X+007396Y-021446X0630Y0630R000S0
+317GND              U9    -1    D0315PA00X+001396Y-002446X0630Y0630R000S0
+327GND              C23   -2          A04X+005360Y-016119X0232Y0252R270S1
+327+3V3             C23   -1          A04X+005360Y-016501X0232Y0252R270S1
+327NET-(R1-PAD2)    R1    -2          A01X+018610Y-012141X0232Y0252R090S2
+327CLK_100MHZ       R1    -1          A01X+018610Y-011759X0232Y0252R090S2
+327+3V3             U1    -144        A01X+011175Y-003302X0118Y0581R000S2
+327A15_5V           U1    -143        A01X+011372Y-003302X0118Y0581R000S2
+327A14_5V           U1    -142        A01X+011569Y-003302X0118Y0581R000S2
+327N/C              U1    -141        A01X+011766Y-003302X0118Y0581R000S2
+327N/C              U1    -140        A01X+011963Y-003302X0118Y0581R000S2
+327N/C              U1    -139        A01X+012159Y-003302X0118Y0581R000S2
+327N/C              U1    -138        A01X+012356Y-003302X0118Y0581R000S2
+327N/C              U1    -137        A01X+012553Y-003302X0118Y0581R000S2
+327GND              U1    -136        A01X+012750Y-003302X0118Y0581R000S2
+327+3V3             U1    -135        A01X+012947Y-003302X0118Y0581R000S2
+327N/C              U1    -134        A01X+013144Y-003302X0118Y0581R000S2
+327N/C              U1    -133        A01X+013340Y-003302X0118Y0581R000S2
+327SRAM_A0          U1    -132        A01X+013537Y-003302X0118Y0581R000S2
+327LED7             U1    -131        A01X+013734Y-003302X0118Y0581R000S2
+327GND              U1    -130        A01X+013931Y-003302X0118Y0581R000S2
+327+3V3             U1    -129        A01X+014128Y-003302X0118Y0581R000S2
+327+1V2             U1    -128        A01X+014325Y-003302X0118Y0581R000S2
+327LED6             U1    -127        A01X+014522Y-003302X0118Y0581R000S2
+327SRAM_A1          U1    -126        A01X+014718Y-003302X0118Y0581R000S2
+327+3V3             U1    -125        A01X+014915Y-003302X0118Y0581R000S2
+327SRAM_A2          U1    -124        A01X+015112Y-003302X0118Y0581R000S2
+327SRAM_A3          U1    -123        A01X+015309Y-003302X0118Y0581R000S2
+327+3V3             U1    -122        A01X+015506Y-003302X0118Y0581R000S2
+327LED5             U1    -121        A01X+015703Y-003302X0118Y0581R000S2
+327LED4             U1    -120        A01X+015900Y-003302X0118Y0581R000S2
+327SRAM_D0          U1    -119        A01X+016096Y-003302X0118Y0581R000S2
+327SRAM_D1          U1    -118        A01X+016293Y-003302X0118Y0581R000S2
+327SRAM_D2          U1    -117        A01X+016490Y-003302X0118Y0581R000S2
+327LED3             U1    -116        A01X+016687Y-003302X0118Y0581R000S2
+327N/C              U1    -115        A01X+016884Y-003302X0118Y0581R000S2
+327LED2             U1    -114        A01X+017081Y-003302X0118Y0581R000S2
+327GND              U1    -113        A01X+017277Y-003302X0118Y0581R000S2
+327LED1             U1    -112        A01X+017474Y-003302X0118Y0581R000S2
+327LED0             U1    -111        A01X+017671Y-003302X0118Y0581R000S2
+327NET-(J1-PAD2)    U1    -110        A01X+017868Y-003302X0118Y0581R000S2
+327NET-(J1-PAD3)    U1    -109        A01X+018065Y-003302X0118Y0581R000S2
+327GND              U1    -108        A01X+018818Y-004055X0581Y0118R000S2
+327NET-(J1-PAD4)    U1    -107        A01X+018818Y-004252X0581Y0118R000S2
+327NET-(J1-PAD5)    U1    -106        A01X+018818Y-004449X0581Y0118R000S2
+327N/C              U1    -105        A01X+018818Y-004646X0581Y0118R000S2
+327N/C              U1    -104        A01X+018818Y-004843X0581Y0118R000S2
+327+3V3             U1    -103        A01X+018818Y-005039X0581Y0118R000S2
+327N/C              U1    -102        A01X+018818Y-005236X0581Y0118R000S2
+327N/C              U1    -101        A01X+018818Y-005433X0581Y0118R000S2
+327SRAM_A15         U1    -100        A01X+018818Y-005630X0581Y0118R000S2
+327SRAM_A18         U1    -99         A01X+018818Y-005827X0581Y0118R000S2
+327SRAM_WE_N        U1    -98         A01X+018818Y-006024X0581Y0118R000S2
+327SRAM_A13         U1    -97         A01X+018818Y-006220X0581Y0118R000S2
+327GND              U1    -96         A01X+018818Y-006417X0581Y0118R000S2
+327SRAM_A8          U1    -95         A01X+018818Y-006614X0581Y0118R000S2
+327SRAM_A9          U1    -94         A01X+018818Y-006811X0581Y0118R000S2
+327SRAM_A11         U1    -93         A01X+018818Y-007008X0581Y0118R000S2
+327SRAM_OE_N        U1    -92         A01X+018818Y-007205X0581Y0118R000S2
+327GND              U1    -91         A01X+018818Y-007402X0581Y0118R000S2
+327+3V3             U1    -90         A01X+018818Y-007598X0581Y0118R000S2
+327+1V2             U1    -89         A01X+018818Y-007795X0581Y0118R000S2
+327SRAM_A10         U1    -88         A01X+018818Y-007992X0581Y0118R000S2
+327SRAM_CE_N        U1    -87         A01X+018818Y-008189X0581Y0118R000S2
+327+3V3             U1    -86         A01X+018818Y-008386X0581Y0118R000S2
+327SRAM_D7          U1    -85         A01X+018818Y-008583X0581Y0118R000S2
+327CLK_100MHZ       U1    -84         A01X+018818Y-008780X0581Y0118R000S2
+327SRAM_D6          U1    -83         A01X+018818Y-008976X0581Y0118R000S2
+327SRAM_D5          U1    -82         A01X+018818Y-009173X0581Y0118R000S2
+327SRAM_D4          U1    -81         A01X+018818Y-009370X0581Y0118R000S2
+327SRAM_D3          U1    -80         A01X+018818Y-009567X0581Y0118R000S2
+327SRAM_A17         U1    -79         A01X+018818Y-009764X0581Y0118R000S2
+327SRAM_A16         U1    -78         A01X+018818Y-009961X0581Y0118R000S2
+327GND              U1    -77         A01X+018818Y-010157X0581Y0118R000S2
+327+3V3             U1    -76         A01X+018818Y-010354X0581Y0118R000S2
+327SRAM_A14         U1    -75         A01X+018818Y-010551X0581Y0118R000S2
+327SRAM_A12         U1    -74         A01X+018818Y-010748X0581Y0118R000S2
+327GND              U1    -73         A01X+018818Y-010945X0581Y0118R000S2
+327N/C              U1    -72         A01X+018065Y-011698X0118Y0581R000S2
+327FPGA_DONE        U1    -71         A01X+017868Y-011698X0118Y0581R000S2
+327NET-(R16-PAD1)   U1    -70         A01X+017671Y-011698X0118Y0581R000S2
+327FPGA_M0          U1    -69         A01X+017474Y-011698X0118Y0581R000S2
+327GND              U1    -68         A01X+017277Y-011698X0118Y0581R000S2
+327SRAM_A7          U1    -67         A01X+017081Y-011698X0118Y0581R000S2
+327SRAM_A6          U1    -66         A01X+016884Y-011698X0118Y0581R000S2
+327SPI_DOUT         U1    -65         A01X+016687Y-011698X0118Y0581R000S2
+327SPI_DIN          U1    -64         A01X+016490Y-011698X0118Y0581R000S2
+327+3V3             U1    -63         A01X+016293Y-011698X0118Y0581R000S2
+327SRAM_A5          U1    -62         A01X+016096Y-011698X0118Y0581R000S2
+327SRAM_A4          U1    -61         A01X+015900Y-011698X0118Y0581R000S2
+327FPGA_M1          U1    -60         A01X+015703Y-011698X0118Y0581R000S2
+327BUF1_OE__N       U1    -59         A01X+015506Y-011698X0118Y0581R000S2
+327INTA_N_3V        U1    -58         A01X+015309Y-011698X0118Y0581R000S2
+327DEN_3V           U1    -57         A01X+015112Y-011698X0118Y0581R000S2
+327DTR_3V           U1    -56         A01X+014915Y-011698X0118Y0581R000S2
+327IOM_3V           U1    -55         A01X+014718Y-011698X0118Y0581R000S2
+327GND              U1    -54         A01X+014522Y-011698X0118Y0581R000S2
+327+3V3             U1    -53         A01X+014325Y-011698X0118Y0581R000S2
+327+1V2             U1    -52         A01X+014128Y-011698X0118Y0581R000S2
+327WR_3V            U1    -51         A01X+013931Y-011698X0118Y0581R000S2
+327RD_3V            U1    -50         A01X+013734Y-011698X0118Y0581R000S2
+327GND              U1    -49         A01X+013537Y-011698X0118Y0581R000S2
+327READY_3V         U1    -48         A01X+013340Y-011698X0118Y0581R000S2
+327RESET_3V         U1    -47         A01X+013144Y-011698X0118Y0581R000S2
+327CLK_3V           U1    -46         A01X+012947Y-011698X0118Y0581R000S2
+327INTR_3V          U1    -45         A01X+012750Y-011698X0118Y0581R000S2
+327NMI_3V           U1    -44         A01X+012553Y-011698X0118Y0581R000S2
+327HOLD_3V          U1    -43         A01X+012356Y-011698X0118Y0581R000S2
+327+3V3             U1    -42         A01X+012159Y-011698X0118Y0581R000S2
+327ALE_3V           U1    -41         A01X+011963Y-011698X0118Y0581R000S2
+327HLDA_3V          U1    -40         A01X+011766Y-011698X0118Y0581R000S2
+327FPGA_INIT        U1    -39         A01X+011569Y-011698X0118Y0581R000S2
+327SPI_CS_N         U1    -38         A01X+011372Y-011698X0118Y0581R000S2
+327FPGA_PROGRAM_N   U1    -37         A01X+011175Y-011698X0118Y0581R000S2
+327+3V3             U1    -36         A01X+010422Y-010945X0581Y0118R000S2
+327AD0_3V           U1    -35         A01X+010422Y-010748X0581Y0118R000S2
+327AD1_3V           U1    -34         A01X+010422Y-010551X0581Y0118R000S2
+327AD2_3V           U1    -33         A01X+010422Y-010354X0581Y0118R000S2
+327AD3_3V           U1    -32         A01X+010422Y-010157X0581Y0118R000S2
+327+3V3             U1    -31         A01X+010422Y-009961X0581Y0118R000S2
+327N/C              U1    -30         A01X+010422Y-009764X0581Y0118R000S2
+327N/C              U1    -29         A01X+010422Y-009567X0581Y0118R000S2
+327+1V2             U1    -28         A01X+010422Y-009370X0581Y0118R000S2
+327AD4_3V           U1    -27         A01X+010422Y-009173X0581Y0118R000S2
+327AD5_3V           U1    -26         A01X+010422Y-008976X0581Y0118R000S2
+327GND              U1    -25         A01X+010422Y-008780X0581Y0118R000S2
+327N/C              U1    -24         A01X+010422Y-008583X0581Y0118R000S2
+327AD6_3V           U1    -23         A01X+010422Y-008386X0581Y0118R000S2
+327AD7_3V           U1    -22         A01X+010422Y-008189X0581Y0118R000S2
+327BUF2_OE__N       U1    -21         A01X+010422Y-007992X0581Y0118R000S2
+327+3V3             U1    -20         A01X+010422Y-007795X0581Y0118R000S2
+327+1V2             U1    -19         A01X+010422Y-007598X0581Y0118R000S2
+327+3V3             U1    -18         A01X+010422Y-007402X0581Y0118R000S2
+327N/C              U1    -17         A01X+010422Y-007205X0581Y0118R000S2
+327BUF2_DIR         U1    -16         A01X+010422Y-007008X0581Y0118R000S2
+327N/C              U1    -15         A01X+010422Y-006811X0581Y0118R000S2
+327A8_5V            U1    -14         A01X+010422Y-006614X0581Y0118R000S2
+327GND              U1    -13         A01X+010422Y-006417X0581Y0118R000S2
+327SSO_5V           U1    -12         A01X+010422Y-006220X0581Y0118R000S2
+327A9_5V            U1    -11         A01X+010422Y-006024X0581Y0118R000S2
+327A19_5V           U1    -10         A01X+010422Y-005827X0581Y0118R000S2
+327A10_5V           U1    -9          A01X+010422Y-005630X0581Y0118R000S2
+327A18_5V           U1    -8          A01X+010422Y-005433X0581Y0118R000S2
+327A11_5V           U1    -7          A01X+010422Y-005236X0581Y0118R000S2
+327A17_5V           U1    -6          A01X+010422Y-005039X0581Y0118R000S2
+327A12_5V           U1    -5          A01X+010422Y-004843X0581Y0118R000S2
+327+3V3             U1    -4          A01X+010422Y-004646X0581Y0118R000S2
+327GND              U1    -3          A01X+010422Y-004449X0581Y0118R000S2
+327A16_5V           U1    -2          A01X+010422Y-004252X0581Y0118R000S2
+327A13_5V           U1    -1          A01X+010422Y-004055X0581Y0118R000S2
+327GND              C27   -2          A04X+017250Y-012749X0232Y0252R270S1
+327+3V3             C27   -1          A04X+017250Y-013131X0232Y0252R270S1
+327GND              C26   -2          A04X+017961Y-002300X0232Y0252R000S1
+327+3V3             C26   -1          A04X+017579Y-002300X0232Y0252R000S1
+327GND              C25   -2          A04X+012461Y-002300X0232Y0252R000S1
+327+3V3             C25   -1          A04X+012079Y-002300X0232Y0252R000S1
+327SPI_CLK          R16   -2          A04X+017690Y-013271X0232Y0252R090S1
+327NET-(R16-PAD1)   R16   -1          A04X+017690Y-012889X0232Y0252R090S1
+327SPI_CS_N         R15   -2          A04X+009081Y-017960X0232Y0252R000S1
+327+3V3             R15   -1          A04X+008699Y-017960X0232Y0252R000S1
+327+3V3             R14   -1          A04X+011700Y-010129X0232Y0252R090S1
+327FPGA_INIT        R14   -2          A04X+011700Y-010511X0232Y0252R090S1
+327+3V3             R13   -1          A04X+011120Y-010309X0232Y0252R090S1
+327FPGA_PROGRAM_N   R13   -2          A04X+011120Y-010691X0232Y0252R090S1
+327+3V3             R12   -1          A04X+017920Y-010309X0232Y0252R090S1
+327FPGA_DONE        R12   -2          A04X+017920Y-010691X0232Y0252R090S1
+327GND              R11   -1          A04X+015720Y-010309X0232Y0252R090S1
+327FPGA_M1          R11   -2          A04X+015720Y-010691X0232Y0252R090S1
+327+3V3             R10   -1          A04X+017470Y-010309X0232Y0252R090S1
+327FPGA_M0          R10   -2          A04X+017470Y-010691X0232Y0252R090S1
+327+1V2             C19   -1          A04X+011740Y-004789X0232Y0252R090S1
+327GND              C19   -2          A04X+011740Y-005171X0232Y0252R090S1
+327+3V3             C18   -1          A04X+010329Y-002300X0232Y0252R000S1
+327GND              C18   -2          A04X+010711Y-002300X0232Y0252R000S1
+327+3V3             C17   -1          A04X+010329Y-001800X0232Y0252R000S1
+327GND              C17   -2          A04X+010711Y-001800X0232Y0252R000S1
+327+5V              C16   -1          A04X+008279Y-002650X0232Y0252R000S1
+327GND              C16   -2          A04X+008661Y-002650X0232Y0252R000S1
+327+3V3             C24   -1          A04X+011130Y-016499X0232Y0252R090S1
+327GND              C24   -2          A04X+011130Y-016881X0232Y0252R090S1
+327GND              C22   -2          A04X+004380Y-010441X0232Y0252R090S1
+327+3V3             C22   -1          A04X+004380Y-010059X0232Y0252R090S1
+327GND              C21   -2          A04X+010061Y-017150X0232Y0252R000S1
+327+3V3             C21   -1          A04X+009679Y-017150X0232Y0252R000S1
+327GND              C20   -2          A04X+019710Y-019229X0232Y0252R270S1
+327+3V3             C20   -1          A04X+019710Y-019611X0232Y0252R270S1
+327GND              C15   -2          A04X+014120Y-010009X0232Y0252R270S1
+327+1V2             C15   -1          A04X+014120Y-010391X0232Y0252R270S1
+327GND              C14   -2          A04X+019890Y-010841X0232Y0252R090S1
+327+3V3             C14   -1          A04X+019890Y-010459X0232Y0252R090S1
+327GND              C13   -2          A04X+017279Y-007800X0232Y0252R180S1
+327+1V2             C13   -1          A04X+017661Y-007800X0232Y0252R180S1
+327GND              C12   -2          A04X+014320Y-004891X0232Y0252R090S1
+327+1V2             C12   -1          A04X+014320Y-004509X0232Y0252R090S1
+327GND              C11   -2          A04X+011861Y-007600X0232Y0252R000S1
+327+1V2             C11   -1          A04X+011479Y-007600X0232Y0252R000S1
+327GND              C10   -2          A04X+016430Y-017731X0232Y0252R090S1
+327+3V3             C10   -1          A04X+016430Y-017349X0232Y0252R090S1
+327GND              C9    -2          A04X+019970Y-008341X0232Y0252R090S1
+327+3V3             C9    -1          A04X+019970Y-007959X0232Y0252R090S1
+327GND              C8    -2          A04X+014310Y-013131X0232Y0252R090S1
+327+3V3             C8    -1          A04X+014310Y-012749X0232Y0252R090S1
+327GND              C7    -2          A04X+013769Y-002220X0232Y0252R180S1
+327+3V3             C7    -1          A04X+014151Y-002220X0232Y0252R180S1
+327GND              C6    -2          A04X+009360Y-008111X0232Y0252R090S1
+327+3V3             C6    -1          A04X+009360Y-007729X0232Y0252R090S1
+327GND              C5    -2          A04X+010682Y-012370X0232Y0252R000S1
+327+3V3             C5    -1          A04X+010300Y-012370X0232Y0252R000S1
+327GND              C4    -2          A04X+019940Y-004339X0232Y0252R270S1
+327+3V3             C4    -1          A04X+019940Y-004721X0232Y0252R270S1
+327GND              C3    -2          A04X+009070Y-005259X0232Y0252R270S1
+327+3V3             C3    -1          A04X+009070Y-005641X0232Y0252R270S1
+327GND              C2    -2          A04X+019000Y-012849X0232Y0252R270S1
+327+3V3             C2    -1          A04X+019000Y-013231X0232Y0252R270S1
+327GND              C1    -2          A04X+009459Y-011590X0232Y0252R180S1
+327+3V3             C1    -1          A04X+009841Y-011590X0232Y0252R180S1
+327NET-(D8-PAD2)    R9    -1          A04X+014710Y-000659X0232Y0252R090S1
+327+3V3             R9    -2          A04X+014710Y-001041X0232Y0252R090S1
+327NET-(D7-PAD2)    R8    -1          A04X+015090Y-000659X0232Y0252R090S1
+327+3V3             R8    -2          A04X+015090Y-001041X0232Y0252R090S1
+327NET-(D6-PAD2)    R7    -1          A04X+015480Y-000659X0232Y0252R090S1
+327+3V3             R7    -2          A04X+015480Y-001041X0232Y0252R090S1
+327NET-(D5-PAD2)    R6    -1          A04X+015860Y-000659X0232Y0252R090S1
+327+3V3             R6    -2          A04X+015860Y-001041X0232Y0252R090S1
+327NET-(D4-PAD2)    R5    -1          A04X+016250Y-000659X0232Y0252R090S1
+327+3V3             R5    -2          A04X+016250Y-001041X0232Y0252R090S1
+327NET-(D3-PAD2)    R4    -1          A04X+016640Y-000659X0232Y0252R090S1
+327+3V3             R4    -2          A04X+016640Y-001041X0232Y0252R090S1
+327NET-(D2-PAD2)    R3    -1          A04X+017030Y-000659X0232Y0252R090S1
+327+3V3             R3    -2          A04X+017030Y-001041X0232Y0252R090S1
+327NET-(D1-PAD2)    R2    -1          A04X+017420Y-000659X0232Y0252R090S1
+327+3V3             R2    -2          A04X+017420Y-001041X0232Y0252R090S1
+327NET-(D8-PAD2)    D8    -2          A01X+014670Y-000649X0232Y0252R270S2
+327LED7             D8    -1          A01X+014670Y-001031X0232Y0252R270S2
+327LED6             D7    -1          A01X+015060Y-001031X0232Y0252R270S2
+327NET-(D7-PAD2)    D7    -2          A01X+015060Y-000649X0232Y0252R270S2
+327LED5             D6    -1          A01X+015450Y-001031X0232Y0252R270S2
+327NET-(D6-PAD2)    D6    -2          A01X+015450Y-000649X0232Y0252R270S2
+327LED4             D5    -1          A01X+015840Y-001031X0232Y0252R270S2
+327NET-(D5-PAD2)    D5    -2          A01X+015840Y-000649X0232Y0252R270S2
+327LED3             D4    -1          A01X+016230Y-001031X0232Y0252R270S2
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new file mode 100644
index 0000000..4233652
--- /dev/null
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+drill  0.000000
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+$EndPAD
+$EndMODULE  R8
+
+$MODULE "R7"
+reference "R7"
+value "330"
+footprint "Resistor_SMD:R_0402_1005Metric"
+attribut smd
+position 152.171400 36.703000  orientation 270.00
+layer back
+$PAD "1"
+Shape Roundrect Layer back
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+drill  0.000000
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+$EndPAD
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+$MODULE "R6"
+reference "R6"
+value "330"
+footprint "Resistor_SMD:R_0402_1005Metric"
+attribut smd
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+layer back
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+Shape Roundrect Layer back
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+$EndPAD
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+$MODULE "R5"
+reference "R5"
+value "330"
+footprint "Resistor_SMD:R_0402_1005Metric"
+attribut smd
+position 154.127200 36.703000  orientation 270.00
+layer back
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+Shape Roundrect Layer back
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+drill  0.000000
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+$EndPAD
+$EndMODULE  R5
+
+$MODULE "R4"
+reference "R4"
+value "330"
+footprint "Resistor_SMD:R_0402_1005Metric"
+attribut smd
+position 155.117800 36.703000  orientation 270.00
+layer back
+$PAD "1"
+Shape Roundrect Layer back
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+drill  0.000000
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+$EndPAD
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+Shape Roundrect Layer back
+position  0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$EndMODULE  R4
+
+$MODULE "R3"
+reference "R3"
+value "330"
+footprint "Resistor_SMD:R_0402_1005Metric"
+attribut smd
+position 156.108400 36.703000  orientation 270.00
+layer back
+$PAD "1"
+Shape Roundrect Layer back
+position -0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
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+Shape Roundrect Layer back
+position  0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$EndMODULE  R3
+
+$MODULE "R2"
+reference "R2"
+value "330"
+footprint "Resistor_SMD:R_0402_1005Metric"
+attribut smd
+position 157.099000 36.703000  orientation 270.00
+layer back
+$PAD "1"
+Shape Roundrect Layer back
+position -0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
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+Shape Roundrect Layer back
+position  0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$EndMODULE  R2
+
+$MODULE "D8"
+reference "D8"
+value "LED"
+footprint "LED_SMD:LED_0402_1005Metric"
+attribut smd
+position 150.114000 36.677600  orientation 90.00
+layer front
+$PAD "2"
+Shape Roundrect Layer front
+position  0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$PAD "1"
+Shape Roundrect Layer front
+position -0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$EndMODULE  D8
+
+$MODULE "D7"
+reference "D7"
+value "LED"
+footprint "LED_SMD:LED_0402_1005Metric"
+attribut smd
+position 151.104600 36.677600  orientation 90.00
+layer front
+$PAD "1"
+Shape Roundrect Layer front
+position -0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$PAD "2"
+Shape Roundrect Layer front
+position  0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$EndMODULE  D7
+
+$MODULE "D6"
+reference "D6"
+value "LED"
+footprint "LED_SMD:LED_0402_1005Metric"
+attribut smd
+position 152.095200 36.677600  orientation 90.00
+layer front
+$PAD "1"
+Shape Roundrect Layer front
+position -0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$PAD "2"
+Shape Roundrect Layer front
+position  0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$EndMODULE  D6
+
+$MODULE "D5"
+reference "D5"
+value "LED"
+footprint "LED_SMD:LED_0402_1005Metric"
+attribut smd
+position 153.085800 36.677600  orientation 90.00
+layer front
+$PAD "1"
+Shape Roundrect Layer front
+position -0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$PAD "2"
+Shape Roundrect Layer front
+position  0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$EndMODULE  D5
+
+$MODULE "D4"
+reference "D4"
+value "LED"
+footprint "LED_SMD:LED_0402_1005Metric"
+attribut smd
+position 154.076400 36.677600  orientation 90.00
+layer front
+$PAD "1"
+Shape Roundrect Layer front
+position -0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$PAD "2"
+Shape Roundrect Layer front
+position  0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$EndMODULE  D4
+
+$MODULE "D3"
+reference "D3"
+value "LED"
+footprint "LED_SMD:LED_0402_1005Metric"
+attribut smd
+position 155.067000 36.677600  orientation 90.00
+layer front
+$PAD "1"
+Shape Roundrect Layer front
+position -0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$PAD "2"
+Shape Roundrect Layer front
+position  0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$EndMODULE  D3
+
+$MODULE "D2"
+reference "D2"
+value "LED"
+footprint "LED_SMD:LED_0402_1005Metric"
+attribut smd
+position 156.083000 36.677600  orientation 90.00
+layer front
+$PAD "1"
+Shape Roundrect Layer front
+position -0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$PAD "2"
+Shape Roundrect Layer front
+position  0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$EndMODULE  D2
+
+$MODULE "D1"
+reference "D1"
+value "LED"
+footprint "LED_SMD:LED_0402_1005Metric"
+attribut smd
+position 157.073600 36.677600  orientation 90.00
+layer front
+$PAD "1"
+Shape Roundrect Layer front
+position -0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$PAD "2"
+Shape Roundrect Layer front
+position  0.485000  0.000000  size  0.590000  0.640000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$EndMODULE  D1
+
+$MODULE "U2"
+reference "U2"
+value "W25Q128JVS"
+footprint "Package_SO:SOIC-8_5.23x5.23mm_P1.27mm"
+attribut smd
+position 158.369000 74.828400  orientation 90.00
+layer back
+$PAD "8"
+Shape Roundrect Layer back
+position  3.600000  1.905000  size  1.600000  0.600000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$PAD "7"
+Shape Roundrect Layer back
+position  3.600000  0.635000  size  1.600000  0.600000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$PAD "6"
+Shape Roundrect Layer back
+position  3.600000 -0.635000  size  1.600000  0.600000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$PAD "5"
+Shape Roundrect Layer back
+position  3.600000 -1.905000  size  1.600000  0.600000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$PAD "4"
+Shape Roundrect Layer back
+position -3.600000 -1.905000  size  1.600000  0.600000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$PAD "3"
+Shape Roundrect Layer back
+position -3.600000 -0.635000  size  1.600000  0.600000  orientation 0.00
+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
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+Shape Roundrect Layer back
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+drill  0.000000
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+$EndPAD
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+Shape Roundrect Layer back
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+drill  0.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$EndMODULE  U2
+
+$MODULE "J1"
+reference "J1"
+value "Conn_01x06_Female"
+footprint "Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical"
+attribut none
+position 124.053600 42.240200  orientation 0.00
+layer front
+$PAD "6"
+Shape Oval Layer both
+position  0.000000 12.700000  size  1.700000  1.700000  orientation 0.00
+drill  1.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$PAD "5"
+Shape Oval Layer both
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+drill  1.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$PAD "4"
+Shape Oval Layer both
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+drill  1.000000
+shape_offset  0.000000  0.000000
+$EndPAD
+$PAD "3"
+Shape Oval Layer both
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+drill  1.000000
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+$EndPAD
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+Shape Oval Layer both
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+$EndPAD
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+Shape Rect Layer both
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+$EndPAD
+$EndMODULE  J1
+
+$EndDESCRIPTION
diff --git a/MCL86jr/PCBA/Fabrication_Products2/MCL86jr_BOM.txt b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr_BOM.txt
new file mode 100644
index 0000000..29d696e
--- /dev/null
+++ b/MCL86jr/PCBA/Fabrication_Products2/MCL86jr_BOM.txt
@@ -0,0 +1,31 @@
+
+BOM
+----
+
+Special instructions:
+----------------------
+1) Dont stuff header  J1
+2) Dont stuff header  U9 Can be purchased here: http://store.go4retro.com/ic-header/
+
+
+    Description                                     Vendor      Part number                             Price   Quantity  Reference     
+---------------------------------------------------------------------------------------------------------------------------------------  
+    CAP CER 4.7UF 10V X5R 0402                      Digikey     1276-1482-1-ND                          $ 0.04      31    C31,C30,C29,C28,C23,C27,C26,C25,C19,C18,C17,C16,C24,C22,C21,C20,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1        
+    RES 33 OHM 1% 1/16W 0402                        Digikey     541-3968-1-ND                           $ 0.10      2     R1,R16            
+    RES SMD 4.7K OHM 5% 1/16W 0402                  Digikey     1276-4392-1-ND                          $ 0.01      6     R15,R14,R13,R12,R11,R10           
+    RES 330 OHM 1% 1/16W 0402                       Digikey     541-3996-1-ND                           $ 0.10      8     R9,R8,R7,R6,R5,R4,R3,R2           
+    LED RED CLEAR 2SMD                              Digikey     1080-EAST1005RA0CT-ND                   $ 0.20      8     D8,D7,D6,D5,D4,D3,D2,D1           
+
+    512x8 SRAM-CY62148GN-45ZSXI                     Mouser      727-CY62148GN-45ZSXI                    $ 4.92      1     U8            
+    Clock Oscillators 50MHz 3.3V 50ppm              Mouser      S774-625L3C050M00000                    $ 1.63      1     Y1            
+    IC REG LINEAR 1.2V 300MA SOT23-5                Digikey     576-4878-1-ND                           $ 0.11      1     U7            
+    IC REG LINEAR 3.3V 300MA SOT23-5                Digikey     576-4764-1-ND                           $ 0.11      1     U3            
+    IC TXRX NON-INVERT 3.6V 20TSSOP                 Digikey     296-26610-5-ND                          $ 0.57      3     U6,U5,U4          
+    IC FPGA 102 I/O 144TQFP                         Digikey     122-1747-ND                             $ 18.70     1     U1            
+    IC FLASH 128M SPI 133MHZ 8SOIC                  Digikey     W25Q128JVSIQ-ND                         $ 1.37      1     U2            
+    
+    
+    
+    
+    
+
diff --git a/MCL86jr/PCBA/MCL86jr b/MCL86jr/PCBA/MCL86jr
new file mode 100644
index 0000000..b066094
--- /dev/null
+++ b/MCL86jr/PCBA/MCL86jr
@@ -0,0 +1,15 @@
+Reference, Quantity, Value, Footprint, Datasheet, Field4, Field5, Field6
+C1 C3 C5 C14 C9 C10 C8 C7 C6 C4 C15 C13 C12 C11 C2 C25 C26 C27 C28 C30 C29 C20 C21 C17 C19 C18 C16 C23 C24 C22 ,30,"4.7uF","Capacitor_SMD:C_0402_1005Metric","~"
+D1 D2 D3 D4 D5 D6 D7 D8 ,8,"LED","LED_SMD:LED_0402_1005Metric","~"
+J1 ,1,"Conn_01x06_Female","Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical","~"
+R1 R16 ,2,"33","Resistor_SMD:R_0402_1005Metric","~"
+R10 R11 R14 R12 R13 R15 ,6,"4.7k","Resistor_SMD:R_0402_1005Metric","~"
+R2 R3 R4 R5 R6 R7 R8 R9 ,8,"330","Resistor_SMD:R_0402_1005Metric","~"
+U1 ,1,"XC6SLX9-TQG144","Package_QFP:TQFP-144_20x20mm_P0.5mm",""
+U2 ,1,"W25Q128JVS","Package_SO:SOIC-8_5.23x5.23mm_P1.27mm","http://www.winbond.com/resource-files/w25q128jv_dtr%20revc%2003272018%20plus.pdf"
+U3 ,1,"MIC5504-3.3YM5-TR","SOT23-5P95_280X145XL45X37N","MICREL"
+U4 U5 U6 ,3,"SN74LVC245APW","SOP65P640X120-20N",""
+U7 ,1,"MIC5504-1.2YM5-TR","SOT23-5P95_280X145XL45X37N","MICREL"
+U8 ,1,"CY62148GN-45ZSXI","SOIC127P1176X120-32N","Cypress Semiconductor","SOIC127P1176X120-32N","",""
+U9 ,1,"8088_Min_Mode","Package_DIP:DIP-40_W15.24mm","http://datasheets.chipdb.org/Intel/x86/808x/datashts/8088/231456-006.pdf"
+Y1 ,1,"100Mhz","OSC_SIT8008BI-13-33E-33.333330E","Manufacturer Recommendations","1.04","0.8mm","SiTime"
\ No newline at end of file
diff --git a/MCL86jr/PCBA/MCL86jr-cache.lib b/MCL86jr/PCBA/MCL86jr-cache.lib
new file mode 100644
index 0000000..b20c31c
--- /dev/null
+++ b/MCL86jr/PCBA/MCL86jr-cache.lib
@@ -0,0 +1,520 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# CY62148GN-45ZSXI_CY62148GN-45ZSXI
+#
+DEF CY62148GN-45ZSXI_CY62148GN-45ZSXI U 0 40 Y Y 1 L N
+F0 "U" -500 1339 50 H V L BNN
+F1 "CY62148GN-45ZSXI_CY62148GN-45ZSXI" -500 -1457 50 H V L BNN
+F2 "SOIC127P1176X120-32N" 0 0 50 H I L BNN
+F3 "Cypress Semiconductor" 0 0 50 H I L BNN
+F4 "SOIC127P1176X120-32N" 0 0 50 H I L BNN
+DRAW
+P 2 0 0 16 -500 -1300 -500 1300 N
+P 2 0 0 16 -500 1300 500 1300 N
+P 2 0 0 16 500 -1300 -500 -1300 N
+P 2 0 0 16 500 1300 500 -1300 N
+X A17 1 700 200 200 L 40 40 0 0 B
+X A2 10 -700 800 200 R 40 40 0 0 B
+X A1 11 -700 900 200 R 40 40 0 0 B
+X A0 12 -700 1000 200 R 40 40 0 0 B
+X D0 13 -700 -300 200 R 40 40 0 0 B
+X D1 14 -700 -400 200 R 40 40 0 0 B
+X D2 15 -700 -500 200 R 40 40 0 0 B
+X GND 16 700 -1200 200 L 40 40 0 0 W
+X D3 17 -700 -600 200 R 40 40 0 0 B
+X D4 18 700 -300 200 L 40 40 0 0 B
+X D5 19 700 -400 200 L 40 40 0 0 B
+X A16 2 700 300 200 L 40 40 0 0 B
+X D6 20 700 -500 200 L 40 40 0 0 B
+X D7 21 700 -600 200 L 40 40 0 0 B
+X CE_N 22 -700 -100 200 R 40 40 0 0 B
+X A10 23 700 900 200 L 40 40 0 0 B
+X OE_N 24 -700 -800 200 R 40 40 0 0 B
+X A11 25 700 800 200 L 40 40 0 0 B
+X A9 26 700 1000 200 L 40 40 0 0 B
+X A8 27 -700 200 200 R 40 40 0 0 B
+X A13 28 700 600 200 L 40 40 0 0 B
+X WE_N 29 -700 -1000 200 R 40 40 0 0 B
+X A14 3 700 500 200 L 40 40 0 0 B
+X A18 30 700 100 200 L 40 40 0 0 B
+X A15 31 700 400 200 L 40 40 0 0 B
+X VCC 32 700 1200 200 L 40 40 0 0 W
+X A12 4 700 700 200 L 40 40 0 0 B
+X A7 5 -700 300 200 R 40 40 0 0 B
+X A6 6 -700 400 200 R 40 40 0 0 B
+X A5 7 -700 500 200 R 40 40 0 0 B
+X A4 8 -700 600 200 R 40 40 0 0 B
+X A3 9 -700 700 200 R 40 40 0 0 B
+ENDDRAW
+ENDDEF
+#
+# Connector_Conn_01x06_Female
+#
+DEF Connector_Conn_01x06_Female J 0 40 Y N 1 F N
+F0 "J" 0 300 50 H V C CNN
+F1 "Connector_Conn_01x06_Female" 0 -400 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*_1x??_*
+$ENDFPLIST
+DRAW
+A 0 -300 20 901 -901 1 1 6 N 0 -280 0 -320
+A 0 -200 20 901 -901 1 1 6 N 0 -180 0 -220
+A 0 -100 20 901 -901 1 1 6 N 0 -80 0 -120
+A 0 0 20 901 -901 1 1 6 N 0 20 0 -20
+A 0 100 20 901 -901 1 1 6 N 0 120 0 80
+A 0 200 20 901 -901 1 1 6 N 0 220 0 180
+P 2 1 1 6 -50 -300 -20 -300 N
+P 2 1 1 6 -50 -200 -20 -200 N
+P 2 1 1 6 -50 -100 -20 -100 N
+P 2 1 1 6 -50 0 -20 0 N
+P 2 1 1 6 -50 100 -20 100 N
+P 2 1 1 6 -50 200 -20 200 N
+X Pin_1 1 -200 200 150 R 50 50 1 1 P
+X Pin_2 2 -200 100 150 R 50 50 1 1 P
+X Pin_3 3 -200 0 150 R 50 50 1 1 P
+X Pin_4 4 -200 -100 150 R 50 50 1 1 P
+X Pin_5 5 -200 -200 150 R 50 50 1 1 P
+X Pin_6 6 -200 -300 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_C_Small
+#
+DEF Device_C_Small C 0 10 N N 1 F N
+F0 "C" 10 70 50 H V L CNN
+F1 "Device_C_Small" 10 -80 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 13 -60 -20 60 -20 N
+P 2 0 1 12 -60 20 60 20 N
+X ~ 1 0 100 80 D 50 50 1 1 P
+X ~ 2 0 -100 80 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_LED
+#
+DEF Device_LED D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "Device_LED" 0 -100 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ LED*
+ LED_SMD:*
+ LED_THT:*
+$ENDFPLIST
+DRAW
+P 2 0 1 8 -50 -50 -50 50 N
+P 2 0 1 0 -50 0 50 0 N
+P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N
+P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
+P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
+X K 1 -150 0 100 R 50 50 1 1 P
+X A 2 150 0 100 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_R_US
+#
+DEF Device_R_US R 0 0 N Y 1 F N
+F0 "R" 100 0 50 V V C CNN
+F1 "Device_R_US" -100 0 50 V V C CNN
+F2 "" 40 -10 50 V I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ R_*
+$ENDFPLIST
+DRAW
+P 2 0 1 0 0 -90 0 -100 N
+P 2 0 1 0 0 90 0 100 N
+P 5 0 1 0 0 -30 40 -45 0 -60 -40 -75 0 -90 N
+P 5 0 1 0 0 30 40 15 0 0 -40 -15 0 -30 N
+P 5 0 1 0 0 90 40 75 0 60 -40 45 0 30 N
+X ~ 1 0 150 50 D 50 50 1 1 P
+X ~ 2 0 -150 50 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# FPGA_Xilinx_Spartan6_XC6SLX9-TQG144
+#
+DEF FPGA_Xilinx_Spartan6_XC6SLX9-TQG144 U 0 40 Y Y 4 L N
+F0 "U" 0 50 50 H V C CNN
+F1 "FPGA_Xilinx_Spartan6_XC6SLX9-TQG144" 0 -50 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+S -1750 1450 1750 -1700 1 1 10 f
+S -1750 1450 1750 -1700 2 1 10 f
+S -1250 600 1250 -600 3 1 10 f
+S -750 700 750 -700 4 1 10 f
+X IO_L33P_1 100 2000 500 250 L 50 50 1 1 B
+X IO_L32N_1 101 2000 600 250 L 50 50 1 1 B
+X IO_L32P_1 102 2000 700 250 L 50 50 1 1 B
+X VCCO_1 103 1600 1700 250 D 50 50 1 1 W
+X IO_L1N_VREF_1 104 2000 800 250 L 50 50 1 1 B
+X IO_L1P_1 105 2000 900 250 L 50 50 1 1 B
+X IO_L66N_SCP0_0 111 -2000 -1600 250 R 50 50 1 1 B
+X IO_L66P_SCP1_0 112 -2000 -1500 250 R 50 50 1 1 B
+X IO_L65N_SCP2_0 114 -2000 -1400 250 R 50 50 1 1 B
+X IO_L65P_SCP3_0 115 -2000 -1300 250 R 50 50 1 1 B
+X IO_L64N_SCP4_0 116 -2000 -1200 250 R 50 50 1 1 B
+X IO_L64P_SCP5_0 117 -2000 -1100 250 R 50 50 1 1 B
+X IO_L63N_SCP6_0 118 -2000 -1000 250 R 50 50 1 1 B
+X IO_L63P_SCP7_0 119 -2000 -900 250 R 50 50 1 1 B
+X IO_L62N_VREF_0 120 -2000 -800 250 R 50 50 1 1 B
+X IO_L62P_0 121 -2000 -700 250 R 50 50 1 1 B
+X VCCO_0 122 -1600 1700 250 D 50 50 1 1 W
+X IO_L37N_GCLK12_0 123 -2000 -600 250 R 50 50 1 1 B
+X IO_L37P_GCLK13_0 124 -2000 -500 250 R 50 50 1 1 B
+X VCCO_0 125 -1500 1700 250 D 50 50 1 1 W
+X IO_L36N_GCLK14_0 126 -2000 -400 250 R 50 50 1 1 B
+X IO_L36P_GCLK15_0 127 -2000 -300 250 R 50 50 1 1 B
+X IO_L35N_GCLK16_0 131 -2000 -200 250 R 50 50 1 1 B
+X IO_L35P_GCLK17_0 132 -2000 -100 250 R 50 50 1 1 B
+X IO_L34N_GCLK18_0 133 -2000 0 250 R 50 50 1 1 B
+X IO_L34P_GCLK19_0 134 -2000 100 250 R 50 50 1 1 B
+X VCCO_0 135 -1400 1700 250 D 50 50 1 1 W
+X IO_L4N_0 137 -2000 200 250 R 50 50 1 1 B
+X IO_L4P_0 138 -2000 300 250 R 50 50 1 1 B
+X IO_L3N_0 139 -2000 400 250 R 50 50 1 1 B
+X IO_L3P_0 140 -2000 500 250 R 50 50 1 1 B
+X IO_L2N_0 141 -2000 600 250 R 50 50 1 1 B
+X IO_L2P_0 142 -2000 700 250 R 50 50 1 1 B
+X IO_L1N_VREF_0 143 -2000 800 250 R 50 50 1 1 B
+X IO_L1P_HSWAPEN_0 144 -2000 900 250 R 50 50 1 1 B
+X IO_L74N_DOUT_BUSY_1 74 2000 -1400 250 L 50 50 1 1 B
+X IO_L74P_AWAKE_1 75 2000 -1300 250 L 50 50 1 1 B
+X VCCO_1 76 1400 1700 250 D 50 50 1 1 W
+X IO_L47N_1 78 2000 -1200 250 L 50 50 1 1 B
+X IO_L47P_1 79 2000 -1100 250 L 50 50 1 1 B
+X IO_L46N_1 80 2000 -1000 250 L 50 50 1 1 B
+X IO_L46P_1 81 2000 -900 250 L 50 50 1 1 B
+X IO_L45N_1 82 2000 -800 250 L 50 50 1 1 B
+X IO_L45P_1 83 2000 -700 250 L 50 50 1 1 B
+X IO_L43N_GCLK4_1 84 2000 -600 250 L 50 50 1 1 B
+X IO_L43P_GCLK5_1 85 2000 -500 250 L 50 50 1 1 B
+X VCCO_1 86 1500 1700 250 D 50 50 1 1 W
+X IO_L42N_GCLK6_TRDY1_1 87 2000 -400 250 L 50 50 1 1 B
+X IO_L42P_GCLK7_1 88 2000 -300 250 L 50 50 1 1 B
+X IO_L41N_GCLK8_1 92 2000 -200 250 L 50 50 1 1 B
+X IO_L41P_GCLK9_IRDY1_1 93 2000 -100 250 L 50 50 1 1 B
+X IO_L40N_GCLK10_1 94 2000 0 250 L 50 50 1 1 B
+X IO_L40P_GCLK11_1 95 2000 100 250 L 50 50 1 1 B
+X IO_L34N_1 97 2000 200 250 L 50 50 1 1 B
+X IO_L34P_1 98 2000 300 250 L 50 50 1 1 B
+X IO_L33N_1 99 2000 400 250 L 50 50 1 1 B
+X IO_L83N_VREF_3 1 2000 -1600 250 L 50 50 2 1 B
+X IO_L50P_3 10 2000 -900 250 L 50 50 2 1 B
+X IO_L49N_3 11 2000 -800 250 L 50 50 2 1 B
+X IO_L49P_3 12 2000 -700 250 L 50 50 2 1 B
+X IO_L44N_GCLK20_3 14 2000 -600 250 L 50 50 2 1 B
+X IO_L44P_GCLK21_3 15 2000 -500 250 L 50 50 2 1 B
+X IO_L43N_GCLK22_IRDY2_3 16 2000 -400 250 L 50 50 2 1 B
+X IO_L43P_GCLK23_3 17 2000 -300 250 L 50 50 2 1 B
+X VCCO_3 18 1500 1700 250 D 50 50 2 1 W
+X IO_L83P_3 2 2000 -1500 250 L 50 50 2 1 B
+X IO_L42N_GCLK24_3 21 2000 -200 250 L 50 50 2 1 B
+X IO_L42P_GCLK25_TRDY2_3 22 2000 -100 250 L 50 50 2 1 B
+X IO_L41N_GCLK26_3 23 2000 0 250 L 50 50 2 1 B
+X IO_L41P_GCLK27_3 24 2000 100 250 L 50 50 2 1 B
+X IO_L37N_3 26 2000 200 250 L 50 50 2 1 B
+X IO_L37P_3 27 2000 300 250 L 50 50 2 1 B
+X IO_L36N_3 29 2000 400 250 L 50 50 2 1 B
+X IO_L36P_3 30 2000 500 250 L 50 50 2 1 B
+X VCCO_3 31 1600 1700 250 D 50 50 2 1 W
+X IO_L2N_3 32 2000 600 250 L 50 50 2 1 B
+X IO_L2P_3 33 2000 700 250 L 50 50 2 1 B
+X IO_L1N_VREF_3 34 2000 800 250 L 50 50 2 1 B
+X IO_L1P_3 35 2000 900 250 L 50 50 2 1 B
+X IO_L65N_CSO_B_2 38 -2000 -1600 250 R 50 50 2 1 B
+X IO_L65P_INIT_B_2 39 -2000 -1500 250 R 50 50 2 1 B
+X VCCO_3 4 1400 1700 250 D 50 50 2 1 W
+X IO_L64N_D9_2 40 -2000 -1400 250 R 50 50 2 1 B
+X IO_L64P_D8_2 41 -2000 -1300 250 R 50 50 2 1 B
+X VCCO_2 42 -1600 1700 250 D 50 50 2 1 W
+X IO_L62N_D6_2 43 -2000 -1200 250 R 50 50 2 1 B
+X IO_L62P_D5_2 44 -2000 -1100 250 R 50 50 2 1 B
+X IO_L49N_D4_2 45 -2000 -1000 250 R 50 50 2 1 B
+X IO_L49P_D3_2 46 -2000 -900 250 R 50 50 2 1 B
+X IO_L48N_RDWR_B_VREF_2 47 -2000 -800 250 R 50 50 2 1 B
+X IO_L48P_D7_2 48 -2000 -700 250 R 50 50 2 1 B
+X IO_L52N_3 5 2000 -1400 250 L 50 50 2 1 B
+X IO_L31N_GCLK30_D15_2 50 -2000 -600 250 R 50 50 2 1 B
+X IO_L31P_GCLK31_D14_2 51 -2000 -500 250 R 50 50 2 1 B
+X IO_L30N_GCLK0_USERCCLK_2 55 -2000 -400 250 R 50 50 2 1 B
+X IO_L30P_GCLK1_D13_2 56 -2000 -300 250 R 50 50 2 1 B
+X IO_L14N_D12_2 57 -2000 -200 250 R 50 50 2 1 B
+X IO_L14P_D11_2 58 -2000 -100 250 R 50 50 2 1 B
+X IO_L13N_D10_2 59 -2000 0 250 R 50 50 2 1 B
+X IO_L52P_3 6 2000 -1300 250 L 50 50 2 1 B
+X IO_L13P_M1_2 60 -2000 100 250 R 50 50 2 1 B
+X IO_L12N_D2_MISO3_2 61 -2000 200 250 R 50 50 2 1 B
+X IO_L12P_D1_MISO2_2 62 -2000 300 250 R 50 50 2 1 B
+X VCCO_2 63 -1500 1700 250 D 50 50 2 1 W
+X IO_L3N_MOSI_CSI_B_MISO0_2 64 -2000 400 250 R 50 50 2 1 B
+X IO_L3P_D0_DIN_MISO_MISO1_2 65 -2000 500 250 R 50 50 2 1 B
+X IO_L2N_CMPMOSI_2 66 -2000 600 250 R 50 50 2 1 B
+X IO_L2P_CMPCLK_2 67 -2000 700 250 R 50 50 2 1 B
+X IO_L1N_M0_CMPMISO_2 69 -2000 800 250 R 50 50 2 1 B
+X IO_L51N_3 7 2000 -1200 250 L 50 50 2 1 B
+X IO_L1P_CCLK_2 70 -2000 900 250 R 50 50 2 1 B
+X IO_L51P_3 8 2000 -1100 250 L 50 50 2 1 B
+X IO_L50N_3 9 2000 -1000 250 L 50 50 2 1 B
+X TDO 106 1500 400 250 L 50 50 3 1 B
+X TMS 107 1500 300 250 L 50 50 3 1 B
+X TCK 109 1500 200 250 L 50 50 3 1 B
+X TDI 110 1500 500 250 L 50 50 3 1 B
+X PROGRAM_B_2 37 1500 -100 250 L 50 50 3 1 B
+X DONE_2 71 1500 0 250 L 50 50 3 1 B
+X CMPCS_B_2 72 1500 -500 250 L 50 50 3 1 B
+X SUSPEND 73 1500 -300 250 L 50 50 3 1 B
+X GND 108 1000 -300 250 L 50 50 4 1 W
+X GND 113 1000 -400 250 L 50 50 4 1 W
+X VCCINT 128 1000 200 250 L 50 50 4 1 W
+X VCCAUX 129 -1000 200 250 R 50 50 4 1 W
+X GND 13 -1000 -100 250 R 50 50 4 1 W
+X GND 130 1000 -500 250 L 50 50 4 1 W
+X GND 136 1000 -600 250 L 50 50 4 1 W
+X VCCINT 19 1000 600 250 L 50 50 4 1 W
+X VCCAUX 20 -1000 600 250 R 50 50 4 1 W
+X GND 25 -1000 -200 250 R 50 50 4 1 W
+X VCCINT 28 1000 500 250 L 50 50 4 1 W
+X GND 3 -1000 0 250 R 50 50 4 1 W
+X VCCAUX 36 -1000 500 250 R 50 50 4 1 W
+X GND 49 -1000 -300 250 R 50 50 4 1 W
+X VCCINT 52 1000 400 250 L 50 50 4 1 W
+X VCCAUX 53 -1000 400 250 R 50 50 4 1 W
+X GND 54 -1000 -400 250 R 50 50 4 1 W
+X GND 68 -1000 -500 250 R 50 50 4 1 W
+X GND 77 -1000 -600 250 R 50 50 4 1 W
+X VCCINT 89 1000 300 250 L 50 50 4 1 W
+X VCCAUX 90 -1000 300 250 R 50 50 4 1 W
+X GND 91 1000 -100 250 L 50 50 4 1 W
+X GND 96 1000 -200 250 L 50 50 4 1 W
+ENDDRAW
+ENDDEF
+#
+# MCU_Intel_8088_Min_Mode
+#
+DEF MCU_Intel_8088_Min_Mode U 0 40 Y Y 1 F N
+F0 "U" -500 1700 50 H V C CNN
+F1 "MCU_Intel_8088_Min_Mode" 400 1700 50 H V C CNN
+F2 "Package_DIP:DIP-40_W15.24mm" 50 100 50 H I C CIN
+F3 "" 0 50 50 H I C CNN
+ALIAS 8088_Min_Mode
+$FPLIST
+ DIP*W15.24mm*
+$ENDFPLIST
+DRAW
+S 550 -1650 -550 1650 0 1 10 f
+X GND 1 -100 -1800 150 U 50 50 1 1 W
+X AD6 10 700 500 150 L 50 50 1 1 B
+X AD5 11 700 600 150 L 50 50 1 1 B
+X AD4 12 700 700 150 L 50 50 1 1 B
+X AD3 13 700 800 150 L 50 50 1 1 B
+X AD2 14 700 900 150 L 50 50 1 1 B
+X AD1 15 700 1000 150 L 50 50 1 1 B
+X AD0 16 700 1100 150 L 50 50 1 1 B
+X NMI 17 -700 900 150 R 50 50 1 1 I
+X INTR 18 -700 700 150 R 50 50 1 1 I
+X CLK 19 -700 1500 150 R 50 50 1 1 I C
+X A14 2 700 -400 150 L 50 50 1 1 O
+X GND 20 100 -1800 150 U 50 50 1 1 W
+X RESET 21 -700 1100 150 R 50 50 1 1 I
+X READY 22 -700 1300 150 R 50 50 1 1 I
+X ~TEST~ 23 -700 -300 150 R 50 50 1 1 I
+X ~INTA~ 24 -700 500 150 R 50 50 1 1 O
+X ALE 25 700 1300 150 L 50 50 1 1 O
+X DEN 26 700 1400 150 L 50 50 1 1 O
+X DT/~R~ 27 700 1500 150 L 50 50 1 1 O
+X IO/~M~ 28 700 -1200 150 L 50 50 1 1 O
+X WR 29 700 -1300 150 L 50 50 1 1 O
+X A13 3 700 -300 150 L 50 50 1 1 O
+X HLDA 30 -700 300 150 R 50 50 1 1 O
+X HOLD 31 -700 100 150 R 50 50 1 1 I
+X ~RD~ 32 700 -1400 150 L 50 50 1 1 O V
+X MN/~MX~ 33 -700 -500 150 R 50 50 1 1 I
+X ~SSO~ 34 -700 -100 150 R 50 50 1 1 O
+X A19/S6 35 700 -1000 150 L 50 50 1 1 O
+X A18/S5 36 700 -900 150 L 50 50 1 1 O
+X A17/S4 37 700 -800 150 L 50 50 1 1 O
+X A16/S3 38 700 -700 150 L 50 50 1 1 O
+X A15 39 700 -500 150 L 50 50 1 1 O
+X A12 4 700 -200 150 L 50 50 1 1 O
+X VCC 40 0 1800 150 D 50 50 1 1 W
+X A11 5 700 -100 150 L 50 50 1 1 O
+X A10 6 700 0 150 L 50 50 1 1 O
+X A9 7 700 100 150 L 50 50 1 1 O
+X A8 8 700 200 150 L 50 50 1 1 O
+X AD7 9 700 400 150 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# MIC5504-1.2YM5-TR_MIC5504-1.2YM5-TR
+#
+DEF MIC5504-1.2YM5-TR_MIC5504-1.2YM5-TR U 0 40 Y Y 1 L N
+F0 "U" -301 321 50 H V L BNN
+F1 "MIC5504-1.2YM5-TR_MIC5504-1.2YM5-TR" -300 -401 50 H V L BNN
+F2 "SOT23-5P95_280X145XL45X37N" 0 0 50 H I L BNN
+F3 "MICREL" 0 0 50 H I L BNN
+DRAW
+P 2 0 0 10 -300 -300 300 -300 N
+P 2 0 0 10 -300 300 -300 -300 N
+P 2 0 0 10 300 -300 300 300 N
+P 2 0 0 10 300 300 -300 300 N
+X VIN 1 400 200 100 L 40 40 0 0 W
+X GND 2 400 -200 100 L 40 40 0 0 W
+X EN 3 -400 200 100 R 40 40 0 0 I
+X VOUT 5 400 0 100 L 40 40 0 0 O
+ENDDRAW
+ENDDEF
+#
+# Memory_Flash_W25Q128JVS
+#
+DEF Memory_Flash_W25Q128JVS U 0 20 Y Y 1 F N
+F0 "U" -350 350 50 H V C CNN
+F1 "Memory_Flash_W25Q128JVS" 300 350 50 H V C CNN
+F2 "Package_SO:SOIC-8_5.23x5.23mm_P1.27mm" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS W25Q128JVS
+$FPLIST
+ SOIC*5.23x5.23mm*P1.27mm*
+$ENDFPLIST
+DRAW
+S -400 300 400 -300 0 1 10 f
+X ~CS 1 -500 100 100 R 50 50 1 1 I
+X DO(IO1) 2 500 100 100 L 50 50 1 1 B
+X IO2 3 500 -100 100 L 50 50 1 1 B
+X GND 4 0 -400 100 U 50 50 1 1 W
+X DI(IO0) 5 500 200 100 L 50 50 1 1 B
+X CLK 6 -500 -100 100 R 50 50 1 1 I
+X IO3 7 500 -200 100 L 50 50 1 1 B
+X VCC 8 0 400 100 D 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# SIT8008BI-13-33E-33.333330E_SIT8008BI-13-33E-33.333330E
+#
+DEF SIT8008BI-13-33E-33.333330E_SIT8008BI-13-33E-33.333330E Y 0 40 Y Y 1 L N
+F0 "Y" -300 240 50 H V L BNN
+F1 "SIT8008BI-13-33E-33.333330E_SIT8008BI-13-33E-33.333330E" -300 -300 50 H V L BNN
+F2 "OSC_SIT8008BI-13-33E-33.333330E" 0 0 50 H I L BNN
+F3 "Manufacturer Recommendations" 0 0 50 H I L BNN
+F4 "1.04" 0 0 50 H I L BNN
+F5 "0.8mm" 0 0 50 H I L BNN
+F6 "SiTime" 0 0 50 H I L BNN
+DRAW
+P 2 0 0 10 -300 -200 300 -200 N
+P 2 0 0 10 -300 200 -300 -200 N
+P 2 0 0 10 300 -200 300 200 N
+P 2 0 0 10 300 200 -300 200 N
+X OE 1 -500 0 200 R 40 40 0 0 I
+X GND 2 500 -100 200 L 40 40 0 0 W
+X OUT 3 500 0 200 L 40 40 0 0 O
+X VDD 4 500 100 200 L 40 40 0 0 W
+ENDDRAW
+ENDDEF
+#
+# SN74LVC245APW_SN74LVC245APW
+#
+DEF SN74LVC245APW_SN74LVC245APW U 0 40 Y Y 1 L N
+F0 "U" -500 939 50 H V L BNN
+F1 "SN74LVC245APW_SN74LVC245APW" -500 -1057 50 H V L BNN
+F2 "SOP65P640X120-20N" 0 0 50 H I L BNN
+F3 "" 0 0 276 H I C CNN
+DRAW
+P 2 0 0 16 -500 -900 -500 900 N
+P 2 0 0 16 -500 900 500 900 N
+P 2 0 0 16 500 -900 -500 -900 N
+P 2 0 0 16 500 900 500 -900 N
+X DIR 1 -700 500 200 R 40 40 0 0 I
+X GND 10 700 -700 200 L 40 40 0 0 W
+X B8 11 700 -500 200 L 40 40 0 0 B
+X B7 12 700 -400 200 L 40 40 0 0 B
+X B6 13 700 -300 200 L 40 40 0 0 B
+X B5 14 700 -200 200 L 40 40 0 0 B
+X B4 15 -700 -500 200 R 40 40 0 0 B
+X B3 16 -700 -400 200 R 40 40 0 0 B
+X B2 17 -700 -300 200 R 40 40 0 0 B
+X B1 18 -700 -200 200 R 40 40 0 0 B
+X ~OE~ 19 -700 600 200 R 40 40 0 0 I
+X A1 2 -700 300 200 R 40 40 0 0 B
+X VCC 20 700 800 200 L 40 40 0 0 W
+X A2 3 -700 200 200 R 40 40 0 0 B
+X A3 4 -700 100 200 R 40 40 0 0 B
+X A4 5 -700 0 200 R 40 40 0 0 B
+X A5 6 700 300 200 L 40 40 0 0 B
+X A6 7 700 200 200 L 40 40 0 0 B
+X A7 8 700 100 200 L 40 40 0 0 B
+X A8 9 700 0 200 L 40 40 0 0 B
+ENDDRAW
+ENDDEF
+#
+# power_+1V2
+#
+DEF power_+1V2 #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "power_+1V2" 0 140 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +1V2 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# power_+3.3V
+#
+DEF power_+3.3V #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "power_+3.3V" 0 140 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS +3.3V
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +3V3 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# power_+5V
+#
+DEF power_+5V #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "power_+5V" 0 140 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +5V 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# power_GND
+#
+DEF power_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "power_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/MCL86jr/PCBA/MCL86jr.kicad_pcb b/MCL86jr/PCBA/MCL86jr.kicad_pcb
new file mode 100644
index 0000000..b589ce8
--- /dev/null
+++ b/MCL86jr/PCBA/MCL86jr.kicad_pcb
@@ -0,0 +1,6119 @@
+(kicad_pcb (version 20171130) (host pcbnew "(5.1.5)-3")
+
+  (general
+    (thickness 1.6)
+    (drawings 5)
+    (tracks 1434)
+    (zones 0)
+    (modules 66)
+    (nets 127)
+  )
+
+  (page A4)
+  (layers
+    (0 F.Cu signal)
+    (1 In1.Cu power hide)
+    (2 In2.Cu power hide)
+    (31 B.Cu signal)
+    (32 B.Adhes user hide)
+    (33 F.Adhes user hide)
+    (34 B.Paste user hide)
+    (35 F.Paste user hide)
+    (36 B.SilkS user hide)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (41 Cmts.User user)
+    (42 Eco1.User user)
+    (43 Eco2.User user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.2)
+    (trace_clearance 0.2)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.1524)
+    (via_size 0.8)
+    (via_drill 0.4)
+    (via_min_size 0.4)
+    (via_min_drill 0.3)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (edge_width 0.05)
+    (segment_width 0.2)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.12)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.6 1.6)
+    (pad_drill 0.8)
+    (pad_to_mask_clearance 0.051)
+    (solder_mask_min_width 0.25)
+    (aux_axis_origin 112.8522 34.544)
+    (grid_origin 112.8522 34.544)
+    (visible_elements 7FFFFFFF)
+    (pcbplotparams
+      (layerselection 0x010fc_ffffffff)
+      (usegerberextensions false)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin true)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 0)
+      (scaleselection 1)
+      (outputdirectory "Fabrication_Products2/"))
+  )
+
+  (net 0 "")
+  (net 1 "Net-(R1-Pad2)")
+  (net 2 CLK_100MHZ)
+  (net 3 GND)
+  (net 4 +3V3)
+  (net 5 +1V2)
+  (net 6 +5V)
+  (net 7 A15_5V)
+  (net 8 CLK_5V)
+  (net 9 A16_5V)
+  (net 10 INTR_5V)
+  (net 11 A17_5V)
+  (net 12 NMI_5V)
+  (net 13 A18_5V)
+  (net 14 AD0_5V)
+  (net 15 A19_5V)
+  (net 16 AD1_5V)
+  (net 17 SSO_5V)
+  (net 18 AD2_5V)
+  (net 19 AD3_5V)
+  (net 20 RD_5V)
+  (net 21 AD4_5V)
+  (net 22 HOLD_5V)
+  (net 23 AD5_5V)
+  (net 24 HLDA_5V)
+  (net 25 AD6_5V)
+  (net 26 WR_5V)
+  (net 27 AD7_5V)
+  (net 28 IOM_5V)
+  (net 29 A8_5V)
+  (net 30 DTR_5V)
+  (net 31 A9_5V)
+  (net 32 DEN_5V)
+  (net 33 A10_5V)
+  (net 34 ALE_5V)
+  (net 35 A11_5V)
+  (net 36 INTA_n_5V)
+  (net 37 A12_5V)
+  (net 38 A13_5V)
+  (net 39 READY_5V)
+  (net 40 A14_5V)
+  (net 41 RESET_5V)
+  (net 42 SRAM_A15)
+  (net 43 SRAM_A18)
+  (net 44 SRAM_WE_n)
+  (net 45 SRAM_A13)
+  (net 46 SRAM_A8)
+  (net 47 SRAM_A9)
+  (net 48 SRAM_A11)
+  (net 49 SRAM_OE_n)
+  (net 50 SRAM_A10)
+  (net 51 SRAM_CE_n)
+  (net 52 SRAM_D7)
+  (net 53 SRAM_D6)
+  (net 54 SRAM_D5)
+  (net 55 SRAM_D4)
+  (net 56 SRAM_D3)
+  (net 57 SRAM_D2)
+  (net 58 SRAM_D1)
+  (net 59 SRAM_D0)
+  (net 60 SRAM_A0)
+  (net 61 SRAM_A1)
+  (net 62 SRAM_A2)
+  (net 63 SRAM_A3)
+  (net 64 SRAM_A4)
+  (net 65 SRAM_A5)
+  (net 66 SRAM_A7)
+  (net 67 SRAM_A12)
+  (net 68 SRAM_A14)
+  (net 69 SRAM_A16)
+  (net 70 SRAM_A17)
+  (net 71 AD4_3V)
+  (net 72 AD5_3V)
+  (net 73 AD6_3V)
+  (net 74 AD7_3V)
+  (net 75 AD3_3V)
+  (net 76 AD2_3V)
+  (net 77 AD1_3V)
+  (net 78 AD0_3V)
+  (net 79 BUF1_OE__n)
+  (net 80 BUF2_OE__n)
+  (net 81 BUF2_DIR)
+  (net 82 "Net-(J1-Pad5)")
+  (net 83 "Net-(J1-Pad4)")
+  (net 84 "Net-(J1-Pad3)")
+  (net 85 "Net-(J1-Pad2)")
+  (net 86 SPI_CLK)
+  (net 87 SPI_DOUT)
+  (net 88 SPI_DIN)
+  (net 89 SPI_CS_n)
+  (net 90 "Net-(D1-Pad2)")
+  (net 91 LED0)
+  (net 92 "Net-(D2-Pad2)")
+  (net 93 LED1)
+  (net 94 "Net-(D3-Pad2)")
+  (net 95 LED2)
+  (net 96 "Net-(D4-Pad2)")
+  (net 97 LED3)
+  (net 98 "Net-(D5-Pad2)")
+  (net 99 LED4)
+  (net 100 "Net-(D6-Pad2)")
+  (net 101 LED5)
+  (net 102 "Net-(D7-Pad2)")
+  (net 103 LED6)
+  (net 104 "Net-(D8-Pad2)")
+  (net 105 LED7)
+  (net 106 FPGA_M0)
+  (net 107 FPGA_M1)
+  (net 108 FPGA_DONE)
+  (net 109 FPGA_PROGRAM_n)
+  (net 110 FPGA_INIT)
+  (net 111 "Net-(R16-Pad1)")
+  (net 112 HOLD_3V)
+  (net 113 NMI_3V)
+  (net 114 INTR_3V)
+  (net 115 CLK_3V)
+  (net 116 RESET_3V)
+  (net 117 READY_3V)
+  (net 118 ALE_3V)
+  (net 119 HLDA_3V)
+  (net 120 RD_3V)
+  (net 121 INTA_n_3V)
+  (net 122 DEN_3V)
+  (net 123 DTR_3V)
+  (net 124 IOM_3V)
+  (net 125 WR_3V)
+  (net 126 SRAM_A6)
+
+  (net_class Default "This is the default net class."
+    (clearance 0.2)
+    (trace_width 0.2)
+    (via_dia 0.8)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net +1V2)
+    (add_net +3V3)
+    (add_net +5V)
+    (add_net A10_5V)
+    (add_net A11_5V)
+    (add_net A12_5V)
+    (add_net A13_5V)
+    (add_net A14_5V)
+    (add_net A15_5V)
+    (add_net A16_5V)
+    (add_net A17_5V)
+    (add_net A18_5V)
+    (add_net A19_5V)
+    (add_net A8_5V)
+    (add_net A9_5V)
+    (add_net AD0_3V)
+    (add_net AD0_5V)
+    (add_net AD1_3V)
+    (add_net AD1_5V)
+    (add_net AD2_3V)
+    (add_net AD2_5V)
+    (add_net AD3_3V)
+    (add_net AD3_5V)
+    (add_net AD4_3V)
+    (add_net AD4_5V)
+    (add_net AD5_3V)
+    (add_net AD5_5V)
+    (add_net AD6_3V)
+    (add_net AD6_5V)
+    (add_net AD7_3V)
+    (add_net AD7_5V)
+    (add_net ALE_3V)
+    (add_net ALE_5V)
+    (add_net BUF1_OE__n)
+    (add_net BUF2_DIR)
+    (add_net BUF2_OE__n)
+    (add_net CLK_100MHZ)
+    (add_net CLK_3V)
+    (add_net CLK_5V)
+    (add_net DEN_3V)
+    (add_net DEN_5V)
+    (add_net DTR_3V)
+    (add_net DTR_5V)
+    (add_net FPGA_DONE)
+    (add_net FPGA_INIT)
+    (add_net FPGA_M0)
+    (add_net FPGA_M1)
+    (add_net FPGA_PROGRAM_n)
+    (add_net GND)
+    (add_net HLDA_3V)
+    (add_net HLDA_5V)
+    (add_net HOLD_3V)
+    (add_net HOLD_5V)
+    (add_net INTA_n_3V)
+    (add_net INTA_n_5V)
+    (add_net INTR_3V)
+    (add_net INTR_5V)
+    (add_net IOM_3V)
+    (add_net IOM_5V)
+    (add_net LED0)
+    (add_net LED1)
+    (add_net LED2)
+    (add_net LED3)
+    (add_net LED4)
+    (add_net LED5)
+    (add_net LED6)
+    (add_net LED7)
+    (add_net NMI_3V)
+    (add_net NMI_5V)
+    (add_net "Net-(D1-Pad2)")
+    (add_net "Net-(D2-Pad2)")
+    (add_net "Net-(D3-Pad2)")
+    (add_net "Net-(D4-Pad2)")
+    (add_net "Net-(D5-Pad2)")
+    (add_net "Net-(D6-Pad2)")
+    (add_net "Net-(D7-Pad2)")
+    (add_net "Net-(D8-Pad2)")
+    (add_net "Net-(J1-Pad2)")
+    (add_net "Net-(J1-Pad3)")
+    (add_net "Net-(J1-Pad4)")
+    (add_net "Net-(J1-Pad5)")
+    (add_net "Net-(R1-Pad2)")
+    (add_net "Net-(R16-Pad1)")
+    (add_net RD_3V)
+    (add_net RD_5V)
+    (add_net READY_3V)
+    (add_net READY_5V)
+    (add_net RESET_3V)
+    (add_net RESET_5V)
+    (add_net SPI_CLK)
+    (add_net SPI_CS_n)
+    (add_net SPI_DIN)
+    (add_net SPI_DOUT)
+    (add_net SRAM_A0)
+    (add_net SRAM_A1)
+    (add_net SRAM_A10)
+    (add_net SRAM_A11)
+    (add_net SRAM_A12)
+    (add_net SRAM_A13)
+    (add_net SRAM_A14)
+    (add_net SRAM_A15)
+    (add_net SRAM_A16)
+    (add_net SRAM_A17)
+    (add_net SRAM_A18)
+    (add_net SRAM_A2)
+    (add_net SRAM_A3)
+    (add_net SRAM_A4)
+    (add_net SRAM_A5)
+    (add_net SRAM_A6)
+    (add_net SRAM_A7)
+    (add_net SRAM_A8)
+    (add_net SRAM_A9)
+    (add_net SRAM_CE_n)
+    (add_net SRAM_D0)
+    (add_net SRAM_D1)
+    (add_net SRAM_D2)
+    (add_net SRAM_D3)
+    (add_net SRAM_D4)
+    (add_net SRAM_D5)
+    (add_net SRAM_D6)
+    (add_net SRAM_D7)
+    (add_net SRAM_OE_n)
+    (add_net SRAM_WE_n)
+    (add_net SSO_5V)
+    (add_net WR_3V)
+    (add_net WR_5V)
+  )
+
+  (module SIT8008BI-13-33E-33:OSC_SIT8008BI-13-33E-33.333330E (layer F.Cu) (tedit 5F5FD094) (tstamp 5F632188)
+    (at 160.274 67.7926 90)
+    (path /5F609430/5F7DBEF0)
+    (attr smd)
+    (fp_text reference Y1 (at 0.975 -2.235 90) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.015)))
+    )
+    (fp_text value 100Mhz (at 17.085 2.165 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.015)))
+    )
+    (fp_circle (center -2.2 0.8) (end -2.05 0.8) (layer F.SilkS) (width 0.2))
+    (fp_line (start -1.75 1.5) (end -1.75 -1.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.75 1.5) (end -1.75 1.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.75 -1.5) (end 1.75 1.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.75 -1.5) (end 1.75 -1.5) (layer F.CrtYd) (width 0.05))
+    (fp_circle (center -2.2 0.8) (end -2.05 0.8) (layer F.Fab) (width 0.2))
+    (fp_line (start 1.25 -1) (end -1.25 -1) (layer F.Fab) (width 0.127))
+    (fp_line (start 1.25 1) (end 1.25 -1) (layer F.Fab) (width 0.127))
+    (fp_line (start -1.25 1) (end 1.25 1) (layer F.Fab) (width 0.127))
+    (fp_line (start -1.25 -1) (end -1.25 1) (layer F.Fab) (width 0.127))
+    (pad 4 smd rect (at -0.95 -0.75 90) (size 1.1 1) (layers F.Cu F.Paste F.Mask)
+      (net 4 +3V3))
+    (pad 3 smd rect (at 0.95 -0.75 90) (size 1.1 1) (layers F.Cu F.Paste F.Mask)
+      (net 1 "Net-(R1-Pad2)"))
+    (pad 2 smd rect (at 0.95 0.75 90) (size 1.1 1) (layers F.Cu F.Paste F.Mask)
+      (net 3 GND))
+    (pad 1 smd rect (at -0.95 0.75 90) (size 1.1 1) (layers F.Cu F.Paste F.Mask)
+      (net 4 +3V3))
+  )
+
+  (module CY62148GN-45ZSXI:SOIC127P1176X120-32N (layer F.Cu) (tedit 5F603937) (tstamp 5F613C2A)
+    (at 151.8412 79.6036 270)
+    (path /5F62178D/5F64044A)
+    (attr smd)
+    (fp_text reference U8 (at -3.41 -11.352 90) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.015)))
+    )
+    (fp_text value CY62148GN-45ZSXI (at 8.8392 2.2352) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.015)))
+    )
+    (fp_line (start 6.59 -10.79) (end 6.59 10.79) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -6.59 -10.79) (end -6.59 10.79) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -6.59 10.79) (end 6.59 10.79) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -6.59 -10.79) (end 6.59 -10.79) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 5.145 -10.54) (end 5.145 10.54) (layer F.Fab) (width 0.127))
+    (fp_line (start -5.145 -10.54) (end -5.145 10.54) (layer F.Fab) (width 0.127))
+    (fp_line (start -5.145 10.54) (end 5.145 10.54) (layer F.SilkS) (width 0.127))
+    (fp_line (start -5.145 -10.54) (end 5.145 -10.54) (layer F.SilkS) (width 0.127))
+    (fp_line (start -5.145 10.54) (end 5.145 10.54) (layer F.Fab) (width 0.127))
+    (fp_line (start -5.145 -10.54) (end 5.145 -10.54) (layer F.Fab) (width 0.127))
+    (fp_circle (center -7.06 -10.135) (end -6.96 -10.135) (layer F.Fab) (width 0.2))
+    (fp_circle (center -7.06 -10.135) (end -6.96 -10.135) (layer F.SilkS) (width 0.2))
+    (pad 32 smd rect (at 5.62 -9.525 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 4 +3V3))
+    (pad 31 smd rect (at 5.62 -8.255 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 42 SRAM_A15))
+    (pad 30 smd rect (at 5.62 -6.985 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 43 SRAM_A18))
+    (pad 29 smd rect (at 5.62 -5.715 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 44 SRAM_WE_n))
+    (pad 28 smd rect (at 5.62 -4.445 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 45 SRAM_A13))
+    (pad 27 smd rect (at 5.62 -3.175 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 46 SRAM_A8))
+    (pad 26 smd rect (at 5.62 -1.905 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 47 SRAM_A9))
+    (pad 25 smd rect (at 5.62 -0.635 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 48 SRAM_A11))
+    (pad 24 smd rect (at 5.62 0.635 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 49 SRAM_OE_n))
+    (pad 23 smd rect (at 5.62 1.905 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 50 SRAM_A10))
+    (pad 22 smd rect (at 5.62 3.175 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 51 SRAM_CE_n))
+    (pad 21 smd rect (at 5.62 4.445 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 52 SRAM_D7))
+    (pad 20 smd rect (at 5.62 5.715 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 53 SRAM_D6))
+    (pad 19 smd rect (at 5.62 6.985 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 54 SRAM_D5))
+    (pad 18 smd rect (at 5.62 8.255 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 55 SRAM_D4))
+    (pad 17 smd rect (at 5.62 9.525 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 56 SRAM_D3))
+    (pad 16 smd rect (at -5.62 9.525 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 3 GND))
+    (pad 15 smd rect (at -5.62 8.255 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 57 SRAM_D2))
+    (pad 14 smd rect (at -5.62 6.985 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 58 SRAM_D1))
+    (pad 13 smd rect (at -5.62 5.715 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 59 SRAM_D0))
+    (pad 12 smd rect (at -5.62 4.445 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 60 SRAM_A0))
+    (pad 11 smd rect (at -5.62 3.175 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 61 SRAM_A1))
+    (pad 10 smd rect (at -5.62 1.905 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 62 SRAM_A2))
+    (pad 9 smd rect (at -5.62 0.635 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 63 SRAM_A3))
+    (pad 8 smd rect (at -5.62 -0.635 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 64 SRAM_A4))
+    (pad 7 smd rect (at -5.62 -1.905 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 65 SRAM_A5))
+    (pad 6 smd rect (at -5.62 -3.175 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 126 SRAM_A6))
+    (pad 5 smd rect (at -5.62 -4.445 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 66 SRAM_A7))
+    (pad 4 smd rect (at -5.62 -5.715 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 67 SRAM_A12))
+    (pad 3 smd rect (at -5.62 -6.985 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 68 SRAM_A14))
+    (pad 2 smd rect (at -5.62 -8.255 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 69 SRAM_A16))
+    (pad 1 smd rect (at -5.62 -9.525 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 70 SRAM_A17))
+  )
+
+  (module MIC5504-1:SOT23-5P95_280X145XL45X37N (layer B.Cu) (tedit 5F5FD964) (tstamp 5F63210B)
+    (at 140.1826 43.5102)
+    (path /5F62178D/5F8012E4)
+    (attr smd)
+    (fp_text reference U7 (at 0.17427 2.108144) (layer B.SilkS)
+      (effects (font (size 0.480762 0.480762) (thickness 0.015)) (justify mirror))
+    )
+    (fp_text value MIC5504-1.2YM5-TR (at 6.392076 -2.201154) (layer B.Fab)
+      (effects (font (size 0.481301 0.481301) (thickness 0.015)) (justify mirror))
+    )
+    (fp_circle (center -1.7 1.5) (end -1.57 1.5) (layer B.SilkS) (width 0.1))
+    (fp_line (start 1.91 -1.7) (end 1.91 1.7) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.91 -1.7) (end 1.91 -1.7) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.91 1.7) (end -1.91 -1.7) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 1.91 1.7) (end -1.91 1.7) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.8 -1.45) (end 0.8 1.45) (layer B.Fab) (width 0.127))
+    (fp_line (start -0.8 1.45) (end -0.8 -1.45) (layer B.Fab) (width 0.127))
+    (pad 5 smd rect (at 1.14 0.95) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask)
+      (net 5 +1V2))
+    (pad 4 smd rect (at 1.14 -0.95) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask))
+    (pad 3 smd rect (at -1.14 -0.95) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask)
+      (net 4 +3V3))
+    (pad 2 smd rect (at -1.14 0) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask)
+      (net 3 GND))
+    (pad 1 smd rect (at -1.14 0.95) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask)
+      (net 4 +3V3))
+  )
+
+  (module SN74LVC245APW:SOP65P640X120-20N (layer F.Cu) (tedit 5F5FB988) (tstamp 5F607F23)
+    (at 123.825 62.7634)
+    (path /5F6217EE/5F623800)
+    (attr smd)
+    (fp_text reference U6 (at -0.325 -4.385) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.015)))
+    )
+    (fp_text value SN74LVC245APW (at 7.295 4.385) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.015)))
+    )
+    (fp_line (start 3.91 -3.55) (end 3.91 3.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -3.91 -3.55) (end -3.91 3.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -3.91 3.55) (end 3.91 3.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -3.91 -3.55) (end 3.91 -3.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 2.2 -3.25) (end 2.2 3.25) (layer F.Fab) (width 0.127))
+    (fp_line (start -2.2 -3.25) (end -2.2 3.25) (layer F.Fab) (width 0.127))
+    (fp_line (start -2.2 3.45) (end 2.2 3.45) (layer F.SilkS) (width 0.127))
+    (fp_line (start -2.2 -3.45) (end 2.2 -3.45) (layer F.SilkS) (width 0.127))
+    (fp_line (start -2.2 3.25) (end 2.2 3.25) (layer F.Fab) (width 0.127))
+    (fp_line (start -2.2 -3.25) (end 2.2 -3.25) (layer F.Fab) (width 0.127))
+    (fp_circle (center -4.19 -2.925) (end -4.09 -2.925) (layer F.Fab) (width 0.2))
+    (fp_circle (center -4.19 -2.925) (end -4.09 -2.925) (layer F.SilkS) (width 0.2))
+    (pad 20 smd rect (at 2.87 -2.925) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 4 +3V3))
+    (pad 19 smd rect (at 2.87 -2.275) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 80 BUF2_OE__n))
+    (pad 18 smd rect (at 2.87 -1.625) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 74 AD7_3V))
+    (pad 17 smd rect (at 2.87 -0.975) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 73 AD6_3V))
+    (pad 16 smd rect (at 2.87 -0.325) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 72 AD5_3V))
+    (pad 15 smd rect (at 2.87 0.325) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 71 AD4_3V))
+    (pad 14 smd rect (at 2.87 0.975) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 75 AD3_3V))
+    (pad 13 smd rect (at 2.87 1.625) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 76 AD2_3V))
+    (pad 12 smd rect (at 2.87 2.275) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 77 AD1_3V))
+    (pad 11 smd rect (at 2.87 2.925) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 78 AD0_3V))
+    (pad 10 smd rect (at -2.87 2.925) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 3 GND))
+    (pad 9 smd rect (at -2.87 2.275) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 14 AD0_5V))
+    (pad 8 smd rect (at -2.87 1.625) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 16 AD1_5V))
+    (pad 7 smd rect (at -2.87 0.975) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 18 AD2_5V))
+    (pad 6 smd rect (at -2.87 0.325) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 19 AD3_5V))
+    (pad 5 smd rect (at -2.87 -0.325) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 21 AD4_5V))
+    (pad 4 smd rect (at -2.87 -0.975) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 23 AD5_5V))
+    (pad 3 smd rect (at -2.87 -1.625) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 25 AD6_5V))
+    (pad 2 smd rect (at -2.87 -2.275) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 27 AD7_5V))
+    (pad 1 smd rect (at -2.87 -2.925) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 81 BUF2_DIR))
+  )
+
+  (module SN74LVC245APW:SOP65P640X120-20N (layer B.Cu) (tedit 5F5FB988) (tstamp 5F607EFF)
+    (at 138.176 72.1868)
+    (path /5F6217EE/5F6230CD)
+    (attr smd)
+    (fp_text reference U5 (at -0.325 4.385) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.015)) (justify mirror))
+    )
+    (fp_text value SN74LVC245APW (at 7.295 -4.385) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.015)) (justify mirror))
+    )
+    (fp_line (start 3.91 3.55) (end 3.91 -3.55) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -3.91 3.55) (end -3.91 -3.55) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -3.91 -3.55) (end 3.91 -3.55) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -3.91 3.55) (end 3.91 3.55) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 2.2 3.25) (end 2.2 -3.25) (layer B.Fab) (width 0.127))
+    (fp_line (start -2.2 3.25) (end -2.2 -3.25) (layer B.Fab) (width 0.127))
+    (fp_line (start -2.2 -3.45) (end 2.2 -3.45) (layer B.SilkS) (width 0.127))
+    (fp_line (start -2.2 3.45) (end 2.2 3.45) (layer B.SilkS) (width 0.127))
+    (fp_line (start -2.2 -3.25) (end 2.2 -3.25) (layer B.Fab) (width 0.127))
+    (fp_line (start -2.2 3.25) (end 2.2 3.25) (layer B.Fab) (width 0.127))
+    (fp_circle (center -4.19 2.925) (end -4.09 2.925) (layer B.Fab) (width 0.2))
+    (fp_circle (center -4.19 2.925) (end -4.09 2.925) (layer B.SilkS) (width 0.2))
+    (pad 20 smd rect (at 2.87 2.925) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 4 +3V3))
+    (pad 19 smd rect (at 2.87 2.275) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 79 BUF1_OE__n))
+    (pad 18 smd rect (at 2.87 1.625) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 121 INTA_n_3V))
+    (pad 17 smd rect (at 2.87 0.975) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 122 DEN_3V))
+    (pad 16 smd rect (at 2.87 0.325) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 123 DTR_3V))
+    (pad 15 smd rect (at 2.87 -0.325) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 124 IOM_3V))
+    (pad 14 smd rect (at 2.87 -0.975) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 125 WR_3V))
+    (pad 13 smd rect (at 2.87 -1.625) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 120 RD_3V))
+    (pad 12 smd rect (at 2.87 -2.275) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask))
+    (pad 11 smd rect (at 2.87 -2.925) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask))
+    (pad 10 smd rect (at -2.87 -2.925) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 3 GND))
+    (pad 9 smd rect (at -2.87 -2.275) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask))
+    (pad 8 smd rect (at -2.87 -1.625) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask))
+    (pad 7 smd rect (at -2.87 -0.975) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 20 RD_5V))
+    (pad 6 smd rect (at -2.87 -0.325) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 26 WR_5V))
+    (pad 5 smd rect (at -2.87 0.325) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 28 IOM_5V))
+    (pad 4 smd rect (at -2.87 0.975) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 30 DTR_5V))
+    (pad 3 smd rect (at -2.87 1.625) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 32 DEN_5V))
+    (pad 2 smd rect (at -2.87 2.275) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 36 INTA_n_5V))
+    (pad 1 smd rect (at -2.87 2.925) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 3 GND))
+  )
+
+  (module SN74LVC245APW:SOP65P640X120-20N (layer F.Cu) (tedit 5F5FB988) (tstamp 5F607EDB)
+    (at 123.6726 81.7118)
+    (path /5F6217EE/5F622E6C)
+    (attr smd)
+    (fp_text reference U4 (at -0.325 -4.385) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.015)))
+    )
+    (fp_text value SN74LVC245APW (at 7.295 4.385) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.015)))
+    )
+    (fp_line (start 3.91 -3.55) (end 3.91 3.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -3.91 -3.55) (end -3.91 3.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -3.91 3.55) (end 3.91 3.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -3.91 -3.55) (end 3.91 -3.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 2.2 -3.25) (end 2.2 3.25) (layer F.Fab) (width 0.127))
+    (fp_line (start -2.2 -3.25) (end -2.2 3.25) (layer F.Fab) (width 0.127))
+    (fp_line (start -2.2 3.45) (end 2.2 3.45) (layer F.SilkS) (width 0.127))
+    (fp_line (start -2.2 -3.45) (end 2.2 -3.45) (layer F.SilkS) (width 0.127))
+    (fp_line (start -2.2 3.25) (end 2.2 3.25) (layer F.Fab) (width 0.127))
+    (fp_line (start -2.2 -3.25) (end 2.2 -3.25) (layer F.Fab) (width 0.127))
+    (fp_circle (center -4.19 -2.925) (end -4.09 -2.925) (layer F.Fab) (width 0.2))
+    (fp_circle (center -4.19 -2.925) (end -4.09 -2.925) (layer F.SilkS) (width 0.2))
+    (pad 20 smd rect (at 2.87 -2.925) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 4 +3V3))
+    (pad 19 smd rect (at 2.87 -2.275) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 3 GND))
+    (pad 18 smd rect (at 2.87 -1.625) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 24 HLDA_5V))
+    (pad 17 smd rect (at 2.87 -0.975) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 112 HOLD_3V))
+    (pad 16 smd rect (at 2.87 -0.325) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 113 NMI_3V))
+    (pad 15 smd rect (at 2.87 0.325) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 114 INTR_3V))
+    (pad 14 smd rect (at 2.87 0.975) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 115 CLK_3V))
+    (pad 13 smd rect (at 2.87 1.625) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 116 RESET_3V))
+    (pad 12 smd rect (at 2.87 2.275) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 117 READY_3V))
+    (pad 11 smd rect (at 2.87 2.925) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 34 ALE_5V))
+    (pad 10 smd rect (at -2.87 2.925) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 3 GND))
+    (pad 9 smd rect (at -2.87 2.275) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 118 ALE_3V))
+    (pad 8 smd rect (at -2.87 1.625) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 39 READY_5V))
+    (pad 7 smd rect (at -2.87 0.975) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 41 RESET_5V))
+    (pad 6 smd rect (at -2.87 0.325) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 8 CLK_5V))
+    (pad 5 smd rect (at -2.87 -0.325) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 10 INTR_5V))
+    (pad 4 smd rect (at -2.87 -0.975) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 12 NMI_5V))
+    (pad 3 smd rect (at -2.87 -1.625) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 22 HOLD_5V))
+    (pad 2 smd rect (at -2.87 -2.275) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 119 HLDA_3V))
+    (pad 1 smd rect (at -2.87 -2.925) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 4 +3V3))
+  )
+
+  (module MIC5504-1:SOT23-5P95_280X145XL45X37N (layer B.Cu) (tedit 5F5FD964) (tstamp 5F632092)
+    (at 135.382 39.116)
+    (path /5F62178D/5F8012DE)
+    (attr smd)
+    (fp_text reference U3 (at 0.17427 2.108144) (layer B.SilkS)
+      (effects (font (size 0.480762 0.480762) (thickness 0.015)) (justify mirror))
+    )
+    (fp_text value MIC5504-3.3YM5-TR (at 6.392076 -2.201154) (layer B.Fab)
+      (effects (font (size 0.481301 0.481301) (thickness 0.015)) (justify mirror))
+    )
+    (fp_circle (center -1.7 1.5) (end -1.57 1.5) (layer B.SilkS) (width 0.1))
+    (fp_line (start 1.91 -1.7) (end 1.91 1.7) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.91 -1.7) (end 1.91 -1.7) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.91 1.7) (end -1.91 -1.7) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 1.91 1.7) (end -1.91 1.7) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.8 -1.45) (end 0.8 1.45) (layer B.Fab) (width 0.127))
+    (fp_line (start -0.8 1.45) (end -0.8 -1.45) (layer B.Fab) (width 0.127))
+    (pad 5 smd rect (at 1.14 0.95) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask)
+      (net 4 +3V3))
+    (pad 4 smd rect (at 1.14 -0.95) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask))
+    (pad 3 smd rect (at -1.14 -0.95) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask)
+      (net 6 +5V))
+    (pad 2 smd rect (at -1.14 0) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask)
+      (net 3 GND))
+    (pad 1 smd rect (at -1.14 0.95) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask)
+      (net 6 +5V))
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F764EFC)
+    (at 148.971 54.991 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5F7CE133)
+    (attr smd)
+    (fp_text reference C31 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F78D7DF)
+    (at 143.4338 79.7306)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/60EB6252)
+    (attr smd)
+    (fp_text reference C30 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F78D7D0)
+    (at 161.8512 41.8084)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/60ECB869)
+    (attr smd)
+    (fp_text reference C29 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F78BA08)
+    (at 145.542 57.023 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/60E87B06)
+    (attr smd)
+    (fp_text reference C28 (at 0 1.17 270) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 270) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 270) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_DIP:DIP-40_W15.24mm (layer F.Cu) (tedit 5F684397) (tstamp 5F632176)
+    (at 116.3978 40.7556)
+    (descr "40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils)")
+    (tags "THT DIP DIL PDIP 2.54mm 15.24mm 600mil")
+    (path /5F6217EE/5F7A8941)
+    (fp_text reference U9 (at -2.174 -0.1156) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 8088_Min_Mode (at 7.478 48.5) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 2.6012 0.24) (layer F.Fab) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 16.3 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 16.3 49.8) (end 16.3 -1.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.05 49.8) (end 16.3 49.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.05 -1.55) (end -1.05 49.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 14.08 -1.33) (end 8.62 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 14.08 49.59) (end 14.08 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.16 49.59) (end 14.08 49.59) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.16 -1.33) (end 1.16 49.59) (layer F.SilkS) (width 0.12))
+    (fp_line (start 6.62 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0.255 -0.27) (end 1.255 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.255 49.53) (end 0.255 -0.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 14.985 49.53) (end 0.255 49.53) (layer F.Fab) (width 0.1))
+    (fp_line (start 14.985 -1.27) (end 14.985 49.53) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.255 -1.27) (end 14.985 -1.27) (layer F.Fab) (width 0.1))
+    (fp_arc (start 7.62 -1.33) (end 6.62 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
+    (pad 40 thru_hole oval (at 15.24 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 6 +5V))
+    (pad 20 thru_hole oval (at 0 48.26) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 3 GND))
+    (pad 39 thru_hole oval (at 15.24 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 7 A15_5V))
+    (pad 19 thru_hole oval (at 0 45.72) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 8 CLK_5V))
+    (pad 38 thru_hole oval (at 15.24 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 9 A16_5V))
+    (pad 18 thru_hole oval (at 0 43.18) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 10 INTR_5V))
+    (pad 37 thru_hole oval (at 15.24 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 11 A17_5V))
+    (pad 17 thru_hole oval (at 0 40.64) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 12 NMI_5V))
+    (pad 36 thru_hole oval (at 15.24 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 13 A18_5V))
+    (pad 16 thru_hole oval (at 0 38.1) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 14 AD0_5V))
+    (pad 35 thru_hole oval (at 15.24 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 15 A19_5V))
+    (pad 15 thru_hole oval (at 0 35.56) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 16 AD1_5V))
+    (pad 34 thru_hole oval (at 15.24 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 17 SSO_5V))
+    (pad 14 thru_hole oval (at 0 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 18 AD2_5V))
+    (pad 33 thru_hole oval (at 15.24 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
+    (pad 13 thru_hole oval (at 0 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 19 AD3_5V))
+    (pad 32 thru_hole oval (at 15.24 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 20 RD_5V))
+    (pad 12 thru_hole oval (at 0 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 21 AD4_5V))
+    (pad 31 thru_hole oval (at 15.24 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 22 HOLD_5V))
+    (pad 11 thru_hole oval (at 0 25.4) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 23 AD5_5V))
+    (pad 30 thru_hole oval (at 15.24 25.4) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 24 HLDA_5V))
+    (pad 10 thru_hole oval (at 0 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 25 AD6_5V))
+    (pad 29 thru_hole oval (at 15.24 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 26 WR_5V))
+    (pad 9 thru_hole oval (at 0 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 27 AD7_5V))
+    (pad 28 thru_hole oval (at 15.24 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 28 IOM_5V))
+    (pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 29 A8_5V))
+    (pad 27 thru_hole oval (at 15.24 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 30 DTR_5V))
+    (pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 31 A9_5V))
+    (pad 26 thru_hole oval (at 15.24 35.56) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 32 DEN_5V))
+    (pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 33 A10_5V))
+    (pad 25 thru_hole oval (at 15.24 38.1) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 34 ALE_5V))
+    (pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 35 A11_5V))
+    (pad 24 thru_hole oval (at 15.24 40.64) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 36 INTA_n_5V))
+    (pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 37 A12_5V))
+    (pad 23 thru_hole oval (at 15.24 43.18) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
+    (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 38 A13_5V))
+    (pad 22 thru_hole oval (at 15.24 45.72) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 39 READY_5V))
+    (pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 40 A14_5V))
+    (pad 21 thru_hole oval (at 15.24 48.26) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 41 RESET_5V))
+    (pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 3 GND))
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645CB7)
+    (at 126.4666 75.9714 90)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F6217EE/5FA1A7AD)
+    (attr smd)
+    (fp_text reference C23 (at 0 1.17 270) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 270) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 270) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5F631EEF)
+    (at 160.1216 64.897 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F609430/5F7DBF00)
+    (attr smd)
+    (fp_text reference R1 (at 0 -1.17 90) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 33 (at 0 1.17 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)))
+    )
+    (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 1 "Net-(R1-Pad2)"))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 2 CLK_100MHZ))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_QFP:TQFP-144_20x20mm_P0.5mm (layer F.Cu) (tedit 5D9F72B1) (tstamp 5F609B49)
+    (at 149.987 53.594)
+    (descr "TQFP, 144 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py")
+    (tags "TQFP QFP")
+    (path /5F609430/5F6440A9)
+    (attr smd)
+    (fp_text reference U1 (at 8.5598 -12.2936) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value XC6SLX9-TQG144 (at 0 12.35) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 0) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 11.65 9.15) (end 11.65 0) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 10.25 9.15) (end 11.65 9.15) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 10.25 10.25) (end 10.25 9.15) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 9.15 10.25) (end 10.25 10.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 9.15 11.65) (end 9.15 10.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0 11.65) (end 9.15 11.65) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -11.65 9.15) (end -11.65 0) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -10.25 9.15) (end -11.65 9.15) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -10.25 10.25) (end -10.25 9.15) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -9.15 10.25) (end -10.25 10.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -9.15 11.65) (end -9.15 10.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0 11.65) (end -9.15 11.65) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 11.65 -9.15) (end 11.65 0) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 10.25 -9.15) (end 11.65 -9.15) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 10.25 -10.25) (end 10.25 -9.15) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 9.15 -10.25) (end 10.25 -10.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 9.15 -11.65) (end 9.15 -10.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0 -11.65) (end 9.15 -11.65) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -11.65 -9.15) (end -11.65 0) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -10.25 -9.15) (end -11.65 -9.15) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -10.25 -10.25) (end -10.25 -9.15) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -9.15 -10.25) (end -10.25 -10.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -9.15 -11.65) (end -9.15 -10.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0 -11.65) (end -9.15 -11.65) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -10 -9) (end -9 -10) (layer F.Fab) (width 0.1))
+    (fp_line (start -10 10) (end -10 -9) (layer F.Fab) (width 0.1))
+    (fp_line (start 10 10) (end -10 10) (layer F.Fab) (width 0.1))
+    (fp_line (start 10 -10) (end 10 10) (layer F.Fab) (width 0.1))
+    (fp_line (start -9 -10) (end 10 -10) (layer F.Fab) (width 0.1))
+    (fp_line (start -10.11 -9.16) (end -11.4 -9.16) (layer F.SilkS) (width 0.12))
+    (fp_line (start -10.11 -10.11) (end -10.11 -9.16) (layer F.SilkS) (width 0.12))
+    (fp_line (start -9.16 -10.11) (end -10.11 -10.11) (layer F.SilkS) (width 0.12))
+    (fp_line (start 10.11 -10.11) (end 10.11 -9.16) (layer F.SilkS) (width 0.12))
+    (fp_line (start 9.16 -10.11) (end 10.11 -10.11) (layer F.SilkS) (width 0.12))
+    (fp_line (start -10.11 10.11) (end -10.11 9.16) (layer F.SilkS) (width 0.12))
+    (fp_line (start -9.16 10.11) (end -10.11 10.11) (layer F.SilkS) (width 0.12))
+    (fp_line (start 10.11 10.11) (end 10.11 9.16) (layer F.SilkS) (width 0.12))
+    (fp_line (start 9.16 10.11) (end 10.11 10.11) (layer F.SilkS) (width 0.12))
+    (pad 144 smd roundrect (at -8.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 143 smd roundrect (at -8.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 7 A15_5V))
+    (pad 142 smd roundrect (at -7.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 40 A14_5V))
+    (pad 141 smd roundrect (at -7.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 140 smd roundrect (at -6.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 139 smd roundrect (at -6.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 138 smd roundrect (at -5.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 137 smd roundrect (at -5.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 136 smd roundrect (at -4.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 135 smd roundrect (at -4.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 134 smd roundrect (at -3.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 133 smd roundrect (at -3.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 132 smd roundrect (at -2.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 60 SRAM_A0))
+    (pad 131 smd roundrect (at -2.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 105 LED7))
+    (pad 130 smd roundrect (at -1.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 129 smd roundrect (at -1.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 128 smd roundrect (at -0.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (pad 127 smd roundrect (at -0.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 103 LED6))
+    (pad 126 smd roundrect (at 0.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 61 SRAM_A1))
+    (pad 125 smd roundrect (at 0.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 124 smd roundrect (at 1.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 62 SRAM_A2))
+    (pad 123 smd roundrect (at 1.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 63 SRAM_A3))
+    (pad 122 smd roundrect (at 2.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 121 smd roundrect (at 2.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 101 LED5))
+    (pad 120 smd roundrect (at 3.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 99 LED4))
+    (pad 119 smd roundrect (at 3.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 59 SRAM_D0))
+    (pad 118 smd roundrect (at 4.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 58 SRAM_D1))
+    (pad 117 smd roundrect (at 4.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 57 SRAM_D2))
+    (pad 116 smd roundrect (at 5.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 97 LED3))
+    (pad 115 smd roundrect (at 5.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 114 smd roundrect (at 6.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 95 LED2))
+    (pad 113 smd roundrect (at 6.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 112 smd roundrect (at 7.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 93 LED1))
+    (pad 111 smd roundrect (at 7.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 91 LED0))
+    (pad 110 smd roundrect (at 8.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 85 "Net-(J1-Pad2)"))
+    (pad 109 smd roundrect (at 8.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 84 "Net-(J1-Pad3)"))
+    (pad 108 smd roundrect (at 10.6625 -8.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 107 smd roundrect (at 10.6625 -8.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 83 "Net-(J1-Pad4)"))
+    (pad 106 smd roundrect (at 10.6625 -7.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 82 "Net-(J1-Pad5)"))
+    (pad 105 smd roundrect (at 10.6625 -7.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 104 smd roundrect (at 10.6625 -6.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 103 smd roundrect (at 10.6625 -6.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 102 smd roundrect (at 10.6625 -5.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 101 smd roundrect (at 10.6625 -5.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 100 smd roundrect (at 10.6625 -4.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 42 SRAM_A15))
+    (pad 99 smd roundrect (at 10.6625 -4.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 43 SRAM_A18))
+    (pad 98 smd roundrect (at 10.6625 -3.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 44 SRAM_WE_n))
+    (pad 97 smd roundrect (at 10.6625 -3.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 45 SRAM_A13))
+    (pad 96 smd roundrect (at 10.6625 -2.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 95 smd roundrect (at 10.6625 -2.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 46 SRAM_A8))
+    (pad 94 smd roundrect (at 10.6625 -1.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 47 SRAM_A9))
+    (pad 93 smd roundrect (at 10.6625 -1.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 48 SRAM_A11))
+    (pad 92 smd roundrect (at 10.6625 -0.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 49 SRAM_OE_n))
+    (pad 91 smd roundrect (at 10.6625 -0.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 90 smd roundrect (at 10.6625 0.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 89 smd roundrect (at 10.6625 0.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (pad 88 smd roundrect (at 10.6625 1.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 50 SRAM_A10))
+    (pad 87 smd roundrect (at 10.6625 1.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 51 SRAM_CE_n))
+    (pad 86 smd roundrect (at 10.6625 2.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 85 smd roundrect (at 10.6625 2.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 52 SRAM_D7))
+    (pad 84 smd roundrect (at 10.6625 3.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 2 CLK_100MHZ))
+    (pad 83 smd roundrect (at 10.6625 3.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 53 SRAM_D6))
+    (pad 82 smd roundrect (at 10.6625 4.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 54 SRAM_D5))
+    (pad 81 smd roundrect (at 10.6625 4.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 55 SRAM_D4))
+    (pad 80 smd roundrect (at 10.6625 5.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 56 SRAM_D3))
+    (pad 79 smd roundrect (at 10.6625 5.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 70 SRAM_A17))
+    (pad 78 smd roundrect (at 10.6625 6.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 69 SRAM_A16))
+    (pad 77 smd roundrect (at 10.6625 6.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 76 smd roundrect (at 10.6625 7.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 75 smd roundrect (at 10.6625 7.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 68 SRAM_A14))
+    (pad 74 smd roundrect (at 10.6625 8.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 67 SRAM_A12))
+    (pad 73 smd roundrect (at 10.6625 8.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 72 smd roundrect (at 8.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 71 smd roundrect (at 8.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 108 FPGA_DONE))
+    (pad 70 smd roundrect (at 7.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 111 "Net-(R16-Pad1)"))
+    (pad 69 smd roundrect (at 7.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 106 FPGA_M0))
+    (pad 68 smd roundrect (at 6.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 67 smd roundrect (at 6.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 66 SRAM_A7))
+    (pad 66 smd roundrect (at 5.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 126 SRAM_A6))
+    (pad 65 smd roundrect (at 5.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 87 SPI_DOUT))
+    (pad 64 smd roundrect (at 4.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 88 SPI_DIN))
+    (pad 63 smd roundrect (at 4.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 62 smd roundrect (at 3.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 65 SRAM_A5))
+    (pad 61 smd roundrect (at 3.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 64 SRAM_A4))
+    (pad 60 smd roundrect (at 2.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 107 FPGA_M1))
+    (pad 59 smd roundrect (at 2.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 79 BUF1_OE__n))
+    (pad 58 smd roundrect (at 1.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 121 INTA_n_3V))
+    (pad 57 smd roundrect (at 1.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 122 DEN_3V))
+    (pad 56 smd roundrect (at 0.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 123 DTR_3V))
+    (pad 55 smd roundrect (at 0.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 124 IOM_3V))
+    (pad 54 smd roundrect (at -0.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 53 smd roundrect (at -0.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 52 smd roundrect (at -1.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (pad 51 smd roundrect (at -1.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 125 WR_3V))
+    (pad 50 smd roundrect (at -2.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 120 RD_3V))
+    (pad 49 smd roundrect (at -2.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 48 smd roundrect (at -3.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 117 READY_3V))
+    (pad 47 smd roundrect (at -3.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 116 RESET_3V))
+    (pad 46 smd roundrect (at -4.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 115 CLK_3V))
+    (pad 45 smd roundrect (at -4.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 114 INTR_3V))
+    (pad 44 smd roundrect (at -5.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 113 NMI_3V))
+    (pad 43 smd roundrect (at -5.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 112 HOLD_3V))
+    (pad 42 smd roundrect (at -6.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 41 smd roundrect (at -6.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 118 ALE_3V))
+    (pad 40 smd roundrect (at -7.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 119 HLDA_3V))
+    (pad 39 smd roundrect (at -7.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 110 FPGA_INIT))
+    (pad 38 smd roundrect (at -8.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 89 SPI_CS_n))
+    (pad 37 smd roundrect (at -8.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 109 FPGA_PROGRAM_n))
+    (pad 36 smd roundrect (at -10.6625 8.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 35 smd roundrect (at -10.6625 8.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 78 AD0_3V))
+    (pad 34 smd roundrect (at -10.6625 7.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 77 AD1_3V))
+    (pad 33 smd roundrect (at -10.6625 7.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 76 AD2_3V))
+    (pad 32 smd roundrect (at -10.6625 6.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 75 AD3_3V))
+    (pad 31 smd roundrect (at -10.6625 6.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 30 smd roundrect (at -10.6625 5.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 29 smd roundrect (at -10.6625 5.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 28 smd roundrect (at -10.6625 4.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (pad 27 smd roundrect (at -10.6625 4.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 71 AD4_3V))
+    (pad 26 smd roundrect (at -10.6625 3.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 72 AD5_3V))
+    (pad 25 smd roundrect (at -10.6625 3.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 24 smd roundrect (at -10.6625 2.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 23 smd roundrect (at -10.6625 2.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 73 AD6_3V))
+    (pad 22 smd roundrect (at -10.6625 1.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 74 AD7_3V))
+    (pad 21 smd roundrect (at -10.6625 1.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 80 BUF2_OE__n))
+    (pad 20 smd roundrect (at -10.6625 0.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 19 smd roundrect (at -10.6625 0.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (pad 18 smd roundrect (at -10.6625 -0.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 17 smd roundrect (at -10.6625 -0.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 16 smd roundrect (at -10.6625 -1.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 81 BUF2_DIR))
+    (pad 15 smd roundrect (at -10.6625 -1.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 14 smd roundrect (at -10.6625 -2.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 29 A8_5V))
+    (pad 13 smd roundrect (at -10.6625 -2.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 12 smd roundrect (at -10.6625 -3.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 17 SSO_5V))
+    (pad 11 smd roundrect (at -10.6625 -3.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 31 A9_5V))
+    (pad 10 smd roundrect (at -10.6625 -4.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 15 A19_5V))
+    (pad 9 smd roundrect (at -10.6625 -4.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 33 A10_5V))
+    (pad 8 smd roundrect (at -10.6625 -5.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 13 A18_5V))
+    (pad 7 smd roundrect (at -10.6625 -5.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 35 A11_5V))
+    (pad 6 smd roundrect (at -10.6625 -6.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 11 A17_5V))
+    (pad 5 smd roundrect (at -10.6625 -6.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 37 A12_5V))
+    (pad 4 smd roundrect (at -10.6625 -7.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 3 smd roundrect (at -10.6625 -7.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 2 smd roundrect (at -10.6625 -8.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 9 A16_5V))
+    (pad 1 smd roundrect (at -10.6625 -8.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 38 A13_5V))
+    (model ${KISYS3DMOD}/Package_QFP.3dshapes/TQFP-144_20x20mm_P0.5mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F683051)
+    (at 156.6672 67.4116 90)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FF27C34)
+    (attr smd)
+    (fp_text reference C27 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F683042)
+    (at 157.988 40.386)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FF1DF62)
+    (attr smd)
+    (fp_text reference C26 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F683033)
+    (at 144.018 40.386)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FF14247)
+    (attr smd)
+    (fp_text reference C25 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6700E3)
+    (at 157.7848 67.7672 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F609430/5FDFB8A4)
+    (attr smd)
+    (fp_text reference R16 (at 0 1.17 270) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 33 (at 0 -1.17 270) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 270) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 86 SPI_CLK))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 111 "Net-(R16-Pad1)"))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6700D4)
+    (at 135.4328 80.1624)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F609430/5FD82F74)
+    (attr smd)
+    (fp_text reference R15 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7k (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 89 SPI_CS_n))
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6470DD)
+    (at 142.5702 60.7568 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F609430/5FBA7A81)
+    (attr smd)
+    (fp_text reference R14 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7k (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 110 FPGA_INIT))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6470CE)
+    (at 141.097 61.214 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F609430/5FBD99FB)
+    (attr smd)
+    (fp_text reference R13 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7k (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 109 FPGA_PROGRAM_n))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6470BF)
+    (at 158.369 61.214 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F609430/5FBB9847)
+    (attr smd)
+    (fp_text reference R12 (at 0 1.17 270) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7k (at 0 -1.17 270) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 270) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 108 FPGA_DONE))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6470B0)
+    (at 152.781 61.214 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F609430/5FB6A4AD)
+    (attr smd)
+    (fp_text reference R11 (at 0 1.17 270) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7k (at 0 -1.17 270) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 270) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 107 FPGA_M1))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6470A1)
+    (at 157.226 61.214 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F609430/5FB0A2A1)
+    (attr smd)
+    (fp_text reference R10 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7k (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 106 FPGA_M0))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F646DD6)
+    (at 142.6718 47.1932 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F62178D/5FAF607D)
+    (attr smd)
+    (fp_text reference C19 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F646DC7)
+    (at 139.573 40.386)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F62178D/5FADFFF0)
+    (attr smd)
+    (fp_text reference C18 (at 0 1.17 180) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 180) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 180) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F646DB8)
+    (at 139.573 39.116)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F62178D/5FAF0B3F)
+    (attr smd)
+    (fp_text reference C17 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F646DA9)
+    (at 134.366 41.275)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F62178D/5FADABE7)
+    (attr smd)
+    (fp_text reference C16 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 6 +5V))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645CC6)
+    (at 141.1224 76.9366 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F6217EE/5FA1EA71)
+    (attr smd)
+    (fp_text reference C24 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645CA8)
+    (at 123.9774 60.579 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F6217EE/5FA22BDC)
+    (attr smd)
+    (fp_text reference C22 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645C99)
+    (at 137.922 78.105)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F62178D/5FA17919)
+    (attr smd)
+    (fp_text reference C21 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645C8A)
+    (at 162.9156 83.8708 90)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F62178D/5FA14AF8)
+    (attr smd)
+    (fp_text reference C20 (at 0 1.17 270) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 270) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 270) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645C37)
+    (at 148.717 60.452 90)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FA9B5A8)
+    (attr smd)
+    (fp_text reference C15 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645C28)
+    (at 163.3728 61.595 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5F99F57A)
+    (attr smd)
+    (fp_text reference C14 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645C19)
+    (at 157.226 54.356 180)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FA9B5B7)
+    (attr smd)
+    (fp_text reference C13 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0.635 0.635) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 180) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 180) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645C0A)
+    (at 149.225 46.482 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FA9B5C7)
+    (attr smd)
+    (fp_text reference C12 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 180) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645BFB)
+    (at 142.494 53.848)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FA9B5D6)
+    (attr smd)
+    (fp_text reference C11 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645BEC)
+    (at 154.5844 79.0956 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FA06BB4)
+    (attr smd)
+    (fp_text reference C10 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645BDD)
+    (at 163.576 55.245 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5F9B5C56)
+    (attr smd)
+    (fp_text reference C9 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645BCE)
+    (at 149.1996 67.4116 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FA708B6)
+    (attr smd)
+    (fp_text reference C8 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645BBF)
+    (at 148.3106 40.1828 180)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FA7D5C4)
+    (attr smd)
+    (fp_text reference C7 (at 0 1.17 180) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 180) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 180) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 180) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 180) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645BB0)
+    (at 136.6266 54.6608 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FA83EE0)
+    (attr smd)
+    (fp_text reference C6 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645BA1)
+    (at 139.4992 65.9638)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5F999BF7)
+    (attr smd)
+    (fp_text reference C5 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at -0.635 -0.381) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645B92)
+    (at 163.4998 46.0502 90)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FA8ABC6)
+    (attr smd)
+    (fp_text reference C4 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645B83)
+    (at 135.89 48.387 90)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5F98F0C7)
+    (attr smd)
+    (fp_text reference C3 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645B74)
+    (at 161.1122 67.6656 90)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FAAB60A)
+    (attr smd)
+    (fp_text reference C2 (at 0 1.17 270) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 270) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 270) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645B65)
+    (at 137.3632 63.9826 180)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5F92D2C4)
+    (attr smd)
+    (fp_text reference C1 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 1.27 -1.524) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 180) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 180) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F64262C)
+    (at 150.2156 36.703 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F62178D/5F908B53)
+    (attr smd)
+    (fp_text reference R9 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 330 (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 104 "Net-(D8-Pad2)"))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F64261D)
+    (at 151.1808 36.703 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F62178D/5F908B4D)
+    (attr smd)
+    (fp_text reference R8 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 330 (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 102 "Net-(D7-Pad2)"))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F64260E)
+    (at 152.1714 36.703 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F62178D/5F908B47)
+    (attr smd)
+    (fp_text reference R7 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 330 (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 100 "Net-(D6-Pad2)"))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6425FF)
+    (at 153.1366 36.703 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F62178D/5F908B41)
+    (attr smd)
+    (fp_text reference R6 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 330 (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 98 "Net-(D5-Pad2)"))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6425F0)
+    (at 154.1272 36.703 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F62178D/5F905C13)
+    (attr smd)
+    (fp_text reference R5 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 330 (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 96 "Net-(D4-Pad2)"))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6425E1)
+    (at 155.1178 36.703 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F62178D/5F905C0D)
+    (attr smd)
+    (fp_text reference R4 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 330 (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 94 "Net-(D3-Pad2)"))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6425D2)
+    (at 156.1084 36.703 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F62178D/5F9031C9)
+    (attr smd)
+    (fp_text reference R3 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 330 (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 92 "Net-(D2-Pad2)"))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6425C3)
+    (at 157.099 36.703 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F62178D/5F8CD1C0)
+    (attr smd)
+    (fp_text reference R2 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 330 (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 90 "Net-(D1-Pad2)"))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module LED_SMD:LED_0402_1005Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5F642562)
+    (at 150.114 36.6776 90)
+    (descr "LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags LED)
+    (path /5F62178D/5F8E33AD)
+    (attr smd)
+    (fp_text reference D8 (at -1.8796 0.0254 90) (layer F.SilkS)
+      (effects (font (size 0.5 0.5) (thickness 0.125)))
+    )
+    (fp_text value LED (at 0 1.17 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)))
+    )
+    (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.3 0.25) (end -0.3 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.4 0.25) (end -0.4 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_circle (center -1.09 0) (end -1.04 0) (layer F.SilkS) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 104 "Net-(D8-Pad2)"))
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 105 LED7))
+    (model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module LED_SMD:LED_0402_1005Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5F642550)
+    (at 151.1046 36.6776 90)
+    (descr "LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags LED)
+    (path /5F62178D/5F8E339C)
+    (attr smd)
+    (fp_text reference D7 (at -1.8796 0.0762 90) (layer F.SilkS)
+      (effects (font (size 0.5 0.5) (thickness 0.125)))
+    )
+    (fp_text value LED (at 0 1.17 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center -1.09 0) (end -1.04 0) (layer F.SilkS) (width 0.1))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.4 0.25) (end -0.4 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.3 0.25) (end -0.3 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)))
+    )
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 103 LED6))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 102 "Net-(D7-Pad2)"))
+    (model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module LED_SMD:LED_0402_1005Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5F64253E)
+    (at 152.0952 36.6776 90)
+    (descr "LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags LED)
+    (path /5F62178D/5F8E338B)
+    (attr smd)
+    (fp_text reference D6 (at -1.905 0.0762 90) (layer F.SilkS)
+      (effects (font (size 0.5 0.5) (thickness 0.125)))
+    )
+    (fp_text value LED (at 0 1.17 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center -1.09 0) (end -1.04 0) (layer F.SilkS) (width 0.1))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.4 0.25) (end -0.4 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.3 0.25) (end -0.3 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)))
+    )
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 101 LED5))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 100 "Net-(D6-Pad2)"))
+    (model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module LED_SMD:LED_0402_1005Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5F64252C)
+    (at 153.0858 36.6776 90)
+    (descr "LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags LED)
+    (path /5F62178D/5F8E337A)
+    (attr smd)
+    (fp_text reference D5 (at -1.905 0.0508 90) (layer F.SilkS)
+      (effects (font (size 0.5 0.5) (thickness 0.125)))
+    )
+    (fp_text value LED (at 0 1.17 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center -1.09 0) (end -1.04 0) (layer F.SilkS) (width 0.1))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.4 0.25) (end -0.4 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.3 0.25) (end -0.3 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)))
+    )
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 99 LED4))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 98 "Net-(D5-Pad2)"))
+    (model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module LED_SMD:LED_0402_1005Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5F64251A)
+    (at 154.0764 36.6776 90)
+    (descr "LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags LED)
+    (path /5F62178D/5F8DEB6E)
+    (attr smd)
+    (fp_text reference D4 (at -1.905 0.0254 90) (layer F.SilkS)
+      (effects (font (size 0.5 0.5) (thickness 0.125)))
+    )
+    (fp_text value LED (at 0 1.17 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center -1.09 0) (end -1.04 0) (layer F.SilkS) (width 0.1))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.4 0.25) (end -0.4 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.3 0.25) (end -0.3 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)))
+    )
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 97 LED3))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 96 "Net-(D4-Pad2)"))
+    (model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module LED_SMD:LED_0402_1005Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5F642508)
+    (at 155.067 36.6776 90)
+    (descr "LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags LED)
+    (path /5F62178D/5F8DEB5D)
+    (attr smd)
+    (fp_text reference D3 (at -1.8796 0.0762 90) (layer F.SilkS)
+      (effects (font (size 0.5 0.5) (thickness 0.125)))
+    )
+    (fp_text value LED (at 0 1.17 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center -1.09 0) (end -1.04 0) (layer F.SilkS) (width 0.1))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.4 0.25) (end -0.4 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.3 0.25) (end -0.3 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)))
+    )
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 95 LED2))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 94 "Net-(D3-Pad2)"))
+    (model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module LED_SMD:LED_0402_1005Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5F6424F6)
+    (at 156.083 36.6776 90)
+    (descr "LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags LED)
+    (path /5F62178D/5F8DC90D)
+    (attr smd)
+    (fp_text reference D2 (at -1.905 0.0508 90) (layer F.SilkS)
+      (effects (font (size 0.5 0.5) (thickness 0.125)))
+    )
+    (fp_text value LED (at 0 1.17 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center -1.09 0) (end -1.04 0) (layer F.SilkS) (width 0.1))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.4 0.25) (end -0.4 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.3 0.25) (end -0.3 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)))
+    )
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 93 LED1))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 92 "Net-(D2-Pad2)"))
+    (model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module LED_SMD:LED_0402_1005Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5F6424E4)
+    (at 157.0736 36.6776 90)
+    (descr "LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags LED)
+    (path /5F62178D/5F8C9584)
+    (attr smd)
+    (fp_text reference D1 (at -1.8796 0.0254 90) (layer F.SilkS)
+      (effects (font (size 0.5 0.5) (thickness 0.125)))
+    )
+    (fp_text value LED (at 0 1.17 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center -1.09 0) (end -1.04 0) (layer F.SilkS) (width 0.1))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.4 0.25) (end -0.4 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.3 0.25) (end -0.3 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)))
+    )
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 91 LED0))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 90 "Net-(D1-Pad2)"))
+    (model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_SO:SOIC-8_5.23x5.23mm_P1.27mm (layer B.Cu) (tedit 5D9F72B1) (tstamp 5F632082)
+    (at 158.369 74.8284 90)
+    (descr "SOIC, 8 Pin (http://www.winbond.com/resource-files/w25q32jv%20revg%2003272018%20plus.pdf#page=68), generated with kicad-footprint-generator ipc_gullwing_generator.py")
+    (tags "SOIC SO")
+    (path /5F609430/5F7F9366)
+    (attr smd)
+    (fp_text reference U2 (at 0 3.56 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value W25Q128JVS (at 0 -3.56 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start 4.65 2.86) (end -4.65 2.86) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 4.65 -2.86) (end 4.65 2.86) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -4.65 -2.86) (end 4.65 -2.86) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -4.65 2.86) (end -4.65 -2.86) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -2.615 1.615) (end -1.615 2.615) (layer B.Fab) (width 0.1))
+    (fp_line (start -2.615 -2.615) (end -2.615 1.615) (layer B.Fab) (width 0.1))
+    (fp_line (start 2.615 -2.615) (end -2.615 -2.615) (layer B.Fab) (width 0.1))
+    (fp_line (start 2.615 2.615) (end 2.615 -2.615) (layer B.Fab) (width 0.1))
+    (fp_line (start -1.615 2.615) (end 2.615 2.615) (layer B.Fab) (width 0.1))
+    (fp_line (start -2.725 2.465) (end -4.4 2.465) (layer B.SilkS) (width 0.12))
+    (fp_line (start -2.725 2.725) (end -2.725 2.465) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 2.725) (end -2.725 2.725) (layer B.SilkS) (width 0.12))
+    (fp_line (start 2.725 2.725) (end 2.725 2.465) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 2.725) (end 2.725 2.725) (layer B.SilkS) (width 0.12))
+    (fp_line (start -2.725 -2.725) (end -2.725 -2.465) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 -2.725) (end -2.725 -2.725) (layer B.SilkS) (width 0.12))
+    (fp_line (start 2.725 -2.725) (end 2.725 -2.465) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 -2.725) (end 2.725 -2.725) (layer B.SilkS) (width 0.12))
+    (pad 8 smd roundrect (at 3.6 1.905 90) (size 1.6 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 7 smd roundrect (at 3.6 0.635 90) (size 1.6 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 6 smd roundrect (at 3.6 -0.635 90) (size 1.6 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 86 SPI_CLK))
+    (pad 5 smd roundrect (at 3.6 -1.905 90) (size 1.6 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 88 SPI_DIN))
+    (pad 4 smd roundrect (at -3.6 -1.905 90) (size 1.6 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 3 smd roundrect (at -3.6 -0.635 90) (size 1.6 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 2 smd roundrect (at -3.6 0.635 90) (size 1.6 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 87 SPI_DOUT))
+    (pad 1 smd roundrect (at -3.6 1.905 90) (size 1.6 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 89 SPI_CS_n))
+    (model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-8_5.23x5.23mm_P1.27mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical (layer F.Cu) (tedit 5F68430F) (tstamp 5F630B27)
+    (at 124.0536 42.2402)
+    (descr "Through hole straight pin header, 1x06, 2.54mm pitch, single row")
+    (tags "Through hole pin header THT 1x06 2.54mm single row")
+    (path /5F609430/5F76EDA5)
+    (fp_text reference J1 (at -2.8194 0.127) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value Conn_01x06_Female (at 0 15.03) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 6.35 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.8 14.5) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 14.5) (end 1.8 14.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 -1.8) (end -1.8 14.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.33 1.27) (end 1.33 14.03) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end -1.33 14.03) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 14.03) (end 1.33 14.03) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.27 13.97) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 13.97) (end -1.27 13.97) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 -1.27) (end 1.27 13.97) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
+    (pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 3 GND))
+    (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 82 "Net-(J1-Pad5)"))
+    (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 83 "Net-(J1-Pad4)"))
+    (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 84 "Net-(J1-Pad3)"))
+    (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 85 "Net-(J1-Pad2)"))
+    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 4 +3V3))
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diff --git a/MCL86jr/PCBA/MCL86jr.kicad_pcb-bak b/MCL86jr/PCBA/MCL86jr.kicad_pcb-bak
new file mode 100644
index 0000000..8c0ccb6
--- /dev/null
+++ b/MCL86jr/PCBA/MCL86jr.kicad_pcb-bak
@@ -0,0 +1,6119 @@
+(kicad_pcb (version 20171130) (host pcbnew "(5.1.5)-3")
+
+  (general
+    (thickness 1.6)
+    (drawings 5)
+    (tracks 1434)
+    (zones 0)
+    (modules 66)
+    (nets 127)
+  )
+
+  (page A4)
+  (layers
+    (0 F.Cu signal hide)
+    (1 In1.Cu power hide)
+    (2 In2.Cu power hide)
+    (31 B.Cu signal hide)
+    (32 B.Adhes user hide)
+    (33 F.Adhes user hide)
+    (34 B.Paste user hide)
+    (35 F.Paste user hide)
+    (36 B.SilkS user hide)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (41 Cmts.User user)
+    (42 Eco1.User user)
+    (43 Eco2.User user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.2)
+    (trace_clearance 0.2)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.1524)
+    (via_size 0.8)
+    (via_drill 0.4)
+    (via_min_size 0.4)
+    (via_min_drill 0.3)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (edge_width 0.05)
+    (segment_width 0.2)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.12)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.6 1.6)
+    (pad_drill 0.8)
+    (pad_to_mask_clearance 0.051)
+    (solder_mask_min_width 0.25)
+    (aux_axis_origin 112.8522 34.544)
+    (grid_origin 112.8522 34.544)
+    (visible_elements 7FFFFFFF)
+    (pcbplotparams
+      (layerselection 0x010fc_ffffffff)
+      (usegerberextensions false)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin true)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 0)
+      (scaleselection 1)
+      (outputdirectory "Fabrication_Products2/"))
+  )
+
+  (net 0 "")
+  (net 1 "Net-(R1-Pad2)")
+  (net 2 CLK_100MHZ)
+  (net 3 GND)
+  (net 4 +3V3)
+  (net 5 +1V2)
+  (net 6 +5V)
+  (net 7 A15_5V)
+  (net 8 CLK_5V)
+  (net 9 A16_5V)
+  (net 10 INTR_5V)
+  (net 11 A17_5V)
+  (net 12 NMI_5V)
+  (net 13 A18_5V)
+  (net 14 AD0_5V)
+  (net 15 A19_5V)
+  (net 16 AD1_5V)
+  (net 17 SSO_5V)
+  (net 18 AD2_5V)
+  (net 19 AD3_5V)
+  (net 20 RD_5V)
+  (net 21 AD4_5V)
+  (net 22 HOLD_5V)
+  (net 23 AD5_5V)
+  (net 24 HLDA_5V)
+  (net 25 AD6_5V)
+  (net 26 WR_5V)
+  (net 27 AD7_5V)
+  (net 28 IOM_5V)
+  (net 29 A8_5V)
+  (net 30 DTR_5V)
+  (net 31 A9_5V)
+  (net 32 DEN_5V)
+  (net 33 A10_5V)
+  (net 34 ALE_5V)
+  (net 35 A11_5V)
+  (net 36 INTA_n_5V)
+  (net 37 A12_5V)
+  (net 38 A13_5V)
+  (net 39 READY_5V)
+  (net 40 A14_5V)
+  (net 41 RESET_5V)
+  (net 42 SRAM_A15)
+  (net 43 SRAM_A18)
+  (net 44 SRAM_WE_n)
+  (net 45 SRAM_A13)
+  (net 46 SRAM_A8)
+  (net 47 SRAM_A9)
+  (net 48 SRAM_A11)
+  (net 49 SRAM_OE_n)
+  (net 50 SRAM_A10)
+  (net 51 SRAM_CE_n)
+  (net 52 SRAM_D7)
+  (net 53 SRAM_D6)
+  (net 54 SRAM_D5)
+  (net 55 SRAM_D4)
+  (net 56 SRAM_D3)
+  (net 57 SRAM_D2)
+  (net 58 SRAM_D1)
+  (net 59 SRAM_D0)
+  (net 60 SRAM_A0)
+  (net 61 SRAM_A1)
+  (net 62 SRAM_A2)
+  (net 63 SRAM_A3)
+  (net 64 SRAM_A4)
+  (net 65 SRAM_A5)
+  (net 66 SRAM_A7)
+  (net 67 SRAM_A12)
+  (net 68 SRAM_A14)
+  (net 69 SRAM_A16)
+  (net 70 SRAM_A17)
+  (net 71 AD4_3V)
+  (net 72 AD5_3V)
+  (net 73 AD6_3V)
+  (net 74 AD7_3V)
+  (net 75 AD3_3V)
+  (net 76 AD2_3V)
+  (net 77 AD1_3V)
+  (net 78 AD0_3V)
+  (net 79 BUF1_OE__n)
+  (net 80 BUF2_OE__n)
+  (net 81 BUF2_DIR)
+  (net 82 "Net-(J1-Pad5)")
+  (net 83 "Net-(J1-Pad4)")
+  (net 84 "Net-(J1-Pad3)")
+  (net 85 "Net-(J1-Pad2)")
+  (net 86 SPI_CLK)
+  (net 87 SPI_DOUT)
+  (net 88 SPI_DIN)
+  (net 89 SPI_CS_n)
+  (net 90 "Net-(D1-Pad2)")
+  (net 91 LED0)
+  (net 92 "Net-(D2-Pad2)")
+  (net 93 LED1)
+  (net 94 "Net-(D3-Pad2)")
+  (net 95 LED2)
+  (net 96 "Net-(D4-Pad2)")
+  (net 97 LED3)
+  (net 98 "Net-(D5-Pad2)")
+  (net 99 LED4)
+  (net 100 "Net-(D6-Pad2)")
+  (net 101 LED5)
+  (net 102 "Net-(D7-Pad2)")
+  (net 103 LED6)
+  (net 104 "Net-(D8-Pad2)")
+  (net 105 LED7)
+  (net 106 FPGA_M0)
+  (net 107 FPGA_M1)
+  (net 108 FPGA_DONE)
+  (net 109 FPGA_PROGRAM_n)
+  (net 110 FPGA_INIT)
+  (net 111 "Net-(R16-Pad1)")
+  (net 112 HOLD_3V)
+  (net 113 NMI_3V)
+  (net 114 INTR_3V)
+  (net 115 CLK_3V)
+  (net 116 RESET_3V)
+  (net 117 READY_3V)
+  (net 118 ALE_3V)
+  (net 119 HLDA_3V)
+  (net 120 RD_3V)
+  (net 121 INTA_n_3V)
+  (net 122 DEN_3V)
+  (net 123 DTR_3V)
+  (net 124 IOM_3V)
+  (net 125 WR_3V)
+  (net 126 SRAM_A6)
+
+  (net_class Default "This is the default net class."
+    (clearance 0.2)
+    (trace_width 0.2)
+    (via_dia 0.8)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net +1V2)
+    (add_net +3V3)
+    (add_net +5V)
+    (add_net A10_5V)
+    (add_net A11_5V)
+    (add_net A12_5V)
+    (add_net A13_5V)
+    (add_net A14_5V)
+    (add_net A15_5V)
+    (add_net A16_5V)
+    (add_net A17_5V)
+    (add_net A18_5V)
+    (add_net A19_5V)
+    (add_net A8_5V)
+    (add_net A9_5V)
+    (add_net AD0_3V)
+    (add_net AD0_5V)
+    (add_net AD1_3V)
+    (add_net AD1_5V)
+    (add_net AD2_3V)
+    (add_net AD2_5V)
+    (add_net AD3_3V)
+    (add_net AD3_5V)
+    (add_net AD4_3V)
+    (add_net AD4_5V)
+    (add_net AD5_3V)
+    (add_net AD5_5V)
+    (add_net AD6_3V)
+    (add_net AD6_5V)
+    (add_net AD7_3V)
+    (add_net AD7_5V)
+    (add_net ALE_3V)
+    (add_net ALE_5V)
+    (add_net BUF1_OE__n)
+    (add_net BUF2_DIR)
+    (add_net BUF2_OE__n)
+    (add_net CLK_100MHZ)
+    (add_net CLK_3V)
+    (add_net CLK_5V)
+    (add_net DEN_3V)
+    (add_net DEN_5V)
+    (add_net DTR_3V)
+    (add_net DTR_5V)
+    (add_net FPGA_DONE)
+    (add_net FPGA_INIT)
+    (add_net FPGA_M0)
+    (add_net FPGA_M1)
+    (add_net FPGA_PROGRAM_n)
+    (add_net GND)
+    (add_net HLDA_3V)
+    (add_net HLDA_5V)
+    (add_net HOLD_3V)
+    (add_net HOLD_5V)
+    (add_net INTA_n_3V)
+    (add_net INTA_n_5V)
+    (add_net INTR_3V)
+    (add_net INTR_5V)
+    (add_net IOM_3V)
+    (add_net IOM_5V)
+    (add_net LED0)
+    (add_net LED1)
+    (add_net LED2)
+    (add_net LED3)
+    (add_net LED4)
+    (add_net LED5)
+    (add_net LED6)
+    (add_net LED7)
+    (add_net NMI_3V)
+    (add_net NMI_5V)
+    (add_net "Net-(D1-Pad2)")
+    (add_net "Net-(D2-Pad2)")
+    (add_net "Net-(D3-Pad2)")
+    (add_net "Net-(D4-Pad2)")
+    (add_net "Net-(D5-Pad2)")
+    (add_net "Net-(D6-Pad2)")
+    (add_net "Net-(D7-Pad2)")
+    (add_net "Net-(D8-Pad2)")
+    (add_net "Net-(J1-Pad2)")
+    (add_net "Net-(J1-Pad3)")
+    (add_net "Net-(J1-Pad4)")
+    (add_net "Net-(J1-Pad5)")
+    (add_net "Net-(R1-Pad2)")
+    (add_net "Net-(R16-Pad1)")
+    (add_net RD_3V)
+    (add_net RD_5V)
+    (add_net READY_3V)
+    (add_net READY_5V)
+    (add_net RESET_3V)
+    (add_net RESET_5V)
+    (add_net SPI_CLK)
+    (add_net SPI_CS_n)
+    (add_net SPI_DIN)
+    (add_net SPI_DOUT)
+    (add_net SRAM_A0)
+    (add_net SRAM_A1)
+    (add_net SRAM_A10)
+    (add_net SRAM_A11)
+    (add_net SRAM_A12)
+    (add_net SRAM_A13)
+    (add_net SRAM_A14)
+    (add_net SRAM_A15)
+    (add_net SRAM_A16)
+    (add_net SRAM_A17)
+    (add_net SRAM_A18)
+    (add_net SRAM_A2)
+    (add_net SRAM_A3)
+    (add_net SRAM_A4)
+    (add_net SRAM_A5)
+    (add_net SRAM_A6)
+    (add_net SRAM_A7)
+    (add_net SRAM_A8)
+    (add_net SRAM_A9)
+    (add_net SRAM_CE_n)
+    (add_net SRAM_D0)
+    (add_net SRAM_D1)
+    (add_net SRAM_D2)
+    (add_net SRAM_D3)
+    (add_net SRAM_D4)
+    (add_net SRAM_D5)
+    (add_net SRAM_D6)
+    (add_net SRAM_D7)
+    (add_net SRAM_OE_n)
+    (add_net SRAM_WE_n)
+    (add_net SSO_5V)
+    (add_net WR_3V)
+    (add_net WR_5V)
+  )
+
+  (module SIT8008BI-13-33E-33:OSC_SIT8008BI-13-33E-33.333330E (layer F.Cu) (tedit 5F5FD094) (tstamp 5F632188)
+    (at 160.274 67.7926 90)
+    (path /5F609430/5F7DBEF0)
+    (attr smd)
+    (fp_text reference Y1 (at 0.975 -2.235 90) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.015)))
+    )
+    (fp_text value 100Mhz (at 17.085 2.165 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.015)))
+    )
+    (fp_circle (center -2.2 0.8) (end -2.05 0.8) (layer F.SilkS) (width 0.2))
+    (fp_line (start -1.75 1.5) (end -1.75 -1.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.75 1.5) (end -1.75 1.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.75 -1.5) (end 1.75 1.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.75 -1.5) (end 1.75 -1.5) (layer F.CrtYd) (width 0.05))
+    (fp_circle (center -2.2 0.8) (end -2.05 0.8) (layer F.Fab) (width 0.2))
+    (fp_line (start 1.25 -1) (end -1.25 -1) (layer F.Fab) (width 0.127))
+    (fp_line (start 1.25 1) (end 1.25 -1) (layer F.Fab) (width 0.127))
+    (fp_line (start -1.25 1) (end 1.25 1) (layer F.Fab) (width 0.127))
+    (fp_line (start -1.25 -1) (end -1.25 1) (layer F.Fab) (width 0.127))
+    (pad 4 smd rect (at -0.95 -0.75 90) (size 1.1 1) (layers F.Cu F.Paste F.Mask)
+      (net 4 +3V3))
+    (pad 3 smd rect (at 0.95 -0.75 90) (size 1.1 1) (layers F.Cu F.Paste F.Mask)
+      (net 1 "Net-(R1-Pad2)"))
+    (pad 2 smd rect (at 0.95 0.75 90) (size 1.1 1) (layers F.Cu F.Paste F.Mask)
+      (net 3 GND))
+    (pad 1 smd rect (at -0.95 0.75 90) (size 1.1 1) (layers F.Cu F.Paste F.Mask)
+      (net 4 +3V3))
+  )
+
+  (module CY62148GN-45ZSXI:SOIC127P1176X120-32N (layer F.Cu) (tedit 5F603937) (tstamp 5F613C2A)
+    (at 151.8412 79.6036 270)
+    (path /5F62178D/5F64044A)
+    (attr smd)
+    (fp_text reference U8 (at -3.41 -11.352 90) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.015)))
+    )
+    (fp_text value CY62148GN-45ZSXI (at 8.8392 2.2352) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.015)))
+    )
+    (fp_line (start 6.59 -10.79) (end 6.59 10.79) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -6.59 -10.79) (end -6.59 10.79) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -6.59 10.79) (end 6.59 10.79) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -6.59 -10.79) (end 6.59 -10.79) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 5.145 -10.54) (end 5.145 10.54) (layer F.Fab) (width 0.127))
+    (fp_line (start -5.145 -10.54) (end -5.145 10.54) (layer F.Fab) (width 0.127))
+    (fp_line (start -5.145 10.54) (end 5.145 10.54) (layer F.SilkS) (width 0.127))
+    (fp_line (start -5.145 -10.54) (end 5.145 -10.54) (layer F.SilkS) (width 0.127))
+    (fp_line (start -5.145 10.54) (end 5.145 10.54) (layer F.Fab) (width 0.127))
+    (fp_line (start -5.145 -10.54) (end 5.145 -10.54) (layer F.Fab) (width 0.127))
+    (fp_circle (center -7.06 -10.135) (end -6.96 -10.135) (layer F.Fab) (width 0.2))
+    (fp_circle (center -7.06 -10.135) (end -6.96 -10.135) (layer F.SilkS) (width 0.2))
+    (pad 32 smd rect (at 5.62 -9.525 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 4 +3V3))
+    (pad 31 smd rect (at 5.62 -8.255 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 42 SRAM_A15))
+    (pad 30 smd rect (at 5.62 -6.985 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 43 SRAM_A18))
+    (pad 29 smd rect (at 5.62 -5.715 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 44 SRAM_WE_n))
+    (pad 28 smd rect (at 5.62 -4.445 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 45 SRAM_A13))
+    (pad 27 smd rect (at 5.62 -3.175 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 46 SRAM_A8))
+    (pad 26 smd rect (at 5.62 -1.905 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 47 SRAM_A9))
+    (pad 25 smd rect (at 5.62 -0.635 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 48 SRAM_A11))
+    (pad 24 smd rect (at 5.62 0.635 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 49 SRAM_OE_n))
+    (pad 23 smd rect (at 5.62 1.905 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 50 SRAM_A10))
+    (pad 22 smd rect (at 5.62 3.175 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 51 SRAM_CE_n))
+    (pad 21 smd rect (at 5.62 4.445 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 52 SRAM_D7))
+    (pad 20 smd rect (at 5.62 5.715 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 53 SRAM_D6))
+    (pad 19 smd rect (at 5.62 6.985 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 54 SRAM_D5))
+    (pad 18 smd rect (at 5.62 8.255 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 55 SRAM_D4))
+    (pad 17 smd rect (at 5.62 9.525 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 56 SRAM_D3))
+    (pad 16 smd rect (at -5.62 9.525 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 3 GND))
+    (pad 15 smd rect (at -5.62 8.255 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 57 SRAM_D2))
+    (pad 14 smd rect (at -5.62 6.985 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 58 SRAM_D1))
+    (pad 13 smd rect (at -5.62 5.715 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 59 SRAM_D0))
+    (pad 12 smd rect (at -5.62 4.445 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 60 SRAM_A0))
+    (pad 11 smd rect (at -5.62 3.175 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 61 SRAM_A1))
+    (pad 10 smd rect (at -5.62 1.905 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 62 SRAM_A2))
+    (pad 9 smd rect (at -5.62 0.635 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 63 SRAM_A3))
+    (pad 8 smd rect (at -5.62 -0.635 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 64 SRAM_A4))
+    (pad 7 smd rect (at -5.62 -1.905 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 65 SRAM_A5))
+    (pad 6 smd rect (at -5.62 -3.175 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 126 SRAM_A6))
+    (pad 5 smd rect (at -5.62 -4.445 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 66 SRAM_A7))
+    (pad 4 smd rect (at -5.62 -5.715 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 67 SRAM_A12))
+    (pad 3 smd rect (at -5.62 -6.985 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 68 SRAM_A14))
+    (pad 2 smd rect (at -5.62 -8.255 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 69 SRAM_A16))
+    (pad 1 smd rect (at -5.62 -9.525 270) (size 1.44 0.61) (layers F.Cu F.Paste F.Mask)
+      (net 70 SRAM_A17))
+  )
+
+  (module MIC5504-1:SOT23-5P95_280X145XL45X37N (layer B.Cu) (tedit 5F5FD964) (tstamp 5F63210B)
+    (at 140.1826 43.5102)
+    (path /5F62178D/5F8012E4)
+    (attr smd)
+    (fp_text reference U7 (at 0.17427 2.108144) (layer B.SilkS)
+      (effects (font (size 0.480762 0.480762) (thickness 0.015)) (justify mirror))
+    )
+    (fp_text value MIC5504-1.2YM5-TR (at 6.392076 -2.201154) (layer B.Fab)
+      (effects (font (size 0.481301 0.481301) (thickness 0.015)) (justify mirror))
+    )
+    (fp_circle (center -1.7 1.5) (end -1.57 1.5) (layer B.SilkS) (width 0.1))
+    (fp_line (start 1.91 -1.7) (end 1.91 1.7) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.91 -1.7) (end 1.91 -1.7) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.91 1.7) (end -1.91 -1.7) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 1.91 1.7) (end -1.91 1.7) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.8 -1.45) (end 0.8 1.45) (layer B.Fab) (width 0.127))
+    (fp_line (start -0.8 1.45) (end -0.8 -1.45) (layer B.Fab) (width 0.127))
+    (pad 5 smd rect (at 1.14 0.95) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask)
+      (net 5 +1V2))
+    (pad 4 smd rect (at 1.14 -0.95) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask))
+    (pad 3 smd rect (at -1.14 -0.95) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask)
+      (net 4 +3V3))
+    (pad 2 smd rect (at -1.14 0) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask)
+      (net 3 GND))
+    (pad 1 smd rect (at -1.14 0.95) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask)
+      (net 4 +3V3))
+  )
+
+  (module SN74LVC245APW:SOP65P640X120-20N (layer F.Cu) (tedit 5F5FB988) (tstamp 5F607F23)
+    (at 123.825 62.7634)
+    (path /5F6217EE/5F623800)
+    (attr smd)
+    (fp_text reference U6 (at -0.325 -4.385) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.015)))
+    )
+    (fp_text value SN74LVC245APW (at 7.295 4.385) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.015)))
+    )
+    (fp_line (start 3.91 -3.55) (end 3.91 3.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -3.91 -3.55) (end -3.91 3.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -3.91 3.55) (end 3.91 3.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -3.91 -3.55) (end 3.91 -3.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 2.2 -3.25) (end 2.2 3.25) (layer F.Fab) (width 0.127))
+    (fp_line (start -2.2 -3.25) (end -2.2 3.25) (layer F.Fab) (width 0.127))
+    (fp_line (start -2.2 3.45) (end 2.2 3.45) (layer F.SilkS) (width 0.127))
+    (fp_line (start -2.2 -3.45) (end 2.2 -3.45) (layer F.SilkS) (width 0.127))
+    (fp_line (start -2.2 3.25) (end 2.2 3.25) (layer F.Fab) (width 0.127))
+    (fp_line (start -2.2 -3.25) (end 2.2 -3.25) (layer F.Fab) (width 0.127))
+    (fp_circle (center -4.19 -2.925) (end -4.09 -2.925) (layer F.Fab) (width 0.2))
+    (fp_circle (center -4.19 -2.925) (end -4.09 -2.925) (layer F.SilkS) (width 0.2))
+    (pad 20 smd rect (at 2.87 -2.925) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 4 +3V3))
+    (pad 19 smd rect (at 2.87 -2.275) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 80 BUF2_OE__n))
+    (pad 18 smd rect (at 2.87 -1.625) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 74 AD7_3V))
+    (pad 17 smd rect (at 2.87 -0.975) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 73 AD6_3V))
+    (pad 16 smd rect (at 2.87 -0.325) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 72 AD5_3V))
+    (pad 15 smd rect (at 2.87 0.325) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 71 AD4_3V))
+    (pad 14 smd rect (at 2.87 0.975) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 75 AD3_3V))
+    (pad 13 smd rect (at 2.87 1.625) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 76 AD2_3V))
+    (pad 12 smd rect (at 2.87 2.275) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 77 AD1_3V))
+    (pad 11 smd rect (at 2.87 2.925) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 78 AD0_3V))
+    (pad 10 smd rect (at -2.87 2.925) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 3 GND))
+    (pad 9 smd rect (at -2.87 2.275) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 14 AD0_5V))
+    (pad 8 smd rect (at -2.87 1.625) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 16 AD1_5V))
+    (pad 7 smd rect (at -2.87 0.975) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 18 AD2_5V))
+    (pad 6 smd rect (at -2.87 0.325) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 19 AD3_5V))
+    (pad 5 smd rect (at -2.87 -0.325) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 21 AD4_5V))
+    (pad 4 smd rect (at -2.87 -0.975) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 23 AD5_5V))
+    (pad 3 smd rect (at -2.87 -1.625) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 25 AD6_5V))
+    (pad 2 smd rect (at -2.87 -2.275) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 27 AD7_5V))
+    (pad 1 smd rect (at -2.87 -2.925) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 81 BUF2_DIR))
+  )
+
+  (module SN74LVC245APW:SOP65P640X120-20N (layer B.Cu) (tedit 5F5FB988) (tstamp 5F607EFF)
+    (at 138.176 72.1868)
+    (path /5F6217EE/5F6230CD)
+    (attr smd)
+    (fp_text reference U5 (at -0.325 4.385) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.015)) (justify mirror))
+    )
+    (fp_text value SN74LVC245APW (at 7.295 -4.385) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.015)) (justify mirror))
+    )
+    (fp_line (start 3.91 3.55) (end 3.91 -3.55) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -3.91 3.55) (end -3.91 -3.55) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -3.91 -3.55) (end 3.91 -3.55) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -3.91 3.55) (end 3.91 3.55) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 2.2 3.25) (end 2.2 -3.25) (layer B.Fab) (width 0.127))
+    (fp_line (start -2.2 3.25) (end -2.2 -3.25) (layer B.Fab) (width 0.127))
+    (fp_line (start -2.2 -3.45) (end 2.2 -3.45) (layer B.SilkS) (width 0.127))
+    (fp_line (start -2.2 3.45) (end 2.2 3.45) (layer B.SilkS) (width 0.127))
+    (fp_line (start -2.2 -3.25) (end 2.2 -3.25) (layer B.Fab) (width 0.127))
+    (fp_line (start -2.2 3.25) (end 2.2 3.25) (layer B.Fab) (width 0.127))
+    (fp_circle (center -4.19 2.925) (end -4.09 2.925) (layer B.Fab) (width 0.2))
+    (fp_circle (center -4.19 2.925) (end -4.09 2.925) (layer B.SilkS) (width 0.2))
+    (pad 20 smd rect (at 2.87 2.925) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 4 +3V3))
+    (pad 19 smd rect (at 2.87 2.275) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 79 BUF1_OE__n))
+    (pad 18 smd rect (at 2.87 1.625) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 121 INTA_n_3V))
+    (pad 17 smd rect (at 2.87 0.975) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 122 DEN_3V))
+    (pad 16 smd rect (at 2.87 0.325) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 123 DTR_3V))
+    (pad 15 smd rect (at 2.87 -0.325) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 124 IOM_3V))
+    (pad 14 smd rect (at 2.87 -0.975) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 125 WR_3V))
+    (pad 13 smd rect (at 2.87 -1.625) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 120 RD_3V))
+    (pad 12 smd rect (at 2.87 -2.275) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask))
+    (pad 11 smd rect (at 2.87 -2.925) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask))
+    (pad 10 smd rect (at -2.87 -2.925) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 3 GND))
+    (pad 9 smd rect (at -2.87 -2.275) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask))
+    (pad 8 smd rect (at -2.87 -1.625) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask))
+    (pad 7 smd rect (at -2.87 -0.975) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 20 RD_5V))
+    (pad 6 smd rect (at -2.87 -0.325) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 26 WR_5V))
+    (pad 5 smd rect (at -2.87 0.325) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 28 IOM_5V))
+    (pad 4 smd rect (at -2.87 0.975) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 30 DTR_5V))
+    (pad 3 smd rect (at -2.87 1.625) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 32 DEN_5V))
+    (pad 2 smd rect (at -2.87 2.275) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 36 INTA_n_5V))
+    (pad 1 smd rect (at -2.87 2.925) (size 1.57 0.41) (layers B.Cu B.Paste B.Mask)
+      (net 3 GND))
+  )
+
+  (module SN74LVC245APW:SOP65P640X120-20N (layer F.Cu) (tedit 5F5FB988) (tstamp 5F607EDB)
+    (at 123.6726 81.7118)
+    (path /5F6217EE/5F622E6C)
+    (attr smd)
+    (fp_text reference U4 (at -0.325 -4.385) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.015)))
+    )
+    (fp_text value SN74LVC245APW (at 7.295 4.385) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.015)))
+    )
+    (fp_line (start 3.91 -3.55) (end 3.91 3.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -3.91 -3.55) (end -3.91 3.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -3.91 3.55) (end 3.91 3.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -3.91 -3.55) (end 3.91 -3.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 2.2 -3.25) (end 2.2 3.25) (layer F.Fab) (width 0.127))
+    (fp_line (start -2.2 -3.25) (end -2.2 3.25) (layer F.Fab) (width 0.127))
+    (fp_line (start -2.2 3.45) (end 2.2 3.45) (layer F.SilkS) (width 0.127))
+    (fp_line (start -2.2 -3.45) (end 2.2 -3.45) (layer F.SilkS) (width 0.127))
+    (fp_line (start -2.2 3.25) (end 2.2 3.25) (layer F.Fab) (width 0.127))
+    (fp_line (start -2.2 -3.25) (end 2.2 -3.25) (layer F.Fab) (width 0.127))
+    (fp_circle (center -4.19 -2.925) (end -4.09 -2.925) (layer F.Fab) (width 0.2))
+    (fp_circle (center -4.19 -2.925) (end -4.09 -2.925) (layer F.SilkS) (width 0.2))
+    (pad 20 smd rect (at 2.87 -2.925) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 4 +3V3))
+    (pad 19 smd rect (at 2.87 -2.275) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 3 GND))
+    (pad 18 smd rect (at 2.87 -1.625) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 24 HLDA_5V))
+    (pad 17 smd rect (at 2.87 -0.975) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 112 HOLD_3V))
+    (pad 16 smd rect (at 2.87 -0.325) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 113 NMI_3V))
+    (pad 15 smd rect (at 2.87 0.325) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 114 INTR_3V))
+    (pad 14 smd rect (at 2.87 0.975) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 115 CLK_3V))
+    (pad 13 smd rect (at 2.87 1.625) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 116 RESET_3V))
+    (pad 12 smd rect (at 2.87 2.275) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 117 READY_3V))
+    (pad 11 smd rect (at 2.87 2.925) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 34 ALE_5V))
+    (pad 10 smd rect (at -2.87 2.925) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 3 GND))
+    (pad 9 smd rect (at -2.87 2.275) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 118 ALE_3V))
+    (pad 8 smd rect (at -2.87 1.625) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 39 READY_5V))
+    (pad 7 smd rect (at -2.87 0.975) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 41 RESET_5V))
+    (pad 6 smd rect (at -2.87 0.325) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 8 CLK_5V))
+    (pad 5 smd rect (at -2.87 -0.325) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 10 INTR_5V))
+    (pad 4 smd rect (at -2.87 -0.975) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 12 NMI_5V))
+    (pad 3 smd rect (at -2.87 -1.625) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 22 HOLD_5V))
+    (pad 2 smd rect (at -2.87 -2.275) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 119 HLDA_3V))
+    (pad 1 smd rect (at -2.87 -2.925) (size 1.57 0.41) (layers F.Cu F.Paste F.Mask)
+      (net 4 +3V3))
+  )
+
+  (module MIC5504-1:SOT23-5P95_280X145XL45X37N (layer B.Cu) (tedit 5F5FD964) (tstamp 5F632092)
+    (at 135.382 39.116)
+    (path /5F62178D/5F8012DE)
+    (attr smd)
+    (fp_text reference U3 (at 0.17427 2.108144) (layer B.SilkS)
+      (effects (font (size 0.480762 0.480762) (thickness 0.015)) (justify mirror))
+    )
+    (fp_text value MIC5504-3.3YM5-TR (at 6.392076 -2.201154) (layer B.Fab)
+      (effects (font (size 0.481301 0.481301) (thickness 0.015)) (justify mirror))
+    )
+    (fp_circle (center -1.7 1.5) (end -1.57 1.5) (layer B.SilkS) (width 0.1))
+    (fp_line (start 1.91 -1.7) (end 1.91 1.7) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.91 -1.7) (end 1.91 -1.7) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.91 1.7) (end -1.91 -1.7) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 1.91 1.7) (end -1.91 1.7) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.8 -1.45) (end 0.8 1.45) (layer B.Fab) (width 0.127))
+    (fp_line (start -0.8 1.45) (end -0.8 -1.45) (layer B.Fab) (width 0.127))
+    (pad 5 smd rect (at 1.14 0.95) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask)
+      (net 4 +3V3))
+    (pad 4 smd rect (at 1.14 -0.95) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask))
+    (pad 3 smd rect (at -1.14 -0.95) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask)
+      (net 6 +5V))
+    (pad 2 smd rect (at -1.14 0) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask)
+      (net 3 GND))
+    (pad 1 smd rect (at -1.14 0.95) (size 1.14 0.6) (layers B.Cu B.Paste B.Mask)
+      (net 6 +5V))
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F764EFC)
+    (at 148.971 54.991 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5F7CE133)
+    (attr smd)
+    (fp_text reference C31 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F78D7DF)
+    (at 143.4338 79.7306)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/60EB6252)
+    (attr smd)
+    (fp_text reference C30 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F78D7D0)
+    (at 161.8512 41.8084)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/60ECB869)
+    (attr smd)
+    (fp_text reference C29 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F78BA08)
+    (at 145.542 57.023 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/60E87B06)
+    (attr smd)
+    (fp_text reference C28 (at 0 1.17 270) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 270) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 270) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_DIP:DIP-40_W15.24mm (layer F.Cu) (tedit 5F684397) (tstamp 5F632176)
+    (at 116.3978 40.7556)
+    (descr "40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils)")
+    (tags "THT DIP DIL PDIP 2.54mm 15.24mm 600mil")
+    (path /5F6217EE/5F7A8941)
+    (fp_text reference U9 (at -2.174 -0.1156) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 8088_Min_Mode (at 7.478 48.5) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 2.6012 0.24) (layer F.Fab) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 16.3 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 16.3 49.8) (end 16.3 -1.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.05 49.8) (end 16.3 49.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.05 -1.55) (end -1.05 49.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 14.08 -1.33) (end 8.62 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 14.08 49.59) (end 14.08 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.16 49.59) (end 14.08 49.59) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.16 -1.33) (end 1.16 49.59) (layer F.SilkS) (width 0.12))
+    (fp_line (start 6.62 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0.255 -0.27) (end 1.255 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.255 49.53) (end 0.255 -0.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 14.985 49.53) (end 0.255 49.53) (layer F.Fab) (width 0.1))
+    (fp_line (start 14.985 -1.27) (end 14.985 49.53) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.255 -1.27) (end 14.985 -1.27) (layer F.Fab) (width 0.1))
+    (fp_arc (start 7.62 -1.33) (end 6.62 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
+    (pad 40 thru_hole oval (at 15.24 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 6 +5V))
+    (pad 20 thru_hole oval (at 0 48.26) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 3 GND))
+    (pad 39 thru_hole oval (at 15.24 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 7 A15_5V))
+    (pad 19 thru_hole oval (at 0 45.72) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 8 CLK_5V))
+    (pad 38 thru_hole oval (at 15.24 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 9 A16_5V))
+    (pad 18 thru_hole oval (at 0 43.18) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 10 INTR_5V))
+    (pad 37 thru_hole oval (at 15.24 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 11 A17_5V))
+    (pad 17 thru_hole oval (at 0 40.64) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 12 NMI_5V))
+    (pad 36 thru_hole oval (at 15.24 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 13 A18_5V))
+    (pad 16 thru_hole oval (at 0 38.1) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 14 AD0_5V))
+    (pad 35 thru_hole oval (at 15.24 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 15 A19_5V))
+    (pad 15 thru_hole oval (at 0 35.56) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 16 AD1_5V))
+    (pad 34 thru_hole oval (at 15.24 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 17 SSO_5V))
+    (pad 14 thru_hole oval (at 0 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 18 AD2_5V))
+    (pad 33 thru_hole oval (at 15.24 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
+    (pad 13 thru_hole oval (at 0 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 19 AD3_5V))
+    (pad 32 thru_hole oval (at 15.24 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 20 RD_5V))
+    (pad 12 thru_hole oval (at 0 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 21 AD4_5V))
+    (pad 31 thru_hole oval (at 15.24 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 22 HOLD_5V))
+    (pad 11 thru_hole oval (at 0 25.4) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 23 AD5_5V))
+    (pad 30 thru_hole oval (at 15.24 25.4) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 24 HLDA_5V))
+    (pad 10 thru_hole oval (at 0 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 25 AD6_5V))
+    (pad 29 thru_hole oval (at 15.24 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 26 WR_5V))
+    (pad 9 thru_hole oval (at 0 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 27 AD7_5V))
+    (pad 28 thru_hole oval (at 15.24 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 28 IOM_5V))
+    (pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 29 A8_5V))
+    (pad 27 thru_hole oval (at 15.24 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 30 DTR_5V))
+    (pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 31 A9_5V))
+    (pad 26 thru_hole oval (at 15.24 35.56) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 32 DEN_5V))
+    (pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 33 A10_5V))
+    (pad 25 thru_hole oval (at 15.24 38.1) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 34 ALE_5V))
+    (pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 35 A11_5V))
+    (pad 24 thru_hole oval (at 15.24 40.64) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 36 INTA_n_5V))
+    (pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 37 A12_5V))
+    (pad 23 thru_hole oval (at 15.24 43.18) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
+    (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 38 A13_5V))
+    (pad 22 thru_hole oval (at 15.24 45.72) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 39 READY_5V))
+    (pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 40 A14_5V))
+    (pad 21 thru_hole oval (at 15.24 48.26) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 41 RESET_5V))
+    (pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 3 GND))
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645CB7)
+    (at 126.4666 75.9714 90)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F6217EE/5FA1A7AD)
+    (attr smd)
+    (fp_text reference C23 (at 0 1.17 270) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 270) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 270) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5F631EEF)
+    (at 160.1216 64.897 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F609430/5F7DBF00)
+    (attr smd)
+    (fp_text reference R1 (at 0 -1.17 90) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 33 (at 0 1.17 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)))
+    )
+    (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 1 "Net-(R1-Pad2)"))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 2 CLK_100MHZ))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_QFP:TQFP-144_20x20mm_P0.5mm (layer F.Cu) (tedit 5D9F72B1) (tstamp 5F609B49)
+    (at 149.987 53.594)
+    (descr "TQFP, 144 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py")
+    (tags "TQFP QFP")
+    (path /5F609430/5F6440A9)
+    (attr smd)
+    (fp_text reference U1 (at 8.5598 -12.2936) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value XC6SLX9-TQG144 (at 0 12.35) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 0) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 11.65 9.15) (end 11.65 0) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 10.25 9.15) (end 11.65 9.15) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 10.25 10.25) (end 10.25 9.15) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 9.15 10.25) (end 10.25 10.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 9.15 11.65) (end 9.15 10.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0 11.65) (end 9.15 11.65) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -11.65 9.15) (end -11.65 0) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -10.25 9.15) (end -11.65 9.15) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -10.25 10.25) (end -10.25 9.15) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -9.15 10.25) (end -10.25 10.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -9.15 11.65) (end -9.15 10.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0 11.65) (end -9.15 11.65) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 11.65 -9.15) (end 11.65 0) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 10.25 -9.15) (end 11.65 -9.15) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 10.25 -10.25) (end 10.25 -9.15) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 9.15 -10.25) (end 10.25 -10.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 9.15 -11.65) (end 9.15 -10.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0 -11.65) (end 9.15 -11.65) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -11.65 -9.15) (end -11.65 0) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -10.25 -9.15) (end -11.65 -9.15) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -10.25 -10.25) (end -10.25 -9.15) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -9.15 -10.25) (end -10.25 -10.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -9.15 -11.65) (end -9.15 -10.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0 -11.65) (end -9.15 -11.65) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -10 -9) (end -9 -10) (layer F.Fab) (width 0.1))
+    (fp_line (start -10 10) (end -10 -9) (layer F.Fab) (width 0.1))
+    (fp_line (start 10 10) (end -10 10) (layer F.Fab) (width 0.1))
+    (fp_line (start 10 -10) (end 10 10) (layer F.Fab) (width 0.1))
+    (fp_line (start -9 -10) (end 10 -10) (layer F.Fab) (width 0.1))
+    (fp_line (start -10.11 -9.16) (end -11.4 -9.16) (layer F.SilkS) (width 0.12))
+    (fp_line (start -10.11 -10.11) (end -10.11 -9.16) (layer F.SilkS) (width 0.12))
+    (fp_line (start -9.16 -10.11) (end -10.11 -10.11) (layer F.SilkS) (width 0.12))
+    (fp_line (start 10.11 -10.11) (end 10.11 -9.16) (layer F.SilkS) (width 0.12))
+    (fp_line (start 9.16 -10.11) (end 10.11 -10.11) (layer F.SilkS) (width 0.12))
+    (fp_line (start -10.11 10.11) (end -10.11 9.16) (layer F.SilkS) (width 0.12))
+    (fp_line (start -9.16 10.11) (end -10.11 10.11) (layer F.SilkS) (width 0.12))
+    (fp_line (start 10.11 10.11) (end 10.11 9.16) (layer F.SilkS) (width 0.12))
+    (fp_line (start 9.16 10.11) (end 10.11 10.11) (layer F.SilkS) (width 0.12))
+    (pad 144 smd roundrect (at -8.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 143 smd roundrect (at -8.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 7 A15_5V))
+    (pad 142 smd roundrect (at -7.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 40 A14_5V))
+    (pad 141 smd roundrect (at -7.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 140 smd roundrect (at -6.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 139 smd roundrect (at -6.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 138 smd roundrect (at -5.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 137 smd roundrect (at -5.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 136 smd roundrect (at -4.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 135 smd roundrect (at -4.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 134 smd roundrect (at -3.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 133 smd roundrect (at -3.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 132 smd roundrect (at -2.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 60 SRAM_A0))
+    (pad 131 smd roundrect (at -2.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 105 LED7))
+    (pad 130 smd roundrect (at -1.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 129 smd roundrect (at -1.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 128 smd roundrect (at -0.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (pad 127 smd roundrect (at -0.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 103 LED6))
+    (pad 126 smd roundrect (at 0.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 61 SRAM_A1))
+    (pad 125 smd roundrect (at 0.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 124 smd roundrect (at 1.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 62 SRAM_A2))
+    (pad 123 smd roundrect (at 1.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 63 SRAM_A3))
+    (pad 122 smd roundrect (at 2.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 121 smd roundrect (at 2.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 101 LED5))
+    (pad 120 smd roundrect (at 3.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 99 LED4))
+    (pad 119 smd roundrect (at 3.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 59 SRAM_D0))
+    (pad 118 smd roundrect (at 4.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 58 SRAM_D1))
+    (pad 117 smd roundrect (at 4.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 57 SRAM_D2))
+    (pad 116 smd roundrect (at 5.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 97 LED3))
+    (pad 115 smd roundrect (at 5.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 114 smd roundrect (at 6.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 95 LED2))
+    (pad 113 smd roundrect (at 6.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 112 smd roundrect (at 7.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 93 LED1))
+    (pad 111 smd roundrect (at 7.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 91 LED0))
+    (pad 110 smd roundrect (at 8.25 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 85 "Net-(J1-Pad2)"))
+    (pad 109 smd roundrect (at 8.75 -10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 84 "Net-(J1-Pad3)"))
+    (pad 108 smd roundrect (at 10.6625 -8.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 107 smd roundrect (at 10.6625 -8.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 83 "Net-(J1-Pad4)"))
+    (pad 106 smd roundrect (at 10.6625 -7.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 82 "Net-(J1-Pad5)"))
+    (pad 105 smd roundrect (at 10.6625 -7.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 104 smd roundrect (at 10.6625 -6.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 103 smd roundrect (at 10.6625 -6.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 102 smd roundrect (at 10.6625 -5.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 101 smd roundrect (at 10.6625 -5.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 100 smd roundrect (at 10.6625 -4.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 42 SRAM_A15))
+    (pad 99 smd roundrect (at 10.6625 -4.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 43 SRAM_A18))
+    (pad 98 smd roundrect (at 10.6625 -3.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 44 SRAM_WE_n))
+    (pad 97 smd roundrect (at 10.6625 -3.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 45 SRAM_A13))
+    (pad 96 smd roundrect (at 10.6625 -2.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 95 smd roundrect (at 10.6625 -2.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 46 SRAM_A8))
+    (pad 94 smd roundrect (at 10.6625 -1.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 47 SRAM_A9))
+    (pad 93 smd roundrect (at 10.6625 -1.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 48 SRAM_A11))
+    (pad 92 smd roundrect (at 10.6625 -0.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 49 SRAM_OE_n))
+    (pad 91 smd roundrect (at 10.6625 -0.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 90 smd roundrect (at 10.6625 0.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 89 smd roundrect (at 10.6625 0.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (pad 88 smd roundrect (at 10.6625 1.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 50 SRAM_A10))
+    (pad 87 smd roundrect (at 10.6625 1.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 51 SRAM_CE_n))
+    (pad 86 smd roundrect (at 10.6625 2.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 85 smd roundrect (at 10.6625 2.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 52 SRAM_D7))
+    (pad 84 smd roundrect (at 10.6625 3.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 2 CLK_100MHZ))
+    (pad 83 smd roundrect (at 10.6625 3.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 53 SRAM_D6))
+    (pad 82 smd roundrect (at 10.6625 4.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 54 SRAM_D5))
+    (pad 81 smd roundrect (at 10.6625 4.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 55 SRAM_D4))
+    (pad 80 smd roundrect (at 10.6625 5.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 56 SRAM_D3))
+    (pad 79 smd roundrect (at 10.6625 5.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 70 SRAM_A17))
+    (pad 78 smd roundrect (at 10.6625 6.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 69 SRAM_A16))
+    (pad 77 smd roundrect (at 10.6625 6.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 76 smd roundrect (at 10.6625 7.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 75 smd roundrect (at 10.6625 7.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 68 SRAM_A14))
+    (pad 74 smd roundrect (at 10.6625 8.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 67 SRAM_A12))
+    (pad 73 smd roundrect (at 10.6625 8.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 72 smd roundrect (at 8.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 71 smd roundrect (at 8.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 108 FPGA_DONE))
+    (pad 70 smd roundrect (at 7.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 111 "Net-(R16-Pad1)"))
+    (pad 69 smd roundrect (at 7.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 106 FPGA_M0))
+    (pad 68 smd roundrect (at 6.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 67 smd roundrect (at 6.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 66 SRAM_A7))
+    (pad 66 smd roundrect (at 5.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 126 SRAM_A6))
+    (pad 65 smd roundrect (at 5.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 87 SPI_DOUT))
+    (pad 64 smd roundrect (at 4.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 88 SPI_DIN))
+    (pad 63 smd roundrect (at 4.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 62 smd roundrect (at 3.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 65 SRAM_A5))
+    (pad 61 smd roundrect (at 3.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 64 SRAM_A4))
+    (pad 60 smd roundrect (at 2.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 107 FPGA_M1))
+    (pad 59 smd roundrect (at 2.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 79 BUF1_OE__n))
+    (pad 58 smd roundrect (at 1.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 121 INTA_n_3V))
+    (pad 57 smd roundrect (at 1.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 122 DEN_3V))
+    (pad 56 smd roundrect (at 0.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 123 DTR_3V))
+    (pad 55 smd roundrect (at 0.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 124 IOM_3V))
+    (pad 54 smd roundrect (at -0.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 53 smd roundrect (at -0.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 52 smd roundrect (at -1.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (pad 51 smd roundrect (at -1.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 125 WR_3V))
+    (pad 50 smd roundrect (at -2.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 120 RD_3V))
+    (pad 49 smd roundrect (at -2.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 48 smd roundrect (at -3.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 117 READY_3V))
+    (pad 47 smd roundrect (at -3.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 116 RESET_3V))
+    (pad 46 smd roundrect (at -4.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 115 CLK_3V))
+    (pad 45 smd roundrect (at -4.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 114 INTR_3V))
+    (pad 44 smd roundrect (at -5.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 113 NMI_3V))
+    (pad 43 smd roundrect (at -5.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 112 HOLD_3V))
+    (pad 42 smd roundrect (at -6.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 41 smd roundrect (at -6.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 118 ALE_3V))
+    (pad 40 smd roundrect (at -7.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 119 HLDA_3V))
+    (pad 39 smd roundrect (at -7.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 110 FPGA_INIT))
+    (pad 38 smd roundrect (at -8.25 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 89 SPI_CS_n))
+    (pad 37 smd roundrect (at -8.75 10.6625) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 109 FPGA_PROGRAM_n))
+    (pad 36 smd roundrect (at -10.6625 8.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 35 smd roundrect (at -10.6625 8.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 78 AD0_3V))
+    (pad 34 smd roundrect (at -10.6625 7.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 77 AD1_3V))
+    (pad 33 smd roundrect (at -10.6625 7.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 76 AD2_3V))
+    (pad 32 smd roundrect (at -10.6625 6.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 75 AD3_3V))
+    (pad 31 smd roundrect (at -10.6625 6.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 30 smd roundrect (at -10.6625 5.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 29 smd roundrect (at -10.6625 5.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 28 smd roundrect (at -10.6625 4.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (pad 27 smd roundrect (at -10.6625 4.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 71 AD4_3V))
+    (pad 26 smd roundrect (at -10.6625 3.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 72 AD5_3V))
+    (pad 25 smd roundrect (at -10.6625 3.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 24 smd roundrect (at -10.6625 2.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 23 smd roundrect (at -10.6625 2.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 73 AD6_3V))
+    (pad 22 smd roundrect (at -10.6625 1.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 74 AD7_3V))
+    (pad 21 smd roundrect (at -10.6625 1.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 80 BUF2_OE__n))
+    (pad 20 smd roundrect (at -10.6625 0.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 19 smd roundrect (at -10.6625 0.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (pad 18 smd roundrect (at -10.6625 -0.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 17 smd roundrect (at -10.6625 -0.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 16 smd roundrect (at -10.6625 -1.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 81 BUF2_DIR))
+    (pad 15 smd roundrect (at -10.6625 -1.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+    (pad 14 smd roundrect (at -10.6625 -2.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 29 A8_5V))
+    (pad 13 smd roundrect (at -10.6625 -2.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 12 smd roundrect (at -10.6625 -3.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 17 SSO_5V))
+    (pad 11 smd roundrect (at -10.6625 -3.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 31 A9_5V))
+    (pad 10 smd roundrect (at -10.6625 -4.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 15 A19_5V))
+    (pad 9 smd roundrect (at -10.6625 -4.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 33 A10_5V))
+    (pad 8 smd roundrect (at -10.6625 -5.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 13 A18_5V))
+    (pad 7 smd roundrect (at -10.6625 -5.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 35 A11_5V))
+    (pad 6 smd roundrect (at -10.6625 -6.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 11 A17_5V))
+    (pad 5 smd roundrect (at -10.6625 -6.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 37 A12_5V))
+    (pad 4 smd roundrect (at -10.6625 -7.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 3 smd roundrect (at -10.6625 -7.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 2 smd roundrect (at -10.6625 -8.25) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 9 A16_5V))
+    (pad 1 smd roundrect (at -10.6625 -8.75) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 38 A13_5V))
+    (model ${KISYS3DMOD}/Package_QFP.3dshapes/TQFP-144_20x20mm_P0.5mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F683051)
+    (at 156.6672 67.4116 90)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FF27C34)
+    (attr smd)
+    (fp_text reference C27 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F683042)
+    (at 157.988 40.386)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FF1DF62)
+    (attr smd)
+    (fp_text reference C26 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F683033)
+    (at 144.018 40.386)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FF14247)
+    (attr smd)
+    (fp_text reference C25 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6700E3)
+    (at 157.7848 67.7672 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F609430/5FDFB8A4)
+    (attr smd)
+    (fp_text reference R16 (at 0 1.17 270) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 33 (at 0 -1.17 270) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 270) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 86 SPI_CLK))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 111 "Net-(R16-Pad1)"))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6700D4)
+    (at 135.4328 80.1624)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F609430/5FD82F74)
+    (attr smd)
+    (fp_text reference R15 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7k (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 89 SPI_CS_n))
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6470DD)
+    (at 142.5702 60.7568 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F609430/5FBA7A81)
+    (attr smd)
+    (fp_text reference R14 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7k (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 110 FPGA_INIT))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6470CE)
+    (at 141.097 61.214 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F609430/5FBD99FB)
+    (attr smd)
+    (fp_text reference R13 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7k (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 109 FPGA_PROGRAM_n))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6470BF)
+    (at 158.369 61.214 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F609430/5FBB9847)
+    (attr smd)
+    (fp_text reference R12 (at 0 1.17 270) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7k (at 0 -1.17 270) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 270) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 108 FPGA_DONE))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6470B0)
+    (at 152.781 61.214 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F609430/5FB6A4AD)
+    (attr smd)
+    (fp_text reference R11 (at 0 1.17 270) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7k (at 0 -1.17 270) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 270) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 107 FPGA_M1))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6470A1)
+    (at 157.226 61.214 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F609430/5FB0A2A1)
+    (attr smd)
+    (fp_text reference R10 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7k (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 106 FPGA_M0))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F646DD6)
+    (at 142.6718 47.1932 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F62178D/5FAF607D)
+    (attr smd)
+    (fp_text reference C19 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F646DC7)
+    (at 139.573 40.386)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F62178D/5FADFFF0)
+    (attr smd)
+    (fp_text reference C18 (at 0 1.17 180) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 180) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 180) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F646DB8)
+    (at 139.573 39.116)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F62178D/5FAF0B3F)
+    (attr smd)
+    (fp_text reference C17 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F646DA9)
+    (at 134.366 41.275)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F62178D/5FADABE7)
+    (attr smd)
+    (fp_text reference C16 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 6 +5V))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645CC6)
+    (at 141.1224 76.9366 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F6217EE/5FA1EA71)
+    (attr smd)
+    (fp_text reference C24 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645CA8)
+    (at 123.9774 60.579 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F6217EE/5FA22BDC)
+    (attr smd)
+    (fp_text reference C22 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645C99)
+    (at 137.922 78.105)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F62178D/5FA17919)
+    (attr smd)
+    (fp_text reference C21 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645C8A)
+    (at 162.9156 83.8708 90)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F62178D/5FA14AF8)
+    (attr smd)
+    (fp_text reference C20 (at 0 1.17 270) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 270) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 270) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645C37)
+    (at 148.717 60.452 90)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FA9B5A8)
+    (attr smd)
+    (fp_text reference C15 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645C28)
+    (at 163.3728 61.595 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5F99F57A)
+    (attr smd)
+    (fp_text reference C14 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645C19)
+    (at 157.226 54.356 180)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FA9B5B7)
+    (attr smd)
+    (fp_text reference C13 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0.635 0.635) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 180) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 180) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645C0A)
+    (at 149.225 46.482 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FA9B5C7)
+    (attr smd)
+    (fp_text reference C12 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 180) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645BFB)
+    (at 142.494 53.848)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FA9B5D6)
+    (attr smd)
+    (fp_text reference C11 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 5 +1V2))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645BEC)
+    (at 154.5844 79.0956 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FA06BB4)
+    (attr smd)
+    (fp_text reference C10 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645BDD)
+    (at 163.576 55.245 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5F9B5C56)
+    (attr smd)
+    (fp_text reference C9 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645BCE)
+    (at 149.1996 67.4116 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FA708B6)
+    (attr smd)
+    (fp_text reference C8 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645BBF)
+    (at 148.3106 40.1828 180)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FA7D5C4)
+    (attr smd)
+    (fp_text reference C7 (at 0 1.17 180) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 180) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 180) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 180) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 180) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645BB0)
+    (at 136.6266 54.6608 270)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FA83EE0)
+    (attr smd)
+    (fp_text reference C6 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645BA1)
+    (at 139.4992 65.9638)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5F999BF7)
+    (attr smd)
+    (fp_text reference C5 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at -0.635 -0.381) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645B92)
+    (at 163.4998 46.0502 90)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FA8ABC6)
+    (attr smd)
+    (fp_text reference C4 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645B83)
+    (at 135.89 48.387 90)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5F98F0C7)
+    (attr smd)
+    (fp_text reference C3 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645B74)
+    (at 161.1122 67.6656 90)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5FAAB60A)
+    (attr smd)
+    (fp_text reference C2 (at 0 1.17 270) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17 270) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 270) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5F645B65)
+    (at 137.3632 63.9826 180)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5F609430/5F92D2C4)
+    (attr smd)
+    (fp_text reference C1 (at 0 1.17) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 4.7uF (at 0 -1.17) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 1.27 -1.524) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 180) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 1 smd roundrect (at -0.485 0 180) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F64262C)
+    (at 150.2156 36.703 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F62178D/5F908B53)
+    (attr smd)
+    (fp_text reference R9 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 330 (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 104 "Net-(D8-Pad2)"))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F64261D)
+    (at 151.1808 36.703 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F62178D/5F908B4D)
+    (attr smd)
+    (fp_text reference R8 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 330 (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 102 "Net-(D7-Pad2)"))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F64260E)
+    (at 152.1714 36.703 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F62178D/5F908B47)
+    (attr smd)
+    (fp_text reference R7 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 330 (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 100 "Net-(D6-Pad2)"))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6425FF)
+    (at 153.1366 36.703 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F62178D/5F908B41)
+    (attr smd)
+    (fp_text reference R6 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 330 (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 98 "Net-(D5-Pad2)"))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6425F0)
+    (at 154.1272 36.703 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F62178D/5F905C13)
+    (attr smd)
+    (fp_text reference R5 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 330 (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 96 "Net-(D4-Pad2)"))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6425E1)
+    (at 155.1178 36.703 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F62178D/5F905C0D)
+    (attr smd)
+    (fp_text reference R4 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 330 (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 94 "Net-(D3-Pad2)"))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6425D2)
+    (at 156.1084 36.703 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F62178D/5F9031C9)
+    (attr smd)
+    (fp_text reference R3 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 330 (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 92 "Net-(D2-Pad2)"))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistor_SMD:R_0402_1005Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5F6425C3)
+    (at 157.099 36.703 270)
+    (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5F62178D/5F8CD1C0)
+    (attr smd)
+    (fp_text reference R2 (at 0 1.17 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value 330 (at 0 -1.17 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -0.5 -0.25) (end -0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end 0.5 0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end 0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end -0.5 -0.25) (layer B.Fab) (width 0.1))
+    (fp_line (start -0.93 -0.47) (end -0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end 0.93 0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end 0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end -0.93 -0.47) (layer B.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)) (justify mirror))
+    )
+    (pad 1 smd roundrect (at -0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 90 "Net-(D1-Pad2)"))
+    (pad 2 smd roundrect (at 0.485 0 270) (size 0.59 0.64) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module LED_SMD:LED_0402_1005Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5F642562)
+    (at 150.114 36.6776 90)
+    (descr "LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags LED)
+    (path /5F62178D/5F8E33AD)
+    (attr smd)
+    (fp_text reference D8 (at -1.8796 0.0254 90) (layer F.SilkS)
+      (effects (font (size 0.5 0.5) (thickness 0.125)))
+    )
+    (fp_text value LED (at 0 1.17 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)))
+    )
+    (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.3 0.25) (end -0.3 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.4 0.25) (end -0.4 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_circle (center -1.09 0) (end -1.04 0) (layer F.SilkS) (width 0.1))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 104 "Net-(D8-Pad2)"))
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 105 LED7))
+    (model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module LED_SMD:LED_0402_1005Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5F642550)
+    (at 151.1046 36.6776 90)
+    (descr "LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags LED)
+    (path /5F62178D/5F8E339C)
+    (attr smd)
+    (fp_text reference D7 (at -1.8796 0.0762 90) (layer F.SilkS)
+      (effects (font (size 0.5 0.5) (thickness 0.125)))
+    )
+    (fp_text value LED (at 0 1.17 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center -1.09 0) (end -1.04 0) (layer F.SilkS) (width 0.1))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.4 0.25) (end -0.4 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.3 0.25) (end -0.3 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)))
+    )
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 103 LED6))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 102 "Net-(D7-Pad2)"))
+    (model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module LED_SMD:LED_0402_1005Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5F64253E)
+    (at 152.0952 36.6776 90)
+    (descr "LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags LED)
+    (path /5F62178D/5F8E338B)
+    (attr smd)
+    (fp_text reference D6 (at -1.905 0.0762 90) (layer F.SilkS)
+      (effects (font (size 0.5 0.5) (thickness 0.125)))
+    )
+    (fp_text value LED (at 0 1.17 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center -1.09 0) (end -1.04 0) (layer F.SilkS) (width 0.1))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.4 0.25) (end -0.4 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.3 0.25) (end -0.3 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)))
+    )
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 101 LED5))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 100 "Net-(D6-Pad2)"))
+    (model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module LED_SMD:LED_0402_1005Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5F64252C)
+    (at 153.0858 36.6776 90)
+    (descr "LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags LED)
+    (path /5F62178D/5F8E337A)
+    (attr smd)
+    (fp_text reference D5 (at -1.905 0.0508 90) (layer F.SilkS)
+      (effects (font (size 0.5 0.5) (thickness 0.125)))
+    )
+    (fp_text value LED (at 0 1.17 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center -1.09 0) (end -1.04 0) (layer F.SilkS) (width 0.1))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.4 0.25) (end -0.4 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.3 0.25) (end -0.3 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)))
+    )
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 99 LED4))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 98 "Net-(D5-Pad2)"))
+    (model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module LED_SMD:LED_0402_1005Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5F64251A)
+    (at 154.0764 36.6776 90)
+    (descr "LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags LED)
+    (path /5F62178D/5F8DEB6E)
+    (attr smd)
+    (fp_text reference D4 (at -1.905 0.0254 90) (layer F.SilkS)
+      (effects (font (size 0.5 0.5) (thickness 0.125)))
+    )
+    (fp_text value LED (at 0 1.17 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center -1.09 0) (end -1.04 0) (layer F.SilkS) (width 0.1))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.4 0.25) (end -0.4 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.3 0.25) (end -0.3 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)))
+    )
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 97 LED3))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 96 "Net-(D4-Pad2)"))
+    (model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module LED_SMD:LED_0402_1005Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5F642508)
+    (at 155.067 36.6776 90)
+    (descr "LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags LED)
+    (path /5F62178D/5F8DEB5D)
+    (attr smd)
+    (fp_text reference D3 (at -1.8796 0.0762 90) (layer F.SilkS)
+      (effects (font (size 0.5 0.5) (thickness 0.125)))
+    )
+    (fp_text value LED (at 0 1.17 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center -1.09 0) (end -1.04 0) (layer F.SilkS) (width 0.1))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.4 0.25) (end -0.4 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.3 0.25) (end -0.3 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)))
+    )
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 95 LED2))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 94 "Net-(D3-Pad2)"))
+    (model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module LED_SMD:LED_0402_1005Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5F6424F6)
+    (at 156.083 36.6776 90)
+    (descr "LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags LED)
+    (path /5F62178D/5F8DC90D)
+    (attr smd)
+    (fp_text reference D2 (at -1.905 0.0508 90) (layer F.SilkS)
+      (effects (font (size 0.5 0.5) (thickness 0.125)))
+    )
+    (fp_text value LED (at 0 1.17 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center -1.09 0) (end -1.04 0) (layer F.SilkS) (width 0.1))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.4 0.25) (end -0.4 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.3 0.25) (end -0.3 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)))
+    )
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 93 LED1))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 92 "Net-(D2-Pad2)"))
+    (model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module LED_SMD:LED_0402_1005Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5F6424E4)
+    (at 157.0736 36.6776 90)
+    (descr "LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
+    (tags LED)
+    (path /5F62178D/5F8C9584)
+    (attr smd)
+    (fp_text reference D1 (at -1.8796 0.0254 90) (layer F.SilkS)
+      (effects (font (size 0.5 0.5) (thickness 0.125)))
+    )
+    (fp_text value LED (at 0 1.17 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center -1.09 0) (end -1.04 0) (layer F.SilkS) (width 0.1))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.4 0.25) (end -0.4 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.3 0.25) (end -0.3 -0.25) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.25 0.25) (thickness 0.04)))
+    )
+    (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 91 LED0))
+    (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 90 "Net-(D1-Pad2)"))
+    (model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0402_1005Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_SO:SOIC-8_5.23x5.23mm_P1.27mm (layer B.Cu) (tedit 5D9F72B1) (tstamp 5F632082)
+    (at 158.369 74.8284 90)
+    (descr "SOIC, 8 Pin (http://www.winbond.com/resource-files/w25q32jv%20revg%2003272018%20plus.pdf#page=68), generated with kicad-footprint-generator ipc_gullwing_generator.py")
+    (tags "SOIC SO")
+    (path /5F609430/5F7F9366)
+    (attr smd)
+    (fp_text reference U2 (at 0 3.56 90) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value W25Q128JVS (at 0 -3.56 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 90) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start 4.65 2.86) (end -4.65 2.86) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 4.65 -2.86) (end 4.65 2.86) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -4.65 -2.86) (end 4.65 -2.86) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -4.65 2.86) (end -4.65 -2.86) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -2.615 1.615) (end -1.615 2.615) (layer B.Fab) (width 0.1))
+    (fp_line (start -2.615 -2.615) (end -2.615 1.615) (layer B.Fab) (width 0.1))
+    (fp_line (start 2.615 -2.615) (end -2.615 -2.615) (layer B.Fab) (width 0.1))
+    (fp_line (start 2.615 2.615) (end 2.615 -2.615) (layer B.Fab) (width 0.1))
+    (fp_line (start -1.615 2.615) (end 2.615 2.615) (layer B.Fab) (width 0.1))
+    (fp_line (start -2.725 2.465) (end -4.4 2.465) (layer B.SilkS) (width 0.12))
+    (fp_line (start -2.725 2.725) (end -2.725 2.465) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 2.725) (end -2.725 2.725) (layer B.SilkS) (width 0.12))
+    (fp_line (start 2.725 2.725) (end 2.725 2.465) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 2.725) (end 2.725 2.725) (layer B.SilkS) (width 0.12))
+    (fp_line (start -2.725 -2.725) (end -2.725 -2.465) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 -2.725) (end -2.725 -2.725) (layer B.SilkS) (width 0.12))
+    (fp_line (start 2.725 -2.725) (end 2.725 -2.465) (layer B.SilkS) (width 0.12))
+    (fp_line (start 0 -2.725) (end 2.725 -2.725) (layer B.SilkS) (width 0.12))
+    (pad 8 smd roundrect (at 3.6 1.905 90) (size 1.6 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 7 smd roundrect (at 3.6 0.635 90) (size 1.6 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 6 smd roundrect (at 3.6 -0.635 90) (size 1.6 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 86 SPI_CLK))
+    (pad 5 smd roundrect (at 3.6 -1.905 90) (size 1.6 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 88 SPI_DIN))
+    (pad 4 smd roundrect (at -3.6 -1.905 90) (size 1.6 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 GND))
+    (pad 3 smd roundrect (at -3.6 -0.635 90) (size 1.6 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 4 +3V3))
+    (pad 2 smd roundrect (at -3.6 0.635 90) (size 1.6 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 87 SPI_DOUT))
+    (pad 1 smd roundrect (at -3.6 1.905 90) (size 1.6 0.6) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 89 SPI_CS_n))
+    (model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-8_5.23x5.23mm_P1.27mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical (layer F.Cu) (tedit 5F68430F) (tstamp 5F630B27)
+    (at 124.0536 42.2402)
+    (descr "Through hole straight pin header, 1x06, 2.54mm pitch, single row")
+    (tags "Through hole pin header THT 1x06 2.54mm single row")
+    (path /5F609430/5F76EDA5)
+    (fp_text reference J1 (at -2.8194 0.127) (layer F.SilkS) hide
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value Conn_01x06_Female (at 0 15.03) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 6.35 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.8 14.5) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 14.5) (end 1.8 14.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 -1.8) (end -1.8 14.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.33 1.27) (end 1.33 14.03) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end -1.33 14.03) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 14.03) (end 1.33 14.03) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.27 13.97) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 13.97) (end -1.27 13.97) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 -1.27) (end 1.27 13.97) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
+    (pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 3 GND))
+    (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 82 "Net-(J1-Pad5)"))
+    (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 83 "Net-(J1-Pad4)"))
+    (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 84 "Net-(J1-Pad3)"))
+    (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 85 "Net-(J1-Pad2)"))
+    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 4 +3V3))
+    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x06_P2.54mm_Vertical.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (gr_line (start 112.8522 91.6432) (end 112.8522 34.544) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 168.9862 91.6432) (end 112.8522 91.6432) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 168.9862 34.544) (end 168.9862 91.6432) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 112.8522 34.544) (end 168.9862 34.544) (layer Edge.Cuts) (width 0.05))
+  (gr_text "MicroCore Labs - MCL86jr" (at 130.302 36.7792) (layer F.SilkS)
+    (effects (font (size 1.5 1.5) (thickness 0.3)))
+  )
+
+  (segment (start 159.9438 66.4228) (end 159.524 66.8426) (width 0.2) (layer F.Cu) (net 1))
+  (segment (start 160.1216 65.382) (end 159.9438 65.5598) (width 0.2) (layer F.Cu) (net 1))
+  (segment (start 159.9438 65.5598) (end 159.9438 66.4228) (width 0.2) (layer F.Cu) (net 1))
+  (segment (start 160.67449 56.86899) (end 160.6495 56.844) (width 0.25) (layer F.Cu) (net 2))
+  (segment (start 158.557999 58.167655) (end 158.557999 62.164999) (width 0.2) (layer F.Cu) (net 2))
+  (segment (start 160.6495 56.844) (end 159.881654 56.844) (width 0.2) (layer F.Cu) (net 2))
+  (segment (start 159.881654 56.844) (end 158.557999 58.167655) (width 0.2) (layer F.Cu) (net 2))
+  (segment (start 160.1216 63.720662) (end 158.571969 62.171031) (width 0.2) (layer F.Cu) (net 2))
+  (segment (start 160.1216 64.412) (end 160.1216 63.720662) (width 0.2) (layer F.Cu) (net 2))
+  (via (at 161.2138 65.5574) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 3))
+  (via (at 132.588 38.481) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 3))
+  (via (at 146.7866 40.1828) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 3))
+  (via (at 159.512 40.386) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 3))
+  (via (at 155.702 54.356) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 3))
+  (segment (start 156.741 54.356) (end 155.702 54.356) (width 0.25) (layer B.Cu) (net 3))
+  (segment (start 158.473 40.386) (end 159.512 40.386) (width 0.25) (layer B.Cu) (net 3))
+  (segment (start 146.7866 40.1828) (end 147.8256 40.1828) (width 0.25) (layer B.Cu) (net 3))
+  (segment (start 144.503 40.386) (end 145.415 40.386) (width 0.25) (layer B.Cu) (net 3))
+  (segment (start 145.415 40.386) (end 145.415 40.386) (width 0.25) (layer B.Cu) (net 3) (tstamp 5F686E49))
+  (via (at 145.415 40.386) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 3))
+  (segment (start 139.9842 65.9638) (end 140.2792 65.9638) (width 0.25) (layer B.Cu) (net 3))
+  (segment (start 139.9842 65.9638) (end 141.0462 65.9638) (width 0.25) (layer B.Cu) (net 3))
+  (segment (start 141.0462 65.9638) (end 141.0462 65.9638) (width 0.25) (layer B.Cu) (net 3) (tstamp 5F687DAD))
+  (via (at 141.0462 65.9638) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 3))
+  (segment (start 136.6266 56.0578) (end 136.6266 56.0578) (width 0.25) (layer B.Cu) (net 3) (tstamp 5F6883EE))
+  (segment (start 135.89 47.902) (end 135.89 46.863) (width 0.25) (layer B.Cu) (net 3))
+  (segment (start 135.89 46.863) (end 135.89 46.863) (width 0.25) (layer B.Cu) (net 3) (tstamp 5F6889E8))
+  (via (at 135.89 46.863) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 3))
+  (segment (start 142.979 53.848) (end 144.018 53.848) (width 0.25) (layer B.Cu) (net 3))
+  (segment (start 144.018 53.848) (end 144.018 53.848) (width 0.25) (layer B.Cu) (net 3) (tstamp 5F688AE8))
+  (via (at 144.018 53.848) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 3))
+  (segment (start 148.717 59.967) (end 148.717 58.674) (width 0.25) (layer B.Cu) (net 3))
+  (segment (start 148.717 58.674) (end 148.717 58.674) (width 0.25) (layer B.Cu) (net 3) (tstamp 5F688DE4))
+  (via (at 148.717 58.674) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 3))
+  (segment (start 149.225 46.967) (end 149.225 48.133) (width 0.25) (layer B.Cu) (net 3))
+  (segment (start 149.225 48.133) (end 149.225 48.133) (width 0.25) (layer B.Cu) (net 3) (tstamp 5F6890E4))
+  (via (at 149.225 48.133) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 3))
+  (segment (start 152.781 60.729) (end 152.781 59.436) (width 0.25) (layer B.Cu) (net 3))
+  (segment (start 152.781 59.436) (end 152.781 59.436) (width 0.25) (layer B.Cu) (net 3) (tstamp 5F68B78A))
+  (via (at 152.781 59.436) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 3))
+  (segment (start 138.407 78.105) (end 138.702 78.105) (width 0.25) (layer B.Cu) (net 3))
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+        (xy 159.405774 41.506502) (xy 159.366 41.706461) (xy 153.031154 41.706461) (xy 153.032216 41.703898) (xy 153.07199 41.503939)
+        (xy 153.07199 41.300061) (xy 153.032216 41.100102) (xy 152.954195 40.911744) (xy 152.840927 40.742226) (xy 152.696764 40.598063)
+        (xy 152.527246 40.484795) (xy 152.338888 40.406774) (xy 152.138929 40.367) (xy 151.935051 40.367) (xy 151.735092 40.406774)
+        (xy 151.546734 40.484795) (xy 151.391832 40.588297) (xy 151.243939 40.489478) (xy 151.055581 40.411457) (xy 150.855622 40.371683)
+        (xy 150.725306 40.371683) (xy 150.7426 40.284739) (xy 150.7426 40.284061) (xy 155.429 40.284061) (xy 155.429 40.487939)
+        (xy 155.468774 40.687898) (xy 155.546795 40.876256) (xy 155.660063 41.045774) (xy 155.804226 41.189937) (xy 155.973744 41.303205)
+        (xy 156.162102 41.381226) (xy 156.362061 41.421) (xy 156.565939 41.421) (xy 156.765898 41.381226) (xy 156.954256 41.303205)
+        (xy 157.123774 41.189937) (xy 157.267937 41.045774) (xy 157.381205 40.876256) (xy 157.459226 40.687898) (xy 157.499 40.487939)
+        (xy 157.499 40.284061) (xy 157.459226 40.084102) (xy 157.381205 39.895744) (xy 157.267937 39.726226) (xy 157.123774 39.582063)
+        (xy 156.954256 39.468795) (xy 156.765898 39.390774) (xy 156.565939 39.351) (xy 156.362061 39.351) (xy 156.162102 39.390774)
+        (xy 155.973744 39.468795) (xy 155.804226 39.582063) (xy 155.660063 39.726226) (xy 155.546795 39.895744) (xy 155.468774 40.084102)
+        (xy 155.429 40.284061) (xy 150.7426 40.284061) (xy 150.7426 40.080861) (xy 150.702826 39.880902) (xy 150.624805 39.692544)
+        (xy 150.511537 39.523026) (xy 150.367374 39.378863) (xy 150.197856 39.265595) (xy 150.009498 39.187574) (xy 149.809539 39.1478)
+        (xy 149.605661 39.1478) (xy 149.405702 39.187574) (xy 149.217344 39.265595) (xy 149.047826 39.378863) (xy 148.903663 39.523026)
+        (xy 148.790395 39.692544) (xy 148.712374 39.880902) (xy 148.6726 40.080861) (xy 148.6726 40.284739) (xy 148.688963 40.367)
+        (xy 148.615061 40.367) (xy 148.415102 40.406774) (xy 148.226744 40.484795) (xy 148.057226 40.598063) (xy 147.913063 40.742226)
+        (xy 147.799795 40.911744) (xy 147.721774 41.100102) (xy 147.682 41.300061) (xy 146.734592 41.300061) (xy 146.715026 41.2017)
+        (xy 146.637005 41.013342) (xy 146.523737 40.843824) (xy 146.379574 40.699661) (xy 146.210056 40.586393) (xy 146.021698 40.508372)
+        (xy 145.821739 40.468598) (xy 145.617861 40.468598) (xy 145.417902 40.508372) (xy 145.229544 40.586393) (xy 145.060026 40.699661)
+        (xy 144.915863 40.843824) (xy 144.802595 41.013342) (xy 144.724574 41.2017) (xy 144.6848 41.401659) (xy 142.693173 41.401659)
+        (xy 142.795898 41.381226) (xy 142.984256 41.303205) (xy 143.153774 41.189937) (xy 143.297937 41.045774) (xy 143.411205 40.876256)
+        (xy 143.489226 40.687898) (xy 143.529 40.487939) (xy 143.529 40.284061) (xy 143.489226 40.084102) (xy 143.411205 39.895744)
+        (xy 143.297937 39.726226) (xy 143.153774 39.582063) (xy 142.984256 39.468795) (xy 142.795898 39.390774) (xy 142.595939 39.351)
+        (xy 142.392061 39.351) (xy 142.192102 39.390774) (xy 142.003744 39.468795) (xy 141.834226 39.582063) (xy 141.690063 39.726226)
+        (xy 141.576795 39.895744) (xy 141.498774 40.084102) (xy 141.459 40.284061) (xy 139.048768 40.284061) (xy 139.084 40.106939)
+        (xy 139.084 39.903061) (xy 139.044226 39.703102) (xy 138.985158 39.5605) (xy 139.044226 39.417898) (xy 139.084 39.217939)
+        (xy 139.084 39.014061) (xy 139.044226 38.814102) (xy 138.966205 38.625744) (xy 138.852937 38.456226) (xy 138.708774 38.312063)
+        (xy 138.539256 38.198795) (xy 138.350898 38.120774) (xy 138.150939 38.081) (xy 137.947061 38.081) (xy 137.747102 38.120774)
+        (xy 137.558744 38.198795) (xy 137.389226 38.312063) (xy 137.245063 38.456226) (xy 137.131795 38.625744) (xy 137.053774 38.814102)
+        (xy 137.014 39.014061) (xy 113.5122 39.014061) (xy 113.5122 37.109061) (xy 147.936 37.109061) (xy 147.936 37.312939)
+        (xy 147.975774 37.512898) (xy 148.053795 37.701256) (xy 148.167063 37.870774) (xy 148.311226 38.014937) (xy 148.480744 38.128205)
+        (xy 148.669102 38.206226) (xy 148.869061 38.246) (xy 149.072939 38.246) (xy 149.272898 38.206226) (xy 149.461256 38.128205)
+        (xy 149.630774 38.014937) (xy 149.774937 37.870774) (xy 149.888205 37.701256) (xy 149.966226 37.512898) (xy 150.006 37.312939)
+        (xy 150.006 37.109061) (xy 149.966226 36.909102) (xy 149.888205 36.720744) (xy 149.774937 36.551226) (xy 149.630774 36.407063)
+        (xy 149.461256 36.293795) (xy 149.272898 36.215774) (xy 149.072939 36.176) (xy 148.869061 36.176) (xy 148.669102 36.215774)
+        (xy 148.480744 36.293795) (xy 148.311226 36.407063) (xy 148.167063 36.551226) (xy 148.053795 36.720744) (xy 147.975774 36.909102)
+        (xy 147.936 37.109061) (xy 113.5122 37.109061) (xy 113.5122 35.204) (xy 148.879987 35.204)
+      )
+    )
+  )
+)
diff --git a/MCL86jr/PCBA/MCL86jr.net b/MCL86jr/PCBA/MCL86jr.net
new file mode 100644
index 0000000..2accf17
--- /dev/null
+++ b/MCL86jr/PCBA/MCL86jr.net
@@ -0,0 +1,1460 @@
+(export (version D)
+  (design
+    (source Z:\Ted\projs\MCL86\MCL86jr\MCL86jr.sch)
+    (date "9/30/2020 9:51:38 PM")
+    (tool "Eeschema (5.1.5)-3")
+    (sheet (number 1) (name /) (tstamps /)
+      (title_block
+        (title)
+        (company)
+        (rev)
+        (date)
+        (source MCL86jr.sch)
+        (comment (number 1) (value ""))
+        (comment (number 2) (value ""))
+        (comment (number 3) (value ""))
+        (comment (number 4) (value ""))))
+    (sheet (number 2) (name /Page1/) (tstamps /5F609430/)
+      (title_block
+        (title)
+        (company)
+        (rev)
+        (date)
+        (source Page1.sch)
+        (comment (number 1) (value ""))
+        (comment (number 2) (value ""))
+        (comment (number 3) (value ""))
+        (comment (number 4) (value ""))))
+    (sheet (number 3) (name /Page3/) (tstamps /5F62178D/)
+      (title_block
+        (title)
+        (company)
+        (rev)
+        (date)
+        (source Page3sch.sch)
+        (comment (number 1) (value ""))
+        (comment (number 2) (value ""))
+        (comment (number 3) (value ""))
+        (comment (number 4) (value ""))))
+    (sheet (number 4) (name /Page4/) (tstamps /5F6217EE/)
+      (title_block
+        (title)
+        (company)
+        (rev)
+        (date)
+        (source Page4.sch)
+        (comment (number 1) (value ""))
+        (comment (number 2) (value ""))
+        (comment (number 3) (value ""))
+        (comment (number 4) (value "")))))
+  (components
+    (comp (ref U1)
+      (value XC6SLX9-TQG144)
+      (footprint Package_QFP:TQFP-144_20x20mm_P0.5mm)
+      (libsource (lib FPGA_Xilinx_Spartan6) (part XC6SLX9-TQG144) (description "Spartan 6 LX 9 XC6SLX9-TQG144"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5F6440A9))
+    (comp (ref Y1)
+      (value 100Mhz)
+      (footprint OSC_SIT8008BI-13-33E-33.333330E)
+      (datasheet "Manufacturer Recommendations")
+      (fields
+        (field (name Field4) 1.04)
+        (field (name Field5) 0.8mm)
+        (field (name Field6) SiTime))
+      (libsource (lib SIT8008BI-13-33E-33.333330E) (part SIT8008BI-13-33E-33.333330E) (description ""))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5F7DBEF0))
+    (comp (ref R1)
+      (value 33)
+      (footprint Resistor_SMD:R_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part R_US) (description "Resistor, US symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5F7DBF00))
+    (comp (ref U2)
+      (value W25Q128JVS)
+      (footprint Package_SO:SOIC-8_5.23x5.23mm_P1.27mm)
+      (datasheet http://www.winbond.com/resource-files/w25q128jv_dtr%20revc%2003272018%20plus.pdf)
+      (libsource (lib Memory_Flash) (part W25Q128JVS) (description "128Mb Serial Flash Memory, Standard/Dual/Quad SPI, SOIC-8"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5F7F9366))
+    (comp (ref C1)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5F92D2C4))
+    (comp (ref C3)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5F98F0C7))
+    (comp (ref C5)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5F999BF7))
+    (comp (ref C14)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5F99F57A))
+    (comp (ref C9)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5F9B5C56))
+    (comp (ref C10)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FA06BB4))
+    (comp (ref C8)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FA708B6))
+    (comp (ref C7)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FA7D5C4))
+    (comp (ref C6)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FA83EE0))
+    (comp (ref C4)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FA8ABC6))
+    (comp (ref C15)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FA9B5A8))
+    (comp (ref C13)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FA9B5B7))
+    (comp (ref C12)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FA9B5C7))
+    (comp (ref C11)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FA9B5D6))
+    (comp (ref C2)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FAAB60A))
+    (comp (ref R10)
+      (value 4.7k)
+      (footprint Resistor_SMD:R_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part R_US) (description "Resistor, US symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FB0A2A1))
+    (comp (ref R11)
+      (value 4.7k)
+      (footprint Resistor_SMD:R_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part R_US) (description "Resistor, US symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FB6A4AD))
+    (comp (ref R14)
+      (value 4.7k)
+      (footprint Resistor_SMD:R_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part R_US) (description "Resistor, US symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FBA7A81))
+    (comp (ref R12)
+      (value 4.7k)
+      (footprint Resistor_SMD:R_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part R_US) (description "Resistor, US symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FBB9847))
+    (comp (ref R13)
+      (value 4.7k)
+      (footprint Resistor_SMD:R_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part R_US) (description "Resistor, US symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FBD99FB))
+    (comp (ref R15)
+      (value 4.7k)
+      (footprint Resistor_SMD:R_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part R_US) (description "Resistor, US symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FD82F74))
+    (comp (ref R16)
+      (value 33)
+      (footprint Resistor_SMD:R_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part R_US) (description "Resistor, US symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FDFB8A4))
+    (comp (ref C25)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FF14247))
+    (comp (ref C26)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FF1DF62))
+    (comp (ref C27)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5FF27C34))
+    (comp (ref J1)
+      (value Conn_01x06_Female)
+      (footprint Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical)
+      (datasheet ~)
+      (libsource (lib Connector) (part Conn_01x06_Female) (description "Generic connector, single row, 01x06, script generated (kicad-library-utils/schlib/autogen/connector/)"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5F76EDA5))
+    (comp (ref C28)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 60E87B06))
+    (comp (ref C30)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 60EB6252))
+    (comp (ref C29)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 60ECB869))
+    (comp (ref C31)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page1/) (tstamps /5F609430/))
+      (tstamp 5F7CE133))
+    (comp (ref U3)
+      (value MIC5504-3.3YM5-TR)
+      (footprint SOT23-5P95_280X145XL45X37N)
+      (datasheet MICREL)
+      (libsource (lib MIC5504-1.2YM5-TR) (part MIC5504-1.2YM5-TR) (description ""))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F8012DE))
+    (comp (ref U7)
+      (value MIC5504-1.2YM5-TR)
+      (footprint SOT23-5P95_280X145XL45X37N)
+      (datasheet MICREL)
+      (libsource (lib MIC5504-1.2YM5-TR) (part MIC5504-1.2YM5-TR) (description ""))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F8012E4))
+    (comp (ref D1)
+      (value LED)
+      (footprint LED_SMD:LED_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part LED) (description "Light emitting diode"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F8C9584))
+    (comp (ref R2)
+      (value 330)
+      (footprint Resistor_SMD:R_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part R_US) (description "Resistor, US symbol"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F8CD1C0))
+    (comp (ref D2)
+      (value LED)
+      (footprint LED_SMD:LED_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part LED) (description "Light emitting diode"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F8DC90D))
+    (comp (ref D3)
+      (value LED)
+      (footprint LED_SMD:LED_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part LED) (description "Light emitting diode"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F8DEB5D))
+    (comp (ref D4)
+      (value LED)
+      (footprint LED_SMD:LED_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part LED) (description "Light emitting diode"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F8DEB6E))
+    (comp (ref D5)
+      (value LED)
+      (footprint LED_SMD:LED_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part LED) (description "Light emitting diode"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F8E337A))
+    (comp (ref D6)
+      (value LED)
+      (footprint LED_SMD:LED_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part LED) (description "Light emitting diode"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F8E338B))
+    (comp (ref D7)
+      (value LED)
+      (footprint LED_SMD:LED_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part LED) (description "Light emitting diode"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F8E339C))
+    (comp (ref D8)
+      (value LED)
+      (footprint LED_SMD:LED_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part LED) (description "Light emitting diode"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F8E33AD))
+    (comp (ref R3)
+      (value 330)
+      (footprint Resistor_SMD:R_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part R_US) (description "Resistor, US symbol"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F9031C9))
+    (comp (ref R4)
+      (value 330)
+      (footprint Resistor_SMD:R_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part R_US) (description "Resistor, US symbol"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F905C0D))
+    (comp (ref R5)
+      (value 330)
+      (footprint Resistor_SMD:R_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part R_US) (description "Resistor, US symbol"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F905C13))
+    (comp (ref R6)
+      (value 330)
+      (footprint Resistor_SMD:R_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part R_US) (description "Resistor, US symbol"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F908B41))
+    (comp (ref R7)
+      (value 330)
+      (footprint Resistor_SMD:R_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part R_US) (description "Resistor, US symbol"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F908B47))
+    (comp (ref R8)
+      (value 330)
+      (footprint Resistor_SMD:R_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part R_US) (description "Resistor, US symbol"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F908B4D))
+    (comp (ref R9)
+      (value 330)
+      (footprint Resistor_SMD:R_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part R_US) (description "Resistor, US symbol"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F908B53))
+    (comp (ref C20)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5FA14AF8))
+    (comp (ref C21)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5FA17919))
+    (comp (ref C17)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5FAF0B3F))
+    (comp (ref C19)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5FAF607D))
+    (comp (ref C18)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5FADFFF0))
+    (comp (ref C16)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5FADABE7))
+    (comp (ref U8)
+      (value CY62148GN-45ZSXI)
+      (footprint SOIC127P1176X120-32N)
+      (datasheet "Cypress Semiconductor")
+      (fields
+        (field (name Field4) SOIC127P1176X120-32N))
+      (libsource (lib CY62148GN-45ZSXI) (part CY62148GN-45ZSXI) (description ""))
+      (sheetpath (names /Page3/) (tstamps /5F62178D/))
+      (tstamp 5F64044A))
+    (comp (ref U4)
+      (value SN74LVC245APW)
+      (footprint SOP65P640X120-20N)
+      (libsource (lib SN74LVC245APW) (part SN74LVC245APW) (description ""))
+      (sheetpath (names /Page4/) (tstamps /5F6217EE/))
+      (tstamp 5F622E6C))
+    (comp (ref U5)
+      (value SN74LVC245APW)
+      (footprint SOP65P640X120-20N)
+      (libsource (lib SN74LVC245APW) (part SN74LVC245APW) (description ""))
+      (sheetpath (names /Page4/) (tstamps /5F6217EE/))
+      (tstamp 5F6230CD))
+    (comp (ref U6)
+      (value SN74LVC245APW)
+      (footprint SOP65P640X120-20N)
+      (libsource (lib SN74LVC245APW) (part SN74LVC245APW) (description ""))
+      (sheetpath (names /Page4/) (tstamps /5F6217EE/))
+      (tstamp 5F623800))
+    (comp (ref U9)
+      (value 8088_Min_Mode)
+      (footprint Package_DIP:DIP-40_W15.24mm)
+      (datasheet http://datasheets.chipdb.org/Intel/x86/808x/datashts/8088/231456-006.pdf)
+      (libsource (lib MCU_Intel) (part 8088_Min_Mode) (description "8088 (minimum mode), 8-Bit HMOS Microprocessor, PDIP-40"))
+      (sheetpath (names /Page4/) (tstamps /5F6217EE/))
+      (tstamp 5F7A8941))
+    (comp (ref C23)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page4/) (tstamps /5F6217EE/))
+      (tstamp 5FA1A7AD))
+    (comp (ref C24)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page4/) (tstamps /5F6217EE/))
+      (tstamp 5FA1EA71))
+    (comp (ref C22)
+      (value 4.7uF)
+      (footprint Capacitor_SMD:C_0402_1005Metric)
+      (datasheet ~)
+      (libsource (lib Device) (part C_Small) (description "Unpolarized capacitor, small symbol"))
+      (sheetpath (names /Page4/) (tstamps /5F6217EE/))
+      (tstamp 5FA22BDC)))
+  (libparts
+    (libpart (lib CY62148GN-45ZSXI) (part CY62148GN-45ZSXI)
+      (fields
+        (field (name Reference) U)
+        (field (name Value) CY62148GN-45ZSXI)
+        (field (name Footprint) SOIC127P1176X120-32N)
+        (field (name Datasheet) "Cypress Semiconductor")
+        (field (name Field4) SOIC127P1176X120-32N))
+      (pins
+        (pin (num 1) (name A17) (type BiDi))
+        (pin (num 2) (name A16) (type BiDi))
+        (pin (num 3) (name A14) (type BiDi))
+        (pin (num 4) (name A12) (type BiDi))
+        (pin (num 5) (name A7) (type BiDi))
+        (pin (num 6) (name A6) (type BiDi))
+        (pin (num 7) (name A5) (type BiDi))
+        (pin (num 8) (name A4) (type BiDi))
+        (pin (num 9) (name A3) (type BiDi))
+        (pin (num 10) (name A2) (type BiDi))
+        (pin (num 11) (name A1) (type BiDi))
+        (pin (num 12) (name A0) (type BiDi))
+        (pin (num 13) (name D0) (type BiDi))
+        (pin (num 14) (name D1) (type BiDi))
+        (pin (num 15) (name D2) (type BiDi))
+        (pin (num 16) (name GND) (type power_in))
+        (pin (num 17) (name D3) (type BiDi))
+        (pin (num 18) (name D4) (type BiDi))
+        (pin (num 19) (name D5) (type BiDi))
+        (pin (num 20) (name D6) (type BiDi))
+        (pin (num 21) (name D7) (type BiDi))
+        (pin (num 22) (name CE_N) (type BiDi))
+        (pin (num 23) (name A10) (type BiDi))
+        (pin (num 24) (name OE_N) (type BiDi))
+        (pin (num 25) (name A11) (type BiDi))
+        (pin (num 26) (name A9) (type BiDi))
+        (pin (num 27) (name A8) (type BiDi))
+        (pin (num 28) (name A13) (type BiDi))
+        (pin (num 29) (name WE_N) (type BiDi))
+        (pin (num 30) (name A18) (type BiDi))
+        (pin (num 31) (name A15) (type BiDi))
+        (pin (num 32) (name VCC) (type power_in))))
+    (libpart (lib Connector) (part Conn_01x06_Female)
+      (description "Generic connector, single row, 01x06, script generated (kicad-library-utils/schlib/autogen/connector/)")
+      (docs ~)
+      (footprints
+        (fp Connector*:*_1x??_*))
+      (fields
+        (field (name Reference) J)
+        (field (name Value) Conn_01x06_Female))
+      (pins
+        (pin (num 1) (name Pin_1) (type passive))
+        (pin (num 2) (name Pin_2) (type passive))
+        (pin (num 3) (name Pin_3) (type passive))
+        (pin (num 4) (name Pin_4) (type passive))
+        (pin (num 5) (name Pin_5) (type passive))
+        (pin (num 6) (name Pin_6) (type passive))))
+    (libpart (lib Device) (part C_Small)
+      (description "Unpolarized capacitor, small symbol")
+      (docs ~)
+      (footprints
+        (fp C_*))
+      (fields
+        (field (name Reference) C)
+        (field (name Value) C_Small))
+      (pins
+        (pin (num 1) (name ~) (type passive))
+        (pin (num 2) (name ~) (type passive))))
+    (libpart (lib Device) (part LED)
+      (description "Light emitting diode")
+      (docs ~)
+      (footprints
+        (fp LED*)
+        (fp LED_SMD:*)
+        (fp LED_THT:*))
+      (fields
+        (field (name Reference) D)
+        (field (name Value) LED))
+      (pins
+        (pin (num 1) (name K) (type passive))
+        (pin (num 2) (name A) (type passive))))
+    (libpart (lib Device) (part R_US)
+      (description "Resistor, US symbol")
+      (docs ~)
+      (footprints
+        (fp R_*))
+      (fields
+        (field (name Reference) R)
+        (field (name Value) R_US))
+      (pins
+        (pin (num 1) (name ~) (type passive))
+        (pin (num 2) (name ~) (type passive))))
+    (libpart (lib FPGA_Xilinx_Spartan6) (part XC6SLX9-TQG144)
+      (description "Spartan 6 LX 9 XC6SLX9-TQG144")
+      (fields
+        (field (name Reference) U)
+        (field (name Value) XC6SLX9-TQG144))
+      (pins
+        (pin (num 1) (name IO_L83N_VREF_3) (type BiDi))
+        (pin (num 2) (name IO_L83P_3) (type BiDi))
+        (pin (num 3) (name GND) (type power_in))
+        (pin (num 4) (name VCCO_3) (type power_in))
+        (pin (num 5) (name IO_L52N_3) (type BiDi))
+        (pin (num 6) (name IO_L52P_3) (type BiDi))
+        (pin (num 7) (name IO_L51N_3) (type BiDi))
+        (pin (num 8) (name IO_L51P_3) (type BiDi))
+        (pin (num 9) (name IO_L50N_3) (type BiDi))
+        (pin (num 10) (name IO_L50P_3) (type BiDi))
+        (pin (num 11) (name IO_L49N_3) (type BiDi))
+        (pin (num 12) (name IO_L49P_3) (type BiDi))
+        (pin (num 13) (name GND) (type power_in))
+        (pin (num 14) (name IO_L44N_GCLK20_3) (type BiDi))
+        (pin (num 15) (name IO_L44P_GCLK21_3) (type BiDi))
+        (pin (num 16) (name IO_L43N_GCLK22_IRDY2_3) (type BiDi))
+        (pin (num 17) (name IO_L43P_GCLK23_3) (type BiDi))
+        (pin (num 18) (name VCCO_3) (type power_in))
+        (pin (num 19) (name VCCINT) (type power_in))
+        (pin (num 20) (name VCCAUX) (type power_in))
+        (pin (num 21) (name IO_L42N_GCLK24_3) (type BiDi))
+        (pin (num 22) (name IO_L42P_GCLK25_TRDY2_3) (type BiDi))
+        (pin (num 23) (name IO_L41N_GCLK26_3) (type BiDi))
+        (pin (num 24) (name IO_L41P_GCLK27_3) (type BiDi))
+        (pin (num 25) (name GND) (type power_in))
+        (pin (num 26) (name IO_L37N_3) (type BiDi))
+        (pin (num 27) (name IO_L37P_3) (type BiDi))
+        (pin (num 28) (name VCCINT) (type power_in))
+        (pin (num 29) (name IO_L36N_3) (type BiDi))
+        (pin (num 30) (name IO_L36P_3) (type BiDi))
+        (pin (num 31) (name VCCO_3) (type power_in))
+        (pin (num 32) (name IO_L2N_3) (type BiDi))
+        (pin (num 33) (name IO_L2P_3) (type BiDi))
+        (pin (num 34) (name IO_L1N_VREF_3) (type BiDi))
+        (pin (num 35) (name IO_L1P_3) (type BiDi))
+        (pin (num 36) (name VCCAUX) (type power_in))
+        (pin (num 37) (name PROGRAM_B_2) (type BiDi))
+        (pin (num 38) (name IO_L65N_CSO_B_2) (type BiDi))
+        (pin (num 39) (name IO_L65P_INIT_B_2) (type BiDi))
+        (pin (num 40) (name IO_L64N_D9_2) (type BiDi))
+        (pin (num 41) (name IO_L64P_D8_2) (type BiDi))
+        (pin (num 42) (name VCCO_2) (type power_in))
+        (pin (num 43) (name IO_L62N_D6_2) (type BiDi))
+        (pin (num 44) (name IO_L62P_D5_2) (type BiDi))
+        (pin (num 45) (name IO_L49N_D4_2) (type BiDi))
+        (pin (num 46) (name IO_L49P_D3_2) (type BiDi))
+        (pin (num 47) (name IO_L48N_RDWR_B_VREF_2) (type BiDi))
+        (pin (num 48) (name IO_L48P_D7_2) (type BiDi))
+        (pin (num 49) (name GND) (type power_in))
+        (pin (num 50) (name IO_L31N_GCLK30_D15_2) (type BiDi))
+        (pin (num 51) (name IO_L31P_GCLK31_D14_2) (type BiDi))
+        (pin (num 52) (name VCCINT) (type power_in))
+        (pin (num 53) (name VCCAUX) (type power_in))
+        (pin (num 54) (name GND) (type power_in))
+        (pin (num 55) (name IO_L30N_GCLK0_USERCCLK_2) (type BiDi))
+        (pin (num 56) (name IO_L30P_GCLK1_D13_2) (type BiDi))
+        (pin (num 57) (name IO_L14N_D12_2) (type BiDi))
+        (pin (num 58) (name IO_L14P_D11_2) (type BiDi))
+        (pin (num 59) (name IO_L13N_D10_2) (type BiDi))
+        (pin (num 60) (name IO_L13P_M1_2) (type BiDi))
+        (pin (num 61) (name IO_L12N_D2_MISO3_2) (type BiDi))
+        (pin (num 62) (name IO_L12P_D1_MISO2_2) (type BiDi))
+        (pin (num 63) (name VCCO_2) (type power_in))
+        (pin (num 64) (name IO_L3N_MOSI_CSI_B_MISO0_2) (type BiDi))
+        (pin (num 65) (name IO_L3P_D0_DIN_MISO_MISO1_2) (type BiDi))
+        (pin (num 66) (name IO_L2N_CMPMOSI_2) (type BiDi))
+        (pin (num 67) (name IO_L2P_CMPCLK_2) (type BiDi))
+        (pin (num 68) (name GND) (type power_in))
+        (pin (num 69) (name IO_L1N_M0_CMPMISO_2) (type BiDi))
+        (pin (num 70) (name IO_L1P_CCLK_2) (type BiDi))
+        (pin (num 71) (name DONE_2) (type BiDi))
+        (pin (num 72) (name CMPCS_B_2) (type BiDi))
+        (pin (num 73) (name SUSPEND) (type BiDi))
+        (pin (num 74) (name IO_L74N_DOUT_BUSY_1) (type BiDi))
+        (pin (num 75) (name IO_L74P_AWAKE_1) (type BiDi))
+        (pin (num 76) (name VCCO_1) (type power_in))
+        (pin (num 77) (name GND) (type power_in))
+        (pin (num 78) (name IO_L47N_1) (type BiDi))
+        (pin (num 79) (name IO_L47P_1) (type BiDi))
+        (pin (num 80) (name IO_L46N_1) (type BiDi))
+        (pin (num 81) (name IO_L46P_1) (type BiDi))
+        (pin (num 82) (name IO_L45N_1) (type BiDi))
+        (pin (num 83) (name IO_L45P_1) (type BiDi))
+        (pin (num 84) (name IO_L43N_GCLK4_1) (type BiDi))
+        (pin (num 85) (name IO_L43P_GCLK5_1) (type BiDi))
+        (pin (num 86) (name VCCO_1) (type power_in))
+        (pin (num 87) (name IO_L42N_GCLK6_TRDY1_1) (type BiDi))
+        (pin (num 88) (name IO_L42P_GCLK7_1) (type BiDi))
+        (pin (num 89) (name VCCINT) (type power_in))
+        (pin (num 90) (name VCCAUX) (type power_in))
+        (pin (num 91) (name GND) (type power_in))
+        (pin (num 92) (name IO_L41N_GCLK8_1) (type BiDi))
+        (pin (num 93) (name IO_L41P_GCLK9_IRDY1_1) (type BiDi))
+        (pin (num 94) (name IO_L40N_GCLK10_1) (type BiDi))
+        (pin (num 95) (name IO_L40P_GCLK11_1) (type BiDi))
+        (pin (num 96) (name GND) (type power_in))
+        (pin (num 97) (name IO_L34N_1) (type BiDi))
+        (pin (num 98) (name IO_L34P_1) (type BiDi))
+        (pin (num 99) (name IO_L33N_1) (type BiDi))
+        (pin (num 100) (name IO_L33P_1) (type BiDi))
+        (pin (num 101) (name IO_L32N_1) (type BiDi))
+        (pin (num 102) (name IO_L32P_1) (type BiDi))
+        (pin (num 103) (name VCCO_1) (type power_in))
+        (pin (num 104) (name IO_L1N_VREF_1) (type BiDi))
+        (pin (num 105) (name IO_L1P_1) (type BiDi))
+        (pin (num 106) (name TDO) (type BiDi))
+        (pin (num 107) (name TMS) (type BiDi))
+        (pin (num 108) (name GND) (type power_in))
+        (pin (num 109) (name TCK) (type BiDi))
+        (pin (num 110) (name TDI) (type BiDi))
+        (pin (num 111) (name IO_L66N_SCP0_0) (type BiDi))
+        (pin (num 112) (name IO_L66P_SCP1_0) (type BiDi))
+        (pin (num 113) (name GND) (type power_in))
+        (pin (num 114) (name IO_L65N_SCP2_0) (type BiDi))
+        (pin (num 115) (name IO_L65P_SCP3_0) (type BiDi))
+        (pin (num 116) (name IO_L64N_SCP4_0) (type BiDi))
+        (pin (num 117) (name IO_L64P_SCP5_0) (type BiDi))
+        (pin (num 118) (name IO_L63N_SCP6_0) (type BiDi))
+        (pin (num 119) (name IO_L63P_SCP7_0) (type BiDi))
+        (pin (num 120) (name IO_L62N_VREF_0) (type BiDi))
+        (pin (num 121) (name IO_L62P_0) (type BiDi))
+        (pin (num 122) (name VCCO_0) (type power_in))
+        (pin (num 123) (name IO_L37N_GCLK12_0) (type BiDi))
+        (pin (num 124) (name IO_L37P_GCLK13_0) (type BiDi))
+        (pin (num 125) (name VCCO_0) (type power_in))
+        (pin (num 126) (name IO_L36N_GCLK14_0) (type BiDi))
+        (pin (num 127) (name IO_L36P_GCLK15_0) (type BiDi))
+        (pin (num 128) (name VCCINT) (type power_in))
+        (pin (num 129) (name VCCAUX) (type power_in))
+        (pin (num 130) (name GND) (type power_in))
+        (pin (num 131) (name IO_L35N_GCLK16_0) (type BiDi))
+        (pin (num 132) (name IO_L35P_GCLK17_0) (type BiDi))
+        (pin (num 133) (name IO_L34N_GCLK18_0) (type BiDi))
+        (pin (num 134) (name IO_L34P_GCLK19_0) (type BiDi))
+        (pin (num 135) (name VCCO_0) (type power_in))
+        (pin (num 136) (name GND) (type power_in))
+        (pin (num 137) (name IO_L4N_0) (type BiDi))
+        (pin (num 138) (name IO_L4P_0) (type BiDi))
+        (pin (num 139) (name IO_L3N_0) (type BiDi))
+        (pin (num 140) (name IO_L3P_0) (type BiDi))
+        (pin (num 141) (name IO_L2N_0) (type BiDi))
+        (pin (num 142) (name IO_L2P_0) (type BiDi))
+        (pin (num 143) (name IO_L1N_VREF_0) (type BiDi))
+        (pin (num 144) (name IO_L1P_HSWAPEN_0) (type BiDi))))
+    (libpart (lib MCU_Intel) (part 8088)
+      (aliases
+        (alias 8088_Min_Mode))
+      (description "8088 (minimum mode), 8-Bit HMOS Microprocessor, PDIP-40")
+      (docs http://datasheets.chipdb.org/Intel/x86/808x/datashts/8088/231456-006.pdf)
+      (footprints
+        (fp DIP*W15.24mm*))
+      (fields
+        (field (name Reference) U)
+        (field (name Value) 8088)
+        (field (name Footprint) Package_DIP:DIP-40_W15.24mm))
+      (pins
+        (pin (num 1) (name GND) (type power_in))
+        (pin (num 2) (name A14) (type output))
+        (pin (num 3) (name A13) (type output))
+        (pin (num 4) (name A12) (type output))
+        (pin (num 5) (name A11) (type output))
+        (pin (num 6) (name A10) (type output))
+        (pin (num 7) (name A9) (type output))
+        (pin (num 8) (name A8) (type output))
+        (pin (num 9) (name AD7) (type BiDi))
+        (pin (num 10) (name AD6) (type BiDi))
+        (pin (num 11) (name AD5) (type BiDi))
+        (pin (num 12) (name AD4) (type BiDi))
+        (pin (num 13) (name AD3) (type BiDi))
+        (pin (num 14) (name AD2) (type BiDi))
+        (pin (num 15) (name AD1) (type BiDi))
+        (pin (num 16) (name AD0) (type BiDi))
+        (pin (num 17) (name NMI) (type input))
+        (pin (num 18) (name INTR) (type input))
+        (pin (num 19) (name CLK) (type input))
+        (pin (num 20) (name GND) (type power_in))
+        (pin (num 21) (name RESET) (type input))
+        (pin (num 22) (name READY) (type input))
+        (pin (num 23) (name ~TEST~) (type input))
+        (pin (num 24) (name ~INTA~) (type output))
+        (pin (num 25) (name ALE) (type output))
+        (pin (num 26) (name DEN) (type output))
+        (pin (num 27) (name DT/~R~) (type output))
+        (pin (num 28) (name IO/~M~) (type output))
+        (pin (num 29) (name WR) (type output))
+        (pin (num 30) (name HLDA) (type output))
+        (pin (num 31) (name HOLD) (type input))
+        (pin (num 32) (name ~RD~) (type output))
+        (pin (num 33) (name MN/~MX~) (type input))
+        (pin (num 34) (name ~SSO~) (type output))
+        (pin (num 35) (name A19/S6) (type output))
+        (pin (num 36) (name A18/S5) (type output))
+        (pin (num 37) (name A17/S4) (type output))
+        (pin (num 38) (name A16/S3) (type output))
+        (pin (num 39) (name A15) (type output))
+        (pin (num 40) (name VCC) (type power_in))))
+    (libpart (lib MIC5504-1.2YM5-TR) (part MIC5504-1.2YM5-TR)
+      (fields
+        (field (name Reference) U)
+        (field (name Value) MIC5504-1.2YM5-TR)
+        (field (name Footprint) SOT23-5P95_280X145XL45X37N)
+        (field (name Datasheet) MICREL))
+      (pins
+        (pin (num 1) (name VIN) (type power_in))
+        (pin (num 2) (name GND) (type power_in))
+        (pin (num 3) (name EN) (type input))
+        (pin (num 5) (name VOUT) (type output))))
+    (libpart (lib Memory_Flash) (part W25Q32JVSS)
+      (aliases
+        (alias W25Q128JVS))
+      (description "32Mb Serial Flash Memory, Standard/Dual/Quad SPI, SOIC-8")
+      (docs http://www.winbond.com/resource-files/w25q32jv%20revg%2003272018%20plus.pdf)
+      (footprints
+        (fp SOIC*5.23x5.23mm*P1.27mm*))
+      (fields
+        (field (name Reference) U)
+        (field (name Value) W25Q32JVSS)
+        (field (name Footprint) Package_SO:SOIC-8_5.23x5.23mm_P1.27mm))
+      (pins
+        (pin (num 1) (name ~CS) (type input))
+        (pin (num 2) (name "DO(IO1)") (type BiDi))
+        (pin (num 3) (name IO2) (type BiDi))
+        (pin (num 4) (name GND) (type power_in))
+        (pin (num 5) (name "DI(IO0)") (type BiDi))
+        (pin (num 6) (name CLK) (type input))
+        (pin (num 7) (name IO3) (type BiDi))
+        (pin (num 8) (name VCC) (type power_in))))
+    (libpart (lib SIT8008BI-13-33E-33.333330E) (part SIT8008BI-13-33E-33.333330E)
+      (fields
+        (field (name Reference) Y)
+        (field (name Value) SIT8008BI-13-33E-33.333330E)
+        (field (name Footprint) OSC_SIT8008BI-13-33E-33.333330E)
+        (field (name Datasheet) "Manufacturer Recommendations")
+        (field (name Field4) 1.04)
+        (field (name Field5) 0.8mm)
+        (field (name Field6) SiTime))
+      (pins
+        (pin (num 1) (name OE) (type input))
+        (pin (num 2) (name GND) (type power_in))
+        (pin (num 3) (name OUT) (type output))
+        (pin (num 4) (name VDD) (type power_in))))
+    (libpart (lib SN74LVC245APW) (part SN74LVC245APW)
+      (fields
+        (field (name Reference) U)
+        (field (name Value) SN74LVC245APW)
+        (field (name Footprint) SOP65P640X120-20N))
+      (pins
+        (pin (num 1) (name DIR) (type input))
+        (pin (num 2) (name A1) (type BiDi))
+        (pin (num 3) (name A2) (type BiDi))
+        (pin (num 4) (name A3) (type BiDi))
+        (pin (num 5) (name A4) (type BiDi))
+        (pin (num 6) (name A5) (type BiDi))
+        (pin (num 7) (name A6) (type BiDi))
+        (pin (num 8) (name A7) (type BiDi))
+        (pin (num 9) (name A8) (type BiDi))
+        (pin (num 10) (name GND) (type power_in))
+        (pin (num 11) (name B8) (type BiDi))
+        (pin (num 12) (name B7) (type BiDi))
+        (pin (num 13) (name B6) (type BiDi))
+        (pin (num 14) (name B5) (type BiDi))
+        (pin (num 15) (name B4) (type BiDi))
+        (pin (num 16) (name B3) (type BiDi))
+        (pin (num 17) (name B2) (type BiDi))
+        (pin (num 18) (name B1) (type BiDi))
+        (pin (num 19) (name ~OE~) (type input))
+        (pin (num 20) (name VCC) (type power_in)))))
+  (libraries
+    (library (logical CY62148GN-45ZSXI)
+      (uri Z:/Ted/projs/KiCAD_Library/CY62148GN-45ZSXI/CY62148GN-45ZSXI.lib))
+    (library (logical Connector)
+      (uri "C:\\Program Files\\KiCad\\share\\kicad\\library/Connector.lib"))
+    (library (logical Device)
+      (uri "C:\\Program Files\\KiCad\\share\\kicad\\library/Device.lib"))
+    (library (logical FPGA_Xilinx_Spartan6)
+      (uri Z:/Ted/projs/KiCAD_Library/Xilinx_6_Series/FPGA_Xilinx_Spartan6.lib))
+    (library (logical MCU_Intel)
+      (uri "C:\\Program Files\\KiCad\\share\\kicad\\library/MCU_Intel.lib"))
+    (library (logical MIC5504-1.2YM5-TR)
+      (uri Z:/Ted/projs/KiCAD_Library/MIC5504-1.2YM5-TR/MIC5504-1.2YM5-TR.lib))
+    (library (logical Memory_Flash)
+      (uri "C:\\Program Files\\KiCad\\share\\kicad\\library/Memory_Flash.lib"))
+    (library (logical SIT8008BI-13-33E-33.333330E)
+      (uri Z:/Ted/projs/KiCAD_Library/SIT8008BI-13-33E-33.333330E/SIT8008BI-13-33E-33.333330E.lib))
+    (library (logical SN74LVC245APW)
+      (uri Z:/Ted/projs/KiCAD_Library/SN74LVC245APW/SN74LVC245APW.lib)))
+  (nets
+    (net (code 1) (name +3V3)
+      (node (ref U2) (pin 8))
+      (node (ref U2) (pin 7))
+      (node (ref U2) (pin 3))
+      (node (ref U1) (pin 63))
+      (node (ref U1) (pin 42))
+      (node (ref U1) (pin 31))
+      (node (ref U1) (pin 18))
+      (node (ref U1) (pin 4))
+      (node (ref C24) (pin 1))
+      (node (ref U1) (pin 144))
+      (node (ref U1) (pin 135))
+      (node (ref C3) (pin 1))
+      (node (ref C5) (pin 1))
+      (node (ref C1) (pin 1))
+      (node (ref U1) (pin 122))
+      (node (ref C10) (pin 1))
+      (node (ref C9) (pin 1))
+      (node (ref C14) (pin 1))
+      (node (ref C22) (pin 1))
+      (node (ref U1) (pin 125))
+      (node (ref U6) (pin 20))
+      (node (ref U4) (pin 20))
+      (node (ref U4) (pin 1))
+      (node (ref U5) (pin 20))
+      (node (ref C30) (pin 1))
+      (node (ref C29) (pin 1))
+      (node (ref C23) (pin 1))
+      (node (ref U1) (pin 103))
+      (node (ref U1) (pin 86))
+      (node (ref U1) (pin 76))
+      (node (ref C18) (pin 1))
+      (node (ref U8) (pin 32))
+      (node (ref R4) (pin 2))
+      (node (ref R3) (pin 2))
+      (node (ref C21) (pin 1))
+      (node (ref U7) (pin 1))
+      (node (ref R2) (pin 2))
+      (node (ref U3) (pin 5))
+      (node (ref U7) (pin 3))
+      (node (ref U1) (pin 90))
+      (node (ref C17) (pin 1))
+      (node (ref R5) (pin 2))
+      (node (ref R6) (pin 2))
+      (node (ref R7) (pin 2))
+      (node (ref R8) (pin 2))
+      (node (ref R9) (pin 2))
+      (node (ref C20) (pin 1))
+      (node (ref U1) (pin 129))
+      (node (ref U1) (pin 53))
+      (node (ref U1) (pin 36))
+      (node (ref U1) (pin 20))
+      (node (ref Y1) (pin 1))
+      (node (ref Y1) (pin 4))
+      (node (ref C7) (pin 1))
+      (node (ref R13) (pin 1))
+      (node (ref C25) (pin 1))
+      (node (ref R10) (pin 1))
+      (node (ref C8) (pin 1))
+      (node (ref C6) (pin 1))
+      (node (ref R12) (pin 1))
+      (node (ref R14) (pin 1))
+      (node (ref C4) (pin 1))
+      (node (ref C27) (pin 1))
+      (node (ref J1) (pin 1))
+      (node (ref R15) (pin 1))
+      (node (ref C26) (pin 1))
+      (node (ref C2) (pin 1)))
+    (net (code 2) (name SPI_CLK)
+      (node (ref U2) (pin 6))
+      (node (ref R16) (pin 2)))
+    (net (code 3) (name SPI_DOUT)
+      (node (ref U2) (pin 2))
+      (node (ref U1) (pin 65)))
+    (net (code 4) (name FPGA_INIT)
+      (node (ref U1) (pin 39))
+      (node (ref R14) (pin 2)))
+    (net (code 5) (name FPGA_DONE)
+      (node (ref U1) (pin 71))
+      (node (ref R12) (pin 2)))
+    (net (code 6) (name FPGA_PROGRAM_n)
+      (node (ref R13) (pin 2))
+      (node (ref U1) (pin 37)))
+    (net (code 7) (name GND)
+      (node (ref U1) (pin 91))
+      (node (ref C12) (pin 2))
+      (node (ref C27) (pin 2))
+      (node (ref C11) (pin 2))
+      (node (ref R11) (pin 1))
+      (node (ref C23) (pin 2))
+      (node (ref Y1) (pin 2))
+      (node (ref C26) (pin 2))
+      (node (ref C2) (pin 2))
+      (node (ref U1) (pin 96))
+      (node (ref U1) (pin 108))
+      (node (ref U1) (pin 113))
+      (node (ref U1) (pin 130))
+      (node (ref U1) (pin 136))
+      (node (ref C24) (pin 2))
+      (node (ref C6) (pin 2))
+      (node (ref C10) (pin 2))
+      (node (ref C9) (pin 2))
+      (node (ref C14) (pin 2))
+      (node (ref C3) (pin 2))
+      (node (ref C5) (pin 2))
+      (node (ref C8) (pin 2))
+      (node (ref C1) (pin 2))
+      (node (ref C7) (pin 2))
+      (node (ref C4) (pin 2))
+      (node (ref U2) (pin 4))
+      (node (ref C13) (pin 2))
+      (node (ref C15) (pin 2))
+      (node (ref U9) (pin 1))
+      (node (ref U4) (pin 10))
+      (node (ref U4) (pin 19))
+      (node (ref U5) (pin 10))
+      (node (ref U9) (pin 20))
+      (node (ref U8) (pin 16))
+      (node (ref C16) (pin 2))
+      (node (ref U1) (pin 73))
+      (node (ref C22) (pin 2))
+      (node (ref J1) (pin 6))
+      (node (ref U6) (pin 10))
+      (node (ref C17) (pin 2))
+      (node (ref C21) (pin 2))
+      (node (ref U5) (pin 1))
+      (node (ref C31) (pin 2))
+      (node (ref U3) (pin 2))
+      (node (ref C29) (pin 2))
+      (node (ref C18) (pin 2))
+      (node (ref C19) (pin 2))
+      (node (ref C30) (pin 2))
+      (node (ref C28) (pin 2))
+      (node (ref U7) (pin 2))
+      (node (ref U1) (pin 13))
+      (node (ref C25) (pin 2))
+      (node (ref U1) (pin 77))
+      (node (ref U1) (pin 68))
+      (node (ref U1) (pin 54))
+      (node (ref U1) (pin 49))
+      (node (ref U1) (pin 25))
+      (node (ref U1) (pin 3))
+      (node (ref C20) (pin 2)))
+    (net (code 8) (name A11_5V)
+      (node (ref U9) (pin 5))
+      (node (ref U1) (pin 7)))
+    (net (code 9) (name A15_5V)
+      (node (ref U1) (pin 143))
+      (node (ref U9) (pin 39)))
+    (net (code 10) (name A13_5V)
+      (node (ref U1) (pin 1))
+      (node (ref U9) (pin 3)))
+    (net (code 11) (name A16_5V)
+      (node (ref U1) (pin 2))
+      (node (ref U9) (pin 38)))
+    (net (code 12) (name A12_5V)
+      (node (ref U9) (pin 4))
+      (node (ref U1) (pin 5)))
+    (net (code 13) (name A17_5V)
+      (node (ref U9) (pin 37))
+      (node (ref U1) (pin 6)))
+    (net (code 14) (name A18_5V)
+      (node (ref U1) (pin 8))
+      (node (ref U9) (pin 36)))
+    (net (code 15) (name A10_5V)
+      (node (ref U9) (pin 6))
+      (node (ref U1) (pin 9)))
+    (net (code 16) (name A19_5V)
+      (node (ref U9) (pin 35))
+      (node (ref U1) (pin 10)))
+    (net (code 17) (name A9_5V)
+      (node (ref U1) (pin 11))
+      (node (ref U9) (pin 7)))
+    (net (code 18) (name SSO_5V)
+      (node (ref U1) (pin 12))
+      (node (ref U9) (pin 34)))
+    (net (code 19) (name FPGA_M1)
+      (node (ref R11) (pin 2))
+      (node (ref U1) (pin 60)))
+    (net (code 20) (name FPGA_M0)
+      (node (ref U1) (pin 69))
+      (node (ref R10) (pin 2)))
+    (net (code 21) (name LED6)
+      (node (ref U1) (pin 127))
+      (node (ref D7) (pin 1)))
+    (net (code 22) (name LED1)
+      (node (ref U1) (pin 112))
+      (node (ref D2) (pin 1)))
+    (net (code 23) (name LED2)
+      (node (ref U1) (pin 114))
+      (node (ref D3) (pin 1)))
+    (net (code 24) (name LED3)
+      (node (ref U1) (pin 116))
+      (node (ref D4) (pin 1)))
+    (net (code 25) (name LED4)
+      (node (ref D5) (pin 1))
+      (node (ref U1) (pin 120)))
+    (net (code 26) (name LED5)
+      (node (ref D6) (pin 1))
+      (node (ref U1) (pin 121)))
+    (net (code 27) (name LED0)
+      (node (ref U1) (pin 111))
+      (node (ref D1) (pin 1)))
+    (net (code 28) (name LED7)
+      (node (ref D8) (pin 1))
+      (node (ref U1) (pin 131)))
+    (net (code 29) (name "Net-(J1-Pad2)")
+      (node (ref U1) (pin 110))
+      (node (ref J1) (pin 2)))
+    (net (code 30) (name "Net-(J1-Pad4)")
+      (node (ref U1) (pin 107))
+      (node (ref J1) (pin 4)))
+    (net (code 31) (name "Net-(J1-Pad5)")
+      (node (ref U1) (pin 106))
+      (node (ref J1) (pin 5)))
+    (net (code 32) (name SRAM_A3)
+      (node (ref U8) (pin 9))
+      (node (ref U1) (pin 123)))
+    (net (code 33) (name SRAM_A13)
+      (node (ref U8) (pin 28))
+      (node (ref U1) (pin 97)))
+    (net (code 34) (name SRAM_WE_n)
+      (node (ref U1) (pin 98))
+      (node (ref U8) (pin 29)))
+    (net (code 35) (name SRAM_A18)
+      (node (ref U1) (pin 99))
+      (node (ref U8) (pin 30)))
+    (net (code 36) (name SRAM_A15)
+      (node (ref U1) (pin 100))
+      (node (ref U8) (pin 31)))
+    (net (code 37) (name SRAM_D2)
+      (node (ref U1) (pin 117))
+      (node (ref U8) (pin 15)))
+    (net (code 38) (name SRAM_D1)
+      (node (ref U8) (pin 14))
+      (node (ref U1) (pin 118)))
+    (net (code 39) (name SRAM_A2)
+      (node (ref U1) (pin 124))
+      (node (ref U8) (pin 10)))
+    (net (code 40) (name SRAM_A1)
+      (node (ref U8) (pin 11))
+      (node (ref U1) (pin 126)))
+    (net (code 41) (name SRAM_A0)
+      (node (ref U1) (pin 132))
+      (node (ref U8) (pin 12)))
+    (net (code 42) (name SRAM_D0)
+      (node (ref U8) (pin 13))
+      (node (ref U1) (pin 119)))
+    (net (code 43) (name "Net-(J1-Pad3)")
+      (node (ref U1) (pin 109))
+      (node (ref J1) (pin 3)))
+    (net (code 44) (name A14_5V)
+      (node (ref U9) (pin 2))
+      (node (ref U1) (pin 142)))
+    (net (code 45) (name RESET_3V)
+      (node (ref U1) (pin 47))
+      (node (ref U4) (pin 13)))
+    (net (code 46) (name HLDA_3V)
+      (node (ref U4) (pin 2))
+      (node (ref U1) (pin 40)))
+    (net (code 47) (name ALE_3V)
+      (node (ref U1) (pin 41))
+      (node (ref U4) (pin 9)))
+    (net (code 48) (name HOLD_3V)
+      (node (ref U1) (pin 43))
+      (node (ref U4) (pin 17)))
+    (net (code 49) (name NMI_3V)
+      (node (ref U1) (pin 44))
+      (node (ref U4) (pin 16)))
+    (net (code 50) (name INTR_3V)
+      (node (ref U4) (pin 15))
+      (node (ref U1) (pin 45)))
+    (net (code 51) (name CLK_3V)
+      (node (ref U1) (pin 46))
+      (node (ref U4) (pin 14)))
+    (net (code 52) (name READY_3V)
+      (node (ref U4) (pin 12))
+      (node (ref U1) (pin 48)))
+    (net (code 53) (name RD_3V)
+      (node (ref U5) (pin 13))
+      (node (ref U1) (pin 50)))
+    (net (code 54) (name WR_3V)
+      (node (ref U1) (pin 51))
+      (node (ref U5) (pin 14)))
+    (net (code 55) (name IOM_3V)
+      (node (ref U5) (pin 15))
+      (node (ref U1) (pin 55)))
+    (net (code 56) (name DTR_3V)
+      (node (ref U1) (pin 56))
+      (node (ref U5) (pin 16)))
+    (net (code 57) (name AD5_3V)
+      (node (ref U6) (pin 16))
+      (node (ref U1) (pin 26)))
+    (net (code 58) (name A8_5V)
+      (node (ref U9) (pin 8))
+      (node (ref U1) (pin 14)))
+    (net (code 59) (name BUF2_DIR)
+      (node (ref U1) (pin 16))
+      (node (ref U6) (pin 1)))
+    (net (code 60) (name BUF2_OE__n)
+      (node (ref U1) (pin 21))
+      (node (ref U6) (pin 19)))
+    (net (code 61) (name AD7_3V)
+      (node (ref U1) (pin 22))
+      (node (ref U6) (pin 18)))
+    (net (code 62) (name AD6_3V)
+      (node (ref U1) (pin 23))
+      (node (ref U6) (pin 17)))
+    (net (code 63) (name AD4_3V)
+      (node (ref U6) (pin 15))
+      (node (ref U1) (pin 27)))
+    (net (code 64) (name AD3_3V)
+      (node (ref U6) (pin 14))
+      (node (ref U1) (pin 32)))
+    (net (code 65) (name AD2_3V)
+      (node (ref U6) (pin 13))
+      (node (ref U1) (pin 33)))
+    (net (code 66) (name AD1_3V)
+      (node (ref U6) (pin 12))
+      (node (ref U1) (pin 34)))
+    (net (code 67) (name AD0_3V)
+      (node (ref U1) (pin 35))
+      (node (ref U6) (pin 11)))
+    (net (code 68) (name SRAM_CE_n)
+      (node (ref U8) (pin 22))
+      (node (ref U1) (pin 87)))
+    (net (code 69) (name SRAM_D3)
+      (node (ref U1) (pin 80))
+      (node (ref U8) (pin 17)))
+    (net (code 70) (name SRAM_D4)
+      (node (ref U1) (pin 81))
+      (node (ref U8) (pin 18)))
+    (net (code 71) (name SRAM_D5)
+      (node (ref U1) (pin 82))
+      (node (ref U8) (pin 19)))
+    (net (code 72) (name SRAM_D6)
+      (node (ref U1) (pin 83))
+      (node (ref U8) (pin 20)))
+    (net (code 73) (name SRAM_D7)
+      (node (ref U8) (pin 21))
+      (node (ref U1) (pin 85)))
+    (net (code 74) (name SRAM_A17)
+      (node (ref U1) (pin 79))
+      (node (ref U8) (pin 1)))
+    (net (code 75) (name SRAM_A10)
+      (node (ref U1) (pin 88))
+      (node (ref U8) (pin 23)))
+    (net (code 76) (name SRAM_OE_n)
+      (node (ref U8) (pin 24))
+      (node (ref U1) (pin 92)))
+    (net (code 77) (name SRAM_A11)
+      (node (ref U8) (pin 25))
+      (node (ref U1) (pin 93)))
+    (net (code 78) (name SRAM_A9)
+      (node (ref U8) (pin 26))
+      (node (ref U1) (pin 94)))
+    (net (code 79) (name SRAM_A8)
+      (node (ref U1) (pin 95))
+      (node (ref U8) (pin 27)))
+    (net (code 80) (name SRAM_A6)
+      (node (ref U8) (pin 6))
+      (node (ref U1) (pin 66)))
+    (net (code 81) (name DEN_3V)
+      (node (ref U1) (pin 57))
+      (node (ref U5) (pin 17)))
+    (net (code 82) (name INTA_n_3V)
+      (node (ref U1) (pin 58))
+      (node (ref U5) (pin 18)))
+    (net (code 83) (name BUF1_OE__n)
+      (node (ref U5) (pin 19))
+      (node (ref U1) (pin 59)))
+    (net (code 84) (name SRAM_A4)
+      (node (ref U1) (pin 61))
+      (node (ref U8) (pin 8)))
+    (net (code 85) (name SRAM_A5)
+      (node (ref U8) (pin 7))
+      (node (ref U1) (pin 62)))
+    (net (code 86) (name SRAM_A7)
+      (node (ref U8) (pin 5))
+      (node (ref U1) (pin 67)))
+    (net (code 87) (name SRAM_A12)
+      (node (ref U1) (pin 74))
+      (node (ref U8) (pin 4)))
+    (net (code 88) (name SRAM_A14)
+      (node (ref U8) (pin 3))
+      (node (ref U1) (pin 75)))
+    (net (code 89) (name SRAM_A16)
+      (node (ref U8) (pin 2))
+      (node (ref U1) (pin 78)))
+    (net (code 90) (name "Net-(U1-Pad72)")
+      (node (ref U1) (pin 72)))
+    (net (code 91) (name "Net-(U1-Pad30)")
+      (node (ref U1) (pin 30)))
+    (net (code 92) (name "Net-(U1-Pad29)")
+      (node (ref U1) (pin 29)))
+    (net (code 93) (name "Net-(U1-Pad24)")
+      (node (ref U1) (pin 24)))
+    (net (code 94) (name "Net-(U1-Pad17)")
+      (node (ref U1) (pin 17)))
+    (net (code 95) (name "Net-(U1-Pad15)")
+      (node (ref U1) (pin 15)))
+    (net (code 96) (name +1V2)
+      (node (ref C28) (pin 1))
+      (node (ref C19) (pin 1))
+      (node (ref U7) (pin 5))
+      (node (ref C11) (pin 1))
+      (node (ref C12) (pin 1))
+      (node (ref C13) (pin 1))
+      (node (ref C15) (pin 1))
+      (node (ref U1) (pin 52))
+      (node (ref U1) (pin 89))
+      (node (ref U1) (pin 128))
+      (node (ref C31) (pin 1))
+      (node (ref U1) (pin 19))
+      (node (ref U1) (pin 28)))
+    (net (code 97) (name "Net-(U1-Pad102)")
+      (node (ref U1) (pin 102)))
+    (net (code 98) (name "Net-(U1-Pad115)")
+      (node (ref U1) (pin 115)))
+    (net (code 99) (name "Net-(U1-Pad105)")
+      (node (ref U1) (pin 105)))
+    (net (code 100) (name "Net-(U1-Pad104)")
+      (node (ref U1) (pin 104)))
+    (net (code 101) (name "Net-(U1-Pad101)")
+      (node (ref U1) (pin 101)))
+    (net (code 102) (name "Net-(U1-Pad134)")
+      (node (ref U1) (pin 134)))
+    (net (code 103) (name "Net-(U1-Pad141)")
+      (node (ref U1) (pin 141)))
+    (net (code 104) (name "Net-(U1-Pad140)")
+      (node (ref U1) (pin 140)))
+    (net (code 105) (name "Net-(U1-Pad139)")
+      (node (ref U1) (pin 139)))
+    (net (code 106) (name "Net-(U1-Pad138)")
+      (node (ref U1) (pin 138)))
+    (net (code 107) (name "Net-(U1-Pad137)")
+      (node (ref U1) (pin 137)))
+    (net (code 108) (name "Net-(U1-Pad133)")
+      (node (ref U1) (pin 133)))
+    (net (code 109) (name "Net-(R16-Pad1)")
+      (node (ref R16) (pin 1))
+      (node (ref U1) (pin 70)))
+    (net (code 110) (name SPI_CS_n)
+      (node (ref U1) (pin 38))
+      (node (ref U2) (pin 1))
+      (node (ref R15) (pin 2)))
+    (net (code 111) (name SPI_DIN)
+      (node (ref U2) (pin 5))
+      (node (ref U1) (pin 64)))
+    (net (code 112) (name CLK_100MHZ)
+      (node (ref U1) (pin 84))
+      (node (ref R1) (pin 1)))
+    (net (code 113) (name "Net-(R1-Pad2)")
+      (node (ref Y1) (pin 3))
+      (node (ref R1) (pin 2)))
+    (net (code 114) (name "Net-(D8-Pad2)")
+      (node (ref D8) (pin 2))
+      (node (ref R9) (pin 1)))
+    (net (code 115) (name "Net-(D7-Pad2)")
+      (node (ref D7) (pin 2))
+      (node (ref R8) (pin 1)))
+    (net (code 116) (name "Net-(D6-Pad2)")
+      (node (ref R7) (pin 1))
+      (node (ref D6) (pin 2)))
+    (net (code 117) (name "Net-(D5-Pad2)")
+      (node (ref R6) (pin 1))
+      (node (ref D5) (pin 2)))
+    (net (code 118) (name "Net-(D4-Pad2)")
+      (node (ref D4) (pin 2))
+      (node (ref R5) (pin 1)))
+    (net (code 119) (name "Net-(D2-Pad2)")
+      (node (ref D2) (pin 2))
+      (node (ref R3) (pin 1)))
+    (net (code 120) (name +5V)
+      (node (ref C16) (pin 1))
+      (node (ref U3) (pin 1))
+      (node (ref U3) (pin 3))
+      (node (ref U9) (pin 40)))
+    (net (code 121) (name "Net-(D3-Pad2)")
+      (node (ref D3) (pin 2))
+      (node (ref R4) (pin 1)))
+    (net (code 122) (name "Net-(D1-Pad2)")
+      (node (ref D1) (pin 2))
+      (node (ref R2) (pin 1)))
+    (net (code 123) (name AD4_5V)
+      (node (ref U9) (pin 12))
+      (node (ref U6) (pin 5)))
+    (net (code 124) (name AD2_5V)
+      (node (ref U6) (pin 7))
+      (node (ref U9) (pin 14)))
+    (net (code 125) (name AD1_5V)
+      (node (ref U9) (pin 15))
+      (node (ref U6) (pin 8)))
+    (net (code 126) (name AD0_5V)
+      (node (ref U6) (pin 9))
+      (node (ref U9) (pin 16)))
+    (net (code 127) (name NMI_5V)
+      (node (ref U9) (pin 17))
+      (node (ref U4) (pin 4)))
+    (net (code 128) (name INTR_5V)
+      (node (ref U9) (pin 18))
+      (node (ref U4) (pin 5)))
+    (net (code 129) (name CLK_5V)
+      (node (ref U9) (pin 19))
+      (node (ref U4) (pin 6)))
+    (net (code 130) (name MINMAX_5V)
+      (node (ref U9) (pin 33)))
+    (net (code 131) (name TEST_5V)
+      (node (ref U9) (pin 23)))
+    (net (code 132) (name HOLD_5V)
+      (node (ref U4) (pin 3))
+      (node (ref U9) (pin 31)))
+    (net (code 133) (name RD_5V)
+      (node (ref U9) (pin 32))
+      (node (ref U5) (pin 7)))
+    (net (code 134) (name RESET_5V)
+      (node (ref U4) (pin 7))
+      (node (ref U9) (pin 21)))
+    (net (code 135) (name WR_5V)
+      (node (ref U9) (pin 29))
+      (node (ref U5) (pin 6)))
+    (net (code 136) (name IOM_5V)
+      (node (ref U9) (pin 28))
+      (node (ref U5) (pin 5)))
+    (net (code 137) (name DTR_5V)
+      (node (ref U9) (pin 27))
+      (node (ref U5) (pin 4)))
+    (net (code 138) (name INTA_n_5V)
+      (node (ref U5) (pin 2))
+      (node (ref U9) (pin 24)))
+    (net (code 139) (name READY_5V)
+      (node (ref U9) (pin 22))
+      (node (ref U4) (pin 8)))
+    (net (code 140) (name HLDA_5V)
+      (node (ref U4) (pin 18))
+      (node (ref U9) (pin 30)))
+    (net (code 141) (name DEN_5V)
+      (node (ref U5) (pin 3))
+      (node (ref U9) (pin 26)))
+    (net (code 142) (name AD6_5V)
+      (node (ref U9) (pin 10))
+      (node (ref U6) (pin 3)))
+    (net (code 143) (name AD7_5V)
+      (node (ref U6) (pin 2))
+      (node (ref U9) (pin 9)))
+    (net (code 144) (name "Net-(U5-Pad11)")
+      (node (ref U5) (pin 11)))
+    (net (code 145) (name "Net-(U5-Pad12)")
+      (node (ref U5) (pin 12)))
+    (net (code 146) (name "Net-(U5-Pad9)")
+      (node (ref U5) (pin 9)))
+    (net (code 147) (name "Net-(U5-Pad8)")
+      (node (ref U5) (pin 8)))
+    (net (code 148) (name AD5_5V)
+      (node (ref U6) (pin 4))
+      (node (ref U9) (pin 11)))
+    (net (code 149) (name ALE_5V)
+      (node (ref U9) (pin 25))
+      (node (ref U4) (pin 11)))
+    (net (code 150) (name AD3_5V)
+      (node (ref U6) (pin 6))
+      (node (ref U9) (pin 13)))))
\ No newline at end of file
diff --git a/MCL86jr/PCBA/MCL86jr.pro b/MCL86jr/PCBA/MCL86jr.pro
new file mode 100644
index 0000000..fe348d5
--- /dev/null
+++ b/MCL86jr/PCBA/MCL86jr.pro
@@ -0,0 +1,248 @@
+update=9/30/2020 10:11:41 PM
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=MCL86jr.net
+CopperLayerCount=4
+BoardThickness=1.6
+AllowMicroVias=0
+AllowBlindVias=0
+RequireCourtyardDefinitions=0
+ProhibitOverlappingCourtyards=1
+MinTrackWidth=0.2
+MinViaDiameter=0.4
+MinViaDrill=0.3
+MinMicroViaDiameter=0.2
+MinMicroViaDrill=0.09999999999999999
+MinHoleToHole=0.25
+TrackWidth1=0.2
+ViaDiameter1=0.8
+ViaDrill1=0.4
+dPairWidth1=0.2
+dPairGap1=0.25
+dPairViaGap1=0.25
+SilkLineWidth=0.12
+SilkTextSizeV=1
+SilkTextSizeH=1
+SilkTextSizeThickness=0.15
+SilkTextItalic=0
+SilkTextUpright=1
+CopperLineWidth=0.2
+CopperTextSizeV=1.5
+CopperTextSizeH=1.5
+CopperTextThickness=0.3
+CopperTextItalic=0
+CopperTextUpright=1
+EdgeCutLineWidth=0.05
+CourtyardLineWidth=0.05
+OthersLineWidth=0.15
+OthersTextSizeV=1
+OthersTextSizeH=1
+OthersTextSizeThickness=0.15
+OthersTextItalic=0
+OthersTextUpright=1
+SolderMaskClearance=0.051
+SolderMaskMinWidth=0.25
+SolderPasteClearance=0
+SolderPasteRatio=-0
+[pcbnew/Layer.F.Cu]
+Name=F.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In1.Cu]
+Name=In1.Cu
+Type=1
+Enabled=1
+[pcbnew/Layer.In2.Cu]
+Name=In2.Cu
+Type=1
+Enabled=1
+[pcbnew/Layer.In3.Cu]
+Name=In3.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In4.Cu]
+Name=In4.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In5.Cu]
+Name=In5.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In6.Cu]
+Name=In6.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In7.Cu]
+Name=In7.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In8.Cu]
+Name=In8.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In9.Cu]
+Name=In9.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In10.Cu]
+Name=In10.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In11.Cu]
+Name=In11.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In12.Cu]
+Name=In12.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In13.Cu]
+Name=In13.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In14.Cu]
+Name=In14.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In15.Cu]
+Name=In15.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In16.Cu]
+Name=In16.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In17.Cu]
+Name=In17.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In18.Cu]
+Name=In18.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In19.Cu]
+Name=In19.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In20.Cu]
+Name=In20.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In21.Cu]
+Name=In21.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In22.Cu]
+Name=In22.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In23.Cu]
+Name=In23.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In24.Cu]
+Name=In24.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In25.Cu]
+Name=In25.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In26.Cu]
+Name=In26.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In27.Cu]
+Name=In27.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In28.Cu]
+Name=In28.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In29.Cu]
+Name=In29.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In30.Cu]
+Name=In30.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.B.Cu]
+Name=B.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.B.Adhes]
+Enabled=1
+[pcbnew/Layer.F.Adhes]
+Enabled=1
+[pcbnew/Layer.B.Paste]
+Enabled=1
+[pcbnew/Layer.F.Paste]
+Enabled=1
+[pcbnew/Layer.B.SilkS]
+Enabled=1
+[pcbnew/Layer.F.SilkS]
+Enabled=1
+[pcbnew/Layer.B.Mask]
+Enabled=1
+[pcbnew/Layer.F.Mask]
+Enabled=1
+[pcbnew/Layer.Dwgs.User]
+Enabled=1
+[pcbnew/Layer.Cmts.User]
+Enabled=1
+[pcbnew/Layer.Eco1.User]
+Enabled=1
+[pcbnew/Layer.Eco2.User]
+Enabled=1
+[pcbnew/Layer.Edge.Cuts]
+Enabled=1
+[pcbnew/Layer.Margin]
+Enabled=1
+[pcbnew/Layer.B.CrtYd]
+Enabled=1
+[pcbnew/Layer.F.CrtYd]
+Enabled=1
+[pcbnew/Layer.B.Fab]
+Enabled=1
+[pcbnew/Layer.F.Fab]
+Enabled=1
+[pcbnew/Layer.Rescue]
+Enabled=0
+[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
+Clearance=0.2
+TrackWidth=0.2
+ViaDiameter=0.8
+ViaDrill=0.4
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=Pcbnew
+SpiceAjustPassiveValues=0
+LabSize=276
+ERC_TestSimilarLabels=1
diff --git a/MCL86jr/PCBA/MCL86jr.sch b/MCL86jr/PCBA/MCL86jr.sch
new file mode 100644
index 0000000..77d994a
--- /dev/null
+++ b/MCL86jr/PCBA/MCL86jr.sch
@@ -0,0 +1,40 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr B 17000 11000
+encoding utf-8
+Sheet 1 4
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Sheet
+S 4000 3000 3000 500 
+U 5F609430
+F0 "Page1" 50
+F1 "Page1.sch" 50
+$EndSheet
+$Sheet
+S 4000 3950 3000 500 
+U 5F62178D
+F0 "Page3" 50
+F1 "Page3sch.sch" 50
+$EndSheet
+$Sheet
+S 4000 4950 3000 500 
+U 5F6217EE
+F0 "Page4" 50
+F1 "Page4.sch" 50
+$EndSheet
+Text Notes 8400 3450 0    276  ~ 0
+FPGA
+Text Notes 8400 4350 0    276  ~ 0
+SRAM and Power
+Text Notes 8400 5300 0    276  ~ 0
+8088 Header and Buffers
+$EndSCHEMATC
diff --git a/MCL86jr/PCBA/MCL86jr.sch-bak b/MCL86jr/PCBA/MCL86jr.sch-bak
new file mode 100644
index 0000000..77d994a
--- /dev/null
+++ b/MCL86jr/PCBA/MCL86jr.sch-bak
@@ -0,0 +1,40 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr B 17000 11000
+encoding utf-8
+Sheet 1 4
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Sheet
+S 4000 3000 3000 500 
+U 5F609430
+F0 "Page1" 50
+F1 "Page1.sch" 50
+$EndSheet
+$Sheet
+S 4000 3950 3000 500 
+U 5F62178D
+F0 "Page3" 50
+F1 "Page3sch.sch" 50
+$EndSheet
+$Sheet
+S 4000 4950 3000 500 
+U 5F6217EE
+F0 "Page4" 50
+F1 "Page4.sch" 50
+$EndSheet
+Text Notes 8400 3450 0    276  ~ 0
+FPGA
+Text Notes 8400 4350 0    276  ~ 0
+SRAM and Power
+Text Notes 8400 5300 0    276  ~ 0
+8088 Header and Buffers
+$EndSCHEMATC
diff --git a/MCL86jr/PCBA/MCL86jr.xml b/MCL86jr/PCBA/MCL86jr.xml
new file mode 100644
index 0000000..c7735ec
--- /dev/null
+++ b/MCL86jr/PCBA/MCL86jr.xml
@@ -0,0 +1,1735 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<export version="D">
+  <design>
+    <source>Z:\Ted\projs\MCL86\MCL86jr\MCL86jr.sch</source>
+    <date>9/27/2020 8:16:31 PM</date>
+    <tool>Eeschema (5.1.5)-3</tool>
+    <sheet number="1" name="/" tstamps="/">
+      <title_block>
+        <title/>
+        <company/>
+        <rev/>
+        <date/>
+        <source>MCL86jr.sch</source>
+        <comment number="1" value=""/>
+        <comment number="2" value=""/>
+        <comment number="3" value=""/>
+        <comment number="4" value=""/>
+      </title_block>
+    </sheet>
+    <sheet number="2" name="/Page1/" tstamps="/5F609430/">
+      <title_block>
+        <title/>
+        <company/>
+        <rev/>
+        <date/>
+        <source>Page1.sch</source>
+        <comment number="1" value=""/>
+        <comment number="2" value=""/>
+        <comment number="3" value=""/>
+        <comment number="4" value=""/>
+      </title_block>
+    </sheet>
+    <sheet number="3" name="/Page3/" tstamps="/5F62178D/">
+      <title_block>
+        <title/>
+        <company/>
+        <rev/>
+        <date/>
+        <source>Page3sch.sch</source>
+        <comment number="1" value=""/>
+        <comment number="2" value=""/>
+        <comment number="3" value=""/>
+        <comment number="4" value=""/>
+      </title_block>
+    </sheet>
+    <sheet number="4" name="/Page4/" tstamps="/5F6217EE/">
+      <title_block>
+        <title/>
+        <company/>
+        <rev/>
+        <date/>
+        <source>Page4.sch</source>
+        <comment number="1" value=""/>
+        <comment number="2" value=""/>
+        <comment number="3" value=""/>
+        <comment number="4" value=""/>
+      </title_block>
+    </sheet>
+  </design>
+  <components>
+    <comp ref="U1">
+      <value>XC6SLX9-TQG144</value>
+      <footprint>Package_QFP:TQFP-144_20x20mm_P0.5mm</footprint>
+      <libsource lib="FPGA_Xilinx_Spartan6" part="XC6SLX9-TQG144" description="Spartan 6 LX 9 XC6SLX9-TQG144"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5F6440A9</tstamp>
+    </comp>
+    <comp ref="Y1">
+      <value>100Mhz</value>
+      <footprint>OSC_SIT8008BI-13-33E-33.333330E</footprint>
+      <datasheet>Manufacturer Recommendations</datasheet>
+      <fields>
+        <field name="Field4">1.04</field>
+        <field name="Field5">0.8mm</field>
+        <field name="Field6">SiTime</field>
+      </fields>
+      <libsource lib="SIT8008BI-13-33E-33.333330E" part="SIT8008BI-13-33E-33.333330E" description=""/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5F7DBEF0</tstamp>
+    </comp>
+    <comp ref="R1">
+      <value>33</value>
+      <footprint>Resistor_SMD:R_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5F7DBF00</tstamp>
+    </comp>
+    <comp ref="U2">
+      <value>W25Q128JVS</value>
+      <footprint>Package_SO:SOIC-8_5.23x5.23mm_P1.27mm</footprint>
+      <datasheet>http://www.winbond.com/resource-files/w25q128jv_dtr%20revc%2003272018%20plus.pdf</datasheet>
+      <libsource lib="Memory_Flash" part="W25Q128JVS" description="128Mb Serial Flash Memory, Standard/Dual/Quad SPI, SOIC-8"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5F7F9366</tstamp>
+    </comp>
+    <comp ref="C1">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5F92D2C4</tstamp>
+    </comp>
+    <comp ref="C3">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5F98F0C7</tstamp>
+    </comp>
+    <comp ref="C5">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5F999BF7</tstamp>
+    </comp>
+    <comp ref="C14">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5F99F57A</tstamp>
+    </comp>
+    <comp ref="C9">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5F9B5C56</tstamp>
+    </comp>
+    <comp ref="C10">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FA06BB4</tstamp>
+    </comp>
+    <comp ref="C8">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FA708B6</tstamp>
+    </comp>
+    <comp ref="C7">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FA7D5C4</tstamp>
+    </comp>
+    <comp ref="C6">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FA83EE0</tstamp>
+    </comp>
+    <comp ref="C4">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FA8ABC6</tstamp>
+    </comp>
+    <comp ref="C15">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FA9B5A8</tstamp>
+    </comp>
+    <comp ref="C13">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FA9B5B7</tstamp>
+    </comp>
+    <comp ref="C12">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FA9B5C7</tstamp>
+    </comp>
+    <comp ref="C11">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FA9B5D6</tstamp>
+    </comp>
+    <comp ref="C2">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FAAB60A</tstamp>
+    </comp>
+    <comp ref="R10">
+      <value>4.7k</value>
+      <footprint>Resistor_SMD:R_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FB0A2A1</tstamp>
+    </comp>
+    <comp ref="R11">
+      <value>4.7k</value>
+      <footprint>Resistor_SMD:R_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FB6A4AD</tstamp>
+    </comp>
+    <comp ref="R14">
+      <value>4.7k</value>
+      <footprint>Resistor_SMD:R_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FBA7A81</tstamp>
+    </comp>
+    <comp ref="R12">
+      <value>4.7k</value>
+      <footprint>Resistor_SMD:R_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FBB9847</tstamp>
+    </comp>
+    <comp ref="R13">
+      <value>4.7k</value>
+      <footprint>Resistor_SMD:R_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FBD99FB</tstamp>
+    </comp>
+    <comp ref="R15">
+      <value>4.7k</value>
+      <footprint>Resistor_SMD:R_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FD82F74</tstamp>
+    </comp>
+    <comp ref="R16">
+      <value>33</value>
+      <footprint>Resistor_SMD:R_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FDFB8A4</tstamp>
+    </comp>
+    <comp ref="C25">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FF14247</tstamp>
+    </comp>
+    <comp ref="C26">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FF1DF62</tstamp>
+    </comp>
+    <comp ref="C27">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5FF27C34</tstamp>
+    </comp>
+    <comp ref="J1">
+      <value>Conn_01x06_Female</value>
+      <footprint>Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Connector" part="Conn_01x06_Female" description="Generic connector, single row, 01x06, script generated (kicad-library-utils/schlib/autogen/connector/)"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>5F76EDA5</tstamp>
+    </comp>
+    <comp ref="C28">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>60E87B06</tstamp>
+    </comp>
+    <comp ref="C30">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>60EB6252</tstamp>
+    </comp>
+    <comp ref="C29">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page1/" tstamps="/5F609430/"/>
+      <tstamp>60ECB869</tstamp>
+    </comp>
+    <comp ref="U3">
+      <value>MIC5504-3.3YM5-TR</value>
+      <footprint>SOT23-5P95_280X145XL45X37N</footprint>
+      <datasheet>MICREL</datasheet>
+      <libsource lib="MIC5504-1.2YM5-TR" part="MIC5504-1.2YM5-TR" description=""/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F8012DE</tstamp>
+    </comp>
+    <comp ref="U7">
+      <value>MIC5504-1.2YM5-TR</value>
+      <footprint>SOT23-5P95_280X145XL45X37N</footprint>
+      <datasheet>MICREL</datasheet>
+      <libsource lib="MIC5504-1.2YM5-TR" part="MIC5504-1.2YM5-TR" description=""/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F8012E4</tstamp>
+    </comp>
+    <comp ref="D1">
+      <value>LED</value>
+      <footprint>LED_SMD:LED_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="LED" description="Light emitting diode"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F8C9584</tstamp>
+    </comp>
+    <comp ref="R2">
+      <value>330</value>
+      <footprint>Resistor_SMD:R_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F8CD1C0</tstamp>
+    </comp>
+    <comp ref="D2">
+      <value>LED</value>
+      <footprint>LED_SMD:LED_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="LED" description="Light emitting diode"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F8DC90D</tstamp>
+    </comp>
+    <comp ref="D3">
+      <value>LED</value>
+      <footprint>LED_SMD:LED_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="LED" description="Light emitting diode"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F8DEB5D</tstamp>
+    </comp>
+    <comp ref="D4">
+      <value>LED</value>
+      <footprint>LED_SMD:LED_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="LED" description="Light emitting diode"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F8DEB6E</tstamp>
+    </comp>
+    <comp ref="D5">
+      <value>LED</value>
+      <footprint>LED_SMD:LED_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="LED" description="Light emitting diode"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F8E337A</tstamp>
+    </comp>
+    <comp ref="D6">
+      <value>LED</value>
+      <footprint>LED_SMD:LED_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="LED" description="Light emitting diode"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F8E338B</tstamp>
+    </comp>
+    <comp ref="D7">
+      <value>LED</value>
+      <footprint>LED_SMD:LED_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="LED" description="Light emitting diode"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F8E339C</tstamp>
+    </comp>
+    <comp ref="D8">
+      <value>LED</value>
+      <footprint>LED_SMD:LED_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="LED" description="Light emitting diode"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F8E33AD</tstamp>
+    </comp>
+    <comp ref="R3">
+      <value>330</value>
+      <footprint>Resistor_SMD:R_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F9031C9</tstamp>
+    </comp>
+    <comp ref="R4">
+      <value>330</value>
+      <footprint>Resistor_SMD:R_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F905C0D</tstamp>
+    </comp>
+    <comp ref="R5">
+      <value>330</value>
+      <footprint>Resistor_SMD:R_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F905C13</tstamp>
+    </comp>
+    <comp ref="R6">
+      <value>330</value>
+      <footprint>Resistor_SMD:R_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F908B41</tstamp>
+    </comp>
+    <comp ref="R7">
+      <value>330</value>
+      <footprint>Resistor_SMD:R_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F908B47</tstamp>
+    </comp>
+    <comp ref="R8">
+      <value>330</value>
+      <footprint>Resistor_SMD:R_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F908B4D</tstamp>
+    </comp>
+    <comp ref="R9">
+      <value>330</value>
+      <footprint>Resistor_SMD:R_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F908B53</tstamp>
+    </comp>
+    <comp ref="C20">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5FA14AF8</tstamp>
+    </comp>
+    <comp ref="C21">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5FA17919</tstamp>
+    </comp>
+    <comp ref="C17">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5FAF0B3F</tstamp>
+    </comp>
+    <comp ref="C19">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5FAF607D</tstamp>
+    </comp>
+    <comp ref="C18">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5FADFFF0</tstamp>
+    </comp>
+    <comp ref="C16">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5FADABE7</tstamp>
+    </comp>
+    <comp ref="U8">
+      <value>CY62148GN-45ZSXI</value>
+      <footprint>SOIC127P1176X120-32N</footprint>
+      <datasheet>Cypress Semiconductor</datasheet>
+      <fields>
+        <field name="Field4">SOIC127P1176X120-32N</field>
+      </fields>
+      <libsource lib="CY62148GN-45ZSXI" part="CY62148GN-45ZSXI" description=""/>
+      <sheetpath names="/Page3/" tstamps="/5F62178D/"/>
+      <tstamp>5F64044A</tstamp>
+    </comp>
+    <comp ref="U4">
+      <value>SN74LVC245APW</value>
+      <footprint>SOP65P640X120-20N</footprint>
+      <libsource lib="SN74LVC245APW" part="SN74LVC245APW" description=""/>
+      <sheetpath names="/Page4/" tstamps="/5F6217EE/"/>
+      <tstamp>5F622E6C</tstamp>
+    </comp>
+    <comp ref="U5">
+      <value>SN74LVC245APW</value>
+      <footprint>SOP65P640X120-20N</footprint>
+      <libsource lib="SN74LVC245APW" part="SN74LVC245APW" description=""/>
+      <sheetpath names="/Page4/" tstamps="/5F6217EE/"/>
+      <tstamp>5F6230CD</tstamp>
+    </comp>
+    <comp ref="U6">
+      <value>SN74LVC245APW</value>
+      <footprint>SOP65P640X120-20N</footprint>
+      <libsource lib="SN74LVC245APW" part="SN74LVC245APW" description=""/>
+      <sheetpath names="/Page4/" tstamps="/5F6217EE/"/>
+      <tstamp>5F623800</tstamp>
+    </comp>
+    <comp ref="U9">
+      <value>8088_Min_Mode</value>
+      <footprint>Package_DIP:DIP-40_W15.24mm</footprint>
+      <datasheet>http://datasheets.chipdb.org/Intel/x86/808x/datashts/8088/231456-006.pdf</datasheet>
+      <libsource lib="MCU_Intel" part="8088_Min_Mode" description="8088 (minimum mode), 8-Bit HMOS Microprocessor, PDIP-40"/>
+      <sheetpath names="/Page4/" tstamps="/5F6217EE/"/>
+      <tstamp>5F7A8941</tstamp>
+    </comp>
+    <comp ref="C23">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page4/" tstamps="/5F6217EE/"/>
+      <tstamp>5FA1A7AD</tstamp>
+    </comp>
+    <comp ref="C24">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page4/" tstamps="/5F6217EE/"/>
+      <tstamp>5FA1EA71</tstamp>
+    </comp>
+    <comp ref="C22">
+      <value>4.7uF</value>
+      <footprint>Capacitor_SMD:C_0402_1005Metric</footprint>
+      <datasheet>~</datasheet>
+      <libsource lib="Device" part="C_Small" description="Unpolarized capacitor, small symbol"/>
+      <sheetpath names="/Page4/" tstamps="/5F6217EE/"/>
+      <tstamp>5FA22BDC</tstamp>
+    </comp>
+  </components>
+  <libparts>
+    <libpart lib="CY62148GN-45ZSXI" part="CY62148GN-45ZSXI">
+      <fields>
+        <field name="Reference">U</field>
+        <field name="Value">CY62148GN-45ZSXI</field>
+        <field name="Footprint">SOIC127P1176X120-32N</field>
+        <field name="Datasheet">Cypress Semiconductor</field>
+        <field name="Field4">SOIC127P1176X120-32N</field>
+      </fields>
+      <pins>
+        <pin num="1" name="A17" type="BiDi"/>
+        <pin num="2" name="A16" type="BiDi"/>
+        <pin num="3" name="A14" type="BiDi"/>
+        <pin num="4" name="A12" type="BiDi"/>
+        <pin num="5" name="A7" type="BiDi"/>
+        <pin num="6" name="A6" type="BiDi"/>
+        <pin num="7" name="A5" type="BiDi"/>
+        <pin num="8" name="A4" type="BiDi"/>
+        <pin num="9" name="A3" type="BiDi"/>
+        <pin num="10" name="A2" type="BiDi"/>
+        <pin num="11" name="A1" type="BiDi"/>
+        <pin num="12" name="A0" type="BiDi"/>
+        <pin num="13" name="D0" type="BiDi"/>
+        <pin num="14" name="D1" type="BiDi"/>
+        <pin num="15" name="D2" type="BiDi"/>
+        <pin num="16" name="GND" type="power_in"/>
+        <pin num="17" name="D3" type="BiDi"/>
+        <pin num="18" name="D4" type="BiDi"/>
+        <pin num="19" name="D5" type="BiDi"/>
+        <pin num="20" name="D6" type="BiDi"/>
+        <pin num="21" name="D7" type="BiDi"/>
+        <pin num="22" name="CE_N" type="BiDi"/>
+        <pin num="23" name="A10" type="BiDi"/>
+        <pin num="24" name="OE_N" type="BiDi"/>
+        <pin num="25" name="A11" type="BiDi"/>
+        <pin num="26" name="A9" type="BiDi"/>
+        <pin num="27" name="A8" type="BiDi"/>
+        <pin num="28" name="A13" type="BiDi"/>
+        <pin num="29" name="WE_N" type="BiDi"/>
+        <pin num="30" name="A18" type="BiDi"/>
+        <pin num="31" name="A15" type="BiDi"/>
+        <pin num="32" name="VCC" type="power_in"/>
+      </pins>
+    </libpart>
+    <libpart lib="Connector" part="Conn_01x06_Female">
+      <description>Generic connector, single row, 01x06, script generated (kicad-library-utils/schlib/autogen/connector/)</description>
+      <docs>~</docs>
+      <footprints>
+        <fp>Connector*:*_1x??_*</fp>
+      </footprints>
+      <fields>
+        <field name="Reference">J</field>
+        <field name="Value">Conn_01x06_Female</field>
+      </fields>
+      <pins>
+        <pin num="1" name="Pin_1" type="passive"/>
+        <pin num="2" name="Pin_2" type="passive"/>
+        <pin num="3" name="Pin_3" type="passive"/>
+        <pin num="4" name="Pin_4" type="passive"/>
+        <pin num="5" name="Pin_5" type="passive"/>
+        <pin num="6" name="Pin_6" type="passive"/>
+      </pins>
+    </libpart>
+    <libpart lib="Device" part="C_Small">
+      <description>Unpolarized capacitor, small symbol</description>
+      <docs>~</docs>
+      <footprints>
+        <fp>C_*</fp>
+      </footprints>
+      <fields>
+        <field name="Reference">C</field>
+        <field name="Value">C_Small</field>
+      </fields>
+      <pins>
+        <pin num="1" name="~" type="passive"/>
+        <pin num="2" name="~" type="passive"/>
+      </pins>
+    </libpart>
+    <libpart lib="Device" part="LED">
+      <description>Light emitting diode</description>
+      <docs>~</docs>
+      <footprints>
+        <fp>LED*</fp>
+        <fp>LED_SMD:*</fp>
+        <fp>LED_THT:*</fp>
+      </footprints>
+      <fields>
+        <field name="Reference">D</field>
+        <field name="Value">LED</field>
+      </fields>
+      <pins>
+        <pin num="1" name="K" type="passive"/>
+        <pin num="2" name="A" type="passive"/>
+      </pins>
+    </libpart>
+    <libpart lib="Device" part="R_US">
+      <description>Resistor, US symbol</description>
+      <docs>~</docs>
+      <footprints>
+        <fp>R_*</fp>
+      </footprints>
+      <fields>
+        <field name="Reference">R</field>
+        <field name="Value">R_US</field>
+      </fields>
+      <pins>
+        <pin num="1" name="~" type="passive"/>
+        <pin num="2" name="~" type="passive"/>
+      </pins>
+    </libpart>
+    <libpart lib="FPGA_Xilinx_Spartan6" part="XC6SLX9-TQG144">
+      <description>Spartan 6 LX 9 XC6SLX9-TQG144</description>
+      <fields>
+        <field name="Reference">U</field>
+        <field name="Value">XC6SLX9-TQG144</field>
+      </fields>
+      <pins>
+        <pin num="1" name="IO_L83N_VREF_3" type="BiDi"/>
+        <pin num="2" name="IO_L83P_3" type="BiDi"/>
+        <pin num="3" name="GND" type="power_in"/>
+        <pin num="4" name="VCCO_3" type="power_in"/>
+        <pin num="5" name="IO_L52N_3" type="BiDi"/>
+        <pin num="6" name="IO_L52P_3" type="BiDi"/>
+        <pin num="7" name="IO_L51N_3" type="BiDi"/>
+        <pin num="8" name="IO_L51P_3" type="BiDi"/>
+        <pin num="9" name="IO_L50N_3" type="BiDi"/>
+        <pin num="10" name="IO_L50P_3" type="BiDi"/>
+        <pin num="11" name="IO_L49N_3" type="BiDi"/>
+        <pin num="12" name="IO_L49P_3" type="BiDi"/>
+        <pin num="13" name="GND" type="power_in"/>
+        <pin num="14" name="IO_L44N_GCLK20_3" type="BiDi"/>
+        <pin num="15" name="IO_L44P_GCLK21_3" type="BiDi"/>
+        <pin num="16" name="IO_L43N_GCLK22_IRDY2_3" type="BiDi"/>
+        <pin num="17" name="IO_L43P_GCLK23_3" type="BiDi"/>
+        <pin num="18" name="VCCO_3" type="power_in"/>
+        <pin num="19" name="VCCINT" type="power_in"/>
+        <pin num="20" name="VCCAUX" type="power_in"/>
+        <pin num="21" name="IO_L42N_GCLK24_3" type="BiDi"/>
+        <pin num="22" name="IO_L42P_GCLK25_TRDY2_3" type="BiDi"/>
+        <pin num="23" name="IO_L41N_GCLK26_3" type="BiDi"/>
+        <pin num="24" name="IO_L41P_GCLK27_3" type="BiDi"/>
+        <pin num="25" name="GND" type="power_in"/>
+        <pin num="26" name="IO_L37N_3" type="BiDi"/>
+        <pin num="27" name="IO_L37P_3" type="BiDi"/>
+        <pin num="28" name="VCCINT" type="power_in"/>
+        <pin num="29" name="IO_L36N_3" type="BiDi"/>
+        <pin num="30" name="IO_L36P_3" type="BiDi"/>
+        <pin num="31" name="VCCO_3" type="power_in"/>
+        <pin num="32" name="IO_L2N_3" type="BiDi"/>
+        <pin num="33" name="IO_L2P_3" type="BiDi"/>
+        <pin num="34" name="IO_L1N_VREF_3" type="BiDi"/>
+        <pin num="35" name="IO_L1P_3" type="BiDi"/>
+        <pin num="36" name="VCCAUX" type="power_in"/>
+        <pin num="37" name="PROGRAM_B_2" type="BiDi"/>
+        <pin num="38" name="IO_L65N_CSO_B_2" type="BiDi"/>
+        <pin num="39" name="IO_L65P_INIT_B_2" type="BiDi"/>
+        <pin num="40" name="IO_L64N_D9_2" type="BiDi"/>
+        <pin num="41" name="IO_L64P_D8_2" type="BiDi"/>
+        <pin num="42" name="VCCO_2" type="power_in"/>
+        <pin num="43" name="IO_L62N_D6_2" type="BiDi"/>
+        <pin num="44" name="IO_L62P_D5_2" type="BiDi"/>
+        <pin num="45" name="IO_L49N_D4_2" type="BiDi"/>
+        <pin num="46" name="IO_L49P_D3_2" type="BiDi"/>
+        <pin num="47" name="IO_L48N_RDWR_B_VREF_2" type="BiDi"/>
+        <pin num="48" name="IO_L48P_D7_2" type="BiDi"/>
+        <pin num="49" name="GND" type="power_in"/>
+        <pin num="50" name="IO_L31N_GCLK30_D15_2" type="BiDi"/>
+        <pin num="51" name="IO_L31P_GCLK31_D14_2" type="BiDi"/>
+        <pin num="52" name="VCCINT" type="power_in"/>
+        <pin num="53" name="VCCAUX" type="power_in"/>
+        <pin num="54" name="GND" type="power_in"/>
+        <pin num="55" name="IO_L30N_GCLK0_USERCCLK_2" type="BiDi"/>
+        <pin num="56" name="IO_L30P_GCLK1_D13_2" type="BiDi"/>
+        <pin num="57" name="IO_L14N_D12_2" type="BiDi"/>
+        <pin num="58" name="IO_L14P_D11_2" type="BiDi"/>
+        <pin num="59" name="IO_L13N_D10_2" type="BiDi"/>
+        <pin num="60" name="IO_L13P_M1_2" type="BiDi"/>
+        <pin num="61" name="IO_L12N_D2_MISO3_2" type="BiDi"/>
+        <pin num="62" name="IO_L12P_D1_MISO2_2" type="BiDi"/>
+        <pin num="63" name="VCCO_2" type="power_in"/>
+        <pin num="64" name="IO_L3N_MOSI_CSI_B_MISO0_2" type="BiDi"/>
+        <pin num="65" name="IO_L3P_D0_DIN_MISO_MISO1_2" type="BiDi"/>
+        <pin num="66" name="IO_L2N_CMPMOSI_2" type="BiDi"/>
+        <pin num="67" name="IO_L2P_CMPCLK_2" type="BiDi"/>
+        <pin num="68" name="GND" type="power_in"/>
+        <pin num="69" name="IO_L1N_M0_CMPMISO_2" type="BiDi"/>
+        <pin num="70" name="IO_L1P_CCLK_2" type="BiDi"/>
+        <pin num="71" name="DONE_2" type="BiDi"/>
+        <pin num="72" name="CMPCS_B_2" type="BiDi"/>
+        <pin num="73" name="SUSPEND" type="BiDi"/>
+        <pin num="74" name="IO_L74N_DOUT_BUSY_1" type="BiDi"/>
+        <pin num="75" name="IO_L74P_AWAKE_1" type="BiDi"/>
+        <pin num="76" name="VCCO_1" type="power_in"/>
+        <pin num="77" name="GND" type="power_in"/>
+        <pin num="78" name="IO_L47N_1" type="BiDi"/>
+        <pin num="79" name="IO_L47P_1" type="BiDi"/>
+        <pin num="80" name="IO_L46N_1" type="BiDi"/>
+        <pin num="81" name="IO_L46P_1" type="BiDi"/>
+        <pin num="82" name="IO_L45N_1" type="BiDi"/>
+        <pin num="83" name="IO_L45P_1" type="BiDi"/>
+        <pin num="84" name="IO_L43N_GCLK4_1" type="BiDi"/>
+        <pin num="85" name="IO_L43P_GCLK5_1" type="BiDi"/>
+        <pin num="86" name="VCCO_1" type="power_in"/>
+        <pin num="87" name="IO_L42N_GCLK6_TRDY1_1" type="BiDi"/>
+        <pin num="88" name="IO_L42P_GCLK7_1" type="BiDi"/>
+        <pin num="89" name="VCCINT" type="power_in"/>
+        <pin num="90" name="VCCAUX" type="power_in"/>
+        <pin num="91" name="GND" type="power_in"/>
+        <pin num="92" name="IO_L41N_GCLK8_1" type="BiDi"/>
+        <pin num="93" name="IO_L41P_GCLK9_IRDY1_1" type="BiDi"/>
+        <pin num="94" name="IO_L40N_GCLK10_1" type="BiDi"/>
+        <pin num="95" name="IO_L40P_GCLK11_1" type="BiDi"/>
+        <pin num="96" name="GND" type="power_in"/>
+        <pin num="97" name="IO_L34N_1" type="BiDi"/>
+        <pin num="98" name="IO_L34P_1" type="BiDi"/>
+        <pin num="99" name="IO_L33N_1" type="BiDi"/>
+        <pin num="100" name="IO_L33P_1" type="BiDi"/>
+        <pin num="101" name="IO_L32N_1" type="BiDi"/>
+        <pin num="102" name="IO_L32P_1" type="BiDi"/>
+        <pin num="103" name="VCCO_1" type="power_in"/>
+        <pin num="104" name="IO_L1N_VREF_1" type="BiDi"/>
+        <pin num="105" name="IO_L1P_1" type="BiDi"/>
+        <pin num="106" name="TDO" type="BiDi"/>
+        <pin num="107" name="TMS" type="BiDi"/>
+        <pin num="108" name="GND" type="power_in"/>
+        <pin num="109" name="TCK" type="BiDi"/>
+        <pin num="110" name="TDI" type="BiDi"/>
+        <pin num="111" name="IO_L66N_SCP0_0" type="BiDi"/>
+        <pin num="112" name="IO_L66P_SCP1_0" type="BiDi"/>
+        <pin num="113" name="GND" type="power_in"/>
+        <pin num="114" name="IO_L65N_SCP2_0" type="BiDi"/>
+        <pin num="115" name="IO_L65P_SCP3_0" type="BiDi"/>
+        <pin num="116" name="IO_L64N_SCP4_0" type="BiDi"/>
+        <pin num="117" name="IO_L64P_SCP5_0" type="BiDi"/>
+        <pin num="118" name="IO_L63N_SCP6_0" type="BiDi"/>
+        <pin num="119" name="IO_L63P_SCP7_0" type="BiDi"/>
+        <pin num="120" name="IO_L62N_VREF_0" type="BiDi"/>
+        <pin num="121" name="IO_L62P_0" type="BiDi"/>
+        <pin num="122" name="VCCO_0" type="power_in"/>
+        <pin num="123" name="IO_L37N_GCLK12_0" type="BiDi"/>
+        <pin num="124" name="IO_L37P_GCLK13_0" type="BiDi"/>
+        <pin num="125" name="VCCO_0" type="power_in"/>
+        <pin num="126" name="IO_L36N_GCLK14_0" type="BiDi"/>
+        <pin num="127" name="IO_L36P_GCLK15_0" type="BiDi"/>
+        <pin num="128" name="VCCINT" type="power_in"/>
+        <pin num="129" name="VCCAUX" type="power_in"/>
+        <pin num="130" name="GND" type="power_in"/>
+        <pin num="131" name="IO_L35N_GCLK16_0" type="BiDi"/>
+        <pin num="132" name="IO_L35P_GCLK17_0" type="BiDi"/>
+        <pin num="133" name="IO_L34N_GCLK18_0" type="BiDi"/>
+        <pin num="134" name="IO_L34P_GCLK19_0" type="BiDi"/>
+        <pin num="135" name="VCCO_0" type="power_in"/>
+        <pin num="136" name="GND" type="power_in"/>
+        <pin num="137" name="IO_L4N_0" type="BiDi"/>
+        <pin num="138" name="IO_L4P_0" type="BiDi"/>
+        <pin num="139" name="IO_L3N_0" type="BiDi"/>
+        <pin num="140" name="IO_L3P_0" type="BiDi"/>
+        <pin num="141" name="IO_L2N_0" type="BiDi"/>
+        <pin num="142" name="IO_L2P_0" type="BiDi"/>
+        <pin num="143" name="IO_L1N_VREF_0" type="BiDi"/>
+        <pin num="144" name="IO_L1P_HSWAPEN_0" type="BiDi"/>
+      </pins>
+    </libpart>
+    <libpart lib="MCU_Intel" part="8088">
+      <aliases>
+        <alias>8088_Min_Mode</alias>
+      </aliases>
+      <description>8088 (minimum mode), 8-Bit HMOS Microprocessor, PDIP-40</description>
+      <docs>http://datasheets.chipdb.org/Intel/x86/808x/datashts/8088/231456-006.pdf</docs>
+      <footprints>
+        <fp>DIP*W15.24mm*</fp>
+      </footprints>
+      <fields>
+        <field name="Reference">U</field>
+        <field name="Value">8088</field>
+        <field name="Footprint">Package_DIP:DIP-40_W15.24mm</field>
+      </fields>
+      <pins>
+        <pin num="1" name="GND" type="power_in"/>
+        <pin num="2" name="A14" type="output"/>
+        <pin num="3" name="A13" type="output"/>
+        <pin num="4" name="A12" type="output"/>
+        <pin num="5" name="A11" type="output"/>
+        <pin num="6" name="A10" type="output"/>
+        <pin num="7" name="A9" type="output"/>
+        <pin num="8" name="A8" type="output"/>
+        <pin num="9" name="AD7" type="BiDi"/>
+        <pin num="10" name="AD6" type="BiDi"/>
+        <pin num="11" name="AD5" type="BiDi"/>
+        <pin num="12" name="AD4" type="BiDi"/>
+        <pin num="13" name="AD3" type="BiDi"/>
+        <pin num="14" name="AD2" type="BiDi"/>
+        <pin num="15" name="AD1" type="BiDi"/>
+        <pin num="16" name="AD0" type="BiDi"/>
+        <pin num="17" name="NMI" type="input"/>
+        <pin num="18" name="INTR" type="input"/>
+        <pin num="19" name="CLK" type="input"/>
+        <pin num="20" name="GND" type="power_in"/>
+        <pin num="21" name="RESET" type="input"/>
+        <pin num="22" name="READY" type="input"/>
+        <pin num="23" name="~TEST~" type="input"/>
+        <pin num="24" name="~INTA~" type="output"/>
+        <pin num="25" name="ALE" type="output"/>
+        <pin num="26" name="DEN" type="output"/>
+        <pin num="27" name="DT/~R~" type="output"/>
+        <pin num="28" name="IO/~M~" type="output"/>
+        <pin num="29" name="WR" type="output"/>
+        <pin num="30" name="HLDA" type="output"/>
+        <pin num="31" name="HOLD" type="input"/>
+        <pin num="32" name="~RD~" type="output"/>
+        <pin num="33" name="MN/~MX~" type="input"/>
+        <pin num="34" name="~SSO~" type="output"/>
+        <pin num="35" name="A19/S6" type="output"/>
+        <pin num="36" name="A18/S5" type="output"/>
+        <pin num="37" name="A17/S4" type="output"/>
+        <pin num="38" name="A16/S3" type="output"/>
+        <pin num="39" name="A15" type="output"/>
+        <pin num="40" name="VCC" type="power_in"/>
+      </pins>
+    </libpart>
+    <libpart lib="MIC5504-1.2YM5-TR" part="MIC5504-1.2YM5-TR">
+      <fields>
+        <field name="Reference">U</field>
+        <field name="Value">MIC5504-1.2YM5-TR</field>
+        <field name="Footprint">SOT23-5P95_280X145XL45X37N</field>
+        <field name="Datasheet">MICREL</field>
+      </fields>
+      <pins>
+        <pin num="1" name="VIN" type="power_in"/>
+        <pin num="2" name="GND" type="power_in"/>
+        <pin num="3" name="EN" type="input"/>
+        <pin num="5" name="VOUT" type="output"/>
+      </pins>
+    </libpart>
+    <libpart lib="Memory_Flash" part="W25Q32JVSS">
+      <aliases>
+        <alias>W25Q128JVS</alias>
+      </aliases>
+      <description>32Mb Serial Flash Memory, Standard/Dual/Quad SPI, SOIC-8</description>
+      <docs>http://www.winbond.com/resource-files/w25q32jv%20revg%2003272018%20plus.pdf</docs>
+      <footprints>
+        <fp>SOIC*5.23x5.23mm*P1.27mm*</fp>
+      </footprints>
+      <fields>
+        <field name="Reference">U</field>
+        <field name="Value">W25Q32JVSS</field>
+        <field name="Footprint">Package_SO:SOIC-8_5.23x5.23mm_P1.27mm</field>
+      </fields>
+      <pins>
+        <pin num="1" name="~CS" type="input"/>
+        <pin num="2" name="DO(IO1)" type="BiDi"/>
+        <pin num="3" name="IO2" type="BiDi"/>
+        <pin num="4" name="GND" type="power_in"/>
+        <pin num="5" name="DI(IO0)" type="BiDi"/>
+        <pin num="6" name="CLK" type="input"/>
+        <pin num="7" name="IO3" type="BiDi"/>
+        <pin num="8" name="VCC" type="power_in"/>
+      </pins>
+    </libpart>
+    <libpart lib="SIT8008BI-13-33E-33.333330E" part="SIT8008BI-13-33E-33.333330E">
+      <fields>
+        <field name="Reference">Y</field>
+        <field name="Value">SIT8008BI-13-33E-33.333330E</field>
+        <field name="Footprint">OSC_SIT8008BI-13-33E-33.333330E</field>
+        <field name="Datasheet">Manufacturer Recommendations</field>
+        <field name="Field4">1.04</field>
+        <field name="Field5">0.8mm</field>
+        <field name="Field6">SiTime</field>
+      </fields>
+      <pins>
+        <pin num="1" name="OE" type="input"/>
+        <pin num="2" name="GND" type="power_in"/>
+        <pin num="3" name="OUT" type="output"/>
+        <pin num="4" name="VDD" type="power_in"/>
+      </pins>
+    </libpart>
+    <libpart lib="SN74LVC245APW" part="SN74LVC245APW">
+      <fields>
+        <field name="Reference">U</field>
+        <field name="Value">SN74LVC245APW</field>
+        <field name="Footprint">SOP65P640X120-20N</field>
+      </fields>
+      <pins>
+        <pin num="1" name="DIR" type="input"/>
+        <pin num="2" name="A1" type="BiDi"/>
+        <pin num="3" name="A2" type="BiDi"/>
+        <pin num="4" name="A3" type="BiDi"/>
+        <pin num="5" name="A4" type="BiDi"/>
+        <pin num="6" name="A5" type="BiDi"/>
+        <pin num="7" name="A6" type="BiDi"/>
+        <pin num="8" name="A7" type="BiDi"/>
+        <pin num="9" name="A8" type="BiDi"/>
+        <pin num="10" name="GND" type="power_in"/>
+        <pin num="11" name="B8" type="BiDi"/>
+        <pin num="12" name="B7" type="BiDi"/>
+        <pin num="13" name="B6" type="BiDi"/>
+        <pin num="14" name="B5" type="BiDi"/>
+        <pin num="15" name="B4" type="BiDi"/>
+        <pin num="16" name="B3" type="BiDi"/>
+        <pin num="17" name="B2" type="BiDi"/>
+        <pin num="18" name="B1" type="BiDi"/>
+        <pin num="19" name="~OE~" type="input"/>
+        <pin num="20" name="VCC" type="power_in"/>
+      </pins>
+    </libpart>
+  </libparts>
+  <libraries>
+    <library logical="CY62148GN-45ZSXI">
+      <uri>Z:\Ted\projs\KiCAD_Library\CY62148GN-45ZSXI\CY62148GN-45ZSXI.lib</uri>
+    </library>
+    <library logical="Connector">
+      <uri>C:\Program Files\KiCad\share\kicad\library/Connector.lib</uri>
+    </library>
+    <library logical="Device">
+      <uri>C:\Program Files\KiCad\share\kicad\library/Device.lib</uri>
+    </library>
+    <library logical="FPGA_Xilinx_Spartan6">
+      <uri>Z:/Ted/projs/KiCAD_Library/Xilinx_6_Series/FPGA_Xilinx_Spartan6.lib</uri>
+    </library>
+    <library logical="MCU_Intel">
+      <uri>C:\Program Files\KiCad\share\kicad\library/MCU_Intel.lib</uri>
+    </library>
+    <library logical="MIC5504-1.2YM5-TR">
+      <uri>Z:/Ted/projs/KiCAD_Library/MIC5504-1.2YM5-TR/MIC5504-1.2YM5-TR.lib</uri>
+    </library>
+    <library logical="Memory_Flash">
+      <uri>C:\Program Files\KiCad\share\kicad\library/Memory_Flash.lib</uri>
+    </library>
+    <library logical="SIT8008BI-13-33E-33.333330E">
+      <uri>Z:\Ted\projs\KiCAD_Library\SIT8008BI-13-33E-33.333330E\SIT8008BI-13-33E-33.333330E.lib</uri>
+    </library>
+    <library logical="SN74LVC245APW">
+      <uri>Z:/Ted/projs/KiCAD_Library/SN74LVC245APW/SN74LVC245APW.lib</uri>
+    </library>
+  </libraries>
+  <nets>
+    <net code="1" name="GND">
+      <node ref="U5" pin="1"/>
+      <node ref="U5" pin="10"/>
+      <node ref="C12" pin="2"/>
+      <node ref="U1" pin="68"/>
+      <node ref="U1" pin="130"/>
+      <node ref="U4" pin="19"/>
+      <node ref="C11" pin="2"/>
+      <node ref="U3" pin="2"/>
+      <node ref="U7" pin="2"/>
+      <node ref="U1" pin="73"/>
+      <node ref="U1" pin="136"/>
+      <node ref="C2" pin="2"/>
+      <node ref="U1" pin="113"/>
+      <node ref="U1" pin="108"/>
+      <node ref="U1" pin="96"/>
+      <node ref="U1" pin="91"/>
+      <node ref="R11" pin="1"/>
+      <node ref="U1" pin="77"/>
+      <node ref="C9" pin="2"/>
+      <node ref="C30" pin="2"/>
+      <node ref="C1" pin="2"/>
+      <node ref="C29" pin="2"/>
+      <node ref="U2" pin="4"/>
+      <node ref="C5" pin="2"/>
+      <node ref="J1" pin="6"/>
+      <node ref="C14" pin="2"/>
+      <node ref="C23" pin="2"/>
+      <node ref="C7" pin="2"/>
+      <node ref="C3" pin="2"/>
+      <node ref="C24" pin="2"/>
+      <node ref="C28" pin="2"/>
+      <node ref="U4" pin="10"/>
+      <node ref="U9" pin="20"/>
+      <node ref="U9" pin="1"/>
+      <node ref="C27" pin="2"/>
+      <node ref="C21" pin="2"/>
+      <node ref="U6" pin="10"/>
+      <node ref="C17" pin="2"/>
+      <node ref="C22" pin="2"/>
+      <node ref="C16" pin="2"/>
+      <node ref="U8" pin="16"/>
+      <node ref="C18" pin="2"/>
+      <node ref="U1" pin="54"/>
+      <node ref="C19" pin="2"/>
+      <node ref="Y1" pin="2"/>
+      <node ref="C15" pin="2"/>
+      <node ref="C4" pin="2"/>
+      <node ref="U1" pin="25"/>
+      <node ref="U1" pin="13"/>
+      <node ref="U1" pin="3"/>
+      <node ref="C10" pin="2"/>
+      <node ref="C8" pin="2"/>
+      <node ref="C13" pin="2"/>
+      <node ref="U1" pin="49"/>
+      <node ref="C20" pin="2"/>
+      <node ref="C25" pin="2"/>
+      <node ref="C26" pin="2"/>
+      <node ref="C6" pin="2"/>
+    </net>
+    <net code="2" name="FPGA_PROGRAM_n">
+      <node ref="U1" pin="37"/>
+      <node ref="R13" pin="2"/>
+    </net>
+    <net code="3" name="+3V3">
+      <node ref="U2" pin="8"/>
+      <node ref="U2" pin="7"/>
+      <node ref="U1" pin="86"/>
+      <node ref="U7" pin="3"/>
+      <node ref="U1" pin="135"/>
+      <node ref="U1" pin="122"/>
+      <node ref="U1" pin="103"/>
+      <node ref="U1" pin="76"/>
+      <node ref="U2" pin="3"/>
+      <node ref="R2" pin="2"/>
+      <node ref="U1" pin="4"/>
+      <node ref="U1" pin="18"/>
+      <node ref="U1" pin="31"/>
+      <node ref="C10" pin="1"/>
+      <node ref="U1" pin="42"/>
+      <node ref="U1" pin="63"/>
+      <node ref="C17" pin="1"/>
+      <node ref="R5" pin="2"/>
+      <node ref="R6" pin="2"/>
+      <node ref="R7" pin="2"/>
+      <node ref="R8" pin="2"/>
+      <node ref="R9" pin="2"/>
+      <node ref="C20" pin="1"/>
+      <node ref="U1" pin="20"/>
+      <node ref="U1" pin="36"/>
+      <node ref="U1" pin="53"/>
+      <node ref="U1" pin="90"/>
+      <node ref="U1" pin="129"/>
+      <node ref="Y1" pin="4"/>
+      <node ref="U8" pin="32"/>
+      <node ref="C18" pin="1"/>
+      <node ref="R4" pin="2"/>
+      <node ref="R3" pin="2"/>
+      <node ref="C21" pin="1"/>
+      <node ref="C1" pin="1"/>
+      <node ref="C9" pin="1"/>
+      <node ref="C14" pin="1"/>
+      <node ref="C5" pin="1"/>
+      <node ref="Y1" pin="1"/>
+      <node ref="U7" pin="1"/>
+      <node ref="U3" pin="5"/>
+      <node ref="C3" pin="1"/>
+      <node ref="C2" pin="1"/>
+      <node ref="J1" pin="1"/>
+      <node ref="C29" pin="1"/>
+      <node ref="C30" pin="1"/>
+      <node ref="U4" pin="20"/>
+      <node ref="U4" pin="1"/>
+      <node ref="U5" pin="20"/>
+      <node ref="R10" pin="1"/>
+      <node ref="C7" pin="1"/>
+      <node ref="C24" pin="1"/>
+      <node ref="C23" pin="1"/>
+      <node ref="C8" pin="1"/>
+      <node ref="C22" pin="1"/>
+      <node ref="U6" pin="20"/>
+      <node ref="R12" pin="1"/>
+      <node ref="C27" pin="1"/>
+      <node ref="R13" pin="1"/>
+      <node ref="R14" pin="1"/>
+      <node ref="R15" pin="1"/>
+      <node ref="C6" pin="1"/>
+      <node ref="C4" pin="1"/>
+      <node ref="C26" pin="1"/>
+      <node ref="C25" pin="1"/>
+      <node ref="U1" pin="125"/>
+    </net>
+    <net code="4" name="FPGA_INIT">
+      <node ref="U1" pin="39"/>
+      <node ref="R14" pin="2"/>
+    </net>
+    <net code="5" name="FPGA_DONE">
+      <node ref="R12" pin="2"/>
+      <node ref="U1" pin="71"/>
+    </net>
+    <net code="6" name="A13_5V">
+      <node ref="U9" pin="3"/>
+      <node ref="U1" pin="1"/>
+    </net>
+    <net code="7" name="A15_5V">
+      <node ref="U1" pin="144"/>
+      <node ref="U9" pin="39"/>
+    </net>
+    <net code="8" name="A16_5V">
+      <node ref="U1" pin="2"/>
+      <node ref="U9" pin="38"/>
+    </net>
+    <net code="9" name="A12_5V">
+      <node ref="U1" pin="5"/>
+      <node ref="U9" pin="4"/>
+    </net>
+    <net code="10" name="A17_5V">
+      <node ref="U1" pin="6"/>
+      <node ref="U9" pin="37"/>
+    </net>
+    <net code="11" name="A11_5V">
+      <node ref="U1" pin="7"/>
+      <node ref="U9" pin="5"/>
+    </net>
+    <net code="12" name="A18_5V">
+      <node ref="U9" pin="36"/>
+      <node ref="U1" pin="8"/>
+    </net>
+    <net code="13" name="SPI_CLK">
+      <node ref="R16" pin="2"/>
+      <node ref="U2" pin="6"/>
+    </net>
+    <net code="14" name="SPI_DIN">
+      <node ref="U2" pin="5"/>
+      <node ref="U1" pin="64"/>
+    </net>
+    <net code="15" name="SPI_DOUT">
+      <node ref="U2" pin="2"/>
+      <node ref="U1" pin="65"/>
+    </net>
+    <net code="16" name="FPGA_M0">
+      <node ref="R10" pin="2"/>
+      <node ref="U1" pin="69"/>
+    </net>
+    <net code="17" name="FPGA_M1">
+      <node ref="U1" pin="60"/>
+      <node ref="R11" pin="2"/>
+    </net>
+    <net code="18" name="A10_5V">
+      <node ref="U9" pin="6"/>
+      <node ref="U1" pin="9"/>
+    </net>
+    <net code="19" name="LED1">
+      <node ref="U1" pin="112"/>
+      <node ref="D2" pin="1"/>
+    </net>
+    <net code="20" name="SRAM_A2">
+      <node ref="U8" pin="10"/>
+      <node ref="U1" pin="124"/>
+    </net>
+    <net code="21" name="SRAM_A1">
+      <node ref="U8" pin="11"/>
+      <node ref="U1" pin="126"/>
+    </net>
+    <net code="22" name="SRAM_A0">
+      <node ref="U1" pin="132"/>
+      <node ref="U8" pin="12"/>
+    </net>
+    <net code="23" name="SRAM_D0">
+      <node ref="U8" pin="13"/>
+      <node ref="U1" pin="119"/>
+    </net>
+    <net code="24" name="LED0">
+      <node ref="D1" pin="1"/>
+      <node ref="U1" pin="111"/>
+    </net>
+    <net code="25" name="SRAM_A3">
+      <node ref="U8" pin="9"/>
+      <node ref="U1" pin="123"/>
+    </net>
+    <net code="26" name="LED2">
+      <node ref="U1" pin="114"/>
+      <node ref="D3" pin="1"/>
+    </net>
+    <net code="27" name="LED3">
+      <node ref="U1" pin="116"/>
+      <node ref="D4" pin="1"/>
+    </net>
+    <net code="28" name="LED4">
+      <node ref="U1" pin="120"/>
+      <node ref="D5" pin="1"/>
+    </net>
+    <net code="29" name="LED5">
+      <node ref="U1" pin="121"/>
+      <node ref="D6" pin="1"/>
+    </net>
+    <net code="30" name="LED6">
+      <node ref="U1" pin="127"/>
+      <node ref="D7" pin="1"/>
+    </net>
+    <net code="31" name="SRAM_WE_n">
+      <node ref="U1" pin="98"/>
+      <node ref="U8" pin="29"/>
+    </net>
+    <net code="32" name="SRAM_OE_n">
+      <node ref="U1" pin="92"/>
+      <node ref="U8" pin="24"/>
+    </net>
+    <net code="33" name="SRAM_A11">
+      <node ref="U8" pin="25"/>
+      <node ref="U1" pin="93"/>
+    </net>
+    <net code="34" name="SRAM_A9">
+      <node ref="U8" pin="26"/>
+      <node ref="U1" pin="94"/>
+    </net>
+    <net code="35" name="SRAM_A8">
+      <node ref="U1" pin="95"/>
+      <node ref="U8" pin="27"/>
+    </net>
+    <net code="36" name="SRAM_A13">
+      <node ref="U1" pin="97"/>
+      <node ref="U8" pin="28"/>
+    </net>
+    <net code="37" name="LED7">
+      <node ref="D8" pin="1"/>
+      <node ref="U1" pin="131"/>
+    </net>
+    <net code="38" name="SRAM_A18">
+      <node ref="U8" pin="30"/>
+      <node ref="U1" pin="99"/>
+    </net>
+    <net code="39" name="SRAM_A15">
+      <node ref="U8" pin="31"/>
+      <node ref="U1" pin="100"/>
+    </net>
+    <net code="40" name="SRAM_D2">
+      <node ref="U1" pin="117"/>
+      <node ref="U8" pin="15"/>
+    </net>
+    <net code="41" name="SRAM_D1">
+      <node ref="U1" pin="118"/>
+      <node ref="U8" pin="14"/>
+    </net>
+    <net code="42" name="Net-(J1-Pad4)">
+      <node ref="J1" pin="4"/>
+      <node ref="U1" pin="107"/>
+    </net>
+    <net code="43" name="Net-(J1-Pad2)">
+      <node ref="J1" pin="2"/>
+      <node ref="U1" pin="110"/>
+    </net>
+    <net code="44" name="Net-(J1-Pad5)">
+      <node ref="J1" pin="5"/>
+      <node ref="U1" pin="106"/>
+    </net>
+    <net code="45" name="SRAM_A10">
+      <node ref="U8" pin="23"/>
+      <node ref="U1" pin="88"/>
+    </net>
+    <net code="46" name="Net-(J1-Pad3)">
+      <node ref="U1" pin="109"/>
+      <node ref="J1" pin="3"/>
+    </net>
+    <net code="47" name="A14_5V">
+      <node ref="U1" pin="143"/>
+      <node ref="U9" pin="2"/>
+    </net>
+    <net code="48" name="HOLD_3V">
+      <node ref="U1" pin="43"/>
+      <node ref="U4" pin="17"/>
+    </net>
+    <net code="49" name="AD3_3V">
+      <node ref="U1" pin="32"/>
+      <node ref="U6" pin="14"/>
+    </net>
+    <net code="50" name="AD2_3V">
+      <node ref="U1" pin="33"/>
+      <node ref="U6" pin="13"/>
+    </net>
+    <net code="51" name="AD1_3V">
+      <node ref="U6" pin="12"/>
+      <node ref="U1" pin="34"/>
+    </net>
+    <net code="52" name="AD0_3V">
+      <node ref="U6" pin="11"/>
+      <node ref="U1" pin="35"/>
+    </net>
+    <net code="53" name="HLDA_3V">
+      <node ref="U4" pin="2"/>
+      <node ref="U1" pin="40"/>
+    </net>
+    <net code="54" name="ALE_3V">
+      <node ref="U4" pin="9"/>
+      <node ref="U1" pin="41"/>
+    </net>
+    <net code="55" name="NMI_3V">
+      <node ref="U1" pin="44"/>
+      <node ref="U4" pin="16"/>
+    </net>
+    <net code="56" name="INTR_3V">
+      <node ref="U4" pin="15"/>
+      <node ref="U1" pin="45"/>
+    </net>
+    <net code="57" name="CLK_3V">
+      <node ref="U4" pin="14"/>
+      <node ref="U1" pin="46"/>
+    </net>
+    <net code="58" name="RESET_3V">
+      <node ref="U1" pin="47"/>
+      <node ref="U4" pin="13"/>
+    </net>
+    <net code="59" name="READY_3V">
+      <node ref="U1" pin="48"/>
+      <node ref="U4" pin="12"/>
+    </net>
+    <net code="60" name="BUF2_DIR">
+      <node ref="U6" pin="1"/>
+      <node ref="U1" pin="16"/>
+    </net>
+    <net code="61" name="A19_5V">
+      <node ref="U1" pin="10"/>
+      <node ref="U9" pin="35"/>
+    </net>
+    <net code="62" name="A9_5V">
+      <node ref="U1" pin="11"/>
+      <node ref="U9" pin="7"/>
+    </net>
+    <net code="63" name="SSO_5V">
+      <node ref="U1" pin="12"/>
+      <node ref="U9" pin="34"/>
+    </net>
+    <net code="64" name="A8_5V">
+      <node ref="U1" pin="14"/>
+      <node ref="U9" pin="8"/>
+    </net>
+    <net code="65" name="BUF2_OE__n">
+      <node ref="U1" pin="21"/>
+      <node ref="U6" pin="19"/>
+    </net>
+    <net code="66" name="AD7_3V">
+      <node ref="U1" pin="22"/>
+      <node ref="U6" pin="18"/>
+    </net>
+    <net code="67" name="AD6_3V">
+      <node ref="U1" pin="23"/>
+      <node ref="U6" pin="17"/>
+    </net>
+    <net code="68" name="AD5_3V">
+      <node ref="U1" pin="26"/>
+      <node ref="U6" pin="16"/>
+    </net>
+    <net code="69" name="AD4_3V">
+      <node ref="U1" pin="27"/>
+      <node ref="U6" pin="15"/>
+    </net>
+    <net code="70" name="SRAM_D4">
+      <node ref="U1" pin="81"/>
+      <node ref="U8" pin="18"/>
+    </net>
+    <net code="71" name="SRAM_A12">
+      <node ref="U1" pin="74"/>
+      <node ref="U8" pin="4"/>
+    </net>
+    <net code="72" name="SRAM_A14">
+      <node ref="U1" pin="75"/>
+      <node ref="U8" pin="3"/>
+    </net>
+    <net code="73" name="SRAM_A16">
+      <node ref="U1" pin="78"/>
+      <node ref="U8" pin="2"/>
+    </net>
+    <net code="74" name="SRAM_A17">
+      <node ref="U8" pin="1"/>
+      <node ref="U1" pin="79"/>
+    </net>
+    <net code="75" name="SRAM_D3">
+      <node ref="U1" pin="80"/>
+      <node ref="U8" pin="17"/>
+    </net>
+    <net code="76" name="SRAM_A7">
+      <node ref="U8" pin="5"/>
+      <node ref="U1" pin="67"/>
+    </net>
+    <net code="77" name="SRAM_D5">
+      <node ref="U1" pin="82"/>
+      <node ref="U8" pin="19"/>
+    </net>
+    <net code="78" name="SRAM_D6">
+      <node ref="U8" pin="20"/>
+      <node ref="U1" pin="83"/>
+    </net>
+    <net code="79" name="SRAM_D7">
+      <node ref="U1" pin="85"/>
+      <node ref="U8" pin="21"/>
+    </net>
+    <net code="80" name="SRAM_CE_n">
+      <node ref="U1" pin="87"/>
+      <node ref="U8" pin="22"/>
+    </net>
+    <net code="81" name="INTA_n_3V">
+      <node ref="U5" pin="18"/>
+      <node ref="U1" pin="58"/>
+    </net>
+    <net code="82" name="RD_3V">
+      <node ref="U1" pin="50"/>
+      <node ref="U5" pin="13"/>
+    </net>
+    <net code="83" name="WR_3V">
+      <node ref="U5" pin="14"/>
+      <node ref="U1" pin="51"/>
+    </net>
+    <net code="84" name="IOM_3V">
+      <node ref="U1" pin="55"/>
+      <node ref="U5" pin="15"/>
+    </net>
+    <net code="85" name="DTR_3V">
+      <node ref="U5" pin="16"/>
+      <node ref="U1" pin="56"/>
+    </net>
+    <net code="86" name="DEN_3V">
+      <node ref="U5" pin="17"/>
+      <node ref="U1" pin="57"/>
+    </net>
+    <net code="87" name="BUF1_OE__n">
+      <node ref="U1" pin="59"/>
+      <node ref="U5" pin="19"/>
+    </net>
+    <net code="88" name="SRAM_A4">
+      <node ref="U1" pin="61"/>
+      <node ref="U8" pin="8"/>
+    </net>
+    <net code="89" name="SRAM_A5">
+      <node ref="U1" pin="62"/>
+      <node ref="U8" pin="7"/>
+    </net>
+    <net code="90" name="SRAM_A6">
+      <node ref="U8" pin="6"/>
+      <node ref="U1" pin="66"/>
+    </net>
+    <net code="91" name="Net-(U1-Pad72)">
+      <node ref="U1" pin="72"/>
+    </net>
+    <net code="92" name="Net-(U1-Pad30)">
+      <node ref="U1" pin="30"/>
+    </net>
+    <net code="93" name="Net-(U1-Pad29)">
+      <node ref="U1" pin="29"/>
+    </net>
+    <net code="94" name="Net-(U1-Pad24)">
+      <node ref="U1" pin="24"/>
+    </net>
+    <net code="95" name="Net-(U1-Pad17)">
+      <node ref="U1" pin="17"/>
+    </net>
+    <net code="96" name="Net-(U1-Pad15)">
+      <node ref="U1" pin="15"/>
+    </net>
+    <net code="97" name="+1V2">
+      <node ref="C11" pin="1"/>
+      <node ref="C15" pin="1"/>
+      <node ref="C13" pin="1"/>
+      <node ref="C28" pin="1"/>
+      <node ref="C12" pin="1"/>
+      <node ref="U1" pin="128"/>
+      <node ref="U1" pin="89"/>
+      <node ref="U1" pin="52"/>
+      <node ref="U1" pin="28"/>
+      <node ref="U1" pin="19"/>
+      <node ref="U7" pin="5"/>
+      <node ref="C19" pin="1"/>
+    </net>
+    <net code="98" name="Net-(U1-Pad104)">
+      <node ref="U1" pin="104"/>
+    </net>
+    <net code="99" name="Net-(U1-Pad115)">
+      <node ref="U1" pin="115"/>
+    </net>
+    <net code="100" name="Net-(U1-Pad105)">
+      <node ref="U1" pin="105"/>
+    </net>
+    <net code="101" name="Net-(U1-Pad102)">
+      <node ref="U1" pin="102"/>
+    </net>
+    <net code="102" name="Net-(U1-Pad101)">
+      <node ref="U1" pin="101"/>
+    </net>
+    <net code="103" name="Net-(U1-Pad137)">
+      <node ref="U1" pin="137"/>
+    </net>
+    <net code="104" name="Net-(U1-Pad142)">
+      <node ref="U1" pin="142"/>
+    </net>
+    <net code="105" name="Net-(U1-Pad141)">
+      <node ref="U1" pin="141"/>
+    </net>
+    <net code="106" name="Net-(U1-Pad140)">
+      <node ref="U1" pin="140"/>
+    </net>
+    <net code="107" name="Net-(U1-Pad139)">
+      <node ref="U1" pin="139"/>
+    </net>
+    <net code="108" name="Net-(U1-Pad138)">
+      <node ref="U1" pin="138"/>
+    </net>
+    <net code="109" name="Net-(U1-Pad134)">
+      <node ref="U1" pin="134"/>
+    </net>
+    <net code="110" name="Net-(U1-Pad133)">
+      <node ref="U1" pin="133"/>
+    </net>
+    <net code="111" name="Net-(R16-Pad1)">
+      <node ref="R16" pin="1"/>
+      <node ref="U1" pin="70"/>
+    </net>
+    <net code="112" name="SPI_CS_n">
+      <node ref="U1" pin="38"/>
+      <node ref="U2" pin="1"/>
+      <node ref="R15" pin="2"/>
+    </net>
+    <net code="113" name="CLK_100MHZ">
+      <node ref="R1" pin="1"/>
+      <node ref="U1" pin="84"/>
+    </net>
+    <net code="114" name="Net-(R1-Pad2)">
+      <node ref="R1" pin="2"/>
+      <node ref="Y1" pin="3"/>
+    </net>
+    <net code="115" name="Net-(D8-Pad2)">
+      <node ref="R9" pin="1"/>
+      <node ref="D8" pin="2"/>
+    </net>
+    <net code="116" name="Net-(D7-Pad2)">
+      <node ref="R8" pin="1"/>
+      <node ref="D7" pin="2"/>
+    </net>
+    <net code="117" name="Net-(D6-Pad2)">
+      <node ref="D6" pin="2"/>
+      <node ref="R7" pin="1"/>
+    </net>
+    <net code="118" name="Net-(D5-Pad2)">
+      <node ref="R6" pin="1"/>
+      <node ref="D5" pin="2"/>
+    </net>
+    <net code="119" name="Net-(D4-Pad2)">
+      <node ref="D4" pin="2"/>
+      <node ref="R5" pin="1"/>
+    </net>
+    <net code="120" name="Net-(D2-Pad2)">
+      <node ref="D2" pin="2"/>
+      <node ref="R3" pin="1"/>
+    </net>
+    <net code="121" name="+5V">
+      <node ref="C16" pin="1"/>
+      <node ref="U3" pin="1"/>
+      <node ref="U3" pin="3"/>
+      <node ref="U9" pin="40"/>
+    </net>
+    <net code="122" name="Net-(D3-Pad2)">
+      <node ref="D3" pin="2"/>
+      <node ref="R4" pin="1"/>
+    </net>
+    <net code="123" name="Net-(D1-Pad2)">
+      <node ref="R2" pin="1"/>
+      <node ref="D1" pin="2"/>
+    </net>
+    <net code="124" name="AD4_5V">
+      <node ref="U9" pin="12"/>
+      <node ref="U6" pin="5"/>
+    </net>
+    <net code="125" name="AD2_5V">
+      <node ref="U6" pin="7"/>
+      <node ref="U9" pin="14"/>
+    </net>
+    <net code="126" name="AD1_5V">
+      <node ref="U6" pin="8"/>
+      <node ref="U9" pin="15"/>
+    </net>
+    <net code="127" name="AD0_5V">
+      <node ref="U9" pin="16"/>
+      <node ref="U6" pin="9"/>
+    </net>
+    <net code="128" name="NMI_5V">
+      <node ref="U4" pin="4"/>
+      <node ref="U9" pin="17"/>
+    </net>
+    <net code="129" name="INTR_5V">
+      <node ref="U4" pin="5"/>
+      <node ref="U9" pin="18"/>
+    </net>
+    <net code="130" name="CLK_5V">
+      <node ref="U9" pin="19"/>
+      <node ref="U4" pin="6"/>
+    </net>
+    <net code="131" name="MINMAX_5V">
+      <node ref="U9" pin="33"/>
+    </net>
+    <net code="132" name="TEST_5V">
+      <node ref="U9" pin="23"/>
+    </net>
+    <net code="133" name="HOLD_5V">
+      <node ref="U9" pin="31"/>
+      <node ref="U4" pin="3"/>
+    </net>
+    <net code="134" name="RD_5V">
+      <node ref="U9" pin="32"/>
+      <node ref="U5" pin="7"/>
+    </net>
+    <net code="135" name="RESET_5V">
+      <node ref="U9" pin="21"/>
+      <node ref="U4" pin="7"/>
+    </net>
+    <net code="136" name="WR_5V">
+      <node ref="U5" pin="6"/>
+      <node ref="U9" pin="29"/>
+    </net>
+    <net code="137" name="IOM_5V">
+      <node ref="U5" pin="5"/>
+      <node ref="U9" pin="28"/>
+    </net>
+    <net code="138" name="DTR_5V">
+      <node ref="U5" pin="4"/>
+      <node ref="U9" pin="27"/>
+    </net>
+    <net code="139" name="INTA_n_5V">
+      <node ref="U5" pin="2"/>
+      <node ref="U9" pin="24"/>
+    </net>
+    <net code="140" name="READY_5V">
+      <node ref="U4" pin="8"/>
+      <node ref="U9" pin="22"/>
+    </net>
+    <net code="141" name="HLDA_5V">
+      <node ref="U4" pin="18"/>
+      <node ref="U9" pin="30"/>
+    </net>
+    <net code="142" name="DEN_5V">
+      <node ref="U5" pin="3"/>
+      <node ref="U9" pin="26"/>
+    </net>
+    <net code="143" name="AD6_5V">
+      <node ref="U6" pin="3"/>
+      <node ref="U9" pin="10"/>
+    </net>
+    <net code="144" name="AD7_5V">
+      <node ref="U9" pin="9"/>
+      <node ref="U6" pin="2"/>
+    </net>
+    <net code="145" name="Net-(U5-Pad11)">
+      <node ref="U5" pin="11"/>
+    </net>
+    <net code="146" name="Net-(U5-Pad12)">
+      <node ref="U5" pin="12"/>
+    </net>
+    <net code="147" name="Net-(U5-Pad9)">
+      <node ref="U5" pin="9"/>
+    </net>
+    <net code="148" name="Net-(U5-Pad8)">
+      <node ref="U5" pin="8"/>
+    </net>
+    <net code="149" name="AD5_5V">
+      <node ref="U6" pin="4"/>
+      <node ref="U9" pin="11"/>
+    </net>
+    <net code="150" name="ALE_5V">
+      <node ref="U4" pin="11"/>
+      <node ref="U9" pin="25"/>
+    </net>
+    <net code="151" name="AD3_5V">
+      <node ref="U9" pin="13"/>
+      <node ref="U6" pin="6"/>
+    </net>
+  </nets>
+</export>
diff --git a/MCL86jr/PCBA/Page1.sch b/MCL86jr/PCBA/Page1.sch
new file mode 100644
index 0000000..42de2f3
--- /dev/null
+++ b/MCL86jr/PCBA/Page1.sch
@@ -0,0 +1,1868 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr B 17000 11000
+encoding utf-8
+Sheet 2 4
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
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+F 1 "XC6SLX9-TQG144" H 4400 1084 50  0000 C CNN
+F 2 "Package_QFP:TQFP-144_20x20mm_P0.5mm" H 4400 2950 50  0001 C CNN
+F 3 "" H 4400 2950 50  0000 C CNN
+	1    4400 2950
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 2 1 5F646C50
+P 11450 2950
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+F 1 "XC6SLX9-TQG144" H 11450 1084 50  0000 C CNN
+F 2 "Package_QFP:TQFP-144_20x20mm_P0.5mm" H 11450 2950 50  0001 C CNN
+F 3 "" H 11450 2950 50  0000 C CNN
+	2    11450 2950
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 3 1 5F648E2A
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+F 1 "XC6SLX9-TQG144" H 2632 7326 50  0000 C CNN
+F 2 "Package_QFP:TQFP-144_20x20mm_P0.5mm" H 2500 6650 50  0001 C CNN
+F 3 "" H 2500 6650 50  0000 C CNN
+	3    2500 6650
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+$EndComp
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 9350 7150
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+Wire Wire Line
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+Connection ~ 9350 7050
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+Wire Wire Line
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+	1    11750 7500
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+	1    9350 5950
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+	1    11750 5950
+	1    0    0    -1  
+$EndComp
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+Text GLabel 4250 6750 2    50   Input ~ 0
+FPGA_PROGRAM_n
+$Comp
+L power:+3.3V #PWR0105
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+	1    2550 1000
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+Connection ~ 2800 1000
+Wire Wire Line
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+F 3 "" H 5550 1000 50  0001 C CNN
+	1    5550 1000
+	1    0    0    -1  
+$EndComp
+$Comp
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+F 3 "" H 9600 1000 50  0001 C CNN
+	1    9600 1000
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+Wire Wire Line
+	9850 1000 9600 1000
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 9850 1000
+$Comp
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+U 1 1 5F69F5B4
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+F 2 "" H 12600 1000 50  0001 C CNN
+F 3 "" H 12600 1000 50  0001 C CNN
+	1    12600 1000
+	1    0    0    -1  
+$EndComp
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+Wire Wire Line
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+Connection ~ 12850 1000
+Wire Wire Line
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+Wire Wire Line
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+	5800 1250 5800 1000
+Text GLabel 6750 3550 2    50   Input ~ 0
+CLK_100MHZ
+Wire Wire Line
+	6750 3550 6400 3550
+$Comp
+L power:+3.3V #PWR0130
+U 1 1 5F7803A9
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+F 3 "" H 5650 5900 50  0001 C CNN
+	1    5650 5900
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+Wire Wire Line
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+U 4 1 5F64A751
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+F 1 "XC6SLX9-TQG144" H 10550 7426 50  0000 C CNN
+F 2 "Package_QFP:TQFP-144_20x20mm_P0.5mm" H 10550 6650 50  0001 C CNN
+F 3 "" H 10550 6650 50  0000 C CNN
+	4    10550 6650
+	1    0    0    -1  
+$EndComp
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+F 2 "" H 9350 7500 50  0001 C CNN
+F 3 "" H 9350 7500 50  0001 C CNN
+	1    9350 7500
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+L power:GND #PWR0131
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+F 2 "" H 5650 6800 50  0001 C CNN
+F 3 "" H 5650 6800 50  0001 C CNN
+	1    5650 6800
+	1    0    0    -1  
+$EndComp
+$Comp
+L SIT8008BI-13-33E-33.333330E:SIT8008BI-13-33E-33.333330E Y?
+U 1 1 5F7DBEF0
+P 3350 9150
+AR Path="/5F602591/5F7DBEF0" Ref="Y?"  Part="1" 
+AR Path="/5F609430/5F7DBEF0" Ref="Y1"  Part="1" 
+F 0 "Y1" H 3350 9517 50  0000 C CNN
+F 1 "100Mhz" H 3350 9426 50  0000 C CNN
+F 2 "OSC_SIT8008BI-13-33E-33.333330E" H 3350 9150 50  0001 L BNN
+F 3 "Manufacturer Recommendations" H 3350 9150 50  0001 L BNN
+F 4 "1.04" H 3350 9150 50  0001 L BNN "Field4"
+F 5 "0.8mm" H 3350 9150 50  0001 L BNN "Field5"
+F 6 "SiTime" H 3350 9150 50  0001 L BNN "Field6"
+	1    3350 9150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4050 9250 3850 9250
+$Comp
+L power:+3.3V #PWR0109
+U 1 1 5F7DBEF7
+P 4050 8850
+AR Path="/5F609430/5F7DBEF7" Ref="#PWR0109"  Part="1" 
+AR Path="/5F602591/5F7DBEF7" Ref="#PWR?"  Part="1" 
+F 0 "#PWR0109" H 4050 8700 50  0001 C CNN
+F 1 "+3.3V" H 4065 9023 50  0000 C CNN
+F 2 "" H 4050 8850 50  0001 C CNN
+F 3 "" H 4050 8850 50  0001 C CNN
+	1    4050 8850
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3850 9050 4050 9050
+Wire Wire Line
+	4050 9050 4050 8850
+Text GLabel 4900 9150 2    50   Input ~ 0
+CLK_100MHZ
+$Comp
+L Device:R_US R?
+U 1 1 5F7DBF00
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+Wire Wire Line
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diff --git a/MCL86jr/PCBA/Page1.sch-bak b/MCL86jr/PCBA/Page1.sch-bak
new file mode 100644
index 0000000..7ae4382
--- /dev/null
+++ b/MCL86jr/PCBA/Page1.sch-bak
@@ -0,0 +1,1868 @@
+EESchema Schematic File Version 4
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+EELAYER END
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+encoding utf-8
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+AR Path="/5F609430/5F7DBEF0" Ref="Y1"  Part="1" 
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+	1    3350 9150
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+AR Path="/5F602591/5F7DBF00" Ref="R?"  Part="1" 
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+F 3 "~" H 4400 9150 50  0001 C CNN
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+AR Path="/5F609430/5FF1DF6E" Ref="#PWR0181"  Part="1" 
+AR Path="/5F602591/5FF1DF6E" Ref="#PWR?"  Part="1" 
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+F 3 "~" H 8100 1300 50  0001 C CNN
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+AR Path="/5F602591/5F76EDA5" Ref="J?"  Part="1" 
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+Wire Wire Line
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+AR Path="/5F602591/60E87B0C" Ref="#PWR?"  Part="1" 
+F 0 "#PWR0187" H 13000 6300 50  0001 C CNN
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new file mode 100644
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+F 3 "http://www.winbond.com/resource-files/w25q128jv_dtr%20revc%2003272018%20plus.pdf" H 9750 7500 50  0001 C CNN
+	1    9750 7500
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/MCL86jr/PCBA/Page3sch.sch b/MCL86jr/PCBA/Page3sch.sch
new file mode 100644
index 0000000..e4acce4
--- /dev/null
+++ b/MCL86jr/PCBA/Page3sch.sch
@@ -0,0 +1,893 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr B 17000 11000
+encoding utf-8
+Sheet 3 4
+Title ""
+Date ""
+Rev ""
+Comp ""
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+	1    10300 2200
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+$EndComp
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+	1    6650 2650
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+	1    10900 2650
+	-1   0    0    -1  
+$EndComp
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+AR Path="/5F609430/5F80130A" Ref="#PWR?"  Part="1" 
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+AR Path="/5F602591/5F801314" Ref="#PWR?"  Part="1" 
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+	1    11450 2000
+	1    0    0    -1  
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+	1    6700 1800
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+F 3 "~" H 12100 6300 50  0001 C CNN
+	1    12100 6300
+	-1   0    0    -1  
+$EndComp
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+AR Path="/5F602591/5F8CD1C0" Ref="R?"  Part="1" 
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+F 3 "~" H 11450 6300 50  0001 C CNN
+	1    11450 6300
+	0    1    1    0   
+$EndComp
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+Wire Wire Line
+	11950 6300 11600 6300
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+AR Path="/5F609430/5F8D1616" Ref="#PWR?"  Part="1" 
+AR Path="/5F602591/5F8D1616" Ref="#PWR?"  Part="1" 
+AR Path="/5F62178D/5F8D1616" Ref="#PWR0135"  Part="1" 
+F 0 "#PWR0135" H 10900 5950 50  0001 C CNN
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+F 3 "" H 10900 6100 50  0001 C CNN
+	1    10900 6100
+	1    0    0    -1  
+$EndComp
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+Text GLabel 12700 6300 2    50   Input ~ 0
+LED0
+Wire Wire Line
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+U 1 1 5F8DC90D
+P 12100 6500
+F 0 "D2" H 11900 6550 50  0000 C CNN
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+F 3 "~" H 12100 6500 50  0001 C CNN
+	1    12100 6500
+	-1   0    0    -1  
+$EndComp
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+	11950 6500 11600 6500
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+	10900 6500 10900 6300
+Text GLabel 12700 6500 2    50   Input ~ 0
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+P 12100 6700
+F 0 "D3" H 11900 6750 50  0000 C CNN
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+F 3 "~" H 12100 6700 50  0001 C CNN
+	1    12100 6700
+	-1   0    0    -1  
+$EndComp
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+	1    12100 6900
+	-1   0    0    -1  
+$EndComp
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+	10900 6900 10900 6700
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+	1    12100 7100
+	-1   0    0    -1  
+$EndComp
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+LED4
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+	1    12100 7300
+	-1   0    0    -1  
+$EndComp
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+	11950 7300 11600 7300
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+	1    12100 7500
+	-1   0    0    -1  
+$EndComp
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+	11950 7500 11600 7500
+Wire Wire Line
+	10900 7500 10900 7300
+Text GLabel 12700 7500 2    50   Input ~ 0
+LED6
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+F 3 "~" H 12100 7700 50  0001 C CNN
+	1    12100 7700
+	-1   0    0    -1  
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+	11950 7700 11600 7700
+Wire Wire Line
+	10900 7700 10900 7500
+Text GLabel 12700 7700 2    50   Input ~ 0
+LED7
+Wire Wire Line
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+Connection ~ 10900 6300
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+Connection ~ 10900 6700
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+Connection ~ 10900 7500
+$Comp
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+AR Path="/5F602591/5F9031C9" Ref="R?"  Part="1" 
+AR Path="/5F609430/5F9031C9" Ref="R?"  Part="1" 
+AR Path="/5F62178D/5F9031C9" Ref="R3"  Part="1" 
+F 0 "R3" V 11400 6700 50  0000 C CNN
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+F 3 "~" H 11450 6500 50  0001 C CNN
+	1    11450 6500
+	0    1    1    0   
+$EndComp
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+AR Path="/5F602591/5F905C0D" Ref="R?"  Part="1" 
+AR Path="/5F609430/5F905C0D" Ref="R?"  Part="1" 
+AR Path="/5F62178D/5F905C0D" Ref="R4"  Part="1" 
+F 0 "R4" V 11400 6900 50  0000 C CNN
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+F 3 "~" H 11450 6700 50  0001 C CNN
+	1    11450 6700
+	0    1    1    0   
+$EndComp
+$Comp
+L Device:R_US R?
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+P 11450 6900
+AR Path="/5F602591/5F905C13" Ref="R?"  Part="1" 
+AR Path="/5F609430/5F905C13" Ref="R?"  Part="1" 
+AR Path="/5F62178D/5F905C13" Ref="R5"  Part="1" 
+F 0 "R5" V 11400 7100 50  0000 C CNN
+F 1 "330" V 11400 6700 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" V 11337 6900 50  0001 C CNN
+F 3 "~" H 11450 6900 50  0001 C CNN
+	1    11450 6900
+	0    1    1    0   
+$EndComp
+$Comp
+L Device:R_US R?
+U 1 1 5F908B41
+P 11450 7100
+AR Path="/5F602591/5F908B41" Ref="R?"  Part="1" 
+AR Path="/5F609430/5F908B41" Ref="R?"  Part="1" 
+AR Path="/5F62178D/5F908B41" Ref="R6"  Part="1" 
+F 0 "R6" V 11400 7300 50  0000 C CNN
+F 1 "330" V 11400 6900 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" V 11337 7100 50  0001 C CNN
+F 3 "~" H 11450 7100 50  0001 C CNN
+	1    11450 7100
+	0    1    1    0   
+$EndComp
+$Comp
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+U 1 1 5F908B47
+P 11450 7300
+AR Path="/5F602591/5F908B47" Ref="R?"  Part="1" 
+AR Path="/5F609430/5F908B47" Ref="R?"  Part="1" 
+AR Path="/5F62178D/5F908B47" Ref="R7"  Part="1" 
+F 0 "R7" V 11400 7500 50  0000 C CNN
+F 1 "330" V 11400 7100 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" V 11337 7300 50  0001 C CNN
+F 3 "~" H 11450 7300 50  0001 C CNN
+	1    11450 7300
+	0    1    1    0   
+$EndComp
+$Comp
+L Device:R_US R?
+U 1 1 5F908B4D
+P 11450 7500
+AR Path="/5F602591/5F908B4D" Ref="R?"  Part="1" 
+AR Path="/5F609430/5F908B4D" Ref="R?"  Part="1" 
+AR Path="/5F62178D/5F908B4D" Ref="R8"  Part="1" 
+F 0 "R8" V 11400 7700 50  0000 C CNN
+F 1 "330" V 11400 7300 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" V 11337 7500 50  0001 C CNN
+F 3 "~" H 11450 7500 50  0001 C CNN
+	1    11450 7500
+	0    1    1    0   
+$EndComp
+$Comp
+L Device:R_US R?
+U 1 1 5F908B53
+P 11450 7700
+AR Path="/5F602591/5F908B53" Ref="R?"  Part="1" 
+AR Path="/5F609430/5F908B53" Ref="R?"  Part="1" 
+AR Path="/5F62178D/5F908B53" Ref="R9"  Part="1" 
+F 0 "R9" V 11400 7900 50  0000 C CNN
+F 1 "330" V 11400 7500 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" V 11337 7700 50  0001 C CNN
+F 3 "~" H 11450 7700 50  0001 C CNN
+	1    11450 7700
+	0    1    1    0   
+$EndComp
+$Comp
+L Device:C_Small C?
+U 1 1 5FA14AF8
+P 7450 5450
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diff --git a/MCL86jr/PCBA/Page3sch.sch-bak b/MCL86jr/PCBA/Page3sch.sch-bak
new file mode 100644
index 0000000..e4acce4
--- /dev/null
+++ b/MCL86jr/PCBA/Page3sch.sch-bak
@@ -0,0 +1,893 @@
+EESchema Schematic File Version 4
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+AR Path="/5F602591/5F8CD1C0" Ref="R?"  Part="1" 
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+AR Path="/5F602591/5F905C13" Ref="R?"  Part="1" 
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+	1    7200 2550
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+AR Path="/5F602591/5FADFFF6" Ref="#PWR?"  Part="1" 
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+	1    9350 2300
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+AR Path="/5F609430/5FADFFF0" Ref="C?"  Part="1" 
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+AR Path="/5F609430/5FADABE7" Ref="C?"  Part="1" 
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diff --git a/MCL86jr/PCBA/Page4.sch-bak b/MCL86jr/PCBA/Page4.sch-bak
new file mode 100644
index 0000000..f53d5ff
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@@ -0,0 +1,741 @@
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+F 0 "U?" H 5200 8267 50  0000 C CNN
+F 1 "XC6SLX9-TQG144" H 5200 8176 50  0000 C CNN
+F 2 "" H 5200 7400 50  0001 C CNN
+F 3 "" H 5200 7400 50  0000 C CNN
+	4    5200 7400
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/MCL86jr/PCBA/fp-info-cache b/MCL86jr/PCBA/fp-info-cache
new file mode 100644
index 0000000..36b9192
--- /dev/null
+++ b/MCL86jr/PCBA/fp-info-cache
@@ -0,0 +1,75328 @@
+16953823848835720
+74LCX16245MTD
+SOP50P810X120-48N
+
+
+0
+48
+48
+0805J0630101JCT
+CAPC2012X130N
+
+
+0
+2
+2
+281740-6
+TE_281740-6
+
+
+0
+12
+12
+Battery
+BatteryHolder_Bulgin_BX0036_1xC
+Bulgin Battery Holder, BX0036, Battery Type C (https://www.bulgin.com/products/pub/media/bulgin/data/Battery_holders.pdf)
+Bulgin BX0036
+0
+2
+2
+Battery
+BatteryHolder_ComfortableElectronic_CH273-2450_1x2450
+Comfortable Electronic CR2450 battery holder, http://www.comf.com.tw/ProductDetail.asp?no=148
+Comfortable Electronic CR2450
+0
+2
+2
+Battery
+BatteryHolder_Eagle_12BH611-GR
+https://eu.mouser.com/datasheet/2/209/EPD-200766-1274481.pdf
+9V Battery Holder
+0
+2
+2
+Battery
+BatteryHolder_Keystone_103_1x20mm
+http://www.keyelco.com/product-pdf.cfm?p=719
+Keystone type 103 battery holder
+0
+2
+2
+Battery
+BatteryHolder_Keystone_104_1x23mm
+http://www.keyelco.com/product-pdf.cfm?p=744
+Keystone type 104 battery holder
+0
+2
+2
+Battery
+BatteryHolder_Keystone_105_1x2430
+http://www.keyelco.com/product-pdf.cfm?p=745
+Keystone type 105 battery holder
+0
+2
+2
+Battery
+BatteryHolder_Keystone_106_1x20mm
+http://www.keyelco.com/product-pdf.cfm?p=720
+Keystone type 106 battery holder
+0
+2
+2
+Battery
+BatteryHolder_Keystone_107_1x23mm
+http://www.keyelco.com/product-pdf.cfm?p=746
+Keystone type 107 battery holder
+0
+2
+2
+Battery
+BatteryHolder_Keystone_500
+Keystone #500, CR1220 battery holder, http://www.keyelco.com/product-pdf.cfm?p=710
+CR1220 battery holder
+0
+2
+2
+Battery
+BatteryHolder_Keystone_1042_1x18650
+Battery holder for 18650 cylindrical cells http://www.keyelco.com/product.cfm/product_id/918
+18650 Keystone 1042 Li-ion
+0
+2
+2
+Battery
+BatteryHolder_Keystone_1058_1x2032
+http://www.keyelco.com/product-pdf.cfm?p=14028
+Keystone type 1058 coin cell retainer
+0
+2
+2
+Battery
+BatteryHolder_Keystone_1060_1x2032
+http://www.keyelco.com/product-pdf.cfm?p=726
+CR2032 BR2032 BatteryHolder Battery
+0
+2
+2
+Battery
+BatteryHolder_Keystone_2460_1xAA
+https://www.keyelco.com/product-pdf.cfm?p=1025
+AA battery cell holder
+0
+2
+2
+Battery
+BatteryHolder_Keystone_2462_2xAA
+2xAA cell battery holder, Keystone P/N 2462, https://www.keyelco.com/product-pdf.cfm?p=1027
+AA battery cell holder
+0
+2
+2
+Battery
+BatteryHolder_Keystone_2466_1xAAA
+1xAAA Battery Holder, Keystone, Plastic Case, http://www.keyelco.com/product-pdf.cfm?p=1031
+AAA battery holder Keystone
+0
+2
+2
+Battery
+BatteryHolder_Keystone_2468_2xAAA
+2xAAA cell battery holder, Keystone P/N 2468, http://www.keyelco.com/product-pdf.cfm?p=1033
+AAA battery cell holder
+0
+2
+2
+Battery
+BatteryHolder_Keystone_2479_3xAAA
+3xAAA cell battery holder, Keystone P/N 2479, http://www.keyelco.com/product-pdf.cfm?p=1041
+AAA battery cell holder
+0
+2
+2
+Battery
+BatteryHolder_Keystone_2993
+http://www.keyelco.com/product-pdf.cfm?p=776
+Keystone type 2993 negative battery contact
+0
+1
+1
+Battery
+BatteryHolder_Keystone_3000_1x12mm
+http://www.keyelco.com/product-pdf.cfm?p=777
+Keystone type 3000 coin cell retainer
+0
+3
+2
+Battery
+BatteryHolder_Keystone_3001_1x12mm
+http://www.keyelco.com/product-pdf.cfm?p=778
+Keystone type 3001 coin cell retainer
+0
+3
+2
+Battery
+BatteryHolder_Keystone_3002_1x2032
+https://www.tme.eu/it/Document/a823211ec201a9e209042d155fe22d2b/KEYS2996.pdf
+BR2016 CR2016 DL2016 BR2020 CL2020 BR2025 CR2025 DL2025 DR2032 CR2032 DL2032
+0
+3
+2
+Battery
+BatteryHolder_Keystone_3008_1x2450
+http://www.keyelco.com/product-pdf.cfm?p=786
+Keystone type 3008 coin cell retainer
+0
+3
+2
+Battery
+BatteryHolder_Keystone_3009_1x2450
+http://www.keyelco.com/product-pdf.cfm?p=787
+Keystone type 3009 coin cell retainer
+0
+3
+2
+Battery
+BatteryHolder_Keystone_3034_1x20mm
+Keystone 3034 SMD battery holder for 2020, 2025 and 2032 coincell batteries. http://www.keyelco.com/product-pdf.cfm?p=798
+Keystone type 3034 coin cell retainer
+0
+3
+2
+Battery
+BatteryHolder_LINX_BAT-HLD-012-SMT
+SMT battery holder for CR1216/1220/1225, https://linxtechnologies.com/wp/wp-content/uploads/bat-hld-012-smt.pdf
+battery holder coin cell cr1216 cr1220 cr1225
+0
+3
+2
+Battery
+BatteryHolder_MPD_BC2AAPC_2xAA
+2xAA cell battery holder, Memory Protection Devices P/N BC2AAPC, http://www.memoryprotectiondevices.com/datasheets/BC2AAPC-datasheet.pdf
+AA battery cell holder
+0
+2
+2
+Battery
+BatteryHolder_MPD_BC12AAPC_2xAA
+2xAA cell battery holder, Memory Protection Devices P/N BC12AAPC, http://www.memoryprotectiondevices.com/datasheets/BC12AAPC-datasheet.pdf
+AA battery cell holder
+0
+2
+2
+Battery
+BatteryHolder_MPD_BC2003_1x2032
+http://www.memoryprotectiondevices.com/datasheets/BC-2003-datasheet.pdf
+BC2003 CR2032 2032 Battery Holder
+0
+3
+2
+Battery
+BatteryHolder_MPD_BH-18650-PC2
+18650 Battery Holder (http://www.memoryprotectiondevices.com/datasheets/BK-18650-PC2-datasheet.pdf)
+18650 Battery Holder
+0
+2
+2
+Battery
+BatteryHolder_Seiko_MS621F
+Seiko MS621F, https://www.sii.co.jp/en/me/files/2014/02/file_EXTENDED_PRDCT_SPEC_75_FILE_11.jpg
+Seiko MS621F
+0
+2
+2
+Battery
+BatteryHolder_TruPower_BH-331P_3xAA
+Keystone Battery Holder BH-331P Battery Type 3xAA (Script generated with StandardBox.py) (Keystone Battery Holder BH-331P Battery Type 3xAA)
+Battery Holder BH-331P Battery Type 3xAA
+0
+2
+2
+Battery
+Battery_CR1225
+CR1225 battery
+battery CR1225 coin cell
+0
+0
+0
+Battery
+Battery_Panasonic_CR1025-VSK_Vertical_CircularHoles
+Panasonic CR-1025/VSK battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf
+battery CR-1025 coin cell vertical
+0
+2
+2
+Battery
+Battery_Panasonic_CR1220-VCN_Vertical_CircularHoles
+Panasonic CR-1220/VCN battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf
+battery CR-1220 coin cell vertical
+0
+2
+2
+Battery
+Battery_Panasonic_CR1632-V1AN_Vertical_CircularHoles
+Panasonic CR-1632-V1AN battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf
+battery CR-1632 coin cell vertical
+0
+2
+2
+Battery
+Battery_Panasonic_CR2025-V1AK_Vertical_CircularHoles
+Panasonic CR-2025/V1AK battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf
+battery CR-2025 coin cell vertical
+0
+2
+2
+Battery
+Battery_Panasonic_CR2032-VS1N_Vertical_CircularHoles
+Panasonic CR-2032/VS1N battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf
+battery CR-2032 coin cell vertical
+0
+2
+2
+Battery
+Battery_Panasonic_CR2354-VCN_Vertical_CircularHoles
+Panasonic CR-2354/VCN battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf
+battery CR-2354/VCN coin cell vertical
+0
+2
+2
+Battery
+Battery_Panasonic_CR2450-VAN_Vertical_CircularHoles
+Panasonic CR-2450/VAN battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf
+battery CR-2450 coin cell
+0
+2
+2
+Battery
+Battery_Panasonic_CR2477-VCN_Vertical_CircularHoles
+Panasonic CR-2477/VCN battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf
+battery CR-2477 coin cell vertical
+0
+2
+2
+Battery
+Battery_Panasonic_CR3032-VCN_Vertical_CircularHoles
+Panasonic CR-3032/VCN battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf
+battery CR-3032 coin cell vertical
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_1.00u_PCB
+Cherry MX keyswitch, 1.00u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch 1.00u PCB
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_1.00u_Plate
+Cherry MX keyswitch, 1.00u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch 1.00u plate
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_1.25u_PCB
+Cherry MX keyswitch, 1.25u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch 1.25u PCB
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_1.25u_Plate
+Cherry MX keyswitch, 1.25u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch 1.25u plate
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_1.50u_PCB
+Cherry MX keyswitch, 1.50u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch 1.50u PCB
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_1.50u_Plate
+Cherry MX keyswitch, 1.50u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch 1.50u plate
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_1.75u_PCB
+Cherry MX keyswitch, 1.75u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch 1.75u PCB
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_1.75u_Plate
+Cherry MX keyswitch, 1.75u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch 1.75u plate
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_2.00u_PCB
+Cherry MX keyswitch, 2.00u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch 2.00u PCB
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_2.00u_Plate
+Cherry MX keyswitch, 2.00u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch 2.00u plate
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_2.00u_Vertical_PCB
+Cherry MX keyswitch, 2.00u, vertical, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch 2.00u vertical PCB
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_2.00u_Vertical_Plate
+Cherry MX keyswitch, 2.00u, vertical, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch 2.00u vertical plate
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_2.25u_PCB
+Cherry MX keyswitch, 2.25u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch 2.25u PCB
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_2.25u_Plate
+Cherry MX keyswitch, 2.25u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch 2.25u plate
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_2.75u_PCB
+Cherry MX keyswitch, 2.75u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch 2.75u PCB
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_2.75u_Plate
+Cherry MX keyswitch, 2.75u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch 2.75u plate
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_6.25u_PCB
+Cherry MX keyswitch, 6.25u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch 6.25u PCB
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_6.25u_Plate
+Cherry MX keyswitch, 6.25u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch 6.25u plate
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_ISOEnter_PCB
+Cherry MX keyswitch, ISO Enter, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch ISO enter PCB
+0
+2
+2
+Button_Switch_Keyboard
+SW_Cherry_MX_ISOEnter_Plate
+Cherry MX keyswitch, ISO Enter, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf
+Cherry MX keyswitch ISO enter plate
+0
+2
+2
+Button_Switch_Keyboard
+SW_Matias_1.00u
+Matias/ALPS keyswitch, 1.00u, http://matias.ca/switches/
+Matias ALPS keyswitch 1.00u
+0
+2
+2
+Button_Switch_Keyboard
+SW_Matias_1.25u
+Matias/ALPS keyswitch, 1.25u, http://matias.ca/switches/
+Matias ALPS keyswitch 1.25u
+0
+2
+2
+Button_Switch_Keyboard
+SW_Matias_1.50u
+Matias/ALPS keyswitch, 1.50u, http://matias.ca/switches/
+Matias ALPS keyswitch 1.50u
+0
+2
+2
+Button_Switch_Keyboard
+SW_Matias_1.75u
+Matias/ALPS keyswitch, 1.75u, http://matias.ca/switches/
+Matias ALPS keyswitch 1.75u
+0
+2
+2
+Button_Switch_Keyboard
+SW_Matias_2.00u
+Matias/ALPS keyswitch, 2.00u, http://matias.ca/switches/
+Matias ALPS keyswitch 2.00u
+0
+2
+2
+Button_Switch_Keyboard
+SW_Matias_2.25u
+Matias/ALPS keyswitch, 2.25u, http://matias.ca/switches/
+Matias ALPS keyswitch 2.25u
+0
+2
+2
+Button_Switch_Keyboard
+SW_Matias_2.75u
+Matias/ALPS keyswitch, 2.75u, http://matias.ca/switches/
+Matias ALPS keyswitch 2.75u
+0
+2
+2
+Button_Switch_Keyboard
+SW_Matias_6.25u
+Matias/ALPS keyswitch, 6.25u, http://matias.ca/switches/
+Matias ALPS keyswitch 6.25u
+0
+2
+2
+Button_Switch_Keyboard
+SW_Matias_ISOEnter
+Matias/ALPS keyswitch, ISO Enter, http://matias.ca/switches/
+Matias ALPS keyswitch ISO enter
+0
+2
+2
+Button_Switch_SMD
+Nidec_Copal_SH-7010A
+4-bit rotary coded switch, J-hook, https://www.nidec-copal-electronics.com/e/catalog/switch/sh-7000.pdf
+rotary switch bcd
+0
+6
+5
+Button_Switch_SMD
+Nidec_Copal_SH-7010B
+4-bit rotary coded switch, gull wing, https://www.nidec-copal-electronics.com/e/catalog/switch/sh-7000.pdf
+rotary switch bcd
+0
+6
+5
+Button_Switch_SMD
+Nidec_Copal_SH-7040B
+4-bit rotary coded switch, gull wing, Gray code, https://www.nidec-copal-electronics.com/e/catalog/switch/sh-7000.pdf
+rotary switch bcd
+0
+5
+5
+Button_Switch_SMD
+Panasonic_EVQPUJ_EVQPUA
+http://industrial.panasonic.com/cdbs/www-data/pdf/ATV0000/ATV0000CE5.pdf
+SMD SMT SPST EVQPUJ EVQPUA
+0
+4
+2
+Button_Switch_SMD
+Panasonic_EVQPUK_EVQPUB
+http://industrial.panasonic.com/cdbs/www-data/pdf/ATV0000/ATV0000CE5.pdf
+SMD SMT SPST EVQPUK EVQPUB
+0
+4
+2
+Button_Switch_SMD
+Panasonic_EVQPUL_EVQPUC
+http://industrial.panasonic.com/cdbs/www-data/pdf/ATV0000/ATV0000CE5.pdf
+SMD SMT SPST EVQPUL EVQPUC
+0
+4
+2
+Button_Switch_SMD
+Panasonic_EVQPUM_EVQPUD
+http://industrial.panasonic.com/cdbs/www-data/pdf/ATV0000/ATV0000CE5.pdf
+SMD SMT SPST EVQPUM EVQPUD
+0
+4
+2
+Button_Switch_SMD
+SW_DIP_SPSTx01_Slide_6.7x4.1mm_W6.73mm_P2.54mm_LowProfile_JPin
+SMD 1x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x4.1mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin
+SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin
+0
+2
+2
+Button_Switch_SMD
+SW_DIP_SPSTx01_Slide_6.7x4.1mm_W8.61mm_P2.54mm_LowProfile
+SMD 1x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x4.1mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile
+0
+2
+2
+Button_Switch_SMD
+SW_DIP_SPSTx01_Slide_9.78x4.72mm_W8.61mm_P2.54mm
+SMD 1x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x4.72mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD
+0
+2
+2
+Button_Switch_SMD
+SW_DIP_SPSTx01_Slide_Copal_CHS-01A_W5.08mm_P1.27mm_JPin
+SMD 1x-dip-switch SPST Copal_CHS-01A, Slide, row spacing 5.08 mm (200 mils), body size  (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD, JPin
+SMD DIP Switch SPST Slide 5.08mm 200mil SMD JPin
+0
+2
+2
+Button_Switch_SMD
+SW_DIP_SPSTx01_Slide_Copal_CHS-01B_W7.62mm_P1.27mm
+SMD 1x-dip-switch SPST Copal_CHS-01B, Slide, row spacing 7.62 mm (300 mils), body size  (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD
+SMD DIP Switch SPST Slide 7.62mm 300mil SMD
+0
+2
+2
+Button_Switch_SMD
+SW_DIP_SPSTx01_Slide_Copal_CVS-01xB_W5.9mm_P1mm
+SMD 1x-dip-switch SPST Copal_CVS-01xB, Slide, row spacing 5.9 mm (232 mils), body size  (see http://www.nidec-copal-electronics.com/e/catalog/switch/cvs.pdf)
+SMD DIP Switch SPST Slide 5.9mm 232mil
+0
+6
+3
+Button_Switch_SMD
+SW_DIP_SPSTx01_Slide_Omron_A6S-110x_W8.9mm_P2.54mm
+SMD 1x-dip-switch SPST Omron_A6S-110x, Slide, row spacing 8.9 mm (350 mils), body size  (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf)
+SMD DIP Switch SPST Slide 8.9mm 350mil
+0
+2
+2
+Button_Switch_SMD
+SW_DIP_SPSTx02_Slide_6.7x6.64mm_W6.73mm_P2.54mm_LowProfile_JPin
+SMD 2x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x6.64mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin
+SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin
+0
+4
+4
+Button_Switch_SMD
+SW_DIP_SPSTx02_Slide_6.7x6.64mm_W8.61mm_P2.54mm_LowProfile
+SMD 2x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x6.64mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile
+0
+4
+4
+Button_Switch_SMD
+SW_DIP_SPSTx02_Slide_9.78x7.26mm_W8.61mm_P2.54mm
+SMD 2x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x7.26mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD
+0
+4
+4
+Button_Switch_SMD
+SW_DIP_SPSTx02_Slide_Copal_CHS-02A_W5.08mm_P1.27mm_JPin
+SMD 2x-dip-switch SPST Copal_CHS-02A, Slide, row spacing 5.08 mm (200 mils), body size  (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD, JPin
+SMD DIP Switch SPST Slide 5.08mm 200mil SMD JPin
+0
+4
+4
+Button_Switch_SMD
+SW_DIP_SPSTx02_Slide_Copal_CHS-02B_W7.62mm_P1.27mm
+SMD 2x-dip-switch SPST Copal_CHS-02B, Slide, row spacing 7.62 mm (300 mils), body size  (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD
+SMD DIP Switch SPST Slide 7.62mm 300mil SMD
+0
+4
+4
+Button_Switch_SMD
+SW_DIP_SPSTx02_Slide_Copal_CVS-02xB_W5.9mm_P1mm
+SMD 2x-dip-switch SPST Copal_CVS-02xB, Slide, row spacing 5.9 mm (232 mils), body size  (see http://www.nidec-copal-electronics.com/e/catalog/switch/cvs.pdf)
+SMD DIP Switch SPST Slide 5.9mm 232mil
+0
+8
+5
+Button_Switch_SMD
+SW_DIP_SPSTx02_Slide_KingTek_DSHP02TJ_W5.25mm_P1.27mm_JPin
+SMD 2x-dip-switch SPST KingTek_DSHP02TJ, Slide, row spacing 5.25 mm (206 mils), body size  (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin
+SMD DIP Switch SPST Slide 5.25mm 206mil JPin
+0
+4
+4
+Button_Switch_SMD
+SW_DIP_SPSTx02_Slide_KingTek_DSHP02TS_W7.62mm_P1.27mm
+SMD 2x-dip-switch SPST KingTek_DSHP02TS, Slide, row spacing 7.62 mm (300 mils), body size  (see http://www.kingtek.net.cn/pic/201601201417455112.pdf)
+SMD DIP Switch SPST Slide 7.62mm 300mil
+0
+4
+4
+Button_Switch_SMD
+SW_DIP_SPSTx02_Slide_Omron_A6H-2101_W6.15mm_P1.27mm
+SMD 2x-dip-switch SPST Omron_A6H-2101, Slide, row spacing 6.15 mm (242 mils), body size  (see https://www.omron.com/ecb/products/pdf/en-a6h.pdf)
+SMD DIP Switch SPST Slide 6.15mm 242mil
+0
+4
+4
+Button_Switch_SMD
+SW_DIP_SPSTx02_Slide_Omron_A6S-210x_W8.9mm_P2.54mm
+SMD 2x-dip-switch SPST Omron_A6S-210x, Slide, row spacing 8.9 mm (350 mils), body size  (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf)
+SMD DIP Switch SPST Slide 8.9mm 350mil
+0
+4
+4
+Button_Switch_SMD
+SW_DIP_SPSTx03_Slide_6.7x9.18mm_W6.73mm_P2.54mm_LowProfile_JPin
+SMD 3x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x9.18mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin
+SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin
+0
+6
+6
+Button_Switch_SMD
+SW_DIP_SPSTx03_Slide_6.7x9.18mm_W8.61mm_P2.54mm_LowProfile
+SMD 3x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x9.18mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile
+0
+6
+6
+Button_Switch_SMD
+SW_DIP_SPSTx03_Slide_9.78x9.8mm_W8.61mm_P2.54mm
+SMD 3x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x9.8mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD
+0
+6
+6
+Button_Switch_SMD
+SW_DIP_SPSTx03_Slide_Copal_CVS-03xB_W5.9mm_P1mm
+SMD 3x-dip-switch SPST Copal_CVS-03xB, Slide, row spacing 5.9 mm (232 mils), body size  (see http://www.nidec-copal-electronics.com/e/catalog/switch/cvs.pdf)
+SMD DIP Switch SPST Slide 5.9mm 232mil
+0
+10
+7
+Button_Switch_SMD
+SW_DIP_SPSTx03_Slide_KingTek_DSHP03TJ_W5.25mm_P1.27mm_JPin
+SMD 3x-dip-switch SPST KingTek_DSHP03TJ, Slide, row spacing 5.25 mm (206 mils), body size  (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin
+SMD DIP Switch SPST Slide 5.25mm 206mil JPin
+0
+6
+6
+Button_Switch_SMD
+SW_DIP_SPSTx03_Slide_KingTek_DSHP03TS_W7.62mm_P1.27mm
+SMD 3x-dip-switch SPST KingTek_DSHP03TS, Slide, row spacing 7.62 mm (300 mils), body size  (see http://www.kingtek.net.cn/pic/201601201417455112.pdf)
+SMD DIP Switch SPST Slide 7.62mm 300mil
+0
+6
+6
+Button_Switch_SMD
+SW_DIP_SPSTx03_Slide_Omron_A6S-310x_W8.9mm_P2.54mm
+SMD 3x-dip-switch SPST Omron_A6S-310x, Slide, row spacing 8.9 mm (350 mils), body size  (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf)
+SMD DIP Switch SPST Slide 8.9mm 350mil
+0
+6
+6
+Button_Switch_SMD
+SW_DIP_SPSTx04_Slide_6.7x11.72mm_W6.73mm_P2.54mm_LowProfile_JPin
+SMD 4x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x11.72mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin
+SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin
+0
+8
+8
+Button_Switch_SMD
+SW_DIP_SPSTx04_Slide_6.7x11.72mm_W8.61mm_P2.54mm_LowProfile
+SMD 4x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x11.72mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile
+0
+8
+8
+Button_Switch_SMD
+SW_DIP_SPSTx04_Slide_9.78x12.34mm_W8.61mm_P2.54mm
+SMD 4x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x12.34mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD
+0
+8
+8
+Button_Switch_SMD
+SW_DIP_SPSTx04_Slide_Copal_CHS-04A_W5.08mm_P1.27mm_JPin
+SMD 4x-dip-switch SPST Copal_CHS-04A, Slide, row spacing 5.08 mm (200 mils), body size  (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD, JPin
+SMD DIP Switch SPST Slide 5.08mm 200mil SMD JPin
+0
+8
+8
+Button_Switch_SMD
+SW_DIP_SPSTx04_Slide_Copal_CHS-04B_W7.62mm_P1.27mm
+SMD 4x-dip-switch SPST Copal_CHS-04B, Slide, row spacing 7.62 mm (300 mils), body size  (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD
+SMD DIP Switch SPST Slide 7.62mm 300mil SMD
+0
+8
+8
+Button_Switch_SMD
+SW_DIP_SPSTx04_Slide_Copal_CVS-04xB_W5.9mm_P1mm
+SMD 4x-dip-switch SPST Copal_CVS-04xB, Slide, row spacing 5.9 mm (232 mils), body size  (see http://www.nidec-copal-electronics.com/e/catalog/switch/cvs.pdf)
+SMD DIP Switch SPST Slide 5.9mm 232mil
+0
+12
+9
+Button_Switch_SMD
+SW_DIP_SPSTx04_Slide_KingTek_DSHP04TJ_W5.25mm_P1.27mm_JPin
+SMD 4x-dip-switch SPST KingTek_DSHP04TJ, Slide, row spacing 5.25 mm (206 mils), body size  (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin
+SMD DIP Switch SPST Slide 5.25mm 206mil JPin
+0
+8
+8
+Button_Switch_SMD
+SW_DIP_SPSTx04_Slide_KingTek_DSHP04TS_W7.62mm_P1.27mm
+SMD 4x-dip-switch SPST KingTek_DSHP04TS, Slide, row spacing 7.62 mm (300 mils), body size  (see http://www.kingtek.net.cn/pic/201601201417455112.pdf)
+SMD DIP Switch SPST Slide 7.62mm 300mil
+0
+8
+8
+Button_Switch_SMD
+SW_DIP_SPSTx04_Slide_Omron_A6H-4101_W6.15mm_P1.27mm
+SMD 4x-dip-switch SPST Omron_A6H-4101, Slide, row spacing 6.15 mm (242 mils), body size  (see https://www.omron.com/ecb/products/pdf/en-a6h.pdf)
+SMD DIP Switch SPST Slide 6.15mm 242mil
+0
+8
+8
+Button_Switch_SMD
+SW_DIP_SPSTx04_Slide_Omron_A6S-410x_W8.9mm_P2.54mm
+SMD 4x-dip-switch SPST Omron_A6S-410x, Slide, row spacing 8.9 mm (350 mils), body size  (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf)
+SMD DIP Switch SPST Slide 8.9mm 350mil
+0
+8
+8
+Button_Switch_SMD
+SW_DIP_SPSTx05_Slide_6.7x14.26mm_W6.73mm_P2.54mm_LowProfile_JPin
+SMD 5x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x14.26mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin
+SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin
+0
+10
+10
+Button_Switch_SMD
+SW_DIP_SPSTx05_Slide_6.7x14.26mm_W8.61mm_P2.54mm_LowProfile
+SMD 5x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x14.26mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile
+0
+10
+10
+Button_Switch_SMD
+SW_DIP_SPSTx05_Slide_9.78x14.88mm_W8.61mm_P2.54mm
+SMD 5x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x14.88mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD
+0
+10
+10
+Button_Switch_SMD
+SW_DIP_SPSTx05_Slide_KingTek_DSHP05TJ_W5.25mm_P1.27mm_JPin
+SMD 5x-dip-switch SPST KingTek_DSHP05TJ, Slide, row spacing 5.25 mm (206 mils), body size  (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin
+SMD DIP Switch SPST Slide 5.25mm 206mil JPin
+0
+10
+10
+Button_Switch_SMD
+SW_DIP_SPSTx05_Slide_KingTek_DSHP05TS_W7.62mm_P1.27mm
+SMD 5x-dip-switch SPST KingTek_DSHP05TS, Slide, row spacing 7.62 mm (300 mils), body size  (see http://www.kingtek.net.cn/pic/201601201417455112.pdf)
+SMD DIP Switch SPST Slide 7.62mm 300mil
+0
+10
+10
+Button_Switch_SMD
+SW_DIP_SPSTx05_Slide_Omron_A6S-510x_W8.9mm_P2.54mm
+SMD 5x-dip-switch SPST Omron_A6S-510x, Slide, row spacing 8.9 mm (350 mils), body size  (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf)
+SMD DIP Switch SPST Slide 8.9mm 350mil
+0
+10
+10
+Button_Switch_SMD
+SW_DIP_SPSTx06_Slide_6.7x16.8mm_W6.73mm_P2.54mm_LowProfile_JPin
+SMD 6x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x16.8mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin
+SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin
+0
+12
+12
+Button_Switch_SMD
+SW_DIP_SPSTx06_Slide_6.7x16.8mm_W8.61mm_P2.54mm_LowProfile
+SMD 6x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x16.8mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile
+0
+12
+12
+Button_Switch_SMD
+SW_DIP_SPSTx06_Slide_9.78x17.42mm_W8.61mm_P2.54mm
+SMD 6x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x17.42mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD
+0
+12
+12
+Button_Switch_SMD
+SW_DIP_SPSTx06_Slide_Copal_CHS-06A_W5.08mm_P1.27mm_JPin
+SMD 6x-dip-switch SPST Copal_CHS-06A, Slide, row spacing 5.08 mm (200 mils), body size  (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD, JPin
+SMD DIP Switch SPST Slide 5.08mm 200mil SMD JPin
+0
+12
+12
+Button_Switch_SMD
+SW_DIP_SPSTx06_Slide_Copal_CHS-06B_W7.62mm_P1.27mm
+SMD 6x-dip-switch SPST Copal_CHS-06B, Slide, row spacing 7.62 mm (300 mils), body size  (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD
+SMD DIP Switch SPST Slide 7.62mm 300mil SMD
+0
+12
+12
+Button_Switch_SMD
+SW_DIP_SPSTx06_Slide_KingTek_DSHP06TJ_W5.25mm_P1.27mm_JPin
+SMD 6x-dip-switch SPST KingTek_DSHP06TJ, Slide, row spacing 5.25 mm (206 mils), body size  (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin
+SMD DIP Switch SPST Slide 5.25mm 206mil JPin
+0
+12
+12
+Button_Switch_SMD
+SW_DIP_SPSTx06_Slide_KingTek_DSHP06TS_W7.62mm_P1.27mm
+SMD 6x-dip-switch SPST KingTek_DSHP06TS, Slide, row spacing 7.62 mm (300 mils), body size  (see http://www.kingtek.net.cn/pic/201601201417455112.pdf)
+SMD DIP Switch SPST Slide 7.62mm 300mil
+0
+12
+12
+Button_Switch_SMD
+SW_DIP_SPSTx06_Slide_Omron_A6H-6101_W6.15mm_P1.27mm
+SMD 6x-dip-switch SPST Omron_A6H-6101, Slide, row spacing 6.15 mm (242 mils), body size  (see https://www.omron.com/ecb/products/pdf/en-a6h.pdf)
+SMD DIP Switch SPST Slide 6.15mm 242mil
+0
+12
+12
+Button_Switch_SMD
+SW_DIP_SPSTx06_Slide_Omron_A6S-610x_W8.9mm_P2.54mm
+SMD 6x-dip-switch SPST Omron_A6S-610x, Slide, row spacing 8.9 mm (350 mils), body size  (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf)
+SMD DIP Switch SPST Slide 8.9mm 350mil
+0
+12
+12
+Button_Switch_SMD
+SW_DIP_SPSTx07_Slide_6.7x19.34mm_W6.73mm_P2.54mm_LowProfile_JPin
+SMD 7x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x19.34mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin
+SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin
+0
+14
+14
+Button_Switch_SMD
+SW_DIP_SPSTx07_Slide_6.7x19.34mm_W8.61mm_P2.54mm_LowProfile
+SMD 7x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x19.34mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile
+0
+14
+14
+Button_Switch_SMD
+SW_DIP_SPSTx07_Slide_9.78x19.96mm_W8.61mm_P2.54mm
+SMD 7x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x19.96mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD
+0
+14
+14
+Button_Switch_SMD
+SW_DIP_SPSTx07_Slide_KingTek_DSHP07TJ_W5.25mm_P1.27mm_JPin
+SMD 7x-dip-switch SPST KingTek_DSHP07TJ, Slide, row spacing 5.25 mm (206 mils), body size  (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin
+SMD DIP Switch SPST Slide 5.25mm 206mil JPin
+0
+14
+14
+Button_Switch_SMD
+SW_DIP_SPSTx07_Slide_KingTek_DSHP07TS_W7.62mm_P1.27mm
+SMD 7x-dip-switch SPST KingTek_DSHP07TS, Slide, row spacing 7.62 mm (300 mils), body size  (see http://www.kingtek.net.cn/pic/201601201417455112.pdf)
+SMD DIP Switch SPST Slide 7.62mm 300mil
+0
+14
+14
+Button_Switch_SMD
+SW_DIP_SPSTx07_Slide_Omron_A6S-710x_W8.9mm_P2.54mm
+SMD 7x-dip-switch SPST Omron_A6S-710x, Slide, row spacing 8.9 mm (350 mils), body size  (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf)
+SMD DIP Switch SPST Slide 8.9mm 350mil
+0
+14
+14
+Button_Switch_SMD
+SW_DIP_SPSTx08_Slide_6.7x21.88mm_W6.73mm_P2.54mm_LowProfile_JPin
+SMD 8x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x21.88mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin
+SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin
+0
+16
+16
+Button_Switch_SMD
+SW_DIP_SPSTx08_Slide_6.7x21.88mm_W8.61mm_P2.54mm_LowProfile
+SMD 8x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x21.88mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile
+0
+16
+16
+Button_Switch_SMD
+SW_DIP_SPSTx08_Slide_9.78x22.5mm_W8.61mm_P2.54mm
+SMD 8x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x22.5mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD
+0
+16
+16
+Button_Switch_SMD
+SW_DIP_SPSTx08_Slide_Copal_CHS-08A_W5.08mm_P1.27mm_JPin
+SMD 8x-dip-switch SPST Copal_CHS-08A, Slide, row spacing 5.08 mm (200 mils), body size  (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD, JPin
+SMD DIP Switch SPST Slide 5.08mm 200mil SMD JPin
+0
+16
+16
+Button_Switch_SMD
+SW_DIP_SPSTx08_Slide_Copal_CHS-08B_W7.62mm_P1.27mm
+SMD 8x-dip-switch SPST Copal_CHS-08B, Slide, row spacing 7.62 mm (300 mils), body size  (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD
+SMD DIP Switch SPST Slide 7.62mm 300mil SMD
+0
+16
+16
+Button_Switch_SMD
+SW_DIP_SPSTx08_Slide_Copal_CVS-08xB_W5.9mm_P1mm
+SMD 8x-dip-switch SPST Copal_CVS-08xB, Slide, row spacing 5.9 mm (232 mils), body size  (see http://www.nidec-copal-electronics.com/e/catalog/switch/cvs.pdf)
+SMD DIP Switch SPST Slide 5.9mm 232mil
+0
+20
+17
+Button_Switch_SMD
+SW_DIP_SPSTx08_Slide_KingTek_DSHP08TJ_W5.25mm_P1.27mm_JPin
+SMD 8x-dip-switch SPST KingTek_DSHP08TJ, Slide, row spacing 5.25 mm (206 mils), body size  (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin
+SMD DIP Switch SPST Slide 5.25mm 206mil JPin
+0
+16
+16
+Button_Switch_SMD
+SW_DIP_SPSTx08_Slide_KingTek_DSHP08TS_W7.62mm_P1.27mm
+SMD 8x-dip-switch SPST KingTek_DSHP08TS, Slide, row spacing 7.62 mm (300 mils), body size  (see http://www.kingtek.net.cn/pic/201601201417455112.pdf)
+SMD DIP Switch SPST Slide 7.62mm 300mil
+0
+16
+16
+Button_Switch_SMD
+SW_DIP_SPSTx08_Slide_Omron_A6H-8101_W6.15mm_P1.27mm
+SMD 8x-dip-switch SPST Omron_A6H-8101, Slide, row spacing 6.15 mm (242 mils), body size  (see https://www.omron.com/ecb/products/pdf/en-a6h.pdf)
+SMD DIP Switch SPST Slide 6.15mm 242mil
+0
+16
+16
+Button_Switch_SMD
+SW_DIP_SPSTx08_Slide_Omron_A6S-810x_W8.9mm_P2.54mm
+SMD 8x-dip-switch SPST Omron_A6S-810x, Slide, row spacing 8.9 mm (350 mils), body size  (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf)
+SMD DIP Switch SPST Slide 8.9mm 350mil
+0
+16
+16
+Button_Switch_SMD
+SW_DIP_SPSTx09_Slide_6.7x24.42mm_W6.73mm_P2.54mm_LowProfile_JPin
+SMD 9x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x24.42mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin
+SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin
+0
+18
+18
+Button_Switch_SMD
+SW_DIP_SPSTx09_Slide_6.7x24.42mm_W8.61mm_P2.54mm_LowProfile
+SMD 9x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x24.42mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile
+0
+18
+18
+Button_Switch_SMD
+SW_DIP_SPSTx09_Slide_9.78x25.04mm_W8.61mm_P2.54mm
+SMD 9x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x25.04mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD
+0
+18
+18
+Button_Switch_SMD
+SW_DIP_SPSTx09_Slide_KingTek_DSHP09TJ_W5.25mm_P1.27mm_JPin
+SMD 9x-dip-switch SPST KingTek_DSHP09TJ, Slide, row spacing 5.25 mm (206 mils), body size  (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin
+SMD DIP Switch SPST Slide 5.25mm 206mil JPin
+0
+18
+18
+Button_Switch_SMD
+SW_DIP_SPSTx09_Slide_KingTek_DSHP09TS_W7.62mm_P1.27mm
+SMD 9x-dip-switch SPST KingTek_DSHP09TS, Slide, row spacing 7.62 mm (300 mils), body size  (see http://www.kingtek.net.cn/pic/201601201417455112.pdf)
+SMD DIP Switch SPST Slide 7.62mm 300mil
+0
+18
+18
+Button_Switch_SMD
+SW_DIP_SPSTx09_Slide_Omron_A6S-910x_W8.9mm_P2.54mm
+SMD 9x-dip-switch SPST Omron_A6S-910x, Slide, row spacing 8.9 mm (350 mils), body size  (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf)
+SMD DIP Switch SPST Slide 8.9mm 350mil
+0
+18
+18
+Button_Switch_SMD
+SW_DIP_SPSTx10_Slide_6.7x26.96mm_W6.73mm_P2.54mm_LowProfile_JPin
+SMD 10x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x26.96mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin
+SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin
+0
+20
+20
+Button_Switch_SMD
+SW_DIP_SPSTx10_Slide_6.7x26.96mm_W8.61mm_P2.54mm_LowProfile
+SMD 10x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x26.96mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile
+0
+20
+20
+Button_Switch_SMD
+SW_DIP_SPSTx10_Slide_9.78x27.58mm_W8.61mm_P2.54mm
+SMD 10x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x27.58mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD
+0
+20
+20
+Button_Switch_SMD
+SW_DIP_SPSTx10_Slide_Copal_CHS-10A_W5.08mm_P1.27mm_JPin
+SMD 10x-dip-switch SPST Copal_CHS-10A, Slide, row spacing 5.08 mm (200 mils), body size  (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD, JPin
+SMD DIP Switch SPST Slide 5.08mm 200mil SMD JPin
+0
+20
+20
+Button_Switch_SMD
+SW_DIP_SPSTx10_Slide_Copal_CHS-10B_W7.62mm_P1.27mm
+SMD 10x-dip-switch SPST Copal_CHS-10B, Slide, row spacing 7.62 mm (300 mils), body size  (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD
+SMD DIP Switch SPST Slide 7.62mm 300mil SMD
+0
+20
+20
+Button_Switch_SMD
+SW_DIP_SPSTx10_Slide_KingTek_DSHP10TJ_W5.25mm_P1.27mm_JPin
+SMD 10x-dip-switch SPST KingTek_DSHP10TJ, Slide, row spacing 5.25 mm (206 mils), body size  (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin
+SMD DIP Switch SPST Slide 5.25mm 206mil JPin
+0
+20
+20
+Button_Switch_SMD
+SW_DIP_SPSTx10_Slide_KingTek_DSHP10TS_W7.62mm_P1.27mm
+SMD 10x-dip-switch SPST KingTek_DSHP10TS, Slide, row spacing 7.62 mm (300 mils), body size  (see http://www.kingtek.net.cn/pic/201601201417455112.pdf)
+SMD DIP Switch SPST Slide 7.62mm 300mil
+0
+20
+20
+Button_Switch_SMD
+SW_DIP_SPSTx10_Slide_Omron_A6H-10101_W6.15mm_P1.27mm
+SMD 10x-dip-switch SPST Omron_A6H-10101, Slide, row spacing 6.15 mm (242 mils), body size  (see https://www.omron.com/ecb/products/pdf/en-a6h.pdf)
+SMD DIP Switch SPST Slide 6.15mm 242mil
+0
+20
+20
+Button_Switch_SMD
+SW_DIP_SPSTx10_Slide_Omron_A6S-1010x_W8.9mm_P2.54mm
+SMD 10x-dip-switch SPST Omron_A6S-1010x, Slide, row spacing 8.9 mm (350 mils), body size  (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf)
+SMD DIP Switch SPST Slide 8.9mm 350mil
+0
+20
+20
+Button_Switch_SMD
+SW_DIP_SPSTx11_Slide_6.7x29.5mm_W6.73mm_P2.54mm_LowProfile_JPin
+SMD 11x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x29.5mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin
+SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin
+0
+22
+22
+Button_Switch_SMD
+SW_DIP_SPSTx11_Slide_6.7x29.5mm_W8.61mm_P2.54mm_LowProfile
+SMD 11x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x29.5mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile
+0
+22
+22
+Button_Switch_SMD
+SW_DIP_SPSTx11_Slide_9.78x30.12mm_W8.61mm_P2.54mm
+SMD 11x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x30.12mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD
+0
+22
+22
+Button_Switch_SMD
+SW_DIP_SPSTx12_Slide_6.7x32.04mm_W6.73mm_P2.54mm_LowProfile_JPin
+SMD 12x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x32.04mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin
+SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin
+0
+24
+24
+Button_Switch_SMD
+SW_DIP_SPSTx12_Slide_6.7x32.04mm_W8.61mm_P2.54mm_LowProfile
+SMD 12x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x32.04mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile
+0
+24
+24
+Button_Switch_SMD
+SW_DIP_SPSTx12_Slide_9.78x32.66mm_W8.61mm_P2.54mm
+SMD 12x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x32.66mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD
+SMD DIP Switch SPST Slide 8.61mm 338mil SMD
+0
+24
+24
+Button_Switch_SMD
+SW_MEC_5GSH9
+MEC 5G single pole normally-open tactile switch
+switch normally-open pushbutton push-button
+0
+4
+4
+Button_Switch_SMD
+SW_Push_1P1T-SH_NO_CK_KMR2xxG
+CK components KMR2 tactile switch with ground pin http://www.ckswitches.com/media/1479/kmr2.pdf
+tactile switch kmr2
+0
+5
+3
+Button_Switch_SMD
+SW_Push_1P1T_NO_6x6mm_H9.5mm
+tactile push button, 6x6mm e.g. PTS645xx series, height=9.5mm
+tact sw push 6mm smd
+0
+4
+2
+Button_Switch_SMD
+SW_Push_1P1T_NO_CK_KMR2
+CK components KMR2 tactile switch http://www.ckswitches.com/media/1479/kmr2.pdf
+tactile switch kmr2
+0
+4
+2
+Button_Switch_SMD
+SW_Push_1P1T_NO_CK_KSC6xxJ
+CK components KSC6 tactile switch https://www.ckswitches.com/media/1972/ksc6.pdf
+tactile switch ksc6
+0
+4
+2
+Button_Switch_SMD
+SW_Push_1P1T_NO_CK_KSC7xxJ
+CK components KSC7 tactile switch https://www.ckswitches.com/media/1973/ksc7.pdf
+tactile switch ksc7
+0
+4
+2
+Button_Switch_SMD
+SW_Push_1P1T_NO_CK_PTS125Sx43PSMTR
+C&K Switches 1P1T SMD PTS125 Series 12mm Tact Switch with Pegs, https://www.ckswitches.com/media/1462/pts125.pdf
+Button Tactile Switch SPST 1P1T
+0
+4
+2
+Button_Switch_SMD
+SW_Push_1P1T_NO_Vertical_Wuerth_434133025816
+https://katalog.we-online.com/em/datasheet/434133025816.pdf
+tactile switch Wurth Wuerth
+0
+4
+2
+Button_Switch_SMD
+SW_Push_SPST_NO_Alps_SKRK
+http://www.alps.com/prod/info/E/HTML/Tact/SurfaceMount/SKRK/SKRKAHE020.html
+SMD SMT button
+0
+2
+2
+Button_Switch_SMD
+SW_SP3T_PCM13
+Ultraminiature Surface Mount Slide Switch, right-angle, https://www.ckswitches.com/media/1424/pcm.pdf
+
+0
+8
+4
+Button_Switch_SMD
+SW_SPDT_CK-JS102011SAQN
+Sub-miniature slide switch, right-angle, http://www.ckswitches.com/media/1422/js.pdf
+switch spdt
+0
+3
+3
+Button_Switch_SMD
+SW_SPDT_PCM12
+Ultraminiature Surface Mount Slide Switch, right-angle, https://www.ckswitches.com/media/1424/pcm.pdf
+
+0
+7
+3
+Button_Switch_SMD
+SW_SPST_B3S-1000
+Surface Mount Tactile Switch for High-Density Packaging
+Tactile Switch
+0
+4
+2
+Button_Switch_SMD
+SW_SPST_B3S-1100
+Surface Mount Tactile Switch for High-Density Packaging with Ground Terminal
+Tactile Switch
+0
+5
+3
+Button_Switch_SMD
+SW_SPST_B3SL-1002P
+Middle Stroke Tactile Switch, B3SL
+Middle Stroke Tactile Switch
+0
+4
+2
+Button_Switch_SMD
+SW_SPST_B3SL-1022P
+Middle Stroke Tactile Switch, B3SL
+Middle Stroke Tactile Switch
+0
+4
+2
+Button_Switch_SMD
+SW_SPST_B3U-1000P
+Ultra-small-sized Tactile Switch with High Contact Reliability, Top-actuated Model, without Ground Terminal, without Boss
+Tactile Switch
+0
+2
+2
+Button_Switch_SMD
+SW_SPST_B3U-1000P-B
+Ultra-small-sized Tactile Switch with High Contact Reliability, Top-actuated Model, without Ground Terminal, with Boss
+Tactile Switch
+0
+2
+2
+Button_Switch_SMD
+SW_SPST_B3U-1100P
+Ultra-small-sized Tactile Switch with High Contact Reliability, Top-actuated Model, with Ground Terminal, without Boss
+Tactile Switch
+0
+3
+3
+Button_Switch_SMD
+SW_SPST_B3U-1100P-B
+Ultra-small-sized Tactile Switch with High Contact Reliability, Top-actuated Model, with Ground Terminal, with Boss
+Tactile Switch
+0
+3
+3
+Button_Switch_SMD
+SW_SPST_B3U-3000P
+Ultra-small-sized Tactile Switch with High Contact Reliability, Side-actuated Model, without Ground Terminal, without Boss
+Tactile Switch
+0
+2
+2
+Button_Switch_SMD
+SW_SPST_B3U-3000P-B
+Ultra-small-sized Tactile Switch with High Contact Reliability, Side-actuated Model, without Ground Terminal, with Boss
+Tactile Switch
+0
+2
+2
+Button_Switch_SMD
+SW_SPST_B3U-3100P
+Ultra-small-sized Tactile Switch with High Contact Reliability, Side-actuated Model, with Ground Terminal, without Boss
+Tactile Switch
+0
+3
+3
+Button_Switch_SMD
+SW_SPST_B3U-3100P-B
+Ultra-small-sized Tactile Switch with High Contact Reliability, Side-actuated Model, with Ground Terminal, with Boss
+Tactile Switch
+0
+3
+3
+Button_Switch_SMD
+SW_SPST_CK_KXT3
+https://www.ckswitches.com/media/1465/kxt3.pdf
+Switch SPST KXT3
+0
+2
+2
+Button_Switch_SMD
+SW_SPST_CK_RS282G05A3
+https://www.mouser.com/ds/2/60/RS-282G05A-SM_RT-1159762.pdf
+SPST button tactile switch
+0
+2
+2
+Button_Switch_SMD
+SW_SPST_EVPBF
+Light Touch Switch
+
+0
+4
+2
+Button_Switch_SMD
+SW_SPST_EVQP0
+Light Touch Switch, https://industrial.panasonic.com/cdbs/www-data/pdf/ATK0000/ATK0000CE28.pdf
+
+0
+4
+2
+Button_Switch_SMD
+SW_SPST_EVQP2
+Light Touch Switch
+
+0
+4
+2
+Button_Switch_SMD
+SW_SPST_EVQP7A
+Light Touch Switch,https://industrial.panasonic.com/cdbs/www-data/pdf/ATK0000/ATK0000CE20.pdf
+
+0
+4
+2
+Button_Switch_SMD
+SW_SPST_EVQP7C
+Light Touch Switch
+
+0
+4
+2
+Button_Switch_SMD
+SW_SPST_EVQPE1
+Light Touch Switch, https://industrial.panasonic.com/cdbs/www-data/pdf/ATK0000/ATK0000CE7.pdf
+
+0
+2
+2
+Button_Switch_SMD
+SW_SPST_EVQQ2
+Light Touch Switch, https://industrial.panasonic.com/cdbs/www-data/pdf/ATK0000/ATK0000CE28.pdf
+
+0
+4
+2
+Button_Switch_SMD
+SW_SPST_FSMSM
+http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=1437566-3&DocType=Customer+Drawing&DocLang=English
+SPST button tactile switch
+0
+2
+2
+Button_Switch_SMD
+SW_SPST_PTS645
+C&K Components SPST SMD PTS645 Series 6mm Tact Switch
+SPST Button Switch
+0
+4
+2
+Button_Switch_SMD
+SW_SPST_PTS810
+C&K Components, PTS 810 Series, Microminiature SMT Top Actuated, http://www.ckswitches.com/media/1476/pts810.pdf
+SPST Button Switch
+0
+4
+2
+Button_Switch_SMD
+SW_SPST_Panasonic_EVQPL_3PL_5PL_PT_A08
+Light Touch Switch, http://industrial.panasonic.com/cdbs/www-data/pdf/ATK0000/ATK0000CE3.pdf
+SMD SMT SPST EVQPL EVQPT
+0
+6
+3
+Button_Switch_SMD
+SW_SPST_Panasonic_EVQPL_3PL_5PL_PT_A15
+Light Touch Switch, http://industrial.panasonic.com/cdbs/www-data/pdf/ATK0000/ATK0000CE3.pdf
+SMD SMT SPST EVQPL EVQPT
+0
+6
+3
+Button_Switch_SMD
+SW_SPST_REED_CT05-XXXX-G1
+Coto Technologies SPST Reed Switch CT05-XXXX-G1
+Coto Reed SPST Switch
+0
+2
+2
+Button_Switch_SMD
+SW_SPST_REED_CT05-XXXX-J1
+Coto Technologies SPST Reed Switch CT05-XXXX-J1
+Coto Reed SPST Switch
+0
+2
+2
+Button_Switch_SMD
+SW_SPST_REED_CT10-XXXX-G1
+Coto Technologies SPST Reed Switch CT10-XXXX-G1
+Coto Reed SPST Switch
+0
+2
+2
+Button_Switch_SMD
+SW_SPST_REED_CT10-XXXX-G2
+Coto Technologies SPST Reed Switch CT10-XXXX-G2
+Coto Reed SPST Switch
+0
+2
+2
+Button_Switch_SMD
+SW_SPST_REED_CT10-XXXX-G4
+Coto Technologies SPST Reed Switch CT10-XXXX-G4
+Coto Reed SPST Switch
+0
+2
+2
+Button_Switch_SMD
+SW_SPST_SKQG_WithStem
+ALPS 5.2mm Square Low-profile Type (Surface Mount) SKQG Series, With stem, http://www.alps.com/prod/info/E/HTML/Tact/SurfaceMount/SKQG/SKQGAFE010.html
+SPST Button Switch
+0
+4
+2
+Button_Switch_SMD
+SW_SPST_SKQG_WithoutStem
+ALPS 5.2mm Square Low-profile Type (Surface Mount) SKQG Series, Without stem, http://www.alps.com/prod/info/E/HTML/Tact/SurfaceMount/SKQG/SKQGAEE010.html
+SPST Button Switch
+0
+4
+2
+Button_Switch_SMD
+SW_SPST_TL3305A
+https://www.e-switch.com/system/asset/product_line/data_sheet/213/TL3305.pdf
+TL3305 Series Tact Switch
+0
+4
+2
+Button_Switch_SMD
+SW_SPST_TL3305B
+https://www.e-switch.com/system/asset/product_line/data_sheet/213/TL3305.pdf
+TL3305 Series Tact Switch
+0
+4
+2
+Button_Switch_SMD
+SW_SPST_TL3305C
+https://www.e-switch.com/system/asset/product_line/data_sheet/213/TL3305.pdf
+TL3305 Series Tact Switch
+0
+4
+2
+Button_Switch_SMD
+SW_SPST_TL3342
+Low-profile SMD Tactile Switch, https://www.e-switch.com/system/asset/product_line/data_sheet/165/TL3342.pdf
+SPST Tactile Switch
+0
+4
+2
+Button_Switch_THT
+KSA_Tactile_SPST
+KSA http://www.ckswitches.com/media/1457/ksa_ksl.pdf
+SWITCH SMD KSA SW
+0
+5
+5
+Button_Switch_THT
+Nidec_Copal_SH-7010C
+4-bit rotary coded switch, through-hole, https://www.nidec-copal-electronics.com/e/catalog/switch/sh-7000.pdf
+rotary switch bcd
+0
+6
+5
+Button_Switch_THT
+Push_E-Switch_KS01Q01
+E-Switch KS01Q01 http://spec_sheets.e-switch.com/specs/29-KS01Q01.pdf
+Push Button
+0
+4
+4
+Button_Switch_THT
+SW_CW_GPTS203211B
+SPST Off-On Pushbutton, 1A, 30V, CW Industries P/N GPTS203211B, http://switches-connectors-custom.cwind.com/Asset/GPTS203211BR2.pdf
+SPST button switch Off-On
+0
+2
+2
+Button_Switch_THT
+SW_CuK_JS202011AQN_DPDT_Angled
+CuK sub miniature slide switch, JS series, DPDT, right angle, http://www.ckswitches.com/media/1422/js.pdf
+switch DPDT
+0
+6
+6
+Button_Switch_THT
+SW_CuK_JS202011CQN_DPDT_Straight
+CuK sub miniature slide switch, JS series, DPDT, right angle, http://www.ckswitches.com/media/1422/js.pdf
+switch DPDT
+0
+6
+6
+Button_Switch_THT
+SW_CuK_OS102011MA1QN1_SPDT_Angled
+CuK miniature slide switch, OS series, SPDT, right angle, http://www.ckswitches.com/media/1428/os.pdf
+switch SPDT
+0
+5
+3
+Button_Switch_THT
+SW_DIP_SPSTx01_Piano_10.8x4.1mm_W7.62mm_P2.54mm
+1x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x4.1mm
+DIP Switch SPST Piano 7.62mm 300mil
+0
+2
+2
+Button_Switch_THT
+SW_DIP_SPSTx01_Slide_6.7x4.1mm_W7.62mm_P2.54mm_LowProfile
+1x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x4.1mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile
+DIP Switch SPST Slide 7.62mm 300mil LowProfile
+0
+2
+2
+Button_Switch_THT
+SW_DIP_SPSTx01_Slide_9.78x4.72mm_W7.62mm_P2.54mm
+1x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x4.72mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf)
+DIP Switch SPST Slide 7.62mm 300mil
+0
+2
+2
+Button_Switch_THT
+SW_DIP_SPSTx02_Piano_10.8x6.64mm_W7.62mm_P2.54mm
+2x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x6.64mm
+DIP Switch SPST Piano 7.62mm 300mil
+0
+4
+4
+Button_Switch_THT
+SW_DIP_SPSTx02_Piano_CTS_Series194-2MSTN_W7.62mm_P2.54mm
+2x-dip-switch SPST CTS_Series194-2MSTN, Piano, row spacing 7.62 mm (300 mils), body size  (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf)
+DIP Switch SPST Piano 7.62mm 300mil
+0
+4
+4
+Button_Switch_THT
+SW_DIP_SPSTx02_Slide_6.7x6.64mm_W7.62mm_P2.54mm_LowProfile
+2x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x6.64mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile
+DIP Switch SPST Slide 7.62mm 300mil LowProfile
+0
+4
+4
+Button_Switch_THT
+SW_DIP_SPSTx02_Slide_9.78x7.26mm_W7.62mm_P2.54mm
+2x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x7.26mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf)
+DIP Switch SPST Slide 7.62mm 300mil
+0
+4
+4
+Button_Switch_THT
+SW_DIP_SPSTx03_Piano_10.8x9.18mm_W7.62mm_P2.54mm
+3x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x9.18mm
+DIP Switch SPST Piano 7.62mm 300mil
+0
+6
+6
+Button_Switch_THT
+SW_DIP_SPSTx03_Piano_CTS_Series194-3MSTN_W7.62mm_P2.54mm
+3x-dip-switch SPST CTS_Series194-3MSTN, Piano, row spacing 7.62 mm (300 mils), body size  (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf)
+DIP Switch SPST Piano 7.62mm 300mil
+0
+6
+6
+Button_Switch_THT
+SW_DIP_SPSTx03_Slide_6.7x9.18mm_W7.62mm_P2.54mm_LowProfile
+3x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x9.18mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile
+DIP Switch SPST Slide 7.62mm 300mil LowProfile
+0
+6
+6
+Button_Switch_THT
+SW_DIP_SPSTx03_Slide_9.78x9.8mm_W7.62mm_P2.54mm
+3x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x9.8mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf)
+DIP Switch SPST Slide 7.62mm 300mil
+0
+6
+6
+Button_Switch_THT
+SW_DIP_SPSTx04_Piano_10.8x11.72mm_W7.62mm_P2.54mm
+4x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x11.72mm
+DIP Switch SPST Piano 7.62mm 300mil
+0
+8
+8
+Button_Switch_THT
+SW_DIP_SPSTx04_Piano_CTS_Series194-4MSTN_W7.62mm_P2.54mm
+4x-dip-switch SPST CTS_Series194-4MSTN, Piano, row spacing 7.62 mm (300 mils), body size  (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf)
+DIP Switch SPST Piano 7.62mm 300mil
+0
+8
+8
+Button_Switch_THT
+SW_DIP_SPSTx04_Slide_6.7x11.72mm_W7.62mm_P2.54mm_LowProfile
+4x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x11.72mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile
+DIP Switch SPST Slide 7.62mm 300mil LowProfile
+0
+8
+8
+Button_Switch_THT
+SW_DIP_SPSTx04_Slide_9.78x12.34mm_W7.62mm_P2.54mm
+4x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x12.34mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf)
+DIP Switch SPST Slide 7.62mm 300mil
+0
+8
+8
+Button_Switch_THT
+SW_DIP_SPSTx05_Piano_10.8x14.26mm_W7.62mm_P2.54mm
+5x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x14.26mm
+DIP Switch SPST Piano 7.62mm 300mil
+0
+10
+10
+Button_Switch_THT
+SW_DIP_SPSTx05_Piano_CTS_Series194-5MSTN_W7.62mm_P2.54mm
+5x-dip-switch SPST CTS_Series194-5MSTN, Piano, row spacing 7.62 mm (300 mils), body size  (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf)
+DIP Switch SPST Piano 7.62mm 300mil
+0
+10
+10
+Button_Switch_THT
+SW_DIP_SPSTx05_Slide_6.7x14.26mm_W7.62mm_P2.54mm_LowProfile
+5x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x14.26mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile
+DIP Switch SPST Slide 7.62mm 300mil LowProfile
+0
+10
+10
+Button_Switch_THT
+SW_DIP_SPSTx05_Slide_9.78x14.88mm_W7.62mm_P2.54mm
+5x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x14.88mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf)
+DIP Switch SPST Slide 7.62mm 300mil
+0
+10
+10
+Button_Switch_THT
+SW_DIP_SPSTx06_Piano_10.8x16.8mm_W7.62mm_P2.54mm
+6x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x16.8mm
+DIP Switch SPST Piano 7.62mm 300mil
+0
+12
+12
+Button_Switch_THT
+SW_DIP_SPSTx06_Piano_CTS_Series194-6MSTN_W7.62mm_P2.54mm
+6x-dip-switch SPST CTS_Series194-6MSTN, Piano, row spacing 7.62 mm (300 mils), body size  (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf)
+DIP Switch SPST Piano 7.62mm 300mil
+0
+12
+12
+Button_Switch_THT
+SW_DIP_SPSTx06_Slide_6.7x16.8mm_W7.62mm_P2.54mm_LowProfile
+6x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x16.8mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile
+DIP Switch SPST Slide 7.62mm 300mil LowProfile
+0
+12
+12
+Button_Switch_THT
+SW_DIP_SPSTx06_Slide_9.78x17.42mm_W7.62mm_P2.54mm
+6x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x17.42mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf)
+DIP Switch SPST Slide 7.62mm 300mil
+0
+12
+12
+Button_Switch_THT
+SW_DIP_SPSTx07_Piano_10.8x19.34mm_W7.62mm_P2.54mm
+7x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x19.34mm
+DIP Switch SPST Piano 7.62mm 300mil
+0
+14
+14
+Button_Switch_THT
+SW_DIP_SPSTx07_Piano_CTS_Series194-7MSTN_W7.62mm_P2.54mm
+7x-dip-switch SPST CTS_Series194-7MSTN, Piano, row spacing 7.62 mm (300 mils), body size  (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf)
+DIP Switch SPST Piano 7.62mm 300mil
+0
+14
+14
+Button_Switch_THT
+SW_DIP_SPSTx07_Slide_6.7x19.34mm_W7.62mm_P2.54mm_LowProfile
+7x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x19.34mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile
+DIP Switch SPST Slide 7.62mm 300mil LowProfile
+0
+14
+14
+Button_Switch_THT
+SW_DIP_SPSTx07_Slide_9.78x19.96mm_W7.62mm_P2.54mm
+7x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x19.96mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf)
+DIP Switch SPST Slide 7.62mm 300mil
+0
+14
+14
+Button_Switch_THT
+SW_DIP_SPSTx08_Piano_10.8x21.88mm_W7.62mm_P2.54mm
+8x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x21.88mm
+DIP Switch SPST Piano 7.62mm 300mil
+0
+16
+16
+Button_Switch_THT
+SW_DIP_SPSTx08_Piano_CTS_Series194-8MSTN_W7.62mm_P2.54mm
+8x-dip-switch SPST CTS_Series194-8MSTN, Piano, row spacing 7.62 mm (300 mils), body size  (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf)
+DIP Switch SPST Piano 7.62mm 300mil
+0
+16
+16
+Button_Switch_THT
+SW_DIP_SPSTx08_Slide_6.7x21.88mm_W7.62mm_P2.54mm_LowProfile
+8x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x21.88mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile
+DIP Switch SPST Slide 7.62mm 300mil LowProfile
+0
+16
+16
+Button_Switch_THT
+SW_DIP_SPSTx08_Slide_9.78x22.5mm_W7.62mm_P2.54mm
+8x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x22.5mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf)
+DIP Switch SPST Slide 7.62mm 300mil
+0
+16
+16
+Button_Switch_THT
+SW_DIP_SPSTx09_Piano_10.8x24.42mm_W7.62mm_P2.54mm
+9x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x24.42mm
+DIP Switch SPST Piano 7.62mm 300mil
+0
+18
+18
+Button_Switch_THT
+SW_DIP_SPSTx09_Piano_CTS_Series194-9MSTN_W7.62mm_P2.54mm
+9x-dip-switch SPST CTS_Series194-9MSTN, Piano, row spacing 7.62 mm (300 mils), body size  (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf)
+DIP Switch SPST Piano 7.62mm 300mil
+0
+18
+18
+Button_Switch_THT
+SW_DIP_SPSTx09_Slide_6.7x24.42mm_W7.62mm_P2.54mm_LowProfile
+9x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x24.42mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile
+DIP Switch SPST Slide 7.62mm 300mil LowProfile
+0
+18
+18
+Button_Switch_THT
+SW_DIP_SPSTx09_Slide_9.78x25.04mm_W7.62mm_P2.54mm
+9x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x25.04mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf)
+DIP Switch SPST Slide 7.62mm 300mil
+0
+18
+18
+Button_Switch_THT
+SW_DIP_SPSTx10_Piano_10.8x26.96mm_W7.62mm_P2.54mm
+10x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x26.96mm
+DIP Switch SPST Piano 7.62mm 300mil
+0
+20
+20
+Button_Switch_THT
+SW_DIP_SPSTx10_Piano_CTS_Series194-10MSTN_W7.62mm_P2.54mm
+10x-dip-switch SPST CTS_Series194-10MSTN, Piano, row spacing 7.62 mm (300 mils), body size  (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf)
+DIP Switch SPST Piano 7.62mm 300mil
+0
+20
+20
+Button_Switch_THT
+SW_DIP_SPSTx10_Slide_6.7x26.96mm_W7.62mm_P2.54mm_LowProfile
+10x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x26.96mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile
+DIP Switch SPST Slide 7.62mm 300mil LowProfile
+0
+20
+20
+Button_Switch_THT
+SW_DIP_SPSTx10_Slide_9.78x27.58mm_W7.62mm_P2.54mm
+10x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x27.58mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf)
+DIP Switch SPST Slide 7.62mm 300mil
+0
+20
+20
+Button_Switch_THT
+SW_DIP_SPSTx11_Piano_10.8x29.5mm_W7.62mm_P2.54mm
+11x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x29.5mm
+DIP Switch SPST Piano 7.62mm 300mil
+0
+22
+22
+Button_Switch_THT
+SW_DIP_SPSTx11_Piano_CTS_Series194-11MSTN_W7.62mm_P2.54mm
+11x-dip-switch SPST CTS_Series194-11MSTN, Piano, row spacing 7.62 mm (300 mils), body size  (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf)
+DIP Switch SPST Piano 7.62mm 300mil
+0
+22
+22
+Button_Switch_THT
+SW_DIP_SPSTx11_Slide_6.7x29.5mm_W7.62mm_P2.54mm_LowProfile
+11x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x29.5mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile
+DIP Switch SPST Slide 7.62mm 300mil LowProfile
+0
+22
+22
+Button_Switch_THT
+SW_DIP_SPSTx11_Slide_9.78x30.12mm_W7.62mm_P2.54mm
+11x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x30.12mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf)
+DIP Switch SPST Slide 7.62mm 300mil
+0
+22
+22
+Button_Switch_THT
+SW_DIP_SPSTx12_Piano_10.8x32.04mm_W7.62mm_P2.54mm
+12x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x32.04mm
+DIP Switch SPST Piano 7.62mm 300mil
+0
+24
+24
+Button_Switch_THT
+SW_DIP_SPSTx12_Piano_CTS_Series194-12MSTN_W7.62mm_P2.54mm
+12x-dip-switch SPST CTS_Series194-12MSTN, Piano, row spacing 7.62 mm (300 mils), body size  (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf)
+DIP Switch SPST Piano 7.62mm 300mil
+0
+24
+24
+Button_Switch_THT
+SW_DIP_SPSTx12_Slide_6.7x32.04mm_W7.62mm_P2.54mm_LowProfile
+12x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x32.04mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile
+DIP Switch SPST Slide 7.62mm 300mil LowProfile
+0
+24
+24
+Button_Switch_THT
+SW_DIP_SPSTx12_Slide_9.78x32.66mm_W7.62mm_P2.54mm
+12x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x32.66mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf)
+DIP Switch SPST Slide 7.62mm 300mil
+0
+24
+24
+Button_Switch_THT
+SW_E-Switch_EG1224_SPDT_Angled
+E-Switch slide switch, EG series, SPDT, right angle, http://spec_sheets.e-switch.com/specs/P040042.pdf
+switch SPDT
+0
+7
+3
+Button_Switch_THT
+SW_E-Switch_EG1271_DPDT
+E-Switch sub miniature slide switch, EG series, DPDT, http://spec_sheets.e-switch.com/specs/P040047.pdf
+switch DPDT
+0
+6
+6
+Button_Switch_THT
+SW_E-Switch_EG2219_DPDT_Angled
+E-Switch slide switch, EG series, DPDT, right angle, http://spec_sheets.e-switch.com/specs/P040170.pdf
+switch DPDT
+0
+10
+6
+Button_Switch_THT
+SW_Lever_1P2T_NKK_GW12LxH
+Switch, single pole double throw, right angle, http://www.nkkswitches.com/pdf/GW.pdf
+switch single-pole double-throw spdt ON-ON horizontal
+0
+5
+3
+Button_Switch_THT
+SW_MEC_5GTH9
+MEC 5G single pole normally-open tactile switch https://cdn.sos.sk/productdata/80/f6/aabf7be6/5gth9358222.pdf
+switch normally-open pushbutton push-button
+0
+4
+2
+Button_Switch_THT
+SW_NKK_BB15AH
+https://www.nkkswitches.com/pdf/Bpushbuttons-1.pdf
+Pushbutton Right-angle
+0
+5
+3
+Button_Switch_THT
+SW_NKK_G1xJP
+Switch NKK G1xJP http://www.nkkswitches.com/pdf/gwillum.pdf
+SWITCH TOGGLE ILLUM SPDT NKK
+0
+6
+6
+Button_Switch_THT
+SW_NKK_GW12LJP
+Switch, single pole double throw, illuminated paddle, http://www.nkkswitches.com/pdf/gwillum.pdf
+switch single-pole double-throw spdt ON-ON illuminated LED
+0
+6
+6
+Button_Switch_THT
+SW_PUSH-12mm
+SW PUSH 12mm https://www.e-switch.com/system/asset/product_line/data_sheet/143/TL1100.pdf
+tact sw push 12mm
+0
+4
+2
+Button_Switch_THT
+SW_PUSH-12mm_Wuerth-430476085716
+SW PUSH 12mm http://katalog.we-online.de/em/datasheet/430476085716.pdf
+tact sw push 12mm
+0
+4
+2
+Button_Switch_THT
+SW_PUSH_6mm
+https://www.omron.com/ecb/products/pdf/en-b3f.pdf
+tact sw push 6mm
+0
+4
+2
+Button_Switch_THT
+SW_PUSH_6mm_H4.3mm
+tactile push button, 6x6mm e.g. PHAP33xx series, height=4.3mm
+tact sw push 6mm
+0
+4
+2
+Button_Switch_THT
+SW_PUSH_6mm_H5mm
+tactile push button, 6x6mm e.g. PHAP33xx series, height=5mm
+tact sw push 6mm
+0
+4
+2
+Button_Switch_THT
+SW_PUSH_6mm_H7.3mm
+tactile push button, 6x6mm e.g. PHAP33xx series, height=7.3mm
+tact sw push 6mm
+0
+4
+2
+Button_Switch_THT
+SW_PUSH_6mm_H8.5mm
+tactile push button, 6x6mm e.g. PHAP33xx series, height=8.5mm
+tact sw push 6mm
+0
+4
+2
+Button_Switch_THT
+SW_PUSH_6mm_H8mm
+tactile push button, 6x6mm e.g. PHAP33xx series, height=8mm
+tact sw push 6mm
+0
+4
+2
+Button_Switch_THT
+SW_PUSH_6mm_H9.5mm
+tactile push button, 6x6mm e.g. PHAP33xx series, height=9.5mm
+tact sw push 6mm
+0
+4
+2
+Button_Switch_THT
+SW_PUSH_6mm_H13mm
+tactile push button, 6x6mm e.g. PHAP33xx series, height=13mm
+tact sw push 6mm
+0
+4
+2
+Button_Switch_THT
+SW_PUSH_E-Switch_FS5700DP_DPDT
+FS5700 series pushbutton footswitch, DPDT, https://www.e-switch.com/system/asset/product_line/data_sheet/226/FS5700.pdf
+switch DPDT footswitch
+0
+6
+6
+Button_Switch_THT
+SW_PUSH_LCD_E3_SAxxxx
+Switch with LCD screen E3 SAxxxx
+switch normally-open pushbutton push-button LCD
+0
+6
+6
+Button_Switch_THT
+SW_PUSH_LCD_E3_SAxxxx_SocketPins
+Switch with LCD screen E3 SAxxxx
+switch normally-open pushbutton push-button LCD
+0
+6
+6
+Button_Switch_THT
+SW_Push_1P1T_NO_LED_E-Switch_TL1250
+illuminated right angle tact switch https://www.e-switch.com/system/asset/product_line/data_sheet/148/TL1250.pdf
+led push switch right angle
+0
+6
+4
+Button_Switch_THT
+SW_Push_1P2T_Vertical_E-Switch_800UDP8P1A1M6
+ right angle SPDT push button https://www.e-switch.com/system/asset/product_line/data_sheet/210/800U.pdf
+IP67 ultra-miniture horizontal
+0
+5
+3
+Button_Switch_THT
+SW_Push_2P2T_Vertical_E-Switch_800UDP8P1A1M6
+ right angle DPDT push button https://www.e-switch.com/system/asset/product_line/data_sheet/210/800U.pdf
+IP67 ultra-miniture horizontal
+0
+8
+6
+Button_Switch_THT
+SW_Slide_1P2T_CK_OS102011MS2Q
+CuK miniature slide switch, OS series, SPDT, https://www.ckswitches.com/media/1428/os.pdf
+switch SPDT
+0
+5
+3
+Button_Switch_THT
+SW_TH_Tactile_Omron_B3F-10xx
+SW_TH_Tactile_Omron_B3F-10xx_https://www.omron.com/ecb/products/pdf/en-b3f.pdf
+Omron B3F-10xx
+0
+4
+4
+Button_Switch_THT
+SW_Tactile_SKHH_Angled
+tactile switch 6mm ALPS SKHH right angle http://www.alps.com/prod/info/E/HTML/Tact/SnapIn/SKHH/SKHHLUA010.html
+tactile switch 6mm ALPS SKHH right angle
+0
+4
+2
+Button_Switch_THT
+SW_Tactile_SPST_Angled_PTS645Vx31-2LFS
+tactile switch SPST right angle, PTS645VL31-2 LFS
+tactile switch SPST angled PTS645VL31-2 LFS C&K Button
+0
+4
+2
+Button_Switch_THT
+SW_Tactile_SPST_Angled_PTS645Vx39-2LFS
+tactile switch SPST right angle, PTS645VL39-2 LFS
+tactile switch SPST angled PTS645VL39-2 LFS C&K Button
+0
+4
+2
+Button_Switch_THT
+SW_Tactile_SPST_Angled_PTS645Vx58-2LFS
+tactile switch SPST right angle, PTS645VL58-2 LFS
+tactile switch SPST angled PTS645VL58-2 LFS C&K Button
+0
+4
+2
+Button_Switch_THT
+SW_Tactile_SPST_Angled_PTS645Vx83-2LFS
+tactile switch SPST right angle, PTS645VL83-2 LFS
+tactile switch SPST angled PTS645VL83-2 LFS C&K Button
+0
+4
+2
+Button_Switch_THT
+SW_Tactile_Straight_KSA0Axx1LFTR
+SW PUSH SMALL http://www.ckswitches.com/media/1457/ksa_ksl.pdf
+SW PUSH SMALL Tactile C&K
+0
+4
+2
+Button_Switch_THT
+SW_Tactile_Straight_KSL0Axx1LFTR
+SW PUSH SMALL http://www.ckswitches.com/media/1457/ksa_ksl.pdf
+SW PUSH SMALL Tactile C&K
+0
+4
+2
+Buzzer_Beeper
+Buzzer_12x9.5RM7.6
+Generic Buzzer, D12mm height 9.5mm with RM7.6mm
+buzzer
+0
+2
+2
+Buzzer_Beeper
+Buzzer_15x7.5RM7.6
+Generic Buzzer, D15mm height 7.5mm with RM7.6mm
+buzzer
+0
+2
+2
+Buzzer_Beeper
+Buzzer_CUI_CPT-9019S-SMT
+https://www.cui.com/product/resource/cpt-9019s-smt.pdf
+buzzer piezo
+0
+2
+2
+Buzzer_Beeper
+Buzzer_D14mm_H7mm_P10mm
+Generic Buzzer, D14mm height 7mm with pitch 10mm
+buzzer
+0
+2
+2
+Buzzer_Beeper
+Buzzer_Mallory_AST1109MLTRQ
+Mallory low-profile piezo buzzer, https://www.mspindy.com/specifications/AST1109MLTRQ.pdf
+buzzer piezo
+0
+2
+2
+Buzzer_Beeper
+Buzzer_Murata_PKMCS0909E4000-R1
+Murata Buzzer http://www.murata.com/en-us/api/pdfdownloadapi?cate=&partno=PKMCS0909E4000-R1
+Murata Buzzer Beeper
+0
+2
+2
+Buzzer_Beeper
+Buzzer_TDK_PS1240P02BT_D12.2mm_H6.5mm
+Buzzer, D12.2mm height 6.5mm, https://product.tdk.com/info/en/catalog/datasheets/piezoelectronic_buzzer_ps_en.pdf
+buzzer
+0
+2
+2
+Buzzer_Beeper
+MagneticBuzzer_CUI_CST-931RP-A
+CST-931RP-A, http://www.cui.com/product/resource/cst-931rp-a.pdf
+CST-931RP-A
+0
+2
+2
+Buzzer_Beeper
+MagneticBuzzer_Kingstate_KCG0601
+Buzzer, Elektromagnetic Beeper, Summer,
+Kingstate KCG0601 
+0
+2
+2
+Buzzer_Beeper
+MagneticBuzzer_Kobitone_254-EMB84Q-RO
+MagneticBuzzer Kobitone 254-EMB84Q-RO https://www.mouser.es/datasheet/2/209/KT-400385-1171904.pdf
+MagneticBuzzer Kobitone 254-EMB84Q-RO
+0
+3
+3
+Buzzer_Beeper
+MagneticBuzzer_PUI_AT-0927-TT-6-R
+Buzzer Magnetic 9mm AT-0927-TT-6-R, http://www.puiaudio.com/pdf/AT-0927-TT-6-R.pdf
+Buzzer Magnetic 9mm AT-0927-TT-6-R
+0
+2
+2
+Buzzer_Beeper
+MagneticBuzzer_ProSignal_ABI-009-RC
+Buzzer, Elektromagnetic Beeper, Summer, 6V-DC,
+Pro Signal ABI-009-RC 
+0
+2
+2
+Buzzer_Beeper
+MagneticBuzzer_ProSignal_ABI-010-RC
+Buzzer, Elektromagnetic Beeper, Summer, 12V-DC,
+Pro Signal ABI-010-RC 
+0
+2
+2
+Buzzer_Beeper
+MagneticBuzzer_ProSignal_ABT-410-RC
+Buzzer, Elektromagnetic Beeper, Summer, 1,5V-DC,
+Pro Signal ABT-410-RC 
+0
+2
+2
+Buzzer_Beeper
+MagneticBuzzer_ProjectsUnlimited_AI-4228-TWT-R
+Buzzer, Elektromagnetic Beeper, Summer, 3-28V-DC, https://www.kynix.com/uploadfiles/pdf/AI-4228-TWT-R.pdf
+Projects Unlimited AI-4228-TWT-R 
+0
+2
+2
+Buzzer_Beeper
+MagneticBuzzer_StarMicronics_HMB-06_HMB-12
+Buzzer, Elektromagnetic Beeper, Summer,
+Star Micronics HMB-06 HMB-12
+0
+2
+2
+Buzzer_Beeper
+PUIAudio_SMT_0825_S_4_R
+SMD 8540, http://www.puiaudio.com/product-detail.aspx?partnumber=SMT-0825-S-4-R
+SMD 8540
+0
+4
+4
+CY62148GN-45ZSXI
+SOIC127P1176X120-32N
+
+
+0
+32
+32
+Calibration_Scale
+Gauge_10mm_Type1_CopperTop
+Gauge, Massstab, 10mm, CopperTop, Type 1,
+Gauge Massstab 10mm CopperTop Type 1
+0
+0
+0
+Calibration_Scale
+Gauge_10mm_Type1_SilkScreenTop
+Gauge, Massstab, 10mm, SilkScreenTop, Type 1,
+Gauge Massstab 10mm SilkScreenTop Type 1
+0
+0
+0
+Calibration_Scale
+Gauge_10mm_Type2_CopperTop
+Gauge, Massstab, 10mm, CopperTop, Type 2,
+Gauge Massstab 10mm CopperTop Type 2
+0
+0
+0
+Calibration_Scale
+Gauge_10mm_Type2_SilkScreenTop
+Gauge, Massstab, 10mm, SilkScreenTop, Type 2,
+Gauge Massstab 10mm SilkScreenTop Type 2
+0
+0
+0
+Calibration_Scale
+Gauge_10mm_Type3_CopperTop
+Gauge, Massstab, 10mm, CopperTop, Type 3,
+Gauge Massstab 10mm CopperTop Type 3
+0
+0
+0
+Calibration_Scale
+Gauge_10mm_Type3_SilkScreenTop
+Gauge, Massstab, 10mm, SilkScreenTop, Type 3,
+Gauge Massstab 10mm SilkScreenTop Type 3
+0
+0
+0
+Calibration_Scale
+Gauge_10mm_Type4_CopperTop
+Gauge, Massstab, 10mm, CopperTop, Type 4,
+Gauge Massstab 10mm CopperTop Type 4
+0
+0
+0
+Calibration_Scale
+Gauge_10mm_Type4_SilkScreenTop
+Gauge, Massstab, 10mm, SilkScreenTop, Type 4,
+Gauge Massstab 10mm SilkScreenTop Type 4
+0
+0
+0
+Calibration_Scale
+Gauge_10mm_Type5_CopperTop
+Gauge, Massstab, 10mm, CopperTop, Type 5,
+Gauge Massstab 10mm CopperTop Type 5
+0
+0
+0
+Calibration_Scale
+Gauge_10mm_Type5_SilkScreenTop
+Gauge, Massstab, 10mm, SilkScreenTop, Type 5,
+Gauge Massstab 10mm SilkScreenTop Type 5
+0
+0
+0
+Calibration_Scale
+Gauge_50mm_Type1_CopperTop
+Gauge, Massstab, 50mm, CopperTop, Type 1,
+Gauge Massstab 50mm CopperTop Type 1
+0
+0
+0
+Calibration_Scale
+Gauge_50mm_Type1_SilkScreenTop
+Gauge, Massstab, 50mm, SilkScreenTop, Type 1,
+Gauge Massstab 50mm SilkScreenTop Type 1
+0
+0
+0
+Calibration_Scale
+Gauge_50mm_Type2_CopperTop
+Gauge, Massstab, 50mm, CopperTop, Type 2,
+Gauge Massstab 50mm CopperTop Type 2
+0
+0
+0
+Calibration_Scale
+Gauge_50mm_Type2_SilkScreenTop
+Gauge, Massstab, 50mm, SilkScreenTop, Type 2,
+Gauge Massstab 50mm SilkScreenTop Type 2
+0
+0
+0
+Calibration_Scale
+Gauge_100mm_Grid_Type1_CopperTop
+Gauge, Massstab, 100mm, Gitter, Grid, CopperTop, Type 1,
+Gauge Massstab 100mm Gitter Grid CopperTop Type 1
+0
+0
+0
+Calibration_Scale
+Gauge_100mm_Type1_CopperTop
+Gauge, Massstab, 100mm, CopperTop, Type 1,
+Gauge Massstab 100mm CopperTop Type 1
+0
+0
+0
+Calibration_Scale
+Gauge_100mm_Type1_SilkScreenTop
+Gauge, Massstab, 100mm, SilkScreenTop, Type 1,
+Gauge Massstab 100mm SilkScreenTop Type 1
+0
+0
+0
+Calibration_Scale
+Gauge_100mm_Type2_CopperTop
+Gauge, Massstab, 100mm, CopperTop, Type 2,
+Gauge Massstab 100mm  CopperTop Type 2
+0
+0
+0
+Calibration_Scale
+Gauge_100mm_Type2_SilkScreenTop
+Gauge, Massstab, 100mm, SilkScreenTop, Type 2,
+Gauge Massstab 100mm SilkScreenTop Type 2
+0
+0
+0
+Capacitor_SMD
+CP_Elec_3x5.3
+SMT capacitor, aluminium electrolytic, 3x5.3, Cornell Dubilier Electronics 
+Capacitor Electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_3x5.4
+SMD capacitor, aluminum electrolytic, Nichicon, 3.0x5.4mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_4x3
+SMD capacitor, aluminum electrolytic, Nichicon, 4.0x3mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_4x3.9
+SMD capacitor, aluminum electrolytic, Nichicon, 4.0x3.9mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_4x4.5
+SMD capacitor, aluminum electrolytic, Nichicon, 4.0x4.5mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_4x5.3
+SMD capacitor, aluminum electrolytic, Vishay, 4.0x5.3mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_4x5.4
+SMD capacitor, aluminum electrolytic, Panasonic A5 / Nichicon, 4.0x5.4mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_4x5.7
+SMD capacitor, aluminum electrolytic, United Chemi-Con, 4.0x5.7mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_4x5.8
+SMD capacitor, aluminum electrolytic, Panasonic, 4.0x5.8mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_5x3
+SMD capacitor, aluminum electrolytic, Nichicon, 5.0x3.0mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_5x3.9
+SMD capacitor, aluminum electrolytic, Nichicon, 5.0x3.9mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_5x4.4
+SMD capacitor, aluminum electrolytic, Panasonic B45, 5.0x4.4mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_5x4.5
+SMD capacitor, aluminum electrolytic, Nichicon, 5.0x4.5mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_5x5.3
+SMD capacitor, aluminum electrolytic, Nichicon, 5.0x5.3mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_5x5.4
+SMD capacitor, aluminum electrolytic, Nichicon, 5.0x5.4mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_5x5.7
+SMD capacitor, aluminum electrolytic, United Chemi-Con, 5.0x5.7mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_5x5.8
+SMD capacitor, aluminum electrolytic, Panasonic, 5.0x5.8mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_5x5.9
+SMD capacitor, aluminum electrolytic, Panasonic B6, 5.0x5.9mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_6.3x3
+SMD capacitor, aluminum electrolytic, Nichicon, 6.3x3.0mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_6.3x3.9
+SMD capacitor, aluminum electrolytic, Nichicon, 6.3x3.9mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_6.3x4.5
+SMD capacitor, aluminum electrolytic, Nichicon, 6.3x4.5mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_6.3x4.9
+SMD capacitor, aluminum electrolytic, Panasonic C5, 6.3x4.9mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_6.3x5.2
+SMD capacitor, aluminum electrolytic, United Chemi-Con, 6.3x5.2mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_6.3x5.3
+SMD capacitor, aluminum electrolytic, Cornell Dubilier, 6.3x5.3mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_6.3x5.4
+SMD capacitor, aluminum electrolytic, Panasonic C55, 6.3x5.4mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_6.3x5.4_Nichicon
+SMD capacitor, aluminum electrolytic, Nichicon, 6.3x5.4mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_6.3x5.7
+SMD capacitor, aluminum electrolytic, United Chemi-Con, 6.3x5.7mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_6.3x5.8
+SMD capacitor, aluminum electrolytic, Nichicon, 6.3x5.8mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_6.3x5.9
+SMD capacitor, aluminum electrolytic, Panasonic C6, 6.3x5.9mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_6.3x7.7
+SMD capacitor, aluminum electrolytic, Nichicon, 6.3x7.7mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_6.3x9.9
+SMD capacitor, aluminum electrolytic, Panasonic C10, 6.3x9.9mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_8x5.4
+SMD capacitor, aluminum electrolytic, Nichicon, 8.0x5.4mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_8x6.2
+SMD capacitor, aluminum electrolytic, Nichicon, 8.0x6.2mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_8x6.5
+SMD capacitor, aluminum electrolytic, Rubycon, 8.0x6.5mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_8x6.7
+SMD capacitor, aluminum electrolytic, United Chemi-Con, 8.0x6.7mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_8x6.9
+SMD capacitor, aluminum electrolytic, Panasonic E7, 8.0x6.9mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_8x10
+SMD capacitor, aluminum electrolytic, Nichicon, 8.0x10mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_8x10.5
+SMD capacitor, aluminum electrolytic, Vishay 0810, 8.0x10.5mm, http://www.vishay.com/docs/28395/150crz.pdf
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_8x11.9
+SMD capacitor, aluminum electrolytic, Panasonic E12, 8.0x11.9mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_10x7.7
+SMD capacitor, aluminum electrolytic, Nichicon, 10.0x7.7mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_10x7.9
+SMD capacitor, aluminum electrolytic, Panasonic F8, 10.0x7.9mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_10x10
+SMD capacitor, aluminum electrolytic, Nichicon, 10.0x10.0mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_10x10.5
+SMD capacitor, aluminum electrolytic, Vishay 1010, 10.0x10.5mm, http://www.vishay.com/docs/28395/150crz.pdf
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_10x12.5
+SMD capacitor, aluminum electrolytic, Vishay 1012, 10.0x12.5mm, http://www.vishay.com/docs/28395/150crz.pdf
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_10x12.6
+SMD capacitor, aluminum electrolytic, Panasonic F12, 10.0x12.6mm
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_10x14.3
+SMD capacitor, aluminum electrolytic, Vishay 1014, 10.0x14.3mm, http://www.vishay.com/docs/28395/150crz.pdf
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_16x17.5
+SMD capacitor, aluminum electrolytic, Vishay 1616, 16.0x17.5mm, http://www.vishay.com/docs/28395/150crz.pdf
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_16x22
+SMD capacitor, aluminum electrolytic, Vishay 1621, 16.0x22.0mm, http://www.vishay.com/docs/28395/150crz.pdf
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_18x17.5
+SMD capacitor, aluminum electrolytic, Vishay 1816, 18.0x17.5mm, http://www.vishay.com/docs/28395/150crz.pdf
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+CP_Elec_18x22
+SMD capacitor, aluminum electrolytic, Vishay 1821, 18.0x22.0mm, http://www.vishay.com/docs/28395/150crz.pdf
+capacitor electrolytic
+0
+2
+2
+Capacitor_SMD
+C_0201_0603Metric
+Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator
+capacitor
+0
+4
+2
+Capacitor_SMD
+C_0402_1005Metric
+Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+capacitor
+0
+2
+2
+Capacitor_SMD
+C_0603_1608Metric
+Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+capacitor
+0
+2
+2
+Capacitor_SMD
+C_0603_1608Metric_Pad1.05x0.95mm_HandSolder
+Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+capacitor handsolder
+0
+2
+2
+Capacitor_SMD
+C_0805_2012Metric
+Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator
+capacitor
+0
+2
+2
+Capacitor_SMD
+C_0805_2012Metric_Pad1.15x1.40mm_HandSolder
+Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator
+capacitor handsolder
+0
+2
+2
+Capacitor_SMD
+C_01005_0402Metric
+Capacitor SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator
+capacitor
+0
+4
+2
+Capacitor_SMD
+C_1206_3216Metric
+Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+capacitor
+0
+2
+2
+Capacitor_SMD
+C_1206_3216Metric_Pad1.42x1.75mm_HandSolder
+Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+capacitor handsolder
+0
+2
+2
+Capacitor_SMD
+C_1210_3225Metric
+Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+capacitor
+0
+2
+2
+Capacitor_SMD
+C_1210_3225Metric_Pad1.42x2.65mm_HandSolder
+Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+capacitor handsolder
+0
+2
+2
+Capacitor_SMD
+C_1806_4516Metric
+Capacitor SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator
+capacitor
+0
+2
+2
+Capacitor_SMD
+C_1806_4516Metric_Pad1.57x1.80mm_HandSolder
+Capacitor SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator
+capacitor handsolder
+0
+2
+2
+Capacitor_SMD
+C_1812_4532Metric
+Capacitor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator
+capacitor
+0
+2
+2
+Capacitor_SMD
+C_1812_4532Metric_Pad1.30x3.40mm_HandSolder
+Capacitor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator
+capacitor handsolder
+0
+2
+2
+Capacitor_SMD
+C_1825_4564Metric
+Capacitor SMD 1825 (4564 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator
+capacitor
+0
+2
+2
+Capacitor_SMD
+C_1825_4564Metric_Pad1.88x6.70mm_HandSolder
+Capacitor SMD 1825 (4564 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator
+capacitor handsolder
+0
+2
+2
+Capacitor_SMD
+C_2010_5025Metric
+Capacitor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+capacitor
+0
+2
+2
+Capacitor_SMD
+C_2010_5025Metric_Pad1.52x2.65mm_HandSolder
+Capacitor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+capacitor handsolder
+0
+2
+2
+Capacitor_SMD
+C_2220_5650Metric
+Capacitor SMD 2220 (5650 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator
+capacitor
+0
+2
+2
+Capacitor_SMD
+C_2220_5650Metric_Pad1.97x5.40mm_HandSolder
+Capacitor SMD 2220 (5650 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator
+capacitor handsolder
+0
+2
+2
+Capacitor_SMD
+C_2225_5664Metric
+Capacitor SMD 2225 (5664 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator
+capacitor
+0
+2
+2
+Capacitor_SMD
+C_2225_5664Metric_Pad1.80x6.60mm_HandSolder
+Capacitor SMD 2225 (5664 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator
+capacitor handsolder
+0
+2
+2
+Capacitor_SMD
+C_2512_6332Metric
+Capacitor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+capacitor
+0
+2
+2
+Capacitor_SMD
+C_2512_6332Metric_Pad1.52x3.35mm_HandSolder
+Capacitor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+capacitor handsolder
+0
+2
+2
+Capacitor_SMD
+C_2816_7142Metric
+Capacitor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator
+capacitor
+0
+2
+2
+Capacitor_SMD
+C_2816_7142Metric_Pad3.20x4.45mm_HandSolder
+Capacitor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator
+capacitor handsolder
+0
+2
+2
+Capacitor_SMD
+C_3640_9110Metric
+Capacitor SMD 3640 (9110 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator
+capacitor
+0
+2
+2
+Capacitor_SMD
+C_3640_9110Metric_Pad2.10x10.45mm_HandSolder
+Capacitor SMD 3640 (9110 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator
+capacitor handsolder
+0
+2
+2
+Capacitor_SMD
+C_Elec_3x5.4
+SMD capacitor, aluminum electrolytic nonpolar, 3.0x5.4mm
+capacitor electrolyic nonpolar
+0
+2
+2
+Capacitor_SMD
+C_Elec_4x5.4
+SMD capacitor, aluminum electrolytic nonpolar, 4.0x5.4mm
+capacitor electrolyic nonpolar
+0
+2
+2
+Capacitor_SMD
+C_Elec_4x5.8
+SMD capacitor, aluminum electrolytic nonpolar, 4.0x5.8mm
+capacitor electrolyic nonpolar
+0
+2
+2
+Capacitor_SMD
+C_Elec_5x5.4
+SMD capacitor, aluminum electrolytic nonpolar, 5.0x5.4mm
+capacitor electrolyic nonpolar
+0
+2
+2
+Capacitor_SMD
+C_Elec_5x5.8
+SMD capacitor, aluminum electrolytic nonpolar, 5.0x5.8mm
+capacitor electrolyic nonpolar
+0
+2
+2
+Capacitor_SMD
+C_Elec_6.3x5.4
+SMD capacitor, aluminum electrolytic nonpolar, 6.3x5.4mm
+capacitor electrolyic nonpolar
+0
+2
+2
+Capacitor_SMD
+C_Elec_6.3x5.8
+SMD capacitor, aluminum electrolytic nonpolar, 6.3x5.8mm
+capacitor electrolyic nonpolar
+0
+2
+2
+Capacitor_SMD
+C_Elec_6.3x7.7
+SMD capacitor, aluminum electrolytic nonpolar, 6.3x7.7mm
+capacitor electrolyic nonpolar
+0
+2
+2
+Capacitor_SMD
+C_Elec_8x5.4
+SMD capacitor, aluminum electrolytic nonpolar, 8.0x5.4mm
+capacitor electrolyic nonpolar
+0
+2
+2
+Capacitor_SMD
+C_Elec_8x6.2
+SMD capacitor, aluminum electrolytic nonpolar, 8.0x6.2mm
+capacitor electrolyic nonpolar
+0
+2
+2
+Capacitor_SMD
+C_Elec_8x10.2
+SMD capacitor, aluminum electrolytic nonpolar, 8.0x10.2mm
+capacitor electrolyic nonpolar
+0
+2
+2
+Capacitor_SMD
+C_Elec_10x10.2
+SMD capacitor, aluminum electrolytic nonpolar, 10.0x10.2mm
+capacitor electrolyic nonpolar
+0
+2
+2
+Capacitor_SMD
+C_Trimmer_Murata_TZB4-A
+trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb
+ Murata TZB4 TZB4-A
+0
+2
+2
+Capacitor_SMD
+C_Trimmer_Murata_TZB4-B
+trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb
+ Murata TZB4 TZB4-A
+0
+2
+2
+Capacitor_SMD
+C_Trimmer_Murata_TZC3
+trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb
+ Murata TZC3
+0
+2
+2
+Capacitor_SMD
+C_Trimmer_Murata_TZR1
+trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb
+ Murata TZR1
+0
+2
+2
+Capacitor_SMD
+C_Trimmer_Murata_TZW4
+trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb
+ Murata TZW4
+0
+2
+2
+Capacitor_SMD
+C_Trimmer_Murata_TZY2
+trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb
+ Murata TZY2
+0
+2
+2
+Capacitor_SMD
+C_Trimmer_Sprague-Goodman_SGC3
+trimmer capacitor SMD horizontal, http://media.wix.com/ugd/d86717_38d9821e12823a7aa9cef38c6c2a73cc.pdf
+ Sprague Goodman SGC3
+0
+2
+2
+Capacitor_SMD
+C_Trimmer_Voltronics_JN
+trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf
+ Voltronics JN
+0
+2
+2
+Capacitor_SMD
+C_Trimmer_Voltronics_JQ
+trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf
+ Voltronics JQ
+0
+2
+2
+Capacitor_SMD
+C_Trimmer_Voltronics_JR
+trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf
+ Voltronics JR
+0
+2
+2
+Capacitor_SMD
+C_Trimmer_Voltronics_JV
+trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf
+ Voltronics JV
+0
+2
+2
+Capacitor_SMD
+C_Trimmer_Voltronics_JZ
+trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf
+ Voltronics JR
+0
+2
+2
+Capacitor_THT
+CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=10*4.5mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf
+CP Axial series Axial Horizontal pin pitch 15mm  length 10mm diameter 4.5mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L10.0mm_D6.0mm_P15.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=10*6mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf
+CP Axial series Axial Horizontal pin pitch 15mm  length 10mm diameter 6mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L11.0mm_D5.0mm_P18.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=18mm, , length*diameter=11*5mm^2, Electrolytic Capacitor
+CP Axial series Axial Horizontal pin pitch 18mm  length 11mm diameter 5mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L11.0mm_D6.0mm_P18.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=18mm, , length*diameter=11*6mm^2, Electrolytic Capacitor
+CP Axial series Axial Horizontal pin pitch 18mm  length 11mm diameter 6mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L11.0mm_D8.0mm_P15.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=11*8mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf
+CP Axial series Axial Horizontal pin pitch 15mm  length 11mm diameter 8mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L18.0mm_D6.5mm_P25.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=18*6.5mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf
+CP Axial series Axial Horizontal pin pitch 25mm  length 18mm diameter 6.5mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L18.0mm_D8.0mm_P25.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=18*8mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf
+CP Axial series Axial Horizontal pin pitch 25mm  length 18mm diameter 8mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L18.0mm_D10.0mm_P25.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=18*10mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf
+CP Axial series Axial Horizontal pin pitch 25mm  length 18mm diameter 10mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L20.0mm_D10.0mm_P26.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=26mm, , length*diameter=20*10mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf
+CP Axial series Axial Horizontal pin pitch 26mm  length 20mm diameter 10mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L20.0mm_D13.0mm_P26.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=26mm, , length*diameter=20*13mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf
+CP Axial series Axial Horizontal pin pitch 26mm  length 20mm diameter 13mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L21.0mm_D8.0mm_P28.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=28mm, , length*diameter=21*8mm^2, Electrolytic Capacitor
+CP Axial series Axial Horizontal pin pitch 28mm  length 21mm diameter 8mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L25.0mm_D10.0mm_P30.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=30mm, , length*diameter=25*10mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf
+CP Axial series Axial Horizontal pin pitch 30mm  length 25mm diameter 10mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L26.5mm_D20.0mm_P33.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=33mm, , length*diameter=26.5*20mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf
+CP Axial series Axial Horizontal pin pitch 33mm  length 26.5mm diameter 20mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L29.0mm_D10.0mm_P35.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=29*10mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf
+CP Axial series Axial Horizontal pin pitch 35mm  length 29mm diameter 10mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L29.0mm_D13.0mm_P35.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=29*13mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf
+CP Axial series Axial Horizontal pin pitch 35mm  length 29mm diameter 13mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L29.0mm_D16.0mm_P35.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=29*16mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf
+CP Axial series Axial Horizontal pin pitch 35mm  length 29mm diameter 16mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L29.0mm_D20.0mm_P35.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=29*20mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf
+CP Axial series Axial Horizontal pin pitch 35mm  length 29mm diameter 20mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L30.0mm_D10.0mm_P35.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=30*10mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf
+CP Axial series Axial Horizontal pin pitch 35mm  length 30mm diameter 10mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L30.0mm_D12.5mm_P35.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=30*12.5mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf
+CP Axial series Axial Horizontal pin pitch 35mm  length 30mm diameter 12.5mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L30.0mm_D15.0mm_P35.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=30*15mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf
+CP Axial series Axial Horizontal pin pitch 35mm  length 30mm diameter 15mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L30.0mm_D18.0mm_P35.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=30*18mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf
+CP Axial series Axial Horizontal pin pitch 35mm  length 30mm diameter 18mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L34.5mm_D20.0mm_P41.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=41mm, , length*diameter=34.5*20mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf
+CP Axial series Axial Horizontal pin pitch 41mm  length 34.5mm diameter 20mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L37.0mm_D13.0mm_P43.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=43mm, , length*diameter=37*13mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf
+CP Axial series Axial Horizontal pin pitch 43mm  length 37mm diameter 13mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L37.0mm_D16.0mm_P43.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=43mm, , length*diameter=37*16mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf
+CP Axial series Axial Horizontal pin pitch 43mm  length 37mm diameter 16mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L37.0mm_D20.0mm_P43.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=43mm, , length*diameter=37*20mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf
+CP Axial series Axial Horizontal pin pitch 43mm  length 37mm diameter 20mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L38.0mm_D18.0mm_P44.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=44mm, , length*diameter=38*18mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf
+CP Axial series Axial Horizontal pin pitch 44mm  length 38mm diameter 18mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L38.0mm_D21.0mm_P44.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=44mm, , length*diameter=38*21mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf
+CP Axial series Axial Horizontal pin pitch 44mm  length 38mm diameter 21mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L40.0mm_D16.0mm_P48.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=48mm, , length*diameter=40*16mm^2, Electrolytic Capacitor
+CP Axial series Axial Horizontal pin pitch 48mm  length 40mm diameter 16mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L42.0mm_D23.0mm_P45.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=45mm, , length*diameter=42*23.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 45mm  length 42mm diameter 23.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L42.0mm_D26.0mm_P45.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=45mm, , length*diameter=42*26mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 45mm  length 42mm diameter 26mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L42.0mm_D29.0mm_P45.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=45mm, , length*diameter=42*29.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 45mm  length 42mm diameter 29.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L42.0mm_D32.0mm_P45.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=45mm, , length*diameter=42*32.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 45mm  length 42mm diameter 32.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L42.0mm_D35.0mm_P45.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=45mm, , length*diameter=42*35.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 45mm  length 42mm diameter 35.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L42.5mm_D20.0mm_P49.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=49mm, , length*diameter=42.5*20mm^2, Electrolytic Capacitor
+CP Axial series Axial Horizontal pin pitch 49mm  length 42.5mm diameter 20mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L46.0mm_D20.0mm_P52.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=52mm, , length*diameter=46*20mm^2, Electrolytic Capacitor
+CP Axial series Axial Horizontal pin pitch 52mm  length 46mm diameter 20mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L55.0mm_D23.0mm_P60.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=60mm, , length*diameter=55*23.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 60mm  length 55mm diameter 23.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L55.0mm_D26.0mm_P60.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=60mm, , length*diameter=55*26mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 60mm  length 55mm diameter 26mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L55.0mm_D29.0mm_P60.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=60mm, , length*diameter=55*29.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 60mm  length 55mm diameter 29.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L55.0mm_D32.0mm_P60.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=60mm, , length*diameter=55*32.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 60mm  length 55mm diameter 32.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L55.0mm_D35.0mm_P60.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=60mm, , length*diameter=55*35.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 60mm  length 55mm diameter 35.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L67.0mm_D23.0mm_P75.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=75mm, , length*diameter=67*23.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 75mm  length 67mm diameter 23.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L67.0mm_D26.0mm_P75.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=75mm, , length*diameter=67*26mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 75mm  length 67mm diameter 26mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L67.0mm_D29.0mm_P75.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=75mm, , length*diameter=67*29.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 75mm  length 67mm diameter 29.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L67.0mm_D32.0mm_P75.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=75mm, , length*diameter=67*32.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 75mm  length 67mm diameter 32.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L67.0mm_D35.0mm_P75.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=75mm, , length*diameter=67*35.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 75mm  length 67mm diameter 35.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L80.0mm_D23.0mm_P85.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=85mm, , length*diameter=80*23.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 85mm  length 80mm diameter 23.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L80.0mm_D26.0mm_P85.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=85mm, , length*diameter=80*26mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 85mm  length 80mm diameter 26mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L80.0mm_D29.0mm_P85.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=85mm, , length*diameter=80*29.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 85mm  length 80mm diameter 29.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L80.0mm_D32.0mm_P85.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=85mm, , length*diameter=80*32.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 85mm  length 80mm diameter 32.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L80.0mm_D35.0mm_P85.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=85mm, , length*diameter=80*35.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 85mm  length 80mm diameter 35.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L93.0mm_D23.0mm_P100.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=100mm, , length*diameter=93*23.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 100mm  length 93mm diameter 23.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L93.0mm_D26.0mm_P100.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=100mm, , length*diameter=93*26mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 100mm  length 93mm diameter 26mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L93.0mm_D29.0mm_P100.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=100mm, , length*diameter=93*29.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 100mm  length 93mm diameter 29.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L93.0mm_D32.0mm_P100.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=100mm, , length*diameter=93*32.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 100mm  length 93mm diameter 32.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Axial_L93.0mm_D35.0mm_P100.00mm_Horizontal
+CP, Axial series, Axial, Horizontal, pin pitch=100mm, , length*diameter=93*35.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf
+CP Axial series Axial Horizontal pin pitch 100mm  length 93mm diameter 35.0mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D4.0mm_P1.50mm
+CP, Radial series, Radial, pin pitch=1.50mm, , diameter=4mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 1.50mm  diameter 4mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D4.0mm_P2.00mm
+CP, Radial series, Radial, pin pitch=2.00mm, , diameter=4mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 2.00mm  diameter 4mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D5.0mm_P2.00mm
+CP, Radial series, Radial, pin pitch=2.00mm, , diameter=5mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 2.00mm  diameter 5mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D5.0mm_P2.50mm
+CP, Radial series, Radial, pin pitch=2.50mm, , diameter=5mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 2.50mm  diameter 5mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D6.3mm_P2.50mm
+CP, Radial series, Radial, pin pitch=2.50mm, , diameter=6.3mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 2.50mm  diameter 6.3mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D7.5mm_P2.50mm
+CP, Radial series, Radial, pin pitch=2.50mm, , diameter=7.5mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 2.50mm  diameter 7.5mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D8.0mm_P2.50mm
+CP, Radial series, Radial, pin pitch=2.50mm, , diameter=8mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 2.50mm  diameter 8mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D8.0mm_P3.50mm
+CP, Radial series, Radial, pin pitch=3.50mm, , diameter=8mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 3.50mm  diameter 8mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D8.0mm_P3.80mm
+CP, Radial series, Radial, pin pitch=3.80mm, , diameter=8mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 3.80mm  diameter 8mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D8.0mm_P5.00mm
+CP, Radial series, Radial, pin pitch=5.00mm, , diameter=8mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 5.00mm  diameter 8mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D10.0mm_P2.50mm
+CP, Radial series, Radial, pin pitch=2.50mm, , diameter=10mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 2.50mm  diameter 10mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D10.0mm_P2.50mm_P5.00mm
+CP, Radial series, Radial, pin pitch=2.50mm 5.00mm, , diameter=10mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 2.50mm 5.00mm  diameter 10mm Electrolytic Capacitor
+0
+4
+2
+Capacitor_THT
+CP_Radial_D10.0mm_P3.50mm
+CP, Radial series, Radial, pin pitch=3.50mm, , diameter=10mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 3.50mm  diameter 10mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D10.0mm_P3.80mm
+CP, Radial series, Radial, pin pitch=3.80mm, , diameter=10mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 3.80mm  diameter 10mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D10.0mm_P5.00mm
+CP, Radial series, Radial, pin pitch=5.00mm, , diameter=10mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 5.00mm  diameter 10mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D10.0mm_P5.00mm_P7.50mm
+CP, Radial series, Radial, pin pitch=5.00mm 7.50mm, , diameter=10mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 5.00mm 7.50mm  diameter 10mm Electrolytic Capacitor
+0
+4
+2
+Capacitor_THT
+CP_Radial_D10.0mm_P7.50mm
+CP, Radial series, Radial, pin pitch=7.50mm, , diameter=10mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 7.50mm  diameter 10mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D12.5mm_P2.50mm
+CP, Radial series, Radial, pin pitch=2.50mm, , diameter=12.5mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 2.50mm  diameter 12.5mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D12.5mm_P5.00mm
+CP, Radial series, Radial, pin pitch=5.00mm, , diameter=12.5mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 5.00mm  diameter 12.5mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D12.5mm_P7.50mm
+CP, Radial series, Radial, pin pitch=7.50mm, , diameter=12.5mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 7.50mm  diameter 12.5mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D13.0mm_P2.50mm
+CP, Radial series, Radial, pin pitch=2.50mm, , diameter=13mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 2.50mm  diameter 13mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D13.0mm_P5.00mm
+CP, Radial series, Radial, pin pitch=5.00mm, , diameter=13mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 5.00mm  diameter 13mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D13.0mm_P7.50mm
+CP, Radial series, Radial, pin pitch=7.50mm, , diameter=13mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 7.50mm  diameter 13mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D14.0mm_P5.00mm
+CP, Radial series, Radial, pin pitch=5.00mm, , diameter=14mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 5.00mm  diameter 14mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D14.0mm_P7.50mm
+CP, Radial series, Radial, pin pitch=7.50mm, , diameter=14mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 7.50mm  diameter 14mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D16.0mm_P7.50mm
+CP, Radial series, Radial, pin pitch=7.50mm, , diameter=16mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 7.50mm  diameter 16mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D17.0mm_P7.50mm
+CP, Radial series, Radial, pin pitch=7.50mm, , diameter=17mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 7.50mm  diameter 17mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D18.0mm_P7.50mm
+CP, Radial series, Radial, pin pitch=7.50mm, , diameter=18mm, Electrolytic Capacitor
+CP Radial series Radial pin pitch 7.50mm  diameter 18mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D22.0mm_P10.00mm_3pin_SnapIn
+CP, Radial series, Radial, pin pitch=10.00mm, , diameter=22mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf
+CP Radial series Radial pin pitch 10.00mm  diameter 22mm Electrolytic Capacitor
+0
+3
+2
+Capacitor_THT
+CP_Radial_D22.0mm_P10.00mm_SnapIn
+CP, Radial series, Radial, pin pitch=10.00mm, , diameter=22mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf
+CP Radial series Radial pin pitch 10.00mm  diameter 22mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D24.0mm_P10.00mm_3pin_SnapIn
+CP, Radial series, Radial, pin pitch=10.00mm, , diameter=24mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf
+CP Radial series Radial pin pitch 10.00mm  diameter 24mm Electrolytic Capacitor
+0
+3
+2
+Capacitor_THT
+CP_Radial_D24.0mm_P10.00mm_SnapIn
+CP, Radial series, Radial, pin pitch=10.00mm, , diameter=24mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf
+CP Radial series Radial pin pitch 10.00mm  diameter 24mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D25.0mm_P10.00mm_3pin_SnapIn
+CP, Radial series, Radial, pin pitch=10.00mm, , diameter=25mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf
+CP Radial series Radial pin pitch 10.00mm  diameter 25mm Electrolytic Capacitor
+0
+3
+2
+Capacitor_THT
+CP_Radial_D25.0mm_P10.00mm_SnapIn
+CP, Radial series, Radial, pin pitch=10.00mm, , diameter=25mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf
+CP Radial series Radial pin pitch 10.00mm  diameter 25mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D26.0mm_P10.00mm_3pin_SnapIn
+CP, Radial series, Radial, pin pitch=10.00mm, , diameter=26mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf
+CP Radial series Radial pin pitch 10.00mm  diameter 26mm Electrolytic Capacitor
+0
+3
+2
+Capacitor_THT
+CP_Radial_D26.0mm_P10.00mm_SnapIn
+CP, Radial series, Radial, pin pitch=10.00mm, , diameter=26mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf
+CP Radial series Radial pin pitch 10.00mm  diameter 26mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D30.0mm_P10.00mm_3pin_SnapIn
+CP, Radial series, Radial, pin pitch=10.00mm, , diameter=30mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf
+CP Radial series Radial pin pitch 10.00mm  diameter 30mm Electrolytic Capacitor
+0
+3
+2
+Capacitor_THT
+CP_Radial_D30.0mm_P10.00mm_SnapIn
+CP, Radial series, Radial, pin pitch=10.00mm, , diameter=30mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf
+CP Radial series Radial pin pitch 10.00mm  diameter 30mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D35.0mm_P10.00mm_3pin_SnapIn
+CP, Radial series, Radial, pin pitch=10.00mm, , diameter=35mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf
+CP Radial series Radial pin pitch 10.00mm  diameter 35mm Electrolytic Capacitor
+0
+3
+2
+Capacitor_THT
+CP_Radial_D35.0mm_P10.00mm_SnapIn
+CP, Radial series, Radial, pin pitch=10.00mm, , diameter=35mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf
+CP Radial series Radial pin pitch 10.00mm  diameter 35mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_D40.0mm_P10.00mm_3pin_SnapIn
+CP, Radial series, Radial, pin pitch=10.00mm, , diameter=40mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf
+CP Radial series Radial pin pitch 10.00mm  diameter 40mm Electrolytic Capacitor
+0
+3
+2
+Capacitor_THT
+CP_Radial_D40.0mm_P10.00mm_SnapIn
+CP, Radial series, Radial, pin pitch=10.00mm, , diameter=40mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf
+CP Radial series Radial pin pitch 10.00mm  diameter 40mm Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_Tantal_D4.5mm_P2.50mm
+CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=4.5mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf
+CP Radial_Tantal series Radial pin pitch 2.50mm  diameter 4.5mm Tantal Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_Tantal_D4.5mm_P5.00mm
+CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=4.5mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf
+CP Radial_Tantal series Radial pin pitch 5.00mm  diameter 4.5mm Tantal Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_Tantal_D5.0mm_P2.50mm
+CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=5.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf
+CP Radial_Tantal series Radial pin pitch 2.50mm  diameter 5.0mm Tantal Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_Tantal_D5.0mm_P5.00mm
+CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=5.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf
+CP Radial_Tantal series Radial pin pitch 5.00mm  diameter 5.0mm Tantal Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_Tantal_D5.5mm_P2.50mm
+CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=5.5mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf
+CP Radial_Tantal series Radial pin pitch 2.50mm  diameter 5.5mm Tantal Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_Tantal_D5.5mm_P5.00mm
+CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=5.5mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf
+CP Radial_Tantal series Radial pin pitch 5.00mm  diameter 5.5mm Tantal Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_Tantal_D6.0mm_P2.50mm
+CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=6.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf
+CP Radial_Tantal series Radial pin pitch 2.50mm  diameter 6.0mm Tantal Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_Tantal_D6.0mm_P5.00mm
+CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=6.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf
+CP Radial_Tantal series Radial pin pitch 5.00mm  diameter 6.0mm Tantal Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_Tantal_D7.0mm_P2.50mm
+CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=7.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf
+CP Radial_Tantal series Radial pin pitch 2.50mm  diameter 7.0mm Tantal Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_Tantal_D7.0mm_P5.00mm
+CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=7.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf
+CP Radial_Tantal series Radial pin pitch 5.00mm  diameter 7.0mm Tantal Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_Tantal_D8.0mm_P2.50mm
+CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=8.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf
+CP Radial_Tantal series Radial pin pitch 2.50mm  diameter 8.0mm Tantal Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_Tantal_D8.0mm_P5.00mm
+CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=8.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf
+CP Radial_Tantal series Radial pin pitch 5.00mm  diameter 8.0mm Tantal Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_Tantal_D9.0mm_P2.50mm
+CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=9.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf
+CP Radial_Tantal series Radial pin pitch 2.50mm  diameter 9.0mm Tantal Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_Tantal_D9.0mm_P5.00mm
+CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=9.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf
+CP Radial_Tantal series Radial pin pitch 5.00mm  diameter 9.0mm Tantal Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_Tantal_D10.5mm_P2.50mm
+CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=10.5mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf
+CP Radial_Tantal series Radial pin pitch 2.50mm  diameter 10.5mm Tantal Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+CP_Radial_Tantal_D10.5mm_P5.00mm
+CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=10.5mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf
+CP Radial_Tantal series Radial pin pitch 5.00mm  diameter 10.5mm Tantal Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Axial_L3.8mm_D2.6mm_P7.50mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=7.5mm, , length*diameter=3.8*2.6mm^2, http://www.vishay.com/docs/45231/arseries.pdf
+C Axial series Axial Horizontal pin pitch 7.5mm  length 3.8mm diameter 2.6mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L3.8mm_D2.6mm_P10.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=10mm, , length*diameter=3.8*2.6mm^2, http://www.vishay.com/docs/45231/arseries.pdf
+C Axial series Axial Horizontal pin pitch 10mm  length 3.8mm diameter 2.6mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L3.8mm_D2.6mm_P12.50mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=12.5mm, , length*diameter=3.8*2.6mm^2, http://www.vishay.com/docs/45231/arseries.pdf
+C Axial series Axial Horizontal pin pitch 12.5mm  length 3.8mm diameter 2.6mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L3.8mm_D2.6mm_P15.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=3.8*2.6mm^2, http://www.vishay.com/docs/45231/arseries.pdf
+C Axial series Axial Horizontal pin pitch 15mm  length 3.8mm diameter 2.6mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L5.1mm_D3.1mm_P7.50mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=7.5mm, , length*diameter=5.1*3.1mm^2, http://www.vishay.com/docs/45231/arseries.pdf
+C Axial series Axial Horizontal pin pitch 7.5mm  length 5.1mm diameter 3.1mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L5.1mm_D3.1mm_P10.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=10mm, , length*diameter=5.1*3.1mm^2, http://www.vishay.com/docs/45231/arseries.pdf
+C Axial series Axial Horizontal pin pitch 10mm  length 5.1mm diameter 3.1mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L5.1mm_D3.1mm_P12.50mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=12.5mm, , length*diameter=5.1*3.1mm^2, http://www.vishay.com/docs/45231/arseries.pdf
+C Axial series Axial Horizontal pin pitch 12.5mm  length 5.1mm diameter 3.1mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L5.1mm_D3.1mm_P15.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=5.1*3.1mm^2, http://www.vishay.com/docs/45231/arseries.pdf
+C Axial series Axial Horizontal pin pitch 15mm  length 5.1mm diameter 3.1mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L12.0mm_D6.5mm_P15.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=12*6.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 15mm  length 12mm diameter 6.5mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L12.0mm_D6.5mm_P20.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=12*6.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 20mm  length 12mm diameter 6.5mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L12.0mm_D7.5mm_P15.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=12*7.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 15mm  length 12mm diameter 7.5mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L12.0mm_D7.5mm_P20.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=12*7.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 20mm  length 12mm diameter 7.5mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L12.0mm_D8.5mm_P15.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=12*8.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 15mm  length 12mm diameter 8.5mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L12.0mm_D8.5mm_P20.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=12*8.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 20mm  length 12mm diameter 8.5mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L12.0mm_D9.5mm_P15.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=12*9.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 15mm  length 12mm diameter 9.5mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L12.0mm_D9.5mm_P20.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=12*9.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 20mm  length 12mm diameter 9.5mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L12.0mm_D10.5mm_P15.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=12*10.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 15mm  length 12mm diameter 10.5mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L12.0mm_D10.5mm_P20.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=12*10.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 20mm  length 12mm diameter 10.5mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L17.0mm_D6.5mm_P20.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=17*6.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 20mm  length 17mm diameter 6.5mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L17.0mm_D6.5mm_P25.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=17*6.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 25mm  length 17mm diameter 6.5mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L17.0mm_D7.0mm_P20.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=17*7.0mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 20mm  length 17mm diameter 7.0mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L17.0mm_D7.0mm_P25.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=17*7.0mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 25mm  length 17mm diameter 7.0mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L19.0mm_D7.5mm_P25.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=19*7.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 25mm  length 19mm diameter 7.5mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L19.0mm_D8.0mm_P25.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=19*8.0mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 25mm  length 19mm diameter 8.0mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L19.0mm_D9.0mm_P25.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=19*9mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 25mm  length 19mm diameter 9mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L19.0mm_D9.5mm_P25.00mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=19*9.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 25mm  length 19mm diameter 9.5mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L22.0mm_D9.5mm_P27.50mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=27.5mm, , length*diameter=22*9.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 27.5mm  length 22mm diameter 9.5mm
+0
+2
+2
+Capacitor_THT
+C_Axial_L22.0mm_D10.5mm_P27.50mm_Horizontal
+C, Axial series, Axial, Horizontal, pin pitch=27.5mm, , length*diameter=22*10.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf
+C Axial series Axial Horizontal pin pitch 27.5mm  length 22mm diameter 10.5mm
+0
+2
+2
+Capacitor_THT
+C_Disc_D3.0mm_W1.6mm_P2.50mm
+C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.0*1.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf
+C Disc series Radial pin pitch 2.50mm  diameter 3.0mm width 1.6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D3.0mm_W2.0mm_P2.50mm
+C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3*2mm^2, Capacitor
+C Disc series Radial pin pitch 2.50mm  diameter 3mm width 2mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D3.4mm_W2.1mm_P2.50mm
+C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.4*2.1mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf
+C Disc series Radial pin pitch 2.50mm  diameter 3.4mm width 2.1mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D3.8mm_W2.6mm_P2.50mm
+C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf
+C Disc series Radial pin pitch 2.50mm  diameter 3.8mm width 2.6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D4.3mm_W1.9mm_P5.00mm
+C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=4.3*1.9mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf
+C Disc series Radial pin pitch 5.00mm  diameter 4.3mm width 1.9mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D4.7mm_W2.5mm_P5.00mm
+C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=4.7*2.5mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf
+C Disc series Radial pin pitch 5.00mm  diameter 4.7mm width 2.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D5.0mm_W2.5mm_P2.50mm
+C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf
+C Disc series Radial pin pitch 2.50mm  diameter 5mm width 2.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D5.0mm_W2.5mm_P5.00mm
+C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf
+C Disc series Radial pin pitch 5.00mm  diameter 5mm width 2.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D5.1mm_W3.2mm_P5.00mm
+C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5.1*3.2mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf
+C Disc series Radial pin pitch 5.00mm  diameter 5.1mm width 3.2mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D6.0mm_W2.5mm_P5.00mm
+C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=6*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf
+C Disc series Radial pin pitch 5.00mm  diameter 6mm width 2.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D6.0mm_W4.4mm_P5.00mm
+C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=6*4.4mm^2, Capacitor
+C Disc series Radial pin pitch 5.00mm  diameter 6mm width 4.4mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D7.0mm_W2.5mm_P5.00mm
+C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=7*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf
+C Disc series Radial pin pitch 5.00mm  diameter 7mm width 2.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D7.5mm_W2.5mm_P5.00mm
+C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=7.5*2.5mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 5.00mm  diameter 7.5mm width 2.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D7.5mm_W4.4mm_P5.00mm
+C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=7.5*4.4mm^2, Capacitor
+C Disc series Radial pin pitch 5.00mm  diameter 7.5mm width 4.4mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D7.5mm_W5.0mm_P5.00mm
+C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=7.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 5.00mm  diameter 7.5mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D7.5mm_W5.0mm_P7.50mm
+C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=7.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 7.50mm  diameter 7.5mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D7.5mm_W5.0mm_P10.00mm
+C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=7.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 10.00mm  diameter 7.5mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D8.0mm_W2.5mm_P5.00mm
+C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=8*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf
+C Disc series Radial pin pitch 5.00mm  diameter 8mm width 2.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D8.0mm_W5.0mm_P5.00mm
+C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=8*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 5.00mm  diameter 8mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D8.0mm_W5.0mm_P7.50mm
+C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=8*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 7.50mm  diameter 8mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D8.0mm_W5.0mm_P10.00mm
+C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=8*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 10.00mm  diameter 8mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D9.0mm_W2.5mm_P5.00mm
+C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=9*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf
+C Disc series Radial pin pitch 5.00mm  diameter 9mm width 2.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D9.0mm_W5.0mm_P5.00mm
+C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=9*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 5.00mm  diameter 9mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D9.0mm_W5.0mm_P7.50mm
+C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=9*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 7.50mm  diameter 9mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D9.0mm_W5.0mm_P10.00mm
+C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=9*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 10.00mm  diameter 9mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D10.0mm_W2.5mm_P5.00mm
+C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=10*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf
+C Disc series Radial pin pitch 5.00mm  diameter 10mm width 2.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D10.5mm_W5.0mm_P5.00mm
+C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=10.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 5.00mm  diameter 10.5mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D10.5mm_W5.0mm_P7.50mm
+C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=10.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 7.50mm  diameter 10.5mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D10.5mm_W5.0mm_P10.00mm
+C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=10.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 10.00mm  diameter 10.5mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D11.0mm_W5.0mm_P5.00mm
+C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=11*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 5.00mm  diameter 11mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D11.0mm_W5.0mm_P7.50mm
+C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=11*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 7.50mm  diameter 11mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D11.0mm_W5.0mm_P10.00mm
+C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=11*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 10.00mm  diameter 11mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D12.0mm_W4.4mm_P7.75mm
+C, Disc series, Radial, pin pitch=7.75mm, , diameter*width=12*4.4mm^2, Capacitor
+C Disc series Radial pin pitch 7.75mm  diameter 12mm width 4.4mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D12.5mm_W5.0mm_P7.50mm
+C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=12.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 7.50mm  diameter 12.5mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D12.5mm_W5.0mm_P10.00mm
+C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=12.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 10.00mm  diameter 12.5mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D14.5mm_W5.0mm_P7.50mm
+C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=14.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 7.50mm  diameter 14.5mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D14.5mm_W5.0mm_P10.00mm
+C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=14.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 10.00mm  diameter 14.5mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D16.0mm_W5.0mm_P7.50mm
+C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=16.0*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 7.50mm  diameter 16.0mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Disc_D16.0mm_W5.0mm_P10.00mm
+C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=16.0*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf
+C Disc series Radial pin pitch 10.00mm  diameter 16.0mm width 5.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Radial_D4.0mm_H5.0mm_P1.50mm
+C, Radial series, Radial, pin pitch=1.50mm, diameter=4mm, height=5mm, Non-Polar Electrolytic Capacitor
+C Radial series Radial pin pitch 1.50mm diameter 4mm height 5mm Non-Polar Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Radial_D4.0mm_H7.0mm_P1.50mm
+C, Radial series, Radial, pin pitch=1.50mm, diameter=4mm, height=7mm, Non-Polar Electrolytic Capacitor
+C Radial series Radial pin pitch 1.50mm diameter 4mm height 7mm Non-Polar Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Radial_D5.0mm_H5.0mm_P2.00mm
+C, Radial series, Radial, pin pitch=2.00mm, diameter=5mm, height=5mm, Non-Polar Electrolytic Capacitor
+C Radial series Radial pin pitch 2.00mm diameter 5mm height 5mm Non-Polar Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Radial_D5.0mm_H7.0mm_P2.00mm
+C, Radial series, Radial, pin pitch=2.00mm, diameter=5mm, height=7mm, Non-Polar Electrolytic Capacitor
+C Radial series Radial pin pitch 2.00mm diameter 5mm height 7mm Non-Polar Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Radial_D5.0mm_H11.0mm_P2.00mm
+C, Radial series, Radial, pin pitch=2.00mm, diameter=5mm, height=11mm, Non-Polar Electrolytic Capacitor
+C Radial series Radial pin pitch 2.00mm diameter 5mm height 11mm Non-Polar Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Radial_D6.3mm_H5.0mm_P2.50mm
+C, Radial series, Radial, pin pitch=2.50mm, diameter=6.3mm, height=5mm, Non-Polar Electrolytic Capacitor
+C Radial series Radial pin pitch 2.50mm diameter 6.3mm height 5mm Non-Polar Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Radial_D6.3mm_H7.0mm_P2.50mm
+C, Radial series, Radial, pin pitch=2.50mm, diameter=6.3mm, height=7mm, Non-Polar Electrolytic Capacitor
+C Radial series Radial pin pitch 2.50mm diameter 6.3mm height 7mm Non-Polar Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Radial_D6.3mm_H11.0mm_P2.50mm
+C, Radial series, Radial, pin pitch=2.50mm, diameter=6.3mm, height=11mm, Non-Polar Electrolytic Capacitor
+C Radial series Radial pin pitch 2.50mm diameter 6.3mm height 11mm Non-Polar Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Radial_D8.0mm_H7.0mm_P3.50mm
+C, Radial series, Radial, pin pitch=3.50mm, diameter=8mm, height=7mm, Non-Polar Electrolytic Capacitor
+C Radial series Radial pin pitch 3.50mm diameter 8mm height 7mm Non-Polar Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Radial_D8.0mm_H11.5mm_P3.50mm
+C, Radial series, Radial, pin pitch=3.50mm, diameter=8mm, height=11.5mm, Non-Polar Electrolytic Capacitor
+C Radial series Radial pin pitch 3.50mm diameter 8mm height 11.5mm Non-Polar Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Radial_D10.0mm_H12.5mm_P5.00mm
+C, Radial series, Radial, pin pitch=5.00mm, diameter=10mm, height=12.5mm, Non-Polar Electrolytic Capacitor
+C Radial series Radial pin pitch 5.00mm diameter 10mm height 12.5mm Non-Polar Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Radial_D10.0mm_H16.0mm_P5.00mm
+C, Radial series, Radial, pin pitch=5.00mm, diameter=10mm, height=16mm, Non-Polar Electrolytic Capacitor
+C Radial series Radial pin pitch 5.00mm diameter 10mm height 16mm Non-Polar Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Radial_D10.0mm_H20.0mm_P5.00mm
+C, Radial series, Radial, pin pitch=5.00mm, diameter=10mm, height=20mm, Non-Polar Electrolytic Capacitor
+C Radial series Radial pin pitch 5.00mm diameter 10mm height 20mm Non-Polar Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Radial_D12.5mm_H20.0mm_P5.00mm
+C, Radial series, Radial, pin pitch=5.00mm, diameter=12.5mm, height=20mm, Non-Polar Electrolytic Capacitor
+C Radial series Radial pin pitch 5.00mm diameter 12.5mm height 20mm Non-Polar Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Radial_D12.5mm_H25.0mm_P5.00mm
+C, Radial series, Radial, pin pitch=5.00mm, diameter=12.5mm, height=25mm, Non-Polar Electrolytic Capacitor
+C Radial series Radial pin pitch 5.00mm diameter 12.5mm height 25mm Non-Polar Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Radial_D16.0mm_H25.0mm_P7.50mm
+C, Radial series, Radial, pin pitch=7.50mm, diameter=16mm, height=25mm, Non-Polar Electrolytic Capacitor
+C Radial series Radial pin pitch 7.50mm diameter 16mm height 25mm Non-Polar Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Radial_D16.0mm_H31.5mm_P7.50mm
+C, Radial series, Radial, pin pitch=7.50mm, diameter=16mm, height=31.5mm, Non-Polar Electrolytic Capacitor
+C Radial series Radial pin pitch 7.50mm diameter 16mm height 31.5mm Non-Polar Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Radial_D18.0mm_H35.5mm_P7.50mm
+C, Radial series, Radial, pin pitch=7.50mm, diameter=18mm, height=35.5mm, Non-Polar Electrolytic Capacitor
+C Radial series Radial pin pitch 7.50mm diameter 18mm height 35.5mm Non-Polar Electrolytic Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L4.0mm_W2.5mm_P2.50mm
+C, Rect series, Radial, pin pitch=2.50mm, , length*width=4*2.5mm^2, Capacitor
+C Rect series Radial pin pitch 2.50mm  length 4mm width 2.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L4.6mm_W2.0mm_P2.50mm_MKS02_FKP02
+C, Rect series, Radial, pin pitch=2.50mm, , length*width=4.6*2mm^2, Capacitor, http://www.wima.de/DE/WIMA_MKS_02.pdf
+C Rect series Radial pin pitch 2.50mm  length 4.6mm width 2mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L4.6mm_W3.0mm_P2.50mm_MKS02_FKP02
+C, Rect series, Radial, pin pitch=2.50mm, , length*width=4.6*3.0mm^2, Capacitor, http://www.wima.de/DE/WIMA_MKS_02.pdf
+C Rect series Radial pin pitch 2.50mm  length 4.6mm width 3.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L4.6mm_W3.8mm_P2.50mm_MKS02_FKP02
+C, Rect series, Radial, pin pitch=2.50mm, , length*width=4.6*3.8mm^2, Capacitor, http://www.wima.de/DE/WIMA_MKS_02.pdf
+C Rect series Radial pin pitch 2.50mm  length 4.6mm width 3.8mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L4.6mm_W4.6mm_P2.50mm_MKS02_FKP02
+C, Rect series, Radial, pin pitch=2.50mm, , length*width=4.6*4.6mm^2, Capacitor, http://www.wima.de/DE/WIMA_MKS_02.pdf
+C Rect series Radial pin pitch 2.50mm  length 4.6mm width 4.6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L4.6mm_W5.5mm_P2.50mm_MKS02_FKP02
+C, Rect series, Radial, pin pitch=2.50mm, , length*width=4.6*5.5mm^2, Capacitor, http://www.wima.de/DE/WIMA_MKS_02.pdf
+C Rect series Radial pin pitch 2.50mm  length 4.6mm width 5.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L7.0mm_W2.0mm_P5.00mm
+C, Rect series, Radial, pin pitch=5.00mm, , length*width=7*2mm^2, Capacitor
+C Rect series Radial pin pitch 5.00mm  length 7mm width 2mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L7.0mm_W2.5mm_P5.00mm
+C, Rect series, Radial, pin pitch=5.00mm, , length*width=7*2.5mm^2, Capacitor
+C Rect series Radial pin pitch 5.00mm  length 7mm width 2.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L7.0mm_W3.5mm_P2.50mm_P5.00mm
+C, Rect series, Radial, pin pitch=2.50mm 5.00mm, , length*width=7*3.5mm^2, Capacitor
+C Rect series Radial pin pitch 2.50mm 5.00mm  length 7mm width 3.5mm Capacitor
+0
+4
+2
+Capacitor_THT
+C_Rect_L7.0mm_W3.5mm_P5.00mm
+C, Rect series, Radial, pin pitch=5.00mm, , length*width=7*3.5mm^2, Capacitor
+C Rect series Radial pin pitch 5.00mm  length 7mm width 3.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L7.0mm_W4.5mm_P5.00mm
+C, Rect series, Radial, pin pitch=5.00mm, , length*width=7*4.5mm^2, Capacitor
+C Rect series Radial pin pitch 5.00mm  length 7mm width 4.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L7.0mm_W6.0mm_P5.00mm
+C, Rect series, Radial, pin pitch=5.00mm, , length*width=7*6mm^2, Capacitor
+C Rect series Radial pin pitch 5.00mm  length 7mm width 6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L7.0mm_W6.5mm_P5.00mm
+C, Rect series, Radial, pin pitch=5.00mm, , length*width=7*6.5mm^2, Capacitor
+C Rect series Radial pin pitch 5.00mm  length 7mm width 6.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L7.2mm_W2.5mm_P5.00mm_FKS2_FKP2_MKS2_MKP2
+C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*2.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf
+C Rect series Radial pin pitch 5.00mm  length 7.2mm width 2.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L7.2mm_W3.0mm_P5.00mm_FKS2_FKP2_MKS2_MKP2
+C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*3.0mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf
+C Rect series Radial pin pitch 5.00mm  length 7.2mm width 3.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L7.2mm_W3.5mm_P5.00mm_FKS2_FKP2_MKS2_MKP2
+C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*3.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf
+C Rect series Radial pin pitch 5.00mm  length 7.2mm width 3.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L7.2mm_W4.5mm_P5.00mm_FKS2_FKP2_MKS2_MKP2
+C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*4.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf
+C Rect series Radial pin pitch 5.00mm  length 7.2mm width 4.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L7.2mm_W5.5mm_P5.00mm_FKS2_FKP2_MKS2_MKP2
+C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*5.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf
+C Rect series Radial pin pitch 5.00mm  length 7.2mm width 5.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L7.2mm_W7.2mm_P5.00mm_FKS2_FKP2_MKS2_MKP2
+C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*7.2mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf
+C Rect series Radial pin pitch 5.00mm  length 7.2mm width 7.2mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L7.2mm_W8.5mm_P5.00mm_FKP2_FKP2_MKS2_MKP2
+C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*8.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf
+C Rect series Radial pin pitch 5.00mm  length 7.2mm width 8.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L7.2mm_W11.0mm_P5.00mm_FKS2_FKP2_MKS2_MKP2
+C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*11mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf
+C Rect series Radial pin pitch 5.00mm  length 7.2mm width 11mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L7.5mm_W6.5mm_P5.00mm
+C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.5*6.5mm^2, Capacitor
+C Rect series Radial pin pitch 5.00mm  length 7.5mm width 6.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W2.5mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*2.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 2.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W2.6mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*2.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 2.6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W2.7mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*2.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 2.7mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W3.2mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*3.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 3.2mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W3.3mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*3.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 3.3mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W3.4mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*3.4mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 3.4mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W3.6mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*3.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 3.6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W3.8mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*3.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 3.8mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W3.9mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*3.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 3.9mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W4.0mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*4.0mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 4.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W4.2mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*4.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 4.2mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W4.9mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*4.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 4.9mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W5.1mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*5.1mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 5.1mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W5.7mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*5.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 5.7mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W6.4mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*6.4mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 6.4mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W6.7mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*6.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 6.7mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W7.7mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*7.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 7.7mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W8.5mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*8.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 8.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W9.5mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*9.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 9.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L9.0mm_W9.8mm_P7.50mm_MKT
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*9.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 7.50mm  length 9mm width 9.8mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L10.0mm_W2.5mm_P7.50mm_MKS4
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=10*2.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 7.50mm  length 10mm width 2.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L10.0mm_W3.0mm_P7.50mm_FKS3_FKP3
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=10*3mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf
+C Rect series Radial pin pitch 7.50mm  length 10mm width 3mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L10.0mm_W3.0mm_P7.50mm_MKS4
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=10*3.0mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 7.50mm  length 10mm width 3.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L10.0mm_W4.0mm_P7.50mm_FKS3_FKP3
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=10*4mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf
+C Rect series Radial pin pitch 7.50mm  length 10mm width 4mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L10.0mm_W4.0mm_P7.50mm_MKS4
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=10*4.0mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 7.50mm  length 10mm width 4.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L10.0mm_W5.0mm_P5.00mm_P7.50mm
+C, Rect series, Radial, pin pitch=5.00mm 7.50mm, , length*width=10*5mm^2, Capacitor
+C Rect series Radial pin pitch 5.00mm 7.50mm  length 10mm width 5mm Capacitor
+0
+4
+2
+Capacitor_THT
+C_Rect_L10.3mm_W4.5mm_P7.50mm_MKS4
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=10.3*4.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 7.50mm  length 10.3mm width 4.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L10.3mm_W5.0mm_P7.50mm_MKS4
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=10.3*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 7.50mm  length 10.3mm width 5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L10.3mm_W5.7mm_P7.50mm_MKS4
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=10.3*5.7mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 7.50mm  length 10.3mm width 5.7mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L10.3mm_W7.2mm_P7.50mm_MKS4
+C, Rect series, Radial, pin pitch=7.50mm, , length*width=10.3*7.2mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 7.50mm  length 10.3mm width 7.2mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.0mm_W2.8mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*2.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.0mm width 2.8mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.0mm_W3.4mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*3.4mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.0mm width 3.4mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.0mm_W3.5mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*3.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.0mm width 3.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.0mm_W4.2mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*4.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.0mm width 4.2mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.0mm_W4.3mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*4.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.0mm width 4.3mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.0mm_W5.1mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*5.1mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.0mm width 5.1mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.0mm_W5.3mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*5.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.0mm width 5.3mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.0mm_W6.3mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*6.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.0mm width 6.3mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.0mm_W6.4mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*6.4mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.0mm width 6.4mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.0mm_W7.3mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*7.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.0mm width 7.3mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.0mm_W8.8mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*8.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.0mm width 8.8mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W2.0mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 2mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W2.6mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*2.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 2.6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W2.8mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*2.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 2.8mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W3.2mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*3.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 3.2mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W3.5mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*3.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 3.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W3.6mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*3.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 3.6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W4.0mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*4.0mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 4.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W4.3mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*4.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 4.3mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W4.5mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*4.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 4.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W5.0mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W5.1mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*5.1mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 5.1mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W5.2mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*5.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 5.2mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W5.6mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*5.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 5.6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W6.4mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*6.4mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 6.4mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W6.6mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*6.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 6.6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W6.9mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*6.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 6.9mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W7.3mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*7.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 7.3mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W7.5mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*7.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 7.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W7.8mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*7.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 7.8mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W8.0mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*8.0mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 8.0mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W8.8mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*8.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 8.8mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W9.5mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*9.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 9.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L11.5mm_W9.8mm_P10.00mm_MKT
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*9.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 10.00mm  length 11.5mm width 9.8mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L13.0mm_W3.0mm_P10.00mm_FKS3_FKP3_MKS4
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=13*3mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 10.00mm  length 13mm width 3mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L13.0mm_W4.0mm_P10.00mm_FKS3_FKP3_MKS4
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=13*4mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 10.00mm  length 13mm width 4mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L13.0mm_W5.0mm_P10.00mm_FKS3_FKP3_MKS4
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=13*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 10.00mm  length 13mm width 5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L13.0mm_W6.0mm_P10.00mm_FKS3_FKP3_MKS4
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=13*6mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 10.00mm  length 13mm width 6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L13.0mm_W6.5mm_P7.50mm_P10.00mm
+C, Rect series, Radial, pin pitch=7.50mm 10.00mm, , length*width=13*6.5mm^2, Capacitor
+C Rect series Radial pin pitch 7.50mm 10.00mm  length 13mm width 6.5mm Capacitor
+0
+4
+2
+Capacitor_THT
+C_Rect_L13.0mm_W8.0mm_P10.00mm_FKS3_FKP3_MKS4
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=13*8mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 10.00mm  length 13mm width 8mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L13.5mm_W4.0mm_P10.00mm_FKS3_FKP3_MKS4
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=13.5*4mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 10.00mm  length 13.5mm width 4mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L13.5mm_W5.0mm_P10.00mm_FKS3_FKP3_MKS4
+C, Rect series, Radial, pin pitch=10.00mm, , length*width=13.5*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 10.00mm  length 13.5mm width 5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L16.5mm_W4.7mm_P15.00mm_MKT
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*4.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 15.00mm  length 16.5mm width 4.7mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L16.5mm_W4.9mm_P15.00mm_MKT
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*4.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 15.00mm  length 16.5mm width 4.9mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L16.5mm_W5.0mm_P15.00mm_MKT
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 15.00mm  length 16.5mm width 5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L16.5mm_W6.0mm_P15.00mm_MKT
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 15.00mm  length 16.5mm width 6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L16.5mm_W7.0mm_P15.00mm_MKT
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 15.00mm  length 16.5mm width 7mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L16.5mm_W7.3mm_P15.00mm_MKT
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*7.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 15.00mm  length 16.5mm width 7.3mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L16.5mm_W8.7mm_P15.00mm_MKT
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*8.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 15.00mm  length 16.5mm width 8.7mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L16.5mm_W8.9mm_P15.00mm_MKT
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*8.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 15.00mm  length 16.5mm width 8.9mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L16.5mm_W9.0mm_P15.00mm_MKT
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 15.00mm  length 16.5mm width 9mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L16.5mm_W9.2mm_P15.00mm_MKT
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*9.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 15.00mm  length 16.5mm width 9.2mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L16.5mm_W10.7mm_P15.00mm_MKT
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*10.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 15.00mm  length 16.5mm width 10.7mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L16.5mm_W10.9mm_P15.00mm_MKT
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*10.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 15.00mm  length 16.5mm width 10.9mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L16.5mm_W11.2mm_P15.00mm_MKT
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*11.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 15.00mm  length 16.5mm width 11.2mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L16.5mm_W11.8mm_P15.00mm_MKT
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*11.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 15.00mm  length 16.5mm width 11.8mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L16.5mm_W13.5mm_P15.00mm_MKT
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*13.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 15.00mm  length 16.5mm width 13.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L16.5mm_W13.7mm_P15.00mm_MKT
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*13.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 15.00mm  length 16.5mm width 13.7mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L16.5mm_W13.9mm_P15.00mm_MKT
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*13.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 15.00mm  length 16.5mm width 13.9mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L18.0mm_W5.0mm_P15.00mm_FKS3_FKP3
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf
+C Rect series Radial pin pitch 15.00mm  length 18mm width 5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L18.0mm_W6.0mm_P15.00mm_FKS3_FKP3
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*6mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf
+C Rect series Radial pin pitch 15.00mm  length 18mm width 6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L18.0mm_W7.0mm_P15.00mm_FKS3_FKP3
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*7mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf
+C Rect series Radial pin pitch 15.00mm  length 18mm width 7mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L18.0mm_W8.0mm_P15.00mm_FKS3_FKP3
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*8mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf
+C Rect series Radial pin pitch 15.00mm  length 18mm width 8mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L18.0mm_W9.0mm_P15.00mm_FKS3_FKP3
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*9mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf
+C Rect series Radial pin pitch 15.00mm  length 18mm width 9mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L18.0mm_W11.0mm_P15.00mm_FKS3_FKP3
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*11mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf
+C Rect series Radial pin pitch 15.00mm  length 18mm width 11mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L19.0mm_W5.0mm_P15.00mm_MKS4
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=19*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 15.00mm  length 19mm width 5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L19.0mm_W6.0mm_P15.00mm_MKS4
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=19*6mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 15.00mm  length 19mm width 6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L19.0mm_W7.0mm_P15.00mm_MKS4
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=19*7mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 15.00mm  length 19mm width 7mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L19.0mm_W8.0mm_P15.00mm_MKS4
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=19*8mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 15.00mm  length 19mm width 8mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L19.0mm_W9.0mm_P15.00mm_MKS4
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=19*9mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 15.00mm  length 19mm width 9mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L19.0mm_W11.0mm_P15.00mm_MKS4
+C, Rect series, Radial, pin pitch=15.00mm, , length*width=19*11mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 15.00mm  length 19mm width 11mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L24.0mm_W7.0mm_P22.50mm_MKT
+C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 22.50mm  length 24mm width 7mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L24.0mm_W8.3mm_P22.50mm_MKT
+C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*8.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 22.50mm  length 24mm width 8.3mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L24.0mm_W8.6mm_P22.50mm_MKT
+C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*8.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 22.50mm  length 24mm width 8.6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L24.0mm_W10.1mm_P22.50mm_MKT
+C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*10.1mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 22.50mm  length 24mm width 10.1mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L24.0mm_W10.3mm_P22.50mm_MKT
+C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*10.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 22.50mm  length 24mm width 10.3mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L24.0mm_W10.9mm_P22.50mm_MKT
+C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*10.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 22.50mm  length 24mm width 10.9mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L24.0mm_W12.2mm_P22.50mm_MKT
+C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*12.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 22.50mm  length 24mm width 12.2mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L24.0mm_W12.6mm_P22.50mm_MKT
+C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*12.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 22.50mm  length 24mm width 12.6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L24.0mm_W12.8mm_P22.50mm_MKT
+C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*12.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 22.50mm  length 24mm width 12.8mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L26.5mm_W5.0mm_P22.50mm_MKS4
+C, Rect series, Radial, pin pitch=22.50mm, , length*width=26.5*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 22.50mm  length 26.5mm width 5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L26.5mm_W6.0mm_P22.50mm_MKS4
+C, Rect series, Radial, pin pitch=22.50mm, , length*width=26.5*6mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 22.50mm  length 26.5mm width 6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L26.5mm_W7.0mm_P22.50mm_MKS4
+C, Rect series, Radial, pin pitch=22.50mm, , length*width=26.5*7mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 22.50mm  length 26.5mm width 7mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L26.5mm_W8.5mm_P22.50mm_MKS4
+C, Rect series, Radial, pin pitch=22.50mm, , length*width=26.5*8.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 22.50mm  length 26.5mm width 8.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L26.5mm_W10.5mm_P22.50mm_MKS4
+C, Rect series, Radial, pin pitch=22.50mm, , length*width=26.5*10.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 22.50mm  length 26.5mm width 10.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L26.5mm_W11.5mm_P22.50mm_MKS4
+C, Rect series, Radial, pin pitch=22.50mm, , length*width=26.5*11.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 22.50mm  length 26.5mm width 11.5mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L27.0mm_W9.0mm_P22.00mm
+C, Rect series, Radial, pin pitch=22.00mm, , length*width=27*9mm^2, Capacitor
+C Rect series Radial pin pitch 22.00mm  length 27mm width 9mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L27.0mm_W9.0mm_P23.00mm
+C, Rect series, Radial, pin pitch=23.00mm, , length*width=27*9mm^2, Capacitor
+C Rect series Radial pin pitch 23.00mm  length 27mm width 9mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L27.0mm_W11.0mm_P22.00mm
+C, Rect series, Radial, pin pitch=22.00mm, , length*width=27*11mm^2, Capacitor
+C Rect series Radial pin pitch 22.00mm  length 27mm width 11mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L28.0mm_W8.0mm_P22.50mm_MKS4
+C, Rect series, Radial, pin pitch=22.50mm, , length*width=28*8mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 22.50mm  length 28mm width 8mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L28.0mm_W10.0mm_P22.50mm_MKS4
+C, Rect series, Radial, pin pitch=22.50mm, , length*width=28*10mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 22.50mm  length 28mm width 10mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L28.0mm_W12.0mm_P22.50mm_MKS4
+C, Rect series, Radial, pin pitch=22.50mm, , length*width=28*12mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 22.50mm  length 28mm width 12mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L29.0mm_W7.6mm_P27.50mm_MKT
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*7.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 27.50mm  length 29mm width 7.6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L29.0mm_W7.8mm_P27.50mm_MKT
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*7.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 27.50mm  length 29mm width 7.8mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L29.0mm_W7.9mm_P27.50mm_MKT
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*7.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 27.50mm  length 29mm width 7.9mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L29.0mm_W9.1mm_P27.50mm_MKT
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*9.1mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 27.50mm  length 29mm width 9.1mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L29.0mm_W9.6mm_P27.50mm_MKT
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*9.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 27.50mm  length 29mm width 9.6mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L29.0mm_W11.0mm_P27.50mm_MKT
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*11mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 27.50mm  length 29mm width 11mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L29.0mm_W11.9mm_P27.50mm_MKT
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*11.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 27.50mm  length 29mm width 11.9mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L29.0mm_W12.2mm_P27.50mm_MKT
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*12.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 27.50mm  length 29mm width 12.2mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L29.0mm_W13.0mm_P27.50mm_MKT
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*13mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 27.50mm  length 29mm width 13mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L29.0mm_W13.8mm_P27.50mm_MKT
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*13.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 27.50mm  length 29mm width 13.8mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L29.0mm_W14.2mm_P27.50mm_MKT
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*14.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 27.50mm  length 29mm width 14.2mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L29.0mm_W16.0mm_P27.50mm_MKT
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*16mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
+C Rect series Radial pin pitch 27.50mm  length 29mm width 16mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L31.5mm_W9.0mm_P27.50mm_MKS4
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*9mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 27.50mm  length 31.5mm width 9mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L31.5mm_W11.0mm_P27.50mm_MKS4
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*11mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 27.50mm  length 31.5mm width 11mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L31.5mm_W13.0mm_P27.50mm_MKS4
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*13mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 27.50mm  length 31.5mm width 13mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L31.5mm_W15.0mm_P27.50mm_MKS4
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*15mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 27.50mm  length 31.5mm width 15mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L31.5mm_W17.0mm_P27.50mm_MKS4
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*17mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 27.50mm  length 31.5mm width 17mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L31.5mm_W20.0mm_P27.50mm_MKS4
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*20mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 27.50mm  length 31.5mm width 20mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L32.0mm_W15.0mm_P27.00mm
+C, Rect series, Radial, pin pitch=27.00mm, , length*width=32*15mm^2, Capacitor
+C Rect series Radial pin pitch 27.00mm  length 32mm width 15mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L33.0mm_W13.0mm_P27.50mm_MKS4
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=33*13mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 27.50mm  length 33mm width 13mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L33.0mm_W15.0mm_P27.50mm_MKS4
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=33*15mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 27.50mm  length 33mm width 15mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L33.0mm_W20.0mm_P27.50mm_MKS4
+C, Rect series, Radial, pin pitch=27.50mm, , length*width=33*20mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 27.50mm  length 33mm width 20mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L41.5mm_W9.0mm_P37.50mm_MKS4
+C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*9mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 37.50mm  length 41.5mm width 9mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L41.5mm_W11.0mm_P37.50mm_MKS4
+C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*11mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 37.50mm  length 41.5mm width 11mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L41.5mm_W13.0mm_P37.50mm_MKS4
+C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*13mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 37.50mm  length 41.5mm width 13mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L41.5mm_W15.0mm_P37.50mm_MKS4
+C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*15mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 37.50mm  length 41.5mm width 15mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L41.5mm_W17.0mm_P37.50mm_MKS4
+C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*17mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 37.50mm  length 41.5mm width 17mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L41.5mm_W19.0mm_P37.50mm_MKS4
+C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*19mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 37.50mm  length 41.5mm width 19mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L41.5mm_W20.0mm_P37.50mm_MKS4
+C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*20mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 37.50mm  length 41.5mm width 20mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L41.5mm_W24.0mm_P37.50mm_MKS4
+C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*24mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 37.50mm  length 41.5mm width 24mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L41.5mm_W31.0mm_P37.50mm_MKS4
+C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*31mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 37.50mm  length 41.5mm width 31mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L41.5mm_W35.0mm_P37.50mm_MKS4
+C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*35mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 37.50mm  length 41.5mm width 35mm Capacitor
+0
+2
+2
+Capacitor_THT
+C_Rect_L41.5mm_W40.0mm_P37.50mm_MKS4
+C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*40mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf
+C Rect series Radial pin pitch 37.50mm  length 41.5mm width 40mm Capacitor
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-1608-08_AVX-J
+Tantalum Capacitor SMD AVX-J (1608-08 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/48064/_t58_vmn_pt0471_1601.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-1608-08_AVX-J_Pad1.25x1.05mm_HandSolder
+Tantalum Capacitor SMD AVX-J (1608-08 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/48064/_t58_vmn_pt0471_1601.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-1608-10_AVX-L
+Tantalum Capacitor SMD AVX-L (1608-10 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/48064/_t58_vmn_pt0471_1601.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-1608-10_AVX-L_Pad1.25x1.05mm_HandSolder
+Tantalum Capacitor SMD AVX-L (1608-10 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/48064/_t58_vmn_pt0471_1601.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-2012-12_Kemet-R
+Tantalum Capacitor SMD Kemet-R (2012-12 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/40182/tmch.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-2012-12_Kemet-R_Pad1.30x1.05mm_HandSolder
+Tantalum Capacitor SMD Kemet-R (2012-12 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/40182/tmch.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-2012-15_AVX-P
+Tantalum Capacitor SMD AVX-P (2012-15 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/40182/tmch.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-2012-15_AVX-P_Pad1.30x1.05mm_HandSolder
+Tantalum Capacitor SMD AVX-P (2012-15 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/40182/tmch.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-3216-10_Kemet-I
+Tantalum Capacitor SMD Kemet-I (3216-10 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-3216-10_Kemet-I_Pad1.58x1.35mm_HandSolder
+Tantalum Capacitor SMD Kemet-I (3216-10 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-3216-12_Kemet-S
+Tantalum Capacitor SMD Kemet-S (3216-12 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-3216-12_Kemet-S_Pad1.58x1.35mm_HandSolder
+Tantalum Capacitor SMD Kemet-S (3216-12 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-3216-18_Kemet-A
+Tantalum Capacitor SMD Kemet-A (3216-18 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-3216-18_Kemet-A_Pad1.58x1.35mm_HandSolder
+Tantalum Capacitor SMD Kemet-A (3216-18 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-3528-12_Kemet-T
+Tantalum Capacitor SMD Kemet-T (3528-12 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-3528-12_Kemet-T_Pad1.50x2.35mm_HandSolder
+Tantalum Capacitor SMD Kemet-T (3528-12 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-3528-15_AVX-H
+Tantalum Capacitor SMD AVX-H (3528-15 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-3528-15_AVX-H_Pad1.50x2.35mm_HandSolder
+Tantalum Capacitor SMD AVX-H (3528-15 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-3528-21_Kemet-B
+Tantalum Capacitor SMD Kemet-B (3528-21 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-3528-21_Kemet-B_Pad1.50x2.35mm_HandSolder
+Tantalum Capacitor SMD Kemet-B (3528-21 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-6032-15_Kemet-U
+Tantalum Capacitor SMD Kemet-U (6032-15 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-6032-15_Kemet-U_Pad2.25x2.35mm_HandSolder
+Tantalum Capacitor SMD Kemet-U (6032-15 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-6032-20_AVX-F
+Tantalum Capacitor SMD AVX-F (6032-20 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-6032-20_AVX-F_Pad2.25x2.35mm_HandSolder
+Tantalum Capacitor SMD AVX-F (6032-20 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-6032-28_Kemet-C
+Tantalum Capacitor SMD Kemet-C (6032-28 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-6032-28_Kemet-C_Pad2.25x2.35mm_HandSolder
+Tantalum Capacitor SMD Kemet-C (6032-28 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7132-20_AVX-U
+Tantalum Capacitor SMD AVX-U (7132-20 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7132-20_AVX-U_Pad2.72x3.50mm_HandSolder
+Tantalum Capacitor SMD AVX-U (7132-20 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7132-28_AVX-C
+Tantalum Capacitor SMD AVX-C (7132-28 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7132-28_AVX-C_Pad2.72x3.50mm_HandSolder
+Tantalum Capacitor SMD AVX-C (7132-28 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7260-15_AVX-R
+Tantalum Capacitor SMD AVX-R (7260-15 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7260-15_AVX-R_Pad2.68x6.30mm_HandSolder
+Tantalum Capacitor SMD AVX-R (7260-15 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7260-20_AVX-M
+Tantalum Capacitor SMD AVX-M (7260-20 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7260-20_AVX-M_Pad2.68x6.30mm_HandSolder
+Tantalum Capacitor SMD AVX-M (7260-20 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7260-28_AVX-M
+Tantalum Capacitor SMD AVX-M (7260-28 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7260-28_AVX-M_Pad2.68x6.30mm_HandSolder
+Tantalum Capacitor SMD AVX-M (7260-28 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7260-38_AVX-R
+Tantalum Capacitor SMD AVX-R (7260-38 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7260-38_AVX-R_Pad2.68x6.30mm_HandSolder
+Tantalum Capacitor SMD AVX-R (7260-38 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7343-15_Kemet-W
+Tantalum Capacitor SMD Kemet-W (7343-15 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7343-15_Kemet-W_Pad2.25x2.55mm_HandSolder
+Tantalum Capacitor SMD Kemet-W (7343-15 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7343-20_Kemet-V
+Tantalum Capacitor SMD Kemet-V (7343-20 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7343-20_Kemet-V_Pad2.25x2.55mm_HandSolder
+Tantalum Capacitor SMD Kemet-V (7343-20 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7343-30_AVX-N
+Tantalum Capacitor SMD AVX-N (7343-30 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7343-30_AVX-N_Pad2.25x2.55mm_HandSolder
+Tantalum Capacitor SMD AVX-N (7343-30 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7343-31_Kemet-D
+Tantalum Capacitor SMD Kemet-D (7343-31 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7343-31_Kemet-D_Pad2.25x2.55mm_HandSolder
+Tantalum Capacitor SMD Kemet-D (7343-31 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7343-40_Kemet-Y
+Tantalum Capacitor SMD Kemet-Y (7343-40 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7343-40_Kemet-Y_Pad2.25x2.55mm_HandSolder
+Tantalum Capacitor SMD Kemet-Y (7343-40 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7343-43_Kemet-X
+Tantalum Capacitor SMD Kemet-X (7343-43 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7343-43_Kemet-X_Pad2.25x2.55mm_HandSolder
+Tantalum Capacitor SMD Kemet-X (7343-43 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7360-38_Kemet-E
+Tantalum Capacitor SMD Kemet-E (7360-38 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7360-38_Kemet-E_Pad2.25x4.25mm_HandSolder
+Tantalum Capacitor SMD Kemet-E (7360-38 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7361-38_AVX-V
+Tantalum Capacitor SMD AVX-V (7361-38 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/NOS.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7361-38_AVX-V_Pad2.18x3.30mm_HandSolder
+Tantalum Capacitor SMD AVX-V (7361-38 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/NOS.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7361-438_AVX-U
+Tantalum Capacitor SMD AVX-U (7361-438 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/NOS.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Capacitor_Tantalum_SMD
+CP_EIA-7361-438_AVX-U_Pad2.18x3.30mm_HandSolder
+Tantalum Capacitor SMD AVX-U (7361-438 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/NOS.pdf), generated with kicad-footprint-generator
+capacitor tantalum
+0
+2
+2
+Connector
+Banana_Jack_1Pin
+Single banana socket, footprint - 6mm drill
+banana socket
+0
+1
+1
+Connector
+Banana_Jack_2Pin
+Dual banana socket, footprint - 2 x 6mm drills
+banana socket
+0
+2
+2
+Connector
+Banana_Jack_3Pin
+Triple banana socket, footprint - 3 x 6mm drills
+banana socket
+0
+3
+3
+Connector
+CUI_PD-30
+3 pin connector, PD-30, http://www.cui.com/product/resource/pd-30.pdf
+connector 3-pin PD-30 power DIN
+0
+4
+4
+Connector
+CalTest_CT3151
+Right-angle standard banana jack, http://www.caltestelectronics.com/images/attachments/P315100rH_drawing.pdf
+banana jack horizontal
+0
+4
+1
+Connector
+Connector_SFP_and_Cage
+https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=2227302&DocType=Customer+Drawing&DocLang=English
+SFP+ SFP
+0
+40
+21
+Connector
+DTF13-12Px
+http://www.te.com/usa-en/product-DTF13-12PA-G003.html
+DEUTSCH DT header 12 pin 
+0
+12
+12
+Connector
+FanPinHeader_1x03_P2.54mm_Vertical
+3-pin CPU fan Through hole pin header, see http://www.formfactors.org/developer%5Cspecs%5Crev1_2_public.pdf
+pin header 3-pin CPU fan
+0
+3
+3
+Connector
+FanPinHeader_1x04_P2.54mm_Vertical
+4-pin CPU fan Through hole pin header, e.g. for Wieson part number 2366C888-007 Molex 47053-1000, Foxconn HF27040-M1, Tyco 1470947-1 or equivalent, see http://www.formfactors.org/developer%5Cspecs%5Crev1_2_public.pdf
+pin header 4-pin CPU fan
+0
+4
+4
+Connector
+GB042-34S-H10
+http://www.lsmtron.com/pdf/Connector&Antenna_catalog.PDF
+34pin SMD connector 
+0
+34
+34
+Connector
+IHI_B6A-PCB-45_Vertical
+https://lugsdirect.com/PDF_Webprint/B6A-PCB-45-XX(-X).pdf
+connector IHI B6A-PCB-45
+0
+49
+1
+Connector
+JWT_A3963_1x02_P3.96mm_Vertical
+JWT A3963, 3.96mm pitch Pin head connector (http://www.jwt.com.tw/pro_pdf/A3963.pdf)
+connector JWT A3963 pinhead
+0
+2
+2
+Connector
+NS-Tech_Grove_1x04_P2mm_Vertical
+https://statics3.seeedstudio.com/images/opl/datasheet/3470130P1.pdf
+Grove-1x04
+0
+4
+4
+Connector
+Tag-Connect_TC2030-IDC-FP_2x03_P1.27mm_Vertical
+Tag-Connect programming header; http://www.tag-connect.com/Materials/TC2030-IDC.pdf
+tag connect programming header pogo pins
+0
+6
+6
+Connector
+Tag-Connect_TC2030-IDC-NL_2x03_P1.27mm_Vertical
+Tag-Connect programming header; http://www.tag-connect.com/Materials/TC2030-IDC-NL.pdf
+tag connect programming header pogo pins
+0
+6
+6
+Connector
+Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical
+Tag-Connect programming header; http://www.tag-connect.com/Materials/TC2050-IDC-430%20Datasheet.pdf
+tag connect programming header pogo pins
+0
+10
+10
+Connector
+Tag-Connect_TC2050-IDC-NL_2x05_P1.27mm_Vertical
+Tag-Connect programming header; http://www.tag-connect.com/Materials/TC2050-IDC-NL%20Datasheet.pdf
+tag connect programming header pogo pins
+0
+10
+10
+Connector
+Tag-Connect_TC2070-IDC-FP_2x07_P1.27mm_Vertical
+Tag-Connect programming header; http://www.tag-connect.com/Materials/TC2070-IDC%20Datasheet.pdf
+tag connect programming header pogo pins
+0
+14
+14
+Connector_AMASS
+AMASS_MR30PW-FB_1x03_P3.50mm_Horizontal
+Connector XT30 Horizontal PCB Female, https://www.tme.eu/en/Document/5e47640ba39fa492dbd4c0f4c8ae7b93/MR30PW%20SPEC.pdf
+RC Connector XT30
+0
+5
+3
+Connector_AMASS
+AMASS_MR30PW-M_1x03_P3.50mm_Horizontal
+Connector XT30 Horizontal PCB Male, https://www.tme.eu/en/Document/5e47640ba39fa492dbd4c0f4c8ae7b93/MR30PW%20SPEC.pdf
+RC Connector XT30
+0
+5
+3
+Connector_AMASS
+AMASS_XT30PW-F_1x02_P2.50mm_Horizontal
+Connector XT30 Horizontal PCB Female, https://www.tme.eu/en/Document/ce4077e36b79046da520ca73227e15de/XT30PW%20SPEC.pdf
+RC Connector XT30
+0
+4
+2
+Connector_AMASS
+AMASS_XT30PW-M_1x02_P2.50mm_Horizontal
+Connector XT30 Horizontal PCB Male, https://www.tme.eu/en/Document/ce4077e36b79046da520ca73227e15de/XT30PW%20SPEC.pdf
+RC Connector XT30
+0
+4
+2
+Connector_AMASS
+AMASS_XT30U-F_1x02_P5.0mm_Vertical
+Connector XT30 Vertical Cable Female, https://www.tme.eu/en/Document/3cbfa5cfa544d79584972dd5234a409e/XT30U%20SPEC.pdf
+RC Connector XT30
+0
+2
+2
+Connector_AMASS
+AMASS_XT30U-M_1x02_P5.0mm_Vertical
+Connector XT30 Vertical Cable Male, https://www.tme.eu/en/Document/3cbfa5cfa544d79584972dd5234a409e/XT30U%20SPEC.pdf
+RC Connector XT30
+0
+2
+2
+Connector_AMASS
+AMASS_XT30UPB-F_1x02_P5.0mm_Vertical
+Connector XT30 Vertical PCB Female, https://www.tme.eu/en/Document/4acc913878197f8c2e30d4b8cdc47230/XT30UPB%20SPEC.pdf
+RC Connector XT30
+0
+2
+2
+Connector_AMASS
+AMASS_XT30UPB-M_1x02_P5.0mm_Vertical
+Connector XT30 Vertical PCB Male, https://www.tme.eu/en/Document/4acc913878197f8c2e30d4b8cdc47230/XT30UPB%20SPEC.pdf
+RC Connector XT30
+0
+2
+2
+Connector_AMASS
+AMASS_XT60-F_1x02_P7.20mm_Vertical
+AMASS female XT60, through hole, vertical, https://www.tme.eu/Document/2d152ced3b7a446066e6c419d84bb460/XT60%20SPEC.pdf
+XT60 female vertical
+0
+2
+2
+Connector_AMASS
+AMASS_XT60-M_1x02_P7.20mm_Vertical
+AMASS female XT60, through hole, vertical, https://www.tme.eu/Document/2d152ced3b7a446066e6c419d84bb460/XT60%20SPEC.pdf
+XT60 female vertical
+0
+2
+2
+Connector_Audio
+Jack_3.5mm_CUI_SJ-3523-SMT_Horizontal
+3.5 mm, Stereo, Right Angle, Surface Mount (SMT), Audio Jack Connector (https://www.cui.com/product/resource/sj-352x-smt-series.pdf)
+3.5mm audio cui horizontal jack stereo
+0
+3
+3
+Connector_Audio
+Jack_3.5mm_CUI_SJ-3524-SMT_Horizontal
+3.5 mm, Stereo, Right Angle, Surface Mount (SMT), Audio Jack Connector (https://www.cui.com/product/resource/sj-352x-smt-series.pdf)
+3.5mm audio cui horizontal jack stereo
+0
+4
+4
+Connector_Audio
+Jack_3.5mm_CUI_SJ1-3533NG_Horizontal
+TRS 3.5mm, horizontal, through-hole, https://www.cui.com/product/resource/sj1-353xng.pdf
+TRS audio jack stereo horizontal
+0
+3
+3
+Connector_Audio
+Jack_3.5mm_CUI_SJ1-3533NG_Horizontal_CircularHoles
+TRS 3.5mm, horizontal, through-hole, , circular holeshttps://www.cui.com/product/resource/sj1-353xng.pdf
+TRS audio jack stereo horizontal circular
+0
+3
+3
+Connector_Audio
+Jack_3.5mm_CUI_SJ1-3535NG_Horizontal
+TRS 3.5mm, horizontal, through-hole, with switch, https://www.cui.com/product/resource/sj1-353xng.pdf
+TRS audio jack stereo horizontal
+0
+5
+5
+Connector_Audio
+Jack_3.5mm_CUI_SJ1-3535NG_Horizontal_CircularHoles
+TRS 3.5mm, horizontal, through-hole, with switch, circular holes, https://www.cui.com/product/resource/sj1-353xng.pdf
+TRS audio jack stereo horizontal circular
+0
+5
+5
+Connector_Audio
+Jack_3.5mm_Ledino_KB3SPRS_Horizontal
+https://www.reichelt.de/index.html?ACTION=7&LA=3&OPEN=0&INDEX=0&FILENAME=C160%252FKB3SPRS.pdf
+jack stereo TRS
+0
+5
+5
+Connector_Audio
+Jack_3.5mm_Neutrik_NMJ6HCD2_Horizontal
+NMJ6HCD2, TRS 1/4in (http://www.neutrik.com/en/audio/plugs-and-jacks/m-series/nmj6hcd2)
+NMJ6HCD2 TRS stereo jack connector
+0
+6
+6
+Connector_Audio
+Jack_3.5mm_PJ311_Horizontal
+PJ311 6pin SMD 3.5mm stereo headphones jack.
+headphones jack plug stereo 3.5mm PJ311
+0
+6
+6
+Connector_Audio
+Jack_3.5mm_PJ320D_Horizontal
+Headphones with microphone connector, 3.5mm, 4 pins (http://www.qingpu-electronics.com/en/products/WQP-PJ320D-72.html)
+3.5mm jack mic microphone phones headphones 4pins audio plug
+0
+4
+4
+Connector_Audio
+Jack_3.5mm_PJ320E_Horizontal
+Headphones with microphone connector, 3.5mm, 4 pins (http://www.qingpu-electronics.com/en/products/WQP-PJ320E-177.html)
+3.5mm jack mic microphone phones headphones 4pins audio plug
+0
+5
+4
+Connector_Audio
+Jack_3.5mm_PJ31060-I_Horizontal
+PJ31060-I 6pin SMD 3.5mm headphones jack (http://www.china-bsun.com/Product48/1577.html)
+headphones jack plug stereo 3.5mm PJ31060-I PJ31060
+0
+6
+6
+Connector_Audio
+Jack_3.5mm_QingPu_WQP-PJ398SM_Vertical_CircularHoles
+TRS 3.5mm, vertical, Thonkiconn, PCB mount, (http://www.qingpu-electronics.com/en/products/WQP-PJ398SM-362.html)
+WQP-PJ398SM WQP-PJ301M-12 TRS 3.5mm mono vertical jack thonkiconn qingpu
+0
+3
+3
+Connector_Audio
+Jack_3.5mm_Switronic_ST-005-G_horizontal
+3.5mm horizontal headphones jack, http://akizukidenshi.com/download/ds/switronic/ST-005-G.pdf
+Connector Audio Switronic ST-005-G
+0
+4
+3
+Connector_Audio
+MiniXLR-5_Switchcraft_TRAPC_Horizontal
+http://www.switchcraft.com/ProductSummary.aspx?Parent=620 http://www.switchcraft.com/Drawings/TRAPC_X-TRASM_X_SERIES_CD.PDF
+THT Mini XLR 5Pin right angle
+0
+5
+5
+Connector_BarrelJack
+BarrelJack_CUI_PJ-036AH-SMT_Horizontal
+Surface-mount DC Barrel Jack, http://www.cui.com/product/resource/pj-036ah-smt.pdf
+Power Jack SMT
+0
+3
+3
+Connector_BarrelJack
+BarrelJack_CUI_PJ-063AH_Horizontal
+Barrel Jack, 2.0mm ID, 5.5mm OD, 24V, 8A, no switch, https://www.cui.com/product/resource/pj-063ah.pdf
+barrel jack cui dc power
+0
+4
+3
+Connector_BarrelJack
+BarrelJack_CUI_PJ-063AH_Horizontal_CircularHoles
+Barrel Jack, 2.0mm ID, 5.5mm OD, 24V, 8A, no switch, https://www.cui.com/product/resource/pj-063ah.pdf
+barrel jack cui dc power
+0
+4
+3
+Connector_BarrelJack
+BarrelJack_CUI_PJ-102AH_Horizontal
+Thin-pin DC Barrel Jack, https://cdn-shop.adafruit.com/datasheets/21mmdcjackDatasheet.pdf
+Power Jack
+0
+3
+3
+Connector_BarrelJack
+BarrelJack_Horizontal
+DC Barrel Jack
+Power Jack
+0
+3
+3
+Connector_BarrelJack
+BarrelJack_Wuerth_6941xx301002
+Wuerth electronics barrel jack connector (5.5mm outher diameter, inner diameter 2.05mm or 2.55mm depending on exact order number), See: http://katalog.we-online.de/em/datasheet/6941xx301002.pdf
+connector barrel jack
+0
+3
+3
+Connector_Card
+CF-Card_3M_N7E50-7516PK-20-WF
+Compact Flash Card connector (https://multimedia.3m.com/mws/media/22365O/3mtm-cf-card-header-compactflashtm-type-i-sm-ts0662.pdf)
+connector cf
+0
+54
+50
+Connector_Card
+SD_Kyocera_145638009211859+
+SD Card Connector, Normal Type, Outer Tail, Without Ejector (https://global.kyocera.com/prdct/electro/product/pdf/5638.pdf)
+sd card smt
+0
+13
+12
+Connector_Card
+SD_Kyocera_145638009511859+
+SD Card Connector, Normal Type, Outer Tail, Spring Eject Type (https://global.kyocera.com/prdct/electro/product/pdf/5638.pdf)
+sd card smt
+0
+13
+12
+Connector_Card
+SD_Kyocera_145638109211859+
+SD Card Connector, Reverse Type, Outer Tail, Without Ejector (https://global.kyocera.com/prdct/electro/product/pdf/5638.pdf)
+sd card smt
+0
+13
+12
+Connector_Card
+SD_Kyocera_145638109511859+
+SD Card Connector, Reverse Type, Outer Tail, Spring Eject Type (https://global.kyocera.com/prdct/electro/product/pdf/5638.pdf)
+sd card smt
+0
+13
+12
+Connector_Card
+SD_TE_2041021
+SD card connector, top mount, SMT (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F2041021%7FB%7Fpdf%7FEnglish%7FENG_CD_2041021_B_C_2041021_B.pdf%7F2041021-4)
+sd card
+0
+15
+12
+Connector_Card
+microSD_HC_Hirose_DM3AT-SF-PEJM5
+Micro SD, SMD, right-angle, push-pull (https://www.hirose.com/product/en/download_file/key_name/DM3AT-SF-PEJM5/category/Drawing%20(2D)/doc_file_id/44099/?file_category_id=6&item_id=06090031000&is_series=)
+Micro SD
+0
+14
+11
+Connector_Card
+microSD_HC_Hirose_DM3BT-DSF-PEJS
+Micro SD, SMD, reverse on-board, right-angle, push-pull (https://www.hirose.com/product/en/download_file/key_name/DM3BT-DSF-PEJS/category/Drawing%20(2D)/doc_file_id/44097/?file_category_id=6&item_id=06090029900&is_series=)
+Micro SD
+0
+16
+11
+Connector_Card
+microSD_HC_Hirose_DM3D-SF
+Micro SD, SMD, right-angle, push-pull (https://media.digikey.com/PDF/Data%20Sheets/Hirose%20PDFs/DM3D-SF.pdf)
+Micro SD
+0
+14
+11
+Connector_Card
+microSD_HC_Molex_104031-0811
+1.10mm Pitch microSD Memory Card Connector, Surface Mount, Push-Pull Type, 1.42mm Height, with Detect Switch (https://www.molex.com/pdm_docs/sd/1040310811_sd.pdf)
+microSD SD molex
+0
+14
+11
+Connector_Card
+microSD_HC_Wuerth_693072010801
+http://katalog.we-online.de/em/datasheet/693072010801.pdf
+Micro SD Wuerth Wurth Würth
+0
+12
+9
+Connector_Card
+microSIM_JAE_SF53S006VCBR2000
+https://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ115712.pdf
+microSIM GSM Card
+0
+14
+7
+Connector_Coaxial
+BNC_Amphenol_031-6575_Horizontal
+dual independently isolated BNC plug (https://www.amphenolrf.com/downloads/dl/file/id/2980/product/644/031_6575_customer_drawing.pdf)
+Dual BNC Amphenol Horizontal
+0
+6
+4
+Connector_Coaxial
+BNC_Amphenol_B6252HB-NPP3G-50_Horizontal
+http://www.farnell.com/datasheets/612848.pdf
+BNC Amphenol Horizontal
+0
+4
+2
+Connector_Coaxial
+BNC_PanelMountable_Vertical
+Panel-mountable BNC connector mounted through PCB, vertical
+BNC connector
+0
+2
+2
+Connector_Coaxial
+BNC_TEConnectivity_1478204_Vertical
+BNC female PCB mount 4 pin straight chassis connector http://www.te.com/usa-en/product-1-1478204-0.html
+BNC female PCB mount 4 pin straight chassis connector 
+0
+5
+2
+Connector_Coaxial
+BNC_Win_364A2x95_Horizontal
+Dual front isolated BNC plug (https://www.winconn.com/wp-content/uploads/364A2595.pdf)
+Dual BNC Horizontal Isolated
+0
+6
+3
+Connector_Coaxial
+MMCX_Molex_73415-0961_Horizontal_0.8mm-PCB
+Molex MMCX Horizontal Coaxial https://www.molex.com/pdm_docs/sd/734150961_sd.pdf
+Molex MMCX Horizontal Coaxial
+0
+3
+2
+Connector_Coaxial
+MMCX_Molex_73415-0961_Horizontal_1.0mm-PCB
+Molex MMCX Horizontal Coaxial https://www.molex.com/pdm_docs/sd/734150961_sd.pdf
+Molex MMCX Horizontal Coaxial
+0
+3
+2
+Connector_Coaxial
+MMCX_Molex_73415-0961_Horizontal_1.6mm-PCB
+Molex MMCX Horizontal Coaxial https://www.molex.com/pdm_docs/sd/734150961_sd.pdf
+Molex MMCX Horizontal Coaxial
+0
+3
+2
+Connector_Coaxial
+MMCX_Molex_73415-1471_Vertical
+http://www.molex.com/pdm_docs/sd/734151471_sd.pdf
+Molex MMCX Coaxial Connector 50 ohms Female Jack Vertical THT
+0
+5
+2
+Connector_Coaxial
+SMA_Amphenol_901-144_Vertical
+https://www.amphenolrf.com/downloads/dl/file/id/7023/product/3103/901_144_customer_drawing.pdf
+SMA THT Female Jack Vertical
+0
+5
+2
+Connector_Coaxial
+SMA_Amphenol_132134-10_Vertical
+https://www.amphenolrf.com/downloads/dl/file/id/4007/product/2974/132134_10_customer_drawing.pdf
+SMA SMD Female Jack Vertical
+0
+3
+2
+Connector_Coaxial
+SMA_Amphenol_132134-11_Vertical
+https://www.amphenolrf.com/downloads/dl/file/id/3406/product/2975/132134_11_customer_drawing.pdf
+SMA THT Female Jack Vertical ExtendedLegs
+0
+5
+2
+Connector_Coaxial
+SMA_Amphenol_132134-14_Vertical
+https://www.amphenolrf.com/downloads/dl/file/id/1793/product/2976/132134_14_customer_drawing.pdf
+SMA THT Female Jack Vertical ExtendedLegs
+0
+5
+2
+Connector_Coaxial
+SMA_Amphenol_132134-16_Vertical
+https://www.amphenolrf.com/downloads/dl/file/id/1141/product/2978/132134_16_customer_drawing.pdf
+SMA THT Female Jack Vertical ExtendedLegs
+0
+5
+2
+Connector_Coaxial
+SMA_Amphenol_132134_Vertical
+https://www.amphenolrf.com/downloads/dl/file/id/2187/product/2843/132134_customer_drawing.pdf
+SMA THT Female Jack Vertical ExtendedLegs
+0
+5
+2
+Connector_Coaxial
+SMA_Amphenol_132203-12_Horizontal
+https://www.amphenolrf.com/media/downloads/1769/132203-12.pdf
+SMA THT Female Jack Horizontal
+0
+5
+2
+Connector_Coaxial
+SMA_Amphenol_132289_EdgeMount
+http://www.amphenolrf.com/132289.html
+SMA
+0
+5
+2
+Connector_Coaxial
+SMA_Amphenol_132291-12_Vertical
+https://www.amphenolrf.com/downloads/dl/file/id/1688/product/3020/132291_12_customer_drawing.pdf
+SMA THT Female Jack Vertical Bulkhead
+0
+5
+2
+Connector_Coaxial
+SMA_Amphenol_132291_Vertical
+https://www.amphenolrf.com/downloads/dl/file/id/3222/product/2918/132291_customer_drawing.pdf
+SMA THT Female Jack Vertical Bulkhead
+0
+5
+2
+Connector_Coaxial
+SMA_Molex_73251-1153_EdgeMount_Horizontal
+Molex SMA RF Connectors, Edge Mount, (http://www.molex.com/pdm_docs/sd/732511150_sd.pdf)
+sma edge
+0
+11
+2
+Connector_Coaxial
+SMA_Molex_73251-2200_Horizontal
+https://www.molex.com/webdocs/datasheets/pdf/en-us/0732512200_RF_COAX_CONNECTORS.pdf
+SMA THT Female Jack Horizontal
+0
+5
+2
+Connector_Coaxial
+SMA_Samtec_SMA-J-P-X-ST-EM1_EdgeMount
+Connector SMA, 0Hz to 20GHz, 50Ohm, Edge Mount (http://suddendocs.samtec.com/prints/sma-j-p-x-st-em1-mkt.pdf)
+SMA Straight Samtec Edge Mount
+0
+5
+2
+Connector_Coaxial
+SMB_Jack_Vertical
+SMB pcb mounting jack
+SMB Jack  Striaght
+0
+5
+2
+Connector_Coaxial
+U.FL_Hirose_U.FL-R-SMT-1_Vertical
+Hirose U.FL Coaxial https://www.hirose.com/product/en/products/U.FL/U.FL-R-SMT-1%2810%29/
+Hirose U.FL Coaxial
+0
+3
+2
+Connector_Coaxial
+U.FL_Molex_MCRF_73412-0110_Vertical
+Molex Microcoaxial RF Connectors (MCRF), mates Hirose U.FL, (http://www.molex.com/pdm_docs/sd/734120110_sd.pdf)
+mcrf hirose ufl u.fl microcoaxial
+0
+4
+2
+Connector_DIN
+DIN41612_B2_2x8_Horizontal
+DIN 41612 connector, type B/2, horizontal, 16 pins wide, 2 rows, even columns
+DIN 41512 IEC 60603 B/2
+0
+16
+16
+Connector_DIN
+DIN41612_B2_2x8_Vertical
+DIN 41612 connector, type B/2, vertical, 16 pins wide, 2 rows, even columns
+DIN 41512 IEC 60603 B/2
+0
+16
+16
+Connector_DIN
+DIN41612_B2_2x16_Horizontal
+DIN 41612 connector, type B/2, horizontal, 16 pins wide, 2 rows, full configuration
+DIN 41512 IEC 60603 B/2
+0
+32
+32
+Connector_DIN
+DIN41612_B2_2x16_Vertical
+DIN 41612 connector, type B/2, vertical, 16 pins wide, 2 rows, full configuration
+DIN 41512 IEC 60603 B/2
+0
+32
+32
+Connector_DIN
+DIN41612_B3_2x5_Horizontal
+DIN 41612 connector, type B/3, horizontal, 10 pins wide, 2 rows, even columns
+DIN 41512 IEC 60603 B/3
+0
+10
+10
+Connector_DIN
+DIN41612_B3_2x5_Vertical
+DIN 41612 connector, type B/3, vertical, 10 pins wide, 2 rows, even columns
+DIN 41512 IEC 60603 B/3
+0
+10
+10
+Connector_DIN
+DIN41612_B3_2x10_Horizontal
+DIN 41612 connector, type B/3, horizontal, 10 pins wide, 2 rows, full configuration
+DIN 41512 IEC 60603 B/3
+0
+20
+20
+Connector_DIN
+DIN41612_B3_2x10_Vertical
+DIN 41612 connector, type B/3, vertical, 10 pins wide, 2 rows, full configuration
+DIN 41512 IEC 60603 B/3
+0
+20
+20
+Connector_DIN
+DIN41612_B_2x16_Horizontal
+DIN 41612 connector, type B, horizontal, 32 pins wide, 2 rows, even columns
+DIN 41512 IEC 60603 B
+0
+32
+32
+Connector_DIN
+DIN41612_B_2x16_Vertical
+DIN 41612 connector, type B, vertical, 32 pins wide, 2 rows, even columns
+DIN 41512 IEC 60603 B
+0
+32
+32
+Connector_DIN
+DIN41612_B_2x32_Horizontal
+DIN 41612 connector, type B, horizontal, 32 pins wide, 2 rows, full configuration
+DIN 41512 IEC 60603 B
+0
+64
+64
+Connector_DIN
+DIN41612_B_2x32_Vertical
+DIN 41612 connector, type B, vertical, 32 pins wide, 2 rows, full configuration
+DIN 41512 IEC 60603 B
+0
+64
+64
+Connector_Dsub
+DSUB-9_Female_EdgeMount_P2.77mm
+9-pin D-Sub connector, solder-cups edge-mounted, female, x-pin-pitch 2.77mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+9-pin D-Sub connector edge mount solder cup female x-pin-pitch 2.77mm mounting holes distance 25mm
+0
+9
+9
+Connector_Dsub
+DSUB-9_Female_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm
+9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.54mm pin-PCB-offset 9.4mm
+0
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+Connector_Dsub
+DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm
+9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 25mm mounting-hole-offset 25mm
+0
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+DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm
+9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 25mm mounting-hole-offset 25mm
+0
+11
+10
+Connector_Dsub
+DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm
+9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.4mm
+0
+9
+9
+Connector_Dsub
+DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm
+9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 25mm mounting-hole-offset 25mm
+0
+11
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+Connector_Dsub
+DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm
+9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 25mm mounting-hole-offset 25mm
+0
+11
+10
+Connector_Dsub
+DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm
+9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 25mm mounting-hole-offset 25mm
+0
+11
+10
+Connector_Dsub
+DSUB-9_Female_Vertical_P2.77x2.84mm
+9-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+9-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 25mm
+0
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+9
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+DSUB-9_Female_Vertical_P2.77x2.84mm_MountingHoles
+9-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+9-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 25mm
+0
+11
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+Connector_Dsub
+DSUB-9_Male_EdgeMount_P2.77mm
+9-pin D-Sub connector, solder-cups edge-mounted, male, x-pin-pitch 2.77mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+9-pin D-Sub connector edge mount solder cup male x-pin-pitch 2.77mm mounting holes distance 25mm
+0
+9
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+Connector_Dsub
+DSUB-9_Male_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm
+9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.54mm pin-PCB-offset 9.4mm
+0
+9
+9
+Connector_Dsub
+DSUB-9_Male_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm
+9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 25mm mounting-hole-offset 25mm
+0
+11
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+9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 25mm mounting-hole-offset 25mm
+0
+11
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+Connector_Dsub
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+9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.4mm
+0
+9
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+9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 25mm mounting-hole-offset 25mm
+0
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+9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 25mm mounting-hole-offset 25mm
+0
+11
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+9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 25mm mounting-hole-offset 25mm
+0
+11
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+DSUB-9_Male_Vertical_P2.77x2.84mm
+9-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+9-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 25mm
+0
+9
+9
+Connector_Dsub
+DSUB-9_Male_Vertical_P2.77x2.84mm_MountingHoles
+9-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+9-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 25mm
+0
+11
+10
+Connector_Dsub
+DSUB-15-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm
+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 25mm mounting-hole-offset 25mm
+0
+17
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+Connector_Dsub
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+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 25mm mounting-hole-offset 25mm
+0
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+Connector_Dsub
+DSUB-15-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset9.40mm
+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 9.4mm
+0
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+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x2.54mm pin-PCB-offset 9.4mm
+0
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+Connector_Dsub
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+15-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.29x1.98mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector straight vertical THT female pitch 2.29x1.98mm mounting holes distance 25mm
+0
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+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 25mm mounting-hole-offset 25mm
+0
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+Connector_Dsub
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+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 25mm mounting-hole-offset 25mm
+0
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+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 9.4mm
+0
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+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x2.54mm pin-PCB-offset 9.4mm
+0
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+15-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.29x1.98mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector straight vertical THT male pitch 2.29x1.98mm mounting holes distance 25mm
+0
+17
+16
+Connector_Dsub
+DSUB-15_Female_EdgeMount_P2.77mm
+15-pin D-Sub connector, solder-cups edge-mounted, female, x-pin-pitch 2.77mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector edge mount solder cup female x-pin-pitch 2.77mm mounting holes distance 33.3mm
+0
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+15
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+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.54mm pin-PCB-offset 9.4mm
+0
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+Connector_Dsub
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+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm
+0
+17
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+Connector_Dsub
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+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm
+0
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+16
+Connector_Dsub
+DSUB-15_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm
+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.4mm
+0
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+Connector_Dsub
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+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm
+0
+17
+16
+Connector_Dsub
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+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm
+0
+17
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+Connector_Dsub
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+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm
+0
+17
+16
+Connector_Dsub
+DSUB-15_Female_Vertical_P2.77x2.84mm
+15-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 33.3mm
+0
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+Connector_Dsub
+DSUB-15_Female_Vertical_P2.77x2.84mm_MountingHoles
+15-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 33.3mm
+0
+17
+16
+Connector_Dsub
+DSUB-15_Male_EdgeMount_P2.77mm
+15-pin D-Sub connector, solder-cups edge-mounted, male, x-pin-pitch 2.77mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector edge mount solder cup male x-pin-pitch 2.77mm mounting holes distance 33.3mm
+0
+15
+15
+Connector_Dsub
+DSUB-15_Male_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm
+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.54mm pin-PCB-offset 9.4mm
+0
+15
+15
+Connector_Dsub
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+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm
+0
+17
+16
+Connector_Dsub
+DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm
+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm
+0
+17
+16
+Connector_Dsub
+DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm
+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.4mm
+0
+15
+15
+Connector_Dsub
+DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm
+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm
+0
+17
+16
+Connector_Dsub
+DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm
+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm
+0
+17
+16
+Connector_Dsub
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+15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm
+0
+17
+16
+Connector_Dsub
+DSUB-15_Male_Vertical_P2.77x2.84mm
+15-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 33.3mm
+0
+15
+15
+Connector_Dsub
+DSUB-15_Male_Vertical_P2.77x2.84mm_MountingHoles
+15-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+15-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 33.3mm
+0
+17
+16
+Connector_Dsub
+DSUB-25_Female_EdgeMount_P2.77mm
+25-pin D-Sub connector, solder-cups edge-mounted, female, x-pin-pitch 2.77mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+25-pin D-Sub connector edge mount solder cup female x-pin-pitch 2.77mm mounting holes distance 47.1mm
+0
+25
+25
+Connector_Dsub
+DSUB-25_Female_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm
+25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.54mm pin-PCB-offset 9.4mm
+0
+25
+25
+Connector_Dsub
+DSUB-25_Female_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm
+25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm
+0
+27
+26
+Connector_Dsub
+DSUB-25_Female_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm
+25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm
+0
+27
+26
+Connector_Dsub
+DSUB-25_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm
+25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.4mm
+0
+25
+25
+Connector_Dsub
+DSUB-25_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm
+25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm
+0
+27
+26
+Connector_Dsub
+DSUB-25_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm
+25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm
+0
+27
+26
+Connector_Dsub
+DSUB-25_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm
+25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm
+0
+27
+26
+Connector_Dsub
+DSUB-25_Female_Vertical_P2.77x2.84mm
+25-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+25-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 47.1mm
+0
+25
+25
+Connector_Dsub
+DSUB-25_Female_Vertical_P2.77x2.84mm_MountingHoles
+25-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+25-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 47.1mm
+0
+27
+26
+Connector_Dsub
+DSUB-25_Male_EdgeMount_P2.77mm
+25-pin D-Sub connector, solder-cups edge-mounted, male, x-pin-pitch 2.77mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+25-pin D-Sub connector edge mount solder cup male x-pin-pitch 2.77mm mounting holes distance 47.1mm
+0
+25
+25
+Connector_Dsub
+DSUB-25_Male_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm
+25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.54mm pin-PCB-offset 9.4mm
+0
+25
+25
+Connector_Dsub
+DSUB-25_Male_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm
+25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm
+0
+27
+26
+Connector_Dsub
+DSUB-25_Male_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm
+25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm
+0
+27
+26
+Connector_Dsub
+DSUB-25_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm
+25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.4mm
+0
+25
+25
+Connector_Dsub
+DSUB-25_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm
+25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm
+0
+27
+26
+Connector_Dsub
+DSUB-25_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm
+25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm
+0
+27
+26
+Connector_Dsub
+DSUB-25_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm
+25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm
+0
+27
+26
+Connector_Dsub
+DSUB-25_Male_Vertical_P2.77x2.84mm
+25-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+25-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 47.1mm
+0
+25
+25
+Connector_Dsub
+DSUB-25_Male_Vertical_P2.77x2.84mm_MountingHoles
+25-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+25-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 47.1mm
+0
+27
+26
+Connector_Dsub
+DSUB-26-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm
+26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+26-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm
+0
+28
+27
+Connector_Dsub
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+26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+26-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm
+0
+28
+27
+Connector_Dsub
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+26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+26-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 9.4mm
+0
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+26
+Connector_Dsub
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+26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+26-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x2.54mm pin-PCB-offset 9.4mm
+0
+26
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+Connector_Dsub
+DSUB-26-HD_Female_Vertical_P2.29x1.98mm_MountingHoles
+26-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.29x1.98mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+26-pin D-Sub connector straight vertical THT female pitch 2.29x1.98mm mounting holes distance 33.3mm
+0
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+27
+Connector_Dsub
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+26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+26-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm
+0
+28
+27
+Connector_Dsub
+DSUB-26-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm
+26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+26-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm
+0
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+27
+Connector_Dsub
+DSUB-26-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset9.40mm
+26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+26-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 9.4mm
+0
+26
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+Connector_Dsub
+DSUB-26-HD_Male_Horizontal_P2.29x2.54mm_EdgePinOffset9.40mm
+26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+26-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x2.54mm pin-PCB-offset 9.4mm
+0
+26
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+Connector_Dsub
+DSUB-26-HD_Male_Vertical_P2.29x1.98mm_MountingHoles
+26-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.29x1.98mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+26-pin D-Sub connector straight vertical THT male pitch 2.29x1.98mm mounting holes distance 33.3mm
+0
+28
+27
+Connector_Dsub
+DSUB-37_Female_EdgeMount_P2.77mm
+37-pin D-Sub connector, solder-cups edge-mounted, female, x-pin-pitch 2.77mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+37-pin D-Sub connector edge mount solder cup female x-pin-pitch 2.77mm mounting holes distance 63.5mm
+0
+37
+37
+Connector_Dsub
+DSUB-37_Female_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm
+37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.54mm pin-PCB-offset 9.4mm
+0
+37
+37
+Connector_Dsub
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+37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm
+0
+39
+38
+Connector_Dsub
+DSUB-37_Female_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm
+37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm
+0
+39
+38
+Connector_Dsub
+DSUB-37_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm
+37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.4mm
+0
+37
+37
+Connector_Dsub
+DSUB-37_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm
+37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm
+0
+39
+38
+Connector_Dsub
+DSUB-37_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm
+37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm
+0
+39
+38
+Connector_Dsub
+DSUB-37_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm
+37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm
+0
+39
+38
+Connector_Dsub
+DSUB-37_Female_Vertical_P2.77x2.84mm
+37-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+37-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 63.5mm
+0
+37
+37
+Connector_Dsub
+DSUB-37_Female_Vertical_P2.77x2.84mm_MountingHoles
+37-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+37-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 63.5mm
+0
+39
+38
+Connector_Dsub
+DSUB-37_Male_EdgeMount_P2.77mm
+37-pin D-Sub connector, solder-cups edge-mounted, male, x-pin-pitch 2.77mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+37-pin D-Sub connector edge mount solder cup male x-pin-pitch 2.77mm mounting holes distance 63.5mm
+0
+37
+37
+Connector_Dsub
+DSUB-37_Male_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm
+37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.54mm pin-PCB-offset 9.4mm
+0
+37
+37
+Connector_Dsub
+DSUB-37_Male_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm
+37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm
+0
+39
+38
+Connector_Dsub
+DSUB-37_Male_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm
+37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm
+0
+39
+38
+Connector_Dsub
+DSUB-37_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm
+37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.4mm
+0
+37
+37
+Connector_Dsub
+DSUB-37_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm
+37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm
+0
+39
+38
+Connector_Dsub
+DSUB-37_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm
+37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm
+0
+39
+38
+Connector_Dsub
+DSUB-37_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm
+37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm
+0
+39
+38
+Connector_Dsub
+DSUB-37_Male_Vertical_P2.77x2.84mm
+37-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+37-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 63.5mm
+0
+37
+37
+Connector_Dsub
+DSUB-37_Male_Vertical_P2.77x2.84mm_MountingHoles
+37-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+37-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 63.5mm
+0
+39
+38
+Connector_Dsub
+DSUB-44-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm
+44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+44-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm
+0
+46
+45
+Connector_Dsub
+DSUB-44-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm
+44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+44-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm
+0
+46
+45
+Connector_Dsub
+DSUB-44-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset9.40mm
+44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+44-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 9.4mm
+0
+44
+44
+Connector_Dsub
+DSUB-44-HD_Female_Horizontal_P2.29x2.54mm_EdgePinOffset9.40mm
+44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+44-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x2.54mm pin-PCB-offset 9.4mm
+0
+44
+44
+Connector_Dsub
+DSUB-44-HD_Female_Vertical_P2.29x1.98mm_MountingHoles
+44-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.29x1.98mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+44-pin D-Sub connector straight vertical THT female pitch 2.29x1.98mm mounting holes distance 47.1mm
+0
+46
+45
+Connector_Dsub
+DSUB-44-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm
+44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+44-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm
+0
+46
+45
+Connector_Dsub
+DSUB-44-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm
+44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+44-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm
+0
+46
+45
+Connector_Dsub
+DSUB-44-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset9.40mm
+44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+44-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 9.4mm
+0
+44
+44
+Connector_Dsub
+DSUB-44-HD_Male_Horizontal_P2.29x2.54mm_EdgePinOffset9.40mm
+44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+44-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x2.54mm pin-PCB-offset 9.4mm
+0
+44
+44
+Connector_Dsub
+DSUB-44-HD_Male_Vertical_P2.29x1.98mm_MountingHoles
+44-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.29x1.98mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+44-pin D-Sub connector straight vertical THT male pitch 2.29x1.98mm mounting holes distance 47.1mm
+0
+46
+45
+Connector_Dsub
+DSUB-62-HD_Female_Horizontal_P2.41x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm
+62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.41x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+62-pin D-Sub connector horizontal angled 90deg THT female pitch 2.41x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm
+0
+64
+63
+Connector_Dsub
+DSUB-62-HD_Female_Horizontal_P2.41x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm
+62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.41x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+62-pin D-Sub connector horizontal angled 90deg THT female pitch 2.41x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm
+0
+64
+63
+Connector_Dsub
+DSUB-62-HD_Female_Horizontal_P2.41x1.98mm_EdgePinOffset9.40mm
+62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.41x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+62-pin D-Sub connector horizontal angled 90deg THT female pitch 2.41x1.98mm pin-PCB-offset 9.4mm
+0
+62
+62
+Connector_Dsub
+DSUB-62-HD_Female_Horizontal_P2.41x2.54mm_EdgePinOffset9.40mm
+62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.41x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+62-pin D-Sub connector horizontal angled 90deg THT female pitch 2.41x2.54mm pin-PCB-offset 9.4mm
+0
+62
+62
+Connector_Dsub
+DSUB-62-HD_Female_Vertical_P2.41x1.98mm_MountingHoles
+62-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.41x1.98mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+62-pin D-Sub connector straight vertical THT female pitch 2.41x1.98mm mounting holes distance 63.5mm
+0
+64
+63
+Connector_Dsub
+DSUB-62-HD_Male_Horizontal_P2.41x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm
+62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.41x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+62-pin D-Sub connector horizontal angled 90deg THT male pitch 2.41x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm
+0
+64
+63
+Connector_Dsub
+DSUB-62-HD_Male_Horizontal_P2.41x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm
+62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.41x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+62-pin D-Sub connector horizontal angled 90deg THT male pitch 2.41x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm
+0
+64
+63
+Connector_Dsub
+DSUB-62-HD_Male_Horizontal_P2.41x1.98mm_EdgePinOffset9.40mm
+62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.41x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+62-pin D-Sub connector horizontal angled 90deg THT male pitch 2.41x1.98mm pin-PCB-offset 9.4mm
+0
+62
+62
+Connector_Dsub
+DSUB-62-HD_Male_Horizontal_P2.41x2.54mm_EdgePinOffset9.40mm
+62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.41x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf
+62-pin D-Sub connector horizontal angled 90deg THT male pitch 2.41x2.54mm pin-PCB-offset 9.4mm
+0
+62
+62
+Connector_Dsub
+DSUB-62-HD_Male_Vertical_P2.41x1.98mm_MountingHoles
+62-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.41x1.98mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf
+62-pin D-Sub connector straight vertical THT male pitch 2.41x1.98mm mounting holes distance 63.5mm
+0
+64
+63
+Connector_FFC-FPC
+Hirose_FH12-6S-0.5SH_1x06-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-6S-0.5SH, 6 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+8
+7
+Connector_FFC-FPC
+Hirose_FH12-8S-0.5SH_1x08-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-8S-0.5SH, 8 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+10
+9
+Connector_FFC-FPC
+Hirose_FH12-10S-0.5SH_1x10-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-10S-0.5SH, 10 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+12
+11
+Connector_FFC-FPC
+Hirose_FH12-11S-0.5SH_1x11-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-11S-0.5SH, 11 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+13
+12
+Connector_FFC-FPC
+Hirose_FH12-12S-0.5SH_1x12-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-12S-0.5SH, 12 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+14
+13
+Connector_FFC-FPC
+Hirose_FH12-13S-0.5SH_1x13-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-13S-0.5SH, 13 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+15
+14
+Connector_FFC-FPC
+Hirose_FH12-14S-0.5SH_1x14-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-14S-0.5SH, 14 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+16
+15
+Connector_FFC-FPC
+Hirose_FH12-15S-0.5SH_1x15-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-15S-0.5SH, 15 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+17
+16
+Connector_FFC-FPC
+Hirose_FH12-16S-0.5SH_1x16-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-16S-0.5SH, 16 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+18
+17
+Connector_FFC-FPC
+Hirose_FH12-17S-0.5SH_1x17-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-17S-0.5SH, 17 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+19
+18
+Connector_FFC-FPC
+Hirose_FH12-18S-0.5SH_1x18-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-18S-0.5SH, 18 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+20
+19
+Connector_FFC-FPC
+Hirose_FH12-19S-0.5SH_1x19-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-19S-0.5SH, 19 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+21
+20
+Connector_FFC-FPC
+Hirose_FH12-20S-0.5SH_1x20-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-20S-0.5SH, 20 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+22
+21
+Connector_FFC-FPC
+Hirose_FH12-22S-0.5SH_1x22-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-22S-0.5SH, 22 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+24
+23
+Connector_FFC-FPC
+Hirose_FH12-24S-0.5SH_1x24-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-24S-0.5SH, 24 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+26
+25
+Connector_FFC-FPC
+Hirose_FH12-25S-0.5SH_1x25-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-25S-0.5SH, 25 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+27
+26
+Connector_FFC-FPC
+Hirose_FH12-26S-0.5SH_1x26-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-26S-0.5SH, 26 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+28
+27
+Connector_FFC-FPC
+Hirose_FH12-28S-0.5SH_1x28-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-28S-0.5SH, 28 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+30
+29
+Connector_FFC-FPC
+Hirose_FH12-30S-0.5SH_1x30-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-30S-0.5SH, 30 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+32
+31
+Connector_FFC-FPC
+Hirose_FH12-32S-0.5SH_1x32-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-32S-0.5SH, 32 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+34
+33
+Connector_FFC-FPC
+Hirose_FH12-33S-0.5SH_1x33-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-33S-0.5SH, 33 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+35
+34
+Connector_FFC-FPC
+Hirose_FH12-34S-0.5SH_1x34-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-34S-0.5SH, 34 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+36
+35
+Connector_FFC-FPC
+Hirose_FH12-35S-0.5SH_1x35-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-35S-0.5SH, 35 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+37
+36
+Connector_FFC-FPC
+Hirose_FH12-36S-0.5SH_1x36-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-36S-0.5SH, 36 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+38
+37
+Connector_FFC-FPC
+Hirose_FH12-40S-0.5SH_1x40-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-40S-0.5SH, 40 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+42
+41
+Connector_FFC-FPC
+Hirose_FH12-45S-0.5SH_1x45-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-45S-0.5SH, 45 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+47
+46
+Connector_FFC-FPC
+Hirose_FH12-50S-0.5SH_1x50-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-50S-0.5SH, 50 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+52
+51
+Connector_FFC-FPC
+Hirose_FH12-53S-0.5SH_1x53-1MP_P0.50mm_Horizontal
+Hirose FH12, FFC/FPC connector, FH12-53S-0.5SH, 53 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator
+connector Hirose FH12 horizontal
+0
+55
+54
+Connector_FFC-FPC
+JAE_FF0825SA1_2Rows-25Pins_P0.40mm_Horizontal
+Molex JAE 0.2mm pitch, 1mm overall height FFC/FPC connector, FF0825SA1, 25 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ108178.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+25
+25
+Connector_FFC-FPC
+JAE_FF0829SA1_2Rows-29Pins_P0.40mm_Horizontal
+Molex JAE 0.2mm pitch, 1mm overall height FFC/FPC connector, FF0829SA1, 29 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ108178.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+29
+29
+Connector_FFC-FPC
+JAE_FF0841SA1_2Rows-41Pins_P0.40mm_Horizontal
+Molex JAE 0.2mm pitch, 1mm overall height FFC/FPC connector, FF0841SA1, 41 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ108178.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+41
+41
+Connector_FFC-FPC
+JAE_FF0851SA1_2Rows-51Pins_P0.40mm_Horizontal
+Molex JAE 0.2mm pitch, 1mm overall height FFC/FPC connector, FF0851SA1, 51 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ108178.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+51
+51
+Connector_FFC-FPC
+JAE_FF0871SA1_2Rows-71Pins_P0.40mm_Horizontal
+Molex JAE 0.2mm pitch, 1mm overall height FFC/FPC connector, FF0871SA1, 71 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ108178.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+71
+71
+Connector_FFC-FPC
+JAE_FF0881SA1_2Rows-81Pins_P0.40mm_Horizontal
+Molex JAE 0.2mm pitch, 1mm overall height FFC/FPC connector, FF0881SA1, 81 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ108178.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+81
+81
+Connector_FFC-FPC
+Molex_54132-5033_1x50-1MP_P0.5mm_Horizontal
+Molex FFC/FPC connector, 50 bottom-side contacts, 0.5mm pitch, 2.0mm height, https://www.molex.com/pdm_docs/sd/541325033_sd.pdf
+FFC FPC
+0
+54
+51
+Connector_FFC-FPC
+Molex_200528-0040_1x04-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0040, 4 Circuits (https://www.molex.com/pdm_docs/sd/2005280040_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+6
+5
+Connector_FFC-FPC
+Molex_200528-0050_1x05-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0050, 5 Circuits (https://www.molex.com/pdm_docs/sd/2005280050_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+7
+6
+Connector_FFC-FPC
+Molex_200528-0060_1x06-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0060, 6 Circuits (https://www.molex.com/pdm_docs/sd/2005280060_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+8
+7
+Connector_FFC-FPC
+Molex_200528-0070_1x07-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0070, 7 Circuits (https://www.molex.com/pdm_docs/sd/2005280070_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+9
+8
+Connector_FFC-FPC
+Molex_200528-0080_1x08-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0080, 8 Circuits (https://www.molex.com/pdm_docs/sd/2005280080_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+10
+9
+Connector_FFC-FPC
+Molex_200528-0090_1x09-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0090, 9 Circuits (https://www.molex.com/pdm_docs/sd/2005280090_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+11
+10
+Connector_FFC-FPC
+Molex_200528-0100_1x10-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0100, 10 Circuits (https://www.molex.com/pdm_docs/sd/2005280100_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+12
+11
+Connector_FFC-FPC
+Molex_200528-0110_1x11-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0110, 11 Circuits (https://www.molex.com/pdm_docs/sd/2005280110_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+13
+12
+Connector_FFC-FPC
+Molex_200528-0120_1x12-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0120, 12 Circuits (https://www.molex.com/pdm_docs/sd/2005280120_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+14
+13
+Connector_FFC-FPC
+Molex_200528-0130_1x13-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0130, 13 Circuits (https://www.molex.com/pdm_docs/sd/2005280130_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+15
+14
+Connector_FFC-FPC
+Molex_200528-0140_1x14-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0140, 14 Circuits (https://www.molex.com/pdm_docs/sd/2005280140_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+16
+15
+Connector_FFC-FPC
+Molex_200528-0150_1x15-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0150, 15 Circuits (https://www.molex.com/pdm_docs/sd/2005280150_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+17
+16
+Connector_FFC-FPC
+Molex_200528-0160_1x16-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0160, 16 Circuits (https://www.molex.com/pdm_docs/sd/2005280160_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+18
+17
+Connector_FFC-FPC
+Molex_200528-0170_1x17-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0170, 17 Circuits (https://www.molex.com/pdm_docs/sd/2005280170_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+19
+18
+Connector_FFC-FPC
+Molex_200528-0180_1x18-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0180, 18 Circuits (https://www.molex.com/pdm_docs/sd/2005280180_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+20
+19
+Connector_FFC-FPC
+Molex_200528-0190_1x19-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0190, 19 Circuits (https://www.molex.com/pdm_docs/sd/2005280190_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+21
+20
+Connector_FFC-FPC
+Molex_200528-0200_1x20-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0200, 20 Circuits (https://www.molex.com/pdm_docs/sd/2005280200_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+22
+21
+Connector_FFC-FPC
+Molex_200528-0210_1x21-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0210, 21 Circuits (https://www.molex.com/pdm_docs/sd/2005280210_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+23
+22
+Connector_FFC-FPC
+Molex_200528-0220_1x22-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0220, 22 Circuits (https://www.molex.com/pdm_docs/sd/2005280220_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+24
+23
+Connector_FFC-FPC
+Molex_200528-0230_1x23-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0230, 23 Circuits (https://www.molex.com/pdm_docs/sd/2005280230_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+25
+24
+Connector_FFC-FPC
+Molex_200528-0240_1x24-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0240, 24 Circuits (https://www.molex.com/pdm_docs/sd/2005280240_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+26
+25
+Connector_FFC-FPC
+Molex_200528-0250_1x25-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0250, 25 Circuits (https://www.molex.com/pdm_docs/sd/2005280250_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+27
+26
+Connector_FFC-FPC
+Molex_200528-0260_1x26-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0260, 26 Circuits (https://www.molex.com/pdm_docs/sd/2005280260_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+28
+27
+Connector_FFC-FPC
+Molex_200528-0270_1x27-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0270, 27 Circuits (https://www.molex.com/pdm_docs/sd/2005280270_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+29
+28
+Connector_FFC-FPC
+Molex_200528-0280_1x28-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0280, 28 Circuits (https://www.molex.com/pdm_docs/sd/2005280280_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+30
+29
+Connector_FFC-FPC
+Molex_200528-0290_1x29-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0290, 29 Circuits (https://www.molex.com/pdm_docs/sd/2005280290_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+31
+30
+Connector_FFC-FPC
+Molex_200528-0300_1x30-1MP_P1.00mm_Horizontal
+Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0300, 30 Circuits (https://www.molex.com/pdm_docs/sd/2005280300_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+32
+31
+Connector_FFC-FPC
+Molex_502231-1500_1x15-1SH_P0.5mm_Vertical
+Molex 0.50mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 6.05mm Height, Vertical, Surface Mount, ZIF, 15 Circuits (https://www.molex.com/pdm_docs/sd/5022311500_sd.pdf)
+molex FFC/FPC connector Pitch 0.5mm vertical
+0
+17
+16
+Connector_FFC-FPC
+Molex_502231-2400_1x24-1SH_P0.5mm_Vertical
+Molex 0.50mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 6.05mm Height, Vertical, Surface Mount, ZIF, 24 Circuits (https://www.molex.com/pdm_docs/sd/5022312400_sd.pdf)
+molex FFC/FPC connector Pitch 0.5mm vertical
+0
+26
+25
+Connector_FFC-FPC
+Molex_502231-3300_1x33-1SH_P0.5mm_Vertical
+Molex 0.50mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 6.05mm Height, Vertical, Surface Mount, ZIF, 33 Circuits (https://www.molex.com/pdm_docs/sd/5022313300_sd.pdf)
+molex FFC/FPC connector Pitch 0.5mm vertical
+0
+36
+34
+Connector_FFC-FPC
+Molex_502244-1530_1x15-1MP_P0.5mm_Horizontal
+Molex 0.50mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 2.33mm Height, Right Angle, Surface Mount, ZIF, Bottom Contact Style, 15 Circuits (http://www.molex.com/pdm_docs/sd/5022441530_sd.pdf)
+molex FFC/FPC connector Pitch 0.5mm right angle
+0
+19
+16
+Connector_FFC-FPC
+Molex_502244-2430_1x24-1MP_P0.5mm_Horizontal
+Molex 0.50mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 2.33mm Height, Right Angle, Surface Mount, ZIF, Bottom Contact Style, 24 Circuits (http://www.molex.com/pdm_docs/sd/5022441530_sd.pdf)
+molex FFC/FPC connector Pitch 0.5mm right angle
+0
+28
+25
+Connector_FFC-FPC
+Molex_502244-3330_1x33-1MP_P0.5mm_Horizontal
+Molex 0.50mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 2.33mm Height, Right Angle, Surface Mount, ZIF, Bottom Contact Style, 33 Circuits (http://www.molex.com/pdm_docs/sd/5022441530_sd.pdf)
+molex FFC/FPC connector Pitch 0.5mm right angle
+0
+39
+34
+Connector_FFC-FPC
+Molex_502250-1791_2Rows-17Pins-1MP_P0.60mm_Horizontal
+Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-1791, 17 Circuits (http://www.molex.com/pdm_docs/sd/5022501791_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+19
+18
+Connector_FFC-FPC
+Molex_502250-2191_2Rows-21Pins-1MP_P0.60mm_Horizontal
+Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-2191, 21 Circuits (http://www.molex.com/pdm_docs/sd/5022502191_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+23
+22
+Connector_FFC-FPC
+Molex_502250-2391_2Rows-23Pins-1MP_P0.60mm_Horizontal
+Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-2391, 23 Circuits (http://www.molex.com/pdm_docs/sd/5022502391_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+25
+24
+Connector_FFC-FPC
+Molex_502250-2791_2Rows-27Pins-1MP_P0.60mm_Horizontal
+Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-2791, 27 Circuits (http://www.molex.com/pdm_docs/sd/5022502791_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+29
+28
+Connector_FFC-FPC
+Molex_502250-3391_2Rows-33Pins-1MP_P0.60mm_Horizontal
+Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-3391, 33 Circuits (http://www.molex.com/pdm_docs/sd/5022503391_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+35
+34
+Connector_FFC-FPC
+Molex_502250-3591_2Rows-35Pins-1MP_P0.60mm_Horizontal
+Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-3591, 35 Circuits (http://www.molex.com/pdm_docs/sd/5022503591_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+37
+36
+Connector_FFC-FPC
+Molex_502250-3991_2Rows-39Pins-1MP_P0.60mm_Horizontal
+Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-3991, 39 Circuits (http://www.molex.com/pdm_docs/sd/5022503991_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+41
+40
+Connector_FFC-FPC
+Molex_502250-4191_2Rows-41Pins-1MP_P0.60mm_Horizontal
+Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-4191, 41 Circuits (http://www.molex.com/pdm_docs/sd/5022504191_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+43
+42
+Connector_FFC-FPC
+Molex_502250-5191_2Rows-51Pins-1MP_P0.60mm_Horizontal
+Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-5191, 51 Circuits (http://www.molex.com/pdm_docs/sd/5022505191_sd.pdf), generated with kicad-footprint-generator
+connector Molex  top entry
+0
+53
+52
+Connector_FFC-FPC
+TE_0-1734839-5_1x05-1MP_P0.5mm_Horizontal
+TE FPC connector, 05 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+7
+6
+Connector_FFC-FPC
+TE_0-1734839-6_1x06-1MP_P0.5mm_Horizontal
+TE FPC connector, 06 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+8
+7
+Connector_FFC-FPC
+TE_0-1734839-7_1x07-1MP_P0.5mm_Horizontal
+TE FPC connector, 07 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+9
+8
+Connector_FFC-FPC
+TE_0-1734839-8_1x08-1MP_P0.5mm_Horizontal
+TE FPC connector, 08 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+10
+9
+Connector_FFC-FPC
+TE_0-1734839-9_1x09-1MP_P0.5mm_Horizontal
+TE FPC connector, 09 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+11
+10
+Connector_FFC-FPC
+TE_1-84952-0_1x10-1MP_P1.0mm_Horizontal
+TE FPC connector, 10 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+12
+11
+Connector_FFC-FPC
+TE_1-84952-1_1x11-1MP_P1.0mm_Horizontal
+TE FPC connector, 11 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+13
+12
+Connector_FFC-FPC
+TE_1-84952-2_1x12-1MP_P1.0mm_Horizontal
+TE FPC connector, 12 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+14
+13
+Connector_FFC-FPC
+TE_1-84952-3_1x13-1MP_P1.0mm_Horizontal
+TE FPC connector, 13 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+15
+14
+Connector_FFC-FPC
+TE_1-84952-4_1x14-1MP_P1.0mm_Horizontal
+TE FPC connector, 14 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+16
+15
+Connector_FFC-FPC
+TE_1-84952-5_1x15-1MP_P1.0mm_Horizontal
+TE FPC connector, 15 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+17
+16
+Connector_FFC-FPC
+TE_1-84952-6_1x16-1MP_P1.0mm_Horizontal
+TE FPC connector, 16 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+18
+17
+Connector_FFC-FPC
+TE_1-84952-7_1x17-1MP_P1.0mm_Horizontal
+TE FPC connector, 17 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+19
+18
+Connector_FFC-FPC
+TE_1-84952-8_1x18-1MP_P1.0mm_Horizontal
+TE FPC connector, 18 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+20
+19
+Connector_FFC-FPC
+TE_1-84952-9_1x19-1MP_P1.0mm_Horizontal
+TE FPC connector, 19 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+21
+20
+Connector_FFC-FPC
+TE_1-84953-0_1x10-1MP_P1.0mm_Horizontal
+TE FPC connector, 10 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+12
+11
+Connector_FFC-FPC
+TE_1-84953-1_1x11-1MP_P1.0mm_Horizontal
+TE FPC connector, 11 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+13
+12
+Connector_FFC-FPC
+TE_1-84953-2_1x12-1MP_P1.0mm_Horizontal
+TE FPC connector, 12 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+14
+13
+Connector_FFC-FPC
+TE_1-84953-3_1x13-1MP_P1.0mm_Horizontal
+TE FPC connector, 13 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+15
+14
+Connector_FFC-FPC
+TE_1-84953-4_1x14-1MP_P1.0mm_Horizontal
+TE FPC connector, 14 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+16
+15
+Connector_FFC-FPC
+TE_1-84953-5_1x15-1MP_P1.0mm_Horizontal
+TE FPC connector, 15 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+17
+16
+Connector_FFC-FPC
+TE_1-84953-6_1x16-1MP_P1.0mm_Horizontal
+TE FPC connector, 16 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+18
+17
+Connector_FFC-FPC
+TE_1-84953-7_1x17-1MP_P1.0mm_Horizontal
+TE FPC connector, 17 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+19
+18
+Connector_FFC-FPC
+TE_1-84953-8_1x18-1MP_P1.0mm_Horizontal
+TE FPC connector, 18 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+20
+19
+Connector_FFC-FPC
+TE_1-84953-9_1x19-1MP_P1.0mm_Horizontal
+TE FPC connector, 19 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+21
+20
+Connector_FFC-FPC
+TE_1-1734839-0_1x10-1MP_P0.5mm_Horizontal
+TE FPC connector, 10 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+12
+11
+Connector_FFC-FPC
+TE_1-1734839-1_1x11-1MP_P0.5mm_Horizontal
+TE FPC connector, 11 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+13
+12
+Connector_FFC-FPC
+TE_1-1734839-2_1x12-1MP_P0.5mm_Horizontal
+TE FPC connector, 12 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+14
+13
+Connector_FFC-FPC
+TE_1-1734839-3_1x13-1MP_P0.5mm_Horizontal
+TE FPC connector, 13 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+15
+14
+Connector_FFC-FPC
+TE_1-1734839-4_1x14-1MP_P0.5mm_Horizontal
+TE FPC connector, 14 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+16
+15
+Connector_FFC-FPC
+TE_1-1734839-5_1x15-1MP_P0.5mm_Horizontal
+TE FPC connector, 15 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+17
+16
+Connector_FFC-FPC
+TE_1-1734839-6_1x16-1MP_P0.5mm_Horizontal
+TE FPC connector, 16 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+18
+17
+Connector_FFC-FPC
+TE_1-1734839-7_1x17-1MP_P0.5mm_Horizontal
+TE FPC connector, 17 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+19
+18
+Connector_FFC-FPC
+TE_1-1734839-8_1x18-1MP_P0.5mm_Horizontal
+TE FPC connector, 18 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+20
+19
+Connector_FFC-FPC
+TE_1-1734839-9_1x19-1MP_P0.5mm_Horizontal
+TE FPC connector, 19 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+21
+20
+Connector_FFC-FPC
+TE_2-84952-0_1x20-1MP_P1.0mm_Horizontal
+TE FPC connector, 20 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+22
+21
+Connector_FFC-FPC
+TE_2-84952-1_1x21-1MP_P1.0mm_Horizontal
+TE FPC connector, 21 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+23
+22
+Connector_FFC-FPC
+TE_2-84952-2_1x22-1MP_P1.0mm_Horizontal
+TE FPC connector, 22 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+24
+23
+Connector_FFC-FPC
+TE_2-84952-3_1x23-1MP_P1.0mm_Horizontal
+TE FPC connector, 23 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+25
+24
+Connector_FFC-FPC
+TE_2-84952-4_1x24-1MP_P1.0mm_Horizontal
+TE FPC connector, 24 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+26
+25
+Connector_FFC-FPC
+TE_2-84952-5_1x25-1MP_P1.0mm_Horizontal
+TE FPC connector, 25 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+27
+26
+Connector_FFC-FPC
+TE_2-84952-6_1x26-1MP_P1.0mm_Horizontal
+TE FPC connector, 26 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+28
+27
+Connector_FFC-FPC
+TE_2-84952-7_1x27-1MP_P1.0mm_Horizontal
+TE FPC connector, 27 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+29
+28
+Connector_FFC-FPC
+TE_2-84952-8_1x28-1MP_P1.0mm_Horizontal
+TE FPC connector, 28 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+30
+29
+Connector_FFC-FPC
+TE_2-84952-9_1x29-1MP_P1.0mm_Horizontal
+TE FPC connector, 29 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+31
+30
+Connector_FFC-FPC
+TE_2-84953-0_1x20-1MP_P1.0mm_Horizontal
+TE FPC connector, 20 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+22
+21
+Connector_FFC-FPC
+TE_2-84953-1_1x21-1MP_P1.0mm_Horizontal
+TE FPC connector, 21 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+23
+22
+Connector_FFC-FPC
+TE_2-84953-2_1x22-1MP_P1.0mm_Horizontal
+TE FPC connector, 22 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+24
+23
+Connector_FFC-FPC
+TE_2-84953-3_1x23-1MP_P1.0mm_Horizontal
+TE FPC connector, 23 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+25
+24
+Connector_FFC-FPC
+TE_2-84953-4_1x24-1MP_P1.0mm_Horizontal
+TE FPC connector, 24 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+26
+25
+Connector_FFC-FPC
+TE_2-84953-5_1x25-1MP_P1.0mm_Horizontal
+TE FPC connector, 25 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+27
+26
+Connector_FFC-FPC
+TE_2-84953-6_1x26-1MP_P1.0mm_Horizontal
+TE FPC connector, 26 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+28
+27
+Connector_FFC-FPC
+TE_2-84953-7_1x27-1MP_P1.0mm_Horizontal
+TE FPC connector, 27 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+29
+28
+Connector_FFC-FPC
+TE_2-84953-8_1x28-1MP_P1.0mm_Horizontal
+TE FPC connector, 28 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+30
+29
+Connector_FFC-FPC
+TE_2-84953-9_1x29-1MP_P1.0mm_Horizontal
+TE FPC connector, 29 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+31
+30
+Connector_FFC-FPC
+TE_2-1734839-0_1x20-1MP_P0.5mm_Horizontal
+TE FPC connector, 20 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+22
+21
+Connector_FFC-FPC
+TE_2-1734839-1_1x21-1MP_P0.5mm_Horizontal
+TE FPC connector, 21 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+23
+22
+Connector_FFC-FPC
+TE_2-1734839-2_1x22-1MP_P0.5mm_Horizontal
+TE FPC connector, 22 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+24
+23
+Connector_FFC-FPC
+TE_2-1734839-3_1x23-1MP_P0.5mm_Horizontal
+TE FPC connector, 23 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+25
+24
+Connector_FFC-FPC
+TE_2-1734839-4_1x24-1MP_P0.5mm_Horizontal
+TE FPC connector, 24 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+26
+25
+Connector_FFC-FPC
+TE_2-1734839-5_1x25-1MP_P0.5mm_Horizontal
+TE FPC connector, 25 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+27
+26
+Connector_FFC-FPC
+TE_2-1734839-6_1x26-1MP_P0.5mm_Horizontal
+TE FPC connector, 26 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+28
+27
+Connector_FFC-FPC
+TE_2-1734839-7_1x27-1MP_P0.5mm_Horizontal
+TE FPC connector, 27 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+29
+28
+Connector_FFC-FPC
+TE_2-1734839-8_1x28-1MP_P0.5mm_Horizontal
+TE FPC connector, 28 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+30
+29
+Connector_FFC-FPC
+TE_2-1734839-9_1x29-1MP_P0.5mm_Horizontal
+TE FPC connector, 29 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+31
+30
+Connector_FFC-FPC
+TE_3-84952-0_1x30-1MP_P1.0mm_Horizontal
+TE FPC connector, 30 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+32
+31
+Connector_FFC-FPC
+TE_3-84953-0_1x30-1MP_P1.0mm_Horizontal
+TE FPC connector, 30 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+32
+31
+Connector_FFC-FPC
+TE_3-1734839-0_1x30-1MP_P0.5mm_Horizontal
+TE FPC connector, 30 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+32
+31
+Connector_FFC-FPC
+TE_3-1734839-1_1x31-1MP_P0.5mm_Horizontal
+TE FPC connector, 31 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+33
+32
+Connector_FFC-FPC
+TE_3-1734839-2_1x32-1MP_P0.5mm_Horizontal
+TE FPC connector, 32 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+34
+33
+Connector_FFC-FPC
+TE_3-1734839-3_1x33-1MP_P0.5mm_Horizontal
+TE FPC connector, 33 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+35
+34
+Connector_FFC-FPC
+TE_3-1734839-4_1x34-1MP_P0.5mm_Horizontal
+TE FPC connector, 34 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+36
+35
+Connector_FFC-FPC
+TE_3-1734839-5_1x35-1MP_P0.5mm_Horizontal
+TE FPC connector, 35 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+37
+36
+Connector_FFC-FPC
+TE_3-1734839-6_1x36-1MP_P0.5mm_Horizontal
+TE FPC connector, 36 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+38
+37
+Connector_FFC-FPC
+TE_3-1734839-7_1x37-1MP_P0.5mm_Horizontal
+TE FPC connector, 37 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+39
+38
+Connector_FFC-FPC
+TE_3-1734839-8_1x38-1MP_P0.5mm_Horizontal
+TE FPC connector, 38 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+40
+39
+Connector_FFC-FPC
+TE_3-1734839-9_1x39-1MP_P0.5mm_Horizontal
+TE FPC connector, 39 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+41
+40
+Connector_FFC-FPC
+TE_4-1734839-0_1x40-1MP_P0.5mm_Horizontal
+TE FPC connector, 40 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+42
+41
+Connector_FFC-FPC
+TE_4-1734839-1_1x41-1MP_P0.5mm_Horizontal
+TE FPC connector, 41 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+43
+42
+Connector_FFC-FPC
+TE_4-1734839-2_1x42-1MP_P0.5mm_Horizontal
+TE FPC connector, 42 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+44
+43
+Connector_FFC-FPC
+TE_4-1734839-3_1x43-1MP_P0.5mm_Horizontal
+TE FPC connector, 43 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+45
+44
+Connector_FFC-FPC
+TE_4-1734839-4_1x44-1MP_P0.5mm_Horizontal
+TE FPC connector, 44 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+46
+45
+Connector_FFC-FPC
+TE_4-1734839-5_1x45-1MP_P0.5mm_Horizontal
+TE FPC connector, 45 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+47
+46
+Connector_FFC-FPC
+TE_4-1734839-6_1x46-1MP_P0.5mm_Horizontal
+TE FPC connector, 46 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+48
+47
+Connector_FFC-FPC
+TE_4-1734839-7_1x47-1MP_P0.5mm_Horizontal
+TE FPC connector, 47 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+49
+48
+Connector_FFC-FPC
+TE_4-1734839-8_1x48-1MP_P0.5mm_Horizontal
+TE FPC connector, 48 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+50
+49
+Connector_FFC-FPC
+TE_4-1734839-9_1x49-1MP_P0.5mm_Horizontal
+TE FPC connector, 49 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+51
+50
+Connector_FFC-FPC
+TE_5-1734839-0_1x50-1MP_P0.5mm_Horizontal
+TE FPC connector, 50 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0
+te fpc 1734839
+0
+52
+51
+Connector_FFC-FPC
+TE_84952-4_1x04-1MP_P1.0mm_Horizontal
+TE FPC connector, 04 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+6
+5
+Connector_FFC-FPC
+TE_84952-5_1x05-1MP_P1.0mm_Horizontal
+TE FPC connector, 05 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+7
+6
+Connector_FFC-FPC
+TE_84952-6_1x06-1MP_P1.0mm_Horizontal
+TE FPC connector, 06 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+8
+7
+Connector_FFC-FPC
+TE_84952-7_1x07-1MP_P1.0mm_Horizontal
+TE FPC connector, 07 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+9
+8
+Connector_FFC-FPC
+TE_84952-8_1x08-1MP_P1.0mm_Horizontal
+TE FPC connector, 08 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+10
+9
+Connector_FFC-FPC
+TE_84952-9_1x09-1MP_P1.0mm_Horizontal
+TE FPC connector, 09 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4
+te fpc 84952
+0
+11
+10
+Connector_FFC-FPC
+TE_84953-4_1x04-1MP_P1.0mm_Horizontal
+TE FPC connector, 04 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+6
+5
+Connector_FFC-FPC
+TE_84953-5_1x05-1MP_P1.0mm_Horizontal
+TE FPC connector, 05 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+7
+6
+Connector_FFC-FPC
+TE_84953-6_1x06-1MP_P1.0mm_Horizontal
+TE FPC connector, 06 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+8
+7
+Connector_FFC-FPC
+TE_84953-7_1x07-1MP_P1.0mm_Horizontal
+TE FPC connector, 07 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+9
+8
+Connector_FFC-FPC
+TE_84953-8_1x08-1MP_P1.0mm_Horizontal
+TE FPC connector, 08 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+10
+9
+Connector_FFC-FPC
+TE_84953-9_1x09-1MP_P1.0mm_Horizontal
+TE FPC connector, 09 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4
+te fpc 84953
+0
+11
+10
+Connector_FFC-FPC
+Wuerth_68611214422_1x12-1MP_P1.0mm_Horizontal
+http://katalog.we-online.de/em/datasheet/68611214422.pdf
+Wuerth FPC 68611214422 connector 12 bottom-side contacts 1.0mm pitch 1.0mm height SMT
+0
+14
+13
+Connector_HDMI
+HDMI_A_Contact_Technology_HDMI-19APL2_Horizontal
+HDMI Contact Technology Type A http://www.contactswitch.com/en/download.aspx?id=1449
+HDMI Contact Technology Type A
+0
+23
+20
+Connector_HDMI
+HDMI_A_Kycon_KDMIX-SL1-NS-WS-B15_VerticalRightAngle
+HDMI, Type A, Kycon KDMIX-SL1-NS-WS-B15, Vertical Right Angle, http://www.kycon.com/Pub_Eng_Draw/KDMIX-SL1-NS-WS-B15.pdf
+hdmi type a
+0
+23
+20
+Connector_HDMI
+HDMI_Micro-D_Molex_46765-0x01
+HDMI, Micro, Type D, SMD, 0.4mm pitch, 19 ckt, right angle (http://www.molex.com/pdm_docs/sd/467651301_sd.pdf)
+hdmi micro type d right angle smd
+0
+23
+20
+Connector_HDMI
+HDMI_Micro-D_Molex_46765-1x01
+HDMI, Micro, Type D, THT, 0.4mm pitch, 19 ckt, right angle (http://www.molex.com/pdm_docs/sd/467651301_sd.pdf)
+hdmi micro type d right angle tht
+0
+23
+20
+Connector_HDMI
+HDMI_Micro-D_Molex_46765-2x0x
+HDMI, Micro, Type D, THT/SMD hybrid, 0.4mm pitch, 19 ckt, right angle (http://www.molex.com/pdm_docs/sd/467651301_sd.pdf)
+hdmi micro type d right angle tht smd hybrid 
+0
+23
+20
+Connector_Harwin
+Harwin_Gecko-G125-FVX0605L0X_2x03_P1.25mm_Vertical
+Harwin Gecko Connector, 6 pins, dual row female, vertical entry, PN:G125-FVX0605L0X
+connector harwin gecko
+0
+6
+6
+Connector_Harwin
+Harwin_Gecko-G125-FVX1005L0X_2x05_P1.25mm_Vertical
+Harwin Gecko Connector, 10 pins, dual row female, vertical entry, PN:G125-FVX1005L0X
+connector harwin gecko
+0
+10
+10
+Connector_Harwin
+Harwin_Gecko-G125-FVX1205L0X_2x06_P1.25mm_Vertical
+Harwin Gecko Connector, 12 pins, dual row female, vertical entry, PN:G125-FVX1205L0X
+connector harwin gecko
+0
+12
+12
+Connector_Harwin
+Harwin_Gecko-G125-FVX1605L0X_2x08_P1.25mm_Vertical
+Harwin Gecko Connector, 16 pins, dual row female, vertical entry, PN:G125-FVX1605L0X
+connector harwin gecko
+0
+16
+16
+Connector_Harwin
+Harwin_Gecko-G125-FVX2005L0X_2x10_P1.25mm_Vertical
+Harwin Gecko Connector, 20 pins, dual row female, vertical entry, PN:G125-FVX2005L0X
+connector harwin gecko
+0
+20
+20
+Connector_Harwin
+Harwin_Gecko-G125-FVX2605L0X_2x13_P1.25mm_Vertical
+Harwin Gecko Connector, 26 pins, dual row female, vertical entry, PN:G125-FVX2605L0X
+connector harwin gecko
+0
+26
+26
+Connector_Harwin
+Harwin_Gecko-G125-FVX3405L0X_2x17_P1.25mm_Vertical
+Harwin Gecko Connector, 34 pins, dual row female, vertical entry, PN:G125-FVX3405L0X
+connector harwin gecko
+0
+34
+34
+Connector_Harwin
+Harwin_Gecko-G125-FVX5005L0X_2x25_P1.25mm_Vertical
+Harwin Gecko Connector, 50 pins, dual row female, vertical entry, PN:G125-FVX5005L0X
+connector harwin gecko
+0
+50
+50
+Connector_Harwin
+Harwin_Gecko-G125-MVX0605L0X_2x03_P1.25mm_Vertical
+Harwin Gecko Connector, 6 pins, dual row male, vertical entry, no latches, PN:G125-MVX0605L0X
+connector harwin gecko
+0
+6
+6
+Connector_Harwin
+Harwin_Gecko-G125-MVX0605L1X_2x03_P1.25mm_Vertical
+Harwin Gecko Connector, 6 pins, dual row male, vertical entry, with latches, PN:G125-MVX0605L1X
+connector harwin gecko
+0
+6
+6
+Connector_Harwin
+Harwin_Gecko-G125-MVX1005L0X_2x05_P1.25mm_Vertical
+Harwin Gecko Connector, 10 pins, dual row male, vertical entry, no latches, PN:G125-MVX1005L0X
+connector harwin gecko
+0
+10
+10
+Connector_Harwin
+Harwin_Gecko-G125-MVX1005L1X_2x05_P1.25mm_Vertical
+Harwin Gecko Connector, 10 pins, dual row male, vertical entry, with latches, PN:G125-MVX1005L1X
+connector harwin gecko
+0
+10
+10
+Connector_Harwin
+Harwin_Gecko-G125-MVX1205L0X_2x06_P1.25mm_Vertical
+Harwin Gecko Connector, 12 pins, dual row male, vertical entry, no latches, PN:G125-MVX1205L0X
+connector harwin gecko
+0
+12
+12
+Connector_Harwin
+Harwin_Gecko-G125-MVX1205L1X_2x06_P1.25mm_Vertical
+Harwin Gecko Connector, 12 pins, dual row male, vertical entry, with latches, PN:G125-MVX1205L1X
+connector harwin gecko
+0
+12
+12
+Connector_Harwin
+Harwin_Gecko-G125-MVX1605L0X_2x08_P1.25mm_Vertical
+Harwin Gecko Connector, 16 pins, dual row male, vertical entry, no latches, PN:G125-MVX1605L0X
+connector harwin gecko
+0
+16
+16
+Connector_Harwin
+Harwin_Gecko-G125-MVX1605L1X_2x08_P1.25mm_Vertical
+Harwin Gecko Connector, 16 pins, dual row male, vertical entry, with latches, PN:G125-MVX1605L1X
+connector harwin gecko
+0
+16
+16
+Connector_Harwin
+Harwin_Gecko-G125-MVX2005L0X_2x10_P1.25mm_Vertical
+Harwin Gecko Connector, 20 pins, dual row male, vertical entry, no latches, PN:G125-MVX2005L0X
+connector harwin gecko
+0
+20
+20
+Connector_Harwin
+Harwin_Gecko-G125-MVX2005L1X_2x10_P1.25mm_Vertical
+Harwin Gecko Connector, 20 pins, dual row male, vertical entry, with latches, PN:G125-MVX2005L1X
+connector harwin gecko
+0
+20
+20
+Connector_Harwin
+Harwin_Gecko-G125-MVX2605L0X_2x13_P1.25mm_Vertical
+Harwin Gecko Connector, 26 pins, dual row male, vertical entry, no latches, PN:G125-MVX2605L0X
+connector harwin gecko
+0
+26
+26
+Connector_Harwin
+Harwin_Gecko-G125-MVX2605L1X_2x13_P1.25mm_Vertical
+Harwin Gecko Connector, 26 pins, dual row male, vertical entry, with latches, PN:G125-MVX2605L1X
+connector harwin gecko
+0
+26
+26
+Connector_Harwin
+Harwin_Gecko-G125-MVX3405L0X_2x17_P1.25mm_Vertical
+Harwin Gecko Connector, 34 pins, dual row male, vertical entry, no latches, PN:G125-MVX3405L0X
+connector harwin gecko
+0
+34
+34
+Connector_Harwin
+Harwin_Gecko-G125-MVX3405L1X_2x17_P1.25mm_Vertical
+Harwin Gecko Connector, 34 pins, dual row male, vertical entry, with latches, PN:G125-MVX3405L1X
+connector harwin gecko
+0
+34
+34
+Connector_Harwin
+Harwin_Gecko-G125-MVX5005L0X_2x25_P1.25mm_Vertical
+Harwin Gecko Connector, 50 pins, dual row male, vertical entry, no latches, PN:G125-MVX5005L0X
+connector harwin gecko
+0
+50
+50
+Connector_Harwin
+Harwin_Gecko-G125-MVX5005L1X_2x25_P1.25mm_Vertical
+Harwin Gecko Connector, 50 pins, dual row male, vertical entry, with latches, PN:G125-MVX5005L1X
+connector harwin gecko
+0
+50
+50
+Connector_Harwin
+Harwin_LTek-Male_02_P2.00mm_Vertical
+Harwin LTek Connector, 2 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+2
+2
+Connector_Harwin
+Harwin_LTek-Male_02_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 2 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+6
+2
+Connector_Harwin
+Harwin_LTek-Male_2x02_P2.00mm_Vertical
+Harwin LTek Connector, 4 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+4
+4
+Connector_Harwin
+Harwin_LTek-Male_2x02_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 4 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+8
+4
+Connector_Harwin
+Harwin_LTek-Male_2x03_P2.00mm_Vertical
+Harwin LTek Connector, 6 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+6
+6
+Connector_Harwin
+Harwin_LTek-Male_2x03_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 6 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+10
+6
+Connector_Harwin
+Harwin_LTek-Male_2x04_P2.00mm_Vertical
+Harwin LTek Connector, 8 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+8
+8
+Connector_Harwin
+Harwin_LTek-Male_2x04_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 8 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+12
+8
+Connector_Harwin
+Harwin_LTek-Male_2x05_P2.00mm_Vertical
+Harwin LTek Connector, 10 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+10
+10
+Connector_Harwin
+Harwin_LTek-Male_2x05_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 10 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+14
+10
+Connector_Harwin
+Harwin_LTek-Male_2x06_P2.00mm_Vertical
+Harwin LTek Connector, 12 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+12
+12
+Connector_Harwin
+Harwin_LTek-Male_2x06_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 12 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+16
+12
+Connector_Harwin
+Harwin_LTek-Male_2x07_P2.00mm_Vertical
+Harwin LTek Connector, 14 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+14
+14
+Connector_Harwin
+Harwin_LTek-Male_2x07_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 14 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+18
+14
+Connector_Harwin
+Harwin_LTek-Male_2x08_P2.00mm_Vertical
+Harwin LTek Connector, 16 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+16
+16
+Connector_Harwin
+Harwin_LTek-Male_2x08_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 16 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+20
+16
+Connector_Harwin
+Harwin_LTek-Male_2x09_P2.00mm_Vertical
+Harwin LTek Connector, 18 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+18
+18
+Connector_Harwin
+Harwin_LTek-Male_2x09_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 18 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+22
+18
+Connector_Harwin
+Harwin_LTek-Male_2x10_P2.00mm_Vertical
+Harwin LTek Connector, 20 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+20
+20
+Connector_Harwin
+Harwin_LTek-Male_2x10_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 20 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+24
+20
+Connector_Harwin
+Harwin_LTek-Male_2x13_P2.00mm_Vertical
+Harwin LTek Connector, 26 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+26
+26
+Connector_Harwin
+Harwin_LTek-Male_2x13_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 26 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+30
+26
+Connector_Harwin
+Harwin_LTek-Male_2x17_P2.00mm_Vertical
+Harwin LTek Connector, 34 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+34
+34
+Connector_Harwin
+Harwin_LTek-Male_2x17_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 34 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+38
+34
+Connector_Harwin
+Harwin_LTek-Male_2x22_P2.00mm_Vertical
+Harwin LTek Connector, 44 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+44
+44
+Connector_Harwin
+Harwin_LTek-Male_2x22_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 44 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+48
+44
+Connector_Harwin
+Harwin_LTek-Male_03_P2.00mm_Vertical
+Harwin LTek Connector, 3 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+3
+3
+Connector_Harwin
+Harwin_LTek-Male_03_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 3 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+7
+3
+Connector_Harwin
+Harwin_LTek-Male_04_P2.00mm_Vertical
+Harwin LTek Connector, 4 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+4
+4
+Connector_Harwin
+Harwin_LTek-Male_04_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 4 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+8
+4
+Connector_Harwin
+Harwin_LTek-Male_05_P2.00mm_Vertical
+Harwin LTek Connector, 5 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+5
+5
+Connector_Harwin
+Harwin_LTek-Male_05_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 5 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+9
+5
+Connector_Harwin
+Harwin_LTek-Male_06_P2.00mm_Vertical
+Harwin LTek Connector, 6 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+6
+6
+Connector_Harwin
+Harwin_LTek-Male_06_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 6 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+10
+6
+Connector_Harwin
+Harwin_LTek-Male_07_P2.00mm_Vertical
+Harwin LTek Connector, 7 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+7
+7
+Connector_Harwin
+Harwin_LTek-Male_07_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 7 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+11
+7
+Connector_Harwin
+Harwin_LTek-Male_17_P2.00mm_Vertical
+Harwin LTek Connector, 17 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+17
+17
+Connector_Harwin
+Harwin_LTek-Male_17_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 17 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+21
+17
+Connector_Harwin
+Harwin_LTek-Male_22_P2.00mm_Vertical
+Harwin LTek Connector, 22 pins, single row male, vertical entry
+connector harwin ltek M80
+0
+22
+22
+Connector_Harwin
+Harwin_LTek-Male_22_P2.00mm_Vertical_StrainRelief
+Harwin LTek Connector, 22 pins, single row male, vertical entry, strain relief clip
+connector harwin ltek M80
+0
+26
+22
+Connector_Harwin
+Harwin_M20-89003xx_1x03_P2.54mm_Horizontal
+Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89003xx, 3 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator
+connector Harwin M20-890 horizontal
+0
+4
+3
+Connector_Harwin
+Harwin_M20-89004xx_1x04_P2.54mm_Horizontal
+Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89004xx, 4 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator
+connector Harwin M20-890 horizontal
+0
+5
+4
+Connector_Harwin
+Harwin_M20-89005xx_1x05_P2.54mm_Horizontal
+Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89005xx, 5 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator
+connector Harwin M20-890 horizontal
+0
+6
+5
+Connector_Harwin
+Harwin_M20-89006xx_1x06_P2.54mm_Horizontal
+Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89006xx, 6 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator
+connector Harwin M20-890 horizontal
+0
+7
+6
+Connector_Harwin
+Harwin_M20-89007xx_1x07_P2.54mm_Horizontal
+Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89007xx, 7 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator
+connector Harwin M20-890 horizontal
+0
+8
+7
+Connector_Harwin
+Harwin_M20-89008xx_1x08_P2.54mm_Horizontal
+Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89008xx, 8 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator
+connector Harwin M20-890 horizontal
+0
+9
+8
+Connector_Harwin
+Harwin_M20-89009xx_1x09_P2.54mm_Horizontal
+Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89009xx, 9 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator
+connector Harwin M20-890 horizontal
+0
+10
+9
+Connector_Harwin
+Harwin_M20-89010xx_1x10_P2.54mm_Horizontal
+Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89010xx, 10 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator
+connector Harwin M20-890 horizontal
+0
+11
+10
+Connector_Harwin
+Harwin_M20-89011xx_1x11_P2.54mm_Horizontal
+Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89011xx, 11 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator
+connector Harwin M20-890 horizontal
+0
+12
+11
+Connector_Harwin
+Harwin_M20-89012xx_1x12_P2.54mm_Horizontal
+Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89012xx, 12 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator
+connector Harwin M20-890 horizontal
+0
+13
+12
+Connector_Harwin
+Harwin_M20-89013xx_1x13_P2.54mm_Horizontal
+Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89013xx, 13 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator
+connector Harwin M20-890 horizontal
+0
+14
+13
+Connector_Harwin
+Harwin_M20-89014xx_1x14_P2.54mm_Horizontal
+Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89014xx, 14 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator
+connector Harwin M20-890 horizontal
+0
+15
+14
+Connector_Harwin
+Harwin_M20-89015xx_1x15_P2.54mm_Horizontal
+Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89015xx, 15 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator
+connector Harwin M20-890 horizontal
+0
+16
+15
+Connector_Harwin
+Harwin_M20-89016xx_1x16_P2.54mm_Horizontal
+Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89016xx, 16 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator
+connector Harwin M20-890 horizontal
+0
+17
+16
+Connector_Harwin
+Harwin_M20-89017xx_1x17_P2.54mm_Horizontal
+Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89017xx, 17 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator
+connector Harwin M20-890 horizontal
+0
+18
+17
+Connector_Harwin
+Harwin_M20-89018xx_1x18_P2.54mm_Horizontal
+Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89018xx, 18 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator
+connector Harwin M20-890 horizontal
+0
+19
+18
+Connector_Harwin
+Harwin_M20-89019xx_1x19_P2.54mm_Horizontal
+Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89019xx, 19 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator
+connector Harwin M20-890 horizontal
+0
+20
+19
+Connector_Harwin
+Harwin_M20-89020xx_1x20_P2.54mm_Horizontal
+Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89020xx, 20 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator
+connector Harwin M20-890 horizontal
+0
+21
+20
+Connector_Harwin
+Harwin_M20-7810245_2x02_P2.54mm_Vertical
+Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810245, 2 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator
+connector Harwin M20 side entry
+0
+4
+4
+Connector_Harwin
+Harwin_M20-7810345_2x03_P2.54mm_Vertical
+Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810345, 3 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator
+connector Harwin M20 side entry
+0
+6
+6
+Connector_Harwin
+Harwin_M20-7810445_2x04_P2.54mm_Vertical
+Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810445, 4 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator
+connector Harwin M20 side entry
+0
+8
+8
+Connector_Harwin
+Harwin_M20-7810545_2x05_P2.54mm_Vertical
+Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810545, 5 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator
+connector Harwin M20 side entry
+0
+10
+10
+Connector_Harwin
+Harwin_M20-7810645_2x06_P2.54mm_Vertical
+Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810645, 6 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator
+connector Harwin M20 side entry
+0
+12
+12
+Connector_Harwin
+Harwin_M20-7810745_2x07_P2.54mm_Vertical
+Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810745, 7 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator
+connector Harwin M20 side entry
+0
+14
+14
+Connector_Harwin
+Harwin_M20-7810845_2x08_P2.54mm_Vertical
+Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810845, 8 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator
+connector Harwin M20 side entry
+0
+16
+16
+Connector_Harwin
+Harwin_M20-7810945_2x09_P2.54mm_Vertical
+Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810945, 9 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator
+connector Harwin M20 side entry
+0
+18
+18
+Connector_Harwin
+Harwin_M20-7811045_2x10_P2.54mm_Vertical
+Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7811045, 10 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator
+connector Harwin M20 side entry
+0
+20
+20
+Connector_Harwin
+Harwin_M20-7811245_2x12_P2.54mm_Vertical
+Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7811245, 12 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator
+connector Harwin M20 side entry
+0
+24
+24
+Connector_Harwin
+Harwin_M20-7811545_2x15_P2.54mm_Vertical
+Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7811545, 15 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator
+connector Harwin M20 side entry
+0
+30
+30
+Connector_Harwin
+Harwin_M20-7812045_2x20_P2.54mm_Vertical
+Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7812045, 20 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator
+connector Harwin M20 side entry
+0
+40
+40
+Connector_Hirose
+Hirose_BM24_BM24-40DP-2-0.35V_2x20_P0.35mm_PowerPin2_Vertical
+Hirose BM24 series connector, BM24-40DP/2-0.35V (https://www.hirose.com/product/en/download_file/key_name/BM24/category/Catalog/doc_file_id/47680/?file_category_id=4&item_id=50&is_series=1)
+connector Hirose  BM24 40pin header
+0
+44
+42
+Connector_Hirose
+Hirose_BM24_BM24-40DS-2-0.35V_2x20_P0.35mm_PowerPin2_Vertical
+Hirose BM24 series connector, BM24-40DS/2-0.35V (https://www.hirose.com/product/en/download_file/key_name/BM24/category/Catalog/doc_file_id/47680/?file_category_id=4&item_id=50&is_series=1)
+connector Hirose 40pin receptacle vertical
+0
+42
+42
+Connector_Hirose
+Hirose_DF3EA-02P-2H_1x02-1MP_P2.00mm_Horizontal
+Hirose  series connector, DF3EA-02P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+4
+3
+Connector_Hirose
+Hirose_DF3EA-03P-2H_1x03-1MP_P2.00mm_Horizontal
+Hirose  series connector, DF3EA-03P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+5
+4
+Connector_Hirose
+Hirose_DF3EA-04P-2H_1x04-1MP_P2.00mm_Horizontal
+Hirose  series connector, DF3EA-04P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+6
+5
+Connector_Hirose
+Hirose_DF3EA-05P-2H_1x05-1MP_P2.00mm_Horizontal
+Hirose  series connector, DF3EA-05P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+7
+6
+Connector_Hirose
+Hirose_DF3EA-06P-2H_1x06-1MP_P2.00mm_Horizontal
+Hirose  series connector, DF3EA-06P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+8
+7
+Connector_Hirose
+Hirose_DF3EA-07P-2H_1x07-1MP_P2.00mm_Horizontal
+Hirose  series connector, DF3EA-07P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+9
+8
+Connector_Hirose
+Hirose_DF3EA-08P-2H_1x08-1MP_P2.00mm_Horizontal
+Hirose  series connector, DF3EA-08P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+10
+9
+Connector_Hirose
+Hirose_DF3EA-09P-2H_1x09-1MP_P2.00mm_Horizontal
+Hirose  series connector, DF3EA-09P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+11
+10
+Connector_Hirose
+Hirose_DF3EA-10P-2H_1x10-1MP_P2.00mm_Horizontal
+Hirose  series connector, DF3EA-10P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+12
+11
+Connector_Hirose
+Hirose_DF3EA-11P-2H_1x11-1MP_P2.00mm_Horizontal
+Hirose  series connector, DF3EA-11P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+13
+12
+Connector_Hirose
+Hirose_DF3EA-12P-2H_1x12-1MP_P2.00mm_Horizontal
+Hirose  series connector, DF3EA-12P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+14
+13
+Connector_Hirose
+Hirose_DF3EA-13P-2H_1x13-1MP_P2.00mm_Horizontal
+Hirose  series connector, DF3EA-13P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+15
+14
+Connector_Hirose
+Hirose_DF3EA-14P-2H_1x14-1MP_P2.00mm_Horizontal
+Hirose  series connector, DF3EA-14P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+16
+15
+Connector_Hirose
+Hirose_DF3EA-15P-2H_1x15-1MP_P2.00mm_Horizontal
+Hirose  series connector, DF3EA-15P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+17
+16
+Connector_Hirose
+Hirose_DF11-4DP-2DSA_2x02_P2.00mm_Vertical
+Hirose DF11 through hole, DF11-4DP-2DSA, 2 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator
+connector Hirose DF11 vertical
+0
+4
+4
+Connector_Hirose
+Hirose_DF11-6DP-2DSA_2x03_P2.00mm_Vertical
+Hirose DF11 through hole, DF11-6DP-2DSA, 3 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator
+connector Hirose DF11 vertical
+0
+6
+6
+Connector_Hirose
+Hirose_DF11-8DP-2DSA_2x04_P2.00mm_Vertical
+Hirose DF11 through hole, DF11-8DP-2DSA, 4 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator
+connector Hirose DF11 vertical
+0
+8
+8
+Connector_Hirose
+Hirose_DF11-10DP-2DSA_2x05_P2.00mm_Vertical
+Hirose DF11 through hole, DF11-10DP-2DSA, 5 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator
+connector Hirose DF11 vertical
+0
+10
+10
+Connector_Hirose
+Hirose_DF11-12DP-2DSA_2x06_P2.00mm_Vertical
+Hirose DF11 through hole, DF11-12DP-2DSA, 6 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator
+connector Hirose DF11 vertical
+0
+12
+12
+Connector_Hirose
+Hirose_DF11-14DP-2DSA_2x07_P2.00mm_Vertical
+Hirose DF11 through hole, DF11-14DP-2DSA, 7 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator
+connector Hirose DF11 vertical
+0
+14
+14
+Connector_Hirose
+Hirose_DF11-16DP-2DSA_2x08_P2.00mm_Vertical
+Hirose DF11 through hole, DF11-16DP-2DSA, 8 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator
+connector Hirose DF11 vertical
+0
+16
+16
+Connector_Hirose
+Hirose_DF11-18DP-2DSA_2x09_P2.00mm_Vertical
+Hirose DF11 through hole, DF11-18DP-2DSA, 9 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator
+connector Hirose DF11 vertical
+0
+18
+18
+Connector_Hirose
+Hirose_DF11-20DP-2DSA_2x10_P2.00mm_Vertical
+Hirose DF11 through hole, DF11-20DP-2DSA, 10 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator
+connector Hirose DF11 vertical
+0
+20
+20
+Connector_Hirose
+Hirose_DF11-22DP-2DSA_2x11_P2.00mm_Vertical
+Hirose DF11 through hole, DF11-22DP-2DSA, 11 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator
+connector Hirose DF11 vertical
+0
+22
+22
+Connector_Hirose
+Hirose_DF11-24DP-2DSA_2x12_P2.00mm_Vertical
+Hirose DF11 through hole, DF11-24DP-2DSA, 12 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator
+connector Hirose DF11 vertical
+0
+24
+24
+Connector_Hirose
+Hirose_DF11-26DP-2DSA_2x13_P2.00mm_Vertical
+Hirose DF11 through hole, DF11-26DP-2DSA, 13 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator
+connector Hirose DF11 vertical
+0
+26
+26
+Connector_Hirose
+Hirose_DF11-28DP-2DSA_2x14_P2.00mm_Vertical
+Hirose DF11 through hole, DF11-28DP-2DSA, 14 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator
+connector Hirose DF11 vertical
+0
+28
+28
+Connector_Hirose
+Hirose_DF11-30DP-2DSA_2x15_P2.00mm_Vertical
+Hirose DF11 through hole, DF11-30DP-2DSA, 15 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator
+connector Hirose DF11 vertical
+0
+30
+30
+Connector_Hirose
+Hirose_DF11-32DP-2DSA_2x16_P2.00mm_Vertical
+Hirose DF11 through hole, DF11-32DP-2DSA, 16 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator
+connector Hirose DF11 vertical
+0
+32
+32
+Connector_Hirose
+Hirose_DF12_DF12C3.0-10DS-0.5V_2x05_P0.50mm_Vertical
+Hirose DF12C SMD, DF12C3.0-10DS-0.5V, 10 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+20
+10
+Connector_Hirose
+Hirose_DF12_DF12C3.0-14DS-0.5V_2x07_P0.50mm_Vertical
+Hirose DF12C SMD, DF12C3.0-14DS-0.5V, 14 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+28
+14
+Connector_Hirose
+Hirose_DF12_DF12C3.0-20DS-0.5V_2x10_P0.50mm_Vertical
+Hirose DF12C SMD, DF12C3.0-20DS-0.5V, 20 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+40
+20
+Connector_Hirose
+Hirose_DF12_DF12C3.0-30DS-0.5V_2x15_P0.50mm_Vertical
+Hirose DF12C SMD, DF12C3.0-30DS-0.5V, 30 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+60
+30
+Connector_Hirose
+Hirose_DF12_DF12C3.0-32DS-0.5V_2x16_P0.50mm_Vertical
+Hirose DF12C SMD, DF12C3.0-32DS-0.5V, 32 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+64
+32
+Connector_Hirose
+Hirose_DF12_DF12C3.0-36DS-0.5V_2x18_P0.50mm_Vertical
+Hirose DF12C SMD, DF12C3.0-36DS-0.5V, 36 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+72
+36
+Connector_Hirose
+Hirose_DF12_DF12C3.0-40DS-0.5V_2x20_P0.50mm_Vertical
+Hirose DF12C SMD, DF12C3.0-40DS-0.5V, 40 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+80
+40
+Connector_Hirose
+Hirose_DF12_DF12C3.0-50DS-0.5V_2x25_P0.50mm_Vertical
+Hirose DF12C SMD, DF12C3.0-50DS-0.5V, 50 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+100
+50
+Connector_Hirose
+Hirose_DF12_DF12C3.0-60DS-0.5V_2x30_P0.50mm_Vertical
+Hirose DF12C SMD, DF12C3.0-60DS-0.5V, 60 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+120
+60
+Connector_Hirose
+Hirose_DF12_DF12E3.0-10DP-0.5V_2x05_P0.50mm_Vertical
+Hirose DF12E SMD, DF12E3.0-10DP-0.5V, 10 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+20
+10
+Connector_Hirose
+Hirose_DF12_DF12E3.0-14DP-0.5V_2x07_P0.50mm_Vertical
+Hirose DF12E SMD, DF12E3.0-14DP-0.5V, 14 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+28
+14
+Connector_Hirose
+Hirose_DF12_DF12E3.0-20DP-0.5V_2x10_P0.50mm_Vertical
+Hirose DF12E SMD, DF12E3.0-20DP-0.5V, 20 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+40
+20
+Connector_Hirose
+Hirose_DF12_DF12E3.0-30DP-0.5V_2x15_P0.50mm_Vertical
+Hirose DF12E SMD, DF12E3.0-30DP-0.5V, 30 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+60
+30
+Connector_Hirose
+Hirose_DF12_DF12E3.0-32DP-0.5V_2x16_P0.50mm_Vertical
+Hirose DF12E SMD, DF12E3.0-32DP-0.5V, 32 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+64
+32
+Connector_Hirose
+Hirose_DF12_DF12E3.0-36DP-0.5V_2x18_P0.50mm_Vertical
+Hirose DF12E SMD, DF12E3.0-36DP-0.5V, 36 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+72
+36
+Connector_Hirose
+Hirose_DF12_DF12E3.0-40DP-0.5V_2x20_P0.50mm_Vertical
+Hirose DF12E SMD, DF12E3.0-40DP-0.5V, 40 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+80
+40
+Connector_Hirose
+Hirose_DF12_DF12E3.0-50DP-0.5V_2x25_P0.50mm_Vertical
+Hirose DF12E SMD, DF12E3.0-50DP-0.5V, 50 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+100
+50
+Connector_Hirose
+Hirose_DF12_DF12E3.0-60DP-0.5V_2x30_P0.50mm_Vertical
+Hirose DF12E SMD, DF12E3.0-60DP-0.5V, 60 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+120
+60
+Connector_Hirose
+Hirose_DF12_DF12E3.0-80DP-0.5V_2x40_P0.50mm_Vertical
+Hirose DF12E SMD, DF12E3.0-80DP-0.5V, 80 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator
+connector Hirose DF12 vertical
+0
+160
+80
+Connector_Hirose
+Hirose_DF13-02P-1.25DSA_1x02_P1.25mm_Vertical
+Hirose DF13 through hole, DF13-02P-1.25DSA, 2 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator
+connector Hirose DF13 vertical
+0
+2
+2
+Connector_Hirose
+Hirose_DF13-02P-1.25DS_1x02_P1.25mm_Horizontal
+Hirose DF13 through hole, DF13-02P-1.25DS, 2 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator
+connector Hirose DF13 horizontal
+0
+2
+2
+Connector_Hirose
+Hirose_DF13-03P-1.25DSA_1x03_P1.25mm_Vertical
+Hirose DF13 through hole, DF13-03P-1.25DSA, 3 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator
+connector Hirose DF13 vertical
+0
+3
+3
+Connector_Hirose
+Hirose_DF13-03P-1.25DS_1x03_P1.25mm_Horizontal
+Hirose DF13 through hole, DF13-03P-1.25DS, 3 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator
+connector Hirose DF13 horizontal
+0
+3
+3
+Connector_Hirose
+Hirose_DF13-04P-1.25DSA_1x04_P1.25mm_Vertical
+Hirose DF13 through hole, DF13-04P-1.25DSA, 4 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator
+connector Hirose DF13 vertical
+0
+4
+4
+Connector_Hirose
+Hirose_DF13-04P-1.25DS_1x04_P1.25mm_Horizontal
+Hirose DF13 through hole, DF13-04P-1.25DS, 4 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator
+connector Hirose DF13 horizontal
+0
+4
+4
+Connector_Hirose
+Hirose_DF13-05P-1.25DSA_1x05_P1.25mm_Vertical
+Hirose DF13 through hole, DF13-05P-1.25DSA, 5 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator
+connector Hirose DF13 vertical
+0
+5
+5
+Connector_Hirose
+Hirose_DF13-05P-1.25DS_1x05_P1.25mm_Horizontal
+Hirose DF13 through hole, DF13-05P-1.25DS, 5 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator
+connector Hirose DF13 horizontal
+0
+5
+5
+Connector_Hirose
+Hirose_DF13-06P-1.25DSA_1x06_P1.25mm_Vertical
+Hirose DF13 through hole, DF13-06P-1.25DSA, 6 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator
+connector Hirose DF13 vertical
+0
+6
+6
+Connector_Hirose
+Hirose_DF13-06P-1.25DS_1x06_P1.25mm_Horizontal
+Hirose DF13 through hole, DF13-06P-1.25DS, 6 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator
+connector Hirose DF13 horizontal
+0
+6
+6
+Connector_Hirose
+Hirose_DF13-07P-1.25DSA_1x07_P1.25mm_Vertical
+Hirose DF13 through hole, DF13-07P-1.25DSA, 7 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator
+connector Hirose DF13 vertical
+0
+7
+7
+Connector_Hirose
+Hirose_DF13-07P-1.25DS_1x07_P1.25mm_Horizontal
+Hirose DF13 through hole, DF13-07P-1.25DS, 7 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator
+connector Hirose DF13 horizontal
+0
+7
+7
+Connector_Hirose
+Hirose_DF13-08P-1.25DSA_1x08_P1.25mm_Vertical
+Hirose DF13 through hole, DF13-08P-1.25DSA, 8 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator
+connector Hirose DF13 vertical
+0
+8
+8
+Connector_Hirose
+Hirose_DF13-08P-1.25DS_1x08_P1.25mm_Horizontal
+Hirose DF13 through hole, DF13-08P-1.25DS, 8 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator
+connector Hirose DF13 horizontal
+0
+8
+8
+Connector_Hirose
+Hirose_DF13-09P-1.25DSA_1x09_P1.25mm_Vertical
+Hirose DF13 through hole, DF13-09P-1.25DSA, 9 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator
+connector Hirose DF13 vertical
+0
+9
+9
+Connector_Hirose
+Hirose_DF13-09P-1.25DS_1x09_P1.25mm_Horizontal
+Hirose DF13 through hole, DF13-09P-1.25DS, 9 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator
+connector Hirose DF13 horizontal
+0
+9
+9
+Connector_Hirose
+Hirose_DF13-10P-1.25DSA_1x10_P1.25mm_Vertical
+Hirose DF13 through hole, DF13-10P-1.25DSA, 10 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator
+connector Hirose DF13 vertical
+0
+10
+10
+Connector_Hirose
+Hirose_DF13-10P-1.25DS_1x10_P1.25mm_Horizontal
+Hirose DF13 through hole, DF13-10P-1.25DS, 10 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator
+connector Hirose DF13 horizontal
+0
+10
+10
+Connector_Hirose
+Hirose_DF13-11P-1.25DSA_1x11_P1.25mm_Vertical
+Hirose DF13 through hole, DF13-11P-1.25DSA, 11 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator
+connector Hirose DF13 vertical
+0
+11
+11
+Connector_Hirose
+Hirose_DF13-11P-1.25DS_1x11_P1.25mm_Horizontal
+Hirose DF13 through hole, DF13-11P-1.25DS, 11 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator
+connector Hirose DF13 horizontal
+0
+11
+11
+Connector_Hirose
+Hirose_DF13-12P-1.25DSA_1x12_P1.25mm_Vertical
+Hirose DF13 through hole, DF13-12P-1.25DSA, 12 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator
+connector Hirose DF13 vertical
+0
+12
+12
+Connector_Hirose
+Hirose_DF13-12P-1.25DS_1x12_P1.25mm_Horizontal
+Hirose DF13 through hole, DF13-12P-1.25DS, 12 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator
+connector Hirose DF13 horizontal
+0
+12
+12
+Connector_Hirose
+Hirose_DF13-13P-1.25DSA_1x13_P1.25mm_Vertical
+Hirose DF13 through hole, DF13-13P-1.25DSA, 13 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator
+connector Hirose DF13 vertical
+0
+13
+13
+Connector_Hirose
+Hirose_DF13-14P-1.25DSA_1x14_P1.25mm_Vertical
+Hirose DF13 through hole, DF13-14P-1.25DSA, 14 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator
+connector Hirose DF13 vertical
+0
+14
+14
+Connector_Hirose
+Hirose_DF13-14P-1.25DS_1x14_P1.25mm_Horizontal
+Hirose DF13 through hole, DF13-14P-1.25DS, 14 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator
+connector Hirose DF13 horizontal
+0
+14
+14
+Connector_Hirose
+Hirose_DF13-15P-1.25DSA_1x15_P1.25mm_Vertical
+Hirose DF13 through hole, DF13-15P-1.25DSA, 15 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator
+connector Hirose DF13 vertical
+0
+15
+15
+Connector_Hirose
+Hirose_DF13-15P-1.25DS_1x15_P1.25mm_Horizontal
+Hirose DF13 through hole, DF13-15P-1.25DS, 15 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator
+connector Hirose DF13 horizontal
+0
+15
+15
+Connector_Hirose
+Hirose_DF13C_CL535-0402-2-51_1x02-1MP_P1.25mm_Vertical
+Hirose DF13C SMD, CL535-0402-2-51, 2 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator
+connector Hirose DF13C vertical
+0
+4
+3
+Connector_Hirose
+Hirose_DF13C_CL535-0403-5-51_1x03-1MP_P1.25mm_Vertical
+Hirose DF13C SMD, CL535-0403-5-51, 3 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator
+connector Hirose DF13C vertical
+0
+5
+4
+Connector_Hirose
+Hirose_DF13C_CL535-0404-8-51_1x04-1MP_P1.25mm_Vertical
+Hirose DF13C SMD, CL535-0404-8-51, 4 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator
+connector Hirose DF13C vertical
+0
+6
+5
+Connector_Hirose
+Hirose_DF13C_CL535-0405-0-51_1x05-1MP_P1.25mm_Vertical
+Hirose DF13C SMD, CL535-0405-0-51, 5 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator
+connector Hirose DF13C vertical
+0
+7
+6
+Connector_Hirose
+Hirose_DF13C_CL535-0406-3-51_1x06-1MP_P1.25mm_Vertical
+Hirose DF13C SMD, CL535-0406-3-51, 6 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator
+connector Hirose DF13C vertical
+0
+8
+7
+Connector_Hirose
+Hirose_DF13C_CL535-0407-6-51_1x07-1MP_P1.25mm_Vertical
+Hirose DF13C SMD, CL535-0407-6-51, 7 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator
+connector Hirose DF13C vertical
+0
+9
+8
+Connector_Hirose
+Hirose_DF13C_CL535-0408-9-51_1x08-1MP_P1.25mm_Vertical
+Hirose DF13C SMD, CL535-0408-9-51, 8 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator
+connector Hirose DF13C vertical
+0
+10
+9
+Connector_Hirose
+Hirose_DF13C_CL535-0409-1-51_1x09-1MP_P1.25mm_Vertical
+Hirose DF13C SMD, CL535-0409-1-51, 9 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator
+connector Hirose DF13C vertical
+0
+11
+10
+Connector_Hirose
+Hirose_DF13C_CL535-0410-4-51_1x10-1MP_P1.25mm_Vertical
+Hirose DF13C SMD, CL535-0410-4-51, 10 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator
+connector Hirose DF13C vertical
+0
+12
+11
+Connector_Hirose
+Hirose_DF13C_CL535-0411-3-51_1x11-1MP_P1.25mm_Vertical
+Hirose DF13C SMD, CL535-0411-3-51, 11 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator
+connector Hirose DF13C vertical
+0
+13
+12
+Connector_Hirose
+Hirose_DF13C_CL535-0412-6-51_1x12-1MP_P1.25mm_Vertical
+Hirose DF13C SMD, CL535-0412-6-51, 12 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator
+connector Hirose DF13C vertical
+0
+14
+13
+Connector_Hirose
+Hirose_DF13C_CL535-0414-1-51_1x14-1MP_P1.25mm_Vertical
+Hirose DF13C SMD, CL535-0414-1-51, 14 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator
+connector Hirose DF13C vertical
+0
+16
+15
+Connector_Hirose
+Hirose_DF13C_CL535-0415-4-51_1x15-1MP_P1.25mm_Vertical
+Hirose DF13C SMD, CL535-0415-4-51, 15 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator
+connector Hirose DF13C vertical
+0
+17
+16
+Connector_Hirose
+Hirose_DF52-2S-0.8H_1x02-1MP_P0.80mm_Horizontal
+Hirose  series connector, DF52-2S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+4
+3
+Connector_Hirose
+Hirose_DF52-3S-0.8H_1x03-1MP_P0.80mm_Horizontal
+Hirose  series connector, DF52-3S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+5
+4
+Connector_Hirose
+Hirose_DF52-4S-0.8H_1x04-1MP_P0.80mm_Horizontal
+Hirose  series connector, DF52-4S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+6
+5
+Connector_Hirose
+Hirose_DF52-5S-0.8H_1x05-1MP_P0.80mm_Horizontal
+Hirose  series connector, DF52-5S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+7
+6
+Connector_Hirose
+Hirose_DF52-6S-0.8H_1x06-1MP_P0.80mm_Horizontal
+Hirose  series connector, DF52-6S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+8
+7
+Connector_Hirose
+Hirose_DF52-7S-0.8H_1x07-1MP_P0.80mm_Horizontal
+Hirose  series connector, DF52-7S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+9
+8
+Connector_Hirose
+Hirose_DF52-8S-0.8H_1x08-1MP_P0.80mm_Horizontal
+Hirose  series connector, DF52-8S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+10
+9
+Connector_Hirose
+Hirose_DF52-9S-0.8H_1x09-1MP_P0.80mm_Horizontal
+Hirose  series connector, DF52-9S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+11
+10
+Connector_Hirose
+Hirose_DF52-10S-0.8H_1x10-1MP_P0.80mm_Horizontal
+Hirose  series connector, DF52-10S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+12
+11
+Connector_Hirose
+Hirose_DF52-11S-0.8H_1x11-1MP_P0.80mm_Horizontal
+Hirose  series connector, DF52-11S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+13
+12
+Connector_Hirose
+Hirose_DF52-12S-0.8H_1x12-1MP_P0.80mm_Horizontal
+Hirose  series connector, DF52-12S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+14
+13
+Connector_Hirose
+Hirose_DF52-14S-0.8H_1x14-1MP_P0.80mm_Horizontal
+Hirose  series connector, DF52-14S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+16
+15
+Connector_Hirose
+Hirose_DF52-15S-0.8H_1x15-1MP_P0.80mm_Horizontal
+Hirose  series connector, DF52-15S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator
+connector Hirose  top entry
+0
+17
+16
+Connector_Hirose
+Hirose_DF63-5P-3.96DSA_1x05_P3.96mm_Vertical
+Hirose DF63 through hole, DF63-5P-3.96DSA, 5 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator
+connector Hirose DF63 vertical
+0
+5
+5
+Connector_Hirose
+Hirose_DF63-6P-3.96DSA_1x06_P3.96mm_Vertical
+Hirose DF63 through hole, DF63-6P-3.96DSA, 6 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator
+connector Hirose DF63 vertical
+0
+6
+6
+Connector_Hirose
+Hirose_DF63M-1P-3.96DSA_1x01_P3.96mm_Vertical
+Hirose DF63 through hole, DF63M-1P-3.96DSA, 1 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator
+connector Hirose DF63 vertical
+0
+1
+1
+Connector_Hirose
+Hirose_DF63M-2P-3.96DSA_1x02_P3.96mm_Vertical
+Hirose DF63 through hole, DF63M-2P-3.96DSA, 2 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator
+connector Hirose DF63 vertical
+0
+2
+2
+Connector_Hirose
+Hirose_DF63M-3P-3.96DSA_1x03_P3.96mm_Vertical
+Hirose DF63 through hole, DF63M-3P-3.96DSA, 3 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator
+connector Hirose DF63 vertical
+0
+3
+3
+Connector_Hirose
+Hirose_DF63M-4P-3.96DSA_1x04_P3.96mm_Vertical
+Hirose DF63 through hole, DF63M-4P-3.96DSA, 4 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator
+connector Hirose DF63 vertical
+0
+4
+4
+Connector_Hirose
+Hirose_DF63R-1P-3.96DSA_1x01_P3.96mm_Vertical
+Hirose DF63 through hole, DF63R-1P-3.96DSA, 1 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator
+connector Hirose DF63 vertical
+0
+1
+1
+Connector_Hirose
+Hirose_DF63R-2P-3.96DSA_1x02_P3.96mm_Vertical
+Hirose DF63 through hole, DF63R-2P-3.96DSA, 2 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator
+connector Hirose DF63 vertical
+0
+2
+2
+Connector_Hirose
+Hirose_DF63R-3P-3.96DSA_1x03_P3.96mm_Vertical
+Hirose DF63 through hole, DF63R-3P-3.96DSA, 3 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator
+connector Hirose DF63 vertical
+0
+3
+3
+Connector_Hirose
+Hirose_DF63R-4P-3.96DSA_1x04_P3.96mm_Vertical
+Hirose DF63 through hole, DF63R-4P-3.96DSA, 4 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator
+connector Hirose DF63 vertical
+0
+4
+4
+Connector_Hirose
+Hirose_DF63R-5P-3.96DSA_1x05_P3.96mm_Vertical
+Hirose DF63 through hole, DF63R-5P-3.96DSA, 5 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator
+connector Hirose DF63 vertical
+0
+5
+5
+Connector_IDC
+IDC-Header_2x03_P2.54mm_Horizontal
+Through hole angled IDC box header, 2x03, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x03 2.54mm double row
+0
+6
+6
+Connector_IDC
+IDC-Header_2x03_P2.54mm_Vertical
+Through hole straight IDC box header, 2x03, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x03 2.54mm double row
+0
+6
+6
+Connector_IDC
+IDC-Header_2x04_P2.54mm_Horizontal
+Through hole angled IDC box header, 2x04, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x04 2.54mm double row
+0
+8
+8
+Connector_IDC
+IDC-Header_2x04_P2.54mm_Vertical
+Through hole straight IDC box header, 2x04, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x04 2.54mm double row
+0
+8
+8
+Connector_IDC
+IDC-Header_2x05_P2.54mm_Horizontal
+Through hole angled IDC box header, 2x05, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x05 2.54mm double row
+0
+10
+10
+Connector_IDC
+IDC-Header_2x05_P2.54mm_Horizontal_Lock
+Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf)
+connector idc locked
+0
+12
+10
+Connector_IDC
+IDC-Header_2x05_P2.54mm_Vertical
+Through hole straight IDC box header, 2x05, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x05 2.54mm double row
+0
+10
+10
+Connector_IDC
+IDC-Header_2x05_P2.54mm_Vertical_Lock
+Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf)
+connector idc locked
+0
+12
+10
+Connector_IDC
+IDC-Header_2x06_P2.54mm_Horizontal
+Through hole angled IDC box header, 2x06, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x06 2.54mm double row
+0
+12
+12
+Connector_IDC
+IDC-Header_2x06_P2.54mm_Vertical
+Through hole straight IDC box header, 2x06, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x06 2.54mm double row
+0
+12
+12
+Connector_IDC
+IDC-Header_2x07_P2.54mm_Horizontal
+Through hole angled IDC box header, 2x07, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x07 2.54mm double row
+0
+14
+14
+Connector_IDC
+IDC-Header_2x07_P2.54mm_Horizontal_Lock
+Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf)
+connector idc locked
+0
+16
+14
+Connector_IDC
+IDC-Header_2x07_P2.54mm_Vertical
+Through hole straight IDC box header, 2x07, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x07 2.54mm double row
+0
+14
+14
+Connector_IDC
+IDC-Header_2x07_P2.54mm_Vertical_Lock
+Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf)
+connector idc locked
+0
+16
+14
+Connector_IDC
+IDC-Header_2x08_P2.54mm_Horizontal
+Through hole angled IDC box header, 2x08, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x08 2.54mm double row
+0
+16
+16
+Connector_IDC
+IDC-Header_2x08_P2.54mm_Horizontal_Lock
+Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf)
+connector idc locked
+0
+18
+16
+Connector_IDC
+IDC-Header_2x08_P2.54mm_Vertical
+Through hole straight IDC box header, 2x08, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x08 2.54mm double row
+0
+16
+16
+Connector_IDC
+IDC-Header_2x08_P2.54mm_Vertical_Lock
+Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf)
+connector idc locked
+0
+18
+16
+Connector_IDC
+IDC-Header_2x10_P2.54mm_Horizontal
+Through hole angled IDC box header, 2x10, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x10 2.54mm double row
+0
+20
+20
+Connector_IDC
+IDC-Header_2x10_P2.54mm_Horizontal_Lock
+Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf)
+connector idc locked
+0
+22
+20
+Connector_IDC
+IDC-Header_2x10_P2.54mm_Vertical
+Through hole straight IDC box header, 2x10, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x10 2.54mm double row
+0
+20
+20
+Connector_IDC
+IDC-Header_2x10_P2.54mm_Vertical_Lock
+Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf)
+connector idc locked
+0
+22
+20
+Connector_IDC
+IDC-Header_2x13_P2.54mm_Horizontal
+Through hole angled IDC box header, 2x13, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x13 2.54mm double row
+0
+26
+26
+Connector_IDC
+IDC-Header_2x13_P2.54mm_Horizontal_Lock
+Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf)
+connector idc locked
+0
+28
+26
+Connector_IDC
+IDC-Header_2x13_P2.54mm_Vertical
+Through hole straight IDC box header, 2x13, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x13 2.54mm double row
+0
+26
+26
+Connector_IDC
+IDC-Header_2x13_P2.54mm_Vertical_Lock
+Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf)
+connector idc locked
+0
+28
+26
+Connector_IDC
+IDC-Header_2x15_P2.54mm_Horizontal
+Through hole angled IDC box header, 2x15, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x15 2.54mm double row
+0
+30
+30
+Connector_IDC
+IDC-Header_2x15_P2.54mm_Vertical
+Through hole straight IDC box header, 2x15, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x15 2.54mm double row
+0
+30
+30
+Connector_IDC
+IDC-Header_2x17_P2.54mm_Horizontal
+Through hole angled IDC box header, 2x17, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x17 2.54mm double row
+0
+34
+34
+Connector_IDC
+IDC-Header_2x17_P2.54mm_Horizontal_Lock
+Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf)
+connector idc locked
+0
+36
+34
+Connector_IDC
+IDC-Header_2x17_P2.54mm_Vertical
+Through hole straight IDC box header, 2x17, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x17 2.54mm double row
+0
+34
+34
+Connector_IDC
+IDC-Header_2x17_P2.54mm_Vertical_Lock
+Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf)
+connector idc locked
+0
+36
+34
+Connector_IDC
+IDC-Header_2x20_P2.54mm_Horizontal
+Through hole angled IDC box header, 2x20, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x20 2.54mm double row
+0
+40
+40
+Connector_IDC
+IDC-Header_2x20_P2.54mm_Horizontal_Lock
+Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf)
+connector idc locked
+0
+42
+41
+Connector_IDC
+IDC-Header_2x20_P2.54mm_Vertical
+Through hole straight IDC box header, 2x20, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x20 2.54mm double row
+0
+40
+40
+Connector_IDC
+IDC-Header_2x20_P2.54mm_Vertical_Lock
+Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf)
+connector idc locked
+0
+42
+40
+Connector_IDC
+IDC-Header_2x25_P2.54mm_Horizontal
+Through hole angled IDC box header, 2x25, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x25 2.54mm double row
+0
+50
+50
+Connector_IDC
+IDC-Header_2x25_P2.54mm_Vertical
+Through hole straight IDC box header, 2x25, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x25 2.54mm double row
+0
+50
+50
+Connector_IDC
+IDC-Header_2x25_P2.54mm_Vertical_Lock
+Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf)
+connector idc locked
+0
+52
+50
+Connector_IDC
+IDC-Header_2x30_P2.54mm_Horizontal
+Through hole angled IDC box header, 2x30, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x30 2.54mm double row
+0
+60
+60
+Connector_IDC
+IDC-Header_2x30_P2.54mm_Vertical
+Through hole straight IDC box header, 2x30, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x30 2.54mm double row
+0
+60
+60
+Connector_IDC
+IDC-Header_2x30_P2.54mm_Vertical_Lock
+Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf)
+connector idc locked
+0
+62
+60
+Connector_IDC
+IDC-Header_2x32_P2.54mm_Horizontal
+Through hole angled IDC box header, 2x32, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x32 2.54mm double row
+0
+64
+64
+Connector_IDC
+IDC-Header_2x32_P2.54mm_Vertical
+Through hole straight IDC box header, 2x32, 2.54mm pitch, double rows
+Through hole IDC box header THT 2x32 2.54mm double row
+0
+64
+64
+Connector_IDC
+IDC-Header_2x32_P2.54mm_Vertical_Lock
+Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf)
+connector idc locked
+0
+66
+64
+Connector_JAE
+JAE_LY20-4P-DLT1_2x02_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-4P-DLT1, 2 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+4
+4
+Connector_JAE
+JAE_LY20-4P-DT1_2x02_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-4P-DT1, 2 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+4
+4
+Connector_JAE
+JAE_LY20-6P-DLT1_2x03_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-6P-DLT1, 3 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+6
+6
+Connector_JAE
+JAE_LY20-6P-DT1_2x03_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-6P-DT1, 3 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+6
+6
+Connector_JAE
+JAE_LY20-8P-DLT1_2x04_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-8P-DLT1, 4 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+8
+8
+Connector_JAE
+JAE_LY20-8P-DT1_2x04_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-8P-DT1, 4 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+8
+8
+Connector_JAE
+JAE_LY20-10P-DLT1_2x05_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-10P-DLT1, 5 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+10
+10
+Connector_JAE
+JAE_LY20-10P-DT1_2x05_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-10P-DT1, 5 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+10
+10
+Connector_JAE
+JAE_LY20-12P-DLT1_2x06_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-12P-DLT1, 6 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+12
+12
+Connector_JAE
+JAE_LY20-12P-DT1_2x06_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-12P-DT1, 6 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+12
+12
+Connector_JAE
+JAE_LY20-14P-DLT1_2x07_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-14P-DLT1, 7 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+14
+14
+Connector_JAE
+JAE_LY20-14P-DT1_2x07_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-14P-DT1, 7 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+14
+14
+Connector_JAE
+JAE_LY20-16P-DLT1_2x08_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-16P-DLT1, 8 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+16
+16
+Connector_JAE
+JAE_LY20-16P-DT1_2x08_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-16P-DT1, 8 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+16
+16
+Connector_JAE
+JAE_LY20-18P-DLT1_2x09_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-18P-DLT1, 9 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+18
+18
+Connector_JAE
+JAE_LY20-18P-DT1_2x09_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-18P-DT1, 9 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+18
+18
+Connector_JAE
+JAE_LY20-20P-DLT1_2x10_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-20P-DLT1, 10 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+20
+20
+Connector_JAE
+JAE_LY20-20P-DT1_2x10_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-20P-DT1, 10 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+20
+20
+Connector_JAE
+JAE_LY20-22P-DLT1_2x11_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-22P-DLT1, 11 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+22
+22
+Connector_JAE
+JAE_LY20-22P-DT1_2x11_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-22P-DT1, 11 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+22
+22
+Connector_JAE
+JAE_LY20-24P-DLT1_2x12_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-24P-DLT1, 12 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+24
+24
+Connector_JAE
+JAE_LY20-24P-DT1_2x12_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-24P-DT1, 12 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+24
+24
+Connector_JAE
+JAE_LY20-26P-DLT1_2x13_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-26P-DLT1, 13 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+26
+26
+Connector_JAE
+JAE_LY20-26P-DT1_2x13_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-26P-DT1, 13 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+26
+26
+Connector_JAE
+JAE_LY20-28P-DLT1_2x14_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-28P-DLT1, 14 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+28
+28
+Connector_JAE
+JAE_LY20-28P-DT1_2x14_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-28P-DT1, 14 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+28
+28
+Connector_JAE
+JAE_LY20-30P-DLT1_2x15_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-30P-DLT1, 15 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+30
+30
+Connector_JAE
+JAE_LY20-30P-DT1_2x15_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-30P-DT1, 15 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+30
+30
+Connector_JAE
+JAE_LY20-32P-DLT1_2x16_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-32P-DLT1, 16 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+32
+32
+Connector_JAE
+JAE_LY20-32P-DT1_2x16_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-32P-DT1, 16 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+32
+32
+Connector_JAE
+JAE_LY20-34P-DLT1_2x17_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-34P-DLT1, 17 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+34
+34
+Connector_JAE
+JAE_LY20-34P-DT1_2x17_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-34P-DT1, 17 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+34
+34
+Connector_JAE
+JAE_LY20-36P-DLT1_2x18_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-36P-DLT1, 18 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+36
+36
+Connector_JAE
+JAE_LY20-36P-DT1_2x18_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-36P-DT1, 18 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+36
+36
+Connector_JAE
+JAE_LY20-38P-DLT1_2x19_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-38P-DLT1, 19 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+38
+38
+Connector_JAE
+JAE_LY20-38P-DT1_2x19_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-38P-DT1, 19 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+38
+38
+Connector_JAE
+JAE_LY20-40P-DLT1_2x20_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-40P-DLT1, 20 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+40
+40
+Connector_JAE
+JAE_LY20-40P-DT1_2x20_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-40P-DT1, 20 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+40
+40
+Connector_JAE
+JAE_LY20-42P-DLT1_2x21_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-42P-DLT1, 21 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+42
+42
+Connector_JAE
+JAE_LY20-42P-DT1_2x21_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-42P-DT1, 21 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+42
+42
+Connector_JAE
+JAE_LY20-44P-DLT1_2x22_P2.00mm_Horizontal
+Molex LY 20 series connector, LY20-44P-DLT1, 22 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator
+connector JAE  top entry
+0
+44
+44
+Connector_JAE
+JAE_LY20-44P-DT1_2x22_P2.00mm_Vertical
+Molex LY 20 series connector, LY20-44P-DT1, 22 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator
+connector JAE  side entry
+0
+44
+44
+Connector_JAE
+JAE_MM70-314-310B1
+http://www.heilind.com/marketing/documents/jae/JAE_MM70.pdf
+connector JAE MXM
+0
+280
+279
+Connector_JST
+JST_ACH_BM01B-ACHSS-A-GAN-ETF_1x01-1MP_P1.20mm_Vertical
+JST ACH series connector, BM01B-ACHSS-A-GAN-ETF (http://www.jst-mfg.com/product/pdf/eng/eACH.pdf), generated with kicad-footprint-generator
+connector JST ACH vertical
+0
+3
+2
+Connector_JST
+JST_ACH_BM02B-ACHSS-GAN-ETF_1x02-1MP_P1.20mm_Vertical
+JST ACH series connector, BM02B-ACHSS-GAN-ETF (http://www.jst-mfg.com/product/pdf/eng/eACH.pdf), generated with kicad-footprint-generator
+connector JST ACH vertical
+0
+4
+3
+Connector_JST
+JST_ACH_BM03B-ACHSS-GAN-ETF_1x03-1MP_P1.20mm_Vertical
+JST ACH series connector, BM03B-ACHSS-GAN-ETF (http://www.jst-mfg.com/product/pdf/eng/eACH.pdf), generated with kicad-footprint-generator
+connector JST ACH vertical
+0
+5
+4
+Connector_JST
+JST_ACH_BM04B-ACHSS-A-GAN-ETF_1x04-1MP_P1.20mm_Vertical
+JST ACH series connector, BM04B-ACHSS-A-GAN-ETF (http://www.jst-mfg.com/product/pdf/eng/eACH.pdf), generated with kicad-footprint-generator
+connector JST ACH vertical
+0
+6
+5
+Connector_JST
+JST_ACH_BM05B-ACHSS-A-GAN-ETF_1x05-1MP_P1.20mm_Vertical
+JST ACH series connector, BM05B-ACHSS-A-GAN-ETF (http://www.jst-mfg.com/product/pdf/eng/eACH.pdf), generated with kicad-footprint-generator
+connector JST ACH vertical
+0
+7
+6
+Connector_JST
+JST_AUH_BM03B-AUHKS-GA-TB_1x03-1MP_P1.50mm_Vertical
+JST AUH series connector, BM03B-AUHKS-GA-TB (http://www.jst-mfg.com/product/pdf/eng/eAUH.pdf), generated with kicad-footprint-generator
+connector JST AUH side entry
+0
+5
+4
+Connector_JST
+JST_AUH_BM05B-AUHKS-GA-TB_1x05-1MP_P1.50mm_Vertical
+JST AUH series connector, BM05B-AUHKS-GA-TB (http://www.jst-mfg.com/product/pdf/eng/eAUH.pdf), generated with kicad-footprint-generator
+connector JST AUH side entry
+0
+7
+6
+Connector_JST
+JST_EH_B2B-EH-A_1x02_P2.50mm_Vertical
+JST EH series connector, B2B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH vertical
+0
+2
+2
+Connector_JST
+JST_EH_B3B-EH-A_1x03_P2.50mm_Vertical
+JST EH series connector, B3B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH vertical
+0
+3
+3
+Connector_JST
+JST_EH_B4B-EH-A_1x04_P2.50mm_Vertical
+JST EH series connector, B4B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH vertical
+0
+4
+4
+Connector_JST
+JST_EH_B5B-EH-A_1x05_P2.50mm_Vertical
+JST EH series connector, B5B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH vertical
+0
+5
+5
+Connector_JST
+JST_EH_B6B-EH-A_1x06_P2.50mm_Vertical
+JST EH series connector, B6B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH vertical
+0
+6
+6
+Connector_JST
+JST_EH_B7B-EH-A_1x07_P2.50mm_Vertical
+JST EH series connector, B7B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH vertical
+0
+7
+7
+Connector_JST
+JST_EH_B8B-EH-A_1x08_P2.50mm_Vertical
+JST EH series connector, B8B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH vertical
+0
+8
+8
+Connector_JST
+JST_EH_B9B-EH-A_1x09_P2.50mm_Vertical
+JST EH series connector, B9B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH vertical
+0
+9
+9
+Connector_JST
+JST_EH_B10B-EH-A_1x10_P2.50mm_Vertical
+JST EH series connector, B10B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH side entry
+0
+10
+10
+Connector_JST
+JST_EH_B11B-EH-A_1x11_P2.50mm_Vertical
+JST EH series connector, B11B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH side entry
+0
+11
+11
+Connector_JST
+JST_EH_B12B-EH-A_1x12_P2.50mm_Vertical
+JST EH series connector, B12B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH side entry
+0
+12
+12
+Connector_JST
+JST_EH_B13B-EH-A_1x13_P2.50mm_Vertical
+JST EH series connector, B13B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH side entry
+0
+13
+13
+Connector_JST
+JST_EH_B14B-EH-A_1x14_P2.50mm_Vertical
+JST EH series connector, B14B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH side entry
+0
+14
+14
+Connector_JST
+JST_EH_B15B-EH-A_1x15_P2.50mm_Vertical
+JST EH series connector, B15B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH side entry
+0
+15
+15
+Connector_JST
+JST_EH_S2B-EH_1x02_P2.50mm_Horizontal
+JST EH series connector, S2B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH horizontal
+0
+2
+2
+Connector_JST
+JST_EH_S3B-EH_1x03_P2.50mm_Horizontal
+JST EH series connector, S3B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH horizontal
+0
+3
+3
+Connector_JST
+JST_EH_S4B-EH_1x04_P2.50mm_Horizontal
+JST EH series connector, S4B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH horizontal
+0
+4
+4
+Connector_JST
+JST_EH_S5B-EH_1x05_P2.50mm_Horizontal
+JST EH series connector, S5B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH horizontal
+0
+5
+5
+Connector_JST
+JST_EH_S6B-EH_1x06_P2.50mm_Horizontal
+JST EH series connector, S6B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH horizontal
+0
+6
+6
+Connector_JST
+JST_EH_S7B-EH_1x07_P2.50mm_Horizontal
+JST EH series connector, S7B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH horizontal
+0
+7
+7
+Connector_JST
+JST_EH_S8B-EH_1x08_P2.50mm_Horizontal
+JST EH series connector, S8B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH horizontal
+0
+8
+8
+Connector_JST
+JST_EH_S9B-EH_1x09_P2.50mm_Horizontal
+JST EH series connector, S9B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH horizontal
+0
+9
+9
+Connector_JST
+JST_EH_S10B-EH_1x10_P2.50mm_Horizontal
+JST EH series connector, S10B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH top entry
+0
+10
+10
+Connector_JST
+JST_EH_S11B-EH_1x11_P2.50mm_Horizontal
+JST EH series connector, S11B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH top entry
+0
+11
+11
+Connector_JST
+JST_EH_S12B-EH_1x12_P2.50mm_Horizontal
+JST EH series connector, S12B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH top entry
+0
+12
+12
+Connector_JST
+JST_EH_S13B-EH_1x13_P2.50mm_Horizontal
+JST EH series connector, S13B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH top entry
+0
+13
+13
+Connector_JST
+JST_EH_S14B-EH_1x14_P2.50mm_Horizontal
+JST EH series connector, S14B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH top entry
+0
+14
+14
+Connector_JST
+JST_EH_S15B-EH_1x15_P2.50mm_Horizontal
+JST EH series connector, S15B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator
+connector JST EH top entry
+0
+15
+15
+Connector_JST
+JST_GH_BM02B-GHS-TBT_1x02-1MP_P1.25mm_Vertical
+JST GH series connector, BM02B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH side entry
+0
+4
+3
+Connector_JST
+JST_GH_BM03B-GHS-TBT_1x03-1MP_P1.25mm_Vertical
+JST GH series connector, BM03B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH side entry
+0
+5
+4
+Connector_JST
+JST_GH_BM04B-GHS-TBT_1x04-1MP_P1.25mm_Vertical
+JST GH series connector, BM04B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH side entry
+0
+6
+5
+Connector_JST
+JST_GH_BM05B-GHS-TBT_1x05-1MP_P1.25mm_Vertical
+JST GH series connector, BM05B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH side entry
+0
+7
+6
+Connector_JST
+JST_GH_BM06B-GHS-TBT_1x06-1MP_P1.25mm_Vertical
+JST GH series connector, BM06B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH side entry
+0
+8
+7
+Connector_JST
+JST_GH_BM07B-GHS-TBT_1x07-1MP_P1.25mm_Vertical
+JST GH series connector, BM07B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH side entry
+0
+9
+8
+Connector_JST
+JST_GH_BM08B-GHS-TBT_1x08-1MP_P1.25mm_Vertical
+JST GH series connector, BM08B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH side entry
+0
+10
+9
+Connector_JST
+JST_GH_BM09B-GHS-TBT_1x09-1MP_P1.25mm_Vertical
+JST GH series connector, BM09B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH side entry
+0
+11
+10
+Connector_JST
+JST_GH_BM10B-GHS-TBT_1x10-1MP_P1.25mm_Vertical
+JST GH series connector, BM10B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH side entry
+0
+12
+11
+Connector_JST
+JST_GH_BM11B-GHS-TBT_1x11-1MP_P1.25mm_Vertical
+JST GH series connector, BM11B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH side entry
+0
+13
+12
+Connector_JST
+JST_GH_BM12B-GHS-TBT_1x12-1MP_P1.25mm_Vertical
+JST GH series connector, BM12B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH side entry
+0
+14
+13
+Connector_JST
+JST_GH_BM13B-GHS-TBT_1x13-1MP_P1.25mm_Vertical
+JST GH series connector, BM13B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH side entry
+0
+15
+14
+Connector_JST
+JST_GH_BM14B-GHS-TBT_1x14-1MP_P1.25mm_Vertical
+JST GH series connector, BM14B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH side entry
+0
+16
+15
+Connector_JST
+JST_GH_BM15B-GHS-TBT_1x15-1MP_P1.25mm_Vertical
+JST GH series connector, BM15B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH side entry
+0
+17
+16
+Connector_JST
+JST_GH_SM02B-GHS-TB_1x02-1MP_P1.25mm_Horizontal
+JST GH series connector, SM02B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH top entry
+0
+4
+3
+Connector_JST
+JST_GH_SM03B-GHS-TB_1x03-1MP_P1.25mm_Horizontal
+JST GH series connector, SM03B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH top entry
+0
+5
+4
+Connector_JST
+JST_GH_SM04B-GHS-TB_1x04-1MP_P1.25mm_Horizontal
+JST GH series connector, SM04B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH top entry
+0
+6
+5
+Connector_JST
+JST_GH_SM05B-GHS-TB_1x05-1MP_P1.25mm_Horizontal
+JST GH series connector, SM05B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH top entry
+0
+7
+6
+Connector_JST
+JST_GH_SM06B-GHS-TB_1x06-1MP_P1.25mm_Horizontal
+JST GH series connector, SM06B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH top entry
+0
+8
+7
+Connector_JST
+JST_GH_SM07B-GHS-TB_1x07-1MP_P1.25mm_Horizontal
+JST GH series connector, SM07B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH top entry
+0
+9
+8
+Connector_JST
+JST_GH_SM08B-GHS-TB_1x08-1MP_P1.25mm_Horizontal
+JST GH series connector, SM08B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH top entry
+0
+10
+9
+Connector_JST
+JST_GH_SM09B-GHS-TB_1x09-1MP_P1.25mm_Horizontal
+JST GH series connector, SM09B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH top entry
+0
+11
+10
+Connector_JST
+JST_GH_SM10B-GHS-TB_1x10-1MP_P1.25mm_Horizontal
+JST GH series connector, SM10B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH top entry
+0
+12
+11
+Connector_JST
+JST_GH_SM11B-GHS-TB_1x11-1MP_P1.25mm_Horizontal
+JST GH series connector, SM11B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH top entry
+0
+13
+12
+Connector_JST
+JST_GH_SM12B-GHS-TB_1x12-1MP_P1.25mm_Horizontal
+JST GH series connector, SM12B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH top entry
+0
+14
+13
+Connector_JST
+JST_GH_SM13B-GHS-TB_1x13-1MP_P1.25mm_Horizontal
+JST GH series connector, SM13B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH top entry
+0
+15
+14
+Connector_JST
+JST_GH_SM14B-GHS-TB_1x14-1MP_P1.25mm_Horizontal
+JST GH series connector, SM14B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH top entry
+0
+16
+15
+Connector_JST
+JST_GH_SM15B-GHS-TB_1x15-1MP_P1.25mm_Horizontal
+JST GH series connector, SM15B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator
+connector JST GH top entry
+0
+17
+16
+Connector_JST
+JST_J2100_B06B-J21DK-GGXR_2x03_P2.50x4.00mm_Vertical
+JST J2100 series connector, B06B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator
+connector JST J2100 vertical
+0
+8
+6
+Connector_JST
+JST_J2100_B08B-J21DK-GGXR_2x04_P2.50x4.00mm_Vertical
+JST J2100 series connector, B08B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator
+connector JST J2100 vertical
+0
+10
+8
+Connector_JST
+JST_J2100_B10B-J21DK-GGXR_2x05_P2.50x4.00mm_Vertical
+JST J2100 series connector, B10B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator
+connector JST J2100 vertical
+0
+12
+10
+Connector_JST
+JST_J2100_B12B-J21DK-GGXR_2x06_P2.50x4.00mm_Vertical
+JST J2100 series connector, B12B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator
+connector JST J2100 vertical
+0
+14
+12
+Connector_JST
+JST_J2100_B16B-J21DK-GGXR_2x08_P2.50x4.00mm_Vertical
+JST J2100 series connector, B16B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator
+connector JST J2100 vertical
+0
+18
+16
+Connector_JST
+JST_J2100_B20B-J21DK-GGXR_2x10_P2.50x4.00mm_Vertical
+JST J2100 series connector, B20B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator
+connector JST J2100 vertical
+0
+22
+20
+Connector_JST
+JST_J2100_S06B-J21DK-GGXR_2x03_P2.50mm_Horizontal
+JST J2100 series connector, S06B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator
+connector JST J2100 horizontal
+0
+7
+6
+Connector_JST
+JST_J2100_S08B-J21DK-GGXR_2x04_P2.50mm_Horizontal
+JST J2100 series connector, S08B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator
+connector JST J2100 horizontal
+0
+10
+8
+Connector_JST
+JST_J2100_S10B-J21DK-GGXR_2x05_P2.50mm_Horizontal
+JST J2100 series connector, S10B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator
+connector JST J2100 horizontal
+0
+12
+10
+Connector_JST
+JST_J2100_S12B-J21DK-GGXR_2x06_P2.50mm_Horizontal
+JST J2100 series connector, S12B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator
+connector JST J2100 horizontal
+0
+14
+12
+Connector_JST
+JST_J2100_S16B-J21DK-GGXR_2x08_P2.50mm_Horizontal
+JST J2100 series connector, S16B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator
+connector JST J2100 horizontal
+0
+18
+16
+Connector_JST
+JST_J2100_S20B-J21DK-GGXR_2x10_P2.50mm_Horizontal
+JST J2100 series connector, S20B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator
+connector JST J2100 horizontal
+0
+22
+20
+Connector_JST
+JST_JWPF_B02B-JWPF-SK-R_1x02_P2.00mm_Vertical
+JST JWPF series connector, B02B-JWPF-SK-R (http://www.jst-mfg.com/product/pdf/eng/eJWPF1.pdf), generated with kicad-footprint-generator
+connector JST JWPF side entry
+0
+2
+2
+Connector_JST
+JST_JWPF_B03B-JWPF-SK-R_1x03_P2.00mm_Vertical
+JST JWPF series connector, B03B-JWPF-SK-R (http://www.jst-mfg.com/product/pdf/eng/eJWPF1.pdf), generated with kicad-footprint-generator
+connector JST JWPF side entry
+0
+3
+3
+Connector_JST
+JST_JWPF_B04B-JWPF-SK-R_1x04_P2.00mm_Vertical
+JST JWPF series connector, B04B-JWPF-SK-R (http://www.jst-mfg.com/product/pdf/eng/eJWPF1.pdf), generated with kicad-footprint-generator
+connector JST JWPF side entry
+0
+4
+4
+Connector_JST
+JST_JWPF_B06B-JWPF-SK-R_2x03_P2.00mm_Vertical
+JST JWPF series connector, B06B-JWPF-SK-R (http://www.jst-mfg.com/product/pdf/eng/eJWPF1.pdf), generated with kicad-footprint-generator
+connector JST JWPF side entry
+0
+6
+6
+Connector_JST
+JST_JWPF_B08B-JWPF-SK-R_2x04_P2.00mm_Vertical
+JST JWPF series connector, B08B-JWPF-SK-R (http://www.jst-mfg.com/product/pdf/eng/eJWPF1.pdf), generated with kicad-footprint-generator
+connector JST JWPF side entry
+0
+8
+8
+Connector_JST
+JST_LEA_SM02B-LEASS-TF_1x02-1MP_P4.20mm_Horizontal
+JST LEA series connector, SM02B-LEASS-TF (http://www.jst-mfg.com/product/pdf/eng/eLEA.pdf), generated with kicad-footprint-generator
+connector JST LEA top entry
+0
+4
+3
+Connector_JST
+JST_NV_B02P-NV_1x02_P5.00mm_Vertical
+JST NV series connector, B02P-NV (http://www.jst-mfg.com/product/pdf/eng/eNV.pdf), generated with kicad-footprint-generator
+connector JST NV side entry
+0
+2
+2
+Connector_JST
+JST_NV_B03P-NV_1x03_P5.00mm_Vertical
+JST NV series connector, B03P-NV (http://www.jst-mfg.com/product/pdf/eng/eNV.pdf), generated with kicad-footprint-generator
+connector JST NV side entry
+0
+3
+3
+Connector_JST
+JST_NV_B04P-NV_1x04_P5.00mm_Vertical
+JST NV series connector, B04P-NV (http://www.jst-mfg.com/product/pdf/eng/eNV.pdf), generated with kicad-footprint-generator
+connector JST NV side entry
+0
+4
+4
+Connector_JST
+JST_PHD_B8B-PHDSS_2x04_P2.00mm_Vertical
+JST PHD series connector, B8B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD vertical
+0
+8
+8
+Connector_JST
+JST_PHD_B10B-PHDSS_2x05_P2.00mm_Vertical
+JST PHD series connector, B10B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD vertical
+0
+10
+10
+Connector_JST
+JST_PHD_B12B-PHDSS_2x06_P2.00mm_Vertical
+JST PHD series connector, B12B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD vertical
+0
+12
+12
+Connector_JST
+JST_PHD_B14B-PHDSS_2x07_P2.00mm_Vertical
+JST PHD series connector, B14B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD vertical
+0
+14
+14
+Connector_JST
+JST_PHD_B16B-PHDSS_2x08_P2.00mm_Vertical
+JST PHD series connector, B16B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD vertical
+0
+16
+16
+Connector_JST
+JST_PHD_B18B-PHDSS_2x09_P2.00mm_Vertical
+JST PHD series connector, B18B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD vertical
+0
+18
+18
+Connector_JST
+JST_PHD_B20B-PHDSS_2x10_P2.00mm_Vertical
+JST PHD series connector, B20B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD vertical
+0
+20
+20
+Connector_JST
+JST_PHD_B22B-PHDSS_2x11_P2.00mm_Vertical
+JST PHD series connector, B22B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD vertical
+0
+22
+22
+Connector_JST
+JST_PHD_B24B-PHDSS_2x12_P2.00mm_Vertical
+JST PHD series connector, B24B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD vertical
+0
+24
+24
+Connector_JST
+JST_PHD_B26B-PHDSS_2x13_P2.00mm_Vertical
+JST PHD series connector, B26B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD vertical
+0
+26
+26
+Connector_JST
+JST_PHD_B28B-PHDSS_2x14_P2.00mm_Vertical
+JST PHD series connector, B28B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD vertical
+0
+28
+28
+Connector_JST
+JST_PHD_B30B-PHDSS_2x15_P2.00mm_Vertical
+JST PHD series connector, B30B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD vertical
+0
+30
+30
+Connector_JST
+JST_PHD_B32B-PHDSS_2x16_P2.00mm_Vertical
+JST PHD series connector, B32B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD vertical
+0
+32
+32
+Connector_JST
+JST_PHD_B34B-PHDSS_2x17_P2.00mm_Vertical
+JST PHD series connector, B34B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD vertical
+0
+34
+34
+Connector_JST
+JST_PHD_S8B-PHDSS_2x04_P2.00mm_Horizontal
+JST PHD series connector, S8B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD horizontal
+0
+8
+8
+Connector_JST
+JST_PHD_S10B-PHDSS_2x05_P2.00mm_Horizontal
+JST PHD series connector, S10B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD horizontal
+0
+10
+10
+Connector_JST
+JST_PHD_S12B-PHDSS_2x06_P2.00mm_Horizontal
+JST PHD series connector, S12B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD horizontal
+0
+12
+12
+Connector_JST
+JST_PHD_S14B-PHDSS_2x07_P2.00mm_Horizontal
+JST PHD series connector, S14B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD horizontal
+0
+14
+14
+Connector_JST
+JST_PHD_S16B-PHDSS_2x08_P2.00mm_Horizontal
+JST PHD series connector, S16B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD horizontal
+0
+16
+16
+Connector_JST
+JST_PHD_S18B-PHDSS_2x09_P2.00mm_Horizontal
+JST PHD series connector, S18B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD horizontal
+0
+18
+18
+Connector_JST
+JST_PHD_S20B-PHDSS_2x10_P2.00mm_Horizontal
+JST PHD series connector, S20B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD horizontal
+0
+20
+20
+Connector_JST
+JST_PHD_S22B-PHDSS_2x11_P2.00mm_Horizontal
+JST PHD series connector, S22B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD horizontal
+0
+22
+22
+Connector_JST
+JST_PHD_S24B-PHDSS_2x12_P2.00mm_Horizontal
+JST PHD series connector, S24B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD horizontal
+0
+24
+24
+Connector_JST
+JST_PHD_S26B-PHDSS_2x13_P2.00mm_Horizontal
+JST PHD series connector, S26B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD horizontal
+0
+26
+26
+Connector_JST
+JST_PHD_S28B-PHDSS_2x14_P2.00mm_Horizontal
+JST PHD series connector, S28B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD horizontal
+0
+28
+28
+Connector_JST
+JST_PHD_S30B-PHDSS_2x15_P2.00mm_Horizontal
+JST PHD series connector, S30B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD horizontal
+0
+30
+30
+Connector_JST
+JST_PHD_S32B-PHDSS_2x16_P2.00mm_Horizontal
+JST PHD series connector, S32B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD horizontal
+0
+32
+32
+Connector_JST
+JST_PHD_S34B-PHDSS_2x17_P2.00mm_Horizontal
+JST PHD series connector, S34B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator
+connector JST PHD horizontal
+0
+34
+34
+Connector_JST
+JST_PH_B2B-PH-K_1x02_P2.00mm_Vertical
+JST PH series connector, B2B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+2
+2
+Connector_JST
+JST_PH_B2B-PH-SM4-TB_1x02-1MP_P2.00mm_Vertical
+JST PH series connector, B2B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+4
+3
+Connector_JST
+JST_PH_B3B-PH-K_1x03_P2.00mm_Vertical
+JST PH series connector, B3B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+3
+3
+Connector_JST
+JST_PH_B3B-PH-SM4-TB_1x03-1MP_P2.00mm_Vertical
+JST PH series connector, B3B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+5
+4
+Connector_JST
+JST_PH_B4B-PH-K_1x04_P2.00mm_Vertical
+JST PH series connector, B4B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+4
+4
+Connector_JST
+JST_PH_B4B-PH-SM4-TB_1x04-1MP_P2.00mm_Vertical
+JST PH series connector, B4B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+6
+5
+Connector_JST
+JST_PH_B5B-PH-K_1x05_P2.00mm_Vertical
+JST PH series connector, B5B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+5
+5
+Connector_JST
+JST_PH_B5B-PH-SM4-TB_1x05-1MP_P2.00mm_Vertical
+JST PH series connector, B5B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+7
+6
+Connector_JST
+JST_PH_B6B-PH-K_1x06_P2.00mm_Vertical
+JST PH series connector, B6B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+6
+6
+Connector_JST
+JST_PH_B6B-PH-SM4-TB_1x06-1MP_P2.00mm_Vertical
+JST PH series connector, B6B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+8
+7
+Connector_JST
+JST_PH_B7B-PH-K_1x07_P2.00mm_Vertical
+JST PH series connector, B7B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+7
+7
+Connector_JST
+JST_PH_B7B-PH-SM4-TB_1x07-1MP_P2.00mm_Vertical
+JST PH series connector, B7B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+9
+8
+Connector_JST
+JST_PH_B8B-PH-K_1x08_P2.00mm_Vertical
+JST PH series connector, B8B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+8
+8
+Connector_JST
+JST_PH_B8B-PH-SM4-TB_1x08-1MP_P2.00mm_Vertical
+JST PH series connector, B8B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+10
+9
+Connector_JST
+JST_PH_B9B-PH-K_1x09_P2.00mm_Vertical
+JST PH series connector, B9B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+9
+9
+Connector_JST
+JST_PH_B9B-PH-SM4-TB_1x09-1MP_P2.00mm_Vertical
+JST PH series connector, B9B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+11
+10
+Connector_JST
+JST_PH_B10B-PH-K_1x10_P2.00mm_Vertical
+JST PH series connector, B10B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+10
+10
+Connector_JST
+JST_PH_B10B-PH-SM4-TB_1x10-1MP_P2.00mm_Vertical
+JST PH series connector, B10B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+12
+11
+Connector_JST
+JST_PH_B11B-PH-K_1x11_P2.00mm_Vertical
+JST PH series connector, B11B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+11
+11
+Connector_JST
+JST_PH_B11B-PH-SM4-TB_1x11-1MP_P2.00mm_Vertical
+JST PH series connector, B11B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+13
+12
+Connector_JST
+JST_PH_B12B-PH-K_1x12_P2.00mm_Vertical
+JST PH series connector, B12B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+12
+12
+Connector_JST
+JST_PH_B12B-PH-SM4-TB_1x12-1MP_P2.00mm_Vertical
+JST PH series connector, B12B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+14
+13
+Connector_JST
+JST_PH_B13B-PH-K_1x13_P2.00mm_Vertical
+JST PH series connector, B13B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+13
+13
+Connector_JST
+JST_PH_B13B-PH-SM4-TB_1x13-1MP_P2.00mm_Vertical
+JST PH series connector, B13B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+15
+14
+Connector_JST
+JST_PH_B14B-PH-K_1x14_P2.00mm_Vertical
+JST PH series connector, B14B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+14
+14
+Connector_JST
+JST_PH_B14B-PH-SM4-TB_1x14-1MP_P2.00mm_Vertical
+JST PH series connector, B14B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+16
+15
+Connector_JST
+JST_PH_B15B-PH-K_1x15_P2.00mm_Vertical
+JST PH series connector, B15B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+15
+15
+Connector_JST
+JST_PH_B15B-PH-SM4-TB_1x15-1MP_P2.00mm_Vertical
+JST PH series connector, B15B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+17
+16
+Connector_JST
+JST_PH_B16B-PH-K_1x16_P2.00mm_Vertical
+JST PH series connector, B16B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+16
+16
+Connector_JST
+JST_PH_B16B-PH-SM4-TB_1x16-1MP_P2.00mm_Vertical
+JST PH series connector, B16B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH side entry
+0
+18
+17
+Connector_JST
+JST_PH_S2B-PH-K_1x02_P2.00mm_Horizontal
+JST PH series connector, S2B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+2
+2
+Connector_JST
+JST_PH_S2B-PH-SM4-TB_1x02-1MP_P2.00mm_Horizontal
+JST PH series connector, S2B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+4
+3
+Connector_JST
+JST_PH_S3B-PH-K_1x03_P2.00mm_Horizontal
+JST PH series connector, S3B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+3
+3
+Connector_JST
+JST_PH_S3B-PH-SM4-TB_1x03-1MP_P2.00mm_Horizontal
+JST PH series connector, S3B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+5
+4
+Connector_JST
+JST_PH_S4B-PH-K_1x04_P2.00mm_Horizontal
+JST PH series connector, S4B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+4
+4
+Connector_JST
+JST_PH_S4B-PH-SM4-TB_1x04-1MP_P2.00mm_Horizontal
+JST PH series connector, S4B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+6
+5
+Connector_JST
+JST_PH_S5B-PH-K_1x05_P2.00mm_Horizontal
+JST PH series connector, S5B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+5
+5
+Connector_JST
+JST_PH_S5B-PH-SM4-TB_1x05-1MP_P2.00mm_Horizontal
+JST PH series connector, S5B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+7
+6
+Connector_JST
+JST_PH_S6B-PH-K_1x06_P2.00mm_Horizontal
+JST PH series connector, S6B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+6
+6
+Connector_JST
+JST_PH_S6B-PH-SM4-TB_1x06-1MP_P2.00mm_Horizontal
+JST PH series connector, S6B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+8
+7
+Connector_JST
+JST_PH_S7B-PH-K_1x07_P2.00mm_Horizontal
+JST PH series connector, S7B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+7
+7
+Connector_JST
+JST_PH_S7B-PH-SM4-TB_1x07-1MP_P2.00mm_Horizontal
+JST PH series connector, S7B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+9
+8
+Connector_JST
+JST_PH_S8B-PH-K_1x08_P2.00mm_Horizontal
+JST PH series connector, S8B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+8
+8
+Connector_JST
+JST_PH_S8B-PH-SM4-TB_1x08-1MP_P2.00mm_Horizontal
+JST PH series connector, S8B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+10
+9
+Connector_JST
+JST_PH_S9B-PH-K_1x09_P2.00mm_Horizontal
+JST PH series connector, S9B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+9
+9
+Connector_JST
+JST_PH_S9B-PH-SM4-TB_1x09-1MP_P2.00mm_Horizontal
+JST PH series connector, S9B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+11
+10
+Connector_JST
+JST_PH_S10B-PH-K_1x10_P2.00mm_Horizontal
+JST PH series connector, S10B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+10
+10
+Connector_JST
+JST_PH_S10B-PH-SM4-TB_1x10-1MP_P2.00mm_Horizontal
+JST PH series connector, S10B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+12
+11
+Connector_JST
+JST_PH_S11B-PH-K_1x11_P2.00mm_Horizontal
+JST PH series connector, S11B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+11
+11
+Connector_JST
+JST_PH_S11B-PH-SM4-TB_1x11-1MP_P2.00mm_Horizontal
+JST PH series connector, S11B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+13
+12
+Connector_JST
+JST_PH_S12B-PH-K_1x12_P2.00mm_Horizontal
+JST PH series connector, S12B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+12
+12
+Connector_JST
+JST_PH_S12B-PH-SM4-TB_1x12-1MP_P2.00mm_Horizontal
+JST PH series connector, S12B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+14
+13
+Connector_JST
+JST_PH_S13B-PH-K_1x13_P2.00mm_Horizontal
+JST PH series connector, S13B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+13
+13
+Connector_JST
+JST_PH_S13B-PH-SM4-TB_1x13-1MP_P2.00mm_Horizontal
+JST PH series connector, S13B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+15
+14
+Connector_JST
+JST_PH_S14B-PH-K_1x14_P2.00mm_Horizontal
+JST PH series connector, S14B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+14
+14
+Connector_JST
+JST_PH_S14B-PH-SM4-TB_1x14-1MP_P2.00mm_Horizontal
+JST PH series connector, S14B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+16
+15
+Connector_JST
+JST_PH_S15B-PH-K_1x15_P2.00mm_Horizontal
+JST PH series connector, S15B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+15
+15
+Connector_JST
+JST_PH_S15B-PH-SM4-TB_1x15-1MP_P2.00mm_Horizontal
+JST PH series connector, S15B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+17
+16
+Connector_JST
+JST_PH_S16B-PH-K_1x16_P2.00mm_Horizontal
+JST PH series connector, S16B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator
+connector JST PH top entry
+0
+16
+16
+Connector_JST
+JST_PUD_B08B-PUDSS_2x04_P2.00mm_Vertical
+JST PUD series connector, B08B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD side entry
+0
+8
+8
+Connector_JST
+JST_PUD_B10B-PUDSS_2x05_P2.00mm_Vertical
+JST PUD series connector, B10B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD side entry
+0
+10
+10
+Connector_JST
+JST_PUD_B12B-PUDSS_2x06_P2.00mm_Vertical
+JST PUD series connector, B12B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD side entry
+0
+12
+12
+Connector_JST
+JST_PUD_B14B-PUDSS_2x07_P2.00mm_Vertical
+JST PUD series connector, B14B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD side entry
+0
+14
+14
+Connector_JST
+JST_PUD_B16B-PUDSS_2x08_P2.00mm_Vertical
+JST PUD series connector, B16B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD side entry
+0
+16
+16
+Connector_JST
+JST_PUD_B18B-PUDSS_2x09_P2.00mm_Vertical
+JST PUD series connector, B18B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD side entry
+0
+18
+18
+Connector_JST
+JST_PUD_B20B-PUDSS_2x10_P2.00mm_Vertical
+JST PUD series connector, B20B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD side entry
+0
+20
+20
+Connector_JST
+JST_PUD_B22B-PUDSS_2x11_P2.00mm_Vertical
+JST PUD series connector, B22B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD side entry
+0
+22
+22
+Connector_JST
+JST_PUD_B24B-PUDSS_2x12_P2.00mm_Vertical
+JST PUD series connector, B24B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD side entry
+0
+24
+24
+Connector_JST
+JST_PUD_B26B-PUDSS_2x13_P2.00mm_Vertical
+JST PUD series connector, B26B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD side entry
+0
+26
+26
+Connector_JST
+JST_PUD_B28B-PUDSS_2x14_P2.00mm_Vertical
+JST PUD series connector, B28B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD side entry
+0
+28
+28
+Connector_JST
+JST_PUD_B30B-PUDSS_2x15_P2.00mm_Vertical
+JST PUD series connector, B30B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD side entry
+0
+30
+30
+Connector_JST
+JST_PUD_B32B-PUDSS_2x16_P2.00mm_Vertical
+JST PUD series connector, B32B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD side entry
+0
+32
+32
+Connector_JST
+JST_PUD_B34B-PUDSS_2x17_P2.00mm_Vertical
+JST PUD series connector, B34B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD side entry
+0
+34
+34
+Connector_JST
+JST_PUD_B36B-PUDSS_2x18_P2.00mm_Vertical
+JST PUD series connector, B36B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD side entry
+0
+36
+36
+Connector_JST
+JST_PUD_B38B-PUDSS_2x19_P2.00mm_Vertical
+JST PUD series connector, B38B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD side entry
+0
+38
+38
+Connector_JST
+JST_PUD_B40B-PUDSS_2x20_P2.00mm_Vertical
+JST PUD series connector, B40B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD side entry
+0
+40
+40
+Connector_JST
+JST_PUD_S08B-PUDSS-1_2x04_P2.00mm_Horizontal
+JST PUD series connector, S08B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD top entry
+0
+8
+8
+Connector_JST
+JST_PUD_S10B-PUDSS-1_2x05_P2.00mm_Horizontal
+JST PUD series connector, S10B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD top entry
+0
+10
+10
+Connector_JST
+JST_PUD_S12B-PUDSS-1_2x06_P2.00mm_Horizontal
+JST PUD series connector, S12B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD top entry
+0
+12
+12
+Connector_JST
+JST_PUD_S14B-PUDSS-1_2x07_P2.00mm_Horizontal
+JST PUD series connector, S14B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD top entry
+0
+14
+14
+Connector_JST
+JST_PUD_S16B-PUDSS-1_2x08_P2.00mm_Horizontal
+JST PUD series connector, S16B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD top entry
+0
+16
+16
+Connector_JST
+JST_PUD_S18B-PUDSS-1_2x09_P2.00mm_Horizontal
+JST PUD series connector, S18B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD top entry
+0
+18
+18
+Connector_JST
+JST_PUD_S20B-PUDSS-1_2x10_P2.00mm_Horizontal
+JST PUD series connector, S20B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD top entry
+0
+20
+20
+Connector_JST
+JST_PUD_S22B-PUDSS-1_2x11_P2.00mm_Horizontal
+JST PUD series connector, S22B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD top entry
+0
+22
+22
+Connector_JST
+JST_PUD_S24B-PUDSS-1_2x12_P2.00mm_Horizontal
+JST PUD series connector, S24B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD top entry
+0
+24
+24
+Connector_JST
+JST_PUD_S26B-PUDSS-1_2x13_P2.00mm_Horizontal
+JST PUD series connector, S26B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD top entry
+0
+26
+26
+Connector_JST
+JST_PUD_S28B-PUDSS-1_2x14_P2.00mm_Horizontal
+JST PUD series connector, S28B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD top entry
+0
+28
+28
+Connector_JST
+JST_PUD_S30B-PUDSS-1_2x15_P2.00mm_Horizontal
+JST PUD series connector, S30B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD top entry
+0
+30
+30
+Connector_JST
+JST_PUD_S32B-PUDSS-1_2x16_P2.00mm_Horizontal
+JST PUD series connector, S32B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD top entry
+0
+32
+32
+Connector_JST
+JST_PUD_S34B-PUDSS-1_2x17_P2.00mm_Horizontal
+JST PUD series connector, S34B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD top entry
+0
+34
+34
+Connector_JST
+JST_PUD_S36B-PUDSS-1_2x18_P2.00mm_Horizontal
+JST PUD series connector, S36B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD top entry
+0
+36
+36
+Connector_JST
+JST_PUD_S38B-PUDSS-1_2x19_P2.00mm_Horizontal
+JST PUD series connector, S38B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD top entry
+0
+38
+38
+Connector_JST
+JST_PUD_S40B-PUDSS-1_2x20_P2.00mm_Horizontal
+JST PUD series connector, S40B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator
+connector JST PUD top entry
+0
+40
+40
+Connector_JST
+JST_SFH_SM02B-SFHRS-TF_1x02-1MP_P4.20mm_Horizontal
+JST SFH series connector, SM02B-SFHRS-TF (http://www.jst-mfg.com/product/pdf/eng/eSFH.pdf), generated with kicad-footprint-generator
+connector JST SFH horizontal
+0
+4
+3
+Connector_JST
+JST_SHL_SM02B-SHLS-TF_1x02-1MP_P1.00mm_Horizontal
+JST SHL series connector, SM02B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator
+connector JST SHL top entry
+0
+4
+3
+Connector_JST
+JST_SHL_SM05B-SHLS-TF_1x05-1MP_P1.00mm_Horizontal
+JST SHL series connector, SM05B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator
+connector JST SHL top entry
+0
+7
+6
+Connector_JST
+JST_SHL_SM06B-SHLS-TF_1x06-1MP_P1.00mm_Horizontal
+JST SHL series connector, SM06B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator
+connector JST SHL top entry
+0
+8
+7
+Connector_JST
+JST_SHL_SM07B-SHLS-TF_1x07-1MP_P1.00mm_Horizontal
+JST SHL series connector, SM07B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator
+connector JST SHL top entry
+0
+9
+8
+Connector_JST
+JST_SHL_SM08B-SHLS-TF_1x08-1MP_P1.00mm_Horizontal
+JST SHL series connector, SM08B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator
+connector JST SHL top entry
+0
+10
+9
+Connector_JST
+JST_SHL_SM10B-SHLS-TF_1x10-1MP_P1.00mm_Horizontal
+JST SHL series connector, SM10B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator
+connector JST SHL top entry
+0
+12
+11
+Connector_JST
+JST_SHL_SM11B-SHLS-TF_1x11-1MP_P1.00mm_Horizontal
+JST SHL series connector, SM11B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator
+connector JST SHL top entry
+0
+13
+12
+Connector_JST
+JST_SHL_SM12B-SHLS-TF_1x12-1MP_P1.00mm_Horizontal
+JST SHL series connector, SM12B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator
+connector JST SHL top entry
+0
+14
+13
+Connector_JST
+JST_SHL_SM14B-SHLS-TF_1x14-1MP_P1.00mm_Horizontal
+JST SHL series connector, SM14B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator
+connector JST SHL top entry
+0
+16
+15
+Connector_JST
+JST_SHL_SM16B-SHLS-TF_1x16-1MP_P1.00mm_Horizontal
+JST SHL series connector, SM16B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator
+connector JST SHL top entry
+0
+18
+17
+Connector_JST
+JST_SHL_SM20B-SHLS-TF_1x20-1MP_P1.00mm_Horizontal
+JST SHL series connector, SM20B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator
+connector JST SHL top entry
+0
+22
+21
+Connector_JST
+JST_SHL_SM22B-SHLS-TF_1x22-1MP_P1.00mm_Horizontal
+JST SHL series connector, SM22B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator
+connector JST SHL top entry
+0
+24
+23
+Connector_JST
+JST_SHL_SM26B-SHLS-TF_1x26-1MP_P1.00mm_Horizontal
+JST SHL series connector, SM26B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator
+connector JST SHL top entry
+0
+28
+27
+Connector_JST
+JST_SHL_SM30B-SHLS-TF_1x30-1MP_P1.00mm_Horizontal
+JST SHL series connector, SM30B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator
+connector JST SHL top entry
+0
+32
+31
+Connector_JST
+JST_SH_BM02B-SRSS-TB_1x02-1MP_P1.00mm_Vertical
+JST SH series connector, BM02B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH side entry
+0
+4
+3
+Connector_JST
+JST_SH_BM03B-SRSS-TB_1x03-1MP_P1.00mm_Vertical
+JST SH series connector, BM03B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH side entry
+0
+5
+4
+Connector_JST
+JST_SH_BM04B-SRSS-TB_1x04-1MP_P1.00mm_Vertical
+JST SH series connector, BM04B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH side entry
+0
+6
+5
+Connector_JST
+JST_SH_BM05B-SRSS-TB_1x05-1MP_P1.00mm_Vertical
+JST SH series connector, BM05B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH side entry
+0
+7
+6
+Connector_JST
+JST_SH_BM06B-SRSS-TB_1x06-1MP_P1.00mm_Vertical
+JST SH series connector, BM06B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH side entry
+0
+8
+7
+Connector_JST
+JST_SH_BM07B-SRSS-TB_1x07-1MP_P1.00mm_Vertical
+JST SH series connector, BM07B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH side entry
+0
+9
+8
+Connector_JST
+JST_SH_BM08B-SRSS-TB_1x08-1MP_P1.00mm_Vertical
+JST SH series connector, BM08B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH side entry
+0
+10
+9
+Connector_JST
+JST_SH_BM09B-SRSS-TB_1x09-1MP_P1.00mm_Vertical
+JST SH series connector, BM09B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH side entry
+0
+11
+10
+Connector_JST
+JST_SH_BM10B-SRSS-TB_1x10-1MP_P1.00mm_Vertical
+JST SH series connector, BM10B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH side entry
+0
+12
+11
+Connector_JST
+JST_SH_BM11B-SRSS-TB_1x11-1MP_P1.00mm_Vertical
+JST SH series connector, BM11B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH side entry
+0
+13
+12
+Connector_JST
+JST_SH_BM12B-SRSS-TB_1x12-1MP_P1.00mm_Vertical
+JST SH series connector, BM12B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH side entry
+0
+14
+13
+Connector_JST
+JST_SH_BM13B-SRSS-TB_1x13-1MP_P1.00mm_Vertical
+JST SH series connector, BM13B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH side entry
+0
+15
+14
+Connector_JST
+JST_SH_BM14B-SRSS-TB_1x14-1MP_P1.00mm_Vertical
+JST SH series connector, BM14B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH side entry
+0
+16
+15
+Connector_JST
+JST_SH_BM15B-SRSS-TB_1x15-1MP_P1.00mm_Vertical
+JST SH series connector, BM15B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH side entry
+0
+17
+16
+Connector_JST
+JST_SH_SM02B-SRSS-TB_1x02-1MP_P1.00mm_Horizontal
+JST SH series connector, SM02B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH top entry
+0
+4
+3
+Connector_JST
+JST_SH_SM03B-SRSS-TB_1x03-1MP_P1.00mm_Horizontal
+JST SH series connector, SM03B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH top entry
+0
+5
+4
+Connector_JST
+JST_SH_SM04B-SRSS-TB_1x04-1MP_P1.00mm_Horizontal
+JST SH series connector, SM04B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH top entry
+0
+6
+5
+Connector_JST
+JST_SH_SM05B-SRSS-TB_1x05-1MP_P1.00mm_Horizontal
+JST SH series connector, SM05B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH top entry
+0
+7
+6
+Connector_JST
+JST_SH_SM06B-SRSS-TB_1x06-1MP_P1.00mm_Horizontal
+JST SH series connector, SM06B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH top entry
+0
+8
+7
+Connector_JST
+JST_SH_SM07B-SRSS-TB_1x07-1MP_P1.00mm_Horizontal
+JST SH series connector, SM07B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH top entry
+0
+9
+8
+Connector_JST
+JST_SH_SM08B-SRSS-TB_1x08-1MP_P1.00mm_Horizontal
+JST SH series connector, SM08B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH top entry
+0
+10
+9
+Connector_JST
+JST_SH_SM09B-SRSS-TB_1x09-1MP_P1.00mm_Horizontal
+JST SH series connector, SM09B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH top entry
+0
+11
+10
+Connector_JST
+JST_SH_SM10B-SRSS-TB_1x10-1MP_P1.00mm_Horizontal
+JST SH series connector, SM10B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH top entry
+0
+12
+11
+Connector_JST
+JST_SH_SM11B-SRSS-TB_1x11-1MP_P1.00mm_Horizontal
+JST SH series connector, SM11B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH top entry
+0
+13
+12
+Connector_JST
+JST_SH_SM12B-SRSS-TB_1x12-1MP_P1.00mm_Horizontal
+JST SH series connector, SM12B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH top entry
+0
+14
+13
+Connector_JST
+JST_SH_SM13B-SRSS-TB_1x13-1MP_P1.00mm_Horizontal
+JST SH series connector, SM13B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH top entry
+0
+15
+14
+Connector_JST
+JST_SH_SM14B-SRSS-TB_1x14-1MP_P1.00mm_Horizontal
+JST SH series connector, SM14B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH top entry
+0
+16
+15
+Connector_JST
+JST_SH_SM15B-SRSS-TB_1x15-1MP_P1.00mm_Horizontal
+JST SH series connector, SM15B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH top entry
+0
+17
+16
+Connector_JST
+JST_SH_SM20B-SRSS-TB_1x20-1MP_P1.00mm_Horizontal
+JST SH series connector, SM20B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator
+connector JST SH top entry
+0
+22
+21
+Connector_JST
+JST_SUR_BM02B-SURS-TF_1x02-1MP_P0.80mm_Vertical
+JST SUR series connector, BM02B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR side entry
+0
+4
+3
+Connector_JST
+JST_SUR_BM03B-SURS-TF_1x03-1MP_P0.80mm_Vertical
+JST SUR series connector, BM03B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR side entry
+0
+5
+4
+Connector_JST
+JST_SUR_BM04B-SURS-TF_1x04-1MP_P0.80mm_Vertical
+JST SUR series connector, BM04B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR side entry
+0
+6
+5
+Connector_JST
+JST_SUR_BM05B-SURS-TF_1x05-1MP_P0.80mm_Vertical
+JST SUR series connector, BM05B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR side entry
+0
+7
+6
+Connector_JST
+JST_SUR_BM06B-SURS-TF_1x06-1MP_P0.80mm_Vertical
+JST SUR series connector, BM06B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR side entry
+0
+8
+7
+Connector_JST
+JST_SUR_BM08B-SURS-TF_1x08-1MP_P0.80mm_Vertical
+JST SUR series connector, BM08B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR side entry
+0
+10
+9
+Connector_JST
+JST_SUR_BM10B-SURS-TF_1x10-1MP_P0.80mm_Vertical
+JST SUR series connector, BM10B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR side entry
+0
+12
+11
+Connector_JST
+JST_SUR_BM12B-SURS-TF_1x12-1MP_P0.80mm_Vertical
+JST SUR series connector, BM12B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR side entry
+0
+14
+13
+Connector_JST
+JST_SUR_BM14B-SURS-TF_1x14-1MP_P0.80mm_Vertical
+JST SUR series connector, BM14B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR side entry
+0
+16
+15
+Connector_JST
+JST_SUR_BM15B-SURS-TF_1x15-1MP_P0.80mm_Vertical
+JST SUR series connector, BM15B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR side entry
+0
+17
+16
+Connector_JST
+JST_SUR_BM16B-SURS-TF_1x16-1MP_P0.80mm_Vertical
+JST SUR series connector, BM16B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR side entry
+0
+18
+17
+Connector_JST
+JST_SUR_BM17B-SURS-TF_1x17-1MP_P0.80mm_Vertical
+JST SUR series connector, BM17B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR side entry
+0
+19
+18
+Connector_JST
+JST_SUR_BM20B-SURS-TF_1x20-1MP_P0.80mm_Vertical
+JST SUR series connector, BM20B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR side entry
+0
+22
+21
+Connector_JST
+JST_SUR_SM02B-SURS-TF_1x02-1MP_P0.80mm_Horizontal
+JST SUR series connector, SM02B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR top entry
+0
+4
+3
+Connector_JST
+JST_SUR_SM03B-SURS-TF_1x03-1MP_P0.80mm_Horizontal
+JST SUR series connector, SM03B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR top entry
+0
+5
+4
+Connector_JST
+JST_SUR_SM04B-SURS-TF_1x04-1MP_P0.80mm_Horizontal
+JST SUR series connector, SM04B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR top entry
+0
+6
+5
+Connector_JST
+JST_SUR_SM05B-SURS-TF_1x05-1MP_P0.80mm_Horizontal
+JST SUR series connector, SM05B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR top entry
+0
+7
+6
+Connector_JST
+JST_SUR_SM06B-SURS-TF_1x06-1MP_P0.80mm_Horizontal
+JST SUR series connector, SM06B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR top entry
+0
+8
+7
+Connector_JST
+JST_SUR_SM08B-SURS-TF_1x08-1MP_P0.80mm_Horizontal
+JST SUR series connector, SM08B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR top entry
+0
+10
+9
+Connector_JST
+JST_SUR_SM10B-SURS-TF_1x10-1MP_P0.80mm_Horizontal
+JST SUR series connector, SM10B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR top entry
+0
+12
+11
+Connector_JST
+JST_SUR_SM12B-SURS-TF_1x12-1MP_P0.80mm_Horizontal
+JST SUR series connector, SM12B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR top entry
+0
+14
+13
+Connector_JST
+JST_SUR_SM14B-SURS-TF_1x14-1MP_P0.80mm_Horizontal
+JST SUR series connector, SM14B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR top entry
+0
+16
+15
+Connector_JST
+JST_SUR_SM15B-SURS-TF_1x15-1MP_P0.80mm_Horizontal
+JST SUR series connector, SM15B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR top entry
+0
+17
+16
+Connector_JST
+JST_SUR_SM16B-SURS-TF_1x16-1MP_P0.80mm_Horizontal
+JST SUR series connector, SM16B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR top entry
+0
+18
+17
+Connector_JST
+JST_SUR_SM17B-SURS-TF_1x17-1MP_P0.80mm_Horizontal
+JST SUR series connector, SM17B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR top entry
+0
+19
+18
+Connector_JST
+JST_SUR_SM20B-SURS-TF_1x20-1MP_P0.80mm_Horizontal
+JST SUR series connector, SM20B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR top entry
+0
+22
+21
+Connector_JST
+JST_SUR_SM22B-SURS-TF_1x22-1MP_P0.80mm_Horizontal
+JST SUR series connector, SM22B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator
+connector JST SUR top entry
+0
+24
+23
+Connector_JST
+JST_VH_B2P-VH-B_1x02_P3.96mm_Vertical
+JST VH PBT series connector, B2P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+2
+2
+Connector_JST
+JST_VH_B2P-VH-FB-B_1x02_P3.96mm_Vertical
+JST VH series connector, B2P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf),  generated with kicad-footprint-generator
+connector JST VH side entry
+0
+2
+2
+Connector_JST
+JST_VH_B2P-VH_1x02_P3.96mm_Vertical
+JST VH series connector, B2P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+2
+2
+Connector_JST
+JST_VH_B2P3-VH_1x02_P7.92mm_Vertical
+JST VH series connector, B2P3-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+2
+2
+Connector_JST
+JST_VH_B2PS-VH_1x02_P3.96mm_Horizontal
+JST VH series connector, B2PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH top entry
+0
+2
+2
+Connector_JST
+JST_VH_B3P-VH-B_1x03_P3.96mm_Vertical
+JST VH PBT series connector, B3P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+3
+3
+Connector_JST
+JST_VH_B3P-VH-FB-B_1x03_P3.96mm_Vertical
+JST VH series connector, B3P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf),  generated with kicad-footprint-generator
+connector JST VH side entry
+0
+3
+3
+Connector_JST
+JST_VH_B3P-VH_1x03_P3.96mm_Vertical
+JST VH series connector, B3P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+3
+3
+Connector_JST
+JST_VH_B3PS-VH_1x03_P3.96mm_Horizontal
+JST VH series connector, B3PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH top entry
+0
+3
+3
+Connector_JST
+JST_VH_B4P-VH-B_1x04_P3.96mm_Vertical
+JST VH PBT series connector, B4P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+4
+4
+Connector_JST
+JST_VH_B4P-VH-FB-B_1x04_P3.96mm_Vertical
+JST VH series connector, B4P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf),  generated with kicad-footprint-generator
+connector JST VH side entry
+0
+4
+4
+Connector_JST
+JST_VH_B4P-VH_1x04_P3.96mm_Vertical
+JST VH series connector, B4P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+4
+4
+Connector_JST
+JST_VH_B4PS-VH_1x04_P3.96mm_Horizontal
+JST VH series connector, B4PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH top entry
+0
+4
+4
+Connector_JST
+JST_VH_B5P-VH-B_1x05_P3.96mm_Vertical
+JST VH PBT series connector, B5P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+5
+5
+Connector_JST
+JST_VH_B5P-VH-FB-B_1x05_P3.96mm_Vertical
+JST VH series connector, B5P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf),  generated with kicad-footprint-generator
+connector JST VH side entry
+0
+5
+5
+Connector_JST
+JST_VH_B5P-VH_1x05_P3.96mm_Vertical
+JST VH series connector, B5P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+5
+5
+Connector_JST
+JST_VH_B5PS-VH_1x05_P3.96mm_Horizontal
+JST VH series connector, B5PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH top entry
+0
+5
+5
+Connector_JST
+JST_VH_B6P-VH-B_1x06_P3.96mm_Vertical
+JST VH PBT series connector, B6P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+6
+6
+Connector_JST
+JST_VH_B6P-VH-FB-B_1x06_P3.96mm_Vertical
+JST VH series connector, B6P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf),  generated with kicad-footprint-generator
+connector JST VH side entry
+0
+6
+6
+Connector_JST
+JST_VH_B6P-VH_1x06_P3.96mm_Vertical
+JST VH series connector, B6P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+6
+6
+Connector_JST
+JST_VH_B6PS-VH_1x06_P3.96mm_Horizontal
+JST VH series connector, B6PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH top entry
+0
+6
+6
+Connector_JST
+JST_VH_B7P-VH-B_1x07_P3.96mm_Vertical
+JST VH PBT series connector, B7P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+7
+7
+Connector_JST
+JST_VH_B7P-VH-FB-B_1x07_P3.96mm_Vertical
+JST VH series connector, B7P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf),  generated with kicad-footprint-generator
+connector JST VH side entry
+0
+7
+7
+Connector_JST
+JST_VH_B7P-VH_1x07_P3.96mm_Vertical
+JST VH series connector, B7P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+7
+7
+Connector_JST
+JST_VH_B7PS-VH_1x07_P3.96mm_Horizontal
+JST VH series connector, B7PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH top entry
+0
+7
+7
+Connector_JST
+JST_VH_B8P-VH-B_1x08_P3.96mm_Vertical
+JST VH PBT series connector, B8P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+8
+8
+Connector_JST
+JST_VH_B8P-VH-FB-B_1x08_P3.96mm_Vertical
+JST VH series connector, B8P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf),  generated with kicad-footprint-generator
+connector JST VH side entry
+0
+8
+8
+Connector_JST
+JST_VH_B8P-VH_1x08_P3.96mm_Vertical
+JST VH series connector, B8P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+8
+8
+Connector_JST
+JST_VH_B8PS-VH_1x08_P3.96mm_Horizontal
+JST VH series connector, B8PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH top entry
+0
+8
+8
+Connector_JST
+JST_VH_B9P-VH-B_1x09_P3.96mm_Vertical
+JST VH PBT series connector, B9P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+9
+9
+Connector_JST
+JST_VH_B9P-VH-FB-B_1x09_P3.96mm_Vertical
+JST VH series connector, B9P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf),  generated with kicad-footprint-generator
+connector JST VH side entry
+0
+9
+9
+Connector_JST
+JST_VH_B9P-VH_1x09_P3.96mm_Vertical
+JST VH series connector, B9P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+9
+9
+Connector_JST
+JST_VH_B9PS-VH_1x09_P3.96mm_Horizontal
+JST VH series connector, B9PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH top entry
+0
+9
+9
+Connector_JST
+JST_VH_B10P-VH-B_1x10_P3.96mm_Vertical
+JST VH PBT series connector, B10P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+10
+10
+Connector_JST
+JST_VH_B10P-VH-FB-B_1x10_P3.96mm_Vertical
+JST VH series connector, B10P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf),  generated with kicad-footprint-generator
+connector JST VH side entry
+0
+10
+10
+Connector_JST
+JST_VH_B10P-VH_1x10_P3.96mm_Vertical
+JST VH series connector, B10P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+10
+10
+Connector_JST
+JST_VH_B10PS-VH_1x10_P3.96mm_Horizontal
+JST VH series connector, B10PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH top entry
+0
+10
+10
+Connector_JST
+JST_VH_B11P-VH-B_1x11_P3.96mm_Vertical
+JST VH PBT series connector, B11P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH vertical
+0
+11
+11
+Connector_JST
+JST_VH_S2P-VH_1x02_P3.96mm_Horizontal
+JST VH series connector, S2P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH top entry
+0
+2
+2
+Connector_JST
+JST_VH_S3P-VH_1x03_P3.96mm_Horizontal
+JST VH series connector, S3P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH top entry
+0
+3
+3
+Connector_JST
+JST_VH_S4P-VH_1x04_P3.96mm_Horizontal
+JST VH series connector, S4P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH top entry
+0
+4
+4
+Connector_JST
+JST_VH_S5P-VH_1x05_P3.96mm_Horizontal
+JST VH series connector, S5P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH top entry
+0
+5
+5
+Connector_JST
+JST_VH_S6P-VH_1x06_P3.96mm_Horizontal
+JST VH series connector, S6P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH top entry
+0
+6
+6
+Connector_JST
+JST_VH_S7P-VH_1x07_P3.96mm_Horizontal
+JST VH series connector, S7P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator
+connector JST VH top entry
+0
+7
+7
+Connector_JST
+JST_XAG_SM05B-XAGKS-BN-TB_1x05-1MP_P2.50mm_Horizontal
+JST XAG series connector, SM05B-XAGKS-BN-TB (http://www.jst-mfg.com/product/pdf/eng/eXAG.pdf), generated with kicad-footprint-generator
+connector JST XAG top entry
+0
+7
+6
+Connector_JST
+JST_XH_B1B-XH-AM_1x01_P2.50mm_Vertical
+JST XH series connector, B1B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH vertical boss
+0
+1
+1
+Connector_JST
+JST_XH_B2B-XH-AM_1x02_P2.50mm_Vertical
+JST XH series connector, B2B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH vertical boss
+0
+2
+2
+Connector_JST
+JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical
+JST XH series connector, B2B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH vertical
+0
+2
+2
+Connector_JST
+JST_XH_B3B-XH-AM_1x03_P2.50mm_Vertical
+JST XH series connector, B3B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH vertical boss
+0
+3
+3
+Connector_JST
+JST_XH_B3B-XH-A_1x03_P2.50mm_Vertical
+JST XH series connector, B3B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH vertical
+0
+3
+3
+Connector_JST
+JST_XH_B4B-XH-AM_1x04_P2.50mm_Vertical
+JST XH series connector, B4B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH vertical boss
+0
+4
+4
+Connector_JST
+JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical
+JST XH series connector, B4B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH vertical
+0
+4
+4
+Connector_JST
+JST_XH_B5B-XH-AM_1x05_P2.50mm_Vertical
+JST XH series connector, B5B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH vertical boss
+0
+5
+5
+Connector_JST
+JST_XH_B5B-XH-A_1x05_P2.50mm_Vertical
+JST XH series connector, B5B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH vertical
+0
+5
+5
+Connector_JST
+JST_XH_B6B-XH-AM_1x06_P2.50mm_Vertical
+JST XH series connector, B6B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH vertical boss
+0
+6
+6
+Connector_JST
+JST_XH_B6B-XH-A_1x06_P2.50mm_Vertical
+JST XH series connector, B6B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH vertical
+0
+6
+6
+Connector_JST
+JST_XH_B7B-XH-AM_1x07_P2.50mm_Vertical
+JST XH series connector, B7B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH vertical boss
+0
+7
+7
+Connector_JST
+JST_XH_B7B-XH-A_1x07_P2.50mm_Vertical
+JST XH series connector, B7B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH vertical
+0
+7
+7
+Connector_JST
+JST_XH_B8B-XH-AM_1x08_P2.50mm_Vertical
+JST XH series connector, B8B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH vertical boss
+0
+8
+8
+Connector_JST
+JST_XH_B8B-XH-A_1x08_P2.50mm_Vertical
+JST XH series connector, B8B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH vertical
+0
+8
+8
+Connector_JST
+JST_XH_B9B-XH-AM_1x09_P2.50mm_Vertical
+JST XH series connector, B9B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH vertical boss
+0
+9
+9
+Connector_JST
+JST_XH_B9B-XH-A_1x09_P2.50mm_Vertical
+JST XH series connector, B9B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH vertical
+0
+9
+9
+Connector_JST
+JST_XH_B10B-XH-AM_1x10_P2.50mm_Vertical
+JST XH series connector, B10B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH side entry boss
+0
+10
+10
+Connector_JST
+JST_XH_B10B-XH-A_1x10_P2.50mm_Vertical
+JST XH series connector, B10B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH side entry
+0
+10
+10
+Connector_JST
+JST_XH_B11B-XH-A_1x11_P2.50mm_Vertical
+JST XH series connector, B11B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH side entry
+0
+11
+11
+Connector_JST
+JST_XH_B12B-XH-AM_1x12_P2.50mm_Vertical
+JST XH series connector, B12B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH side entry boss
+0
+12
+12
+Connector_JST
+JST_XH_B12B-XH-A_1x12_P2.50mm_Vertical
+JST XH series connector, B12B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH side entry
+0
+12
+12
+Connector_JST
+JST_XH_B13B-XH-A_1x13_P2.50mm_Vertical
+JST XH series connector, B13B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH side entry
+0
+13
+13
+Connector_JST
+JST_XH_B14B-XH-A_1x14_P2.50mm_Vertical
+JST XH series connector, B14B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH side entry
+0
+14
+14
+Connector_JST
+JST_XH_B15B-XH-A_1x15_P2.50mm_Vertical
+JST XH series connector, B15B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH side entry
+0
+15
+15
+Connector_JST
+JST_XH_B16B-XH-A_1x16_P2.50mm_Vertical
+JST XH series connector, B16B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH side entry
+0
+16
+16
+Connector_JST
+JST_XH_B20B-XH-A_1x20_P2.50mm_Vertical
+JST XH series connector, B20B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH side entry
+0
+20
+20
+Connector_JST
+JST_XH_S2B-XH-A-1_1x02_P2.50mm_Horizontal
+JST XH series connector, S2B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH horizontal
+0
+2
+2
+Connector_JST
+JST_XH_S2B-XH-A_1x02_P2.50mm_Horizontal
+JST XH series connector, S2B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH horizontal
+0
+2
+2
+Connector_JST
+JST_XH_S3B-XH-A-1_1x03_P2.50mm_Horizontal
+JST XH series connector, S3B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH horizontal
+0
+3
+3
+Connector_JST
+JST_XH_S3B-XH-A_1x03_P2.50mm_Horizontal
+JST XH series connector, S3B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH horizontal
+0
+3
+3
+Connector_JST
+JST_XH_S4B-XH-A-1_1x04_P2.50mm_Horizontal
+JST XH series connector, S4B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH horizontal
+0
+4
+4
+Connector_JST
+JST_XH_S4B-XH-A_1x04_P2.50mm_Horizontal
+JST XH series connector, S4B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH horizontal
+0
+4
+4
+Connector_JST
+JST_XH_S5B-XH-A-1_1x05_P2.50mm_Horizontal
+JST XH series connector, S5B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH horizontal
+0
+5
+5
+Connector_JST
+JST_XH_S5B-XH-A_1x05_P2.50mm_Horizontal
+JST XH series connector, S5B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH horizontal
+0
+5
+5
+Connector_JST
+JST_XH_S6B-XH-A-1_1x06_P2.50mm_Horizontal
+JST XH series connector, S6B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH horizontal
+0
+6
+6
+Connector_JST
+JST_XH_S6B-XH-A_1x06_P2.50mm_Horizontal
+JST XH series connector, S6B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH horizontal
+0
+6
+6
+Connector_JST
+JST_XH_S7B-XH-A-1_1x07_P2.50mm_Horizontal
+JST XH series connector, S7B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH horizontal
+0
+7
+7
+Connector_JST
+JST_XH_S7B-XH-A_1x07_P2.50mm_Horizontal
+JST XH series connector, S7B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH horizontal
+0
+7
+7
+Connector_JST
+JST_XH_S8B-XH-A-1_1x08_P2.50mm_Horizontal
+JST XH series connector, S8B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH horizontal
+0
+8
+8
+Connector_JST
+JST_XH_S8B-XH-A_1x08_P2.50mm_Horizontal
+JST XH series connector, S8B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH horizontal
+0
+8
+8
+Connector_JST
+JST_XH_S9B-XH-A-1_1x09_P2.50mm_Horizontal
+JST XH series connector, S9B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH horizontal
+0
+9
+9
+Connector_JST
+JST_XH_S9B-XH-A_1x09_P2.50mm_Horizontal
+JST XH series connector, S9B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH horizontal
+0
+9
+9
+Connector_JST
+JST_XH_S10B-XH-A-1_1x10_P2.50mm_Horizontal
+JST XH series connector, S10B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH top entry
+0
+10
+10
+Connector_JST
+JST_XH_S10B-XH-A_1x10_P2.50mm_Horizontal
+JST XH series connector, S10B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH top entry
+0
+10
+10
+Connector_JST
+JST_XH_S11B-XH-A-1_1x11_P2.50mm_Horizontal
+JST XH series connector, S11B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH top entry
+0
+11
+11
+Connector_JST
+JST_XH_S11B-XH-A_1x11_P2.50mm_Horizontal
+JST XH series connector, S11B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH top entry
+0
+11
+11
+Connector_JST
+JST_XH_S12B-XH-A-1_1x12_P2.50mm_Horizontal
+JST XH series connector, S12B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH top entry
+0
+12
+12
+Connector_JST
+JST_XH_S12B-XH-A_1x12_P2.50mm_Horizontal
+JST XH series connector, S12B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH top entry
+0
+12
+12
+Connector_JST
+JST_XH_S13B-XH-A-1_1x13_P2.50mm_Horizontal
+JST XH series connector, S13B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH top entry
+0
+13
+13
+Connector_JST
+JST_XH_S13B-XH-A_1x13_P2.50mm_Horizontal
+JST XH series connector, S13B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH top entry
+0
+13
+13
+Connector_JST
+JST_XH_S14B-XH-A-1_1x14_P2.50mm_Horizontal
+JST XH series connector, S14B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH top entry
+0
+14
+14
+Connector_JST
+JST_XH_S14B-XH-A_1x14_P2.50mm_Horizontal
+JST XH series connector, S14B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH top entry
+0
+14
+14
+Connector_JST
+JST_XH_S15B-XH-A-1_1x15_P2.50mm_Horizontal
+JST XH series connector, S15B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH top entry
+0
+15
+15
+Connector_JST
+JST_XH_S15B-XH-A_1x15_P2.50mm_Horizontal
+JST XH series connector, S15B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH top entry
+0
+15
+15
+Connector_JST
+JST_XH_S16B-XH-A_1x16_P2.50mm_Horizontal
+JST XH series connector, S16B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator
+connector JST XH top entry
+0
+16
+16
+Connector_JST
+JST_ZE_B02B-ZESK-1D_1x02_P1.50mm_Vertical
+JST ZE series connector, B02B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry boss
+0
+2
+2
+Connector_JST
+JST_ZE_B03B-ZESK-1D_1x03_P1.50mm_Vertical
+JST ZE series connector, B03B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry boss
+0
+3
+3
+Connector_JST
+JST_ZE_B03B-ZESK-D_1x03_P1.50mm_Vertical
+JST ZE series connector, B03B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry
+0
+3
+3
+Connector_JST
+JST_ZE_B04B-ZESK-1D_1x04_P1.50mm_Vertical
+JST ZE series connector, B04B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry boss
+0
+4
+4
+Connector_JST
+JST_ZE_B04B-ZESK-D_1x04_P1.50mm_Vertical
+JST ZE series connector, B04B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry
+0
+4
+4
+Connector_JST
+JST_ZE_B05B-ZESK-1D_1x05_P1.50mm_Vertical
+JST ZE series connector, B05B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry boss
+0
+5
+5
+Connector_JST
+JST_ZE_B05B-ZESK-D_1x05_P1.50mm_Vertical
+JST ZE series connector, B05B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry
+0
+5
+5
+Connector_JST
+JST_ZE_B06B-ZESK-1D_1x06_P1.50mm_Vertical
+JST ZE series connector, B06B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry boss
+0
+6
+6
+Connector_JST
+JST_ZE_B06B-ZESK-D_1x06_P1.50mm_Vertical
+JST ZE series connector, B06B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry
+0
+6
+6
+Connector_JST
+JST_ZE_B07B-ZESK-1D_1x07_P1.50mm_Vertical
+JST ZE series connector, B07B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry boss
+0
+7
+7
+Connector_JST
+JST_ZE_B07B-ZESK-D_1x07_P1.50mm_Vertical
+JST ZE series connector, B07B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry
+0
+7
+7
+Connector_JST
+JST_ZE_B08B-ZESK-1D_1x08_P1.50mm_Vertical
+JST ZE series connector, B08B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry boss
+0
+8
+8
+Connector_JST
+JST_ZE_B08B-ZESK-D_1x08_P1.50mm_Vertical
+JST ZE series connector, B08B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry
+0
+8
+8
+Connector_JST
+JST_ZE_B09B-ZESK-1D_1x09_P1.50mm_Vertical
+JST ZE series connector, B09B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry boss
+0
+9
+9
+Connector_JST
+JST_ZE_B09B-ZESK-D_1x09_P1.50mm_Vertical
+JST ZE series connector, B09B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry
+0
+9
+9
+Connector_JST
+JST_ZE_B10B-ZESK-1D_1x10_P1.50mm_Vertical
+JST ZE series connector, B10B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry boss
+0
+10
+10
+Connector_JST
+JST_ZE_B10B-ZESK-D_1x10_P1.50mm_Vertical
+JST ZE series connector, B10B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry
+0
+10
+10
+Connector_JST
+JST_ZE_B11B-ZESK-1D_1x11_P1.50mm_Vertical
+JST ZE series connector, B11B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry boss
+0
+11
+11
+Connector_JST
+JST_ZE_B11B-ZESK-D_1x11_P1.50mm_Vertical
+JST ZE series connector, B11B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry
+0
+11
+11
+Connector_JST
+JST_ZE_B12B-ZESK-1D_1x12_P1.50mm_Vertical
+JST ZE series connector, B12B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry boss
+0
+12
+12
+Connector_JST
+JST_ZE_B12B-ZESK-D_1x12_P1.50mm_Vertical
+JST ZE series connector, B12B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry
+0
+12
+12
+Connector_JST
+JST_ZE_B13B-ZESK-1D_1x13_P1.50mm_Vertical
+JST ZE series connector, B13B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry boss
+0
+13
+13
+Connector_JST
+JST_ZE_B13B-ZESK-D_1x13_P1.50mm_Vertical
+JST ZE series connector, B13B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry
+0
+13
+13
+Connector_JST
+JST_ZE_B14B-ZESK-1D_1x14_P1.50mm_Vertical
+JST ZE series connector, B14B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry boss
+0
+14
+14
+Connector_JST
+JST_ZE_B14B-ZESK-D_1x14_P1.50mm_Vertical
+JST ZE series connector, B14B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry
+0
+14
+14
+Connector_JST
+JST_ZE_B15B-ZESK-1D_1x15_P1.50mm_Vertical
+JST ZE series connector, B15B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry boss
+0
+15
+15
+Connector_JST
+JST_ZE_B15B-ZESK-D_1x15_P1.50mm_Vertical
+JST ZE series connector, B15B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry
+0
+15
+15
+Connector_JST
+JST_ZE_B16B-ZESK-1D_1x16_P1.50mm_Vertical
+JST ZE series connector, B16B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry boss
+0
+16
+16
+Connector_JST
+JST_ZE_B16B-ZESK-D_1x16_P1.50mm_Vertical
+JST ZE series connector, B16B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE side entry
+0
+16
+16
+Connector_JST
+JST_ZE_BM02B-ZESS-TBT_1x02-1MP_P1.50mm_Vertical
+JST ZE series connector, BM02B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE vertical
+0
+4
+3
+Connector_JST
+JST_ZE_BM03B-ZESS-TBT_1x03-1MP_P1.50mm_Vertical
+JST ZE series connector, BM03B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE vertical
+0
+5
+4
+Connector_JST
+JST_ZE_BM04B-ZESS-TBT_1x04-1MP_P1.50mm_Vertical
+JST ZE series connector, BM04B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE vertical
+0
+6
+5
+Connector_JST
+JST_ZE_BM05B-ZESS-TBT_1x05-1MP_P1.50mm_Vertical
+JST ZE series connector, BM05B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE vertical
+0
+7
+6
+Connector_JST
+JST_ZE_BM06B-ZESS-TBT_1x06-1MP_P1.50mm_Vertical
+JST ZE series connector, BM06B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE vertical
+0
+8
+7
+Connector_JST
+JST_ZE_BM07B-ZESS-TBT_1x07-1MP_P1.50mm_Vertical
+JST ZE series connector, BM07B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE vertical
+0
+9
+8
+Connector_JST
+JST_ZE_BM08B-ZESS-TBT_1x08-1MP_P1.50mm_Vertical
+JST ZE series connector, BM08B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE vertical
+0
+10
+9
+Connector_JST
+JST_ZE_BM09B-ZESS-TBT_1x09-1MP_P1.50mm_Vertical
+JST ZE series connector, BM09B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE vertical
+0
+11
+10
+Connector_JST
+JST_ZE_BM10B-ZESS-TBT_1x10-1MP_P1.50mm_Vertical
+JST ZE series connector, BM10B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE vertical
+0
+12
+11
+Connector_JST
+JST_ZE_BM11B-ZESS-TBT_1x11-1MP_P1.50mm_Vertical
+JST ZE series connector, BM11B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE vertical
+0
+13
+12
+Connector_JST
+JST_ZE_BM12B-ZESS-TBT_1x12-1MP_P1.50mm_Vertical
+JST ZE series connector, BM12B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE vertical
+0
+14
+13
+Connector_JST
+JST_ZE_BM13B-ZESS-TBT_1x13-1MP_P1.50mm_Vertical
+JST ZE series connector, BM13B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE vertical
+0
+15
+14
+Connector_JST
+JST_ZE_BM14B-ZESS-TBT_1x14-1MP_P1.50mm_Vertical
+JST ZE series connector, BM14B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE vertical
+0
+16
+15
+Connector_JST
+JST_ZE_BM15B-ZESS-TBT_1x15-1MP_P1.50mm_Vertical
+JST ZE series connector, BM15B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE vertical
+0
+17
+16
+Connector_JST
+JST_ZE_BM16B-ZESS-TBT_1x16-1MP_P1.50mm_Vertical
+JST ZE series connector, BM16B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE vertical
+0
+18
+17
+Connector_JST
+JST_ZE_S02B-ZESK-2D_1x02_P1.50mm_Horizontal
+JST ZE series connector, S02B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE top entry
+0
+2
+2
+Connector_JST
+JST_ZE_S03B-ZESK-2D_1x03_P1.50mm_Horizontal
+JST ZE series connector, S03B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE top entry
+0
+3
+3
+Connector_JST
+JST_ZE_S04B-ZESK-2D_1x04_P1.50mm_Horizontal
+JST ZE series connector, S04B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE top entry
+0
+4
+4
+Connector_JST
+JST_ZE_S05B-ZESK-2D_1x05_P1.50mm_Horizontal
+JST ZE series connector, S05B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE top entry
+0
+5
+5
+Connector_JST
+JST_ZE_S06B-ZESK-2D_1x06_P1.50mm_Horizontal
+JST ZE series connector, S06B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE top entry
+0
+6
+6
+Connector_JST
+JST_ZE_S07B-ZESK-2D_1x07_P1.50mm_Horizontal
+JST ZE series connector, S07B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE top entry
+0
+7
+7
+Connector_JST
+JST_ZE_S08B-ZESK-2D_1x08_P1.50mm_Horizontal
+JST ZE series connector, S08B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE top entry
+0
+8
+8
+Connector_JST
+JST_ZE_S09B-ZESK-2D_1x09_P1.50mm_Horizontal
+JST ZE series connector, S09B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE top entry
+0
+9
+9
+Connector_JST
+JST_ZE_S10B-ZESK-2D_1x10_P1.50mm_Horizontal
+JST ZE series connector, S10B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE top entry
+0
+10
+10
+Connector_JST
+JST_ZE_S11B-ZESK-2D_1x11_P1.50mm_Horizontal
+JST ZE series connector, S11B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE top entry
+0
+11
+11
+Connector_JST
+JST_ZE_S12B-ZESK-2D_1x12_P1.50mm_Horizontal
+JST ZE series connector, S12B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE top entry
+0
+12
+12
+Connector_JST
+JST_ZE_S13B-ZESK-2D_1x13_P1.50mm_Horizontal
+JST ZE series connector, S13B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE top entry
+0
+13
+13
+Connector_JST
+JST_ZE_S14B-ZESK-2D_1x14_P1.50mm_Horizontal
+JST ZE series connector, S14B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE top entry
+0
+14
+14
+Connector_JST
+JST_ZE_S15B-ZESK-2D_1x15_P1.50mm_Horizontal
+JST ZE series connector, S15B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE top entry
+0
+15
+15
+Connector_JST
+JST_ZE_S16B-ZESK-2D_1x16_P1.50mm_Horizontal
+JST ZE series connector, S16B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE top entry
+0
+16
+16
+Connector_JST
+JST_ZE_SM02B-ZESS-TB_1x02-1MP_P1.50mm_Horizontal
+JST ZE series connector, SM02B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE horizontal
+0
+4
+3
+Connector_JST
+JST_ZE_SM03B-ZESS-TB_1x03-1MP_P1.50mm_Horizontal
+JST ZE series connector, SM03B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE horizontal
+0
+5
+4
+Connector_JST
+JST_ZE_SM04B-ZESS-TB_1x04-1MP_P1.50mm_Horizontal
+JST ZE series connector, SM04B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE horizontal
+0
+6
+5
+Connector_JST
+JST_ZE_SM05B-ZESS-TB_1x05-1MP_P1.50mm_Horizontal
+JST ZE series connector, SM05B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE horizontal
+0
+7
+6
+Connector_JST
+JST_ZE_SM06B-ZESS-TB_1x06-1MP_P1.50mm_Horizontal
+JST ZE series connector, SM06B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE horizontal
+0
+8
+7
+Connector_JST
+JST_ZE_SM07B-ZESS-TB_1x07-1MP_P1.50mm_Horizontal
+JST ZE series connector, SM07B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE horizontal
+0
+9
+8
+Connector_JST
+JST_ZE_SM08B-ZESS-TB_1x08-1MP_P1.50mm_Horizontal
+JST ZE series connector, SM08B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE horizontal
+0
+10
+9
+Connector_JST
+JST_ZE_SM09B-ZESS-TB_1x09-1MP_P1.50mm_Horizontal
+JST ZE series connector, SM09B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE horizontal
+0
+11
+10
+Connector_JST
+JST_ZE_SM10B-ZESS-TB_1x10-1MP_P1.50mm_Horizontal
+JST ZE series connector, SM10B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE horizontal
+0
+12
+11
+Connector_JST
+JST_ZE_SM11B-ZESS-TB_1x11-1MP_P1.50mm_Horizontal
+JST ZE series connector, SM11B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE horizontal
+0
+13
+12
+Connector_JST
+JST_ZE_SM12B-ZESS-TB_1x12-1MP_P1.50mm_Horizontal
+JST ZE series connector, SM12B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE horizontal
+0
+14
+13
+Connector_JST
+JST_ZE_SM13B-ZESS-TB_1x13-1MP_P1.50mm_Horizontal
+JST ZE series connector, SM13B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE horizontal
+0
+15
+14
+Connector_JST
+JST_ZE_SM14B-ZESS-TB_1x14-1MP_P1.50mm_Horizontal
+JST ZE series connector, SM14B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE horizontal
+0
+16
+15
+Connector_JST
+JST_ZE_SM15B-ZESS-TB_1x15-1MP_P1.50mm_Horizontal
+JST ZE series connector, SM15B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE horizontal
+0
+17
+16
+Connector_JST
+JST_ZE_SM16B-ZESS-TB_1x16-1MP_P1.50mm_Horizontal
+JST ZE series connector, SM16B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator
+connector JST ZE horizontal
+0
+18
+17
+Connector_Molex
+Molex_CLIK-Mate_502382-0270_1x02-1MP_P1.25mm_Vertical
+Molex CLIK-Mate series connector, 502382-0270 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+4
+3
+Connector_Molex
+Molex_CLIK-Mate_502382-0370_1x03-1MP_P1.25mm_Vertical
+Molex CLIK-Mate series connector, 502382-0370 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+5
+4
+Connector_Molex
+Molex_CLIK-Mate_502382-0470_1x04-1MP_P1.25mm_Vertical
+Molex CLIK-Mate series connector, 502382-0470 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+6
+5
+Connector_Molex
+Molex_CLIK-Mate_502382-0570_1x05-1MP_P1.25mm_Vertical
+Molex CLIK-Mate series connector, 502382-0570 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+7
+6
+Connector_Molex
+Molex_CLIK-Mate_502382-0670_1x06-1MP_P1.25mm_Vertical
+Molex CLIK-Mate series connector, 502382-0670 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+8
+7
+Connector_Molex
+Molex_CLIK-Mate_502382-0770_1x07-1MP_P1.25mm_Vertical
+Molex CLIK-Mate series connector, 502382-0770 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+9
+8
+Connector_Molex
+Molex_CLIK-Mate_502382-0870_1x08-1MP_P1.25mm_Vertical
+Molex CLIK-Mate series connector, 502382-0870 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+10
+9
+Connector_Molex
+Molex_CLIK-Mate_502382-0970_1x09-1MP_P1.25mm_Vertical
+Molex CLIK-Mate series connector, 502382-0970 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+11
+10
+Connector_Molex
+Molex_CLIK-Mate_502382-1070_1x10-1MP_P1.25mm_Vertical
+Molex CLIK-Mate series connector, 502382-1070 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+12
+11
+Connector_Molex
+Molex_CLIK-Mate_502382-1170_1x11-1MP_P1.25mm_Vertical
+Molex CLIK-Mate series connector, 502382-1170 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+13
+12
+Connector_Molex
+Molex_CLIK-Mate_502382-1270_1x12-1MP_P1.25mm_Vertical
+Molex CLIK-Mate series connector, 502382-1270 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+14
+13
+Connector_Molex
+Molex_CLIK-Mate_502382-1370_1x13-1MP_P1.25mm_Vertical
+Molex CLIK-Mate series connector, 502382-1370 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+15
+14
+Connector_Molex
+Molex_CLIK-Mate_502382-1470_1x14-1MP_P1.25mm_Vertical
+Molex CLIK-Mate series connector, 502382-1470 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+16
+15
+Connector_Molex
+Molex_CLIK-Mate_502382-1570_1x15-1MP_P1.25mm_Vertical
+Molex CLIK-Mate series connector, 502382-1570 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+17
+16
+Connector_Molex
+Molex_CLIK-Mate_502386-0270_1x02-1MP_P1.25mm_Horizontal
+Molex CLIK-Mate series connector, 502386-0270 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+4
+3
+Connector_Molex
+Molex_CLIK-Mate_502386-0370_1x03-1MP_P1.25mm_Horizontal
+Molex CLIK-Mate series connector, 502386-0370 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+5
+4
+Connector_Molex
+Molex_CLIK-Mate_502386-0470_1x04-1MP_P1.25mm_Horizontal
+Molex CLIK-Mate series connector, 502386-0470 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+6
+5
+Connector_Molex
+Molex_CLIK-Mate_502386-0570_1x05-1MP_P1.25mm_Horizontal
+Molex CLIK-Mate series connector, 502386-0570 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+7
+6
+Connector_Molex
+Molex_CLIK-Mate_502386-0670_1x06-1MP_P1.25mm_Horizontal
+Molex CLIK-Mate series connector, 502386-0670 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+8
+7
+Connector_Molex
+Molex_CLIK-Mate_502386-0770_1x07-1MP_P1.25mm_Horizontal
+Molex CLIK-Mate series connector, 502386-0770 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+9
+8
+Connector_Molex
+Molex_CLIK-Mate_502386-0870_1x08-1MP_P1.25mm_Horizontal
+Molex CLIK-Mate series connector, 502386-0870 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+10
+9
+Connector_Molex
+Molex_CLIK-Mate_502386-0970_1x09-1MP_P1.25mm_Horizontal
+Molex CLIK-Mate series connector, 502386-0970 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+11
+10
+Connector_Molex
+Molex_CLIK-Mate_502386-1070_1x10-1MP_P1.25mm_Horizontal
+Molex CLIK-Mate series connector, 502386-1070 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+12
+11
+Connector_Molex
+Molex_CLIK-Mate_502386-1170_1x11-1MP_P1.25mm_Horizontal
+Molex CLIK-Mate series connector, 502386-1170 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+13
+12
+Connector_Molex
+Molex_CLIK-Mate_502386-1270_1x12-1MP_P1.25mm_Horizontal
+Molex CLIK-Mate series connector, 502386-1270 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+14
+13
+Connector_Molex
+Molex_CLIK-Mate_502386-1370_1x13-1MP_P1.25mm_Horizontal
+Molex CLIK-Mate series connector, 502386-1370 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+15
+14
+Connector_Molex
+Molex_CLIK-Mate_502386-1470_1x14-1MP_P1.25mm_Horizontal
+Molex CLIK-Mate series connector, 502386-1470 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+16
+15
+Connector_Molex
+Molex_CLIK-Mate_502386-1570_1x15-1MP_P1.25mm_Horizontal
+Molex CLIK-Mate series connector, 502386-1570 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+17
+16
+Connector_Molex
+Molex_CLIK-Mate_502443-0270_1x02-1MP_P2.00mm_Vertical
+Molex CLIK-Mate series connector, 502443-0270 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+4
+3
+Connector_Molex
+Molex_CLIK-Mate_502443-0370_1x03-1MP_P2.00mm_Vertical
+Molex CLIK-Mate series connector, 502443-0370 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+5
+4
+Connector_Molex
+Molex_CLIK-Mate_502443-0470_1x04-1MP_P2.00mm_Vertical
+Molex CLIK-Mate series connector, 502443-0470 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+6
+5
+Connector_Molex
+Molex_CLIK-Mate_502443-0570_1x05-1MP_P2.00mm_Vertical
+Molex CLIK-Mate series connector, 502443-0570 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+7
+6
+Connector_Molex
+Molex_CLIK-Mate_502443-0670_1x06-1MP_P2.00mm_Vertical
+Molex CLIK-Mate series connector, 502443-0670 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+8
+7
+Connector_Molex
+Molex_CLIK-Mate_502443-0770_1x07-1MP_P2.00mm_Vertical
+Molex CLIK-Mate series connector, 502443-0770 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+9
+8
+Connector_Molex
+Molex_CLIK-Mate_502443-0870_1x08-1MP_P2.00mm_Vertical
+Molex CLIK-Mate series connector, 502443-0870 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+10
+9
+Connector_Molex
+Molex_CLIK-Mate_502443-0970_1x09-1MP_P2.00mm_Vertical
+Molex CLIK-Mate series connector, 502443-0970 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+11
+10
+Connector_Molex
+Molex_CLIK-Mate_502443-1270_1x12-1MP_P2.00mm_Vertical
+Molex CLIK-Mate series connector, 502443-1270 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+14
+13
+Connector_Molex
+Molex_CLIK-Mate_502443-1370_1x13-1MP_P2.00mm_Vertical
+Molex CLIK-Mate series connector, 502443-1370 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+15
+14
+Connector_Molex
+Molex_CLIK-Mate_502443-1470_1x14-1MP_P2.00mm_Vertical
+Molex CLIK-Mate series connector, 502443-1470 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+16
+15
+Connector_Molex
+Molex_CLIK-Mate_502443-1570_1x15-1MP_P2.00mm_Vertical
+Molex CLIK-Mate series connector, 502443-1570 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+17
+16
+Connector_Molex
+Molex_CLIK-Mate_502494-0270_1x02-1MP_P2.00mm_Horizontal
+Molex CLIK-Mate series connector, 502494-0270 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+4
+3
+Connector_Molex
+Molex_CLIK-Mate_502494-0370_1x03-1MP_P2.00mm_Horizontal
+Molex CLIK-Mate series connector, 502494-0370 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+5
+4
+Connector_Molex
+Molex_CLIK-Mate_502494-0470_1x04-1MP_P2.00mm_Horizontal
+Molex CLIK-Mate series connector, 502494-0470 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+6
+5
+Connector_Molex
+Molex_CLIK-Mate_502494-0670_1x06-1MP_P2.00mm_Horizontal
+Molex CLIK-Mate series connector, 502494-0670 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+8
+7
+Connector_Molex
+Molex_CLIK-Mate_502494-0870_1x08-1MP_P2.00mm_Horizontal
+Molex CLIK-Mate series connector, 502494-0870 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+10
+9
+Connector_Molex
+Molex_CLIK-Mate_502494-1070_1x10-1MP_P2.00mm_Horizontal
+Molex CLIK-Mate series connector, 502494-1070 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+12
+11
+Connector_Molex
+Molex_CLIK-Mate_502494-1270_1x12-1MP_P2.00mm_Horizontal
+Molex CLIK-Mate series connector, 502494-1270 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+14
+13
+Connector_Molex
+Molex_CLIK-Mate_502494-1370_1x13-1MP_P2.00mm_Horizontal
+Molex CLIK-Mate series connector, 502494-1370 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+15
+14
+Connector_Molex
+Molex_CLIK-Mate_502494-1470_1x14-1MP_P2.00mm_Horizontal
+Molex CLIK-Mate series connector, 502494-1470 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+16
+15
+Connector_Molex
+Molex_CLIK-Mate_502494-1570_1x15-1MP_P2.00mm_Horizontal
+Molex CLIK-Mate series connector, 502494-1570 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+17
+16
+Connector_Molex
+Molex_CLIK-Mate_502585-0270_1x02-1MP_P1.50mm_Horizontal
+Molex CLIK-Mate series connector, 502585-0270 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+4
+3
+Connector_Molex
+Molex_CLIK-Mate_502585-0370_1x03-1MP_P1.50mm_Horizontal
+Molex CLIK-Mate series connector, 502585-0370 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+5
+4
+Connector_Molex
+Molex_CLIK-Mate_502585-0470_1x04-1MP_P1.50mm_Horizontal
+Molex CLIK-Mate series connector, 502585-0470 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+6
+5
+Connector_Molex
+Molex_CLIK-Mate_502585-0570_1x05-1MP_P1.50mm_Horizontal
+Molex CLIK-Mate series connector, 502585-0570 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+7
+6
+Connector_Molex
+Molex_CLIK-Mate_502585-0670_1x06-1MP_P1.50mm_Horizontal
+Molex CLIK-Mate series connector, 502585-0670 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+8
+7
+Connector_Molex
+Molex_CLIK-Mate_502585-0770_1x07-1MP_P1.50mm_Horizontal
+Molex CLIK-Mate series connector, 502585-0770 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+9
+8
+Connector_Molex
+Molex_CLIK-Mate_502585-0870_1x08-1MP_P1.50mm_Horizontal
+Molex CLIK-Mate series connector, 502585-0870 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+10
+9
+Connector_Molex
+Molex_CLIK-Mate_502585-0970_1x09-1MP_P1.50mm_Horizontal
+Molex CLIK-Mate series connector, 502585-0970 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+11
+10
+Connector_Molex
+Molex_CLIK-Mate_502585-1070_1x10-1MP_P1.50mm_Horizontal
+Molex CLIK-Mate series connector, 502585-1070 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+12
+11
+Connector_Molex
+Molex_CLIK-Mate_502585-1170_1x11-1MP_P1.50mm_Horizontal
+Molex CLIK-Mate series connector, 502585-1170 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+13
+12
+Connector_Molex
+Molex_CLIK-Mate_502585-1270_1x12-1MP_P1.50mm_Horizontal
+Molex CLIK-Mate series connector, 502585-1270 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+14
+13
+Connector_Molex
+Molex_CLIK-Mate_502585-1370_1x13-1MP_P1.50mm_Horizontal
+Molex CLIK-Mate series connector, 502585-1370 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+15
+14
+Connector_Molex
+Molex_CLIK-Mate_502585-1470_1x14-1MP_P1.50mm_Horizontal
+Molex CLIK-Mate series connector, 502585-1470 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+16
+15
+Connector_Molex
+Molex_CLIK-Mate_502585-1570_1x15-1MP_P1.50mm_Horizontal
+Molex CLIK-Mate series connector, 502585-1570 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate top entry
+0
+17
+16
+Connector_Molex
+Molex_CLIK-Mate_505405-0270_1x02-1MP_P1.50mm_Vertical
+Molex CLIK-Mate series connector, 505405-0270 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+4
+3
+Connector_Molex
+Molex_CLIK-Mate_505405-0370_1x03-1MP_P1.50mm_Vertical
+Molex CLIK-Mate series connector, 505405-0370 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+5
+4
+Connector_Molex
+Molex_CLIK-Mate_505405-0470_1x04-1MP_P1.50mm_Vertical
+Molex CLIK-Mate series connector, 505405-0470 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+6
+5
+Connector_Molex
+Molex_CLIK-Mate_505405-0570_1x05-1MP_P1.50mm_Vertical
+Molex CLIK-Mate series connector, 505405-0570 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+7
+6
+Connector_Molex
+Molex_CLIK-Mate_505405-0670_1x06-1MP_P1.50mm_Vertical
+Molex CLIK-Mate series connector, 505405-0670 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+8
+7
+Connector_Molex
+Molex_CLIK-Mate_505405-0770_1x07-1MP_P1.50mm_Vertical
+Molex CLIK-Mate series connector, 505405-0770 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+9
+8
+Connector_Molex
+Molex_CLIK-Mate_505405-0870_1x08-1MP_P1.50mm_Vertical
+Molex CLIK-Mate series connector, 505405-0870 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+10
+9
+Connector_Molex
+Molex_CLIK-Mate_505405-0970_1x09-1MP_P1.50mm_Vertical
+Molex CLIK-Mate series connector, 505405-0970 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+11
+10
+Connector_Molex
+Molex_CLIK-Mate_505405-1070_1x10-1MP_P1.50mm_Vertical
+Molex CLIK-Mate series connector, 505405-1070 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+12
+11
+Connector_Molex
+Molex_CLIK-Mate_505405-1170_1x11-1MP_P1.50mm_Vertical
+Molex CLIK-Mate series connector, 505405-1170 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+13
+12
+Connector_Molex
+Molex_CLIK-Mate_505405-1270_1x12-1MP_P1.50mm_Vertical
+Molex CLIK-Mate series connector, 505405-1270 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+14
+13
+Connector_Molex
+Molex_CLIK-Mate_505405-1370_1x13-1MP_P1.50mm_Vertical
+Molex CLIK-Mate series connector, 505405-1370 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+15
+14
+Connector_Molex
+Molex_CLIK-Mate_505405-1470_1x14-1MP_P1.50mm_Vertical
+Molex CLIK-Mate series connector, 505405-1470 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+16
+15
+Connector_Molex
+Molex_CLIK-Mate_505405-1570_1x15-1MP_P1.50mm_Vertical
+Molex CLIK-Mate series connector, 505405-1570 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator
+connector Molex CLIK-Mate side entry
+0
+17
+16
+Connector_Molex
+Molex_KK-254_AE-6410-02A_1x02_P2.54mm_Vertical
+Molex KK-254 Interconnect System, old/engineering part number: AE-6410-02A example for new part number: 22-27-2021, 2 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-254 side entry
+0
+2
+2
+Connector_Molex
+Molex_KK-254_AE-6410-03A_1x03_P2.54mm_Vertical
+Molex KK-254 Interconnect System, old/engineering part number: AE-6410-03A example for new part number: 22-27-2031, 3 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-254 side entry
+0
+3
+3
+Connector_Molex
+Molex_KK-254_AE-6410-04A_1x04_P2.54mm_Vertical
+Molex KK-254 Interconnect System, old/engineering part number: AE-6410-04A example for new part number: 22-27-2041, 4 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-254 side entry
+0
+4
+4
+Connector_Molex
+Molex_KK-254_AE-6410-05A_1x05_P2.54mm_Vertical
+Molex KK-254 Interconnect System, old/engineering part number: AE-6410-05A example for new part number: 22-27-2051, 5 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-254 side entry
+0
+5
+5
+Connector_Molex
+Molex_KK-254_AE-6410-06A_1x06_P2.54mm_Vertical
+Molex KK-254 Interconnect System, old/engineering part number: AE-6410-06A example for new part number: 22-27-2061, 6 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-254 side entry
+0
+6
+6
+Connector_Molex
+Molex_KK-254_AE-6410-07A_1x07_P2.54mm_Vertical
+Molex KK-254 Interconnect System, old/engineering part number: AE-6410-07A example for new part number: 22-27-2071, 7 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-254 side entry
+0
+7
+7
+Connector_Molex
+Molex_KK-254_AE-6410-08A_1x08_P2.54mm_Vertical
+Molex KK-254 Interconnect System, old/engineering part number: AE-6410-08A example for new part number: 22-27-2081, 8 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-254 side entry
+0
+8
+8
+Connector_Molex
+Molex_KK-254_AE-6410-09A_1x09_P2.54mm_Vertical
+Molex KK-254 Interconnect System, old/engineering part number: AE-6410-09A example for new part number: 22-27-2091, 9 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-254 side entry
+0
+9
+9
+Connector_Molex
+Molex_KK-254_AE-6410-10A_1x10_P2.54mm_Vertical
+Molex KK-254 Interconnect System, old/engineering part number: AE-6410-10A example for new part number: 22-27-2101, 10 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-254 side entry
+0
+10
+10
+Connector_Molex
+Molex_KK-254_AE-6410-11A_1x11_P2.54mm_Vertical
+Molex KK-254 Interconnect System, old/engineering part number: AE-6410-11A example for new part number: 22-27-2111, 11 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-254 side entry
+0
+11
+11
+Connector_Molex
+Molex_KK-254_AE-6410-12A_1x12_P2.54mm_Vertical
+Molex KK-254 Interconnect System, old/engineering part number: AE-6410-12A example for new part number: 22-27-2121, 12 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-254 side entry
+0
+12
+12
+Connector_Molex
+Molex_KK-254_AE-6410-13A_1x13_P2.54mm_Vertical
+Molex KK-254 Interconnect System, old/engineering part number: AE-6410-13A example for new part number: 22-27-2131, 13 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-254 side entry
+0
+13
+13
+Connector_Molex
+Molex_KK-254_AE-6410-14A_1x14_P2.54mm_Vertical
+Molex KK-254 Interconnect System, old/engineering part number: AE-6410-14A example for new part number: 22-27-2141, 14 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-254 side entry
+0
+14
+14
+Connector_Molex
+Molex_KK-254_AE-6410-15A_1x15_P2.54mm_Vertical
+Molex KK-254 Interconnect System, old/engineering part number: AE-6410-15A example for new part number: 22-27-2151, 15 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-254 side entry
+0
+15
+15
+Connector_Molex
+Molex_KK-254_AE-6410-16A_1x16_P2.54mm_Vertical
+Molex KK-254 Interconnect System, old/engineering part number: AE-6410-16A example for new part number: 22-27-2161, 16 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-254 side entry
+0
+16
+16
+Connector_Molex
+Molex_KK-396_A-41791-0002_1x02_P3.96mm_Vertical
+Molex KK 396 Interconnect System, old/engineering part number: A-41791-0002 example for new part number: 26-60-4020, 2 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-396 vertical
+0
+2
+2
+Connector_Molex
+Molex_KK-396_A-41791-0003_1x03_P3.96mm_Vertical
+Molex KK 396 Interconnect System, old/engineering part number: A-41791-0003 example for new part number: 26-60-4030, 3 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-396 vertical
+0
+3
+3
+Connector_Molex
+Molex_KK-396_A-41791-0004_1x04_P3.96mm_Vertical
+Molex KK 396 Interconnect System, old/engineering part number: A-41791-0004 example for new part number: 26-60-4040, 4 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-396 vertical
+0
+4
+4
+Connector_Molex
+Molex_KK-396_A-41791-0005_1x05_P3.96mm_Vertical
+Molex KK 396 Interconnect System, old/engineering part number: A-41791-0005 example for new part number: 26-60-4050, 5 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-396 vertical
+0
+5
+5
+Connector_Molex
+Molex_KK-396_A-41791-0006_1x06_P3.96mm_Vertical
+Molex KK 396 Interconnect System, old/engineering part number: A-41791-0006 example for new part number: 26-60-4060, 6 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-396 vertical
+0
+6
+6
+Connector_Molex
+Molex_KK-396_A-41791-0007_1x07_P3.96mm_Vertical
+Molex KK 396 Interconnect System, old/engineering part number: A-41791-0007 example for new part number: 26-60-4070, 7 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-396 vertical
+0
+7
+7
+Connector_Molex
+Molex_KK-396_A-41791-0008_1x08_P3.96mm_Vertical
+Molex KK 396 Interconnect System, old/engineering part number: A-41791-0008 example for new part number: 26-60-4080, 8 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-396 vertical
+0
+8
+8
+Connector_Molex
+Molex_KK-396_A-41791-0009_1x09_P3.96mm_Vertical
+Molex KK 396 Interconnect System, old/engineering part number: A-41791-0009 example for new part number: 26-60-4090, 9 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-396 vertical
+0
+9
+9
+Connector_Molex
+Molex_KK-396_A-41791-0010_1x10_P3.96mm_Vertical
+Molex KK 396 Interconnect System, old/engineering part number: A-41791-0010 example for new part number: 26-60-4100, 10 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-396 vertical
+0
+10
+10
+Connector_Molex
+Molex_KK-396_A-41791-0011_1x11_P3.96mm_Vertical
+Molex KK 396 Interconnect System, old/engineering part number: A-41791-0011 example for new part number: 26-60-4110, 11 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-396 vertical
+0
+11
+11
+Connector_Molex
+Molex_KK-396_A-41791-0012_1x12_P3.96mm_Vertical
+Molex KK 396 Interconnect System, old/engineering part number: A-41791-0012 example for new part number: 26-60-4120, 12 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-396 vertical
+0
+12
+12
+Connector_Molex
+Molex_KK-396_A-41791-0013_1x13_P3.96mm_Vertical
+Molex KK 396 Interconnect System, old/engineering part number: A-41791-0013 example for new part number: 26-60-4130, 13 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-396 vertical
+0
+13
+13
+Connector_Molex
+Molex_KK-396_A-41791-0014_1x14_P3.96mm_Vertical
+Molex KK 396 Interconnect System, old/engineering part number: A-41791-0014 example for new part number: 26-60-4140, 14 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-396 vertical
+0
+14
+14
+Connector_Molex
+Molex_KK-396_A-41791-0015_1x15_P3.96mm_Vertical
+Molex KK 396 Interconnect System, old/engineering part number: A-41791-0015 example for new part number: 26-60-4150, 15 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-396 vertical
+0
+15
+15
+Connector_Molex
+Molex_KK-396_A-41791-0016_1x16_P3.96mm_Vertical
+Molex KK 396 Interconnect System, old/engineering part number: A-41791-0016 example for new part number: 26-60-4160, 16 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-396 vertical
+0
+16
+16
+Connector_Molex
+Molex_KK-396_A-41791-0017_1x17_P3.96mm_Vertical
+Molex KK 396 Interconnect System, old/engineering part number: A-41791-0017 example for new part number: 26-60-4170, 17 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-396 vertical
+0
+17
+17
+Connector_Molex
+Molex_KK-396_A-41791-0018_1x18_P3.96mm_Vertical
+Molex KK 396 Interconnect System, old/engineering part number: A-41791-0018 example for new part number: 26-60-4180, 18 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator
+connector Molex KK-396 vertical
+0
+18
+18
+Connector_Molex
+Molex_Mega-Fit_76825-0002_2x01_P5.70mm_Horizontal
+Molex Mega-Fit Power Connectors, 76825-0002 (compatible alternatives: 172064-0002, 172064-1002), 1 Pins per row (http://www.molex.com/pdm_docs/sd/1720640002_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mega-Fit top entry
+0
+2
+2
+Connector_Molex
+Molex_Mega-Fit_76825-0004_2x02_P5.70mm_Horizontal
+Molex Mega-Fit Power Connectors, 76825-0004 (compatible alternatives: 172064-0004, 172064-1004), 2 Pins per row (http://www.molex.com/pdm_docs/sd/1720640002_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mega-Fit top entry
+0
+4
+4
+Connector_Molex
+Molex_Mega-Fit_76825-0006_2x03_P5.70mm_Horizontal
+Molex Mega-Fit Power Connectors, 76825-0006 (compatible alternatives: 172064-0006, 172064-1006), 3 Pins per row (http://www.molex.com/pdm_docs/sd/1720640002_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mega-Fit top entry
+0
+6
+6
+Connector_Molex
+Molex_Mega-Fit_76825-0008_2x04_P5.70mm_Horizontal
+Molex Mega-Fit Power Connectors, 76825-0008 (compatible alternatives: 172064-0008, 172064-1008), 4 Pins per row (http://www.molex.com/pdm_docs/sd/1720640002_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mega-Fit top entry
+0
+8
+8
+Connector_Molex
+Molex_Mega-Fit_76825-0010_2x05_P5.70mm_Horizontal
+Molex Mega-Fit Power Connectors, 76825-0010 (compatible alternatives: 172064-0010, 172064-1010), 5 Pins per row (http://www.molex.com/pdm_docs/sd/1720640002_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mega-Fit top entry
+0
+10
+10
+Connector_Molex
+Molex_Mega-Fit_76825-0012_2x06_P5.70mm_Horizontal
+Molex Mega-Fit Power Connectors, 76825-0012 (compatible alternatives: 172064-0012, 172064-1012), 6 Pins per row (http://www.molex.com/pdm_docs/sd/1720640002_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mega-Fit top entry
+0
+12
+12
+Connector_Molex
+Molex_Mega-Fit_76829-0002_2x01_P5.70mm_Vertical
+Molex Mega-Fit Power Connectors, 76829-0002 (compatible alternatives: 172065-0002, 172065-1002), 1 Pins per row (http://www.molex.com/pdm_docs/sd/768290004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mega-Fit side entry
+0
+2
+2
+Connector_Molex
+Molex_Mega-Fit_76829-0004_2x02_P5.70mm_Vertical
+Molex Mega-Fit Power Connectors, 76829-0004 (compatible alternatives: 172065-0004, 172065-1004), 2 Pins per row (http://www.molex.com/pdm_docs/sd/768290004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mega-Fit side entry
+0
+4
+4
+Connector_Molex
+Molex_Mega-Fit_76829-0006_2x03_P5.70mm_Vertical
+Molex Mega-Fit Power Connectors, 76829-0006 (compatible alternatives: 172065-0006, 172065-1006), 3 Pins per row (http://www.molex.com/pdm_docs/sd/768290004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mega-Fit side entry
+0
+6
+6
+Connector_Molex
+Molex_Mega-Fit_76829-0008_2x04_P5.70mm_Vertical
+Molex Mega-Fit Power Connectors, 76829-0008 (compatible alternatives: 172065-0008, 172065-1008), 4 Pins per row (http://www.molex.com/pdm_docs/sd/768290004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mega-Fit side entry
+0
+8
+8
+Connector_Molex
+Molex_Mega-Fit_76829-0010_2x05_P5.70mm_Vertical
+Molex Mega-Fit Power Connectors, 76829-0010 (compatible alternatives: 172065-0010, 172065-1010), 5 Pins per row (http://www.molex.com/pdm_docs/sd/768290004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mega-Fit side entry
+0
+10
+10
+Connector_Molex
+Molex_Mega-Fit_76829-0012_2x06_P5.70mm_Vertical
+Molex Mega-Fit Power Connectors, 76829-0012 (compatible alternatives: 172065-0012, 172065-1012), 6 Pins per row (http://www.molex.com/pdm_docs/sd/768290004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mega-Fit side entry
+0
+12
+12
+Connector_Molex
+Molex_Mega-Fit_76829-0102_2x01_P5.70mm_Vertical
+Molex Mega-Fit Power Connectors, 76829-0102 (compatible alternatives: 172065-0202, 172065-0302), 1 Pins per row (http://www.molex.com/pdm_docs/sd/768290102_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mega-Fit side entry
+0
+2
+2
+Connector_Molex
+Molex_Mega-Fit_76829-0104_2x02_P5.70mm_Vertical
+Molex Mega-Fit Power Connectors, 76829-0104 (compatible alternatives: 172065-0204, 172065-0304), 2 Pins per row (http://www.molex.com/pdm_docs/sd/768290102_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mega-Fit side entry
+0
+4
+4
+Connector_Molex
+Molex_Mega-Fit_76829-0106_2x03_P5.70mm_Vertical
+Molex Mega-Fit Power Connectors, 76829-0106 (compatible alternatives: 172065-0206, 172065-0306), 3 Pins per row (http://www.molex.com/pdm_docs/sd/768290102_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mega-Fit side entry
+0
+6
+6
+Connector_Molex
+Molex_Mega-Fit_76829-0108_2x04_P5.70mm_Vertical
+Molex Mega-Fit Power Connectors, 76829-0108 (compatible alternatives: 172065-0208, 172065-0308), 4 Pins per row (http://www.molex.com/pdm_docs/sd/768290102_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mega-Fit side entry
+0
+8
+8
+Connector_Molex
+Molex_Mega-Fit_76829-0110_2x05_P5.70mm_Vertical
+Molex Mega-Fit Power Connectors, 76829-0110 (compatible alternatives: 172065-0210, 172065-0310), 5 Pins per row (http://www.molex.com/pdm_docs/sd/768290102_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mega-Fit side entry
+0
+10
+10
+Connector_Molex
+Molex_Mega-Fit_76829-0112_2x06_P5.70mm_Vertical
+Molex Mega-Fit Power Connectors, 76829-0112 (compatible alternatives: 172065-0212, 172065-0312), 6 Pins per row (http://www.molex.com/pdm_docs/sd/768290102_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mega-Fit side entry
+0
+12
+12
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0200_2x01_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-0200 (alternative finishes: 43045-020x), 1 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+2
+2
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0210_2x01-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-0210 (compatible alternatives: 43045-0211, 43045-0209), 1 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+4
+3
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0212_2x01_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-0212 (compatible alternatives: 43045-0213, 43045-0224), 1 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+2
+2
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0215_2x01_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-0215 (compatible alternatives: 43045-0216, 43045-0217), 1 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+2
+2
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0218_2x01-1MP_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-0218 (compatible alternatives: 43045-0219, 43045-0220), 1 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+4
+3
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0221_2x01-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-0221 (alternative finishes: 43045-022x), 1 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+4
+3
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0400_2x02_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-0400 (alternative finishes: 43045-040x), 2 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+4
+4
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0410_2x02-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-0410 (compatible alternatives: 43045-0411, 43045-0409), 2 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+6
+5
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0412_2x02_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-0412 (compatible alternatives: 43045-0413, 43045-0424), 2 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+4
+4
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0415_2x02_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-0415 (compatible alternatives: 43045-0416, 43045-0417), 2 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+4
+4
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0418_2x02-1MP_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-0418 (compatible alternatives: 43045-0419, 43045-0420), 2 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+6
+5
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0421_2x02-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-0421 (alternative finishes: 43045-042x), 2 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+6
+5
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0600_2x03_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-0600 (alternative finishes: 43045-060x), 3 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+6
+6
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0610_2x03-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-0610 (compatible alternatives: 43045-0611, 43045-0609), 3 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+8
+7
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0612_2x03_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-0612 (compatible alternatives: 43045-0613, 43045-0624), 3 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+6
+6
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0615_2x03_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-0615 (compatible alternatives: 43045-0616, 43045-0617), 3 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+6
+6
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0618_2x03-1MP_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-0618 (compatible alternatives: 43045-0619, 43045-0620), 3 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+8
+7
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0621_2x03-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-0621 (alternative finishes: 43045-062x), 3 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+8
+7
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0800_2x04_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-0800 (alternative finishes: 43045-080x), 4 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+8
+8
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0810_2x04-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-0810 (compatible alternatives: 43045-0811, 43045-0809), 4 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+10
+9
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0812_2x04_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-0812 (compatible alternatives: 43045-0813, 43045-0824), 4 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+8
+8
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0815_2x04_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-0815 (compatible alternatives: 43045-0816, 43045-0817), 4 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+8
+8
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0818_2x04-1MP_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-0818 (compatible alternatives: 43045-0819, 43045-0820), 4 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+10
+9
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-0821_2x04-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-0821 (alternative finishes: 43045-082x), 4 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+10
+9
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1000_2x05_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-1000 (alternative finishes: 43045-100x), 5 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+10
+10
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1010_2x05-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-1010 (compatible alternatives: 43045-1011, 43045-1009), 5 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+12
+11
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1012_2x05_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-1012 (compatible alternatives: 43045-1013, 43045-1024), 5 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+10
+10
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1015_2x05_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-1015 (compatible alternatives: 43045-1016, 43045-1017), 5 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+10
+10
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1018_2x05-1MP_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-1018 (compatible alternatives: 43045-1019, 43045-1020), 5 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+12
+11
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1021_2x05-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-1021 (alternative finishes: 43045-102x), 5 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+12
+11
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1200_2x06_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-1200 (alternative finishes: 43045-120x), 6 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+12
+12
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1210_2x06-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-1210 (compatible alternatives: 43045-1211, 43045-1209), 6 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+14
+13
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1212_2x06_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-1212 (compatible alternatives: 43045-1213, 43045-1224), 6 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+12
+12
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1215_2x06_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-1215 (compatible alternatives: 43045-1216, 43045-1217), 6 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+12
+12
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1218_2x06-1MP_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-1218 (compatible alternatives: 43045-1219, 43045-1220), 6 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+14
+13
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1221_2x06-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-1221 (alternative finishes: 43045-122x), 6 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+14
+13
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1400_2x07_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-1400 (alternative finishes: 43045-140x), 7 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+14
+14
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1410_2x07-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-1410 (compatible alternatives: 43045-1411, 43045-1409), 7 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+16
+15
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1412_2x07_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-1412 (compatible alternatives: 43045-1413, 43045-1424), 7 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+14
+14
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1415_2x07_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-1415 (compatible alternatives: 43045-1416, 43045-1417), 7 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+14
+14
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1418_2x07-1MP_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-1418 (compatible alternatives: 43045-1419, 43045-1420), 7 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+16
+15
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1421_2x07-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-1421 (alternative finishes: 43045-142x), 7 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+16
+15
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1600_2x08_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-1600 (alternative finishes: 43045-160x), 8 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+16
+16
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1610_2x08-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-1610 (compatible alternatives: 43045-1611, 43045-1609), 8 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+18
+17
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1612_2x08_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-1612 (compatible alternatives: 43045-1613, 43045-1624), 8 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+16
+16
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1615_2x08_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-1615 (compatible alternatives: 43045-1616, 43045-1617), 8 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+16
+16
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1618_2x08-1MP_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-1618 (compatible alternatives: 43045-1619, 43045-1620), 8 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+18
+17
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1621_2x08-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-1621 (alternative finishes: 43045-162x), 8 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+18
+17
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1800_2x09_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-1800 (alternative finishes: 43045-180x), 9 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+18
+18
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1810_2x09-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-1810 (compatible alternatives: 43045-1811, 43045-1809), 9 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+20
+19
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1812_2x09_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-1812 (compatible alternatives: 43045-1813, 43045-1824), 9 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+18
+18
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1815_2x09_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-1815 (compatible alternatives: 43045-1816, 43045-1817), 9 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+18
+18
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1818_2x09-1MP_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-1818 (compatible alternatives: 43045-1819, 43045-1820), 9 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+20
+19
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-1821_2x09-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-1821 (alternative finishes: 43045-182x), 9 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+20
+19
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-2000_2x10_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-2000 (alternative finishes: 43045-200x), 10 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+20
+20
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-2010_2x10-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-2010 (compatible alternatives: 43045-2011, 43045-2009), 10 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+22
+21
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-2012_2x10_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-2012 (compatible alternatives: 43045-2013, 43045-2024), 10 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+20
+20
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-2015_2x10_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-2015 (compatible alternatives: 43045-2016, 43045-2017), 10 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+20
+20
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-2018_2x10-1MP_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-2018 (compatible alternatives: 43045-2019, 43045-2020), 10 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+22
+21
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-2021_2x10-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-2021 (alternative finishes: 43045-202x), 10 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+22
+21
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-2200_2x11_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-2200 (alternative finishes: 43045-220x), 11 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+22
+22
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-2210_2x11-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-2210 (compatible alternatives: 43045-2211, 43045-2209), 11 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+24
+23
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-2212_2x11_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-2212 (compatible alternatives: 43045-2213, 43045-2224), 11 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+22
+22
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-2215_2x11_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-2215 (compatible alternatives: 43045-2216, 43045-2217), 11 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+22
+22
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-2218_2x11-1MP_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-2218 (compatible alternatives: 43045-2219, 43045-2220), 11 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+24
+23
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-2221_2x11-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-2221 (alternative finishes: 43045-222x), 11 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+24
+23
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-2400_2x12_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-2400 (alternative finishes: 43045-240x), 12 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+24
+24
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-2410_2x12-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-2410 (compatible alternatives: 43045-2411, 43045-2409), 12 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+26
+25
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-2412_2x12_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-2412 (compatible alternatives: 43045-2413, 43045-2424), 12 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+24
+24
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-2415_2x12_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-2415 (compatible alternatives: 43045-2416, 43045-2417), 12 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+24
+24
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-2418_2x12-1MP_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43045-2418 (compatible alternatives: 43045-2419, 43045-2420), 12 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 side entry
+0
+26
+25
+Connector_Molex
+Molex_Micro-Fit_3.0_43045-2421_2x12-1MP_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43045-2421 (alternative finishes: 43045-242x), 12 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 horizontal
+0
+26
+25
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-0200_1x02_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43650-0200 (compatible alternatives: 43650-0201, 43650-0202), 2 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+2
+2
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-0215_1x02_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43650-0215 (compatible alternatives: 43650-0216, 43650-0217), 2 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 vertical
+0
+2
+2
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-0300_1x03_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43650-0300 (compatible alternatives: 43650-0301, 43650-0302), 3 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+3
+3
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-0315_1x03_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43650-0315 (compatible alternatives: 43650-0316, 43650-0317), 3 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 vertical
+0
+3
+3
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-0400_1x04_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43650-0400 (compatible alternatives: 43650-0401, 43650-0402), 4 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+4
+4
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-0415_1x04_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43650-0415 (compatible alternatives: 43650-0416, 43650-0417), 4 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 vertical
+0
+4
+4
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-0500_1x05_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43650-0500 (compatible alternatives: 43650-0501, 43650-0502), 5 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+5
+5
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-0515_1x05_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43650-0515 (compatible alternatives: 43650-0516, 43650-0517), 5 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 vertical
+0
+5
+5
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-0600_1x06_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43650-0600 (compatible alternatives: 43650-0601, 43650-0602), 6 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+6
+6
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-0615_1x06_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43650-0615 (compatible alternatives: 43650-0616, 43650-0617), 6 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 vertical
+0
+6
+6
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-0700_1x07_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43650-0700 (compatible alternatives: 43650-0701, 43650-0702), 7 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+7
+7
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-0715_1x07_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43650-0715 (compatible alternatives: 43650-0716, 43650-0717), 7 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 vertical
+0
+7
+7
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-0800_1x08_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43650-0800 (compatible alternatives: 43650-0801, 43650-0802), 8 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+8
+8
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-0815_1x08_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43650-0815 (compatible alternatives: 43650-0816, 43650-0817), 8 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 vertical
+0
+8
+8
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-0900_1x09_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43650-0900 (compatible alternatives: 43650-0901, 43650-0902), 9 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+9
+9
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-0915_1x09_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43650-0915 (compatible alternatives: 43650-0916, 43650-0917), 9 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 vertical
+0
+9
+9
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-1000_1x10_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43650-1000 (compatible alternatives: 43650-1001, 43650-1002), 10 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+10
+10
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-1015_1x10_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43650-1015 (compatible alternatives: 43650-1016, 43650-1017), 10 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 vertical
+0
+10
+10
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-1100_1x11_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43650-1100 (compatible alternatives: 43650-1101, 43650-1102), 11 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+11
+11
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-1115_1x11_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43650-1115 (compatible alternatives: 43650-1116, 43650-1117), 11 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 vertical
+0
+11
+11
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-1200_1x12_P3.00mm_Horizontal
+Molex Micro-Fit 3.0 Connector System, 43650-1200 (compatible alternatives: 43650-1201, 43650-1202), 12 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 top entry
+0
+12
+12
+Connector_Molex
+Molex_Micro-Fit_3.0_43650-1215_1x12_P3.00mm_Vertical
+Molex Micro-Fit 3.0 Connector System, 43650-1215 (compatible alternatives: 43650-1216, 43650-1217), 12 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Fit_3.0 vertical
+0
+12
+12
+Connector_Molex
+Molex_Micro-Latch_53253-0270_1x02_P2.00mm_Vertical
+Molex Micro-Latch Wire-to-Board Connector System, 53253-0270 (compatible alternatives: 53253-0250), 2 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch side entry
+0
+2
+2
+Connector_Molex
+Molex_Micro-Latch_53253-0370_1x03_P2.00mm_Vertical
+Molex Micro-Latch Wire-to-Board Connector System, 53253-0370 (compatible alternatives: 53253-0350), 3 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch side entry
+0
+3
+3
+Connector_Molex
+Molex_Micro-Latch_53253-0470_1x04_P2.00mm_Vertical
+Molex Micro-Latch Wire-to-Board Connector System, 53253-0470 (compatible alternatives: 53253-0450), 4 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch side entry
+0
+4
+4
+Connector_Molex
+Molex_Micro-Latch_53253-0570_1x05_P2.00mm_Vertical
+Molex Micro-Latch Wire-to-Board Connector System, 53253-0570 (compatible alternatives: 53253-0550), 5 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch side entry
+0
+5
+5
+Connector_Molex
+Molex_Micro-Latch_53253-0670_1x06_P2.00mm_Vertical
+Molex Micro-Latch Wire-to-Board Connector System, 53253-0670 (compatible alternatives: 53253-0650), 6 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch side entry
+0
+6
+6
+Connector_Molex
+Molex_Micro-Latch_53253-0770_1x07_P2.00mm_Vertical
+Molex Micro-Latch Wire-to-Board Connector System, 53253-0770 (compatible alternatives: 53253-0750), 7 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch side entry
+0
+7
+7
+Connector_Molex
+Molex_Micro-Latch_53253-0870_1x08_P2.00mm_Vertical
+Molex Micro-Latch Wire-to-Board Connector System, 53253-0870 (compatible alternatives: 53253-0850), 8 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch side entry
+0
+8
+8
+Connector_Molex
+Molex_Micro-Latch_53253-0970_1x09_P2.00mm_Vertical
+Molex Micro-Latch Wire-to-Board Connector System, 53253-0970 (compatible alternatives: 53253-0950), 9 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch side entry
+0
+9
+9
+Connector_Molex
+Molex_Micro-Latch_53253-1070_1x10_P2.00mm_Vertical
+Molex Micro-Latch Wire-to-Board Connector System, 53253-1070 (compatible alternatives: 53253-1050), 10 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch side entry
+0
+10
+10
+Connector_Molex
+Molex_Micro-Latch_53253-1170_1x11_P2.00mm_Vertical
+Molex Micro-Latch Wire-to-Board Connector System, 53253-1170 (compatible alternatives: 53253-1150), 11 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch side entry
+0
+11
+11
+Connector_Molex
+Molex_Micro-Latch_53253-1270_1x12_P2.00mm_Vertical
+Molex Micro-Latch Wire-to-Board Connector System, 53253-1270 (compatible alternatives: 53253-1250), 12 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch side entry
+0
+12
+12
+Connector_Molex
+Molex_Micro-Latch_53253-1370_1x13_P2.00mm_Vertical
+Molex Micro-Latch Wire-to-Board Connector System, 53253-1370 (compatible alternatives: 53253-1350), 13 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch side entry
+0
+13
+13
+Connector_Molex
+Molex_Micro-Latch_53253-1470_1x14_P2.00mm_Vertical
+Molex Micro-Latch Wire-to-Board Connector System, 53253-1470 (compatible alternatives: 53253-1450), 14 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch side entry
+0
+14
+14
+Connector_Molex
+Molex_Micro-Latch_53253-1570_1x15_P2.00mm_Vertical
+Molex Micro-Latch Wire-to-Board Connector System, 53253-1570 (compatible alternatives: 53253-1550), 15 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch side entry
+0
+15
+15
+Connector_Molex
+Molex_Micro-Latch_53254-0270_1x02_P2.00mm_Horizontal
+Molex Micro-Latch Wire-to-Board Connector System, 53254-0270 (compatible alternatives: 53254-0250), 2 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch top entry
+0
+2
+2
+Connector_Molex
+Molex_Micro-Latch_53254-0370_1x03_P2.00mm_Horizontal
+Molex Micro-Latch Wire-to-Board Connector System, 53254-0370 (compatible alternatives: 53254-0350), 3 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch top entry
+0
+3
+3
+Connector_Molex
+Molex_Micro-Latch_53254-0470_1x04_P2.00mm_Horizontal
+Molex Micro-Latch Wire-to-Board Connector System, 53254-0470 (compatible alternatives: 53254-0450), 4 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch top entry
+0
+4
+4
+Connector_Molex
+Molex_Micro-Latch_53254-0570_1x05_P2.00mm_Horizontal
+Molex Micro-Latch Wire-to-Board Connector System, 53254-0570 (compatible alternatives: 53254-0550), 5 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch top entry
+0
+5
+5
+Connector_Molex
+Molex_Micro-Latch_53254-0670_1x06_P2.00mm_Horizontal
+Molex Micro-Latch Wire-to-Board Connector System, 53254-0670 (compatible alternatives: 53254-0650), 6 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch top entry
+0
+6
+6
+Connector_Molex
+Molex_Micro-Latch_53254-0770_1x07_P2.00mm_Horizontal
+Molex Micro-Latch Wire-to-Board Connector System, 53254-0770 (compatible alternatives: 53254-0750), 7 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch top entry
+0
+7
+7
+Connector_Molex
+Molex_Micro-Latch_53254-0870_1x08_P2.00mm_Horizontal
+Molex Micro-Latch Wire-to-Board Connector System, 53254-0870 (compatible alternatives: 53254-0850), 8 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch top entry
+0
+8
+8
+Connector_Molex
+Molex_Micro-Latch_53254-0970_1x09_P2.00mm_Horizontal
+Molex Micro-Latch Wire-to-Board Connector System, 53254-0970 (compatible alternatives: 53254-0950), 9 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch top entry
+0
+9
+9
+Connector_Molex
+Molex_Micro-Latch_53254-1070_1x10_P2.00mm_Horizontal
+Molex Micro-Latch Wire-to-Board Connector System, 53254-1070 (compatible alternatives: 53254-1050), 10 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch top entry
+0
+10
+10
+Connector_Molex
+Molex_Micro-Latch_53254-1170_1x11_P2.00mm_Horizontal
+Molex Micro-Latch Wire-to-Board Connector System, 53254-1170 (compatible alternatives: 53254-1150), 11 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch top entry
+0
+11
+11
+Connector_Molex
+Molex_Micro-Latch_53254-1270_1x12_P2.00mm_Horizontal
+Molex Micro-Latch Wire-to-Board Connector System, 53254-1270 (compatible alternatives: 53254-1250), 12 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch top entry
+0
+12
+12
+Connector_Molex
+Molex_Micro-Latch_53254-1370_1x13_P2.00mm_Horizontal
+Molex Micro-Latch Wire-to-Board Connector System, 53254-1370 (compatible alternatives: 53254-1350), 13 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch top entry
+0
+13
+13
+Connector_Molex
+Molex_Micro-Latch_53254-1470_1x14_P2.00mm_Horizontal
+Molex Micro-Latch Wire-to-Board Connector System, 53254-1470 (compatible alternatives: 53254-1450), 14 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch top entry
+0
+14
+14
+Connector_Molex
+Molex_Micro-Latch_53254-1570_1x15_P2.00mm_Horizontal
+Molex Micro-Latch Wire-to-Board Connector System, 53254-1570 (compatible alternatives: 53254-1550), 15 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator
+connector Molex Micro-Latch top entry
+0
+15
+15
+Connector_Molex
+Molex_MicroClasp_55932-0210_1x02_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-0210, with PCB locator, 2 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+2
+2
+Connector_Molex
+Molex_MicroClasp_55932-0230_1x02_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-0230, 2 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+2
+2
+Connector_Molex
+Molex_MicroClasp_55932-0310_1x03_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-0310, with PCB locator, 3 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+3
+3
+Connector_Molex
+Molex_MicroClasp_55932-0330_1x03_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-0330, 3 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+3
+3
+Connector_Molex
+Molex_MicroClasp_55932-0410_1x04_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-0410, with PCB locator, 4 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+4
+4
+Connector_Molex
+Molex_MicroClasp_55932-0430_1x04_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-0430, 4 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+4
+4
+Connector_Molex
+Molex_MicroClasp_55932-0510_1x05_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-0510, with PCB locator, 5 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+5
+5
+Connector_Molex
+Molex_MicroClasp_55932-0530_1x05_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-0530, 5 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+5
+5
+Connector_Molex
+Molex_MicroClasp_55932-0610_1x06_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-0610, with PCB locator, 6 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+6
+6
+Connector_Molex
+Molex_MicroClasp_55932-0630_1x06_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-0630, 6 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+6
+6
+Connector_Molex
+Molex_MicroClasp_55932-0710_1x07_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-0710, with PCB locator, 7 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+7
+7
+Connector_Molex
+Molex_MicroClasp_55932-0730_1x07_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-0730, 7 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+7
+7
+Connector_Molex
+Molex_MicroClasp_55932-0810_1x08_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-0810, with PCB locator, 8 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+8
+8
+Connector_Molex
+Molex_MicroClasp_55932-0830_1x08_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-0830, 8 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+8
+8
+Connector_Molex
+Molex_MicroClasp_55932-0910_1x09_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-0910, with PCB locator, 9 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+9
+9
+Connector_Molex
+Molex_MicroClasp_55932-0930_1x09_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-0930, 9 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+9
+9
+Connector_Molex
+Molex_MicroClasp_55932-1010_1x10_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-1010, with PCB locator, 10 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+10
+10
+Connector_Molex
+Molex_MicroClasp_55932-1030_1x10_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-1030, 10 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+10
+10
+Connector_Molex
+Molex_MicroClasp_55932-1110_1x11_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-1110, with PCB locator, 11 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+11
+11
+Connector_Molex
+Molex_MicroClasp_55932-1130_1x11_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-1130, 11 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+11
+11
+Connector_Molex
+Molex_MicroClasp_55932-1210_1x12_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-1210, with PCB locator, 12 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+12
+12
+Connector_Molex
+Molex_MicroClasp_55932-1230_1x12_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-1230, 12 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+12
+12
+Connector_Molex
+Molex_MicroClasp_55932-1310_1x13_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-1310, with PCB locator, 13 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+13
+13
+Connector_Molex
+Molex_MicroClasp_55932-1330_1x13_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-1330, 13 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+13
+13
+Connector_Molex
+Molex_MicroClasp_55932-1410_1x14_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-1410, with PCB locator, 14 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+14
+14
+Connector_Molex
+Molex_MicroClasp_55932-1430_1x14_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-1430, 14 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+14
+14
+Connector_Molex
+Molex_MicroClasp_55932-1510_1x15_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-1510, with PCB locator, 15 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+15
+15
+Connector_Molex
+Molex_MicroClasp_55932-1530_1x15_P2.00mm_Vertical
+Molex MicroClasp Wire-to-Board System, 55932-1530, 15 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp side entry
+0
+15
+15
+Connector_Molex
+Molex_MicroClasp_55935-0210_1x02_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-0210, with PCB locator, 2 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+2
+2
+Connector_Molex
+Molex_MicroClasp_55935-0230_1x02_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-0230, 2 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+2
+2
+Connector_Molex
+Molex_MicroClasp_55935-0310_1x03_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-0310, with PCB locator, 3 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+3
+3
+Connector_Molex
+Molex_MicroClasp_55935-0330_1x03_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-0330, 3 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+3
+3
+Connector_Molex
+Molex_MicroClasp_55935-0410_1x04_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-0410, with PCB locator, 4 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+4
+4
+Connector_Molex
+Molex_MicroClasp_55935-0430_1x04_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-0430, 4 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+4
+4
+Connector_Molex
+Molex_MicroClasp_55935-0510_1x05_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-0510, with PCB locator, 5 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+5
+5
+Connector_Molex
+Molex_MicroClasp_55935-0530_1x05_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-0530, 5 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+5
+5
+Connector_Molex
+Molex_MicroClasp_55935-0610_1x06_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-0610, with PCB locator, 6 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+6
+6
+Connector_Molex
+Molex_MicroClasp_55935-0630_1x06_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-0630, 6 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+6
+6
+Connector_Molex
+Molex_MicroClasp_55935-0710_1x07_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-0710, with PCB locator, 7 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+7
+7
+Connector_Molex
+Molex_MicroClasp_55935-0730_1x07_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-0730, 7 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+7
+7
+Connector_Molex
+Molex_MicroClasp_55935-0810_1x08_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-0810, with PCB locator, 8 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+8
+8
+Connector_Molex
+Molex_MicroClasp_55935-0830_1x08_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-0830, 8 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+8
+8
+Connector_Molex
+Molex_MicroClasp_55935-0910_1x09_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-0910, with PCB locator, 9 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+9
+9
+Connector_Molex
+Molex_MicroClasp_55935-0930_1x09_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-0930, 9 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+9
+9
+Connector_Molex
+Molex_MicroClasp_55935-1010_1x10_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-1010, with PCB locator, 10 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+10
+10
+Connector_Molex
+Molex_MicroClasp_55935-1030_1x10_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-1030, 10 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+10
+10
+Connector_Molex
+Molex_MicroClasp_55935-1110_1x11_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-1110, with PCB locator, 11 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+11
+11
+Connector_Molex
+Molex_MicroClasp_55935-1130_1x11_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-1130, 11 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+11
+11
+Connector_Molex
+Molex_MicroClasp_55935-1210_1x12_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-1210, with PCB locator, 12 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+12
+12
+Connector_Molex
+Molex_MicroClasp_55935-1230_1x12_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-1230, 12 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+12
+12
+Connector_Molex
+Molex_MicroClasp_55935-1310_1x13_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-1310, with PCB locator, 13 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+13
+13
+Connector_Molex
+Molex_MicroClasp_55935-1330_1x13_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-1330, 13 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+13
+13
+Connector_Molex
+Molex_MicroClasp_55935-1410_1x14_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-1410, with PCB locator, 14 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+14
+14
+Connector_Molex
+Molex_MicroClasp_55935-1430_1x14_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-1430, 14 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+14
+14
+Connector_Molex
+Molex_MicroClasp_55935-1510_1x15_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-1510, with PCB locator, 15 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+15
+15
+Connector_Molex
+Molex_MicroClasp_55935-1530_1x15_P2.00mm_Horizontal
+Molex MicroClasp Wire-to-Board System, 55935-1530, 15 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator
+connector Molex MicroClasp horizontal
+0
+15
+15
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-02A2_2x01_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-02A2, example for new mpn: 39-28-902x, 1 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entryplastic_peg
+0
+2
+2
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-02A_2x01_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-02A, example for new mpn: 39-28-x02x, 1 Pins per row, Mounting:  (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entry
+0
+2
+2
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-04A2_2x02_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-04A2, example for new mpn: 39-28-904x, 2 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entryplastic_peg
+0
+4
+4
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-04A_2x02_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-04A, example for new mpn: 39-28-x04x, 2 Pins per row, Mounting:  (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entry
+0
+4
+4
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-06A2_2x03_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-06A2, example for new mpn: 39-28-906x, 3 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entryplastic_peg
+0
+6
+6
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-06A_2x03_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-06A, example for new mpn: 39-28-x06x, 3 Pins per row, Mounting:  (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entry
+0
+6
+6
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-08A2_2x04_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-08A2, example for new mpn: 39-28-908x, 4 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entryplastic_peg
+0
+8
+8
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-08A_2x04_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-08A, example for new mpn: 39-28-x08x, 4 Pins per row, Mounting:  (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entry
+0
+8
+8
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-10A2_2x05_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-10A2, example for new mpn: 39-28-910x, 5 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entryplastic_peg
+0
+10
+10
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-10A_2x05_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-10A, example for new mpn: 39-28-x10x, 5 Pins per row, Mounting:  (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entry
+0
+10
+10
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-12A2_2x06_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-12A2, example for new mpn: 39-28-912x, 6 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entryplastic_peg
+0
+12
+12
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-12A_2x06_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-12A, example for new mpn: 39-28-x12x, 6 Pins per row, Mounting:  (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entry
+0
+12
+12
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-14A2_2x07_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-14A2, example for new mpn: 39-28-914x, 7 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entryplastic_peg
+0
+14
+14
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-14A_2x07_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-14A, example for new mpn: 39-28-x14x, 7 Pins per row, Mounting:  (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entry
+0
+14
+14
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-16A2_2x08_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-16A2, example for new mpn: 39-28-916x, 8 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entryplastic_peg
+0
+16
+16
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-16A_2x08_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-16A, example for new mpn: 39-28-x16x, 8 Pins per row, Mounting:  (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entry
+0
+16
+16
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-18A2_2x09_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-18A2, example for new mpn: 39-28-918x, 9 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entryplastic_peg
+0
+18
+18
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-18A_2x09_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-18A, example for new mpn: 39-28-x18x, 9 Pins per row, Mounting:  (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entry
+0
+18
+18
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-20A2_2x10_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-20A2, example for new mpn: 39-28-920x, 10 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entryplastic_peg
+0
+20
+20
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-20A_2x10_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-20A, example for new mpn: 39-28-x20x, 10 Pins per row, Mounting:  (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entry
+0
+20
+20
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-22A2_2x11_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-22A2, example for new mpn: 39-28-922x, 11 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entryplastic_peg
+0
+22
+22
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-22A_2x11_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-22A, example for new mpn: 39-28-x22x, 11 Pins per row, Mounting:  (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entry
+0
+22
+22
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-24A2_2x12_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-24A2, example for new mpn: 39-28-924x, 12 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entryplastic_peg
+0
+24
+24
+Connector_Molex
+Molex_Mini-Fit_Jr_5566-24A_2x12_P4.20mm_Vertical
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-24A, example for new mpn: 39-28-x24x, 12 Pins per row, Mounting:  (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr side entry
+0
+24
+24
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-02A1_2x01_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-02A1, example for new mpn: 39-29-4029, 1 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryscrew_flange
+0
+2
+2
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-02A2_2x01_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-02A2, example for new mpn: 39-30-0020, 1 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryplastic_peg
+0
+2
+2
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-04A1_2x02_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-04A1, example for new mpn: 39-29-4049, 2 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryscrew_flange
+0
+4
+4
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-04A2_2x02_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-04A2, example for new mpn: 39-30-0040, 2 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryplastic_peg
+0
+4
+4
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-06A1_2x03_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-06A1, example for new mpn: 39-29-4069, 3 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryscrew_flange
+0
+6
+6
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-06A2_2x03_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-06A2, example for new mpn: 39-30-0060, 3 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryplastic_peg
+0
+6
+6
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-08A1_2x04_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-08A1, example for new mpn: 39-29-4089, 4 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryscrew_flange
+0
+8
+8
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-08A2_2x04_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-08A2, example for new mpn: 39-30-0080, 4 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryplastic_peg
+0
+8
+8
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-10A1_2x05_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-10A1, example for new mpn: 39-29-4109, 5 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryscrew_flange
+0
+10
+10
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-10A2_2x05_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-10A2, example for new mpn: 39-30-0100, 5 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryplastic_peg
+0
+10
+10
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-12A1_2x06_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-12A1, example for new mpn: 39-29-4129, 6 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryscrew_flange
+0
+12
+12
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-12A2_2x06_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-12A2, example for new mpn: 39-30-0120, 6 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryplastic_peg
+0
+12
+12
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-14A1_2x07_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-14A1, example for new mpn: 39-29-4149, 7 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryscrew_flange
+0
+14
+14
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-14A2_2x07_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-14A2, example for new mpn: 39-30-0140, 7 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryplastic_peg
+0
+14
+14
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-16A1_2x08_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-16A1, example for new mpn: 39-29-4169, 8 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryscrew_flange
+0
+16
+16
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-16A2_2x08_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-16A2, example for new mpn: 39-30-0160, 8 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryplastic_peg
+0
+16
+16
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-18A1_2x09_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-18A1, example for new mpn: 39-29-4189, 9 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryscrew_flange
+0
+18
+18
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-18A2_2x09_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-18A2, example for new mpn: 39-30-0180, 9 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryplastic_peg
+0
+18
+18
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-20A1_2x10_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-20A1, example for new mpn: 39-29-4209, 10 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryscrew_flange
+0
+20
+20
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-20A2_2x10_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-20A2, example for new mpn: 39-30-0200, 10 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryplastic_peg
+0
+20
+20
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-22A1_2x11_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-22A1, example for new mpn: 39-29-4229, 11 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryscrew_flange
+0
+22
+22
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-22A2_2x11_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-22A2, example for new mpn: 39-30-0220, 11 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryplastic_peg
+0
+22
+22
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-24A1_2x12_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-24A1, example for new mpn: 39-29-4249, 12 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryscrew_flange
+0
+24
+24
+Connector_Molex
+Molex_Mini-Fit_Jr_5569-24A2_2x12_P4.20mm_Horizontal
+Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-24A2, example for new mpn: 39-30-0240, 12 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Jr top entryplastic_peg
+0
+24
+24
+Connector_Molex
+Molex_Mini-Fit_Sr_42819-22XX_1x02_P10.00mm_Vertical
+Molex Mini-Fit Sr. Power Connectors, 42819-22XX, 2 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+6
+2
+Connector_Molex
+Molex_Mini-Fit_Sr_42819-22XX_1x02_P10.00mm_Vertical_ThermalVias
+Molex Mini-Fit Sr. Power Connectors, 42819-22XX, With thermal vias in pads, 2 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+32
+2
+Connector_Molex
+Molex_Mini-Fit_Sr_42819-32XX_1x03_P10.00mm_Vertical
+Molex Mini-Fit Sr. Power Connectors, 42819-32XX, 3 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+8
+3
+Connector_Molex
+Molex_Mini-Fit_Sr_42819-32XX_1x03_P10.00mm_Vertical_ThermalVias
+Molex Mini-Fit Sr. Power Connectors, 42819-32XX, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+47
+3
+Connector_Molex
+Molex_Mini-Fit_Sr_42819-42XX_1x04_P10.00mm_Vertical
+Molex Mini-Fit Sr. Power Connectors, 42819-42XX, 4 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+10
+4
+Connector_Molex
+Molex_Mini-Fit_Sr_42819-42XX_1x04_P10.00mm_Vertical_ThermalVias
+Molex Mini-Fit Sr. Power Connectors, 42819-42XX, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+62
+4
+Connector_Molex
+Molex_Mini-Fit_Sr_42819-52XX_1x05_P10.00mm_Vertical
+Molex Mini-Fit Sr. Power Connectors, 42819-52XX, 5 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+12
+5
+Connector_Molex
+Molex_Mini-Fit_Sr_42819-52XX_1x05_P10.00mm_Vertical_ThermalVias
+Molex Mini-Fit Sr. Power Connectors, 42819-52XX, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+77
+5
+Connector_Molex
+Molex_Mini-Fit_Sr_42819-62XX_1x06_P10.00mm_Vertical
+Molex Mini-Fit Sr. Power Connectors, 42819-62XX, 6 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+14
+6
+Connector_Molex
+Molex_Mini-Fit_Sr_42819-62XX_1x06_P10.00mm_Vertical_ThermalVias
+Molex Mini-Fit Sr. Power Connectors, 42819-62XX, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+92
+6
+Connector_Molex
+Molex_Mini-Fit_Sr_42820-22XX_1x02_P10.00mm_Horizontal
+Molex Mini-Fit Sr. Power Connectors, 42820-22XX, 2 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr top entry
+0
+6
+2
+Connector_Molex
+Molex_Mini-Fit_Sr_42820-22XX_1x02_P10.00mm_Horizontal_ThermalVias
+Molex Mini-Fit Sr. Power Connectors, 42820-22XX, With thermal vias in pads, 2 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr top entry
+0
+32
+2
+Connector_Molex
+Molex_Mini-Fit_Sr_42820-32XX_1x03_P10.00mm_Horizontal
+Molex Mini-Fit Sr. Power Connectors, 42820-32XX, 3 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr top entry
+0
+8
+3
+Connector_Molex
+Molex_Mini-Fit_Sr_42820-32XX_1x03_P10.00mm_Horizontal_ThermalVias
+Molex Mini-Fit Sr. Power Connectors, 42820-32XX, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr top entry
+0
+47
+3
+Connector_Molex
+Molex_Mini-Fit_Sr_42820-42XX_1x04_P10.00mm_Horizontal
+Molex Mini-Fit Sr. Power Connectors, 42820-42XX, 4 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr top entry
+0
+10
+4
+Connector_Molex
+Molex_Mini-Fit_Sr_42820-42XX_1x04_P10.00mm_Horizontal_ThermalVias
+Molex Mini-Fit Sr. Power Connectors, 42820-42XX, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr top entry
+0
+62
+4
+Connector_Molex
+Molex_Mini-Fit_Sr_42820-52XX_1x05_P10.00mm_Horizontal
+Molex Mini-Fit Sr. Power Connectors, 42820-52XX, 5 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr top entry
+0
+12
+5
+Connector_Molex
+Molex_Mini-Fit_Sr_42820-52XX_1x05_P10.00mm_Horizontal_ThermalVias
+Molex Mini-Fit Sr. Power Connectors, 42820-52XX, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr top entry
+0
+77
+5
+Connector_Molex
+Molex_Mini-Fit_Sr_42820-62XX_1x06_P10.00mm_Horizontal
+Molex Mini-Fit Sr. Power Connectors, 42820-62XX, 6 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr top entry
+0
+14
+6
+Connector_Molex
+Molex_Mini-Fit_Sr_42820-62XX_1x06_P10.00mm_Horizontal_ThermalVias
+Molex Mini-Fit Sr. Power Connectors, 42820-62XX, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr top entry
+0
+92
+6
+Connector_Molex
+Molex_Mini-Fit_Sr_43915-xx06_2x03_P10.00mm_Vertical
+Molex Mini-Fit Sr. Power Connectors, 43915-xx06, 3 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+14
+6
+Connector_Molex
+Molex_Mini-Fit_Sr_43915-xx06_2x03_P10.00mm_Vertical_ThermalVias
+Molex Mini-Fit Sr. Power Connectors, 43915-xx06, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+92
+6
+Connector_Molex
+Molex_Mini-Fit_Sr_43915-xx08_2x04_P10.00mm_Vertical
+Molex Mini-Fit Sr. Power Connectors, 43915-xx08, 4 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+18
+8
+Connector_Molex
+Molex_Mini-Fit_Sr_43915-xx08_2x04_P10.00mm_Vertical_ThermalVias
+Molex Mini-Fit Sr. Power Connectors, 43915-xx08, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+122
+8
+Connector_Molex
+Molex_Mini-Fit_Sr_43915-xx10_2x05_P10.00mm_Vertical
+Molex Mini-Fit Sr. Power Connectors, 43915-xx10, 5 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+22
+10
+Connector_Molex
+Molex_Mini-Fit_Sr_43915-xx10_2x05_P10.00mm_Vertical_ThermalVias
+Molex Mini-Fit Sr. Power Connectors, 43915-xx10, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+152
+10
+Connector_Molex
+Molex_Mini-Fit_Sr_43915-xx12_2x06_P10.00mm_Vertical
+Molex Mini-Fit Sr. Power Connectors, 43915-xx12, 6 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+26
+12
+Connector_Molex
+Molex_Mini-Fit_Sr_43915-xx12_2x06_P10.00mm_Vertical_ThermalVias
+Molex Mini-Fit Sr. Power Connectors, 43915-xx12, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+182
+12
+Connector_Molex
+Molex_Mini-Fit_Sr_43915-xx14_2x07_P10.00mm_Vertical
+Molex Mini-Fit Sr. Power Connectors, 43915-xx14, 7 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+30
+14
+Connector_Molex
+Molex_Mini-Fit_Sr_43915-xx14_2x07_P10.00mm_Vertical_ThermalVias
+Molex Mini-Fit Sr. Power Connectors, 43915-xx14, With thermal vias in pads, 7 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator
+connector Molex Mini-Fit_Sr side entry
+0
+212
+14
+Connector_Molex
+Molex_Nano-Fit_105309-xx02_1x02_P2.50mm_Vertical
+Molex Nano-Fit Power Connectors, 105309-xx02, 2 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit side entry
+0
+2
+2
+Connector_Molex
+Molex_Nano-Fit_105309-xx03_1x03_P2.50mm_Vertical
+Molex Nano-Fit Power Connectors, 105309-xx03, 3 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit side entry
+0
+3
+3
+Connector_Molex
+Molex_Nano-Fit_105309-xx04_1x04_P2.50mm_Vertical
+Molex Nano-Fit Power Connectors, 105309-xx04, 4 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit side entry
+0
+4
+4
+Connector_Molex
+Molex_Nano-Fit_105309-xx05_1x05_P2.50mm_Vertical
+Molex Nano-Fit Power Connectors, 105309-xx05, 5 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit side entry
+0
+5
+5
+Connector_Molex
+Molex_Nano-Fit_105309-xx06_1x06_P2.50mm_Vertical
+Molex Nano-Fit Power Connectors, 105309-xx06, 6 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit side entry
+0
+6
+6
+Connector_Molex
+Molex_Nano-Fit_105309-xx07_1x07_P2.50mm_Vertical
+Molex Nano-Fit Power Connectors, 105309-xx07, 7 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit side entry
+0
+7
+7
+Connector_Molex
+Molex_Nano-Fit_105309-xx08_1x08_P2.50mm_Vertical
+Molex Nano-Fit Power Connectors, 105309-xx08, 8 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit side entry
+0
+8
+8
+Connector_Molex
+Molex_Nano-Fit_105310-xx04_2x02_P2.50mm_Vertical
+Molex Nano-Fit Power Connectors, 105310-xx04, 2 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit side entry
+0
+4
+4
+Connector_Molex
+Molex_Nano-Fit_105310-xx06_2x03_P2.50mm_Vertical
+Molex Nano-Fit Power Connectors, 105310-xx06, 3 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit side entry
+0
+6
+6
+Connector_Molex
+Molex_Nano-Fit_105310-xx08_2x04_P2.50mm_Vertical
+Molex Nano-Fit Power Connectors, 105310-xx08, 4 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit side entry
+0
+8
+8
+Connector_Molex
+Molex_Nano-Fit_105310-xx10_2x05_P2.50mm_Vertical
+Molex Nano-Fit Power Connectors, 105310-xx10, 5 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit side entry
+0
+10
+10
+Connector_Molex
+Molex_Nano-Fit_105310-xx12_2x06_P2.50mm_Vertical
+Molex Nano-Fit Power Connectors, 105310-xx12, 6 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit side entry
+0
+12
+12
+Connector_Molex
+Molex_Nano-Fit_105310-xx14_2x07_P2.50mm_Vertical
+Molex Nano-Fit Power Connectors, 105310-xx14, 7 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit side entry
+0
+14
+14
+Connector_Molex
+Molex_Nano-Fit_105310-xx16_2x08_P2.50mm_Vertical
+Molex Nano-Fit Power Connectors, 105310-xx16, 8 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit side entry
+0
+16
+16
+Connector_Molex
+Molex_Nano-Fit_105313-xx02_1x02_P2.50mm_Horizontal
+Molex Nano-Fit Power Connectors, 105313-xx02, 2 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit top entry
+0
+2
+2
+Connector_Molex
+Molex_Nano-Fit_105313-xx03_1x03_P2.50mm_Horizontal
+Molex Nano-Fit Power Connectors, 105313-xx03, 3 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit top entry
+0
+3
+3
+Connector_Molex
+Molex_Nano-Fit_105313-xx04_1x04_P2.50mm_Horizontal
+Molex Nano-Fit Power Connectors, 105313-xx04, 4 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit top entry
+0
+4
+4
+Connector_Molex
+Molex_Nano-Fit_105313-xx05_1x05_P2.50mm_Horizontal
+Molex Nano-Fit Power Connectors, 105313-xx05, 5 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit top entry
+0
+5
+5
+Connector_Molex
+Molex_Nano-Fit_105313-xx06_1x06_P2.50mm_Horizontal
+Molex Nano-Fit Power Connectors, 105313-xx06, 6 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit top entry
+0
+6
+6
+Connector_Molex
+Molex_Nano-Fit_105313-xx07_1x07_P2.50mm_Horizontal
+Molex Nano-Fit Power Connectors, 105313-xx07, 7 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit top entry
+0
+7
+7
+Connector_Molex
+Molex_Nano-Fit_105313-xx08_1x08_P2.50mm_Horizontal
+Molex Nano-Fit Power Connectors, 105313-xx08, 8 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit top entry
+0
+8
+8
+Connector_Molex
+Molex_Nano-Fit_105314-xx04_2x02_P2.50mm_Horizontal
+Molex Nano-Fit Power Connectors, 105314-xx04, 2 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit top entry
+0
+4
+4
+Connector_Molex
+Molex_Nano-Fit_105314-xx06_2x03_P2.50mm_Horizontal
+Molex Nano-Fit Power Connectors, 105314-xx06, 3 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit top entry
+0
+6
+6
+Connector_Molex
+Molex_Nano-Fit_105314-xx08_2x04_P2.50mm_Horizontal
+Molex Nano-Fit Power Connectors, 105314-xx08, 4 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit top entry
+0
+8
+8
+Connector_Molex
+Molex_Nano-Fit_105314-xx10_2x05_P2.50mm_Horizontal
+Molex Nano-Fit Power Connectors, 105314-xx10, 5 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit top entry
+0
+10
+10
+Connector_Molex
+Molex_Nano-Fit_105314-xx12_2x06_P2.50mm_Horizontal
+Molex Nano-Fit Power Connectors, 105314-xx12, 6 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit top entry
+0
+12
+12
+Connector_Molex
+Molex_Nano-Fit_105314-xx14_2x07_P2.50mm_Horizontal
+Molex Nano-Fit Power Connectors, 105314-xx14, 7 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit top entry
+0
+14
+14
+Connector_Molex
+Molex_Nano-Fit_105314-xx16_2x08_P2.50mm_Horizontal
+Molex Nano-Fit Power Connectors, 105314-xx16, 8 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator
+connector Molex Nano-Fit top entry
+0
+16
+16
+Connector_Molex
+Molex_Panelmate_53780-0270_1x02-1MP_P1.25mm_Horizontal
+Molex Panelmate series connector, 53780-0270 (), generated with kicad-footprint-generator
+connector Molex Panelmate top entry
+0
+4
+3
+Connector_Molex
+Molex_Panelmate_53780-0370_1x03-1MP_P1.25mm_Horizontal
+Molex Panelmate series connector, 53780-0370 (), generated with kicad-footprint-generator
+connector Molex Panelmate top entry
+0
+5
+4
+Connector_Molex
+Molex_Panelmate_53780-0470_1x04-1MP_P1.25mm_Horizontal
+Molex Panelmate series connector, 53780-0470 (), generated with kicad-footprint-generator
+connector Molex Panelmate top entry
+0
+6
+5
+Connector_Molex
+Molex_Panelmate_53780-0570_1x05-1MP_P1.25mm_Horizontal
+Molex Panelmate series connector, 53780-0570 (), generated with kicad-footprint-generator
+connector Molex Panelmate top entry
+0
+7
+6
+Connector_Molex
+Molex_Panelmate_53780-0670_1x06-1MP_P1.25mm_Horizontal
+Molex Panelmate series connector, 53780-0670 (), generated with kicad-footprint-generator
+connector Molex Panelmate top entry
+0
+8
+7
+Connector_Molex
+Molex_Panelmate_53780-0770_1x07-1MP_P1.25mm_Horizontal
+Molex Panelmate series connector, 53780-0770 (), generated with kicad-footprint-generator
+connector Molex Panelmate top entry
+0
+9
+8
+Connector_Molex
+Molex_Panelmate_53780-0870_1x08-1MP_P1.25mm_Horizontal
+Molex Panelmate series connector, 53780-0870 (), generated with kicad-footprint-generator
+connector Molex Panelmate top entry
+0
+10
+9
+Connector_Molex
+Molex_Panelmate_53780-0970_1x09-1MP_P1.25mm_Horizontal
+Molex Panelmate series connector, 53780-0970 (), generated with kicad-footprint-generator
+connector Molex Panelmate top entry
+0
+11
+10
+Connector_Molex
+Molex_Panelmate_53780-1070_1x10-1MP_P1.25mm_Horizontal
+Molex Panelmate series connector, 53780-1070 (), generated with kicad-footprint-generator
+connector Molex Panelmate top entry
+0
+12
+11
+Connector_Molex
+Molex_Panelmate_53780-1270_1x12-1MP_P1.25mm_Horizontal
+Molex Panelmate series connector, 53780-1270 (), generated with kicad-footprint-generator
+connector Molex Panelmate top entry
+0
+14
+13
+Connector_Molex
+Molex_Panelmate_53780-1470_1x14-1MP_P1.25mm_Horizontal
+Molex Panelmate series connector, 53780-1470 (), generated with kicad-footprint-generator
+connector Molex Panelmate top entry
+0
+16
+15
+Connector_Molex
+Molex_Panelmate_53780-1570_1x15-1MP_P1.25mm_Horizontal
+Molex Panelmate series connector, 53780-1570 (), generated with kicad-footprint-generator
+connector Molex Panelmate top entry
+0
+17
+16
+Connector_Molex
+Molex_Panelmate_53780-1870_1x18-1MP_P1.25mm_Horizontal
+Molex Panelmate series connector, 53780-1870 (), generated with kicad-footprint-generator
+connector Molex Panelmate top entry
+0
+20
+19
+Connector_Molex
+Molex_Panelmate_53780-3070_1x30-1MP_P1.25mm_Horizontal
+Molex Panelmate series connector, 53780-3070 (), generated with kicad-footprint-generator
+connector Molex Panelmate top entry
+0
+32
+31
+Connector_Molex
+Molex_Pico-Clasp_202396-0207_1x02-1MP_P1.00mm_Horizontal
+Molex Pico-Clasp series connector, 202396-0207 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp top entry
+0
+4
+3
+Connector_Molex
+Molex_Pico-Clasp_202396-0307_1x03-1MP_P1.00mm_Horizontal
+Molex Pico-Clasp series connector, 202396-0307 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp top entry
+0
+5
+4
+Connector_Molex
+Molex_Pico-Clasp_202396-0407_1x04-1MP_P1.00mm_Horizontal
+Molex Pico-Clasp series connector, 202396-0407 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp top entry
+0
+6
+5
+Connector_Molex
+Molex_Pico-Clasp_202396-0507_1x05-1MP_P1.00mm_Horizontal
+Molex Pico-Clasp series connector, 202396-0507 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp top entry
+0
+7
+6
+Connector_Molex
+Molex_Pico-Clasp_202396-0607_1x06-1MP_P1.00mm_Horizontal
+Molex Pico-Clasp series connector, 202396-0607 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp top entry
+0
+8
+7
+Connector_Molex
+Molex_Pico-Clasp_202396-0707_1x07-1MP_P1.00mm_Horizontal
+Molex Pico-Clasp series connector, 202396-0707 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp top entry
+0
+9
+8
+Connector_Molex
+Molex_Pico-Clasp_202396-0807_1x08-1MP_P1.00mm_Horizontal
+Molex Pico-Clasp series connector, 202396-0807 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp top entry
+0
+10
+9
+Connector_Molex
+Molex_Pico-Clasp_202396-0907_1x09-1MP_P1.00mm_Horizontal
+Molex Pico-Clasp series connector, 202396-0907 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp top entry
+0
+11
+10
+Connector_Molex
+Molex_Pico-Clasp_202396-1007_1x10-1MP_P1.00mm_Horizontal
+Molex Pico-Clasp series connector, 202396-1007 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp top entry
+0
+12
+11
+Connector_Molex
+Molex_Pico-Clasp_202396-1107_1x11-1MP_P1.00mm_Horizontal
+Molex Pico-Clasp series connector, 202396-1107 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp top entry
+0
+13
+12
+Connector_Molex
+Molex_Pico-Clasp_202396-1207_1x12-1MP_P1.00mm_Horizontal
+Molex Pico-Clasp series connector, 202396-1207 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp top entry
+0
+14
+13
+Connector_Molex
+Molex_Pico-Clasp_202396-1307_1x13-1MP_P1.00mm_Horizontal
+Molex Pico-Clasp series connector, 202396-1307 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp top entry
+0
+15
+14
+Connector_Molex
+Molex_Pico-Clasp_202396-1407_1x14-1MP_P1.00mm_Horizontal
+Molex Pico-Clasp series connector, 202396-1407 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp top entry
+0
+16
+15
+Connector_Molex
+Molex_Pico-Clasp_202396-1507_1x15-1MP_P1.00mm_Horizontal
+Molex Pico-Clasp series connector, 202396-1507 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp top entry
+0
+17
+16
+Connector_Molex
+Molex_Pico-Clasp_501331-0207_1x02-1MP_P1.00mm_Vertical
+Molex Pico-Clasp series connector, 501331-0207 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp side entry
+0
+4
+3
+Connector_Molex
+Molex_Pico-Clasp_501331-0307_1x03-1MP_P1.00mm_Vertical
+Molex Pico-Clasp series connector, 501331-0307 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp side entry
+0
+5
+4
+Connector_Molex
+Molex_Pico-Clasp_501331-0407_1x04-1MP_P1.00mm_Vertical
+Molex Pico-Clasp series connector, 501331-0407 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp side entry
+0
+6
+5
+Connector_Molex
+Molex_Pico-Clasp_501331-0507_1x05-1MP_P1.00mm_Vertical
+Molex Pico-Clasp series connector, 501331-0507 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp side entry
+0
+7
+6
+Connector_Molex
+Molex_Pico-Clasp_501331-0607_1x06-1MP_P1.00mm_Vertical
+Molex Pico-Clasp series connector, 501331-0607 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp side entry
+0
+8
+7
+Connector_Molex
+Molex_Pico-Clasp_501331-0707_1x07-1MP_P1.00mm_Vertical
+Molex Pico-Clasp series connector, 501331-0707 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp side entry
+0
+9
+8
+Connector_Molex
+Molex_Pico-Clasp_501331-0807_1x08-1MP_P1.00mm_Vertical
+Molex Pico-Clasp series connector, 501331-0807 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp side entry
+0
+10
+9
+Connector_Molex
+Molex_Pico-Clasp_501331-0907_1x09-1MP_P1.00mm_Vertical
+Molex Pico-Clasp series connector, 501331-0907 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp side entry
+0
+11
+10
+Connector_Molex
+Molex_Pico-Clasp_501331-1007_1x10-1MP_P1.00mm_Vertical
+Molex Pico-Clasp series connector, 501331-1007 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp side entry
+0
+12
+11
+Connector_Molex
+Molex_Pico-Clasp_501331-1107_1x11-1MP_P1.00mm_Vertical
+Molex Pico-Clasp series connector, 501331-1107 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp side entry
+0
+13
+12
+Connector_Molex
+Molex_Pico-Clasp_501331-1207_1x12-1MP_P1.00mm_Vertical
+Molex Pico-Clasp series connector, 501331-1207 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp side entry
+0
+14
+13
+Connector_Molex
+Molex_Pico-Clasp_501331-1307_1x13-1MP_P1.00mm_Vertical
+Molex Pico-Clasp series connector, 501331-1307 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp side entry
+0
+15
+14
+Connector_Molex
+Molex_Pico-Clasp_501331-1407_1x14-1MP_P1.00mm_Vertical
+Molex Pico-Clasp series connector, 501331-1407 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp side entry
+0
+16
+15
+Connector_Molex
+Molex_Pico-Clasp_501331-1507_1x15-1MP_P1.00mm_Vertical
+Molex Pico-Clasp series connector, 501331-1507 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Clasp side entry
+0
+17
+16
+Connector_Molex
+Molex_Pico-EZmate_78171-0002_1x02-1MP_P1.20mm_Vertical
+Molex Pico-EZmate series connector, 78171-0002 (http://www.molex.com/pdm_docs/sd/781710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-EZmate side entry
+0
+4
+3
+Connector_Molex
+Molex_Pico-EZmate_78171-0003_1x03-1MP_P1.20mm_Vertical
+Molex Pico-EZmate series connector, 78171-0003 (http://www.molex.com/pdm_docs/sd/781710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-EZmate side entry
+0
+5
+4
+Connector_Molex
+Molex_Pico-EZmate_78171-0004_1x04-1MP_P1.20mm_Vertical
+Molex Pico-EZmate series connector, 78171-0004 (http://www.molex.com/pdm_docs/sd/781710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-EZmate side entry
+0
+6
+5
+Connector_Molex
+Molex_Pico-EZmate_78171-0005_1x05-1MP_P1.20mm_Vertical
+Molex Pico-EZmate series connector, 78171-0005 (http://www.molex.com/pdm_docs/sd/781710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-EZmate side entry
+0
+7
+6
+Connector_Molex
+Molex_Pico-EZmate_Slim_202656-0021_1x02-1MP_P1.20mm_Vertical
+Molex Pico-EZmate_Slim series connector, 202656-0021 (http://www.molex.com/pdm_docs/sd/2026560021_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-EZmate_Slim side entry
+0
+4
+3
+Connector_Molex
+Molex_Pico-Lock_504050-0491_1x04-1MP_P1.50mm_Horizontal
+Molex Pico-Lock series connector, 504050-0491 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Lock top entry
+0
+6
+5
+Connector_Molex
+Molex_Pico-Lock_504050-0591_1x05-1MP_P1.50mm_Horizontal
+Molex Pico-Lock series connector, 504050-0591 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Lock top entry
+0
+7
+6
+Connector_Molex
+Molex_Pico-Lock_504050-0691_1x06-1MP_P1.50mm_Horizontal
+Molex Pico-Lock series connector, 504050-0691 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Lock top entry
+0
+8
+7
+Connector_Molex
+Molex_Pico-Lock_504050-0791_1x07-1MP_P1.50mm_Horizontal
+Molex Pico-Lock series connector, 504050-0791 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Lock top entry
+0
+9
+8
+Connector_Molex
+Molex_Pico-Lock_504050-0891_1x08-1MP_P1.50mm_Horizontal
+Molex Pico-Lock series connector, 504050-0891 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Lock top entry
+0
+10
+9
+Connector_Molex
+Molex_Pico-Lock_504050-1091_1x10-1MP_P1.50mm_Horizontal
+Molex Pico-Lock series connector, 504050-1091 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Lock top entry
+0
+12
+11
+Connector_Molex
+Molex_Pico-Lock_504050-1291_1x12-1MP_P1.50mm_Horizontal
+Molex Pico-Lock series connector, 504050-1291 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator
+connector Molex Pico-Lock top entry
+0
+14
+13
+Connector_Molex
+Molex_PicoBlade_53047-0210_1x02_P1.25mm_Vertical
+Molex PicoBlade Connector System, 53047-0210, 2 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+2
+2
+Connector_Molex
+Molex_PicoBlade_53047-0310_1x03_P1.25mm_Vertical
+Molex PicoBlade Connector System, 53047-0310, 3 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+3
+3
+Connector_Molex
+Molex_PicoBlade_53047-0410_1x04_P1.25mm_Vertical
+Molex PicoBlade Connector System, 53047-0410, 4 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+4
+4
+Connector_Molex
+Molex_PicoBlade_53047-0510_1x05_P1.25mm_Vertical
+Molex PicoBlade Connector System, 53047-0510, 5 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+5
+5
+Connector_Molex
+Molex_PicoBlade_53047-0610_1x06_P1.25mm_Vertical
+Molex PicoBlade Connector System, 53047-0610, 6 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+6
+6
+Connector_Molex
+Molex_PicoBlade_53047-0710_1x07_P1.25mm_Vertical
+Molex PicoBlade Connector System, 53047-0710, 7 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+7
+7
+Connector_Molex
+Molex_PicoBlade_53047-0810_1x08_P1.25mm_Vertical
+Molex PicoBlade Connector System, 53047-0810, 8 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+8
+8
+Connector_Molex
+Molex_PicoBlade_53047-0910_1x09_P1.25mm_Vertical
+Molex PicoBlade Connector System, 53047-0910, 9 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+9
+9
+Connector_Molex
+Molex_PicoBlade_53047-1010_1x10_P1.25mm_Vertical
+Molex PicoBlade Connector System, 53047-1010, 10 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+10
+10
+Connector_Molex
+Molex_PicoBlade_53047-1110_1x11_P1.25mm_Vertical
+Molex PicoBlade Connector System, 53047-1110, 11 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+11
+11
+Connector_Molex
+Molex_PicoBlade_53047-1210_1x12_P1.25mm_Vertical
+Molex PicoBlade Connector System, 53047-1210, 12 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+12
+12
+Connector_Molex
+Molex_PicoBlade_53047-1310_1x13_P1.25mm_Vertical
+Molex PicoBlade Connector System, 53047-1310, 13 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+13
+13
+Connector_Molex
+Molex_PicoBlade_53047-1410_1x14_P1.25mm_Vertical
+Molex PicoBlade Connector System, 53047-1410, 14 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+14
+14
+Connector_Molex
+Molex_PicoBlade_53047-1510_1x15_P1.25mm_Vertical
+Molex PicoBlade Connector System, 53047-1510, 15 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+15
+15
+Connector_Molex
+Molex_PicoBlade_53048-0210_1x02_P1.25mm_Horizontal
+Molex PicoBlade Connector System, 53048-0210, 2 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+2
+2
+Connector_Molex
+Molex_PicoBlade_53048-0310_1x03_P1.25mm_Horizontal
+Molex PicoBlade Connector System, 53048-0310, 3 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+3
+3
+Connector_Molex
+Molex_PicoBlade_53048-0410_1x04_P1.25mm_Horizontal
+Molex PicoBlade Connector System, 53048-0410, 4 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+4
+4
+Connector_Molex
+Molex_PicoBlade_53048-0510_1x05_P1.25mm_Horizontal
+Molex PicoBlade Connector System, 53048-0510, 5 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+5
+5
+Connector_Molex
+Molex_PicoBlade_53048-0610_1x06_P1.25mm_Horizontal
+Molex PicoBlade Connector System, 53048-0610, 6 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+6
+6
+Connector_Molex
+Molex_PicoBlade_53048-0710_1x07_P1.25mm_Horizontal
+Molex PicoBlade Connector System, 53048-0710, 7 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+7
+7
+Connector_Molex
+Molex_PicoBlade_53048-0810_1x08_P1.25mm_Horizontal
+Molex PicoBlade Connector System, 53048-0810, 8 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+8
+8
+Connector_Molex
+Molex_PicoBlade_53048-0910_1x09_P1.25mm_Horizontal
+Molex PicoBlade Connector System, 53048-0910, 9 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+9
+9
+Connector_Molex
+Molex_PicoBlade_53048-1010_1x10_P1.25mm_Horizontal
+Molex PicoBlade Connector System, 53048-1010, 10 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+10
+10
+Connector_Molex
+Molex_PicoBlade_53048-1110_1x11_P1.25mm_Horizontal
+Molex PicoBlade Connector System, 53048-1110, 11 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+11
+11
+Connector_Molex
+Molex_PicoBlade_53048-1210_1x12_P1.25mm_Horizontal
+Molex PicoBlade Connector System, 53048-1210, 12 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+12
+12
+Connector_Molex
+Molex_PicoBlade_53048-1310_1x13_P1.25mm_Horizontal
+Molex PicoBlade Connector System, 53048-1310, 13 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+13
+13
+Connector_Molex
+Molex_PicoBlade_53048-1410_1x14_P1.25mm_Horizontal
+Molex PicoBlade Connector System, 53048-1410, 14 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+14
+14
+Connector_Molex
+Molex_PicoBlade_53048-1510_1x15_P1.25mm_Horizontal
+Molex PicoBlade Connector System, 53048-1510, 15 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+15
+15
+Connector_Molex
+Molex_PicoBlade_53261-0271_1x02-1MP_P1.25mm_Horizontal
+Molex PicoBlade series connector, 53261-0271 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+4
+3
+Connector_Molex
+Molex_PicoBlade_53261-0371_1x03-1MP_P1.25mm_Horizontal
+Molex PicoBlade series connector, 53261-0371 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+5
+4
+Connector_Molex
+Molex_PicoBlade_53261-0471_1x04-1MP_P1.25mm_Horizontal
+Molex PicoBlade series connector, 53261-0471 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+6
+5
+Connector_Molex
+Molex_PicoBlade_53261-0571_1x05-1MP_P1.25mm_Horizontal
+Molex PicoBlade series connector, 53261-0571 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+7
+6
+Connector_Molex
+Molex_PicoBlade_53261-0671_1x06-1MP_P1.25mm_Horizontal
+Molex PicoBlade series connector, 53261-0671 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+8
+7
+Connector_Molex
+Molex_PicoBlade_53261-0771_1x07-1MP_P1.25mm_Horizontal
+Molex PicoBlade series connector, 53261-0771 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+9
+8
+Connector_Molex
+Molex_PicoBlade_53261-0871_1x08-1MP_P1.25mm_Horizontal
+Molex PicoBlade series connector, 53261-0871 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+10
+9
+Connector_Molex
+Molex_PicoBlade_53261-0971_1x09-1MP_P1.25mm_Horizontal
+Molex PicoBlade series connector, 53261-0971 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+11
+10
+Connector_Molex
+Molex_PicoBlade_53261-1071_1x10-1MP_P1.25mm_Horizontal
+Molex PicoBlade series connector, 53261-1071 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+12
+11
+Connector_Molex
+Molex_PicoBlade_53261-1171_1x11-1MP_P1.25mm_Horizontal
+Molex PicoBlade series connector, 53261-1171 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+13
+12
+Connector_Molex
+Molex_PicoBlade_53261-1271_1x12-1MP_P1.25mm_Horizontal
+Molex PicoBlade series connector, 53261-1271 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+14
+13
+Connector_Molex
+Molex_PicoBlade_53261-1371_1x13-1MP_P1.25mm_Horizontal
+Molex PicoBlade series connector, 53261-1371 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+15
+14
+Connector_Molex
+Molex_PicoBlade_53261-1471_1x14-1MP_P1.25mm_Horizontal
+Molex PicoBlade series connector, 53261-1471 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+16
+15
+Connector_Molex
+Molex_PicoBlade_53261-1571_1x15-1MP_P1.25mm_Horizontal
+Molex PicoBlade series connector, 53261-1571 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+17
+16
+Connector_Molex
+Molex_PicoBlade_53261-1771_1x17-1MP_P1.25mm_Horizontal
+Molex PicoBlade series connector, 53261-1771 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade top entry
+0
+19
+18
+Connector_Molex
+Molex_PicoBlade_53398-0271_1x02-1MP_P1.25mm_Vertical
+Molex PicoBlade series connector, 53398-0271 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+4
+3
+Connector_Molex
+Molex_PicoBlade_53398-0371_1x03-1MP_P1.25mm_Vertical
+Molex PicoBlade series connector, 53398-0371 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+5
+4
+Connector_Molex
+Molex_PicoBlade_53398-0471_1x04-1MP_P1.25mm_Vertical
+Molex PicoBlade series connector, 53398-0471 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+6
+5
+Connector_Molex
+Molex_PicoBlade_53398-0571_1x05-1MP_P1.25mm_Vertical
+Molex PicoBlade series connector, 53398-0571 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+7
+6
+Connector_Molex
+Molex_PicoBlade_53398-0671_1x06-1MP_P1.25mm_Vertical
+Molex PicoBlade series connector, 53398-0671 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+8
+7
+Connector_Molex
+Molex_PicoBlade_53398-0771_1x07-1MP_P1.25mm_Vertical
+Molex PicoBlade series connector, 53398-0771 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+9
+8
+Connector_Molex
+Molex_PicoBlade_53398-0871_1x08-1MP_P1.25mm_Vertical
+Molex PicoBlade series connector, 53398-0871 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+10
+9
+Connector_Molex
+Molex_PicoBlade_53398-0971_1x09-1MP_P1.25mm_Vertical
+Molex PicoBlade series connector, 53398-0971 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+11
+10
+Connector_Molex
+Molex_PicoBlade_53398-1071_1x10-1MP_P1.25mm_Vertical
+Molex PicoBlade series connector, 53398-1071 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+12
+11
+Connector_Molex
+Molex_PicoBlade_53398-1171_1x11-1MP_P1.25mm_Vertical
+Molex PicoBlade series connector, 53398-1171 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+13
+12
+Connector_Molex
+Molex_PicoBlade_53398-1271_1x12-1MP_P1.25mm_Vertical
+Molex PicoBlade series connector, 53398-1271 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+14
+13
+Connector_Molex
+Molex_PicoBlade_53398-1371_1x13-1MP_P1.25mm_Vertical
+Molex PicoBlade series connector, 53398-1371 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+15
+14
+Connector_Molex
+Molex_PicoBlade_53398-1471_1x14-1MP_P1.25mm_Vertical
+Molex PicoBlade series connector, 53398-1471 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+16
+15
+Connector_Molex
+Molex_PicoBlade_53398-1571_1x15-1MP_P1.25mm_Vertical
+Molex PicoBlade series connector, 53398-1571 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator
+connector Molex PicoBlade side entry
+0
+17
+16
+Connector_Molex
+Molex_Picoflex_90325-0004_2x02_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90325-0004, 4 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+4
+4
+Connector_Molex
+Molex_Picoflex_90325-0006_2x03_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90325-0006, 6 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+6
+6
+Connector_Molex
+Molex_Picoflex_90325-0008_2x04_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90325-0008, 8 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+8
+8
+Connector_Molex
+Molex_Picoflex_90325-0010_2x05_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90325-0010, 10 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+10
+10
+Connector_Molex
+Molex_Picoflex_90325-0012_2x06_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90325-0012, 12 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+12
+12
+Connector_Molex
+Molex_Picoflex_90325-0014_2x07_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90325-0014, 14 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+14
+14
+Connector_Molex
+Molex_Picoflex_90325-0016_2x08_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90325-0016, 16 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+16
+16
+Connector_Molex
+Molex_Picoflex_90325-0018_2x09_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90325-0018, 18 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+18
+18
+Connector_Molex
+Molex_Picoflex_90325-0020_2x10_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90325-0020, 20 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+20
+20
+Connector_Molex
+Molex_Picoflex_90325-0022_2x11_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90325-0022, 22 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+22
+22
+Connector_Molex
+Molex_Picoflex_90325-0024_2x12_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90325-0024, 24 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+24
+24
+Connector_Molex
+Molex_Picoflex_90325-0026_2x13_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90325-0026, 26 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+26
+26
+Connector_Molex
+Molex_Picoflex_90814-0004_2x02_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90814-0004, 4 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+4
+4
+Connector_Molex
+Molex_Picoflex_90814-0006_2x03_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90814-0006, 6 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+6
+6
+Connector_Molex
+Molex_Picoflex_90814-0008_2x04_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90814-0008, 8 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+8
+8
+Connector_Molex
+Molex_Picoflex_90814-0010_2x05_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90814-0010, 10 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+10
+10
+Connector_Molex
+Molex_Picoflex_90814-0012_2x06_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90814-0012, 12 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+12
+12
+Connector_Molex
+Molex_Picoflex_90814-0014_2x07_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90814-0014, 14 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+14
+14
+Connector_Molex
+Molex_Picoflex_90814-0016_2x08_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90814-0016, 16 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+16
+16
+Connector_Molex
+Molex_Picoflex_90814-0018_2x09_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90814-0018, 18 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+18
+18
+Connector_Molex
+Molex_Picoflex_90814-0020_2x10_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90814-0020, 20 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+20
+20
+Connector_Molex
+Molex_Picoflex_90814-0022_2x11_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90814-0022, 22 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+22
+22
+Connector_Molex
+Molex_Picoflex_90814-0024_2x12_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90814-0024, 24 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+24
+24
+Connector_Molex
+Molex_Picoflex_90814-0026_2x13_P1.27mm_Vertical
+Molex Picoflex Ribbon-Cable Connectors, 90814-0026, 26 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator
+connector Molex Picoflex side entry
+0
+26
+26
+Connector_Molex
+Molex_SL_171971-0002_1x02_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0002 (compatible alternatives: 171971-0102, 171971-0202), 2 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+2
+2
+Connector_Molex
+Molex_SL_171971-0003_1x03_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0003 (compatible alternatives: 171971-0103, 171971-0203), 3 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+3
+3
+Connector_Molex
+Molex_SL_171971-0004_1x04_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0004 (compatible alternatives: 171971-0104, 171971-0204), 4 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+4
+4
+Connector_Molex
+Molex_SL_171971-0005_1x05_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0005 (compatible alternatives: 171971-0105, 171971-0205), 5 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+5
+5
+Connector_Molex
+Molex_SL_171971-0006_1x06_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0006 (compatible alternatives: 171971-0106, 171971-0206), 6 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+6
+6
+Connector_Molex
+Molex_SL_171971-0007_1x07_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0007 (compatible alternatives: 171971-0107, 171971-0207), 7 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+7
+7
+Connector_Molex
+Molex_SL_171971-0008_1x08_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0008 (compatible alternatives: 171971-0108, 171971-0208), 8 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+8
+8
+Connector_Molex
+Molex_SL_171971-0009_1x09_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0009 (compatible alternatives: 171971-0109, 171971-0209), 9 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+9
+9
+Connector_Molex
+Molex_SL_171971-0010_1x10_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0010 (compatible alternatives: 171971-0110, 171971-0210), 10 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+10
+10
+Connector_Molex
+Molex_SL_171971-0011_1x11_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0011 (compatible alternatives: 171971-0111, 171971-0211), 11 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+11
+11
+Connector_Molex
+Molex_SL_171971-0012_1x12_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0012 (compatible alternatives: 171971-0112, 171971-0212), 12 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+12
+12
+Connector_Molex
+Molex_SL_171971-0013_1x13_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0013 (compatible alternatives: 171971-0113, 171971-0213), 13 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+13
+13
+Connector_Molex
+Molex_SL_171971-0014_1x14_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0014 (compatible alternatives: 171971-0114, 171971-0214), 14 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+14
+14
+Connector_Molex
+Molex_SL_171971-0015_1x15_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0015 (compatible alternatives: 171971-0115, 171971-0215), 15 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+15
+15
+Connector_Molex
+Molex_SL_171971-0016_1x16_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0016 (compatible alternatives: 171971-0116, 171971-0216), 16 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+16
+16
+Connector_Molex
+Molex_SL_171971-0017_1x17_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0017 (compatible alternatives: 171971-0117, 171971-0217), 17 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+17
+17
+Connector_Molex
+Molex_SL_171971-0018_1x18_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0018 (compatible alternatives: 171971-0118, 171971-0218), 18 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+18
+18
+Connector_Molex
+Molex_SL_171971-0019_1x19_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0019 (compatible alternatives: 171971-0119, 171971-0219), 19 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+19
+19
+Connector_Molex
+Molex_SL_171971-0020_1x20_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0020 (compatible alternatives: 171971-0120, 171971-0220), 20 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+20
+20
+Connector_Molex
+Molex_SL_171971-0021_1x21_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0021 (compatible alternatives: 171971-0121, 171971-0221), 21 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+21
+21
+Connector_Molex
+Molex_SL_171971-0022_1x22_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0022 (compatible alternatives: 171971-0122, 171971-0222), 22 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+22
+22
+Connector_Molex
+Molex_SL_171971-0023_1x23_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0023 (compatible alternatives: 171971-0123, 171971-0223), 23 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+23
+23
+Connector_Molex
+Molex_SL_171971-0024_1x24_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0024 (compatible alternatives: 171971-0124, 171971-0224), 24 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+24
+24
+Connector_Molex
+Molex_SL_171971-0025_1x25_P2.54mm_Vertical
+Molex Stackable Linear Connector, 171971-0025 (compatible alternatives: 171971-0125, 171971-0225), 25 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator
+connector Molex SL vertical
+0
+25
+25
+Connector_Molex
+Molex_SPOX_5267-02A_1x02_P2.50mm_Vertical
+Molex SPOX Connector System, 5267-02A, 2 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX side entry
+0
+2
+2
+Connector_Molex
+Molex_SPOX_5267-03A_1x03_P2.50mm_Vertical
+Molex SPOX Connector System, 5267-03A, 3 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX side entry
+0
+3
+3
+Connector_Molex
+Molex_SPOX_5267-04A_1x04_P2.50mm_Vertical
+Molex SPOX Connector System, 5267-04A, 4 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX side entry
+0
+4
+4
+Connector_Molex
+Molex_SPOX_5267-05A_1x05_P2.50mm_Vertical
+Molex SPOX Connector System, 5267-05A, 5 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX side entry
+0
+5
+5
+Connector_Molex
+Molex_SPOX_5267-06A_1x06_P2.50mm_Vertical
+Molex SPOX Connector System, 5267-06A, 6 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX side entry
+0
+6
+6
+Connector_Molex
+Molex_SPOX_5267-07A_1x07_P2.50mm_Vertical
+Molex SPOX Connector System, 5267-07A, 7 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX side entry
+0
+7
+7
+Connector_Molex
+Molex_SPOX_5267-08A_1x08_P2.50mm_Vertical
+Molex SPOX Connector System, 5267-08A, 8 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX side entry
+0
+8
+8
+Connector_Molex
+Molex_SPOX_5267-09A_1x09_P2.50mm_Vertical
+Molex SPOX Connector System, 5267-09A, 9 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX side entry
+0
+9
+9
+Connector_Molex
+Molex_SPOX_5267-10A_1x10_P2.50mm_Vertical
+Molex SPOX Connector System, 5267-10A, 10 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX side entry
+0
+10
+10
+Connector_Molex
+Molex_SPOX_5267-11A_1x11_P2.50mm_Vertical
+Molex SPOX Connector System, 5267-11A, 11 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX side entry
+0
+11
+11
+Connector_Molex
+Molex_SPOX_5267-12A_1x12_P2.50mm_Vertical
+Molex SPOX Connector System, 5267-12A, 12 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX side entry
+0
+12
+12
+Connector_Molex
+Molex_SPOX_5267-13A_1x13_P2.50mm_Vertical
+Molex SPOX Connector System, 5267-13A, 13 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX side entry
+0
+13
+13
+Connector_Molex
+Molex_SPOX_5267-14A_1x14_P2.50mm_Vertical
+Molex SPOX Connector System, 5267-14A, 14 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX side entry
+0
+14
+14
+Connector_Molex
+Molex_SPOX_5267-15A_1x15_P2.50mm_Vertical
+Molex SPOX Connector System, 5267-15A, 15 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX side entry
+0
+15
+15
+Connector_Molex
+Molex_SPOX_5268-02A_1x02_P2.50mm_Horizontal
+Molex SPOX Connector System, 5268-02A, 2 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX horizontal
+0
+2
+2
+Connector_Molex
+Molex_SPOX_5268-03A_1x03_P2.50mm_Horizontal
+Molex SPOX Connector System, 5268-03A, 3 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX horizontal
+0
+3
+3
+Connector_Molex
+Molex_SPOX_5268-04A_1x04_P2.50mm_Horizontal
+Molex SPOX Connector System, 5268-04A, 4 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX horizontal
+0
+4
+4
+Connector_Molex
+Molex_SPOX_5268-05A_1x05_P2.50mm_Horizontal
+Molex SPOX Connector System, 5268-05A, 5 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX horizontal
+0
+5
+5
+Connector_Molex
+Molex_SPOX_5268-06A_1x06_P2.50mm_Horizontal
+Molex SPOX Connector System, 5268-06A, 6 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX horizontal
+0
+6
+6
+Connector_Molex
+Molex_SPOX_5268-07A_1x07_P2.50mm_Horizontal
+Molex SPOX Connector System, 5268-07A, 7 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX horizontal
+0
+7
+7
+Connector_Molex
+Molex_SPOX_5268-08A_1x08_P2.50mm_Horizontal
+Molex SPOX Connector System, 5268-08A, 8 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX horizontal
+0
+8
+8
+Connector_Molex
+Molex_SPOX_5268-09A_1x09_P2.50mm_Horizontal
+Molex SPOX Connector System, 5268-09A, 9 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX horizontal
+0
+9
+9
+Connector_Molex
+Molex_SPOX_5268-10A_1x10_P2.50mm_Horizontal
+Molex SPOX Connector System, 5268-10A, 10 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX horizontal
+0
+10
+10
+Connector_Molex
+Molex_SPOX_5268-11A_1x11_P2.50mm_Horizontal
+Molex SPOX Connector System, 5268-11A, 11 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX horizontal
+0
+11
+11
+Connector_Molex
+Molex_SPOX_5268-12A_1x12_P2.50mm_Horizontal
+Molex SPOX Connector System, 5268-12A, 12 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX horizontal
+0
+12
+12
+Connector_Molex
+Molex_SPOX_5268-13A_1x13_P2.50mm_Horizontal
+Molex SPOX Connector System, 5268-13A, 13 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX horizontal
+0
+13
+13
+Connector_Molex
+Molex_SPOX_5268-14A_1x14_P2.50mm_Horizontal
+Molex SPOX Connector System, 5268-14A, 14 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX horizontal
+0
+14
+14
+Connector_Molex
+Molex_SPOX_5268-15A_1x15_P2.50mm_Horizontal
+Molex SPOX Connector System, 5268-15A, 15 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator
+connector Molex SPOX horizontal
+0
+15
+15
+Connector_Molex
+Molex_Sabre_43160-0102_1x02_P7.49mm_Vertical
+Molex Sabre Power Connector, 43160-0102, 2 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+4
+2
+Connector_Molex
+Molex_Sabre_43160-0102_1x02_P7.49mm_Vertical_ThermalVias
+Molex Sabre Power Connector, 43160-0102, With thermal vias in pads, 2 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+30
+2
+Connector_Molex
+Molex_Sabre_43160-0103_1x03_P7.49mm_Vertical
+Molex Sabre Power Connector, 43160-0103, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+6
+3
+Connector_Molex
+Molex_Sabre_43160-0103_1x03_P7.49mm_Vertical_ThermalVias
+Molex Sabre Power Connector, 43160-0103, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+45
+3
+Connector_Molex
+Molex_Sabre_43160-0104_1x04_P7.49mm_Vertical
+Molex Sabre Power Connector, 43160-0104, 4 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+8
+4
+Connector_Molex
+Molex_Sabre_43160-0104_1x04_P7.49mm_Vertical_ThermalVias
+Molex Sabre Power Connector, 43160-0104, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+60
+4
+Connector_Molex
+Molex_Sabre_43160-0105_1x05_P7.49mm_Vertical
+Molex Sabre Power Connector, 43160-0105, 5 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+10
+5
+Connector_Molex
+Molex_Sabre_43160-0105_1x05_P7.49mm_Vertical_ThermalVias
+Molex Sabre Power Connector, 43160-0105, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+75
+5
+Connector_Molex
+Molex_Sabre_43160-0106_1x06_P7.49mm_Vertical
+Molex Sabre Power Connector, 43160-0106, 6 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+12
+6
+Connector_Molex
+Molex_Sabre_43160-0106_1x06_P7.49mm_Vertical_ThermalVias
+Molex Sabre Power Connector, 43160-0106, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+90
+6
+Connector_Molex
+Molex_Sabre_43160-1102_1x02_P7.49mm_Horizontal
+Molex Sabre Power Connector, 43160-1102, 2 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+6
+2
+Connector_Molex
+Molex_Sabre_43160-1102_1x02_P7.49mm_Horizontal_ThermalVias
+Molex Sabre Power Connector, 43160-1102, With thermal vias in pads, 2 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+32
+2
+Connector_Molex
+Molex_Sabre_43160-1103_1x03_P7.49mm_Horizontal
+Molex Sabre Power Connector, 43160-1103, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+8
+3
+Connector_Molex
+Molex_Sabre_43160-1103_1x03_P7.49mm_Horizontal_ThermalVias
+Molex Sabre Power Connector, 43160-1103, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+47
+3
+Connector_Molex
+Molex_Sabre_43160-1104_1x04_P7.49mm_Horizontal
+Molex Sabre Power Connector, 43160-1104, 4 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+10
+4
+Connector_Molex
+Molex_Sabre_43160-1104_1x04_P7.49mm_Horizontal_ThermalVias
+Molex Sabre Power Connector, 43160-1104, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+62
+4
+Connector_Molex
+Molex_Sabre_43160-1105_1x05_P7.49mm_Horizontal
+Molex Sabre Power Connector, 43160-1105, 5 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+12
+5
+Connector_Molex
+Molex_Sabre_43160-1105_1x05_P7.49mm_Horizontal_ThermalVias
+Molex Sabre Power Connector, 43160-1105, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+77
+5
+Connector_Molex
+Molex_Sabre_43160-1106_1x06_P7.49mm_Horizontal
+Molex Sabre Power Connector, 43160-1106, 6 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+14
+6
+Connector_Molex
+Molex_Sabre_43160-1106_1x06_P7.49mm_Horizontal_ThermalVias
+Molex Sabre Power Connector, 43160-1106, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+92
+6
+Connector_Molex
+Molex_Sabre_43160-2102_1x02_P7.49mm_Vertical
+Molex Sabre Power Connector, 43160-2102, 2 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+6
+2
+Connector_Molex
+Molex_Sabre_43160-2102_1x02_P7.49mm_Vertical_ThermalVias
+Molex Sabre Power Connector, 43160-2102, With thermal vias in pads, 2 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+32
+2
+Connector_Molex
+Molex_Sabre_43160-2103_1x03_P7.49mm_Vertical
+Molex Sabre Power Connector, 43160-2103, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+8
+3
+Connector_Molex
+Molex_Sabre_43160-2103_1x03_P7.49mm_Vertical_ThermalVias
+Molex Sabre Power Connector, 43160-2103, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+47
+3
+Connector_Molex
+Molex_Sabre_43160-2104_1x04_P7.49mm_Vertical
+Molex Sabre Power Connector, 43160-2104, 4 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+10
+4
+Connector_Molex
+Molex_Sabre_43160-2104_1x04_P7.49mm_Vertical_ThermalVias
+Molex Sabre Power Connector, 43160-2104, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+62
+4
+Connector_Molex
+Molex_Sabre_43160-2105_1x05_P7.49mm_Vertical
+Molex Sabre Power Connector, 43160-2105, 5 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+12
+5
+Connector_Molex
+Molex_Sabre_43160-2105_1x05_P7.49mm_Vertical_ThermalVias
+Molex Sabre Power Connector, 43160-2105, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+77
+5
+Connector_Molex
+Molex_Sabre_43160-2106_1x06_P7.49mm_Vertical
+Molex Sabre Power Connector, 43160-2106, 6 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+14
+6
+Connector_Molex
+Molex_Sabre_43160-2106_1x06_P7.49mm_Vertical_ThermalVias
+Molex Sabre Power Connector, 43160-2106, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre side entry
+0
+92
+6
+Connector_Molex
+Molex_Sabre_46007-1102_1x02_P7.49mm_Horizontal
+Molex Sabre Power Connector, 46007-1102, 2 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+4
+2
+Connector_Molex
+Molex_Sabre_46007-1102_1x02_P7.49mm_Horizontal_ThermalVias
+Molex Sabre Power Connector, 46007-1102, With thermal vias in pads, 2 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+30
+2
+Connector_Molex
+Molex_Sabre_46007-1103_1x03_P7.49mm_Horizontal
+Molex Sabre Power Connector, 46007-1103, 3 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+6
+3
+Connector_Molex
+Molex_Sabre_46007-1103_1x03_P7.49mm_Horizontal_ThermalVias
+Molex Sabre Power Connector, 46007-1103, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+45
+3
+Connector_Molex
+Molex_Sabre_46007-1104_1x04_P7.49mm_Horizontal
+Molex Sabre Power Connector, 46007-1104, 4 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+8
+4
+Connector_Molex
+Molex_Sabre_46007-1104_1x04_P7.49mm_Horizontal_ThermalVias
+Molex Sabre Power Connector, 46007-1104, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+60
+4
+Connector_Molex
+Molex_Sabre_46007-1105_1x05_P7.49mm_Horizontal
+Molex Sabre Power Connector, 46007-1105, 5 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+10
+5
+Connector_Molex
+Molex_Sabre_46007-1105_1x05_P7.49mm_Horizontal_ThermalVias
+Molex Sabre Power Connector, 46007-1105, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+75
+5
+Connector_Molex
+Molex_Sabre_46007-1106_1x06_P7.49mm_Horizontal
+Molex Sabre Power Connector, 46007-1106, 6 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+12
+6
+Connector_Molex
+Molex_Sabre_46007-1106_1x06_P7.49mm_Horizontal_ThermalVias
+Molex Sabre Power Connector, 46007-1106, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator
+connector Molex Sabre top entry
+0
+90
+6
+Connector_Molex
+Molex_SlimStack_52991-0208_2x10_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0208, 20 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack vertical
+0
+20
+20
+Connector_Molex
+Molex_SlimStack_52991-0308_2x15_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0308, 30 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack vertical
+0
+30
+30
+Connector_Molex
+Molex_SlimStack_52991-0408_2x20_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0408, 40 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack vertical
+0
+40
+40
+Connector_Molex
+Molex_SlimStack_52991-0508_2x25_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0508, 50 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack vertical
+0
+50
+50
+Connector_Molex
+Molex_SlimStack_52991-0608_2x30_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0608, 60 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack vertical
+0
+60
+60
+Connector_Molex
+Molex_SlimStack_52991-0708_2x35_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0708, 70 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack vertical
+0
+70
+70
+Connector_Molex
+Molex_SlimStack_52991-0808_2x40_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0808, 80 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack vertical
+0
+80
+80
+Connector_Molex
+Molex_SlimStack_54722-0164_2x08_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0164, 16 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+16
+16
+Connector_Molex
+Molex_SlimStack_54722-0204_2x10_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0204, 20 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+20
+20
+Connector_Molex
+Molex_SlimStack_54722-0224_2x11_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0224, 22 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+22
+22
+Connector_Molex
+Molex_SlimStack_54722-0244_2x12_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0244, 24 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+24
+24
+Connector_Molex
+Molex_SlimStack_54722-0304_2x15_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0304, 30 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+30
+30
+Connector_Molex
+Molex_SlimStack_54722-0344_2x17_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0344, 34 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+34
+34
+Connector_Molex
+Molex_SlimStack_54722-0404_2x20_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0404, 40 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+40
+40
+Connector_Molex
+Molex_SlimStack_54722-0504_2x25_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0504, 50 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+50
+50
+Connector_Molex
+Molex_SlimStack_54722-0604_2x30_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0604, 60 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+60
+60
+Connector_Molex
+Molex_SlimStack_54722-0804_2x40_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0804, 80 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+80
+80
+Connector_Molex
+Molex_SlimStack_55560-0161_2x08_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0161, 16 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+16
+16
+Connector_Molex
+Molex_SlimStack_55560-0201_2x10_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0201, 20 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+20
+20
+Connector_Molex
+Molex_SlimStack_55560-0221_2x11_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0221, 22 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+22
+22
+Connector_Molex
+Molex_SlimStack_55560-0241_2x12_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0241, 24 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+24
+24
+Connector_Molex
+Molex_SlimStack_55560-0301_2x15_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0301, 30 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+30
+30
+Connector_Molex
+Molex_SlimStack_55560-0341_2x17_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0341, 34 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+34
+34
+Connector_Molex
+Molex_SlimStack_55560-0401_2x20_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0401, 40 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+40
+40
+Connector_Molex
+Molex_SlimStack_55560-0501_2x25_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0501, 50 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+50
+50
+Connector_Molex
+Molex_SlimStack_55560-0601_2x30_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0601, 60 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+60
+60
+Connector_Molex
+Molex_SlimStack_55560-0801_2x40_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0801, 80 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+80
+80
+Connector_Molex
+Molex_SlimStack_501920-3001_2x15_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 501920-3001, 30 Pins (http://www.molex.com/pdm_docs/sd/5019204001_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+30
+30
+Connector_Molex
+Molex_SlimStack_501920-4001_2x20_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 501920-4001, 40 Pins (http://www.molex.com/pdm_docs/sd/5019204001_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+40
+40
+Connector_Molex
+Molex_SlimStack_501920-5001_2x25_P0.50mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 501920-5001, 50 Pins (http://www.molex.com/pdm_docs/sd/5019204001_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+50
+50
+Connector_Molex
+Molex_SlimStack_502426-0810_2x04_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-0810, 8 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+8
+8
+Connector_Molex
+Molex_SlimStack_502426-1410_2x07_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-1410, 14 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+14
+14
+Connector_Molex
+Molex_SlimStack_502426-2010_2x10_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-2010, 20 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+20
+20
+Connector_Molex
+Molex_SlimStack_502426-2210_2x11_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-2210, 22 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+22
+22
+Connector_Molex
+Molex_SlimStack_502426-2410_2x12_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-2410, 24 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+24
+24
+Connector_Molex
+Molex_SlimStack_502426-2610_2x13_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-2610, 26 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+26
+26
+Connector_Molex
+Molex_SlimStack_502426-3010_2x15_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-3010, 30 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+30
+30
+Connector_Molex
+Molex_SlimStack_502426-3210_2x16_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-3210, 32 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+32
+32
+Connector_Molex
+Molex_SlimStack_502426-3410_2x17_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-3410, 34 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+34
+34
+Connector_Molex
+Molex_SlimStack_502426-4010_2x20_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-4010, 40 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+40
+40
+Connector_Molex
+Molex_SlimStack_502426-4410_2x22_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-4410, 44 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+44
+44
+Connector_Molex
+Molex_SlimStack_502426-5010_2x25_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-5010, 50 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+50
+50
+Connector_Molex
+Molex_SlimStack_502426-6010_2x30_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-6010, 60 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+60
+60
+Connector_Molex
+Molex_SlimStack_502426-6410_2x32_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-6410, 64 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+64
+64
+Connector_Molex
+Molex_SlimStack_502426-8010_2x40_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-8010, 80 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+80
+80
+Connector_Molex
+Molex_SlimStack_502430-0820_2x04_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-0820, 8 Pins (http://www.molex.com/pdm_docs/sd/5024300820_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+8
+8
+Connector_Molex
+Molex_SlimStack_502430-1410_2x07_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-1410, 14 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+14
+14
+Connector_Molex
+Molex_SlimStack_502430-2010_2x10_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-2010, 20 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+20
+20
+Connector_Molex
+Molex_SlimStack_502430-2210_2x11_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-2210, 22 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+22
+22
+Connector_Molex
+Molex_SlimStack_502430-2410_2x12_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-2410, 24 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+24
+24
+Connector_Molex
+Molex_SlimStack_502430-2610_2x13_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-2610, 26 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+26
+26
+Connector_Molex
+Molex_SlimStack_502430-3010_2x15_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-3010, 30 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+30
+30
+Connector_Molex
+Molex_SlimStack_502430-3210_2x16_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-3210, 32 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+32
+32
+Connector_Molex
+Molex_SlimStack_502430-3410_2x17_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-3410, 34 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+34
+34
+Connector_Molex
+Molex_SlimStack_502430-4010_2x20_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-4010, 40 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+40
+40
+Connector_Molex
+Molex_SlimStack_502430-4410_2x22_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-4410, 44 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+44
+44
+Connector_Molex
+Molex_SlimStack_502430-5010_2x25_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-5010, 50 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+50
+50
+Connector_Molex
+Molex_SlimStack_502430-6010_2x30_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-6010, 60 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+60
+60
+Connector_Molex
+Molex_SlimStack_502430-6410_2x32_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-6410, 64 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+64
+64
+Connector_Molex
+Molex_SlimStack_502430-8010_2x40_P0.40mm_Vertical
+Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-8010, 80 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator
+connector Molex SlimStack side entry
+0
+80
+80
+Connector_Multicomp
+Multicomp_MC9A12-1034_2x05_P2.54mm_Vertical
+http://www.farnell.com/datasheets/1520732.pdf
+connector multicomp MC9A MC9A12
+0
+10
+10
+Connector_Multicomp
+Multicomp_MC9A12-1434_2x07_P2.54mm_Vertical
+http://www.farnell.com/datasheets/1520732.pdf
+connector multicomp MC9A MC9A12
+0
+14
+14
+Connector_Multicomp
+Multicomp_MC9A12-1634_2x08_P2.54mm_Vertical
+http://www.farnell.com/datasheets/1520732.pdf
+connector multicomp MC9A MC9A12
+0
+16
+16
+Connector_Multicomp
+Multicomp_MC9A12-2034_2x10_P2.54mm_Vertical
+http://www.farnell.com/datasheets/1520732.pdf
+connector multicomp MC9A MC9A12
+0
+20
+20
+Connector_Multicomp
+Multicomp_MC9A12-2634_2x13_P2.54mm_Vertical
+http://www.farnell.com/datasheets/1520732.pdf
+connector multicomp MC9A MC9A12
+0
+26
+26
+Connector_Multicomp
+Multicomp_MC9A12-3434_2x17_P2.54mm_Vertical
+http://www.farnell.com/datasheets/1520732.pdf
+connector multicomp MC9A MC9A12
+0
+34
+34
+Connector_Multicomp
+Multicomp_MC9A12-4034_2x20_P2.54mm_Vertical
+http://www.farnell.com/datasheets/1520732.pdf
+connector multicomp MC9A MC9A12
+0
+40
+40
+Connector_Multicomp
+Multicomp_MC9A12-5034_2x25_P2.54mm_Vertical
+http://www.farnell.com/datasheets/1520732.pdf
+connector multicomp MC9A MC9A12
+0
+50
+50
+Connector_Multicomp
+Multicomp_MC9A12-6034_2x30_P2.54mm_Vertical
+http://www.farnell.com/datasheets/1520732.pdf
+connector multicomp MC9A MC9A12
+0
+60
+60
+Connector_Multicomp
+Multicomp_MC9A12-6434_2x32_P2.54mm_Vertical
+http://www.farnell.com/datasheets/1520732.pdf
+connector multicomp MC9A MC9A12
+0
+64
+64
+Connector_Multicomp
+Multicomp_MC9A22-1034_2x05_P2.54mm_Horizontal
+http://www.farnell.com/cad/360651.pdf
+connector multicomp MC9A MC9A22
+0
+10
+10
+Connector_Multicomp
+Multicomp_MC9A22-1434_2x07_P2.54mm_Horizontal
+http://www.farnell.com/cad/360651.pdf
+connector multicomp MC9A MC9A22
+0
+14
+14
+Connector_Multicomp
+Multicomp_MC9A22-1634_2x08_P2.54mm_Horizontal
+http://www.farnell.com/cad/360651.pdf
+connector multicomp MC9A MC9A22
+0
+16
+16
+Connector_Multicomp
+Multicomp_MC9A22-2034_2x10_P2.54mm_Horizontal
+http://www.farnell.com/cad/360651.pdf
+connector multicomp MC9A MC9A22
+0
+20
+20
+Connector_Multicomp
+Multicomp_MC9A22-2634_2x13_P2.54mm_Horizontal
+http://www.farnell.com/cad/360651.pdf
+connector multicomp MC9A MC9A22
+0
+26
+26
+Connector_Multicomp
+Multicomp_MC9A22-3434_2x17_P2.54mm_Horizontal
+http://www.farnell.com/cad/360651.pdf
+connector multicomp MC9A MC9A22
+0
+34
+34
+Connector_Multicomp
+Multicomp_MC9A22-4034_2x20_P2.54mm_Horizontal
+http://www.farnell.com/cad/360651.pdf
+connector multicomp MC9A MC9A22
+0
+40
+40
+Connector_Multicomp
+Multicomp_MC9A22-5034_2x25_P2.54mm_Horizontal
+http://www.farnell.com/cad/360651.pdf
+connector multicomp MC9A MC9A22
+0
+50
+50
+Connector_Multicomp
+Multicomp_MC9A22-6034_2x30_P2.54mm_Horizontal
+http://www.farnell.com/cad/360651.pdf
+connector multicomp MC9A MC9A22
+0
+60
+60
+Connector_PCBEdge
+4UCON_10156_2x40_P1.27mm_Socket_Horizontal
+4UCON 10156 Card edge socket with 80 contacts (40 each side), through-hole, http://www.4uconnector.com/online/object/4udrawing/10156.pdf
+4UCON 10156 Card edge socket with 80 contacts
+0
+80
+80
+Connector_PCBEdge
+BUS_AT
+AT ISA 16 bits Bus Edge Connector
+BUS ISA AT Edge connector
+0
+98
+98
+Connector_PCBEdge
+BUS_PCI
+PCI bus Edge Connector
+PCI bus Edge Connector
+0
+240
+120
+Connector_PCBEdge
+BUS_PCIexpress_x1
+PCIexpress Bus Edge Connector x1 http://www.ritrontek.com/uploadfile/2016/1026/20161026105231124.pdf#page=70
+PCIe
+0
+36
+36
+Connector_PCBEdge
+BUS_PCIexpress_x4
+PCIexpress Bus Edge Connector x1 http://www.ritrontek.com/uploadfile/2016/1026/20161026105231124.pdf#page=70
+PCIe
+0
+64
+64
+Connector_PCBEdge
+BUS_PCIexpress_x8
+PCIexpress Bus Edge Connector x1 http://www.ritrontek.com/uploadfile/2016/1026/20161026105231124.pdf#page=70
+PCIe
+0
+98
+98
+Connector_PCBEdge
+BUS_PCIexpress_x16
+PCIexpress Bus Edge Connector x1 http://www.ritrontek.com/uploadfile/2016/1026/20161026105231124.pdf#page=70
+PCIe
+0
+164
+164
+Connector_PCBEdge
+Samtec_MECF-05-0_-L-DV_2x05_P1.27mm_Polarized_Edge
+Highspeed card edge connector for PCB's with 05 contacts (polarized)
+conn samtec card-edge high-speed
+0
+8
+8
+Connector_PCBEdge
+Samtec_MECF-05-0_-NP-L-DV_2x05_P1.27mm_Edge
+Highspeed card edge connector for PCB's with 05 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+10
+10
+Connector_PCBEdge
+Samtec_MECF-05-01-L-DV-WT_2x05_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 05 contacts (polarized)
+conn samtec card-edge high-speed
+0
+10
+8
+Connector_PCBEdge
+Samtec_MECF-05-01-L-DV_2x05_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 05 contacts (polarized)
+conn samtec card-edge high-speed
+0
+8
+8
+Connector_PCBEdge
+Samtec_MECF-05-01-NP-L-DV-WT_2x05_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 05 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+12
+10
+Connector_PCBEdge
+Samtec_MECF-05-01-NP-L-DV_2x05_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 05 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+10
+10
+Connector_PCBEdge
+Samtec_MECF-05-02-L-DV-WT_2x05_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 05 contacts (polarized)
+conn samtec card-edge high-speed
+0
+10
+8
+Connector_PCBEdge
+Samtec_MECF-05-02-L-DV_2x05_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 05 contacts (polarized)
+conn samtec card-edge high-speed
+0
+8
+8
+Connector_PCBEdge
+Samtec_MECF-05-02-NP-L-DV-WT_2x05_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 05 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+12
+10
+Connector_PCBEdge
+Samtec_MECF-05-02-NP-L-DV_2x05_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 05 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+10
+10
+Connector_PCBEdge
+Samtec_MECF-08-0_-L-DV_2x08_P1.27mm_Polarized_Edge
+Highspeed card edge connector for PCB's with 08 contacts (polarized)
+conn samtec card-edge high-speed
+0
+14
+14
+Connector_PCBEdge
+Samtec_MECF-08-0_-NP-L-DV_2x08_P1.27mm_Edge
+Highspeed card edge connector for PCB's with 08 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+16
+16
+Connector_PCBEdge
+Samtec_MECF-08-01-L-DV-WT_2x08_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 08 contacts (polarized)
+conn samtec card-edge high-speed
+0
+16
+14
+Connector_PCBEdge
+Samtec_MECF-08-01-L-DV_2x08_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 08 contacts (polarized)
+conn samtec card-edge high-speed
+0
+14
+14
+Connector_PCBEdge
+Samtec_MECF-08-01-NP-L-DV-WT_2x08_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 08 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+18
+16
+Connector_PCBEdge
+Samtec_MECF-08-01-NP-L-DV_2x08_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 08 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+16
+16
+Connector_PCBEdge
+Samtec_MECF-08-02-L-DV-WT_2x08_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 08 contacts (polarized)
+conn samtec card-edge high-speed
+0
+16
+14
+Connector_PCBEdge
+Samtec_MECF-08-02-L-DV_2x08_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 08 contacts (polarized)
+conn samtec card-edge high-speed
+0
+14
+14
+Connector_PCBEdge
+Samtec_MECF-08-02-NP-L-DV-WT_2x08_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 08 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+18
+16
+Connector_PCBEdge
+Samtec_MECF-08-02-NP-L-DV_2x08_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 08 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+16
+16
+Connector_PCBEdge
+Samtec_MECF-20-0_-L-DV_2x20_P1.27mm_Polarized_Edge
+Highspeed card edge connector for PCB's with 20 contacts (polarized)
+conn samtec card-edge high-speed
+0
+38
+38
+Connector_PCBEdge
+Samtec_MECF-20-0_-NP-L-DV_2x20_P1.27mm_Edge
+Highspeed card edge connector for PCB's with 20 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+40
+40
+Connector_PCBEdge
+Samtec_MECF-20-01-L-DV-WT_2x20_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 20 contacts (polarized)
+conn samtec card-edge high-speed
+0
+40
+38
+Connector_PCBEdge
+Samtec_MECF-20-01-L-DV_2x20_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 20 contacts (polarized)
+conn samtec card-edge high-speed
+0
+38
+38
+Connector_PCBEdge
+Samtec_MECF-20-01-NP-L-DV-WT_2x20_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 20 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+42
+40
+Connector_PCBEdge
+Samtec_MECF-20-01-NP-L-DV_2x20_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 20 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+40
+40
+Connector_PCBEdge
+Samtec_MECF-20-02-L-DV-WT_2x20_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 20 contacts (polarized)
+conn samtec card-edge high-speed
+0
+40
+38
+Connector_PCBEdge
+Samtec_MECF-20-02-L-DV_2x20_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 20 contacts (polarized)
+conn samtec card-edge high-speed
+0
+38
+38
+Connector_PCBEdge
+Samtec_MECF-20-02-NP-L-DV-WT_2x20_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 20 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+42
+40
+Connector_PCBEdge
+Samtec_MECF-20-02-NP-L-DV_2x20_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 20 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+40
+40
+Connector_PCBEdge
+Samtec_MECF-30-0_-L-DV_2x30_P1.27mm_Polarized_Edge
+Highspeed card edge connector for PCB's with 30 contacts (polarized)
+conn samtec card-edge high-speed
+0
+58
+58
+Connector_PCBEdge
+Samtec_MECF-30-0_-NP-L-DV_2x30_P1.27mm_Edge
+Highspeed card edge connector for PCB's with 30 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+60
+60
+Connector_PCBEdge
+Samtec_MECF-30-01-L-DV-WT_2x30_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 30 contacts (polarized)
+conn samtec card-edge high-speed
+0
+60
+58
+Connector_PCBEdge
+Samtec_MECF-30-01-L-DV_2x30_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 30 contacts (polarized)
+conn samtec card-edge high-speed
+0
+58
+58
+Connector_PCBEdge
+Samtec_MECF-30-01-NP-L-DV-WT_2x30_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 30 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+62
+60
+Connector_PCBEdge
+Samtec_MECF-30-01-NP-L-DV_2x30_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 30 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+60
+60
+Connector_PCBEdge
+Samtec_MECF-30-02-L-DV-WT_2x30_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 30 contacts (polarized)
+conn samtec card-edge high-speed
+0
+60
+58
+Connector_PCBEdge
+Samtec_MECF-30-02-L-DV_2x30_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 30 contacts (polarized)
+conn samtec card-edge high-speed
+0
+58
+58
+Connector_PCBEdge
+Samtec_MECF-30-02-NP-L-DV-WT_2x30_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 30 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+62
+60
+Connector_PCBEdge
+Samtec_MECF-30-02-NP-L-DV_2x30_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 30 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+60
+60
+Connector_PCBEdge
+Samtec_MECF-40-0_-L-DV_2x40_P1.27mm_Polarized_Edge
+Highspeed card edge connector for PCB's with 40 contacts (polarized)
+conn samtec card-edge high-speed
+0
+78
+78
+Connector_PCBEdge
+Samtec_MECF-40-0_-NP-L-DV_2x40_P1.27mm_Edge
+Highspeed card edge connector for PCB's with 40 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+80
+80
+Connector_PCBEdge
+Samtec_MECF-40-01-L-DV-WT_2x40_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 40 contacts (polarized)
+conn samtec card-edge high-speed
+0
+80
+78
+Connector_PCBEdge
+Samtec_MECF-40-01-L-DV_2x40_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 40 contacts (polarized)
+conn samtec card-edge high-speed
+0
+78
+78
+Connector_PCBEdge
+Samtec_MECF-40-01-NP-L-DV-WT_2x40_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 40 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+82
+80
+Connector_PCBEdge
+Samtec_MECF-40-01-NP-L-DV_2x40_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 40 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+80
+80
+Connector_PCBEdge
+Samtec_MECF-40-02-L-DV-WT_2x40_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 40 contacts (polarized)
+conn samtec card-edge high-speed
+0
+80
+78
+Connector_PCBEdge
+Samtec_MECF-40-02-L-DV_2x40_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 40 contacts (polarized)
+conn samtec card-edge high-speed
+0
+78
+78
+Connector_PCBEdge
+Samtec_MECF-40-02-NP-L-DV-WT_2x40_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 40 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+82
+80
+Connector_PCBEdge
+Samtec_MECF-40-02-NP-L-DV_2x40_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 40 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+80
+80
+Connector_PCBEdge
+Samtec_MECF-50-0_-L-DV_2x50_P1.27mm_Polarized_Edge
+Highspeed card edge connector for PCB's with 50 contacts (polarized)
+conn samtec card-edge high-speed
+0
+98
+98
+Connector_PCBEdge
+Samtec_MECF-50-0_-NP-L-DV_2x50_P1.27mm_Edge
+Highspeed card edge connector for PCB's with 50 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+100
+100
+Connector_PCBEdge
+Samtec_MECF-50-01-L-DV-WT_2x50_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 50 contacts (polarized)
+conn samtec card-edge high-speed
+0
+100
+98
+Connector_PCBEdge
+Samtec_MECF-50-01-L-DV_2x50_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 50 contacts (polarized)
+conn samtec card-edge high-speed
+0
+98
+98
+Connector_PCBEdge
+Samtec_MECF-50-01-NP-L-DV-WT_2x50_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 50 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+102
+100
+Connector_PCBEdge
+Samtec_MECF-50-01-NP-L-DV_2x50_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 50 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+100
+100
+Connector_PCBEdge
+Samtec_MECF-50-02-L-DV-WT_2x50_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 50 contacts (polarized)
+conn samtec card-edge high-speed
+0
+100
+98
+Connector_PCBEdge
+Samtec_MECF-50-02-L-DV_2x50_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 50 contacts (polarized)
+conn samtec card-edge high-speed
+0
+98
+98
+Connector_PCBEdge
+Samtec_MECF-50-02-NP-L-DV-WT_2x50_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 50 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+102
+100
+Connector_PCBEdge
+Samtec_MECF-50-02-NP-L-DV_2x50_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 50 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+100
+100
+Connector_PCBEdge
+Samtec_MECF-60-0_-L-DV_2x60_P1.27mm_Polarized_Edge
+Highspeed card edge connector for PCB's with 60 contacts (polarized)
+conn samtec card-edge high-speed
+0
+116
+116
+Connector_PCBEdge
+Samtec_MECF-60-0_-NP-L-DV_2x60_P1.27mm_Edge
+Highspeed card edge connector for PCB's with 60 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+120
+120
+Connector_PCBEdge
+Samtec_MECF-60-01-L-DV-WT_2x60_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 60 contacts (polarized)
+conn samtec card-edge high-speed
+0
+118
+116
+Connector_PCBEdge
+Samtec_MECF-60-01-L-DV_2x60_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 60 contacts (polarized)
+conn samtec card-edge high-speed
+0
+116
+116
+Connector_PCBEdge
+Samtec_MECF-60-01-NP-L-DV-WT_2x60_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 60 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+122
+120
+Connector_PCBEdge
+Samtec_MECF-60-01-NP-L-DV_2x60_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 60 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+120
+120
+Connector_PCBEdge
+Samtec_MECF-60-02-L-DV-WT_2x60_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 60 contacts (polarized)
+conn samtec card-edge high-speed
+0
+118
+116
+Connector_PCBEdge
+Samtec_MECF-60-02-L-DV_2x60_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 60 contacts (polarized)
+conn samtec card-edge high-speed
+0
+116
+116
+Connector_PCBEdge
+Samtec_MECF-60-02-NP-L-DV-WT_2x60_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 60 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+122
+120
+Connector_PCBEdge
+Samtec_MECF-60-02-NP-L-DV_2x60_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 60 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+120
+120
+Connector_PCBEdge
+Samtec_MECF-70-0_-L-DV_2x70_P1.27mm_Polarized_Edge
+Highspeed card edge connector for PCB's with 70 contacts (polarized)
+conn samtec card-edge high-speed
+0
+136
+136
+Connector_PCBEdge
+Samtec_MECF-70-0_-NP-L-DV_2x70_P1.27mm_Edge
+Highspeed card edge connector for PCB's with 70 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+140
+140
+Connector_PCBEdge
+Samtec_MECF-70-01-L-DV-WT_2x70_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 70 contacts (polarized)
+conn samtec card-edge high-speed
+0
+138
+136
+Connector_PCBEdge
+Samtec_MECF-70-01-L-DV_2x70_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 70 contacts (polarized)
+conn samtec card-edge high-speed
+0
+136
+136
+Connector_PCBEdge
+Samtec_MECF-70-01-NP-L-DV-WT_2x70_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 70 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+142
+140
+Connector_PCBEdge
+Samtec_MECF-70-01-NP-L-DV_2x70_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 1.6mm PCB's with 70 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+140
+140
+Connector_PCBEdge
+Samtec_MECF-70-02-L-DV-WT_2x70_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 70 contacts (polarized)
+conn samtec card-edge high-speed
+0
+138
+136
+Connector_PCBEdge
+Samtec_MECF-70-02-L-DV_2x70_P1.27mm_Polarized_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 70 contacts (polarized)
+conn samtec card-edge high-speed
+0
+136
+136
+Connector_PCBEdge
+Samtec_MECF-70-02-NP-L-DV-WT_2x70_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 70 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+142
+140
+Connector_PCBEdge
+Samtec_MECF-70-02-NP-L-DV_2x70_P1.27mm_Socket_Horizontal
+Highspeed card edge connector for 2.4mm PCB's with 70 contacts (not polarized)
+conn samtec card-edge high-speed
+0
+140
+140
+Connector_PCBEdge
+molex_EDGELOCK_2-CKT
+https://www.molex.com/pdm_docs/sd/2008900106_sd.pdf
+Connector PCBEdge molex EDGELOCK
+0
+2
+2
+Connector_PCBEdge
+molex_EDGELOCK_4-CKT
+https://www.molex.com/pdm_docs/sd/2008900106_sd.pdf
+Connector PCBEdge molex EDGELOCK
+0
+4
+4
+Connector_PCBEdge
+molex_EDGELOCK_6-CKT
+https://www.molex.com/pdm_docs/sd/2008900106_sd.pdf
+Connector PCBEdge molex EDGELOCK
+0
+6
+6
+Connector_PCBEdge
+molex_EDGELOCK_8-CKT
+https://www.molex.com/pdm_docs/sd/2008900106_sd.pdf
+Connector PCBEdge molex EDGELOCK
+0
+8
+8
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_2-G-7,62_1x02_P7.62mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/2-G-7,62; number of pins: 02; pin pitch: 7.62mm; Angled || order number: 1766233 12A 630V
+phoenix_contact connector GMSTBA_01x02_G_7.62mm
+0
+2
+2
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_2-G_1x02_P7.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/2-G; number of pins: 02; pin pitch: 7.50mm; Angled || order number: 1766343 12A 630V
+phoenix_contact connector GMSTBA_01x02_G_7.50mm
+0
+2
+2
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_3-G-7,62_1x03_P7.62mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/3-G-7,62; number of pins: 03; pin pitch: 7.62mm; Angled || order number: 1766246 12A 630V
+phoenix_contact connector GMSTBA_01x03_G_7.62mm
+0
+3
+3
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_3-G_1x03_P7.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/3-G; number of pins: 03; pin pitch: 7.50mm; Angled || order number: 1766356 12A 630V
+phoenix_contact connector GMSTBA_01x03_G_7.50mm
+0
+3
+3
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_4-G-7,62_1x04_P7.62mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/4-G-7,62; number of pins: 04; pin pitch: 7.62mm; Angled || order number: 1766259 12A 630V
+phoenix_contact connector GMSTBA_01x04_G_7.62mm
+0
+4
+4
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_4-G_1x04_P7.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/4-G; number of pins: 04; pin pitch: 7.50mm; Angled || order number: 1766369 12A 630V
+phoenix_contact connector GMSTBA_01x04_G_7.50mm
+0
+4
+4
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_5-G-7,62_1x05_P7.62mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/5-G-7,62; number of pins: 05; pin pitch: 7.62mm; Angled || order number: 1766262 12A 630V
+phoenix_contact connector GMSTBA_01x05_G_7.62mm
+0
+5
+5
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_5-G_1x05_P7.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/5-G; number of pins: 05; pin pitch: 7.50mm; Angled || order number: 1766372 12A 630V
+phoenix_contact connector GMSTBA_01x05_G_7.50mm
+0
+5
+5
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_6-G-7,62_1x06_P7.62mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/6-G-7,62; number of pins: 06; pin pitch: 7.62mm; Angled || order number: 1766275 12A 630V
+phoenix_contact connector GMSTBA_01x06_G_7.62mm
+0
+6
+6
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_6-G_1x06_P7.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/6-G; number of pins: 06; pin pitch: 7.50mm; Angled || order number: 1766385 12A 630V
+phoenix_contact connector GMSTBA_01x06_G_7.50mm
+0
+6
+6
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_7-G-7,62_1x07_P7.62mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/7-G-7,62; number of pins: 07; pin pitch: 7.62mm; Angled || order number: 1766288 12A 630V
+phoenix_contact connector GMSTBA_01x07_G_7.62mm
+0
+7
+7
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_7-G_1x07_P7.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/7-G; number of pins: 07; pin pitch: 7.50mm; Angled || order number: 1766398 12A 630V
+phoenix_contact connector GMSTBA_01x07_G_7.50mm
+0
+7
+7
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_8-G-7,62_1x08_P7.62mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/8-G-7,62; number of pins: 08; pin pitch: 7.62mm; Angled || order number: 1766291 12A 630V
+phoenix_contact connector GMSTBA_01x08_G_7.62mm
+0
+8
+8
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_8-G_1x08_P7.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/8-G; number of pins: 08; pin pitch: 7.50mm; Angled || order number: 1766408 12A 630V
+phoenix_contact connector GMSTBA_01x08_G_7.50mm
+0
+8
+8
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_9-G-7,62_1x09_P7.62mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/9-G-7,62; number of pins: 09; pin pitch: 7.62mm; Angled || order number: 1766301 12A 630V
+phoenix_contact connector GMSTBA_01x09_G_7.62mm
+0
+9
+9
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_9-G_1x09_P7.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/9-G; number of pins: 09; pin pitch: 7.50mm; Angled || order number: 1766411 12A 630V
+phoenix_contact connector GMSTBA_01x09_G_7.50mm
+0
+9
+9
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_10-G-7,62_1x10_P7.62mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/10-G-7,62; number of pins: 10; pin pitch: 7.62mm; Angled || order number: 1766314 12A 630V
+phoenix_contact connector GMSTBA_01x10_G_7.62mm
+0
+10
+10
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_10-G_1x10_P7.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/10-G; number of pins: 10; pin pitch: 7.50mm; Angled || order number: 1766424 12A 630V
+phoenix_contact connector GMSTBA_01x10_G_7.50mm
+0
+10
+10
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_11-G-7,62_1x11_P7.62mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/11-G-7,62; number of pins: 11; pin pitch: 7.62mm; Angled || order number: 1766327 12A 630V
+phoenix_contact connector GMSTBA_01x11_G_7.62mm
+0
+11
+11
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_11-G_1x11_P7.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/11-G; number of pins: 11; pin pitch: 7.50mm; Angled || order number: 1766437 12A 630V
+phoenix_contact connector GMSTBA_01x11_G_7.50mm
+0
+11
+11
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_12-G-7,62_1x12_P7.62mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/12-G-7,62; number of pins: 12; pin pitch: 7.62mm; Angled || order number: 1766330 12A 630V
+phoenix_contact connector GMSTBA_01x12_G_7.62mm
+0
+12
+12
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBA_2,5_12-G_1x12_P7.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: GMSTBA_2,5/12-G; number of pins: 12; pin pitch: 7.50mm; Angled || order number: 1766440 12A 630V
+phoenix_contact connector GMSTBA_01x12_G_7.50mm
+0
+12
+12
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_2-G-7,62_1x02_P7.62mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/2-G-7,62; number of pins: 02; pin pitch: 7.62mm; Vertical || order number: 1766770 12A 630V
+phoenix_contact connector GMSTBVA_01x02_G_7.62mm
+0
+2
+2
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_2-G_1x02_P7.50mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/2-G; number of pins: 02; pin pitch: 7.50mm; Vertical || order number: 1766660 12A 630V
+phoenix_contact connector GMSTBVA_01x02_G_7.50mm
+0
+2
+2
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_3-G-7,62_1x03_P7.62mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/3-G-7,62; number of pins: 03; pin pitch: 7.62mm; Vertical || order number: 1766783 12A 630V
+phoenix_contact connector GMSTBVA_01x03_G_7.62mm
+0
+3
+3
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_3-G_1x03_P7.50mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/3-G; number of pins: 03; pin pitch: 7.50mm; Vertical || order number: 1766673 12A 630V
+phoenix_contact connector GMSTBVA_01x03_G_7.50mm
+0
+3
+3
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_4-G-7,62_1x04_P7.62mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/4-G-7,62; number of pins: 04; pin pitch: 7.62mm; Vertical || order number: 1766796 12A 630V
+phoenix_contact connector GMSTBVA_01x04_G_7.62mm
+0
+4
+4
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_4-G_1x04_P7.50mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/4-G; number of pins: 04; pin pitch: 7.50mm; Vertical || order number: 1766686 12A 630V
+phoenix_contact connector GMSTBVA_01x04_G_7.50mm
+0
+4
+4
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_5-G-7,62_1x05_P7.62mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/5-G-7,62; number of pins: 05; pin pitch: 7.62mm; Vertical || order number: 1766806 12A 630V
+phoenix_contact connector GMSTBVA_01x05_G_7.62mm
+0
+5
+5
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_5-G_1x05_P7.50mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/5-G; number of pins: 05; pin pitch: 7.50mm; Vertical || order number: 1766699 12A 630V
+phoenix_contact connector GMSTBVA_01x05_G_7.50mm
+0
+5
+5
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_6-G-7,62_1x06_P7.62mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/6-G-7,62; number of pins: 06; pin pitch: 7.62mm; Vertical || order number: 1766819 12A 630V
+phoenix_contact connector GMSTBVA_01x06_G_7.62mm
+0
+6
+6
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_6-G_1x06_P7.50mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/6-G; number of pins: 06; pin pitch: 7.50mm; Vertical || order number: 1766709 12A 630V
+phoenix_contact connector GMSTBVA_01x06_G_7.50mm
+0
+6
+6
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_7-G-7,62_1x07_P7.62mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/7-G-7,62; number of pins: 07; pin pitch: 7.62mm; Vertical || order number: 1766822 12A 630V
+phoenix_contact connector GMSTBVA_01x07_G_7.62mm
+0
+7
+7
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_7-G_1x07_P7.50mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/7-G; number of pins: 07; pin pitch: 7.50mm; Vertical || order number: 1766712 12A 630V
+phoenix_contact connector GMSTBVA_01x07_G_7.50mm
+0
+7
+7
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_8-G-7,62_1x08_P7.62mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/8-G-7,62; number of pins: 08; pin pitch: 7.62mm; Vertical || order number: 1766835 12A 630V
+phoenix_contact connector GMSTBVA_01x08_G_7.62mm
+0
+8
+8
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_8-G_1x08_P7.50mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/8-G; number of pins: 08; pin pitch: 7.50mm; Vertical || order number: 1766725 12A 630V
+phoenix_contact connector GMSTBVA_01x08_G_7.50mm
+0
+8
+8
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_9-G-7,62_1x09_P7.62mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/9-G-7,62; number of pins: 09; pin pitch: 7.62mm; Vertical || order number: 1766848 12A 630V
+phoenix_contact connector GMSTBVA_01x09_G_7.62mm
+0
+9
+9
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_9-G_1x09_P7.50mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/9-G; number of pins: 09; pin pitch: 7.50mm; Vertical || order number: 1766738 12A 630V
+phoenix_contact connector GMSTBVA_01x09_G_7.50mm
+0
+9
+9
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_10-G-7,62_1x10_P7.62mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/10-G-7,62; number of pins: 10; pin pitch: 7.62mm; Vertical || order number: 1766851 12A 630V
+phoenix_contact connector GMSTBVA_01x10_G_7.62mm
+0
+10
+10
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_10-G_1x10_P7.50mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/10-G; number of pins: 10; pin pitch: 7.50mm; Vertical || order number: 1766741 12A 630V
+phoenix_contact connector GMSTBVA_01x10_G_7.50mm
+0
+10
+10
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_11-G-7,62_1x11_P7.62mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/11-G-7,62; number of pins: 11; pin pitch: 7.62mm; Vertical || order number: 1766864 12A 630V
+phoenix_contact connector GMSTBVA_01x11_G_7.62mm
+0
+11
+11
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_11-G_1x11_P7.50mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/11-G; number of pins: 11; pin pitch: 7.50mm; Vertical || order number: 1766754 12A 630V
+phoenix_contact connector GMSTBVA_01x11_G_7.50mm
+0
+11
+11
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_12-G-7,62_1x12_P7.62mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/12-G-7,62; number of pins: 12; pin pitch: 7.62mm; Vertical || order number: 1766877 12A 630V
+phoenix_contact connector GMSTBVA_01x12_G_7.62mm
+0
+12
+12
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBVA_2,5_12-G_1x12_P7.50mm_Vertical
+Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/12-G; number of pins: 12; pin pitch: 7.50mm; Vertical || order number: 1766767 12A 630V
+phoenix_contact connector GMSTBVA_01x12_G_7.50mm
+0
+12
+12
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_2-GF-7,62_1x02_P7.62mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/2-GF-7,62; number of pins: 02; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829154 12A 630V
+phoenix_contact connector GMSTBV_01x02_GF_7.62mm
+0
+2
+2
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_2-GF-7,62_1x02_P7.62mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/2-GF-7,62; number of pins: 02; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829154 12A 630V
+phoenix_contact connector GMSTBV_01x02_GF_7.62mm_MH
+0
+2
+2
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_3-GF-7,62_1x03_P7.62mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/3-GF-7,62; number of pins: 03; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829167 12A 630V
+phoenix_contact connector GMSTBV_01x03_GF_7.62mm
+0
+3
+3
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_3-GF-7,62_1x03_P7.62mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/3-GF-7,62; number of pins: 03; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829167 12A 630V
+phoenix_contact connector GMSTBV_01x03_GF_7.62mm_MH
+0
+3
+3
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_4-GF-7,62_1x04_P7.62mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/4-GF-7,62; number of pins: 04; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829170 12A 630V
+phoenix_contact connector GMSTBV_01x04_GF_7.62mm
+0
+4
+4
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_4-GF-7,62_1x04_P7.62mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/4-GF-7,62; number of pins: 04; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829170 12A 630V
+phoenix_contact connector GMSTBV_01x04_GF_7.62mm_MH
+0
+4
+4
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_5-GF-7,62_1x05_P7.62mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/5-GF-7,62; number of pins: 05; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829183 12A 630V
+phoenix_contact connector GMSTBV_01x05_GF_7.62mm
+0
+5
+5
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_5-GF-7,62_1x05_P7.62mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/5-GF-7,62; number of pins: 05; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829183 12A 630V
+phoenix_contact connector GMSTBV_01x05_GF_7.62mm_MH
+0
+5
+5
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_6-GF-7,62_1x06_P7.62mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/6-GF-7,62; number of pins: 06; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829196 12A 630V
+phoenix_contact connector GMSTBV_01x06_GF_7.62mm
+0
+6
+6
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_6-GF-7,62_1x06_P7.62mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/6-GF-7,62; number of pins: 06; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829196 12A 630V
+phoenix_contact connector GMSTBV_01x06_GF_7.62mm_MH
+0
+6
+6
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_7-GF-7,62_1x07_P7.62mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/7-GF-7,62; number of pins: 07; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829206 12A 630V
+phoenix_contact connector GMSTBV_01x07_GF_7.62mm
+0
+7
+7
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_7-GF-7,62_1x07_P7.62mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/7-GF-7,62; number of pins: 07; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829206 12A 630V
+phoenix_contact connector GMSTBV_01x07_GF_7.62mm_MH
+0
+7
+7
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_8-GF-7,62_1x08_P7.62mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/8-GF-7,62; number of pins: 08; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829219 12A 630V
+phoenix_contact connector GMSTBV_01x08_GF_7.62mm
+0
+8
+8
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_8-GF-7,62_1x08_P7.62mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/8-GF-7,62; number of pins: 08; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829219 12A 630V
+phoenix_contact connector GMSTBV_01x08_GF_7.62mm_MH
+0
+8
+8
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_9-GF-7,62_1x09_P7.62mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/9-GF-7,62; number of pins: 09; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829222 12A 630V
+phoenix_contact connector GMSTBV_01x09_GF_7.62mm
+0
+9
+9
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_9-GF-7,62_1x09_P7.62mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/9-GF-7,62; number of pins: 09; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829222 12A 630V
+phoenix_contact connector GMSTBV_01x09_GF_7.62mm_MH
+0
+9
+9
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_10-GF-7,62_1x10_P7.62mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/10-GF-7,62; number of pins: 10; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829235 12A 630V
+phoenix_contact connector GMSTBV_01x10_GF_7.62mm
+0
+10
+10
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_10-GF-7,62_1x10_P7.62mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/10-GF-7,62; number of pins: 10; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829235 12A 630V
+phoenix_contact connector GMSTBV_01x10_GF_7.62mm_MH
+0
+10
+10
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_11-GF-7,62_1x11_P7.62mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/11-GF-7,62; number of pins: 11; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829248 12A 630V
+phoenix_contact connector GMSTBV_01x11_GF_7.62mm
+0
+11
+11
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_11-GF-7,62_1x11_P7.62mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/11-GF-7,62; number of pins: 11; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829248 12A 630V
+phoenix_contact connector GMSTBV_01x11_GF_7.62mm_MH
+0
+11
+11
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_12-GF-7,62_1x12_P7.62mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/12-GF-7,62; number of pins: 12; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829251 12A 630V
+phoenix_contact connector GMSTBV_01x12_GF_7.62mm
+0
+12
+12
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTBV_2,5_12-GF-7,62_1x12_P7.62mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTBV_2,5/12-GF-7,62; number of pins: 12; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829251 12A 630V
+phoenix_contact connector GMSTBV_01x12_GF_7.62mm_MH
+0
+12
+12
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_2-GF-7,62_1x02_P7.62mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/2-GF-7,62; number of pins: 02; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806229 12A 630V
+phoenix_contact connector GMSTB_01x02_GF_7.62mm
+0
+2
+2
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_2-GF-7,62_1x02_P7.62mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/2-GF-7,62; number of pins: 02; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806229 12A 630V
+phoenix_contact connector GMSTB_01x02_GF_7.62mm_MH
+0
+2
+2
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_3-GF-7,62_1x03_P7.62mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/3-GF-7,62; number of pins: 03; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806232 12A 630V
+phoenix_contact connector GMSTB_01x03_GF_7.62mm
+0
+3
+3
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_3-GF-7,62_1x03_P7.62mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/3-GF-7,62; number of pins: 03; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806232 12A 630V
+phoenix_contact connector GMSTB_01x03_GF_7.62mm_MH
+0
+3
+3
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_4-GF-7,62_1x04_P7.62mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/4-GF-7,62; number of pins: 04; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806245 12A 630V
+phoenix_contact connector GMSTB_01x04_GF_7.62mm
+0
+4
+4
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_4-GF-7,62_1x04_P7.62mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/4-GF-7,62; number of pins: 04; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806245 12A 630V
+phoenix_contact connector GMSTB_01x04_GF_7.62mm_MH
+0
+4
+4
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_5-GF-7,62_1x05_P7.62mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/5-GF-7,62; number of pins: 05; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806258 12A 630V
+phoenix_contact connector GMSTB_01x05_GF_7.62mm
+0
+5
+5
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_5-GF-7,62_1x05_P7.62mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/5-GF-7,62; number of pins: 05; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806258 12A 630V
+phoenix_contact connector GMSTB_01x05_GF_7.62mm_MH
+0
+5
+5
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_6-GF-7,62_1x06_P7.62mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/6-GF-7,62; number of pins: 06; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806261 12A 630V
+phoenix_contact connector GMSTB_01x06_GF_7.62mm
+0
+6
+6
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_6-GF-7,62_1x06_P7.62mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/6-GF-7,62; number of pins: 06; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806261 12A 630V
+phoenix_contact connector GMSTB_01x06_GF_7.62mm_MH
+0
+6
+6
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_7-GF-7,62_1x07_P7.62mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/7-GF-7,62; number of pins: 07; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806274 12A 630V
+phoenix_contact connector GMSTB_01x07_GF_7.62mm
+0
+7
+7
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_7-GF-7,62_1x07_P7.62mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/7-GF-7,62; number of pins: 07; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806274 12A 630V
+phoenix_contact connector GMSTB_01x07_GF_7.62mm_MH
+0
+7
+7
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_8-GF-7,62_1x08_P7.62mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/8-GF-7,62; number of pins: 08; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806287 12A 630V
+phoenix_contact connector GMSTB_01x08_GF_7.62mm
+0
+8
+8
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_8-GF-7,62_1x08_P7.62mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/8-GF-7,62; number of pins: 08; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806287 12A 630V
+phoenix_contact connector GMSTB_01x08_GF_7.62mm_MH
+0
+8
+8
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_9-GF-7,62_1x09_P7.62mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/9-GF-7,62; number of pins: 09; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806290 12A 630V
+phoenix_contact connector GMSTB_01x09_GF_7.62mm
+0
+9
+9
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_9-GF-7,62_1x09_P7.62mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/9-GF-7,62; number of pins: 09; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806290 12A 630V
+phoenix_contact connector GMSTB_01x09_GF_7.62mm_MH
+0
+9
+9
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_10-GF-7,62_1x10_P7.62mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/10-GF-7,62; number of pins: 10; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806300 12A 630V
+phoenix_contact connector GMSTB_01x10_GF_7.62mm
+0
+10
+10
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_10-GF-7,62_1x10_P7.62mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/10-GF-7,62; number of pins: 10; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806300 12A 630V
+phoenix_contact connector GMSTB_01x10_GF_7.62mm_MH
+0
+10
+10
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_11-GF-7,62_1x11_P7.62mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/11-GF-7,62; number of pins: 11; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806313 12A 630V
+phoenix_contact connector GMSTB_01x11_GF_7.62mm
+0
+11
+11
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_11-GF-7,62_1x11_P7.62mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/11-GF-7,62; number of pins: 11; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806313 12A 630V
+phoenix_contact connector GMSTB_01x11_GF_7.62mm_MH
+0
+11
+11
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_12-GF-7,62_1x12_P7.62mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/12-GF-7,62; number of pins: 12; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806326 12A 630V
+phoenix_contact connector GMSTB_01x12_GF_7.62mm
+0
+12
+12
+Connector_Phoenix_GMSTB
+PhoenixContact_GMSTB_2,5_12-GF-7,62_1x12_P7.62mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: GMSTB_2,5/12-GF-7,62; number of pins: 12; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806326 12A 630V
+phoenix_contact connector GMSTB_01x12_GF_7.62mm_MH
+0
+12
+12
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_2-G-3.5_1x02_P3.50mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/2-G-3.5; number of pins: 02; pin pitch: 3.50mm; Vertical || order number: 1843606 8A 160V
+phoenix_contact connector MCV_01x02_G_3.5mm
+0
+2
+2
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_2-G-3.81_1x02_P3.81mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/2-G-3.81; number of pins: 02; pin pitch: 3.81mm; Vertical || order number: 1803426 8A 160V
+phoenix_contact connector MCV_01x02_G_3.81mm
+0
+2
+2
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_2-GF-3.5_1x02_P3.50mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/2-GF-3.5; number of pins: 02; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843224 8A 160V
+phoenix_contact connector MCV_01x02_GF_3.5mm
+0
+2
+2
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_2-GF-3.5_1x02_P3.50mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/2-GF-3.5; number of pins: 02; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843224 8A 160V
+phoenix_contact connector MCV_01x02_GF_3.5mm_MH
+0
+2
+2
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_2-GF-3.81_1x02_P3.81mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/2-GF-3.81; number of pins: 02; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830596 8A 160V
+phoenix_contact connector MCV_01x02_GF_3.81mm
+0
+2
+2
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_2-GF-3.81_1x02_P3.81mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/2-GF-3.81; number of pins: 02; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830596 8A 160V
+phoenix_contact connector MCV_01x02_GF_3.81mm_MH
+0
+2
+2
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_3-G-3.5_1x03_P3.50mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/3-G-3.5; number of pins: 03; pin pitch: 3.50mm; Vertical || order number: 1843619 8A 160V
+phoenix_contact connector MCV_01x03_G_3.5mm
+0
+3
+3
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_3-G-3.81_1x03_P3.81mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/3-G-3.81; number of pins: 03; pin pitch: 3.81mm; Vertical || order number: 1803439 8A 160V
+phoenix_contact connector MCV_01x03_G_3.81mm
+0
+3
+3
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_3-GF-3.5_1x03_P3.50mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/3-GF-3.5; number of pins: 03; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843237 8A 160V
+phoenix_contact connector MCV_01x03_GF_3.5mm
+0
+3
+3
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_3-GF-3.5_1x03_P3.50mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/3-GF-3.5; number of pins: 03; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843237 8A 160V
+phoenix_contact connector MCV_01x03_GF_3.5mm_MH
+0
+3
+3
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_3-GF-3.81_1x03_P3.81mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/3-GF-3.81; number of pins: 03; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830606 8A 160V
+phoenix_contact connector MCV_01x03_GF_3.81mm
+0
+3
+3
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_3-GF-3.81_1x03_P3.81mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/3-GF-3.81; number of pins: 03; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830606 8A 160V
+phoenix_contact connector MCV_01x03_GF_3.81mm_MH
+0
+3
+3
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_4-G-3.5_1x04_P3.50mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/4-G-3.5; number of pins: 04; pin pitch: 3.50mm; Vertical || order number: 1843622 8A 160V
+phoenix_contact connector MCV_01x04_G_3.5mm
+0
+4
+4
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_4-G-3.81_1x04_P3.81mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/4-G-3.81; number of pins: 04; pin pitch: 3.81mm; Vertical || order number: 1803442 8A 160V
+phoenix_contact connector MCV_01x04_G_3.81mm
+0
+4
+4
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_4-GF-3.5_1x04_P3.50mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/4-GF-3.5; number of pins: 04; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843240 8A 160V
+phoenix_contact connector MCV_01x04_GF_3.5mm
+0
+4
+4
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_4-GF-3.5_1x04_P3.50mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/4-GF-3.5; number of pins: 04; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843240 8A 160V
+phoenix_contact connector MCV_01x04_GF_3.5mm_MH
+0
+4
+4
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_4-GF-3.81_1x04_P3.81mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/4-GF-3.81; number of pins: 04; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830619 8A 160V
+phoenix_contact connector MCV_01x04_GF_3.81mm
+0
+4
+4
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_4-GF-3.81_1x04_P3.81mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/4-GF-3.81; number of pins: 04; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830619 8A 160V
+phoenix_contact connector MCV_01x04_GF_3.81mm_MH
+0
+4
+4
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_5-G-3.5_1x05_P3.50mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/5-G-3.5; number of pins: 05; pin pitch: 3.50mm; Vertical || order number: 1843635 8A 160V
+phoenix_contact connector MCV_01x05_G_3.5mm
+0
+5
+5
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_5-G-3.81_1x05_P3.81mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/5-G-3.81; number of pins: 05; pin pitch: 3.81mm; Vertical || order number: 1803455 8A 160V
+phoenix_contact connector MCV_01x05_G_3.81mm
+0
+5
+5
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_5-GF-3.5_1x05_P3.50mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/5-GF-3.5; number of pins: 05; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843253 8A 160V
+phoenix_contact connector MCV_01x05_GF_3.5mm
+0
+5
+5
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_5-GF-3.5_1x05_P3.50mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/5-GF-3.5; number of pins: 05; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843253 8A 160V
+phoenix_contact connector MCV_01x05_GF_3.5mm_MH
+0
+5
+5
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_5-GF-3.81_1x05_P3.81mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/5-GF-3.81; number of pins: 05; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830622 8A 160V
+phoenix_contact connector MCV_01x05_GF_3.81mm
+0
+5
+5
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_5-GF-3.81_1x05_P3.81mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/5-GF-3.81; number of pins: 05; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830622 8A 160V
+phoenix_contact connector MCV_01x05_GF_3.81mm_MH
+0
+5
+5
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_6-G-3.5_1x06_P3.50mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/6-G-3.5; number of pins: 06; pin pitch: 3.50mm; Vertical || order number: 1843648 8A 160V
+phoenix_contact connector MCV_01x06_G_3.5mm
+0
+6
+6
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_6-G-3.81_1x06_P3.81mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/6-G-3.81; number of pins: 06; pin pitch: 3.81mm; Vertical || order number: 1803468 8A 160V
+phoenix_contact connector MCV_01x06_G_3.81mm
+0
+6
+6
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_6-GF-3.5_1x06_P3.50mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/6-GF-3.5; number of pins: 06; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843266 8A 160V
+phoenix_contact connector MCV_01x06_GF_3.5mm
+0
+6
+6
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_6-GF-3.5_1x06_P3.50mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/6-GF-3.5; number of pins: 06; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843266 8A 160V
+phoenix_contact connector MCV_01x06_GF_3.5mm_MH
+0
+6
+6
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_6-GF-3.81_1x06_P3.81mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/6-GF-3.81; number of pins: 06; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830635 8A 160V
+phoenix_contact connector MCV_01x06_GF_3.81mm
+0
+6
+6
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_6-GF-3.81_1x06_P3.81mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/6-GF-3.81; number of pins: 06; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830635 8A 160V
+phoenix_contact connector MCV_01x06_GF_3.81mm_MH
+0
+6
+6
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_7-G-3.5_1x07_P3.50mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/7-G-3.5; number of pins: 07; pin pitch: 3.50mm; Vertical || order number: 1843651 8A 160V
+phoenix_contact connector MCV_01x07_G_3.5mm
+0
+7
+7
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_7-G-3.81_1x07_P3.81mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/7-G-3.81; number of pins: 07; pin pitch: 3.81mm; Vertical || order number: 1803471 8A 160V
+phoenix_contact connector MCV_01x07_G_3.81mm
+0
+7
+7
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_7-GF-3.5_1x07_P3.50mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/7-GF-3.5; number of pins: 07; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843279 8A 160V
+phoenix_contact connector MCV_01x07_GF_3.5mm
+0
+7
+7
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_7-GF-3.5_1x07_P3.50mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/7-GF-3.5; number of pins: 07; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843279 8A 160V
+phoenix_contact connector MCV_01x07_GF_3.5mm_MH
+0
+7
+7
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_7-GF-3.81_1x07_P3.81mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/7-GF-3.81; number of pins: 07; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830648 8A 160V
+phoenix_contact connector MCV_01x07_GF_3.81mm
+0
+7
+7
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_7-GF-3.81_1x07_P3.81mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/7-GF-3.81; number of pins: 07; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830648 8A 160V
+phoenix_contact connector MCV_01x07_GF_3.81mm_MH
+0
+7
+7
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_8-G-3.5_1x08_P3.50mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/8-G-3.5; number of pins: 08; pin pitch: 3.50mm; Vertical || order number: 1843664 8A 160V
+phoenix_contact connector MCV_01x08_G_3.5mm
+0
+8
+8
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_8-G-3.81_1x08_P3.81mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/8-G-3.81; number of pins: 08; pin pitch: 3.81mm; Vertical || order number: 1803484 8A 160V
+phoenix_contact connector MCV_01x08_G_3.81mm
+0
+8
+8
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_8-GF-3.5_1x08_P3.50mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/8-GF-3.5; number of pins: 08; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843282 8A 160V
+phoenix_contact connector MCV_01x08_GF_3.5mm
+0
+8
+8
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_8-GF-3.5_1x08_P3.50mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/8-GF-3.5; number of pins: 08; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843282 8A 160V
+phoenix_contact connector MCV_01x08_GF_3.5mm_MH
+0
+8
+8
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_8-GF-3.81_1x08_P3.81mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/8-GF-3.81; number of pins: 08; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830651 8A 160V
+phoenix_contact connector MCV_01x08_GF_3.81mm
+0
+8
+8
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_8-GF-3.81_1x08_P3.81mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/8-GF-3.81; number of pins: 08; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830651 8A 160V
+phoenix_contact connector MCV_01x08_GF_3.81mm_MH
+0
+8
+8
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_9-G-3.5_1x09_P3.50mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/9-G-3.5; number of pins: 09; pin pitch: 3.50mm; Vertical || order number: 1843677 8A 160V
+phoenix_contact connector MCV_01x09_G_3.5mm
+0
+9
+9
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_9-G-3.81_1x09_P3.81mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/9-G-3.81; number of pins: 09; pin pitch: 3.81mm; Vertical || order number: 1803497 8A 160V
+phoenix_contact connector MCV_01x09_G_3.81mm
+0
+9
+9
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_9-GF-3.5_1x09_P3.50mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/9-GF-3.5; number of pins: 09; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843295 8A 160V
+phoenix_contact connector MCV_01x09_GF_3.5mm
+0
+9
+9
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_9-GF-3.5_1x09_P3.50mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/9-GF-3.5; number of pins: 09; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843295 8A 160V
+phoenix_contact connector MCV_01x09_GF_3.5mm_MH
+0
+9
+9
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_9-GF-3.81_1x09_P3.81mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/9-GF-3.81; number of pins: 09; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830664 8A 160V
+phoenix_contact connector MCV_01x09_GF_3.81mm
+0
+9
+9
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_9-GF-3.81_1x09_P3.81mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/9-GF-3.81; number of pins: 09; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830664 8A 160V
+phoenix_contact connector MCV_01x09_GF_3.81mm_MH
+0
+9
+9
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_10-G-3.5_1x10_P3.50mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/10-G-3.5; number of pins: 10; pin pitch: 3.50mm; Vertical || order number: 1843680 8A 160V
+phoenix_contact connector MCV_01x10_G_3.5mm
+0
+10
+10
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_10-G-3.81_1x10_P3.81mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/10-G-3.81; number of pins: 10; pin pitch: 3.81mm; Vertical || order number: 1803507 8A 160V
+phoenix_contact connector MCV_01x10_G_3.81mm
+0
+10
+10
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_10-GF-3.5_1x10_P3.50mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/10-GF-3.5; number of pins: 10; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843305 8A 160V
+phoenix_contact connector MCV_01x10_GF_3.5mm
+0
+10
+10
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_10-GF-3.5_1x10_P3.50mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/10-GF-3.5; number of pins: 10; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843305 8A 160V
+phoenix_contact connector MCV_01x10_GF_3.5mm_MH
+0
+10
+10
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_10-GF-3.81_1x10_P3.81mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/10-GF-3.81; number of pins: 10; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830677 8A 160V
+phoenix_contact connector MCV_01x10_GF_3.81mm
+0
+10
+10
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_10-GF-3.81_1x10_P3.81mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/10-GF-3.81; number of pins: 10; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830677 8A 160V
+phoenix_contact connector MCV_01x10_GF_3.81mm_MH
+0
+10
+10
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_11-G-3.5_1x11_P3.50mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/11-G-3.5; number of pins: 11; pin pitch: 3.50mm; Vertical || order number: 1843693 8A 160V
+phoenix_contact connector MCV_01x11_G_3.5mm
+0
+11
+11
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_11-G-3.81_1x11_P3.81mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/11-G-3.81; number of pins: 11; pin pitch: 3.81mm; Vertical || order number: 1803510 8A 160V
+phoenix_contact connector MCV_01x11_G_3.81mm
+0
+11
+11
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_11-GF-3.5_1x11_P3.50mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/11-GF-3.5; number of pins: 11; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843318 8A 160V
+phoenix_contact connector MCV_01x11_GF_3.5mm
+0
+11
+11
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_11-GF-3.5_1x11_P3.50mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/11-GF-3.5; number of pins: 11; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843318 8A 160V
+phoenix_contact connector MCV_01x11_GF_3.5mm_MH
+0
+11
+11
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_11-GF-3.81_1x11_P3.81mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/11-GF-3.81; number of pins: 11; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830680 8A 160V
+phoenix_contact connector MCV_01x11_GF_3.81mm
+0
+11
+11
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_11-GF-3.81_1x11_P3.81mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/11-GF-3.81; number of pins: 11; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830680 8A 160V
+phoenix_contact connector MCV_01x11_GF_3.81mm_MH
+0
+11
+11
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_12-G-3.5_1x12_P3.50mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/12-G-3.5; number of pins: 12; pin pitch: 3.50mm; Vertical || order number: 1843703 8A 160V
+phoenix_contact connector MCV_01x12_G_3.5mm
+0
+12
+12
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_12-G-3.81_1x12_P3.81mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/12-G-3.81; number of pins: 12; pin pitch: 3.81mm; Vertical || order number: 1803523 8A 160V
+phoenix_contact connector MCV_01x12_G_3.81mm
+0
+12
+12
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_12-GF-3.5_1x12_P3.50mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/12-GF-3.5; number of pins: 12; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843321 8A 160V
+phoenix_contact connector MCV_01x12_GF_3.5mm
+0
+12
+12
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_12-GF-3.5_1x12_P3.50mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/12-GF-3.5; number of pins: 12; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843321 8A 160V
+phoenix_contact connector MCV_01x12_GF_3.5mm_MH
+0
+12
+12
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_12-GF-3.81_1x12_P3.81mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/12-GF-3.81; number of pins: 12; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830693 8A 160V
+phoenix_contact connector MCV_01x12_GF_3.81mm
+0
+12
+12
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_12-GF-3.81_1x12_P3.81mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/12-GF-3.81; number of pins: 12; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830693 8A 160V
+phoenix_contact connector MCV_01x12_GF_3.81mm_MH
+0
+12
+12
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_13-G-3.5_1x13_P3.50mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/13-G-3.5; number of pins: 13; pin pitch: 3.50mm; Vertical || order number: 1843716 8A 160V
+phoenix_contact connector MCV_01x13_G_3.5mm
+0
+13
+13
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_13-G-3.81_1x13_P3.81mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/13-G-3.81; number of pins: 13; pin pitch: 3.81mm; Vertical || order number: 1803536 8A 160V
+phoenix_contact connector MCV_01x13_G_3.81mm
+0
+13
+13
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_13-GF-3.5_1x13_P3.50mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/13-GF-3.5; number of pins: 13; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843334 8A 160V
+phoenix_contact connector MCV_01x13_GF_3.5mm
+0
+13
+13
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_13-GF-3.5_1x13_P3.50mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/13-GF-3.5; number of pins: 13; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843334 8A 160V
+phoenix_contact connector MCV_01x13_GF_3.5mm_MH
+0
+13
+13
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_13-GF-3.81_1x13_P3.81mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/13-GF-3.81; number of pins: 13; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830703 8A 160V
+phoenix_contact connector MCV_01x13_GF_3.81mm
+0
+13
+13
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_13-GF-3.81_1x13_P3.81mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/13-GF-3.81; number of pins: 13; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830703 8A 160V
+phoenix_contact connector MCV_01x13_GF_3.81mm_MH
+0
+13
+13
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_14-G-3.5_1x14_P3.50mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/14-G-3.5; number of pins: 14; pin pitch: 3.50mm; Vertical || order number: 1843729 8A 160V
+phoenix_contact connector MCV_01x14_G_3.5mm
+0
+14
+14
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_14-G-3.81_1x14_P3.81mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/14-G-3.81; number of pins: 14; pin pitch: 3.81mm; Vertical || order number: 1803549 8A 160V
+phoenix_contact connector MCV_01x14_G_3.81mm
+0
+14
+14
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_14-GF-3.5_1x14_P3.50mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/14-GF-3.5; number of pins: 14; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843347 8A 160V
+phoenix_contact connector MCV_01x14_GF_3.5mm
+0
+14
+14
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_14-GF-3.5_1x14_P3.50mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/14-GF-3.5; number of pins: 14; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843347 8A 160V
+phoenix_contact connector MCV_01x14_GF_3.5mm_MH
+0
+14
+14
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_14-GF-3.81_1x14_P3.81mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/14-GF-3.81; number of pins: 14; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830716 8A 160V
+phoenix_contact connector MCV_01x14_GF_3.81mm
+0
+14
+14
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_14-GF-3.81_1x14_P3.81mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/14-GF-3.81; number of pins: 14; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830716 8A 160V
+phoenix_contact connector MCV_01x14_GF_3.81mm_MH
+0
+14
+14
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_15-G-3.5_1x15_P3.50mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/15-G-3.5; number of pins: 15; pin pitch: 3.50mm; Vertical || order number: 1843732 8A 160V
+phoenix_contact connector MCV_01x15_G_3.5mm
+0
+15
+15
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_15-G-3.81_1x15_P3.81mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/15-G-3.81; number of pins: 15; pin pitch: 3.81mm; Vertical || order number: 1803552 8A 160V
+phoenix_contact connector MCV_01x15_G_3.81mm
+0
+15
+15
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_15-GF-3.5_1x15_P3.50mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/15-GF-3.5; number of pins: 15; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843350 8A 160V
+phoenix_contact connector MCV_01x15_GF_3.5mm
+0
+15
+15
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_15-GF-3.5_1x15_P3.50mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/15-GF-3.5; number of pins: 15; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843350 8A 160V
+phoenix_contact connector MCV_01x15_GF_3.5mm_MH
+0
+15
+15
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_15-GF-3.81_1x15_P3.81mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/15-GF-3.81; number of pins: 15; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830729 8A 160V
+phoenix_contact connector MCV_01x15_GF_3.81mm
+0
+15
+15
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_15-GF-3.81_1x15_P3.81mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/15-GF-3.81; number of pins: 15; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830729 8A 160V
+phoenix_contact connector MCV_01x15_GF_3.81mm_MH
+0
+15
+15
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_16-G-3.5_1x16_P3.50mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/16-G-3.5; number of pins: 16; pin pitch: 3.50mm; Vertical || order number: 1843745 8A 160V
+phoenix_contact connector MCV_01x16_G_3.5mm
+0
+16
+16
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_16-G-3.81_1x16_P3.81mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/16-G-3.81; number of pins: 16; pin pitch: 3.81mm; Vertical || order number: 1803565 8A 160V
+phoenix_contact connector MCV_01x16_G_3.81mm
+0
+16
+16
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_16-GF-3.5_1x16_P3.50mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/16-GF-3.5; number of pins: 16; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843363 8A 160V
+phoenix_contact connector MCV_01x16_GF_3.5mm
+0
+16
+16
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_16-GF-3.5_1x16_P3.50mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/16-GF-3.5; number of pins: 16; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843363 8A 160V
+phoenix_contact connector MCV_01x16_GF_3.5mm_MH
+0
+16
+16
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_16-GF-3.81_1x16_P3.81mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/16-GF-3.81; number of pins: 16; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830732 8A 160V
+phoenix_contact connector MCV_01x16_GF_3.81mm
+0
+16
+16
+Connector_Phoenix_MC
+PhoenixContact_MCV_1,5_16-GF-3.81_1x16_P3.81mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/16-GF-3.81; number of pins: 16; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830732 8A 160V
+phoenix_contact connector MCV_01x16_GF_3.81mm_MH
+0
+16
+16
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_2-G-3.5_1x02_P3.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/2-G-3.5; number of pins: 02; pin pitch: 3.50mm; Angled || order number: 1844210 8A 160V
+phoenix_contact connector MC_01x02_G_3.5mm
+0
+2
+2
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_2-G-3.81_1x02_P3.81mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/2-G-3.81; number of pins: 02; pin pitch: 3.81mm; Angled || order number: 1803277 8A 160V
+phoenix_contact connector MC_01x02_G_3.81mm
+0
+2
+2
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_2-GF-3.5_1x02_P3.50mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/2-GF-3.5; number of pins: 02; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843790 8A 160V
+phoenix_contact connector MC_01x02_GF_3.5mm
+0
+2
+2
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_2-GF-3.5_1x02_P3.50mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/2-GF-3.5; number of pins: 02; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843790 8A 160V
+phoenix_contact connector MC_01x02_GF_3.5mm_MH
+0
+2
+2
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_2-GF-3.81_1x02_P3.81mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/2-GF-3.81; number of pins: 02; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827868 8A 160V
+phoenix_contact connector MC_01x02_GF_3.81mm
+0
+2
+2
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_2-GF-3.81_1x02_P3.81mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/2-GF-3.81; number of pins: 02; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827868 8A 160V
+phoenix_contact connector MC_01x02_GF_3.81mm_MH
+0
+2
+2
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/3-G-3.5; number of pins: 03; pin pitch: 3.50mm; Angled || order number: 1844223 8A 160V
+phoenix_contact connector MC_01x03_G_3.5mm
+0
+3
+3
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_3-G-3.81_1x03_P3.81mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/3-G-3.81; number of pins: 03; pin pitch: 3.81mm; Angled || order number: 1803280 8A 160V
+phoenix_contact connector MC_01x03_G_3.81mm
+0
+3
+3
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_3-GF-3.5_1x03_P3.50mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/3-GF-3.5; number of pins: 03; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843800 8A 160V
+phoenix_contact connector MC_01x03_GF_3.5mm
+0
+3
+3
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_3-GF-3.5_1x03_P3.50mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/3-GF-3.5; number of pins: 03; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843800 8A 160V
+phoenix_contact connector MC_01x03_GF_3.5mm_MH
+0
+3
+3
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_3-GF-3.81_1x03_P3.81mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/3-GF-3.81; number of pins: 03; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827871 8A 160V
+phoenix_contact connector MC_01x03_GF_3.81mm
+0
+3
+3
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_3-GF-3.81_1x03_P3.81mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/3-GF-3.81; number of pins: 03; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827871 8A 160V
+phoenix_contact connector MC_01x03_GF_3.81mm_MH
+0
+3
+3
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_4-G-3.5_1x04_P3.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/4-G-3.5; number of pins: 04; pin pitch: 3.50mm; Angled || order number: 1844236 8A 160V
+phoenix_contact connector MC_01x04_G_3.5mm
+0
+4
+4
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_4-G-3.81_1x04_P3.81mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/4-G-3.81; number of pins: 04; pin pitch: 3.81mm; Angled || order number: 1803293 8A 160V
+phoenix_contact connector MC_01x04_G_3.81mm
+0
+4
+4
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_4-GF-3.5_1x04_P3.50mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/4-GF-3.5; number of pins: 04; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843813 8A 160V
+phoenix_contact connector MC_01x04_GF_3.5mm
+0
+4
+4
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_4-GF-3.5_1x04_P3.50mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/4-GF-3.5; number of pins: 04; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843813 8A 160V
+phoenix_contact connector MC_01x04_GF_3.5mm_MH
+0
+4
+4
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_4-GF-3.81_1x04_P3.81mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/4-GF-3.81; number of pins: 04; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827884 8A 160V
+phoenix_contact connector MC_01x04_GF_3.81mm
+0
+4
+4
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_4-GF-3.81_1x04_P3.81mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/4-GF-3.81; number of pins: 04; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827884 8A 160V
+phoenix_contact connector MC_01x04_GF_3.81mm_MH
+0
+4
+4
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_5-G-3.5_1x05_P3.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/5-G-3.5; number of pins: 05; pin pitch: 3.50mm; Angled || order number: 1844249 8A 160V
+phoenix_contact connector MC_01x05_G_3.5mm
+0
+5
+5
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_5-G-3.81_1x05_P3.81mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/5-G-3.81; number of pins: 05; pin pitch: 3.81mm; Angled || order number: 1803303 8A 160V
+phoenix_contact connector MC_01x05_G_3.81mm
+0
+5
+5
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_5-GF-3.5_1x05_P3.50mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/5-GF-3.5; number of pins: 05; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843826 8A 160V
+phoenix_contact connector MC_01x05_GF_3.5mm
+0
+5
+5
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_5-GF-3.5_1x05_P3.50mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/5-GF-3.5; number of pins: 05; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843826 8A 160V
+phoenix_contact connector MC_01x05_GF_3.5mm_MH
+0
+5
+5
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_5-GF-3.81_1x05_P3.81mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/5-GF-3.81; number of pins: 05; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827897 8A 160V
+phoenix_contact connector MC_01x05_GF_3.81mm
+0
+5
+5
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_5-GF-3.81_1x05_P3.81mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/5-GF-3.81; number of pins: 05; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827897 8A 160V
+phoenix_contact connector MC_01x05_GF_3.81mm_MH
+0
+5
+5
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_6-G-3.5_1x06_P3.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/6-G-3.5; number of pins: 06; pin pitch: 3.50mm; Angled || order number: 1844252 8A 160V
+phoenix_contact connector MC_01x06_G_3.5mm
+0
+6
+6
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_6-G-3.81_1x06_P3.81mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/6-G-3.81; number of pins: 06; pin pitch: 3.81mm; Angled || order number: 1803316 8A 160V
+phoenix_contact connector MC_01x06_G_3.81mm
+0
+6
+6
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_6-GF-3.5_1x06_P3.50mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/6-GF-3.5; number of pins: 06; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843839 8A 160V
+phoenix_contact connector MC_01x06_GF_3.5mm
+0
+6
+6
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_6-GF-3.5_1x06_P3.50mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/6-GF-3.5; number of pins: 06; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843839 8A 160V
+phoenix_contact connector MC_01x06_GF_3.5mm_MH
+0
+6
+6
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_6-GF-3.81_1x06_P3.81mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/6-GF-3.81; number of pins: 06; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827907 8A 160V
+phoenix_contact connector MC_01x06_GF_3.81mm
+0
+6
+6
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_6-GF-3.81_1x06_P3.81mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/6-GF-3.81; number of pins: 06; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827907 8A 160V
+phoenix_contact connector MC_01x06_GF_3.81mm_MH
+0
+6
+6
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_7-G-3.5_1x07_P3.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/7-G-3.5; number of pins: 07; pin pitch: 3.50mm; Angled || order number: 1844265 8A 160V
+phoenix_contact connector MC_01x07_G_3.5mm
+0
+7
+7
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_7-G-3.81_1x07_P3.81mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/7-G-3.81; number of pins: 07; pin pitch: 3.81mm; Angled || order number: 1803329 8A 160V
+phoenix_contact connector MC_01x07_G_3.81mm
+0
+7
+7
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_7-GF-3.5_1x07_P3.50mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/7-GF-3.5; number of pins: 07; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843842 8A 160V
+phoenix_contact connector MC_01x07_GF_3.5mm
+0
+7
+7
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_7-GF-3.5_1x07_P3.50mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/7-GF-3.5; number of pins: 07; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843842 8A 160V
+phoenix_contact connector MC_01x07_GF_3.5mm_MH
+0
+7
+7
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_7-GF-3.81_1x07_P3.81mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/7-GF-3.81; number of pins: 07; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827910 8A 160V
+phoenix_contact connector MC_01x07_GF_3.81mm
+0
+7
+7
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_7-GF-3.81_1x07_P3.81mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/7-GF-3.81; number of pins: 07; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827910 8A 160V
+phoenix_contact connector MC_01x07_GF_3.81mm_MH
+0
+7
+7
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_8-G-3.5_1x08_P3.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/8-G-3.5; number of pins: 08; pin pitch: 3.50mm; Angled || order number: 1844278 8A 160V
+phoenix_contact connector MC_01x08_G_3.5mm
+0
+8
+8
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_8-G-3.81_1x08_P3.81mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/8-G-3.81; number of pins: 08; pin pitch: 3.81mm; Angled || order number: 1803332 8A 160V
+phoenix_contact connector MC_01x08_G_3.81mm
+0
+8
+8
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_8-GF-3.5_1x08_P3.50mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/8-GF-3.5; number of pins: 08; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843855 8A 160V
+phoenix_contact connector MC_01x08_GF_3.5mm
+0
+8
+8
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_8-GF-3.5_1x08_P3.50mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/8-GF-3.5; number of pins: 08; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843855 8A 160V
+phoenix_contact connector MC_01x08_GF_3.5mm_MH
+0
+8
+8
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_8-GF-3.81_1x08_P3.81mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/8-GF-3.81; number of pins: 08; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827923 8A 160V
+phoenix_contact connector MC_01x08_GF_3.81mm
+0
+8
+8
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_8-GF-3.81_1x08_P3.81mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/8-GF-3.81; number of pins: 08; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827923 8A 160V
+phoenix_contact connector MC_01x08_GF_3.81mm_MH
+0
+8
+8
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_9-G-3.5_1x09_P3.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/9-G-3.5; number of pins: 09; pin pitch: 3.50mm; Angled || order number: 1844281 8A 160V
+phoenix_contact connector MC_01x09_G_3.5mm
+0
+9
+9
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_9-G-3.81_1x09_P3.81mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/9-G-3.81; number of pins: 09; pin pitch: 3.81mm; Angled || order number: 1803345 8A 160V
+phoenix_contact connector MC_01x09_G_3.81mm
+0
+9
+9
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_9-GF-3.5_1x09_P3.50mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/9-GF-3.5; number of pins: 09; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843868 8A 160V
+phoenix_contact connector MC_01x09_GF_3.5mm
+0
+9
+9
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_9-GF-3.5_1x09_P3.50mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/9-GF-3.5; number of pins: 09; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843868 8A 160V
+phoenix_contact connector MC_01x09_GF_3.5mm_MH
+0
+9
+9
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_9-GF-3.81_1x09_P3.81mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/9-GF-3.81; number of pins: 09; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827936 8A 160V
+phoenix_contact connector MC_01x09_GF_3.81mm
+0
+9
+9
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_9-GF-3.81_1x09_P3.81mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/9-GF-3.81; number of pins: 09; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827936 8A 160V
+phoenix_contact connector MC_01x09_GF_3.81mm_MH
+0
+9
+9
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_10-G-3.5_1x10_P3.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/10-G-3.5; number of pins: 10; pin pitch: 3.50mm; Angled || order number: 1844294 8A 160V
+phoenix_contact connector MC_01x10_G_3.5mm
+0
+10
+10
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_10-G-3.81_1x10_P3.81mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/10-G-3.81; number of pins: 10; pin pitch: 3.81mm; Angled || order number: 1803358 8A 160V
+phoenix_contact connector MC_01x10_G_3.81mm
+0
+10
+10
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_10-GF-3.5_1x10_P3.50mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/10-GF-3.5; number of pins: 10; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843871 8A 160V
+phoenix_contact connector MC_01x10_GF_3.5mm
+0
+10
+10
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_10-GF-3.5_1x10_P3.50mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/10-GF-3.5; number of pins: 10; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843871 8A 160V
+phoenix_contact connector MC_01x10_GF_3.5mm_MH
+0
+10
+10
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_10-GF-3.81_1x10_P3.81mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/10-GF-3.81; number of pins: 10; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827949 8A 160V
+phoenix_contact connector MC_01x10_GF_3.81mm
+0
+10
+10
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_10-GF-3.81_1x10_P3.81mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/10-GF-3.81; number of pins: 10; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827949 8A 160V
+phoenix_contact connector MC_01x10_GF_3.81mm_MH
+0
+10
+10
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_11-G-3.5_1x11_P3.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/11-G-3.5; number of pins: 11; pin pitch: 3.50mm; Angled || order number: 1844304 8A 160V
+phoenix_contact connector MC_01x11_G_3.5mm
+0
+11
+11
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_11-G-3.81_1x11_P3.81mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/11-G-3.81; number of pins: 11; pin pitch: 3.81mm; Angled || order number: 1803361 8A 160V
+phoenix_contact connector MC_01x11_G_3.81mm
+0
+11
+11
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_11-GF-3.5_1x11_P3.50mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/11-GF-3.5; number of pins: 11; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843884 8A 160V
+phoenix_contact connector MC_01x11_GF_3.5mm
+0
+11
+11
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_11-GF-3.5_1x11_P3.50mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/11-GF-3.5; number of pins: 11; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843884 8A 160V
+phoenix_contact connector MC_01x11_GF_3.5mm_MH
+0
+11
+11
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_11-GF-3.81_1x11_P3.81mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/11-GF-3.81; number of pins: 11; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827952 8A 160V
+phoenix_contact connector MC_01x11_GF_3.81mm
+0
+11
+11
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_11-GF-3.81_1x11_P3.81mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/11-GF-3.81; number of pins: 11; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827952 8A 160V
+phoenix_contact connector MC_01x11_GF_3.81mm_MH
+0
+11
+11
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_12-G-3.5_1x12_P3.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/12-G-3.5; number of pins: 12; pin pitch: 3.50mm; Angled || order number: 1844317 8A 160V
+phoenix_contact connector MC_01x12_G_3.5mm
+0
+12
+12
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_12-G-3.81_1x12_P3.81mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/12-G-3.81; number of pins: 12; pin pitch: 3.81mm; Angled || order number: 1803374 8A 160V
+phoenix_contact connector MC_01x12_G_3.81mm
+0
+12
+12
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_12-GF-3.5_1x12_P3.50mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/12-GF-3.5; number of pins: 12; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843897 8A 160V
+phoenix_contact connector MC_01x12_GF_3.5mm
+0
+12
+12
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_12-GF-3.5_1x12_P3.50mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/12-GF-3.5; number of pins: 12; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843897 8A 160V
+phoenix_contact connector MC_01x12_GF_3.5mm_MH
+0
+12
+12
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_12-GF-3.81_1x12_P3.81mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/12-GF-3.81; number of pins: 12; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827965 8A 160V
+phoenix_contact connector MC_01x12_GF_3.81mm
+0
+12
+12
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_12-GF-3.81_1x12_P3.81mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/12-GF-3.81; number of pins: 12; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827965 8A 160V
+phoenix_contact connector MC_01x12_GF_3.81mm_MH
+0
+12
+12
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_13-G-3.5_1x13_P3.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/13-G-3.5; number of pins: 13; pin pitch: 3.50mm; Angled || order number: 1844320 8A 160V
+phoenix_contact connector MC_01x13_G_3.5mm
+0
+13
+13
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_13-G-3.81_1x13_P3.81mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/13-G-3.81; number of pins: 13; pin pitch: 3.81mm; Angled || order number: 1803387 8A 160V
+phoenix_contact connector MC_01x13_G_3.81mm
+0
+13
+13
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_13-GF-3.5_1x13_P3.50mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/13-GF-3.5; number of pins: 13; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843907 8A 160V
+phoenix_contact connector MC_01x13_GF_3.5mm
+0
+13
+13
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_13-GF-3.5_1x13_P3.50mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/13-GF-3.5; number of pins: 13; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843907 8A 160V
+phoenix_contact connector MC_01x13_GF_3.5mm_MH
+0
+13
+13
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_13-GF-3.81_1x13_P3.81mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/13-GF-3.81; number of pins: 13; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827978 8A 160V
+phoenix_contact connector MC_01x13_GF_3.81mm
+0
+13
+13
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_13-GF-3.81_1x13_P3.81mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/13-GF-3.81; number of pins: 13; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827978 8A 160V
+phoenix_contact connector MC_01x13_GF_3.81mm_MH
+0
+13
+13
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_14-G-3.5_1x14_P3.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/14-G-3.5; number of pins: 14; pin pitch: 3.50mm; Angled || order number: 1844333 8A 160V
+phoenix_contact connector MC_01x14_G_3.5mm
+0
+14
+14
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_14-G-3.81_1x14_P3.81mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/14-G-3.81; number of pins: 14; pin pitch: 3.81mm; Angled || order number: 1803390 8A 160V
+phoenix_contact connector MC_01x14_G_3.81mm
+0
+14
+14
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_14-GF-3.5_1x14_P3.50mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/14-GF-3.5; number of pins: 14; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843910 8A 160V
+phoenix_contact connector MC_01x14_GF_3.5mm
+0
+14
+14
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_14-GF-3.5_1x14_P3.50mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/14-GF-3.5; number of pins: 14; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843910 8A 160V
+phoenix_contact connector MC_01x14_GF_3.5mm_MH
+0
+14
+14
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_14-GF-3.81_1x14_P3.81mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/14-GF-3.81; number of pins: 14; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827981 8A 160V
+phoenix_contact connector MC_01x14_GF_3.81mm
+0
+14
+14
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_14-GF-3.81_1x14_P3.81mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/14-GF-3.81; number of pins: 14; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827981 8A 160V
+phoenix_contact connector MC_01x14_GF_3.81mm_MH
+0
+14
+14
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_15-G-3.5_1x15_P3.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/15-G-3.5; number of pins: 15; pin pitch: 3.50mm; Angled || order number: 1844346 8A 160V
+phoenix_contact connector MC_01x15_G_3.5mm
+0
+15
+15
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_15-G-3.81_1x15_P3.81mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/15-G-3.81; number of pins: 15; pin pitch: 3.81mm; Angled || order number: 1803400 8A 160V
+phoenix_contact connector MC_01x15_G_3.81mm
+0
+15
+15
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_15-GF-3.5_1x15_P3.50mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/15-GF-3.5; number of pins: 15; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843923 8A 160V
+phoenix_contact connector MC_01x15_GF_3.5mm
+0
+15
+15
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_15-GF-3.5_1x15_P3.50mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/15-GF-3.5; number of pins: 15; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843923 8A 160V
+phoenix_contact connector MC_01x15_GF_3.5mm_MH
+0
+15
+15
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_15-GF-3.81_1x15_P3.81mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/15-GF-3.81; number of pins: 15; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827994 8A 160V
+phoenix_contact connector MC_01x15_GF_3.81mm
+0
+15
+15
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_15-GF-3.81_1x15_P3.81mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/15-GF-3.81; number of pins: 15; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827994 8A 160V
+phoenix_contact connector MC_01x15_GF_3.81mm_MH
+0
+15
+15
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_16-G-3.5_1x16_P3.50mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/16-G-3.5; number of pins: 16; pin pitch: 3.50mm; Angled || order number: 1844359 8A 160V
+phoenix_contact connector MC_01x16_G_3.5mm
+0
+16
+16
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_16-G-3.81_1x16_P3.81mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/16-G-3.81; number of pins: 16; pin pitch: 3.81mm; Angled || order number: 1803413 8A 160V
+phoenix_contact connector MC_01x16_G_3.81mm
+0
+16
+16
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_16-GF-3.5_1x16_P3.50mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/16-GF-3.5; number of pins: 16; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843936 8A 160V
+phoenix_contact connector MC_01x16_GF_3.5mm
+0
+16
+16
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_16-GF-3.5_1x16_P3.50mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/16-GF-3.5; number of pins: 16; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843936 8A 160V
+phoenix_contact connector MC_01x16_GF_3.5mm_MH
+0
+16
+16
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_16-GF-3.81_1x16_P3.81mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/16-GF-3.81; number of pins: 16; pin pitch: 3.81mm; Angled; threaded flange || order number: 1828003 8A 160V
+phoenix_contact connector MC_01x16_GF_3.81mm
+0
+16
+16
+Connector_Phoenix_MC
+PhoenixContact_MC_1,5_16-GF-3.81_1x16_P3.81mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/16-GF-3.81; number of pins: 16; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1828003 8A 160V
+phoenix_contact connector MC_01x16_GF_3.81mm_MH
+0
+16
+16
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_2-G-5.08_1x02_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/2-G-5.08; number of pins: 02; pin pitch: 5.08mm; Vertical || order number: 1836299 8A 320V
+phoenix_contact connector MCV_01x02_G_5.08mm
+0
+2
+2
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_2-GF-5.08_1x02_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/2-GF-5.08; number of pins: 02; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847615 8A 320V
+phoenix_contact connector MCV_01x02_GF_5.08mm
+0
+2
+2
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_2-GF-5.08_1x02_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/2-GF-5.08; number of pins: 02; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847615 8A 320V
+phoenix_contact connector MCV_01x02_GF_5.08mm_MH
+0
+2
+2
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_3-G-5.08_1x03_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/3-G-5.08; number of pins: 03; pin pitch: 5.08mm; Vertical || order number: 1836309 8A 320V
+phoenix_contact connector MCV_01x03_G_5.08mm
+0
+3
+3
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_3-GF-5.08_1x03_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/3-GF-5.08; number of pins: 03; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847628 8A 320V
+phoenix_contact connector MCV_01x03_GF_5.08mm
+0
+3
+3
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_3-GF-5.08_1x03_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/3-GF-5.08; number of pins: 03; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847628 8A 320V
+phoenix_contact connector MCV_01x03_GF_5.08mm_MH
+0
+3
+3
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_4-G-5.08_1x04_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/4-G-5.08; number of pins: 04; pin pitch: 5.08mm; Vertical || order number: 1836312 8A 320V
+phoenix_contact connector MCV_01x04_G_5.08mm
+0
+4
+4
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_4-GF-5.08_1x04_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/4-GF-5.08; number of pins: 04; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847631 8A 320V
+phoenix_contact connector MCV_01x04_GF_5.08mm
+0
+4
+4
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_4-GF-5.08_1x04_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/4-GF-5.08; number of pins: 04; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847631 8A 320V
+phoenix_contact connector MCV_01x04_GF_5.08mm_MH
+0
+4
+4
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_5-G-5.08_1x05_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/5-G-5.08; number of pins: 05; pin pitch: 5.08mm; Vertical || order number: 1836325 8A 320V
+phoenix_contact connector MCV_01x05_G_5.08mm
+0
+5
+5
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_5-GF-5.08_1x05_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/5-GF-5.08; number of pins: 05; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847644 8A 320V
+phoenix_contact connector MCV_01x05_GF_5.08mm
+0
+5
+5
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_5-GF-5.08_1x05_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/5-GF-5.08; number of pins: 05; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847644 8A 320V
+phoenix_contact connector MCV_01x05_GF_5.08mm_MH
+0
+5
+5
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_6-G-5.08_1x06_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/6-G-5.08; number of pins: 06; pin pitch: 5.08mm; Vertical || order number: 1836338 8A 320V
+phoenix_contact connector MCV_01x06_G_5.08mm
+0
+6
+6
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_6-GF-5.08_1x06_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/6-GF-5.08; number of pins: 06; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847657 8A 320V
+phoenix_contact connector MCV_01x06_GF_5.08mm
+0
+6
+6
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_6-GF-5.08_1x06_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/6-GF-5.08; number of pins: 06; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847657 8A 320V
+phoenix_contact connector MCV_01x06_GF_5.08mm_MH
+0
+6
+6
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_7-G-5.08_1x07_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/7-G-5.08; number of pins: 07; pin pitch: 5.08mm; Vertical || order number: 1836341 8A 320V
+phoenix_contact connector MCV_01x07_G_5.08mm
+0
+7
+7
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_7-GF-5.08_1x07_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/7-GF-5.08; number of pins: 07; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847660 8A 320V
+phoenix_contact connector MCV_01x07_GF_5.08mm
+0
+7
+7
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_7-GF-5.08_1x07_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/7-GF-5.08; number of pins: 07; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847660 8A 320V
+phoenix_contact connector MCV_01x07_GF_5.08mm_MH
+0
+7
+7
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_8-G-5.08_1x08_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/8-G-5.08; number of pins: 08; pin pitch: 5.08mm; Vertical || order number: 1836354 8A 320V
+phoenix_contact connector MCV_01x08_G_5.08mm
+0
+8
+8
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_8-GF-5.08_1x08_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/8-GF-5.08; number of pins: 08; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847673 8A 320V
+phoenix_contact connector MCV_01x08_GF_5.08mm
+0
+8
+8
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_8-GF-5.08_1x08_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/8-GF-5.08; number of pins: 08; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847673 8A 320V
+phoenix_contact connector MCV_01x08_GF_5.08mm_MH
+0
+8
+8
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_9-G-5.08_1x09_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/9-G-5.08; number of pins: 09; pin pitch: 5.08mm; Vertical || order number: 1836367 8A 320V
+phoenix_contact connector MCV_01x09_G_5.08mm
+0
+9
+9
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_9-GF-5.08_1x09_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/9-GF-5.08; number of pins: 09; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847686 8A 320V
+phoenix_contact connector MCV_01x09_GF_5.08mm
+0
+9
+9
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_9-GF-5.08_1x09_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/9-GF-5.08; number of pins: 09; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847686 8A 320V
+phoenix_contact connector MCV_01x09_GF_5.08mm_MH
+0
+9
+9
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_10-G-5.08_1x10_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/10-G-5.08; number of pins: 10; pin pitch: 5.08mm; Vertical || order number: 1836370 8A 320V
+phoenix_contact connector MCV_01x10_G_5.08mm
+0
+10
+10
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_10-GF-5.08_1x10_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/10-GF-5.08; number of pins: 10; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847699 8A 320V
+phoenix_contact connector MCV_01x10_GF_5.08mm
+0
+10
+10
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_10-GF-5.08_1x10_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/10-GF-5.08; number of pins: 10; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847699 8A 320V
+phoenix_contact connector MCV_01x10_GF_5.08mm_MH
+0
+10
+10
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_11-G-5.08_1x11_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/11-G-5.08; number of pins: 11; pin pitch: 5.08mm; Vertical || order number: 1836383 8A 320V
+phoenix_contact connector MCV_01x11_G_5.08mm
+0
+11
+11
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_11-GF-5.08_1x11_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/11-GF-5.08; number of pins: 11; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847709 8A 320V
+phoenix_contact connector MCV_01x11_GF_5.08mm
+0
+11
+11
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_11-GF-5.08_1x11_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/11-GF-5.08; number of pins: 11; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847709 8A 320V
+phoenix_contact connector MCV_01x11_GF_5.08mm_MH
+0
+11
+11
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_12-G-5.08_1x12_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MCV_1,5/12-G-5.08; number of pins: 12; pin pitch: 5.08mm; Vertical || order number: 1836396 8A 320V
+phoenix_contact connector MCV_01x12_G_5.08mm
+0
+12
+12
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_12-GF-5.08_1x12_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MCV_1,5/12-GF-5.08; number of pins: 12; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847712 8A 320V
+phoenix_contact connector MCV_01x12_GF_5.08mm
+0
+12
+12
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MCV_1,5_12-GF-5.08_1x12_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MCV_1,5/12-GF-5.08; number of pins: 12; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847712 8A 320V
+phoenix_contact connector MCV_01x12_GF_5.08mm_MH
+0
+12
+12
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_2-G-5.08_1x02_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/2-G-5.08; number of pins: 02; pin pitch: 5.08mm; Angled || order number: 1836189 8A 320V
+phoenix_contact connector MC_01x02_G_5.08mm
+0
+2
+2
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_2-GF-5.08_1x02_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/2-GF-5.08; number of pins: 02; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847466 8A 320V
+phoenix_contact connector MC_01x02_GF_5.08mm
+0
+2
+2
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_2-GF-5.08_1x02_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/2-GF-5.08; number of pins: 02; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847466 8A 320V
+phoenix_contact connector MC_01x02_GF_5.08mm_MH
+0
+2
+2
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_3-G-5.08_1x03_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/3-G-5.08; number of pins: 03; pin pitch: 5.08mm; Angled || order number: 1836192 8A 320V
+phoenix_contact connector MC_01x03_G_5.08mm
+0
+3
+3
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_3-GF-5.08_1x03_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/3-GF-5.08; number of pins: 03; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847479 8A 320V
+phoenix_contact connector MC_01x03_GF_5.08mm
+0
+3
+3
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_3-GF-5.08_1x03_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/3-GF-5.08; number of pins: 03; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847479 8A 320V
+phoenix_contact connector MC_01x03_GF_5.08mm_MH
+0
+3
+3
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_4-G-5.08_1x04_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/4-G-5.08; number of pins: 04; pin pitch: 5.08mm; Angled || order number: 1836202 8A 320V
+phoenix_contact connector MC_01x04_G_5.08mm
+0
+4
+4
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_4-GF-5.08_1x04_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/4-GF-5.08; number of pins: 04; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847482 8A 320V
+phoenix_contact connector MC_01x04_GF_5.08mm
+0
+4
+4
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_4-GF-5.08_1x04_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/4-GF-5.08; number of pins: 04; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847482 8A 320V
+phoenix_contact connector MC_01x04_GF_5.08mm_MH
+0
+4
+4
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_5-G-5.08_1x05_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/5-G-5.08; number of pins: 05; pin pitch: 5.08mm; Angled || order number: 1836215 8A 320V
+phoenix_contact connector MC_01x05_G_5.08mm
+0
+5
+5
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_5-GF-5.08_1x05_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/5-GF-5.08; number of pins: 05; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847495 8A 320V
+phoenix_contact connector MC_01x05_GF_5.08mm
+0
+5
+5
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_5-GF-5.08_1x05_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/5-GF-5.08; number of pins: 05; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847495 8A 320V
+phoenix_contact connector MC_01x05_GF_5.08mm_MH
+0
+5
+5
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_6-G-5.08_1x06_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/6-G-5.08; number of pins: 06; pin pitch: 5.08mm; Angled || order number: 1836228 8A 320V
+phoenix_contact connector MC_01x06_G_5.08mm
+0
+6
+6
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_6-GF-5.08_1x06_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/6-GF-5.08; number of pins: 06; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847505 8A 320V
+phoenix_contact connector MC_01x06_GF_5.08mm
+0
+6
+6
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_6-GF-5.08_1x06_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/6-GF-5.08; number of pins: 06; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847505 8A 320V
+phoenix_contact connector MC_01x06_GF_5.08mm_MH
+0
+6
+6
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_7-G-5.08_1x07_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/7-G-5.08; number of pins: 07; pin pitch: 5.08mm; Angled || order number: 1836231 8A 320V
+phoenix_contact connector MC_01x07_G_5.08mm
+0
+7
+7
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_7-GF-5.08_1x07_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/7-GF-5.08; number of pins: 07; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847518 8A 320V
+phoenix_contact connector MC_01x07_GF_5.08mm
+0
+7
+7
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_7-GF-5.08_1x07_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/7-GF-5.08; number of pins: 07; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847518 8A 320V
+phoenix_contact connector MC_01x07_GF_5.08mm_MH
+0
+7
+7
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_8-G-5.08_1x08_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/8-G-5.08; number of pins: 08; pin pitch: 5.08mm; Angled || order number: 1836244 8A 320V
+phoenix_contact connector MC_01x08_G_5.08mm
+0
+8
+8
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_8-GF-5.08_1x08_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/8-GF-5.08; number of pins: 08; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847521 8A 320V
+phoenix_contact connector MC_01x08_GF_5.08mm
+0
+8
+8
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_8-GF-5.08_1x08_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/8-GF-5.08; number of pins: 08; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847521 8A 320V
+phoenix_contact connector MC_01x08_GF_5.08mm_MH
+0
+8
+8
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_9-G-5.08_1x09_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/9-G-5.08; number of pins: 09; pin pitch: 5.08mm; Angled || order number: 1836257 8A 320V
+phoenix_contact connector MC_01x09_G_5.08mm
+0
+9
+9
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_9-GF-5.08_1x09_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/9-GF-5.08; number of pins: 09; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847534 8A 320V
+phoenix_contact connector MC_01x09_GF_5.08mm
+0
+9
+9
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_9-GF-5.08_1x09_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/9-GF-5.08; number of pins: 09; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847534 8A 320V
+phoenix_contact connector MC_01x09_GF_5.08mm_MH
+0
+9
+9
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_10-G-5.08_1x10_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/10-G-5.08; number of pins: 10; pin pitch: 5.08mm; Angled || order number: 1836260 8A 320V
+phoenix_contact connector MC_01x10_G_5.08mm
+0
+10
+10
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_10-GF-5.08_1x10_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/10-GF-5.08; number of pins: 10; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847547 8A 320V
+phoenix_contact connector MC_01x10_GF_5.08mm
+0
+10
+10
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_10-GF-5.08_1x10_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/10-GF-5.08; number of pins: 10; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847547 8A 320V
+phoenix_contact connector MC_01x10_GF_5.08mm_MH
+0
+10
+10
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_11-G-5.08_1x11_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/11-G-5.08; number of pins: 11; pin pitch: 5.08mm; Angled || order number: 1836273 8A 320V
+phoenix_contact connector MC_01x11_G_5.08mm
+0
+11
+11
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_11-GF-5.08_1x11_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/11-GF-5.08; number of pins: 11; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847550 8A 320V
+phoenix_contact connector MC_01x11_GF_5.08mm
+0
+11
+11
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_11-GF-5.08_1x11_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/11-GF-5.08; number of pins: 11; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847550 8A 320V
+phoenix_contact connector MC_01x11_GF_5.08mm_MH
+0
+11
+11
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_12-G-5.08_1x12_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MC_1,5/12-G-5.08; number of pins: 12; pin pitch: 5.08mm; Angled || order number: 1836286 8A 320V
+phoenix_contact connector MC_01x12_G_5.08mm
+0
+12
+12
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_12-GF-5.08_1x12_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MC_1,5/12-GF-5.08; number of pins: 12; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847563 8A 320V
+phoenix_contact connector MC_01x12_GF_5.08mm
+0
+12
+12
+Connector_Phoenix_MC_HighVoltage
+PhoenixContact_MC_1,5_12-GF-5.08_1x12_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MC_1,5/12-GF-5.08; number of pins: 12; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847563 8A 320V
+phoenix_contact connector MC_01x12_GF_5.08mm_MH
+0
+12
+12
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_2-G-5,08_1x02_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/2-G-5,08; number of pins: 02; pin pitch: 5.08mm; Angled || order number: 1757242 12A || order number: 1923869 16A (HC)
+phoenix_contact connector MSTBA_01x02_G_5.08mm
+0
+2
+2
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_2-G_1x02_P5.00mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/2-G; number of pins: 02; pin pitch: 5.00mm; Angled || order number: 1757475 12A || order number: 1923759 16A (HC)
+phoenix_contact connector MSTBA_01x02_G_5.00mm
+0
+2
+2
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_3-G-5,08_1x03_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/3-G-5,08; number of pins: 03; pin pitch: 5.08mm; Angled || order number: 1757255 12A || order number: 1923872 16A (HC)
+phoenix_contact connector MSTBA_01x03_G_5.08mm
+0
+3
+3
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_3-G_1x03_P5.00mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/3-G; number of pins: 03; pin pitch: 5.00mm; Angled || order number: 1757488 12A || order number: 1923762 16A (HC)
+phoenix_contact connector MSTBA_01x03_G_5.00mm
+0
+3
+3
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_4-G-5,08_1x04_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/4-G-5,08; number of pins: 04; pin pitch: 5.08mm; Angled || order number: 1757268 12A || order number: 1923885 16A (HC)
+phoenix_contact connector MSTBA_01x04_G_5.08mm
+0
+4
+4
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_4-G_1x04_P5.00mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/4-G; number of pins: 04; pin pitch: 5.00mm; Angled || order number: 1757491 12A || order number: 1923775 16A (HC)
+phoenix_contact connector MSTBA_01x04_G_5.00mm
+0
+4
+4
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_5-G-5,08_1x05_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/5-G-5,08; number of pins: 05; pin pitch: 5.08mm; Angled || order number: 1757271 12A || order number: 1923898 16A (HC)
+phoenix_contact connector MSTBA_01x05_G_5.08mm
+0
+5
+5
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_5-G_1x05_P5.00mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/5-G; number of pins: 05; pin pitch: 5.00mm; Angled || order number: 1757501 12A || order number: 1923788 16A (HC)
+phoenix_contact connector MSTBA_01x05_G_5.00mm
+0
+5
+5
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_6-G-5,08_1x06_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/6-G-5,08; number of pins: 06; pin pitch: 5.08mm; Angled || order number: 1757284 12A || order number: 1923908 16A (HC)
+phoenix_contact connector MSTBA_01x06_G_5.08mm
+0
+6
+6
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_6-G_1x06_P5.00mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/6-G; number of pins: 06; pin pitch: 5.00mm; Angled || order number: 1757514 12A || order number: 1923791 16A (HC)
+phoenix_contact connector MSTBA_01x06_G_5.00mm
+0
+6
+6
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_7-G-5,08_1x07_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/7-G-5,08; number of pins: 07; pin pitch: 5.08mm; Angled || order number: 1757297 12A || order number: 1923911 16A (HC)
+phoenix_contact connector MSTBA_01x07_G_5.08mm
+0
+7
+7
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_7-G_1x07_P5.00mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/7-G; number of pins: 07; pin pitch: 5.00mm; Angled || order number: 1757493 12A || order number: 1923801 16A (HC)
+phoenix_contact connector MSTBA_01x07_G_5.00mm
+0
+7
+7
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_8-G-5,08_1x08_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/8-G-5,08; number of pins: 08; pin pitch: 5.08mm; Angled || order number: 1757307 12A || order number: 1923924 16A (HC)
+phoenix_contact connector MSTBA_01x08_G_5.08mm
+0
+8
+8
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_8-G_1x08_P5.00mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/8-G; number of pins: 08; pin pitch: 5.00mm; Angled || order number: 1757527 12A || order number: 1923814 16A (HC)
+phoenix_contact connector MSTBA_01x08_G_5.00mm
+0
+8
+8
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_9-G-5,08_1x09_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/9-G-5,08; number of pins: 09; pin pitch: 5.08mm; Angled || order number: 1757310 12A || order number: 1923937 16A (HC)
+phoenix_contact connector MSTBA_01x09_G_5.08mm
+0
+9
+9
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_9-G_1x09_P5.00mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/9-G; number of pins: 09; pin pitch: 5.00mm; Angled || order number: 1757530 12A || order number: 1923827 16A (HC)
+phoenix_contact connector MSTBA_01x09_G_5.00mm
+0
+9
+9
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_10-G-5,08_1x10_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/10-G-5,08; number of pins: 10; pin pitch: 5.08mm; Angled || order number: 1757323 12A || order number: 1923940 16A (HC)
+phoenix_contact connector MSTBA_01x10_G_5.08mm
+0
+10
+10
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_10-G_1x10_P5.00mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/10-G; number of pins: 10; pin pitch: 5.00mm; Angled || order number: 1757543 12A || order number: 1923830 16A (HC)
+phoenix_contact connector MSTBA_01x10_G_5.00mm
+0
+10
+10
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_11-G-5,08_1x11_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/11-G-5,08; number of pins: 11; pin pitch: 5.08mm; Angled || order number: 1757336 12A || order number: 1923953 16A (HC)
+phoenix_contact connector MSTBA_01x11_G_5.08mm
+0
+11
+11
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_11-G_1x11_P5.00mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/11-G; number of pins: 11; pin pitch: 5.00mm; Angled || order number: 1757556 12A || order number: 1923843 16A (HC)
+phoenix_contact connector MSTBA_01x11_G_5.00mm
+0
+11
+11
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_12-G-5,08_1x12_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/12-G-5,08; number of pins: 12; pin pitch: 5.08mm; Angled || order number: 1757349 12A || order number: 1923966 16A (HC)
+phoenix_contact connector MSTBA_01x12_G_5.08mm
+0
+12
+12
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_12-G_1x12_P5.00mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/12-G; number of pins: 12; pin pitch: 5.00mm; Angled || order number: 1757569 12A || order number: 1923856 16A (HC)
+phoenix_contact connector MSTBA_01x12_G_5.00mm
+0
+12
+12
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_13-G-5,08_1x13_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/13-G-5,08; number of pins: 13; pin pitch: 5.08mm; Angled || order number: 1757352 12A
+phoenix_contact connector MSTBA_01x13_G_5.08mm
+0
+13
+13
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_13-G_1x13_P5.00mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/13-G; number of pins: 13; pin pitch: 5.00mm; Angled || order number: 1757572 12A
+phoenix_contact connector MSTBA_01x13_G_5.00mm
+0
+13
+13
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_14-G-5,08_1x14_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/14-G-5,08; number of pins: 14; pin pitch: 5.08mm; Angled || order number: 1757365 12A
+phoenix_contact connector MSTBA_01x14_G_5.08mm
+0
+14
+14
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_14-G_1x14_P5.00mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/14-G; number of pins: 14; pin pitch: 5.00mm; Angled || order number: 1757585 12A
+phoenix_contact connector MSTBA_01x14_G_5.00mm
+0
+14
+14
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_15-G-5,08_1x15_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/15-G-5,08; number of pins: 15; pin pitch: 5.08mm; Angled || order number: 1757378 12A
+phoenix_contact connector MSTBA_01x15_G_5.08mm
+0
+15
+15
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_15-G_1x15_P5.00mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/15-G; number of pins: 15; pin pitch: 5.00mm; Angled || order number: 1757598 12A
+phoenix_contact connector MSTBA_01x15_G_5.00mm
+0
+15
+15
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_16-G-5,08_1x16_P5.08mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/16-G-5,08; number of pins: 16; pin pitch: 5.08mm; Angled || order number: 1757381 12A
+phoenix_contact connector MSTBA_01x16_G_5.08mm
+0
+16
+16
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBA_2,5_16-G_1x16_P5.00mm_Horizontal
+Generic Phoenix Contact connector footprint for: MSTBA_2,5/16-G; number of pins: 16; pin pitch: 5.00mm; Angled || order number: 1757608 12A
+phoenix_contact connector MSTBA_01x16_G_5.00mm
+0
+16
+16
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_2-G-5,08_1x02_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/2-G-5,08; number of pins: 02; pin pitch: 5.08mm; Vertical || order number: 1755736 12A || order number: 1924305 16A (HC)
+phoenix_contact connector MSTBVA_01x02_G_5.08mm
+0
+2
+2
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_2-G_1x02_P5.00mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/2-G; number of pins: 02; pin pitch: 5.00mm; Vertical || order number: 1755516 12A || order number: 1924198 16A (HC)
+phoenix_contact connector MSTBVA_01x02_G_5.00mm
+0
+2
+2
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_3-G-5,08_1x03_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/3-G-5,08; number of pins: 03; pin pitch: 5.08mm; Vertical || order number: 1755749 12A || order number: 1924318 16A (HC)
+phoenix_contact connector MSTBVA_01x03_G_5.08mm
+0
+3
+3
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_3-G_1x03_P5.00mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/3-G; number of pins: 03; pin pitch: 5.00mm; Vertical || order number: 1755529 12A || order number: 1924208 16A (HC)
+phoenix_contact connector MSTBVA_01x03_G_5.00mm
+0
+3
+3
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_4-G-5,08_1x04_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/4-G-5,08; number of pins: 04; pin pitch: 5.08mm; Vertical || order number: 1755752 12A || order number: 1924321 16A (HC)
+phoenix_contact connector MSTBVA_01x04_G_5.08mm
+0
+4
+4
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_4-G_1x04_P5.00mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/4-G; number of pins: 04; pin pitch: 5.00mm; Vertical || order number: 1755532 12A || order number: 1924211 16A (HC)
+phoenix_contact connector MSTBVA_01x04_G_5.00mm
+0
+4
+4
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_5-G-5,08_1x05_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/5-G-5,08; number of pins: 05; pin pitch: 5.08mm; Vertical || order number: 1755765 12A || order number: 1924334 16A (HC)
+phoenix_contact connector MSTBVA_01x05_G_5.08mm
+0
+5
+5
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_5-G_1x05_P5.00mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/5-G; number of pins: 05; pin pitch: 5.00mm; Vertical || order number: 1755545 12A || order number: 1924224 16A (HC)
+phoenix_contact connector MSTBVA_01x05_G_5.00mm
+0
+5
+5
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_6-G-5,08_1x06_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/6-G-5,08; number of pins: 06; pin pitch: 5.08mm; Vertical || order number: 1755778 12A || order number: 1924347 16A (HC)
+phoenix_contact connector MSTBVA_01x06_G_5.08mm
+0
+6
+6
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_6-G_1x06_P5.00mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/6-G; number of pins: 06; pin pitch: 5.00mm; Vertical || order number: 1755558 12A || order number: 1924237 16A (HC)
+phoenix_contact connector MSTBVA_01x06_G_5.00mm
+0
+6
+6
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_7-G-5,08_1x07_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/7-G-5,08; number of pins: 07; pin pitch: 5.08mm; Vertical || order number: 1755781 12A || order number: 1924350 16A (HC)
+phoenix_contact connector MSTBVA_01x07_G_5.08mm
+0
+7
+7
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_7-G_1x07_P5.00mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/7-G; number of pins: 07; pin pitch: 5.00mm; Vertical || order number: 1755561 12A || order number: 1924240 16A (HC)
+phoenix_contact connector MSTBVA_01x07_G_5.00mm
+0
+7
+7
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_8-G-5,08_1x08_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/8-G-5,08; number of pins: 08; pin pitch: 5.08mm; Vertical || order number: 1755794 12A || order number: 1924363 16A (HC)
+phoenix_contact connector MSTBVA_01x08_G_5.08mm
+0
+8
+8
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_8-G_1x08_P5.00mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/8-G; number of pins: 08; pin pitch: 5.00mm; Vertical || order number: 1755574 12A || order number: 1924253 16A (HC)
+phoenix_contact connector MSTBVA_01x08_G_5.00mm
+0
+8
+8
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_9-G-5,08_1x09_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/9-G-5,08; number of pins: 09; pin pitch: 5.08mm; Vertical || order number: 1755804 12A || order number: 1924376 16A (HC)
+phoenix_contact connector MSTBVA_01x09_G_5.08mm
+0
+9
+9
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_9-G_1x09_P5.00mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/9-G; number of pins: 09; pin pitch: 5.00mm; Vertical || order number: 1755587 12A || order number: 1924266 16A (HC)
+phoenix_contact connector MSTBVA_01x09_G_5.00mm
+0
+9
+9
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_10-G-5,08_1x10_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/10-G-5,08; number of pins: 10; pin pitch: 5.08mm; Vertical || order number: 1755817 12A || order number: 1924389 16A (HC)
+phoenix_contact connector MSTBVA_01x10_G_5.08mm
+0
+10
+10
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_10-G_1x10_P5.00mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/10-G; number of pins: 10; pin pitch: 5.00mm; Vertical || order number: 1755503 12A || order number: 1924279 16A (HC)
+phoenix_contact connector MSTBVA_01x10_G_5.00mm
+0
+10
+10
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_11-G-5,08_1x11_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/11-G-5,08; number of pins: 11; pin pitch: 5.08mm; Vertical || order number: 1755820 12A || order number: 1924392 16A (HC)
+phoenix_contact connector MSTBVA_01x11_G_5.08mm
+0
+11
+11
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_11-G_1x11_P5.00mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/11-G; number of pins: 11; pin pitch: 5.00mm; Vertical || order number: 1755590 12A || order number: 1924282 16A (HC)
+phoenix_contact connector MSTBVA_01x11_G_5.00mm
+0
+11
+11
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_12-G-5,08_1x12_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/12-G-5,08; number of pins: 12; pin pitch: 5.08mm; Vertical || order number: 1755833 12A || order number: 1924402 16A (HC)
+phoenix_contact connector MSTBVA_01x12_G_5.08mm
+0
+12
+12
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_12-G_1x12_P5.00mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/12-G; number of pins: 12; pin pitch: 5.00mm; Vertical || order number: 1755600 12A || order number: 1924295 16A (HC)
+phoenix_contact connector MSTBVA_01x12_G_5.00mm
+0
+12
+12
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_13-G-5,08_1x13_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/13-G-5,08; number of pins: 13; pin pitch: 5.08mm; Vertical || order number: 1755846 12A
+phoenix_contact connector MSTBVA_01x13_G_5.08mm
+0
+13
+13
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_13-G_1x13_P5.00mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/13-G; number of pins: 13; pin pitch: 5.00mm; Vertical || order number: 1755613 12A
+phoenix_contact connector MSTBVA_01x13_G_5.00mm
+0
+13
+13
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_14-G-5,08_1x14_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/14-G-5,08; number of pins: 14; pin pitch: 5.08mm; Vertical || order number: 1755859 12A
+phoenix_contact connector MSTBVA_01x14_G_5.08mm
+0
+14
+14
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_14-G_1x14_P5.00mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/14-G; number of pins: 14; pin pitch: 5.00mm; Vertical || order number: 1755626 12A
+phoenix_contact connector MSTBVA_01x14_G_5.00mm
+0
+14
+14
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_15-G-5,08_1x15_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/15-G-5,08; number of pins: 15; pin pitch: 5.08mm; Vertical || order number: 1755862 12A
+phoenix_contact connector MSTBVA_01x15_G_5.08mm
+0
+15
+15
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_15-G_1x15_P5.00mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/15-G; number of pins: 15; pin pitch: 5.00mm; Vertical || order number: 1755639 12A
+phoenix_contact connector MSTBVA_01x15_G_5.00mm
+0
+15
+15
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_16-G-5,08_1x16_P5.08mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/16-G-5,08; number of pins: 16; pin pitch: 5.08mm; Vertical || order number: 1755875 12A
+phoenix_contact connector MSTBVA_01x16_G_5.08mm
+0
+16
+16
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBVA_2,5_16-G_1x16_P5.00mm_Vertical
+Generic Phoenix Contact connector footprint for: MSTBVA_2,5/16-G; number of pins: 16; pin pitch: 5.00mm; Vertical || order number: 1755642 12A
+phoenix_contact connector MSTBVA_01x16_G_5.00mm
+0
+16
+16
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_2-GF-5,08_1x02_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/2-GF-5,08; number of pins: 02; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777073 12A || order number: 1924525 16A (HC)
+phoenix_contact connector MSTBV_01x02_GF_5.08mm
+0
+2
+2
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_2-GF-5,08_1x02_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/2-GF-5,08; number of pins: 02; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777073 12A || order number: 1924525 16A (HC)
+phoenix_contact connector MSTBV_01x02_GF_5.08mm_MH
+0
+2
+2
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_2-GF_1x02_P5.00mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/2-GF; number of pins: 02; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776883 12A || order number: 1924415 16A (HC)
+phoenix_contact connector MSTBV_01x02_GF_5.00mm
+0
+2
+2
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_2-GF_1x02_P5.00mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/2-GF; number of pins: 02; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776883 12A || order number: 1924415 16A (HC)
+phoenix_contact connector MSTBV_01x02_GF_5.00mm_MH
+0
+2
+2
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_3-GF-5,08_1x03_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/3-GF-5,08; number of pins: 03; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777086 12A || order number: 1924538 16A (HC)
+phoenix_contact connector MSTBV_01x03_GF_5.08mm
+0
+3
+3
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_3-GF-5,08_1x03_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/3-GF-5,08; number of pins: 03; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777086 12A || order number: 1924538 16A (HC)
+phoenix_contact connector MSTBV_01x03_GF_5.08mm_MH
+0
+3
+3
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_3-GF_1x03_P5.00mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/3-GF; number of pins: 03; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776896 12A || order number: 1924428 16A (HC)
+phoenix_contact connector MSTBV_01x03_GF_5.00mm
+0
+3
+3
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_3-GF_1x03_P5.00mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/3-GF; number of pins: 03; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776896 12A || order number: 1924428 16A (HC)
+phoenix_contact connector MSTBV_01x03_GF_5.00mm_MH
+0
+3
+3
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_4-GF-5,08_1x04_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/4-GF-5,08; number of pins: 04; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777099 12A || order number: 1924541 16A (HC)
+phoenix_contact connector MSTBV_01x04_GF_5.08mm
+0
+4
+4
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_4-GF-5,08_1x04_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/4-GF-5,08; number of pins: 04; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777099 12A || order number: 1924541 16A (HC)
+phoenix_contact connector MSTBV_01x04_GF_5.08mm_MH
+0
+4
+4
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_4-GF_1x04_P5.00mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/4-GF; number of pins: 04; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776906 12A || order number: 1924431 16A (HC)
+phoenix_contact connector MSTBV_01x04_GF_5.00mm
+0
+4
+4
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_4-GF_1x04_P5.00mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/4-GF; number of pins: 04; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776906 12A || order number: 1924431 16A (HC)
+phoenix_contact connector MSTBV_01x04_GF_5.00mm_MH
+0
+4
+4
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_5-GF-5,08_1x05_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/5-GF-5,08; number of pins: 05; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777109 12A || order number: 1924554 16A (HC)
+phoenix_contact connector MSTBV_01x05_GF_5.08mm
+0
+5
+5
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_5-GF-5,08_1x05_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/5-GF-5,08; number of pins: 05; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777109 12A || order number: 1924554 16A (HC)
+phoenix_contact connector MSTBV_01x05_GF_5.08mm_MH
+0
+5
+5
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_5-GF_1x05_P5.00mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/5-GF; number of pins: 05; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776919 12A || order number: 1924444 16A (HC)
+phoenix_contact connector MSTBV_01x05_GF_5.00mm
+0
+5
+5
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_5-GF_1x05_P5.00mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/5-GF; number of pins: 05; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776919 12A || order number: 1924444 16A (HC)
+phoenix_contact connector MSTBV_01x05_GF_5.00mm_MH
+0
+5
+5
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_6-GF-5,08_1x06_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/6-GF-5,08; number of pins: 06; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777112 12A || order number: 1924567 16A (HC)
+phoenix_contact connector MSTBV_01x06_GF_5.08mm
+0
+6
+6
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_6-GF-5,08_1x06_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/6-GF-5,08; number of pins: 06; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777112 12A || order number: 1924567 16A (HC)
+phoenix_contact connector MSTBV_01x06_GF_5.08mm_MH
+0
+6
+6
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_6-GF_1x06_P5.00mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/6-GF; number of pins: 06; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776922 12A || order number: 1924457 16A (HC)
+phoenix_contact connector MSTBV_01x06_GF_5.00mm
+0
+6
+6
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_6-GF_1x06_P5.00mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/6-GF; number of pins: 06; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776922 12A || order number: 1924457 16A (HC)
+phoenix_contact connector MSTBV_01x06_GF_5.00mm_MH
+0
+6
+6
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_7-GF-5,08_1x07_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/7-GF-5,08; number of pins: 07; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777125 12A || order number: 1924570 16A (HC)
+phoenix_contact connector MSTBV_01x07_GF_5.08mm
+0
+7
+7
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_7-GF-5,08_1x07_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/7-GF-5,08; number of pins: 07; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777125 12A || order number: 1924570 16A (HC)
+phoenix_contact connector MSTBV_01x07_GF_5.08mm_MH
+0
+7
+7
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_7-GF_1x07_P5.00mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/7-GF; number of pins: 07; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776935 12A || order number: 1924460 16A (HC)
+phoenix_contact connector MSTBV_01x07_GF_5.00mm
+0
+7
+7
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_7-GF_1x07_P5.00mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/7-GF; number of pins: 07; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776935 12A || order number: 1924460 16A (HC)
+phoenix_contact connector MSTBV_01x07_GF_5.00mm_MH
+0
+7
+7
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_8-GF-5,08_1x08_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/8-GF-5,08; number of pins: 08; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777138 12A || order number: 1924583 16A (HC)
+phoenix_contact connector MSTBV_01x08_GF_5.08mm
+0
+8
+8
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_8-GF-5,08_1x08_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/8-GF-5,08; number of pins: 08; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777138 12A || order number: 1924583 16A (HC)
+phoenix_contact connector MSTBV_01x08_GF_5.08mm_MH
+0
+8
+8
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_8-GF_1x08_P5.00mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/8-GF; number of pins: 08; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776948 12A || order number: 1924473 16A (HC)
+phoenix_contact connector MSTBV_01x08_GF_5.00mm
+0
+8
+8
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_8-GF_1x08_P5.00mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/8-GF; number of pins: 08; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776948 12A || order number: 1924473 16A (HC)
+phoenix_contact connector MSTBV_01x08_GF_5.00mm_MH
+0
+8
+8
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_9-GF-5,08_1x09_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/9-GF-5,08; number of pins: 09; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777141 12A || order number: 1924596 16A (HC)
+phoenix_contact connector MSTBV_01x09_GF_5.08mm
+0
+9
+9
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_9-GF-5,08_1x09_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/9-GF-5,08; number of pins: 09; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777141 12A || order number: 1924596 16A (HC)
+phoenix_contact connector MSTBV_01x09_GF_5.08mm_MH
+0
+9
+9
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_9-GF_1x09_P5.00mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/9-GF; number of pins: 09; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776951 12A || order number: 1924486 16A (HC)
+phoenix_contact connector MSTBV_01x09_GF_5.00mm
+0
+9
+9
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_9-GF_1x09_P5.00mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/9-GF; number of pins: 09; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776951 12A || order number: 1924486 16A (HC)
+phoenix_contact connector MSTBV_01x09_GF_5.00mm_MH
+0
+9
+9
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_10-GF-5,08_1x10_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/10-GF-5,08; number of pins: 10; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777154 12A || order number: 1924606 16A (HC)
+phoenix_contact connector MSTBV_01x10_GF_5.08mm
+0
+10
+10
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_10-GF-5,08_1x10_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/10-GF-5,08; number of pins: 10; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777154 12A || order number: 1924606 16A (HC)
+phoenix_contact connector MSTBV_01x10_GF_5.08mm_MH
+0
+10
+10
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_10-GF_1x10_P5.00mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/10-GF; number of pins: 10; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776964 12A || order number: 1924499 16A (HC)
+phoenix_contact connector MSTBV_01x10_GF_5.00mm
+0
+10
+10
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_10-GF_1x10_P5.00mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/10-GF; number of pins: 10; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776964 12A || order number: 1924499 16A (HC)
+phoenix_contact connector MSTBV_01x10_GF_5.00mm_MH
+0
+10
+10
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_11-GF-5,08_1x11_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/11-GF-5,08; number of pins: 11; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777167 12A || order number: 1924619 16A (HC)
+phoenix_contact connector MSTBV_01x11_GF_5.08mm
+0
+11
+11
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_11-GF-5,08_1x11_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/11-GF-5,08; number of pins: 11; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777167 12A || order number: 1924619 16A (HC)
+phoenix_contact connector MSTBV_01x11_GF_5.08mm_MH
+0
+11
+11
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_11-GF_1x11_P5.00mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/11-GF; number of pins: 11; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776977 12A || order number: 1924509 16A (HC)
+phoenix_contact connector MSTBV_01x11_GF_5.00mm
+0
+11
+11
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_11-GF_1x11_P5.00mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/11-GF; number of pins: 11; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776977 12A || order number: 1924509 16A (HC)
+phoenix_contact connector MSTBV_01x11_GF_5.00mm_MH
+0
+11
+11
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_12-GF-5,08_1x12_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/12-GF-5,08; number of pins: 12; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777170 12A || order number: 1924622 16A (HC)
+phoenix_contact connector MSTBV_01x12_GF_5.08mm
+0
+12
+12
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_12-GF-5,08_1x12_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/12-GF-5,08; number of pins: 12; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777170 12A || order number: 1924622 16A (HC)
+phoenix_contact connector MSTBV_01x12_GF_5.08mm_MH
+0
+12
+12
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_12-GF_1x12_P5.00mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/12-GF; number of pins: 12; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776980 12A || order number: 1924512 16A (HC)
+phoenix_contact connector MSTBV_01x12_GF_5.00mm
+0
+12
+12
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_12-GF_1x12_P5.00mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/12-GF; number of pins: 12; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776980 12A || order number: 1924512 16A (HC)
+phoenix_contact connector MSTBV_01x12_GF_5.00mm_MH
+0
+12
+12
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_13-GF-5,08_1x13_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/13-GF-5,08; number of pins: 13; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777183 12A
+phoenix_contact connector MSTBV_01x13_GF_5.08mm
+0
+13
+13
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_13-GF-5,08_1x13_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/13-GF-5,08; number of pins: 13; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777183 12A
+phoenix_contact connector MSTBV_01x13_GF_5.08mm_MH
+0
+13
+13
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_13-GF_1x13_P5.00mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/13-GF; number of pins: 13; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776993 12A
+phoenix_contact connector MSTBV_01x13_GF_5.00mm
+0
+13
+13
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_13-GF_1x13_P5.00mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/13-GF; number of pins: 13; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776993 12A
+phoenix_contact connector MSTBV_01x13_GF_5.00mm_MH
+0
+13
+13
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_14-GF-5,08_1x14_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/14-GF-5,08; number of pins: 14; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777196 12A
+phoenix_contact connector MSTBV_01x14_GF_5.08mm
+0
+14
+14
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_14-GF-5,08_1x14_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/14-GF-5,08; number of pins: 14; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777196 12A
+phoenix_contact connector MSTBV_01x14_GF_5.08mm_MH
+0
+14
+14
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_14-GF_1x14_P5.00mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/14-GF; number of pins: 14; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776002 12A
+phoenix_contact connector MSTBV_01x14_GF_5.00mm
+0
+14
+14
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_14-GF_1x14_P5.00mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/14-GF; number of pins: 14; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776002 12A
+phoenix_contact connector MSTBV_01x14_GF_5.00mm_MH
+0
+14
+14
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_15-GF-5,08_1x15_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/15-GF-5,08; number of pins: 15; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777206 12A
+phoenix_contact connector MSTBV_01x15_GF_5.08mm
+0
+15
+15
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_15-GF-5,08_1x15_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/15-GF-5,08; number of pins: 15; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777206 12A
+phoenix_contact connector MSTBV_01x15_GF_5.08mm_MH
+0
+15
+15
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_15-GF_1x15_P5.00mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/15-GF; number of pins: 15; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776015 12A
+phoenix_contact connector MSTBV_01x15_GF_5.00mm
+0
+15
+15
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_15-GF_1x15_P5.00mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/15-GF; number of pins: 15; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776015 12A
+phoenix_contact connector MSTBV_01x15_GF_5.00mm_MH
+0
+15
+15
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_16-GF-5,08_1x16_P5.08mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/16-GF-5,08; number of pins: 16; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777219 12A
+phoenix_contact connector MSTBV_01x16_GF_5.08mm
+0
+16
+16
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_16-GF-5,08_1x16_P5.08mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/16-GF-5,08; number of pins: 16; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777219 12A
+phoenix_contact connector MSTBV_01x16_GF_5.08mm_MH
+0
+16
+16
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_16-GF_1x16_P5.00mm_Vertical_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/16-GF; number of pins: 16; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776028 12A
+phoenix_contact connector MSTBV_01x16_GF_5.00mm
+0
+16
+16
+Connector_Phoenix_MSTB
+PhoenixContact_MSTBV_2,5_16-GF_1x16_P5.00mm_Vertical_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTBV_2,5/16-GF; number of pins: 16; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776028 12A
+phoenix_contact connector MSTBV_01x16_GF_5.00mm_MH
+0
+16
+16
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_2-GF-5,08_1x02_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/2-GF-5,08; number of pins: 02; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776508 12A || order number: 1924088 16A (HC)
+phoenix_contact connector MSTB_01x02_GF_5.08mm
+0
+2
+2
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_2-GF-5,08_1x02_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/2-GF-5,08; number of pins: 02; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776508 12A || order number: 1924088 16A (HC)
+phoenix_contact connector MSTB_01x02_GF_5.08mm_MH
+0
+2
+2
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_2-GF_1x02_P5.00mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/2-GF; number of pins: 02; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776692 12A || order number: 1923979 16A (HC)
+phoenix_contact connector MSTB_01x02_GF_5.00mm
+0
+2
+2
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_2-GF_1x02_P5.00mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/2-GF; number of pins: 02; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776692 12A || order number: 1923979 16A (HC)
+phoenix_contact connector MSTB_01x02_GF_5.00mm_MH
+0
+2
+2
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_3-GF-5,08_1x03_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/3-GF-5,08; number of pins: 03; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776511 12A || order number: 1924091 16A (HC)
+phoenix_contact connector MSTB_01x03_GF_5.08mm
+0
+3
+3
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_3-GF-5,08_1x03_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/3-GF-5,08; number of pins: 03; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776511 12A || order number: 1924091 16A (HC)
+phoenix_contact connector MSTB_01x03_GF_5.08mm_MH
+0
+3
+3
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_3-GF_1x03_P5.00mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/3-GF; number of pins: 03; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776702 12A || order number: 1923982 16A (HC)
+phoenix_contact connector MSTB_01x03_GF_5.00mm
+0
+3
+3
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_3-GF_1x03_P5.00mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/3-GF; number of pins: 03; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776702 12A || order number: 1923982 16A (HC)
+phoenix_contact connector MSTB_01x03_GF_5.00mm_MH
+0
+3
+3
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_4-GF-5,08_1x04_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/4-GF-5,08; number of pins: 04; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776524 12A || order number: 1924101 16A (HC)
+phoenix_contact connector MSTB_01x04_GF_5.08mm
+0
+4
+4
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_4-GF-5,08_1x04_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/4-GF-5,08; number of pins: 04; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776524 12A || order number: 1924101 16A (HC)
+phoenix_contact connector MSTB_01x04_GF_5.08mm_MH
+0
+4
+4
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_4-GF_1x04_P5.00mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/4-GF; number of pins: 04; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776715 12A || order number: 1923995 16A (HC)
+phoenix_contact connector MSTB_01x04_GF_5.00mm
+0
+4
+4
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_4-GF_1x04_P5.00mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/4-GF; number of pins: 04; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776715 12A || order number: 1923995 16A (HC)
+phoenix_contact connector MSTB_01x04_GF_5.00mm_MH
+0
+4
+4
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_5-GF-5,08_1x05_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/5-GF-5,08; number of pins: 05; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776537 12A || order number: 1924114 16A (HC)
+phoenix_contact connector MSTB_01x05_GF_5.08mm
+0
+5
+5
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_5-GF-5,08_1x05_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/5-GF-5,08; number of pins: 05; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776537 12A || order number: 1924114 16A (HC)
+phoenix_contact connector MSTB_01x05_GF_5.08mm_MH
+0
+5
+5
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_5-GF_1x05_P5.00mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/5-GF; number of pins: 05; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776728 12A || order number: 1924004 16A (HC)
+phoenix_contact connector MSTB_01x05_GF_5.00mm
+0
+5
+5
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_5-GF_1x05_P5.00mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/5-GF; number of pins: 05; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776728 12A || order number: 1924004 16A (HC)
+phoenix_contact connector MSTB_01x05_GF_5.00mm_MH
+0
+5
+5
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_6-GF-5,08_1x06_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/6-GF-5,08; number of pins: 06; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776540 12A || order number: 1924127 16A (HC)
+phoenix_contact connector MSTB_01x06_GF_5.08mm
+0
+6
+6
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_6-GF-5,08_1x06_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/6-GF-5,08; number of pins: 06; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776540 12A || order number: 1924127 16A (HC)
+phoenix_contact connector MSTB_01x06_GF_5.08mm_MH
+0
+6
+6
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_6-GF_1x06_P5.00mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/6-GF; number of pins: 06; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776731 12A || order number: 1924017 16A (HC)
+phoenix_contact connector MSTB_01x06_GF_5.00mm
+0
+6
+6
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_6-GF_1x06_P5.00mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/6-GF; number of pins: 06; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776731 12A || order number: 1924017 16A (HC)
+phoenix_contact connector MSTB_01x06_GF_5.00mm_MH
+0
+6
+6
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_7-GF-5,08_1x07_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/7-GF-5,08; number of pins: 07; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776553 12A || order number: 1924130 16A (HC)
+phoenix_contact connector MSTB_01x07_GF_5.08mm
+0
+7
+7
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_7-GF-5,08_1x07_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/7-GF-5,08; number of pins: 07; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776553 12A || order number: 1924130 16A (HC)
+phoenix_contact connector MSTB_01x07_GF_5.08mm_MH
+0
+7
+7
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_7-GF_1x07_P5.00mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/7-GF; number of pins: 07; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776744 12A || order number: 1924020 16A (HC)
+phoenix_contact connector MSTB_01x07_GF_5.00mm
+0
+7
+7
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_7-GF_1x07_P5.00mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/7-GF; number of pins: 07; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776744 12A || order number: 1924020 16A (HC)
+phoenix_contact connector MSTB_01x07_GF_5.00mm_MH
+0
+7
+7
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_8-GF-5,08_1x08_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/8-GF-5,08; number of pins: 08; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776566 12A || order number: 1924143 16A (HC)
+phoenix_contact connector MSTB_01x08_GF_5.08mm
+0
+8
+8
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_8-GF-5,08_1x08_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/8-GF-5,08; number of pins: 08; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776566 12A || order number: 1924143 16A (HC)
+phoenix_contact connector MSTB_01x08_GF_5.08mm_MH
+0
+8
+8
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_8-GF_1x08_P5.00mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/8-GF; number of pins: 08; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776757 12A || order number: 1924033 16A (HC)
+phoenix_contact connector MSTB_01x08_GF_5.00mm
+0
+8
+8
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_8-GF_1x08_P5.00mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/8-GF; number of pins: 08; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776757 12A || order number: 1924033 16A (HC)
+phoenix_contact connector MSTB_01x08_GF_5.00mm_MH
+0
+8
+8
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_9-GF-5,08_1x09_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/9-GF-5,08; number of pins: 09; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776579 12A || order number: 1924156 16A (HC)
+phoenix_contact connector MSTB_01x09_GF_5.08mm
+0
+9
+9
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_9-GF-5,08_1x09_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/9-GF-5,08; number of pins: 09; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776579 12A || order number: 1924156 16A (HC)
+phoenix_contact connector MSTB_01x09_GF_5.08mm_MH
+0
+9
+9
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_9-GF_1x09_P5.00mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/9-GF; number of pins: 09; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776760 12A || order number: 1924046 16A (HC)
+phoenix_contact connector MSTB_01x09_GF_5.00mm
+0
+9
+9
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_9-GF_1x09_P5.00mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/9-GF; number of pins: 09; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776760 12A || order number: 1924046 16A (HC)
+phoenix_contact connector MSTB_01x09_GF_5.00mm_MH
+0
+9
+9
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_10-GF-5,08_1x10_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/10-GF-5,08; number of pins: 10; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776582 12A || order number: 1924169 16A (HC)
+phoenix_contact connector MSTB_01x10_GF_5.08mm
+0
+10
+10
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_10-GF-5,08_1x10_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/10-GF-5,08; number of pins: 10; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776582 12A || order number: 1924169 16A (HC)
+phoenix_contact connector MSTB_01x10_GF_5.08mm_MH
+0
+10
+10
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_10-GF_1x10_P5.00mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/10-GF; number of pins: 10; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776773 12A || order number: 1924059 16A (HC)
+phoenix_contact connector MSTB_01x10_GF_5.00mm
+0
+10
+10
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_10-GF_1x10_P5.00mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/10-GF; number of pins: 10; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776773 12A || order number: 1924059 16A (HC)
+phoenix_contact connector MSTB_01x10_GF_5.00mm_MH
+0
+10
+10
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_11-GF-5,08_1x11_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/11-GF-5,08; number of pins: 11; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776595 12A || order number: 1924172 16A (HC)
+phoenix_contact connector MSTB_01x11_GF_5.08mm
+0
+11
+11
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_11-GF-5,08_1x11_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/11-GF-5,08; number of pins: 11; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776595 12A || order number: 1924172 16A (HC)
+phoenix_contact connector MSTB_01x11_GF_5.08mm_MH
+0
+11
+11
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_11-GF_1x11_P5.00mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/11-GF; number of pins: 11; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776786 12A || order number: 1924062 16A (HC)
+phoenix_contact connector MSTB_01x11_GF_5.00mm
+0
+11
+11
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_11-GF_1x11_P5.00mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/11-GF; number of pins: 11; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776786 12A || order number: 1924062 16A (HC)
+phoenix_contact connector MSTB_01x11_GF_5.00mm_MH
+0
+11
+11
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_12-GF-5,08_1x12_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/12-GF-5,08; number of pins: 12; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776605 12A || order number: 1924185 16A (HC)
+phoenix_contact connector MSTB_01x12_GF_5.08mm
+0
+12
+12
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_12-GF-5,08_1x12_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/12-GF-5,08; number of pins: 12; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776605 12A || order number: 1924185 16A (HC)
+phoenix_contact connector MSTB_01x12_GF_5.08mm_MH
+0
+12
+12
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_12-GF_1x12_P5.00mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/12-GF; number of pins: 12; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776799 12A || order number: 1924075 16A (HC)
+phoenix_contact connector MSTB_01x12_GF_5.00mm
+0
+12
+12
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_12-GF_1x12_P5.00mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/12-GF; number of pins: 12; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776799 12A || order number: 1924075 16A (HC)
+phoenix_contact connector MSTB_01x12_GF_5.00mm_MH
+0
+12
+12
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_13-GF-5,08_1x13_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/13-GF-5,08; number of pins: 13; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776618 12A
+phoenix_contact connector MSTB_01x13_GF_5.08mm
+0
+13
+13
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_13-GF-5,08_1x13_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/13-GF-5,08; number of pins: 13; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776618 12A
+phoenix_contact connector MSTB_01x13_GF_5.08mm_MH
+0
+13
+13
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_13-GF_1x13_P5.00mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/13-GF; number of pins: 13; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776809 12A
+phoenix_contact connector MSTB_01x13_GF_5.00mm
+0
+13
+13
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_13-GF_1x13_P5.00mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/13-GF; number of pins: 13; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776809 12A
+phoenix_contact connector MSTB_01x13_GF_5.00mm_MH
+0
+13
+13
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_14-GF-5,08_1x14_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/14-GF-5,08; number of pins: 14; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776621 12A
+phoenix_contact connector MSTB_01x14_GF_5.08mm
+0
+14
+14
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_14-GF-5,08_1x14_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/14-GF-5,08; number of pins: 14; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776621 12A
+phoenix_contact connector MSTB_01x14_GF_5.08mm_MH
+0
+14
+14
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_14-GF_1x14_P5.00mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/14-GF; number of pins: 14; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776812 12A
+phoenix_contact connector MSTB_01x14_GF_5.00mm
+0
+14
+14
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_14-GF_1x14_P5.00mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/14-GF; number of pins: 14; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776812 12A
+phoenix_contact connector MSTB_01x14_GF_5.00mm_MH
+0
+14
+14
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_15-GF-5,08_1x15_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/15-GF-5,08; number of pins: 15; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776634 12A
+phoenix_contact connector MSTB_01x15_GF_5.08mm
+0
+15
+15
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_15-GF-5,08_1x15_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/15-GF-5,08; number of pins: 15; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776634 12A
+phoenix_contact connector MSTB_01x15_GF_5.08mm_MH
+0
+15
+15
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_15-GF_1x15_P5.00mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/15-GF; number of pins: 15; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776825 12A
+phoenix_contact connector MSTB_01x15_GF_5.00mm
+0
+15
+15
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_15-GF_1x15_P5.00mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/15-GF; number of pins: 15; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776825 12A
+phoenix_contact connector MSTB_01x15_GF_5.00mm_MH
+0
+15
+15
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_16-GF-5,08_1x16_P5.08mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/16-GF-5,08; number of pins: 16; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776647 12A
+phoenix_contact connector MSTB_01x16_GF_5.08mm
+0
+16
+16
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_16-GF-5,08_1x16_P5.08mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/16-GF-5,08; number of pins: 16; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776647 12A
+phoenix_contact connector MSTB_01x16_GF_5.08mm_MH
+0
+16
+16
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_16-GF_1x16_P5.00mm_Horizontal_ThreadedFlange
+Generic Phoenix Contact connector footprint for: MSTB_2,5/16-GF; number of pins: 16; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776838 12A
+phoenix_contact connector MSTB_01x16_GF_5.00mm
+0
+16
+16
+Connector_Phoenix_MSTB
+PhoenixContact_MSTB_2,5_16-GF_1x16_P5.00mm_Horizontal_ThreadedFlange_MountHole
+Generic Phoenix Contact connector footprint for: MSTB_2,5/16-GF; number of pins: 16; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776838 12A
+phoenix_contact connector MSTB_01x16_GF_5.00mm_MH
+0
+16
+16
+Connector_Pin
+Pin_D0.7mm_L6.5mm_W1.8mm_FlatFork
+solder Pin_ with flat fork, hole diameter 0.7mm, length 6.5mm, width 1.8mm
+solder Pin_ with flat fork
+0
+1
+1
+Connector_Pin
+Pin_D0.9mm_L10.0mm_W2.4mm_FlatFork
+solder Pin_ with flat fork, hole diameter 0.9mm, length 10.0mm, width 2.4mm
+solder Pin_ with flat fork
+0
+1
+1
+Connector_Pin
+Pin_D1.0mm_L10.0mm
+solder Pin_ diameter 1.0mm, hole diameter 1.0mm (press fit), length 10.0mm
+solder Pin_ press fit
+0
+1
+1
+Connector_Pin
+Pin_D1.0mm_L10.0mm_LooseFit
+solder Pin_ diameter 1.0mm, hole diameter 1.2mm (loose fit), length 10.0mm
+solder Pin_ loose fit
+0
+1
+1
+Connector_Pin
+Pin_D1.1mm_L8.5mm_W2.5mm_FlatFork
+solder Pin_ with flat fork, hole diameter 1.1mm, length 8.5mm, width 2.5mm
+solder Pin_ with flat fork
+0
+1
+1
+Connector_Pin
+Pin_D1.1mm_L10.2mm_W3.5mm_Flat
+solder Pin_ with flat with hole, hole diameter 1.1mm, length 10.2mm, width 3.5mm
+solder Pin_ with flat fork
+0
+1
+1
+Connector_Pin
+Pin_D1.2mm_L10.2mm_W2.9mm_FlatFork
+solder Pin_ with flat with fork, hole diameter 1.2mm, length 11.3mm, width 3.0mm
+solder Pin_ with flat fork
+0
+1
+1
+Connector_Pin
+Pin_D1.2mm_L11.3mm_W3.0mm_Flat
+solder Pin_ with flat with hole, hole diameter 1.2mm, length 11.3mm, width 3.0mm
+solder Pin_ with flat fork
+0
+1
+1
+Connector_Pin
+Pin_D1.3mm_L10.0mm_W3.5mm_Flat
+solder Pin_ with flat with hole, hole diameter 1.3mm, length 10.0mm, width 3.5mm, e.g. Ettinger 13.13.865, https://katalog.ettinger.de/#p=434
+solder Pin_ with flat fork
+0
+1
+1
+Connector_Pin
+Pin_D1.3mm_L11.0mm
+solder Pin_ diameter 1.3mm, hole diameter 1.3mm, length 11.0mm
+solder Pin_ pressfit
+0
+1
+1
+Connector_Pin
+Pin_D1.3mm_L11.0mm_LooseFit
+solder Pin_ diameter 1.3mm, hole diameter 1.5mm (loose fit), length 11.0mm
+solder Pin_ loose fit
+0
+1
+1
+Connector_Pin
+Pin_D1.3mm_L11.3mm_W2.8mm_Flat
+solder Pin_ with flat with hole, hole diameter 1.3mm, length 11.3mm, width 2.8mm
+solder Pin_ with flat fork
+0
+1
+1
+Connector_Pin
+Pin_D1.4mm_L8.5mm_W2.8mm_FlatFork
+solder Pin_ with flat with fork, hole diameter 1.4mm, length 8.5mm, width 2.8mm, e.g. Ettinger 13.13.890, https://katalog.ettinger.de/#p=434
+solder Pin_ with flat fork
+0
+1
+1
+Connector_PinHeader_1.00mm
+PinHeader_1x01_P1.00mm_Horizontal
+Through hole angled pin header, 1x01, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x01 1.00mm single row
+0
+1
+1
+Connector_PinHeader_1.00mm
+PinHeader_1x01_P1.00mm_Vertical
+Through hole straight pin header, 1x01, 1.00mm pitch, single row
+Through hole pin header THT 1x01 1.00mm single row
+0
+1
+1
+Connector_PinHeader_1.00mm
+PinHeader_1x02_P1.00mm_Horizontal
+Through hole angled pin header, 1x02, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x02 1.00mm single row
+0
+2
+2
+Connector_PinHeader_1.00mm
+PinHeader_1x02_P1.00mm_Vertical
+Through hole straight pin header, 1x02, 1.00mm pitch, single row
+Through hole pin header THT 1x02 1.00mm single row
+0
+2
+2
+Connector_PinHeader_1.00mm
+PinHeader_1x02_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x02, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x02 1.00mm single row style1 pin1 left
+0
+2
+2
+Connector_PinHeader_1.00mm
+PinHeader_1x02_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x02, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x02 1.00mm single row style2 pin1 right
+0
+2
+2
+Connector_PinHeader_1.00mm
+PinHeader_1x03_P1.00mm_Horizontal
+Through hole angled pin header, 1x03, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x03 1.00mm single row
+0
+3
+3
+Connector_PinHeader_1.00mm
+PinHeader_1x03_P1.00mm_Vertical
+Through hole straight pin header, 1x03, 1.00mm pitch, single row
+Through hole pin header THT 1x03 1.00mm single row
+0
+3
+3
+Connector_PinHeader_1.00mm
+PinHeader_1x03_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x03, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x03 1.00mm single row style1 pin1 left
+0
+3
+3
+Connector_PinHeader_1.00mm
+PinHeader_1x03_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x03, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x03 1.00mm single row style2 pin1 right
+0
+3
+3
+Connector_PinHeader_1.00mm
+PinHeader_1x04_P1.00mm_Horizontal
+Through hole angled pin header, 1x04, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x04 1.00mm single row
+0
+4
+4
+Connector_PinHeader_1.00mm
+PinHeader_1x04_P1.00mm_Vertical
+Through hole straight pin header, 1x04, 1.00mm pitch, single row
+Through hole pin header THT 1x04 1.00mm single row
+0
+4
+4
+Connector_PinHeader_1.00mm
+PinHeader_1x04_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x04, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x04 1.00mm single row style1 pin1 left
+0
+4
+4
+Connector_PinHeader_1.00mm
+PinHeader_1x04_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x04, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x04 1.00mm single row style2 pin1 right
+0
+4
+4
+Connector_PinHeader_1.00mm
+PinHeader_1x05_P1.00mm_Horizontal
+Through hole angled pin header, 1x05, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x05 1.00mm single row
+0
+5
+5
+Connector_PinHeader_1.00mm
+PinHeader_1x05_P1.00mm_Vertical
+Through hole straight pin header, 1x05, 1.00mm pitch, single row
+Through hole pin header THT 1x05 1.00mm single row
+0
+5
+5
+Connector_PinHeader_1.00mm
+PinHeader_1x05_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x05, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x05 1.00mm single row style1 pin1 left
+0
+5
+5
+Connector_PinHeader_1.00mm
+PinHeader_1x05_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x05, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x05 1.00mm single row style2 pin1 right
+0
+5
+5
+Connector_PinHeader_1.00mm
+PinHeader_1x06_P1.00mm_Horizontal
+Through hole angled pin header, 1x06, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x06 1.00mm single row
+0
+6
+6
+Connector_PinHeader_1.00mm
+PinHeader_1x06_P1.00mm_Vertical
+Through hole straight pin header, 1x06, 1.00mm pitch, single row
+Through hole pin header THT 1x06 1.00mm single row
+0
+6
+6
+Connector_PinHeader_1.00mm
+PinHeader_1x06_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x06, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x06 1.00mm single row style1 pin1 left
+0
+6
+6
+Connector_PinHeader_1.00mm
+PinHeader_1x06_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x06, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x06 1.00mm single row style2 pin1 right
+0
+6
+6
+Connector_PinHeader_1.00mm
+PinHeader_1x07_P1.00mm_Horizontal
+Through hole angled pin header, 1x07, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x07 1.00mm single row
+0
+7
+7
+Connector_PinHeader_1.00mm
+PinHeader_1x07_P1.00mm_Vertical
+Through hole straight pin header, 1x07, 1.00mm pitch, single row
+Through hole pin header THT 1x07 1.00mm single row
+0
+7
+7
+Connector_PinHeader_1.00mm
+PinHeader_1x07_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x07, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x07 1.00mm single row style1 pin1 left
+0
+7
+7
+Connector_PinHeader_1.00mm
+PinHeader_1x07_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x07, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x07 1.00mm single row style2 pin1 right
+0
+7
+7
+Connector_PinHeader_1.00mm
+PinHeader_1x08_P1.00mm_Horizontal
+Through hole angled pin header, 1x08, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x08 1.00mm single row
+0
+8
+8
+Connector_PinHeader_1.00mm
+PinHeader_1x08_P1.00mm_Vertical
+Through hole straight pin header, 1x08, 1.00mm pitch, single row
+Through hole pin header THT 1x08 1.00mm single row
+0
+8
+8
+Connector_PinHeader_1.00mm
+PinHeader_1x08_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x08, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x08 1.00mm single row style1 pin1 left
+0
+8
+8
+Connector_PinHeader_1.00mm
+PinHeader_1x08_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x08, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x08 1.00mm single row style2 pin1 right
+0
+8
+8
+Connector_PinHeader_1.00mm
+PinHeader_1x09_P1.00mm_Horizontal
+Through hole angled pin header, 1x09, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x09 1.00mm single row
+0
+9
+9
+Connector_PinHeader_1.00mm
+PinHeader_1x09_P1.00mm_Vertical
+Through hole straight pin header, 1x09, 1.00mm pitch, single row
+Through hole pin header THT 1x09 1.00mm single row
+0
+9
+9
+Connector_PinHeader_1.00mm
+PinHeader_1x09_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x09, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x09 1.00mm single row style1 pin1 left
+0
+9
+9
+Connector_PinHeader_1.00mm
+PinHeader_1x09_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x09, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x09 1.00mm single row style2 pin1 right
+0
+9
+9
+Connector_PinHeader_1.00mm
+PinHeader_1x10_P1.00mm_Horizontal
+Through hole angled pin header, 1x10, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x10 1.00mm single row
+0
+10
+10
+Connector_PinHeader_1.00mm
+PinHeader_1x10_P1.00mm_Vertical
+Through hole straight pin header, 1x10, 1.00mm pitch, single row
+Through hole pin header THT 1x10 1.00mm single row
+0
+10
+10
+Connector_PinHeader_1.00mm
+PinHeader_1x10_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x10, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x10 1.00mm single row style1 pin1 left
+0
+10
+10
+Connector_PinHeader_1.00mm
+PinHeader_1x10_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x10, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x10 1.00mm single row style2 pin1 right
+0
+10
+10
+Connector_PinHeader_1.00mm
+PinHeader_1x11_P1.00mm_Horizontal
+Through hole angled pin header, 1x11, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x11 1.00mm single row
+0
+11
+11
+Connector_PinHeader_1.00mm
+PinHeader_1x11_P1.00mm_Vertical
+Through hole straight pin header, 1x11, 1.00mm pitch, single row
+Through hole pin header THT 1x11 1.00mm single row
+0
+11
+11
+Connector_PinHeader_1.00mm
+PinHeader_1x11_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x11, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x11 1.00mm single row style1 pin1 left
+0
+11
+11
+Connector_PinHeader_1.00mm
+PinHeader_1x11_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x11, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x11 1.00mm single row style2 pin1 right
+0
+11
+11
+Connector_PinHeader_1.00mm
+PinHeader_1x12_P1.00mm_Horizontal
+Through hole angled pin header, 1x12, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x12 1.00mm single row
+0
+12
+12
+Connector_PinHeader_1.00mm
+PinHeader_1x12_P1.00mm_Vertical
+Through hole straight pin header, 1x12, 1.00mm pitch, single row
+Through hole pin header THT 1x12 1.00mm single row
+0
+12
+12
+Connector_PinHeader_1.00mm
+PinHeader_1x12_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x12, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x12 1.00mm single row style1 pin1 left
+0
+12
+12
+Connector_PinHeader_1.00mm
+PinHeader_1x12_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x12, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x12 1.00mm single row style2 pin1 right
+0
+12
+12
+Connector_PinHeader_1.00mm
+PinHeader_1x13_P1.00mm_Horizontal
+Through hole angled pin header, 1x13, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x13 1.00mm single row
+0
+13
+13
+Connector_PinHeader_1.00mm
+PinHeader_1x13_P1.00mm_Vertical
+Through hole straight pin header, 1x13, 1.00mm pitch, single row
+Through hole pin header THT 1x13 1.00mm single row
+0
+13
+13
+Connector_PinHeader_1.00mm
+PinHeader_1x13_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x13, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x13 1.00mm single row style1 pin1 left
+0
+13
+13
+Connector_PinHeader_1.00mm
+PinHeader_1x13_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x13, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x13 1.00mm single row style2 pin1 right
+0
+13
+13
+Connector_PinHeader_1.00mm
+PinHeader_1x14_P1.00mm_Horizontal
+Through hole angled pin header, 1x14, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x14 1.00mm single row
+0
+14
+14
+Connector_PinHeader_1.00mm
+PinHeader_1x14_P1.00mm_Vertical
+Through hole straight pin header, 1x14, 1.00mm pitch, single row
+Through hole pin header THT 1x14 1.00mm single row
+0
+14
+14
+Connector_PinHeader_1.00mm
+PinHeader_1x14_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x14, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x14 1.00mm single row style1 pin1 left
+0
+14
+14
+Connector_PinHeader_1.00mm
+PinHeader_1x14_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x14, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x14 1.00mm single row style2 pin1 right
+0
+14
+14
+Connector_PinHeader_1.00mm
+PinHeader_1x15_P1.00mm_Horizontal
+Through hole angled pin header, 1x15, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x15 1.00mm single row
+0
+15
+15
+Connector_PinHeader_1.00mm
+PinHeader_1x15_P1.00mm_Vertical
+Through hole straight pin header, 1x15, 1.00mm pitch, single row
+Through hole pin header THT 1x15 1.00mm single row
+0
+15
+15
+Connector_PinHeader_1.00mm
+PinHeader_1x15_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x15, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x15 1.00mm single row style1 pin1 left
+0
+15
+15
+Connector_PinHeader_1.00mm
+PinHeader_1x15_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x15, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x15 1.00mm single row style2 pin1 right
+0
+15
+15
+Connector_PinHeader_1.00mm
+PinHeader_1x16_P1.00mm_Horizontal
+Through hole angled pin header, 1x16, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x16 1.00mm single row
+0
+16
+16
+Connector_PinHeader_1.00mm
+PinHeader_1x16_P1.00mm_Vertical
+Through hole straight pin header, 1x16, 1.00mm pitch, single row
+Through hole pin header THT 1x16 1.00mm single row
+0
+16
+16
+Connector_PinHeader_1.00mm
+PinHeader_1x16_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x16, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x16 1.00mm single row style1 pin1 left
+0
+16
+16
+Connector_PinHeader_1.00mm
+PinHeader_1x16_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x16, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x16 1.00mm single row style2 pin1 right
+0
+16
+16
+Connector_PinHeader_1.00mm
+PinHeader_1x17_P1.00mm_Horizontal
+Through hole angled pin header, 1x17, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x17 1.00mm single row
+0
+17
+17
+Connector_PinHeader_1.00mm
+PinHeader_1x17_P1.00mm_Vertical
+Through hole straight pin header, 1x17, 1.00mm pitch, single row
+Through hole pin header THT 1x17 1.00mm single row
+0
+17
+17
+Connector_PinHeader_1.00mm
+PinHeader_1x17_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x17, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x17 1.00mm single row style1 pin1 left
+0
+17
+17
+Connector_PinHeader_1.00mm
+PinHeader_1x17_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x17, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x17 1.00mm single row style2 pin1 right
+0
+17
+17
+Connector_PinHeader_1.00mm
+PinHeader_1x18_P1.00mm_Horizontal
+Through hole angled pin header, 1x18, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x18 1.00mm single row
+0
+18
+18
+Connector_PinHeader_1.00mm
+PinHeader_1x18_P1.00mm_Vertical
+Through hole straight pin header, 1x18, 1.00mm pitch, single row
+Through hole pin header THT 1x18 1.00mm single row
+0
+18
+18
+Connector_PinHeader_1.00mm
+PinHeader_1x18_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x18, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x18 1.00mm single row style1 pin1 left
+0
+18
+18
+Connector_PinHeader_1.00mm
+PinHeader_1x18_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x18, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x18 1.00mm single row style2 pin1 right
+0
+18
+18
+Connector_PinHeader_1.00mm
+PinHeader_1x19_P1.00mm_Horizontal
+Through hole angled pin header, 1x19, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x19 1.00mm single row
+0
+19
+19
+Connector_PinHeader_1.00mm
+PinHeader_1x19_P1.00mm_Vertical
+Through hole straight pin header, 1x19, 1.00mm pitch, single row
+Through hole pin header THT 1x19 1.00mm single row
+0
+19
+19
+Connector_PinHeader_1.00mm
+PinHeader_1x19_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x19, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x19 1.00mm single row style1 pin1 left
+0
+19
+19
+Connector_PinHeader_1.00mm
+PinHeader_1x19_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x19, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x19 1.00mm single row style2 pin1 right
+0
+19
+19
+Connector_PinHeader_1.00mm
+PinHeader_1x20_P1.00mm_Horizontal
+Through hole angled pin header, 1x20, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x20 1.00mm single row
+0
+20
+20
+Connector_PinHeader_1.00mm
+PinHeader_1x20_P1.00mm_Vertical
+Through hole straight pin header, 1x20, 1.00mm pitch, single row
+Through hole pin header THT 1x20 1.00mm single row
+0
+20
+20
+Connector_PinHeader_1.00mm
+PinHeader_1x20_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x20, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x20 1.00mm single row style1 pin1 left
+0
+20
+20
+Connector_PinHeader_1.00mm
+PinHeader_1x20_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x20, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x20 1.00mm single row style2 pin1 right
+0
+20
+20
+Connector_PinHeader_1.00mm
+PinHeader_1x21_P1.00mm_Horizontal
+Through hole angled pin header, 1x21, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x21 1.00mm single row
+0
+21
+21
+Connector_PinHeader_1.00mm
+PinHeader_1x21_P1.00mm_Vertical
+Through hole straight pin header, 1x21, 1.00mm pitch, single row
+Through hole pin header THT 1x21 1.00mm single row
+0
+21
+21
+Connector_PinHeader_1.00mm
+PinHeader_1x21_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x21, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x21 1.00mm single row style1 pin1 left
+0
+21
+21
+Connector_PinHeader_1.00mm
+PinHeader_1x21_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x21, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x21 1.00mm single row style2 pin1 right
+0
+21
+21
+Connector_PinHeader_1.00mm
+PinHeader_1x22_P1.00mm_Horizontal
+Through hole angled pin header, 1x22, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x22 1.00mm single row
+0
+22
+22
+Connector_PinHeader_1.00mm
+PinHeader_1x22_P1.00mm_Vertical
+Through hole straight pin header, 1x22, 1.00mm pitch, single row
+Through hole pin header THT 1x22 1.00mm single row
+0
+22
+22
+Connector_PinHeader_1.00mm
+PinHeader_1x22_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x22, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x22 1.00mm single row style1 pin1 left
+0
+22
+22
+Connector_PinHeader_1.00mm
+PinHeader_1x22_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x22, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x22 1.00mm single row style2 pin1 right
+0
+22
+22
+Connector_PinHeader_1.00mm
+PinHeader_1x23_P1.00mm_Horizontal
+Through hole angled pin header, 1x23, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x23 1.00mm single row
+0
+23
+23
+Connector_PinHeader_1.00mm
+PinHeader_1x23_P1.00mm_Vertical
+Through hole straight pin header, 1x23, 1.00mm pitch, single row
+Through hole pin header THT 1x23 1.00mm single row
+0
+23
+23
+Connector_PinHeader_1.00mm
+PinHeader_1x23_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x23, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x23 1.00mm single row style1 pin1 left
+0
+23
+23
+Connector_PinHeader_1.00mm
+PinHeader_1x23_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x23, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x23 1.00mm single row style2 pin1 right
+0
+23
+23
+Connector_PinHeader_1.00mm
+PinHeader_1x24_P1.00mm_Horizontal
+Through hole angled pin header, 1x24, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x24 1.00mm single row
+0
+24
+24
+Connector_PinHeader_1.00mm
+PinHeader_1x24_P1.00mm_Vertical
+Through hole straight pin header, 1x24, 1.00mm pitch, single row
+Through hole pin header THT 1x24 1.00mm single row
+0
+24
+24
+Connector_PinHeader_1.00mm
+PinHeader_1x24_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x24, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x24 1.00mm single row style1 pin1 left
+0
+24
+24
+Connector_PinHeader_1.00mm
+PinHeader_1x24_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x24, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x24 1.00mm single row style2 pin1 right
+0
+24
+24
+Connector_PinHeader_1.00mm
+PinHeader_1x25_P1.00mm_Horizontal
+Through hole angled pin header, 1x25, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x25 1.00mm single row
+0
+25
+25
+Connector_PinHeader_1.00mm
+PinHeader_1x25_P1.00mm_Vertical
+Through hole straight pin header, 1x25, 1.00mm pitch, single row
+Through hole pin header THT 1x25 1.00mm single row
+0
+25
+25
+Connector_PinHeader_1.00mm
+PinHeader_1x25_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x25, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x25 1.00mm single row style1 pin1 left
+0
+25
+25
+Connector_PinHeader_1.00mm
+PinHeader_1x25_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x25, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x25 1.00mm single row style2 pin1 right
+0
+25
+25
+Connector_PinHeader_1.00mm
+PinHeader_1x26_P1.00mm_Horizontal
+Through hole angled pin header, 1x26, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x26 1.00mm single row
+0
+26
+26
+Connector_PinHeader_1.00mm
+PinHeader_1x26_P1.00mm_Vertical
+Through hole straight pin header, 1x26, 1.00mm pitch, single row
+Through hole pin header THT 1x26 1.00mm single row
+0
+26
+26
+Connector_PinHeader_1.00mm
+PinHeader_1x26_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x26, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x26 1.00mm single row style1 pin1 left
+0
+26
+26
+Connector_PinHeader_1.00mm
+PinHeader_1x26_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x26, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x26 1.00mm single row style2 pin1 right
+0
+26
+26
+Connector_PinHeader_1.00mm
+PinHeader_1x27_P1.00mm_Horizontal
+Through hole angled pin header, 1x27, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x27 1.00mm single row
+0
+27
+27
+Connector_PinHeader_1.00mm
+PinHeader_1x27_P1.00mm_Vertical
+Through hole straight pin header, 1x27, 1.00mm pitch, single row
+Through hole pin header THT 1x27 1.00mm single row
+0
+27
+27
+Connector_PinHeader_1.00mm
+PinHeader_1x27_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x27, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x27 1.00mm single row style1 pin1 left
+0
+27
+27
+Connector_PinHeader_1.00mm
+PinHeader_1x27_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x27, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x27 1.00mm single row style2 pin1 right
+0
+27
+27
+Connector_PinHeader_1.00mm
+PinHeader_1x28_P1.00mm_Horizontal
+Through hole angled pin header, 1x28, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x28 1.00mm single row
+0
+28
+28
+Connector_PinHeader_1.00mm
+PinHeader_1x28_P1.00mm_Vertical
+Through hole straight pin header, 1x28, 1.00mm pitch, single row
+Through hole pin header THT 1x28 1.00mm single row
+0
+28
+28
+Connector_PinHeader_1.00mm
+PinHeader_1x28_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x28, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x28 1.00mm single row style1 pin1 left
+0
+28
+28
+Connector_PinHeader_1.00mm
+PinHeader_1x28_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x28, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x28 1.00mm single row style2 pin1 right
+0
+28
+28
+Connector_PinHeader_1.00mm
+PinHeader_1x29_P1.00mm_Horizontal
+Through hole angled pin header, 1x29, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x29 1.00mm single row
+0
+29
+29
+Connector_PinHeader_1.00mm
+PinHeader_1x29_P1.00mm_Vertical
+Through hole straight pin header, 1x29, 1.00mm pitch, single row
+Through hole pin header THT 1x29 1.00mm single row
+0
+29
+29
+Connector_PinHeader_1.00mm
+PinHeader_1x29_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x29, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x29 1.00mm single row style1 pin1 left
+0
+29
+29
+Connector_PinHeader_1.00mm
+PinHeader_1x29_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x29, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x29 1.00mm single row style2 pin1 right
+0
+29
+29
+Connector_PinHeader_1.00mm
+PinHeader_1x30_P1.00mm_Horizontal
+Through hole angled pin header, 1x30, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x30 1.00mm single row
+0
+30
+30
+Connector_PinHeader_1.00mm
+PinHeader_1x30_P1.00mm_Vertical
+Through hole straight pin header, 1x30, 1.00mm pitch, single row
+Through hole pin header THT 1x30 1.00mm single row
+0
+30
+30
+Connector_PinHeader_1.00mm
+PinHeader_1x30_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x30, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x30 1.00mm single row style1 pin1 left
+0
+30
+30
+Connector_PinHeader_1.00mm
+PinHeader_1x30_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x30, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x30 1.00mm single row style2 pin1 right
+0
+30
+30
+Connector_PinHeader_1.00mm
+PinHeader_1x31_P1.00mm_Horizontal
+Through hole angled pin header, 1x31, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x31 1.00mm single row
+0
+31
+31
+Connector_PinHeader_1.00mm
+PinHeader_1x31_P1.00mm_Vertical
+Through hole straight pin header, 1x31, 1.00mm pitch, single row
+Through hole pin header THT 1x31 1.00mm single row
+0
+31
+31
+Connector_PinHeader_1.00mm
+PinHeader_1x31_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x31, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x31 1.00mm single row style1 pin1 left
+0
+31
+31
+Connector_PinHeader_1.00mm
+PinHeader_1x31_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x31, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x31 1.00mm single row style2 pin1 right
+0
+31
+31
+Connector_PinHeader_1.00mm
+PinHeader_1x32_P1.00mm_Horizontal
+Through hole angled pin header, 1x32, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x32 1.00mm single row
+0
+32
+32
+Connector_PinHeader_1.00mm
+PinHeader_1x32_P1.00mm_Vertical
+Through hole straight pin header, 1x32, 1.00mm pitch, single row
+Through hole pin header THT 1x32 1.00mm single row
+0
+32
+32
+Connector_PinHeader_1.00mm
+PinHeader_1x32_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x32, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x32 1.00mm single row style1 pin1 left
+0
+32
+32
+Connector_PinHeader_1.00mm
+PinHeader_1x32_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x32, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x32 1.00mm single row style2 pin1 right
+0
+32
+32
+Connector_PinHeader_1.00mm
+PinHeader_1x33_P1.00mm_Horizontal
+Through hole angled pin header, 1x33, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x33 1.00mm single row
+0
+33
+33
+Connector_PinHeader_1.00mm
+PinHeader_1x33_P1.00mm_Vertical
+Through hole straight pin header, 1x33, 1.00mm pitch, single row
+Through hole pin header THT 1x33 1.00mm single row
+0
+33
+33
+Connector_PinHeader_1.00mm
+PinHeader_1x33_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x33, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x33 1.00mm single row style1 pin1 left
+0
+33
+33
+Connector_PinHeader_1.00mm
+PinHeader_1x33_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x33, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x33 1.00mm single row style2 pin1 right
+0
+33
+33
+Connector_PinHeader_1.00mm
+PinHeader_1x34_P1.00mm_Horizontal
+Through hole angled pin header, 1x34, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x34 1.00mm single row
+0
+34
+34
+Connector_PinHeader_1.00mm
+PinHeader_1x34_P1.00mm_Vertical
+Through hole straight pin header, 1x34, 1.00mm pitch, single row
+Through hole pin header THT 1x34 1.00mm single row
+0
+34
+34
+Connector_PinHeader_1.00mm
+PinHeader_1x34_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x34, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x34 1.00mm single row style1 pin1 left
+0
+34
+34
+Connector_PinHeader_1.00mm
+PinHeader_1x34_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x34, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x34 1.00mm single row style2 pin1 right
+0
+34
+34
+Connector_PinHeader_1.00mm
+PinHeader_1x35_P1.00mm_Horizontal
+Through hole angled pin header, 1x35, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x35 1.00mm single row
+0
+35
+35
+Connector_PinHeader_1.00mm
+PinHeader_1x35_P1.00mm_Vertical
+Through hole straight pin header, 1x35, 1.00mm pitch, single row
+Through hole pin header THT 1x35 1.00mm single row
+0
+35
+35
+Connector_PinHeader_1.00mm
+PinHeader_1x35_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x35, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x35 1.00mm single row style1 pin1 left
+0
+35
+35
+Connector_PinHeader_1.00mm
+PinHeader_1x35_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x35, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x35 1.00mm single row style2 pin1 right
+0
+35
+35
+Connector_PinHeader_1.00mm
+PinHeader_1x36_P1.00mm_Horizontal
+Through hole angled pin header, 1x36, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x36 1.00mm single row
+0
+36
+36
+Connector_PinHeader_1.00mm
+PinHeader_1x36_P1.00mm_Vertical
+Through hole straight pin header, 1x36, 1.00mm pitch, single row
+Through hole pin header THT 1x36 1.00mm single row
+0
+36
+36
+Connector_PinHeader_1.00mm
+PinHeader_1x36_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x36, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x36 1.00mm single row style1 pin1 left
+0
+36
+36
+Connector_PinHeader_1.00mm
+PinHeader_1x36_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x36, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x36 1.00mm single row style2 pin1 right
+0
+36
+36
+Connector_PinHeader_1.00mm
+PinHeader_1x37_P1.00mm_Horizontal
+Through hole angled pin header, 1x37, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x37 1.00mm single row
+0
+37
+37
+Connector_PinHeader_1.00mm
+PinHeader_1x37_P1.00mm_Vertical
+Through hole straight pin header, 1x37, 1.00mm pitch, single row
+Through hole pin header THT 1x37 1.00mm single row
+0
+37
+37
+Connector_PinHeader_1.00mm
+PinHeader_1x37_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x37, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x37 1.00mm single row style1 pin1 left
+0
+37
+37
+Connector_PinHeader_1.00mm
+PinHeader_1x37_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x37, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x37 1.00mm single row style2 pin1 right
+0
+37
+37
+Connector_PinHeader_1.00mm
+PinHeader_1x38_P1.00mm_Horizontal
+Through hole angled pin header, 1x38, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x38 1.00mm single row
+0
+38
+38
+Connector_PinHeader_1.00mm
+PinHeader_1x38_P1.00mm_Vertical
+Through hole straight pin header, 1x38, 1.00mm pitch, single row
+Through hole pin header THT 1x38 1.00mm single row
+0
+38
+38
+Connector_PinHeader_1.00mm
+PinHeader_1x38_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x38, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x38 1.00mm single row style1 pin1 left
+0
+38
+38
+Connector_PinHeader_1.00mm
+PinHeader_1x38_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x38, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x38 1.00mm single row style2 pin1 right
+0
+38
+38
+Connector_PinHeader_1.00mm
+PinHeader_1x39_P1.00mm_Horizontal
+Through hole angled pin header, 1x39, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x39 1.00mm single row
+0
+39
+39
+Connector_PinHeader_1.00mm
+PinHeader_1x39_P1.00mm_Vertical
+Through hole straight pin header, 1x39, 1.00mm pitch, single row
+Through hole pin header THT 1x39 1.00mm single row
+0
+39
+39
+Connector_PinHeader_1.00mm
+PinHeader_1x39_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x39, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x39 1.00mm single row style1 pin1 left
+0
+39
+39
+Connector_PinHeader_1.00mm
+PinHeader_1x39_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x39, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x39 1.00mm single row style2 pin1 right
+0
+39
+39
+Connector_PinHeader_1.00mm
+PinHeader_1x40_P1.00mm_Horizontal
+Through hole angled pin header, 1x40, 1.00mm pitch, 2.0mm pin length, single row
+Through hole angled pin header THT 1x40 1.00mm single row
+0
+40
+40
+Connector_PinHeader_1.00mm
+PinHeader_1x40_P1.00mm_Vertical
+Through hole straight pin header, 1x40, 1.00mm pitch, single row
+Through hole pin header THT 1x40 1.00mm single row
+0
+40
+40
+Connector_PinHeader_1.00mm
+PinHeader_1x40_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x40, 1.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x40 1.00mm single row style1 pin1 left
+0
+40
+40
+Connector_PinHeader_1.00mm
+PinHeader_1x40_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x40, 1.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x40 1.00mm single row style2 pin1 right
+0
+40
+40
+Connector_PinHeader_1.00mm
+PinHeader_2x01_P1.00mm_Horizontal
+Through hole angled pin header, 2x01, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x01 1.00mm double row
+0
+2
+2
+Connector_PinHeader_1.00mm
+PinHeader_2x01_P1.00mm_Vertical
+Through hole straight pin header, 2x01, 1.00mm pitch, double rows
+Through hole pin header THT 2x01 1.00mm double row
+0
+2
+2
+Connector_PinHeader_1.00mm
+PinHeader_2x01_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x01, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x01 1.00mm double row
+0
+2
+2
+Connector_PinHeader_1.00mm
+PinHeader_2x02_P1.00mm_Horizontal
+Through hole angled pin header, 2x02, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x02 1.00mm double row
+0
+4
+4
+Connector_PinHeader_1.00mm
+PinHeader_2x02_P1.00mm_Vertical
+Through hole straight pin header, 2x02, 1.00mm pitch, double rows
+Through hole pin header THT 2x02 1.00mm double row
+0
+4
+4
+Connector_PinHeader_1.00mm
+PinHeader_2x02_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x02, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x02 1.00mm double row
+0
+4
+4
+Connector_PinHeader_1.00mm
+PinHeader_2x03_P1.00mm_Horizontal
+Through hole angled pin header, 2x03, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x03 1.00mm double row
+0
+6
+6
+Connector_PinHeader_1.00mm
+PinHeader_2x03_P1.00mm_Vertical
+Through hole straight pin header, 2x03, 1.00mm pitch, double rows
+Through hole pin header THT 2x03 1.00mm double row
+0
+6
+6
+Connector_PinHeader_1.00mm
+PinHeader_2x03_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x03, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x03 1.00mm double row
+0
+6
+6
+Connector_PinHeader_1.00mm
+PinHeader_2x04_P1.00mm_Horizontal
+Through hole angled pin header, 2x04, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x04 1.00mm double row
+0
+8
+8
+Connector_PinHeader_1.00mm
+PinHeader_2x04_P1.00mm_Vertical
+Through hole straight pin header, 2x04, 1.00mm pitch, double rows
+Through hole pin header THT 2x04 1.00mm double row
+0
+8
+8
+Connector_PinHeader_1.00mm
+PinHeader_2x04_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x04, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x04 1.00mm double row
+0
+8
+8
+Connector_PinHeader_1.00mm
+PinHeader_2x05_P1.00mm_Horizontal
+Through hole angled pin header, 2x05, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x05 1.00mm double row
+0
+10
+10
+Connector_PinHeader_1.00mm
+PinHeader_2x05_P1.00mm_Vertical
+Through hole straight pin header, 2x05, 1.00mm pitch, double rows
+Through hole pin header THT 2x05 1.00mm double row
+0
+10
+10
+Connector_PinHeader_1.00mm
+PinHeader_2x05_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x05, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x05 1.00mm double row
+0
+10
+10
+Connector_PinHeader_1.00mm
+PinHeader_2x06_P1.00mm_Horizontal
+Through hole angled pin header, 2x06, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x06 1.00mm double row
+0
+12
+12
+Connector_PinHeader_1.00mm
+PinHeader_2x06_P1.00mm_Vertical
+Through hole straight pin header, 2x06, 1.00mm pitch, double rows
+Through hole pin header THT 2x06 1.00mm double row
+0
+12
+12
+Connector_PinHeader_1.00mm
+PinHeader_2x06_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x06, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x06 1.00mm double row
+0
+12
+12
+Connector_PinHeader_1.00mm
+PinHeader_2x07_P1.00mm_Horizontal
+Through hole angled pin header, 2x07, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x07 1.00mm double row
+0
+14
+14
+Connector_PinHeader_1.00mm
+PinHeader_2x07_P1.00mm_Vertical
+Through hole straight pin header, 2x07, 1.00mm pitch, double rows
+Through hole pin header THT 2x07 1.00mm double row
+0
+14
+14
+Connector_PinHeader_1.00mm
+PinHeader_2x07_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x07, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x07 1.00mm double row
+0
+14
+14
+Connector_PinHeader_1.00mm
+PinHeader_2x08_P1.00mm_Horizontal
+Through hole angled pin header, 2x08, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x08 1.00mm double row
+0
+16
+16
+Connector_PinHeader_1.00mm
+PinHeader_2x08_P1.00mm_Vertical
+Through hole straight pin header, 2x08, 1.00mm pitch, double rows
+Through hole pin header THT 2x08 1.00mm double row
+0
+16
+16
+Connector_PinHeader_1.00mm
+PinHeader_2x08_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x08, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x08 1.00mm double row
+0
+16
+16
+Connector_PinHeader_1.00mm
+PinHeader_2x09_P1.00mm_Horizontal
+Through hole angled pin header, 2x09, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x09 1.00mm double row
+0
+18
+18
+Connector_PinHeader_1.00mm
+PinHeader_2x09_P1.00mm_Vertical
+Through hole straight pin header, 2x09, 1.00mm pitch, double rows
+Through hole pin header THT 2x09 1.00mm double row
+0
+18
+18
+Connector_PinHeader_1.00mm
+PinHeader_2x09_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x09, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x09 1.00mm double row
+0
+18
+18
+Connector_PinHeader_1.00mm
+PinHeader_2x10_P1.00mm_Horizontal
+Through hole angled pin header, 2x10, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x10 1.00mm double row
+0
+20
+20
+Connector_PinHeader_1.00mm
+PinHeader_2x10_P1.00mm_Vertical
+Through hole straight pin header, 2x10, 1.00mm pitch, double rows
+Through hole pin header THT 2x10 1.00mm double row
+0
+20
+20
+Connector_PinHeader_1.00mm
+PinHeader_2x10_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x10, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x10 1.00mm double row
+0
+20
+20
+Connector_PinHeader_1.00mm
+PinHeader_2x11_P1.00mm_Horizontal
+Through hole angled pin header, 2x11, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x11 1.00mm double row
+0
+22
+22
+Connector_PinHeader_1.00mm
+PinHeader_2x11_P1.00mm_Vertical
+Through hole straight pin header, 2x11, 1.00mm pitch, double rows
+Through hole pin header THT 2x11 1.00mm double row
+0
+22
+22
+Connector_PinHeader_1.00mm
+PinHeader_2x11_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x11, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x11 1.00mm double row
+0
+22
+22
+Connector_PinHeader_1.00mm
+PinHeader_2x12_P1.00mm_Horizontal
+Through hole angled pin header, 2x12, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x12 1.00mm double row
+0
+24
+24
+Connector_PinHeader_1.00mm
+PinHeader_2x12_P1.00mm_Vertical
+Through hole straight pin header, 2x12, 1.00mm pitch, double rows
+Through hole pin header THT 2x12 1.00mm double row
+0
+24
+24
+Connector_PinHeader_1.00mm
+PinHeader_2x12_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x12, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x12 1.00mm double row
+0
+24
+24
+Connector_PinHeader_1.00mm
+PinHeader_2x13_P1.00mm_Horizontal
+Through hole angled pin header, 2x13, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x13 1.00mm double row
+0
+26
+26
+Connector_PinHeader_1.00mm
+PinHeader_2x13_P1.00mm_Vertical
+Through hole straight pin header, 2x13, 1.00mm pitch, double rows
+Through hole pin header THT 2x13 1.00mm double row
+0
+26
+26
+Connector_PinHeader_1.00mm
+PinHeader_2x13_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x13, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x13 1.00mm double row
+0
+26
+26
+Connector_PinHeader_1.00mm
+PinHeader_2x14_P1.00mm_Horizontal
+Through hole angled pin header, 2x14, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x14 1.00mm double row
+0
+28
+28
+Connector_PinHeader_1.00mm
+PinHeader_2x14_P1.00mm_Vertical
+Through hole straight pin header, 2x14, 1.00mm pitch, double rows
+Through hole pin header THT 2x14 1.00mm double row
+0
+28
+28
+Connector_PinHeader_1.00mm
+PinHeader_2x14_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x14, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x14 1.00mm double row
+0
+28
+28
+Connector_PinHeader_1.00mm
+PinHeader_2x15_P1.00mm_Horizontal
+Through hole angled pin header, 2x15, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x15 1.00mm double row
+0
+30
+30
+Connector_PinHeader_1.00mm
+PinHeader_2x15_P1.00mm_Vertical
+Through hole straight pin header, 2x15, 1.00mm pitch, double rows
+Through hole pin header THT 2x15 1.00mm double row
+0
+30
+30
+Connector_PinHeader_1.00mm
+PinHeader_2x15_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x15, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x15 1.00mm double row
+0
+30
+30
+Connector_PinHeader_1.00mm
+PinHeader_2x16_P1.00mm_Horizontal
+Through hole angled pin header, 2x16, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x16 1.00mm double row
+0
+32
+32
+Connector_PinHeader_1.00mm
+PinHeader_2x16_P1.00mm_Vertical
+Through hole straight pin header, 2x16, 1.00mm pitch, double rows
+Through hole pin header THT 2x16 1.00mm double row
+0
+32
+32
+Connector_PinHeader_1.00mm
+PinHeader_2x16_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x16, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x16 1.00mm double row
+0
+32
+32
+Connector_PinHeader_1.00mm
+PinHeader_2x17_P1.00mm_Horizontal
+Through hole angled pin header, 2x17, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x17 1.00mm double row
+0
+34
+34
+Connector_PinHeader_1.00mm
+PinHeader_2x17_P1.00mm_Vertical
+Through hole straight pin header, 2x17, 1.00mm pitch, double rows
+Through hole pin header THT 2x17 1.00mm double row
+0
+34
+34
+Connector_PinHeader_1.00mm
+PinHeader_2x17_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x17, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x17 1.00mm double row
+0
+34
+34
+Connector_PinHeader_1.00mm
+PinHeader_2x18_P1.00mm_Horizontal
+Through hole angled pin header, 2x18, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x18 1.00mm double row
+0
+36
+36
+Connector_PinHeader_1.00mm
+PinHeader_2x18_P1.00mm_Vertical
+Through hole straight pin header, 2x18, 1.00mm pitch, double rows
+Through hole pin header THT 2x18 1.00mm double row
+0
+36
+36
+Connector_PinHeader_1.00mm
+PinHeader_2x18_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x18, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x18 1.00mm double row
+0
+36
+36
+Connector_PinHeader_1.00mm
+PinHeader_2x19_P1.00mm_Horizontal
+Through hole angled pin header, 2x19, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x19 1.00mm double row
+0
+38
+38
+Connector_PinHeader_1.00mm
+PinHeader_2x19_P1.00mm_Vertical
+Through hole straight pin header, 2x19, 1.00mm pitch, double rows
+Through hole pin header THT 2x19 1.00mm double row
+0
+38
+38
+Connector_PinHeader_1.00mm
+PinHeader_2x19_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x19, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x19 1.00mm double row
+0
+38
+38
+Connector_PinHeader_1.00mm
+PinHeader_2x20_P1.00mm_Horizontal
+Through hole angled pin header, 2x20, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x20 1.00mm double row
+0
+40
+40
+Connector_PinHeader_1.00mm
+PinHeader_2x20_P1.00mm_Vertical
+Through hole straight pin header, 2x20, 1.00mm pitch, double rows
+Through hole pin header THT 2x20 1.00mm double row
+0
+40
+40
+Connector_PinHeader_1.00mm
+PinHeader_2x20_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x20, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x20 1.00mm double row
+0
+40
+40
+Connector_PinHeader_1.00mm
+PinHeader_2x21_P1.00mm_Horizontal
+Through hole angled pin header, 2x21, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x21 1.00mm double row
+0
+42
+42
+Connector_PinHeader_1.00mm
+PinHeader_2x21_P1.00mm_Vertical
+Through hole straight pin header, 2x21, 1.00mm pitch, double rows
+Through hole pin header THT 2x21 1.00mm double row
+0
+42
+42
+Connector_PinHeader_1.00mm
+PinHeader_2x21_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x21, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x21 1.00mm double row
+0
+42
+42
+Connector_PinHeader_1.00mm
+PinHeader_2x22_P1.00mm_Horizontal
+Through hole angled pin header, 2x22, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x22 1.00mm double row
+0
+44
+44
+Connector_PinHeader_1.00mm
+PinHeader_2x22_P1.00mm_Vertical
+Through hole straight pin header, 2x22, 1.00mm pitch, double rows
+Through hole pin header THT 2x22 1.00mm double row
+0
+44
+44
+Connector_PinHeader_1.00mm
+PinHeader_2x22_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x22, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x22 1.00mm double row
+0
+44
+44
+Connector_PinHeader_1.00mm
+PinHeader_2x23_P1.00mm_Horizontal
+Through hole angled pin header, 2x23, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x23 1.00mm double row
+0
+46
+46
+Connector_PinHeader_1.00mm
+PinHeader_2x23_P1.00mm_Vertical
+Through hole straight pin header, 2x23, 1.00mm pitch, double rows
+Through hole pin header THT 2x23 1.00mm double row
+0
+46
+46
+Connector_PinHeader_1.00mm
+PinHeader_2x23_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x23, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x23 1.00mm double row
+0
+46
+46
+Connector_PinHeader_1.00mm
+PinHeader_2x24_P1.00mm_Horizontal
+Through hole angled pin header, 2x24, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x24 1.00mm double row
+0
+48
+48
+Connector_PinHeader_1.00mm
+PinHeader_2x24_P1.00mm_Vertical
+Through hole straight pin header, 2x24, 1.00mm pitch, double rows
+Through hole pin header THT 2x24 1.00mm double row
+0
+48
+48
+Connector_PinHeader_1.00mm
+PinHeader_2x24_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x24, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x24 1.00mm double row
+0
+48
+48
+Connector_PinHeader_1.00mm
+PinHeader_2x25_P1.00mm_Horizontal
+Through hole angled pin header, 2x25, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x25 1.00mm double row
+0
+50
+50
+Connector_PinHeader_1.00mm
+PinHeader_2x25_P1.00mm_Vertical
+Through hole straight pin header, 2x25, 1.00mm pitch, double rows
+Through hole pin header THT 2x25 1.00mm double row
+0
+50
+50
+Connector_PinHeader_1.00mm
+PinHeader_2x25_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x25, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x25 1.00mm double row
+0
+50
+50
+Connector_PinHeader_1.00mm
+PinHeader_2x26_P1.00mm_Horizontal
+Through hole angled pin header, 2x26, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x26 1.00mm double row
+0
+52
+52
+Connector_PinHeader_1.00mm
+PinHeader_2x26_P1.00mm_Vertical
+Through hole straight pin header, 2x26, 1.00mm pitch, double rows
+Through hole pin header THT 2x26 1.00mm double row
+0
+52
+52
+Connector_PinHeader_1.00mm
+PinHeader_2x26_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x26, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x26 1.00mm double row
+0
+52
+52
+Connector_PinHeader_1.00mm
+PinHeader_2x27_P1.00mm_Horizontal
+Through hole angled pin header, 2x27, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x27 1.00mm double row
+0
+54
+54
+Connector_PinHeader_1.00mm
+PinHeader_2x27_P1.00mm_Vertical
+Through hole straight pin header, 2x27, 1.00mm pitch, double rows
+Through hole pin header THT 2x27 1.00mm double row
+0
+54
+54
+Connector_PinHeader_1.00mm
+PinHeader_2x27_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x27, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x27 1.00mm double row
+0
+54
+54
+Connector_PinHeader_1.00mm
+PinHeader_2x28_P1.00mm_Horizontal
+Through hole angled pin header, 2x28, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x28 1.00mm double row
+0
+56
+56
+Connector_PinHeader_1.00mm
+PinHeader_2x28_P1.00mm_Vertical
+Through hole straight pin header, 2x28, 1.00mm pitch, double rows
+Through hole pin header THT 2x28 1.00mm double row
+0
+56
+56
+Connector_PinHeader_1.00mm
+PinHeader_2x28_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x28, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x28 1.00mm double row
+0
+56
+56
+Connector_PinHeader_1.00mm
+PinHeader_2x29_P1.00mm_Horizontal
+Through hole angled pin header, 2x29, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x29 1.00mm double row
+0
+58
+58
+Connector_PinHeader_1.00mm
+PinHeader_2x29_P1.00mm_Vertical
+Through hole straight pin header, 2x29, 1.00mm pitch, double rows
+Through hole pin header THT 2x29 1.00mm double row
+0
+58
+58
+Connector_PinHeader_1.00mm
+PinHeader_2x29_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x29, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x29 1.00mm double row
+0
+58
+58
+Connector_PinHeader_1.00mm
+PinHeader_2x30_P1.00mm_Horizontal
+Through hole angled pin header, 2x30, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x30 1.00mm double row
+0
+60
+60
+Connector_PinHeader_1.00mm
+PinHeader_2x30_P1.00mm_Vertical
+Through hole straight pin header, 2x30, 1.00mm pitch, double rows
+Through hole pin header THT 2x30 1.00mm double row
+0
+60
+60
+Connector_PinHeader_1.00mm
+PinHeader_2x30_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x30, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x30 1.00mm double row
+0
+60
+60
+Connector_PinHeader_1.00mm
+PinHeader_2x31_P1.00mm_Horizontal
+Through hole angled pin header, 2x31, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x31 1.00mm double row
+0
+62
+62
+Connector_PinHeader_1.00mm
+PinHeader_2x31_P1.00mm_Vertical
+Through hole straight pin header, 2x31, 1.00mm pitch, double rows
+Through hole pin header THT 2x31 1.00mm double row
+0
+62
+62
+Connector_PinHeader_1.00mm
+PinHeader_2x31_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x31, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x31 1.00mm double row
+0
+62
+62
+Connector_PinHeader_1.00mm
+PinHeader_2x32_P1.00mm_Horizontal
+Through hole angled pin header, 2x32, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x32 1.00mm double row
+0
+64
+64
+Connector_PinHeader_1.00mm
+PinHeader_2x32_P1.00mm_Vertical
+Through hole straight pin header, 2x32, 1.00mm pitch, double rows
+Through hole pin header THT 2x32 1.00mm double row
+0
+64
+64
+Connector_PinHeader_1.00mm
+PinHeader_2x32_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x32, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x32 1.00mm double row
+0
+64
+64
+Connector_PinHeader_1.00mm
+PinHeader_2x33_P1.00mm_Horizontal
+Through hole angled pin header, 2x33, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x33 1.00mm double row
+0
+66
+66
+Connector_PinHeader_1.00mm
+PinHeader_2x33_P1.00mm_Vertical
+Through hole straight pin header, 2x33, 1.00mm pitch, double rows
+Through hole pin header THT 2x33 1.00mm double row
+0
+66
+66
+Connector_PinHeader_1.00mm
+PinHeader_2x33_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x33, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x33 1.00mm double row
+0
+66
+66
+Connector_PinHeader_1.00mm
+PinHeader_2x34_P1.00mm_Horizontal
+Through hole angled pin header, 2x34, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x34 1.00mm double row
+0
+68
+68
+Connector_PinHeader_1.00mm
+PinHeader_2x34_P1.00mm_Vertical
+Through hole straight pin header, 2x34, 1.00mm pitch, double rows
+Through hole pin header THT 2x34 1.00mm double row
+0
+68
+68
+Connector_PinHeader_1.00mm
+PinHeader_2x34_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x34, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x34 1.00mm double row
+0
+68
+68
+Connector_PinHeader_1.00mm
+PinHeader_2x35_P1.00mm_Horizontal
+Through hole angled pin header, 2x35, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x35 1.00mm double row
+0
+70
+70
+Connector_PinHeader_1.00mm
+PinHeader_2x35_P1.00mm_Vertical
+Through hole straight pin header, 2x35, 1.00mm pitch, double rows
+Through hole pin header THT 2x35 1.00mm double row
+0
+70
+70
+Connector_PinHeader_1.00mm
+PinHeader_2x35_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x35, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x35 1.00mm double row
+0
+70
+70
+Connector_PinHeader_1.00mm
+PinHeader_2x36_P1.00mm_Horizontal
+Through hole angled pin header, 2x36, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x36 1.00mm double row
+0
+72
+72
+Connector_PinHeader_1.00mm
+PinHeader_2x36_P1.00mm_Vertical
+Through hole straight pin header, 2x36, 1.00mm pitch, double rows
+Through hole pin header THT 2x36 1.00mm double row
+0
+72
+72
+Connector_PinHeader_1.00mm
+PinHeader_2x36_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x36, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x36 1.00mm double row
+0
+72
+72
+Connector_PinHeader_1.00mm
+PinHeader_2x37_P1.00mm_Horizontal
+Through hole angled pin header, 2x37, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x37 1.00mm double row
+0
+74
+74
+Connector_PinHeader_1.00mm
+PinHeader_2x37_P1.00mm_Vertical
+Through hole straight pin header, 2x37, 1.00mm pitch, double rows
+Through hole pin header THT 2x37 1.00mm double row
+0
+74
+74
+Connector_PinHeader_1.00mm
+PinHeader_2x37_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x37, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x37 1.00mm double row
+0
+74
+74
+Connector_PinHeader_1.00mm
+PinHeader_2x38_P1.00mm_Horizontal
+Through hole angled pin header, 2x38, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x38 1.00mm double row
+0
+76
+76
+Connector_PinHeader_1.00mm
+PinHeader_2x38_P1.00mm_Vertical
+Through hole straight pin header, 2x38, 1.00mm pitch, double rows
+Through hole pin header THT 2x38 1.00mm double row
+0
+76
+76
+Connector_PinHeader_1.00mm
+PinHeader_2x38_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x38, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x38 1.00mm double row
+0
+76
+76
+Connector_PinHeader_1.00mm
+PinHeader_2x39_P1.00mm_Horizontal
+Through hole angled pin header, 2x39, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x39 1.00mm double row
+0
+78
+78
+Connector_PinHeader_1.00mm
+PinHeader_2x39_P1.00mm_Vertical
+Through hole straight pin header, 2x39, 1.00mm pitch, double rows
+Through hole pin header THT 2x39 1.00mm double row
+0
+78
+78
+Connector_PinHeader_1.00mm
+PinHeader_2x39_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x39, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x39 1.00mm double row
+0
+78
+78
+Connector_PinHeader_1.00mm
+PinHeader_2x40_P1.00mm_Horizontal
+Through hole angled pin header, 2x40, 1.00mm pitch, 2.0mm pin length, double rows
+Through hole angled pin header THT 2x40 1.00mm double row
+0
+80
+80
+Connector_PinHeader_1.00mm
+PinHeader_2x40_P1.00mm_Vertical
+Through hole straight pin header, 2x40, 1.00mm pitch, double rows
+Through hole pin header THT 2x40 1.00mm double row
+0
+80
+80
+Connector_PinHeader_1.00mm
+PinHeader_2x40_P1.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x40, 1.00mm pitch, double rows
+Surface mounted pin header SMD 2x40 1.00mm double row
+0
+80
+80
+Connector_PinHeader_1.27mm
+PinHeader_1x01_P1.27mm_Horizontal
+Through hole angled pin header, 1x01, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x01 1.27mm single row
+0
+1
+1
+Connector_PinHeader_1.27mm
+PinHeader_1x01_P1.27mm_Vertical
+Through hole straight pin header, 1x01, 1.27mm pitch, single row
+Through hole pin header THT 1x01 1.27mm single row
+0
+1
+1
+Connector_PinHeader_1.27mm
+PinHeader_1x02_P1.27mm_Horizontal
+Through hole angled pin header, 1x02, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x02 1.27mm single row
+0
+2
+2
+Connector_PinHeader_1.27mm
+PinHeader_1x02_P1.27mm_Vertical
+Through hole straight pin header, 1x02, 1.27mm pitch, single row
+Through hole pin header THT 1x02 1.27mm single row
+0
+2
+2
+Connector_PinHeader_1.27mm
+PinHeader_1x02_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x02, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x02 1.27mm single row style1 pin1 left
+0
+2
+2
+Connector_PinHeader_1.27mm
+PinHeader_1x02_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x02, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x02 1.27mm single row style2 pin1 right
+0
+2
+2
+Connector_PinHeader_1.27mm
+PinHeader_1x03_P1.27mm_Horizontal
+Through hole angled pin header, 1x03, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x03 1.27mm single row
+0
+3
+3
+Connector_PinHeader_1.27mm
+PinHeader_1x03_P1.27mm_Vertical
+Through hole straight pin header, 1x03, 1.27mm pitch, single row
+Through hole pin header THT 1x03 1.27mm single row
+0
+3
+3
+Connector_PinHeader_1.27mm
+PinHeader_1x03_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x03, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x03 1.27mm single row style1 pin1 left
+0
+3
+3
+Connector_PinHeader_1.27mm
+PinHeader_1x03_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x03, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x03 1.27mm single row style2 pin1 right
+0
+3
+3
+Connector_PinHeader_1.27mm
+PinHeader_1x04_P1.27mm_Horizontal
+Through hole angled pin header, 1x04, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x04 1.27mm single row
+0
+4
+4
+Connector_PinHeader_1.27mm
+PinHeader_1x04_P1.27mm_Vertical
+Through hole straight pin header, 1x04, 1.27mm pitch, single row
+Through hole pin header THT 1x04 1.27mm single row
+0
+4
+4
+Connector_PinHeader_1.27mm
+PinHeader_1x04_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x04, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x04 1.27mm single row style1 pin1 left
+0
+4
+4
+Connector_PinHeader_1.27mm
+PinHeader_1x04_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x04, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x04 1.27mm single row style2 pin1 right
+0
+4
+4
+Connector_PinHeader_1.27mm
+PinHeader_1x05_P1.27mm_Horizontal
+Through hole angled pin header, 1x05, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x05 1.27mm single row
+0
+5
+5
+Connector_PinHeader_1.27mm
+PinHeader_1x05_P1.27mm_Vertical
+Through hole straight pin header, 1x05, 1.27mm pitch, single row
+Through hole pin header THT 1x05 1.27mm single row
+0
+5
+5
+Connector_PinHeader_1.27mm
+PinHeader_1x05_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x05, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x05 1.27mm single row style1 pin1 left
+0
+5
+5
+Connector_PinHeader_1.27mm
+PinHeader_1x05_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x05, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x05 1.27mm single row style2 pin1 right
+0
+5
+5
+Connector_PinHeader_1.27mm
+PinHeader_1x06_P1.27mm_Horizontal
+Through hole angled pin header, 1x06, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x06 1.27mm single row
+0
+6
+6
+Connector_PinHeader_1.27mm
+PinHeader_1x06_P1.27mm_Vertical
+Through hole straight pin header, 1x06, 1.27mm pitch, single row
+Through hole pin header THT 1x06 1.27mm single row
+0
+6
+6
+Connector_PinHeader_1.27mm
+PinHeader_1x06_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x06, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x06 1.27mm single row style1 pin1 left
+0
+6
+6
+Connector_PinHeader_1.27mm
+PinHeader_1x06_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x06, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x06 1.27mm single row style2 pin1 right
+0
+6
+6
+Connector_PinHeader_1.27mm
+PinHeader_1x07_P1.27mm_Horizontal
+Through hole angled pin header, 1x07, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x07 1.27mm single row
+0
+7
+7
+Connector_PinHeader_1.27mm
+PinHeader_1x07_P1.27mm_Vertical
+Through hole straight pin header, 1x07, 1.27mm pitch, single row
+Through hole pin header THT 1x07 1.27mm single row
+0
+7
+7
+Connector_PinHeader_1.27mm
+PinHeader_1x07_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x07, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x07 1.27mm single row style1 pin1 left
+0
+7
+7
+Connector_PinHeader_1.27mm
+PinHeader_1x07_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x07, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x07 1.27mm single row style2 pin1 right
+0
+7
+7
+Connector_PinHeader_1.27mm
+PinHeader_1x08_P1.27mm_Horizontal
+Through hole angled pin header, 1x08, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x08 1.27mm single row
+0
+8
+8
+Connector_PinHeader_1.27mm
+PinHeader_1x08_P1.27mm_Vertical
+Through hole straight pin header, 1x08, 1.27mm pitch, single row
+Through hole pin header THT 1x08 1.27mm single row
+0
+8
+8
+Connector_PinHeader_1.27mm
+PinHeader_1x08_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x08, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x08 1.27mm single row style1 pin1 left
+0
+8
+8
+Connector_PinHeader_1.27mm
+PinHeader_1x08_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x08, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x08 1.27mm single row style2 pin1 right
+0
+8
+8
+Connector_PinHeader_1.27mm
+PinHeader_1x09_P1.27mm_Horizontal
+Through hole angled pin header, 1x09, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x09 1.27mm single row
+0
+9
+9
+Connector_PinHeader_1.27mm
+PinHeader_1x09_P1.27mm_Vertical
+Through hole straight pin header, 1x09, 1.27mm pitch, single row
+Through hole pin header THT 1x09 1.27mm single row
+0
+9
+9
+Connector_PinHeader_1.27mm
+PinHeader_1x09_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x09, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x09 1.27mm single row style1 pin1 left
+0
+9
+9
+Connector_PinHeader_1.27mm
+PinHeader_1x09_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x09, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x09 1.27mm single row style2 pin1 right
+0
+9
+9
+Connector_PinHeader_1.27mm
+PinHeader_1x10_P1.27mm_Horizontal
+Through hole angled pin header, 1x10, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x10 1.27mm single row
+0
+10
+10
+Connector_PinHeader_1.27mm
+PinHeader_1x10_P1.27mm_Vertical
+Through hole straight pin header, 1x10, 1.27mm pitch, single row
+Through hole pin header THT 1x10 1.27mm single row
+0
+10
+10
+Connector_PinHeader_1.27mm
+PinHeader_1x10_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x10, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x10 1.27mm single row style1 pin1 left
+0
+10
+10
+Connector_PinHeader_1.27mm
+PinHeader_1x10_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x10, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x10 1.27mm single row style2 pin1 right
+0
+10
+10
+Connector_PinHeader_1.27mm
+PinHeader_1x11_P1.27mm_Horizontal
+Through hole angled pin header, 1x11, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x11 1.27mm single row
+0
+11
+11
+Connector_PinHeader_1.27mm
+PinHeader_1x11_P1.27mm_Vertical
+Through hole straight pin header, 1x11, 1.27mm pitch, single row
+Through hole pin header THT 1x11 1.27mm single row
+0
+11
+11
+Connector_PinHeader_1.27mm
+PinHeader_1x11_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x11, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x11 1.27mm single row style1 pin1 left
+0
+11
+11
+Connector_PinHeader_1.27mm
+PinHeader_1x11_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x11, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x11 1.27mm single row style2 pin1 right
+0
+11
+11
+Connector_PinHeader_1.27mm
+PinHeader_1x12_P1.27mm_Horizontal
+Through hole angled pin header, 1x12, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x12 1.27mm single row
+0
+12
+12
+Connector_PinHeader_1.27mm
+PinHeader_1x12_P1.27mm_Vertical
+Through hole straight pin header, 1x12, 1.27mm pitch, single row
+Through hole pin header THT 1x12 1.27mm single row
+0
+12
+12
+Connector_PinHeader_1.27mm
+PinHeader_1x12_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x12, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x12 1.27mm single row style1 pin1 left
+0
+12
+12
+Connector_PinHeader_1.27mm
+PinHeader_1x12_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x12, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x12 1.27mm single row style2 pin1 right
+0
+12
+12
+Connector_PinHeader_1.27mm
+PinHeader_1x13_P1.27mm_Horizontal
+Through hole angled pin header, 1x13, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x13 1.27mm single row
+0
+13
+13
+Connector_PinHeader_1.27mm
+PinHeader_1x13_P1.27mm_Vertical
+Through hole straight pin header, 1x13, 1.27mm pitch, single row
+Through hole pin header THT 1x13 1.27mm single row
+0
+13
+13
+Connector_PinHeader_1.27mm
+PinHeader_1x13_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x13, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x13 1.27mm single row style1 pin1 left
+0
+13
+13
+Connector_PinHeader_1.27mm
+PinHeader_1x13_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x13, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x13 1.27mm single row style2 pin1 right
+0
+13
+13
+Connector_PinHeader_1.27mm
+PinHeader_1x14_P1.27mm_Horizontal
+Through hole angled pin header, 1x14, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x14 1.27mm single row
+0
+14
+14
+Connector_PinHeader_1.27mm
+PinHeader_1x14_P1.27mm_Vertical
+Through hole straight pin header, 1x14, 1.27mm pitch, single row
+Through hole pin header THT 1x14 1.27mm single row
+0
+14
+14
+Connector_PinHeader_1.27mm
+PinHeader_1x14_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x14, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x14 1.27mm single row style1 pin1 left
+0
+14
+14
+Connector_PinHeader_1.27mm
+PinHeader_1x14_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x14, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x14 1.27mm single row style2 pin1 right
+0
+14
+14
+Connector_PinHeader_1.27mm
+PinHeader_1x15_P1.27mm_Horizontal
+Through hole angled pin header, 1x15, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x15 1.27mm single row
+0
+15
+15
+Connector_PinHeader_1.27mm
+PinHeader_1x15_P1.27mm_Vertical
+Through hole straight pin header, 1x15, 1.27mm pitch, single row
+Through hole pin header THT 1x15 1.27mm single row
+0
+15
+15
+Connector_PinHeader_1.27mm
+PinHeader_1x15_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x15, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x15 1.27mm single row style1 pin1 left
+0
+15
+15
+Connector_PinHeader_1.27mm
+PinHeader_1x15_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x15, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x15 1.27mm single row style2 pin1 right
+0
+15
+15
+Connector_PinHeader_1.27mm
+PinHeader_1x16_P1.27mm_Horizontal
+Through hole angled pin header, 1x16, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x16 1.27mm single row
+0
+16
+16
+Connector_PinHeader_1.27mm
+PinHeader_1x16_P1.27mm_Vertical
+Through hole straight pin header, 1x16, 1.27mm pitch, single row
+Through hole pin header THT 1x16 1.27mm single row
+0
+16
+16
+Connector_PinHeader_1.27mm
+PinHeader_1x16_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x16, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x16 1.27mm single row style1 pin1 left
+0
+16
+16
+Connector_PinHeader_1.27mm
+PinHeader_1x16_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x16, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x16 1.27mm single row style2 pin1 right
+0
+16
+16
+Connector_PinHeader_1.27mm
+PinHeader_1x17_P1.27mm_Horizontal
+Through hole angled pin header, 1x17, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x17 1.27mm single row
+0
+17
+17
+Connector_PinHeader_1.27mm
+PinHeader_1x17_P1.27mm_Vertical
+Through hole straight pin header, 1x17, 1.27mm pitch, single row
+Through hole pin header THT 1x17 1.27mm single row
+0
+17
+17
+Connector_PinHeader_1.27mm
+PinHeader_1x17_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x17, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x17 1.27mm single row style1 pin1 left
+0
+17
+17
+Connector_PinHeader_1.27mm
+PinHeader_1x17_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x17, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x17 1.27mm single row style2 pin1 right
+0
+17
+17
+Connector_PinHeader_1.27mm
+PinHeader_1x18_P1.27mm_Horizontal
+Through hole angled pin header, 1x18, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x18 1.27mm single row
+0
+18
+18
+Connector_PinHeader_1.27mm
+PinHeader_1x18_P1.27mm_Vertical
+Through hole straight pin header, 1x18, 1.27mm pitch, single row
+Through hole pin header THT 1x18 1.27mm single row
+0
+18
+18
+Connector_PinHeader_1.27mm
+PinHeader_1x18_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x18, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x18 1.27mm single row style1 pin1 left
+0
+18
+18
+Connector_PinHeader_1.27mm
+PinHeader_1x18_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x18, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x18 1.27mm single row style2 pin1 right
+0
+18
+18
+Connector_PinHeader_1.27mm
+PinHeader_1x19_P1.27mm_Horizontal
+Through hole angled pin header, 1x19, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x19 1.27mm single row
+0
+19
+19
+Connector_PinHeader_1.27mm
+PinHeader_1x19_P1.27mm_Vertical
+Through hole straight pin header, 1x19, 1.27mm pitch, single row
+Through hole pin header THT 1x19 1.27mm single row
+0
+19
+19
+Connector_PinHeader_1.27mm
+PinHeader_1x19_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x19, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x19 1.27mm single row style1 pin1 left
+0
+19
+19
+Connector_PinHeader_1.27mm
+PinHeader_1x19_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x19, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x19 1.27mm single row style2 pin1 right
+0
+19
+19
+Connector_PinHeader_1.27mm
+PinHeader_1x20_P1.27mm_Horizontal
+Through hole angled pin header, 1x20, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x20 1.27mm single row
+0
+20
+20
+Connector_PinHeader_1.27mm
+PinHeader_1x20_P1.27mm_Vertical
+Through hole straight pin header, 1x20, 1.27mm pitch, single row
+Through hole pin header THT 1x20 1.27mm single row
+0
+20
+20
+Connector_PinHeader_1.27mm
+PinHeader_1x20_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x20, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x20 1.27mm single row style1 pin1 left
+0
+20
+20
+Connector_PinHeader_1.27mm
+PinHeader_1x20_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x20, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x20 1.27mm single row style2 pin1 right
+0
+20
+20
+Connector_PinHeader_1.27mm
+PinHeader_1x21_P1.27mm_Horizontal
+Through hole angled pin header, 1x21, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x21 1.27mm single row
+0
+21
+21
+Connector_PinHeader_1.27mm
+PinHeader_1x21_P1.27mm_Vertical
+Through hole straight pin header, 1x21, 1.27mm pitch, single row
+Through hole pin header THT 1x21 1.27mm single row
+0
+21
+21
+Connector_PinHeader_1.27mm
+PinHeader_1x21_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x21, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x21 1.27mm single row style1 pin1 left
+0
+21
+21
+Connector_PinHeader_1.27mm
+PinHeader_1x21_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x21, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x21 1.27mm single row style2 pin1 right
+0
+21
+21
+Connector_PinHeader_1.27mm
+PinHeader_1x22_P1.27mm_Horizontal
+Through hole angled pin header, 1x22, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x22 1.27mm single row
+0
+22
+22
+Connector_PinHeader_1.27mm
+PinHeader_1x22_P1.27mm_Vertical
+Through hole straight pin header, 1x22, 1.27mm pitch, single row
+Through hole pin header THT 1x22 1.27mm single row
+0
+22
+22
+Connector_PinHeader_1.27mm
+PinHeader_1x22_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x22, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x22 1.27mm single row style1 pin1 left
+0
+22
+22
+Connector_PinHeader_1.27mm
+PinHeader_1x22_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x22, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x22 1.27mm single row style2 pin1 right
+0
+22
+22
+Connector_PinHeader_1.27mm
+PinHeader_1x23_P1.27mm_Horizontal
+Through hole angled pin header, 1x23, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x23 1.27mm single row
+0
+23
+23
+Connector_PinHeader_1.27mm
+PinHeader_1x23_P1.27mm_Vertical
+Through hole straight pin header, 1x23, 1.27mm pitch, single row
+Through hole pin header THT 1x23 1.27mm single row
+0
+23
+23
+Connector_PinHeader_1.27mm
+PinHeader_1x23_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x23, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x23 1.27mm single row style1 pin1 left
+0
+23
+23
+Connector_PinHeader_1.27mm
+PinHeader_1x23_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x23, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x23 1.27mm single row style2 pin1 right
+0
+23
+23
+Connector_PinHeader_1.27mm
+PinHeader_1x24_P1.27mm_Horizontal
+Through hole angled pin header, 1x24, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x24 1.27mm single row
+0
+24
+24
+Connector_PinHeader_1.27mm
+PinHeader_1x24_P1.27mm_Vertical
+Through hole straight pin header, 1x24, 1.27mm pitch, single row
+Through hole pin header THT 1x24 1.27mm single row
+0
+24
+24
+Connector_PinHeader_1.27mm
+PinHeader_1x24_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x24, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x24 1.27mm single row style1 pin1 left
+0
+24
+24
+Connector_PinHeader_1.27mm
+PinHeader_1x24_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x24, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x24 1.27mm single row style2 pin1 right
+0
+24
+24
+Connector_PinHeader_1.27mm
+PinHeader_1x25_P1.27mm_Horizontal
+Through hole angled pin header, 1x25, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x25 1.27mm single row
+0
+25
+25
+Connector_PinHeader_1.27mm
+PinHeader_1x25_P1.27mm_Vertical
+Through hole straight pin header, 1x25, 1.27mm pitch, single row
+Through hole pin header THT 1x25 1.27mm single row
+0
+25
+25
+Connector_PinHeader_1.27mm
+PinHeader_1x25_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x25, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x25 1.27mm single row style1 pin1 left
+0
+25
+25
+Connector_PinHeader_1.27mm
+PinHeader_1x25_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x25, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x25 1.27mm single row style2 pin1 right
+0
+25
+25
+Connector_PinHeader_1.27mm
+PinHeader_1x26_P1.27mm_Horizontal
+Through hole angled pin header, 1x26, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x26 1.27mm single row
+0
+26
+26
+Connector_PinHeader_1.27mm
+PinHeader_1x26_P1.27mm_Vertical
+Through hole straight pin header, 1x26, 1.27mm pitch, single row
+Through hole pin header THT 1x26 1.27mm single row
+0
+26
+26
+Connector_PinHeader_1.27mm
+PinHeader_1x26_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x26, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x26 1.27mm single row style1 pin1 left
+0
+26
+26
+Connector_PinHeader_1.27mm
+PinHeader_1x26_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x26, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x26 1.27mm single row style2 pin1 right
+0
+26
+26
+Connector_PinHeader_1.27mm
+PinHeader_1x27_P1.27mm_Horizontal
+Through hole angled pin header, 1x27, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x27 1.27mm single row
+0
+27
+27
+Connector_PinHeader_1.27mm
+PinHeader_1x27_P1.27mm_Vertical
+Through hole straight pin header, 1x27, 1.27mm pitch, single row
+Through hole pin header THT 1x27 1.27mm single row
+0
+27
+27
+Connector_PinHeader_1.27mm
+PinHeader_1x27_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x27, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x27 1.27mm single row style1 pin1 left
+0
+27
+27
+Connector_PinHeader_1.27mm
+PinHeader_1x27_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x27, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x27 1.27mm single row style2 pin1 right
+0
+27
+27
+Connector_PinHeader_1.27mm
+PinHeader_1x28_P1.27mm_Horizontal
+Through hole angled pin header, 1x28, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x28 1.27mm single row
+0
+28
+28
+Connector_PinHeader_1.27mm
+PinHeader_1x28_P1.27mm_Vertical
+Through hole straight pin header, 1x28, 1.27mm pitch, single row
+Through hole pin header THT 1x28 1.27mm single row
+0
+28
+28
+Connector_PinHeader_1.27mm
+PinHeader_1x28_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x28, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x28 1.27mm single row style1 pin1 left
+0
+28
+28
+Connector_PinHeader_1.27mm
+PinHeader_1x28_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x28, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x28 1.27mm single row style2 pin1 right
+0
+28
+28
+Connector_PinHeader_1.27mm
+PinHeader_1x29_P1.27mm_Horizontal
+Through hole angled pin header, 1x29, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x29 1.27mm single row
+0
+29
+29
+Connector_PinHeader_1.27mm
+PinHeader_1x29_P1.27mm_Vertical
+Through hole straight pin header, 1x29, 1.27mm pitch, single row
+Through hole pin header THT 1x29 1.27mm single row
+0
+29
+29
+Connector_PinHeader_1.27mm
+PinHeader_1x29_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x29, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x29 1.27mm single row style1 pin1 left
+0
+29
+29
+Connector_PinHeader_1.27mm
+PinHeader_1x29_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x29, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x29 1.27mm single row style2 pin1 right
+0
+29
+29
+Connector_PinHeader_1.27mm
+PinHeader_1x30_P1.27mm_Horizontal
+Through hole angled pin header, 1x30, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x30 1.27mm single row
+0
+30
+30
+Connector_PinHeader_1.27mm
+PinHeader_1x30_P1.27mm_Vertical
+Through hole straight pin header, 1x30, 1.27mm pitch, single row
+Through hole pin header THT 1x30 1.27mm single row
+0
+30
+30
+Connector_PinHeader_1.27mm
+PinHeader_1x30_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x30, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x30 1.27mm single row style1 pin1 left
+0
+30
+30
+Connector_PinHeader_1.27mm
+PinHeader_1x30_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x30, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x30 1.27mm single row style2 pin1 right
+0
+30
+30
+Connector_PinHeader_1.27mm
+PinHeader_1x31_P1.27mm_Horizontal
+Through hole angled pin header, 1x31, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x31 1.27mm single row
+0
+31
+31
+Connector_PinHeader_1.27mm
+PinHeader_1x31_P1.27mm_Vertical
+Through hole straight pin header, 1x31, 1.27mm pitch, single row
+Through hole pin header THT 1x31 1.27mm single row
+0
+31
+31
+Connector_PinHeader_1.27mm
+PinHeader_1x31_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x31, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x31 1.27mm single row style1 pin1 left
+0
+31
+31
+Connector_PinHeader_1.27mm
+PinHeader_1x31_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x31, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x31 1.27mm single row style2 pin1 right
+0
+31
+31
+Connector_PinHeader_1.27mm
+PinHeader_1x32_P1.27mm_Horizontal
+Through hole angled pin header, 1x32, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x32 1.27mm single row
+0
+32
+32
+Connector_PinHeader_1.27mm
+PinHeader_1x32_P1.27mm_Vertical
+Through hole straight pin header, 1x32, 1.27mm pitch, single row
+Through hole pin header THT 1x32 1.27mm single row
+0
+32
+32
+Connector_PinHeader_1.27mm
+PinHeader_1x32_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x32, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x32 1.27mm single row style1 pin1 left
+0
+32
+32
+Connector_PinHeader_1.27mm
+PinHeader_1x32_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x32, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x32 1.27mm single row style2 pin1 right
+0
+32
+32
+Connector_PinHeader_1.27mm
+PinHeader_1x33_P1.27mm_Horizontal
+Through hole angled pin header, 1x33, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x33 1.27mm single row
+0
+33
+33
+Connector_PinHeader_1.27mm
+PinHeader_1x33_P1.27mm_Vertical
+Through hole straight pin header, 1x33, 1.27mm pitch, single row
+Through hole pin header THT 1x33 1.27mm single row
+0
+33
+33
+Connector_PinHeader_1.27mm
+PinHeader_1x33_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x33, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x33 1.27mm single row style1 pin1 left
+0
+33
+33
+Connector_PinHeader_1.27mm
+PinHeader_1x33_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x33, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x33 1.27mm single row style2 pin1 right
+0
+33
+33
+Connector_PinHeader_1.27mm
+PinHeader_1x34_P1.27mm_Horizontal
+Through hole angled pin header, 1x34, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x34 1.27mm single row
+0
+34
+34
+Connector_PinHeader_1.27mm
+PinHeader_1x34_P1.27mm_Vertical
+Through hole straight pin header, 1x34, 1.27mm pitch, single row
+Through hole pin header THT 1x34 1.27mm single row
+0
+34
+34
+Connector_PinHeader_1.27mm
+PinHeader_1x34_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x34, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x34 1.27mm single row style1 pin1 left
+0
+34
+34
+Connector_PinHeader_1.27mm
+PinHeader_1x34_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x34, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x34 1.27mm single row style2 pin1 right
+0
+34
+34
+Connector_PinHeader_1.27mm
+PinHeader_1x35_P1.27mm_Horizontal
+Through hole angled pin header, 1x35, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x35 1.27mm single row
+0
+35
+35
+Connector_PinHeader_1.27mm
+PinHeader_1x35_P1.27mm_Vertical
+Through hole straight pin header, 1x35, 1.27mm pitch, single row
+Through hole pin header THT 1x35 1.27mm single row
+0
+35
+35
+Connector_PinHeader_1.27mm
+PinHeader_1x35_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x35, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x35 1.27mm single row style1 pin1 left
+0
+35
+35
+Connector_PinHeader_1.27mm
+PinHeader_1x35_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x35, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x35 1.27mm single row style2 pin1 right
+0
+35
+35
+Connector_PinHeader_1.27mm
+PinHeader_1x36_P1.27mm_Horizontal
+Through hole angled pin header, 1x36, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x36 1.27mm single row
+0
+36
+36
+Connector_PinHeader_1.27mm
+PinHeader_1x36_P1.27mm_Vertical
+Through hole straight pin header, 1x36, 1.27mm pitch, single row
+Through hole pin header THT 1x36 1.27mm single row
+0
+36
+36
+Connector_PinHeader_1.27mm
+PinHeader_1x36_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x36, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x36 1.27mm single row style1 pin1 left
+0
+36
+36
+Connector_PinHeader_1.27mm
+PinHeader_1x36_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x36, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x36 1.27mm single row style2 pin1 right
+0
+36
+36
+Connector_PinHeader_1.27mm
+PinHeader_1x37_P1.27mm_Horizontal
+Through hole angled pin header, 1x37, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x37 1.27mm single row
+0
+37
+37
+Connector_PinHeader_1.27mm
+PinHeader_1x37_P1.27mm_Vertical
+Through hole straight pin header, 1x37, 1.27mm pitch, single row
+Through hole pin header THT 1x37 1.27mm single row
+0
+37
+37
+Connector_PinHeader_1.27mm
+PinHeader_1x37_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x37, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x37 1.27mm single row style1 pin1 left
+0
+37
+37
+Connector_PinHeader_1.27mm
+PinHeader_1x37_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x37, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x37 1.27mm single row style2 pin1 right
+0
+37
+37
+Connector_PinHeader_1.27mm
+PinHeader_1x38_P1.27mm_Horizontal
+Through hole angled pin header, 1x38, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x38 1.27mm single row
+0
+38
+38
+Connector_PinHeader_1.27mm
+PinHeader_1x38_P1.27mm_Vertical
+Through hole straight pin header, 1x38, 1.27mm pitch, single row
+Through hole pin header THT 1x38 1.27mm single row
+0
+38
+38
+Connector_PinHeader_1.27mm
+PinHeader_1x38_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x38, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x38 1.27mm single row style1 pin1 left
+0
+38
+38
+Connector_PinHeader_1.27mm
+PinHeader_1x38_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x38, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x38 1.27mm single row style2 pin1 right
+0
+38
+38
+Connector_PinHeader_1.27mm
+PinHeader_1x39_P1.27mm_Horizontal
+Through hole angled pin header, 1x39, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x39 1.27mm single row
+0
+39
+39
+Connector_PinHeader_1.27mm
+PinHeader_1x39_P1.27mm_Vertical
+Through hole straight pin header, 1x39, 1.27mm pitch, single row
+Through hole pin header THT 1x39 1.27mm single row
+0
+39
+39
+Connector_PinHeader_1.27mm
+PinHeader_1x39_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x39, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x39 1.27mm single row style1 pin1 left
+0
+39
+39
+Connector_PinHeader_1.27mm
+PinHeader_1x39_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x39, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x39 1.27mm single row style2 pin1 right
+0
+39
+39
+Connector_PinHeader_1.27mm
+PinHeader_1x40_P1.27mm_Horizontal
+Through hole angled pin header, 1x40, 1.27mm pitch, 4.0mm pin length, single row
+Through hole angled pin header THT 1x40 1.27mm single row
+0
+40
+40
+Connector_PinHeader_1.27mm
+PinHeader_1x40_P1.27mm_Vertical
+Through hole straight pin header, 1x40, 1.27mm pitch, single row
+Through hole pin header THT 1x40 1.27mm single row
+0
+40
+40
+Connector_PinHeader_1.27mm
+PinHeader_1x40_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x40, 1.27mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x40 1.27mm single row style1 pin1 left
+0
+40
+40
+Connector_PinHeader_1.27mm
+PinHeader_1x40_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x40, 1.27mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x40 1.27mm single row style2 pin1 right
+0
+40
+40
+Connector_PinHeader_1.27mm
+PinHeader_2x01_P1.27mm_Horizontal
+Through hole angled pin header, 2x01, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x01 1.27mm double row
+0
+2
+2
+Connector_PinHeader_1.27mm
+PinHeader_2x01_P1.27mm_Vertical
+Through hole straight pin header, 2x01, 1.27mm pitch, double rows
+Through hole pin header THT 2x01 1.27mm double row
+0
+2
+2
+Connector_PinHeader_1.27mm
+PinHeader_2x01_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x01, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x01 1.27mm double row
+0
+2
+2
+Connector_PinHeader_1.27mm
+PinHeader_2x02_P1.27mm_Horizontal
+Through hole angled pin header, 2x02, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x02 1.27mm double row
+0
+4
+4
+Connector_PinHeader_1.27mm
+PinHeader_2x02_P1.27mm_Vertical
+Through hole straight pin header, 2x02, 1.27mm pitch, double rows
+Through hole pin header THT 2x02 1.27mm double row
+0
+4
+4
+Connector_PinHeader_1.27mm
+PinHeader_2x02_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x02, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x02 1.27mm double row
+0
+4
+4
+Connector_PinHeader_1.27mm
+PinHeader_2x03_P1.27mm_Horizontal
+Through hole angled pin header, 2x03, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x03 1.27mm double row
+0
+6
+6
+Connector_PinHeader_1.27mm
+PinHeader_2x03_P1.27mm_Vertical
+Through hole straight pin header, 2x03, 1.27mm pitch, double rows
+Through hole pin header THT 2x03 1.27mm double row
+0
+6
+6
+Connector_PinHeader_1.27mm
+PinHeader_2x03_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x03, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x03 1.27mm double row
+0
+6
+6
+Connector_PinHeader_1.27mm
+PinHeader_2x04_P1.27mm_Horizontal
+Through hole angled pin header, 2x04, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x04 1.27mm double row
+0
+8
+8
+Connector_PinHeader_1.27mm
+PinHeader_2x04_P1.27mm_Vertical
+Through hole straight pin header, 2x04, 1.27mm pitch, double rows
+Through hole pin header THT 2x04 1.27mm double row
+0
+8
+8
+Connector_PinHeader_1.27mm
+PinHeader_2x04_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x04, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x04 1.27mm double row
+0
+8
+8
+Connector_PinHeader_1.27mm
+PinHeader_2x05_P1.27mm_Horizontal
+Through hole angled pin header, 2x05, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x05 1.27mm double row
+0
+10
+10
+Connector_PinHeader_1.27mm
+PinHeader_2x05_P1.27mm_Vertical
+Through hole straight pin header, 2x05, 1.27mm pitch, double rows
+Through hole pin header THT 2x05 1.27mm double row
+0
+10
+10
+Connector_PinHeader_1.27mm
+PinHeader_2x05_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x05, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x05 1.27mm double row
+0
+10
+10
+Connector_PinHeader_1.27mm
+PinHeader_2x06_P1.27mm_Horizontal
+Through hole angled pin header, 2x06, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x06 1.27mm double row
+0
+12
+12
+Connector_PinHeader_1.27mm
+PinHeader_2x06_P1.27mm_Vertical
+Through hole straight pin header, 2x06, 1.27mm pitch, double rows
+Through hole pin header THT 2x06 1.27mm double row
+0
+12
+12
+Connector_PinHeader_1.27mm
+PinHeader_2x06_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x06, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x06 1.27mm double row
+0
+12
+12
+Connector_PinHeader_1.27mm
+PinHeader_2x07_P1.27mm_Horizontal
+Through hole angled pin header, 2x07, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x07 1.27mm double row
+0
+14
+14
+Connector_PinHeader_1.27mm
+PinHeader_2x07_P1.27mm_Vertical
+Through hole straight pin header, 2x07, 1.27mm pitch, double rows
+Through hole pin header THT 2x07 1.27mm double row
+0
+14
+14
+Connector_PinHeader_1.27mm
+PinHeader_2x07_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x07, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x07 1.27mm double row
+0
+14
+14
+Connector_PinHeader_1.27mm
+PinHeader_2x08_P1.27mm_Horizontal
+Through hole angled pin header, 2x08, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x08 1.27mm double row
+0
+16
+16
+Connector_PinHeader_1.27mm
+PinHeader_2x08_P1.27mm_Vertical
+Through hole straight pin header, 2x08, 1.27mm pitch, double rows
+Through hole pin header THT 2x08 1.27mm double row
+0
+16
+16
+Connector_PinHeader_1.27mm
+PinHeader_2x08_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x08, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x08 1.27mm double row
+0
+16
+16
+Connector_PinHeader_1.27mm
+PinHeader_2x09_P1.27mm_Horizontal
+Through hole angled pin header, 2x09, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x09 1.27mm double row
+0
+18
+18
+Connector_PinHeader_1.27mm
+PinHeader_2x09_P1.27mm_Vertical
+Through hole straight pin header, 2x09, 1.27mm pitch, double rows
+Through hole pin header THT 2x09 1.27mm double row
+0
+18
+18
+Connector_PinHeader_1.27mm
+PinHeader_2x09_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x09, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x09 1.27mm double row
+0
+18
+18
+Connector_PinHeader_1.27mm
+PinHeader_2x10_P1.27mm_Horizontal
+Through hole angled pin header, 2x10, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x10 1.27mm double row
+0
+20
+20
+Connector_PinHeader_1.27mm
+PinHeader_2x10_P1.27mm_Vertical
+Through hole straight pin header, 2x10, 1.27mm pitch, double rows
+Through hole pin header THT 2x10 1.27mm double row
+0
+20
+20
+Connector_PinHeader_1.27mm
+PinHeader_2x10_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x10, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x10 1.27mm double row
+0
+20
+20
+Connector_PinHeader_1.27mm
+PinHeader_2x11_P1.27mm_Horizontal
+Through hole angled pin header, 2x11, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x11 1.27mm double row
+0
+22
+22
+Connector_PinHeader_1.27mm
+PinHeader_2x11_P1.27mm_Vertical
+Through hole straight pin header, 2x11, 1.27mm pitch, double rows
+Through hole pin header THT 2x11 1.27mm double row
+0
+22
+22
+Connector_PinHeader_1.27mm
+PinHeader_2x11_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x11, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x11 1.27mm double row
+0
+22
+22
+Connector_PinHeader_1.27mm
+PinHeader_2x12_P1.27mm_Horizontal
+Through hole angled pin header, 2x12, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x12 1.27mm double row
+0
+24
+24
+Connector_PinHeader_1.27mm
+PinHeader_2x12_P1.27mm_Vertical
+Through hole straight pin header, 2x12, 1.27mm pitch, double rows
+Through hole pin header THT 2x12 1.27mm double row
+0
+24
+24
+Connector_PinHeader_1.27mm
+PinHeader_2x12_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x12, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x12 1.27mm double row
+0
+24
+24
+Connector_PinHeader_1.27mm
+PinHeader_2x13_P1.27mm_Horizontal
+Through hole angled pin header, 2x13, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x13 1.27mm double row
+0
+26
+26
+Connector_PinHeader_1.27mm
+PinHeader_2x13_P1.27mm_Vertical
+Through hole straight pin header, 2x13, 1.27mm pitch, double rows
+Through hole pin header THT 2x13 1.27mm double row
+0
+26
+26
+Connector_PinHeader_1.27mm
+PinHeader_2x13_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x13, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x13 1.27mm double row
+0
+26
+26
+Connector_PinHeader_1.27mm
+PinHeader_2x14_P1.27mm_Horizontal
+Through hole angled pin header, 2x14, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x14 1.27mm double row
+0
+28
+28
+Connector_PinHeader_1.27mm
+PinHeader_2x14_P1.27mm_Vertical
+Through hole straight pin header, 2x14, 1.27mm pitch, double rows
+Through hole pin header THT 2x14 1.27mm double row
+0
+28
+28
+Connector_PinHeader_1.27mm
+PinHeader_2x14_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x14, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x14 1.27mm double row
+0
+28
+28
+Connector_PinHeader_1.27mm
+PinHeader_2x15_P1.27mm_Horizontal
+Through hole angled pin header, 2x15, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x15 1.27mm double row
+0
+30
+30
+Connector_PinHeader_1.27mm
+PinHeader_2x15_P1.27mm_Vertical
+Through hole straight pin header, 2x15, 1.27mm pitch, double rows
+Through hole pin header THT 2x15 1.27mm double row
+0
+30
+30
+Connector_PinHeader_1.27mm
+PinHeader_2x15_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x15, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x15 1.27mm double row
+0
+30
+30
+Connector_PinHeader_1.27mm
+PinHeader_2x16_P1.27mm_Horizontal
+Through hole angled pin header, 2x16, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x16 1.27mm double row
+0
+32
+32
+Connector_PinHeader_1.27mm
+PinHeader_2x16_P1.27mm_Vertical
+Through hole straight pin header, 2x16, 1.27mm pitch, double rows
+Through hole pin header THT 2x16 1.27mm double row
+0
+32
+32
+Connector_PinHeader_1.27mm
+PinHeader_2x16_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x16, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x16 1.27mm double row
+0
+32
+32
+Connector_PinHeader_1.27mm
+PinHeader_2x17_P1.27mm_Horizontal
+Through hole angled pin header, 2x17, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x17 1.27mm double row
+0
+34
+34
+Connector_PinHeader_1.27mm
+PinHeader_2x17_P1.27mm_Vertical
+Through hole straight pin header, 2x17, 1.27mm pitch, double rows
+Through hole pin header THT 2x17 1.27mm double row
+0
+34
+34
+Connector_PinHeader_1.27mm
+PinHeader_2x17_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x17, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x17 1.27mm double row
+0
+34
+34
+Connector_PinHeader_1.27mm
+PinHeader_2x18_P1.27mm_Horizontal
+Through hole angled pin header, 2x18, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x18 1.27mm double row
+0
+36
+36
+Connector_PinHeader_1.27mm
+PinHeader_2x18_P1.27mm_Vertical
+Through hole straight pin header, 2x18, 1.27mm pitch, double rows
+Through hole pin header THT 2x18 1.27mm double row
+0
+36
+36
+Connector_PinHeader_1.27mm
+PinHeader_2x18_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x18, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x18 1.27mm double row
+0
+36
+36
+Connector_PinHeader_1.27mm
+PinHeader_2x19_P1.27mm_Horizontal
+Through hole angled pin header, 2x19, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x19 1.27mm double row
+0
+38
+38
+Connector_PinHeader_1.27mm
+PinHeader_2x19_P1.27mm_Vertical
+Through hole straight pin header, 2x19, 1.27mm pitch, double rows
+Through hole pin header THT 2x19 1.27mm double row
+0
+38
+38
+Connector_PinHeader_1.27mm
+PinHeader_2x19_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x19, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x19 1.27mm double row
+0
+38
+38
+Connector_PinHeader_1.27mm
+PinHeader_2x20_P1.27mm_Horizontal
+Through hole angled pin header, 2x20, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x20 1.27mm double row
+0
+40
+40
+Connector_PinHeader_1.27mm
+PinHeader_2x20_P1.27mm_Vertical
+Through hole straight pin header, 2x20, 1.27mm pitch, double rows
+Through hole pin header THT 2x20 1.27mm double row
+0
+40
+40
+Connector_PinHeader_1.27mm
+PinHeader_2x20_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x20, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x20 1.27mm double row
+0
+40
+40
+Connector_PinHeader_1.27mm
+PinHeader_2x21_P1.27mm_Horizontal
+Through hole angled pin header, 2x21, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x21 1.27mm double row
+0
+42
+42
+Connector_PinHeader_1.27mm
+PinHeader_2x21_P1.27mm_Vertical
+Through hole straight pin header, 2x21, 1.27mm pitch, double rows
+Through hole pin header THT 2x21 1.27mm double row
+0
+42
+42
+Connector_PinHeader_1.27mm
+PinHeader_2x21_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x21, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x21 1.27mm double row
+0
+42
+42
+Connector_PinHeader_1.27mm
+PinHeader_2x22_P1.27mm_Horizontal
+Through hole angled pin header, 2x22, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x22 1.27mm double row
+0
+44
+44
+Connector_PinHeader_1.27mm
+PinHeader_2x22_P1.27mm_Vertical
+Through hole straight pin header, 2x22, 1.27mm pitch, double rows
+Through hole pin header THT 2x22 1.27mm double row
+0
+44
+44
+Connector_PinHeader_1.27mm
+PinHeader_2x22_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x22, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x22 1.27mm double row
+0
+44
+44
+Connector_PinHeader_1.27mm
+PinHeader_2x23_P1.27mm_Horizontal
+Through hole angled pin header, 2x23, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x23 1.27mm double row
+0
+46
+46
+Connector_PinHeader_1.27mm
+PinHeader_2x23_P1.27mm_Vertical
+Through hole straight pin header, 2x23, 1.27mm pitch, double rows
+Through hole pin header THT 2x23 1.27mm double row
+0
+46
+46
+Connector_PinHeader_1.27mm
+PinHeader_2x23_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x23, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x23 1.27mm double row
+0
+46
+46
+Connector_PinHeader_1.27mm
+PinHeader_2x24_P1.27mm_Horizontal
+Through hole angled pin header, 2x24, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x24 1.27mm double row
+0
+48
+48
+Connector_PinHeader_1.27mm
+PinHeader_2x24_P1.27mm_Vertical
+Through hole straight pin header, 2x24, 1.27mm pitch, double rows
+Through hole pin header THT 2x24 1.27mm double row
+0
+48
+48
+Connector_PinHeader_1.27mm
+PinHeader_2x24_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x24, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x24 1.27mm double row
+0
+48
+48
+Connector_PinHeader_1.27mm
+PinHeader_2x25_P1.27mm_Horizontal
+Through hole angled pin header, 2x25, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x25 1.27mm double row
+0
+50
+50
+Connector_PinHeader_1.27mm
+PinHeader_2x25_P1.27mm_Vertical
+Through hole straight pin header, 2x25, 1.27mm pitch, double rows
+Through hole pin header THT 2x25 1.27mm double row
+0
+50
+50
+Connector_PinHeader_1.27mm
+PinHeader_2x25_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x25, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x25 1.27mm double row
+0
+50
+50
+Connector_PinHeader_1.27mm
+PinHeader_2x26_P1.27mm_Horizontal
+Through hole angled pin header, 2x26, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x26 1.27mm double row
+0
+52
+52
+Connector_PinHeader_1.27mm
+PinHeader_2x26_P1.27mm_Vertical
+Through hole straight pin header, 2x26, 1.27mm pitch, double rows
+Through hole pin header THT 2x26 1.27mm double row
+0
+52
+52
+Connector_PinHeader_1.27mm
+PinHeader_2x26_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x26, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x26 1.27mm double row
+0
+52
+52
+Connector_PinHeader_1.27mm
+PinHeader_2x27_P1.27mm_Horizontal
+Through hole angled pin header, 2x27, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x27 1.27mm double row
+0
+54
+54
+Connector_PinHeader_1.27mm
+PinHeader_2x27_P1.27mm_Vertical
+Through hole straight pin header, 2x27, 1.27mm pitch, double rows
+Through hole pin header THT 2x27 1.27mm double row
+0
+54
+54
+Connector_PinHeader_1.27mm
+PinHeader_2x27_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x27, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x27 1.27mm double row
+0
+54
+54
+Connector_PinHeader_1.27mm
+PinHeader_2x28_P1.27mm_Horizontal
+Through hole angled pin header, 2x28, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x28 1.27mm double row
+0
+56
+56
+Connector_PinHeader_1.27mm
+PinHeader_2x28_P1.27mm_Vertical
+Through hole straight pin header, 2x28, 1.27mm pitch, double rows
+Through hole pin header THT 2x28 1.27mm double row
+0
+56
+56
+Connector_PinHeader_1.27mm
+PinHeader_2x28_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x28, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x28 1.27mm double row
+0
+56
+56
+Connector_PinHeader_1.27mm
+PinHeader_2x29_P1.27mm_Horizontal
+Through hole angled pin header, 2x29, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x29 1.27mm double row
+0
+58
+58
+Connector_PinHeader_1.27mm
+PinHeader_2x29_P1.27mm_Vertical
+Through hole straight pin header, 2x29, 1.27mm pitch, double rows
+Through hole pin header THT 2x29 1.27mm double row
+0
+58
+58
+Connector_PinHeader_1.27mm
+PinHeader_2x29_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x29, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x29 1.27mm double row
+0
+58
+58
+Connector_PinHeader_1.27mm
+PinHeader_2x30_P1.27mm_Horizontal
+Through hole angled pin header, 2x30, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x30 1.27mm double row
+0
+60
+60
+Connector_PinHeader_1.27mm
+PinHeader_2x30_P1.27mm_Vertical
+Through hole straight pin header, 2x30, 1.27mm pitch, double rows
+Through hole pin header THT 2x30 1.27mm double row
+0
+60
+60
+Connector_PinHeader_1.27mm
+PinHeader_2x30_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x30, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x30 1.27mm double row
+0
+60
+60
+Connector_PinHeader_1.27mm
+PinHeader_2x31_P1.27mm_Horizontal
+Through hole angled pin header, 2x31, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x31 1.27mm double row
+0
+62
+62
+Connector_PinHeader_1.27mm
+PinHeader_2x31_P1.27mm_Vertical
+Through hole straight pin header, 2x31, 1.27mm pitch, double rows
+Through hole pin header THT 2x31 1.27mm double row
+0
+62
+62
+Connector_PinHeader_1.27mm
+PinHeader_2x31_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x31, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x31 1.27mm double row
+0
+62
+62
+Connector_PinHeader_1.27mm
+PinHeader_2x32_P1.27mm_Horizontal
+Through hole angled pin header, 2x32, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x32 1.27mm double row
+0
+64
+64
+Connector_PinHeader_1.27mm
+PinHeader_2x32_P1.27mm_Vertical
+Through hole straight pin header, 2x32, 1.27mm pitch, double rows
+Through hole pin header THT 2x32 1.27mm double row
+0
+64
+64
+Connector_PinHeader_1.27mm
+PinHeader_2x32_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x32, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x32 1.27mm double row
+0
+64
+64
+Connector_PinHeader_1.27mm
+PinHeader_2x33_P1.27mm_Horizontal
+Through hole angled pin header, 2x33, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x33 1.27mm double row
+0
+66
+66
+Connector_PinHeader_1.27mm
+PinHeader_2x33_P1.27mm_Vertical
+Through hole straight pin header, 2x33, 1.27mm pitch, double rows
+Through hole pin header THT 2x33 1.27mm double row
+0
+66
+66
+Connector_PinHeader_1.27mm
+PinHeader_2x33_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x33, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x33 1.27mm double row
+0
+66
+66
+Connector_PinHeader_1.27mm
+PinHeader_2x34_P1.27mm_Horizontal
+Through hole angled pin header, 2x34, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x34 1.27mm double row
+0
+68
+68
+Connector_PinHeader_1.27mm
+PinHeader_2x34_P1.27mm_Vertical
+Through hole straight pin header, 2x34, 1.27mm pitch, double rows
+Through hole pin header THT 2x34 1.27mm double row
+0
+68
+68
+Connector_PinHeader_1.27mm
+PinHeader_2x34_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x34, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x34 1.27mm double row
+0
+68
+68
+Connector_PinHeader_1.27mm
+PinHeader_2x35_P1.27mm_Horizontal
+Through hole angled pin header, 2x35, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x35 1.27mm double row
+0
+70
+70
+Connector_PinHeader_1.27mm
+PinHeader_2x35_P1.27mm_Vertical
+Through hole straight pin header, 2x35, 1.27mm pitch, double rows
+Through hole pin header THT 2x35 1.27mm double row
+0
+70
+70
+Connector_PinHeader_1.27mm
+PinHeader_2x35_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x35, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x35 1.27mm double row
+0
+70
+70
+Connector_PinHeader_1.27mm
+PinHeader_2x36_P1.27mm_Horizontal
+Through hole angled pin header, 2x36, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x36 1.27mm double row
+0
+72
+72
+Connector_PinHeader_1.27mm
+PinHeader_2x36_P1.27mm_Vertical
+Through hole straight pin header, 2x36, 1.27mm pitch, double rows
+Through hole pin header THT 2x36 1.27mm double row
+0
+72
+72
+Connector_PinHeader_1.27mm
+PinHeader_2x36_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x36, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x36 1.27mm double row
+0
+72
+72
+Connector_PinHeader_1.27mm
+PinHeader_2x37_P1.27mm_Horizontal
+Through hole angled pin header, 2x37, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x37 1.27mm double row
+0
+74
+74
+Connector_PinHeader_1.27mm
+PinHeader_2x37_P1.27mm_Vertical
+Through hole straight pin header, 2x37, 1.27mm pitch, double rows
+Through hole pin header THT 2x37 1.27mm double row
+0
+74
+74
+Connector_PinHeader_1.27mm
+PinHeader_2x37_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x37, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x37 1.27mm double row
+0
+74
+74
+Connector_PinHeader_1.27mm
+PinHeader_2x38_P1.27mm_Horizontal
+Through hole angled pin header, 2x38, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x38 1.27mm double row
+0
+76
+76
+Connector_PinHeader_1.27mm
+PinHeader_2x38_P1.27mm_Vertical
+Through hole straight pin header, 2x38, 1.27mm pitch, double rows
+Through hole pin header THT 2x38 1.27mm double row
+0
+76
+76
+Connector_PinHeader_1.27mm
+PinHeader_2x38_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x38, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x38 1.27mm double row
+0
+76
+76
+Connector_PinHeader_1.27mm
+PinHeader_2x39_P1.27mm_Horizontal
+Through hole angled pin header, 2x39, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x39 1.27mm double row
+0
+78
+78
+Connector_PinHeader_1.27mm
+PinHeader_2x39_P1.27mm_Vertical
+Through hole straight pin header, 2x39, 1.27mm pitch, double rows
+Through hole pin header THT 2x39 1.27mm double row
+0
+78
+78
+Connector_PinHeader_1.27mm
+PinHeader_2x39_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x39, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x39 1.27mm double row
+0
+78
+78
+Connector_PinHeader_1.27mm
+PinHeader_2x40_P1.27mm_Horizontal
+Through hole angled pin header, 2x40, 1.27mm pitch, 4.0mm pin length, double rows
+Through hole angled pin header THT 2x40 1.27mm double row
+0
+80
+80
+Connector_PinHeader_1.27mm
+PinHeader_2x40_P1.27mm_Vertical
+Through hole straight pin header, 2x40, 1.27mm pitch, double rows
+Through hole pin header THT 2x40 1.27mm double row
+0
+80
+80
+Connector_PinHeader_1.27mm
+PinHeader_2x40_P1.27mm_Vertical_SMD
+surface-mounted straight pin header, 2x40, 1.27mm pitch, double rows
+Surface mounted pin header SMD 2x40 1.27mm double row
+0
+80
+80
+Connector_PinHeader_2.00mm
+PinHeader_1x01_P2.00mm_Horizontal
+Through hole angled pin header, 1x01, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x01 2.00mm single row
+0
+1
+1
+Connector_PinHeader_2.00mm
+PinHeader_1x01_P2.00mm_Vertical
+Through hole straight pin header, 1x01, 2.00mm pitch, single row
+Through hole pin header THT 1x01 2.00mm single row
+0
+1
+1
+Connector_PinHeader_2.00mm
+PinHeader_1x02_P2.00mm_Horizontal
+Through hole angled pin header, 1x02, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x02 2.00mm single row
+0
+2
+2
+Connector_PinHeader_2.00mm
+PinHeader_1x02_P2.00mm_Vertical
+Through hole straight pin header, 1x02, 2.00mm pitch, single row
+Through hole pin header THT 1x02 2.00mm single row
+0
+2
+2
+Connector_PinHeader_2.00mm
+PinHeader_1x02_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x02, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x02 2.00mm single row style1 pin1 left
+0
+2
+2
+Connector_PinHeader_2.00mm
+PinHeader_1x02_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x02, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x02 2.00mm single row style2 pin1 right
+0
+2
+2
+Connector_PinHeader_2.00mm
+PinHeader_1x03_P2.00mm_Horizontal
+Through hole angled pin header, 1x03, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x03 2.00mm single row
+0
+3
+3
+Connector_PinHeader_2.00mm
+PinHeader_1x03_P2.00mm_Vertical
+Through hole straight pin header, 1x03, 2.00mm pitch, single row
+Through hole pin header THT 1x03 2.00mm single row
+0
+3
+3
+Connector_PinHeader_2.00mm
+PinHeader_1x03_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x03, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x03 2.00mm single row style1 pin1 left
+0
+3
+3
+Connector_PinHeader_2.00mm
+PinHeader_1x03_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x03, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x03 2.00mm single row style2 pin1 right
+0
+3
+3
+Connector_PinHeader_2.00mm
+PinHeader_1x04_P2.00mm_Horizontal
+Through hole angled pin header, 1x04, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x04 2.00mm single row
+0
+4
+4
+Connector_PinHeader_2.00mm
+PinHeader_1x04_P2.00mm_Vertical
+Through hole straight pin header, 1x04, 2.00mm pitch, single row
+Through hole pin header THT 1x04 2.00mm single row
+0
+4
+4
+Connector_PinHeader_2.00mm
+PinHeader_1x04_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x04, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x04 2.00mm single row style1 pin1 left
+0
+4
+4
+Connector_PinHeader_2.00mm
+PinHeader_1x04_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x04, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x04 2.00mm single row style2 pin1 right
+0
+4
+4
+Connector_PinHeader_2.00mm
+PinHeader_1x05_P2.00mm_Horizontal
+Through hole angled pin header, 1x05, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x05 2.00mm single row
+0
+5
+5
+Connector_PinHeader_2.00mm
+PinHeader_1x05_P2.00mm_Vertical
+Through hole straight pin header, 1x05, 2.00mm pitch, single row
+Through hole pin header THT 1x05 2.00mm single row
+0
+5
+5
+Connector_PinHeader_2.00mm
+PinHeader_1x05_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x05, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x05 2.00mm single row style1 pin1 left
+0
+5
+5
+Connector_PinHeader_2.00mm
+PinHeader_1x05_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x05, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x05 2.00mm single row style2 pin1 right
+0
+5
+5
+Connector_PinHeader_2.00mm
+PinHeader_1x06_P2.00mm_Horizontal
+Through hole angled pin header, 1x06, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x06 2.00mm single row
+0
+6
+6
+Connector_PinHeader_2.00mm
+PinHeader_1x06_P2.00mm_Vertical
+Through hole straight pin header, 1x06, 2.00mm pitch, single row
+Through hole pin header THT 1x06 2.00mm single row
+0
+6
+6
+Connector_PinHeader_2.00mm
+PinHeader_1x06_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x06, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x06 2.00mm single row style1 pin1 left
+0
+6
+6
+Connector_PinHeader_2.00mm
+PinHeader_1x06_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x06, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x06 2.00mm single row style2 pin1 right
+0
+6
+6
+Connector_PinHeader_2.00mm
+PinHeader_1x07_P2.00mm_Horizontal
+Through hole angled pin header, 1x07, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x07 2.00mm single row
+0
+7
+7
+Connector_PinHeader_2.00mm
+PinHeader_1x07_P2.00mm_Vertical
+Through hole straight pin header, 1x07, 2.00mm pitch, single row
+Through hole pin header THT 1x07 2.00mm single row
+0
+7
+7
+Connector_PinHeader_2.00mm
+PinHeader_1x07_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x07, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x07 2.00mm single row style1 pin1 left
+0
+7
+7
+Connector_PinHeader_2.00mm
+PinHeader_1x07_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x07, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x07 2.00mm single row style2 pin1 right
+0
+7
+7
+Connector_PinHeader_2.00mm
+PinHeader_1x08_P2.00mm_Horizontal
+Through hole angled pin header, 1x08, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x08 2.00mm single row
+0
+8
+8
+Connector_PinHeader_2.00mm
+PinHeader_1x08_P2.00mm_Vertical
+Through hole straight pin header, 1x08, 2.00mm pitch, single row
+Through hole pin header THT 1x08 2.00mm single row
+0
+8
+8
+Connector_PinHeader_2.00mm
+PinHeader_1x08_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x08, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x08 2.00mm single row style1 pin1 left
+0
+8
+8
+Connector_PinHeader_2.00mm
+PinHeader_1x08_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x08, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x08 2.00mm single row style2 pin1 right
+0
+8
+8
+Connector_PinHeader_2.00mm
+PinHeader_1x09_P2.00mm_Horizontal
+Through hole angled pin header, 1x09, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x09 2.00mm single row
+0
+9
+9
+Connector_PinHeader_2.00mm
+PinHeader_1x09_P2.00mm_Vertical
+Through hole straight pin header, 1x09, 2.00mm pitch, single row
+Through hole pin header THT 1x09 2.00mm single row
+0
+9
+9
+Connector_PinHeader_2.00mm
+PinHeader_1x09_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x09, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x09 2.00mm single row style1 pin1 left
+0
+9
+9
+Connector_PinHeader_2.00mm
+PinHeader_1x09_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x09, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x09 2.00mm single row style2 pin1 right
+0
+9
+9
+Connector_PinHeader_2.00mm
+PinHeader_1x10_P2.00mm_Horizontal
+Through hole angled pin header, 1x10, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x10 2.00mm single row
+0
+10
+10
+Connector_PinHeader_2.00mm
+PinHeader_1x10_P2.00mm_Vertical
+Through hole straight pin header, 1x10, 2.00mm pitch, single row
+Through hole pin header THT 1x10 2.00mm single row
+0
+10
+10
+Connector_PinHeader_2.00mm
+PinHeader_1x10_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x10, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x10 2.00mm single row style1 pin1 left
+0
+10
+10
+Connector_PinHeader_2.00mm
+PinHeader_1x10_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x10, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x10 2.00mm single row style2 pin1 right
+0
+10
+10
+Connector_PinHeader_2.00mm
+PinHeader_1x11_P2.00mm_Horizontal
+Through hole angled pin header, 1x11, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x11 2.00mm single row
+0
+11
+11
+Connector_PinHeader_2.00mm
+PinHeader_1x11_P2.00mm_Vertical
+Through hole straight pin header, 1x11, 2.00mm pitch, single row
+Through hole pin header THT 1x11 2.00mm single row
+0
+11
+11
+Connector_PinHeader_2.00mm
+PinHeader_1x11_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x11, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x11 2.00mm single row style1 pin1 left
+0
+11
+11
+Connector_PinHeader_2.00mm
+PinHeader_1x11_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x11, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x11 2.00mm single row style2 pin1 right
+0
+11
+11
+Connector_PinHeader_2.00mm
+PinHeader_1x12_P2.00mm_Horizontal
+Through hole angled pin header, 1x12, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x12 2.00mm single row
+0
+12
+12
+Connector_PinHeader_2.00mm
+PinHeader_1x12_P2.00mm_Vertical
+Through hole straight pin header, 1x12, 2.00mm pitch, single row
+Through hole pin header THT 1x12 2.00mm single row
+0
+12
+12
+Connector_PinHeader_2.00mm
+PinHeader_1x12_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x12, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x12 2.00mm single row style1 pin1 left
+0
+12
+12
+Connector_PinHeader_2.00mm
+PinHeader_1x12_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x12, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x12 2.00mm single row style2 pin1 right
+0
+12
+12
+Connector_PinHeader_2.00mm
+PinHeader_1x13_P2.00mm_Horizontal
+Through hole angled pin header, 1x13, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x13 2.00mm single row
+0
+13
+13
+Connector_PinHeader_2.00mm
+PinHeader_1x13_P2.00mm_Vertical
+Through hole straight pin header, 1x13, 2.00mm pitch, single row
+Through hole pin header THT 1x13 2.00mm single row
+0
+13
+13
+Connector_PinHeader_2.00mm
+PinHeader_1x13_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x13, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x13 2.00mm single row style1 pin1 left
+0
+13
+13
+Connector_PinHeader_2.00mm
+PinHeader_1x13_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x13, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x13 2.00mm single row style2 pin1 right
+0
+13
+13
+Connector_PinHeader_2.00mm
+PinHeader_1x14_P2.00mm_Horizontal
+Through hole angled pin header, 1x14, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x14 2.00mm single row
+0
+14
+14
+Connector_PinHeader_2.00mm
+PinHeader_1x14_P2.00mm_Vertical
+Through hole straight pin header, 1x14, 2.00mm pitch, single row
+Through hole pin header THT 1x14 2.00mm single row
+0
+14
+14
+Connector_PinHeader_2.00mm
+PinHeader_1x14_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x14, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x14 2.00mm single row style1 pin1 left
+0
+14
+14
+Connector_PinHeader_2.00mm
+PinHeader_1x14_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x14, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x14 2.00mm single row style2 pin1 right
+0
+14
+14
+Connector_PinHeader_2.00mm
+PinHeader_1x15_P2.00mm_Horizontal
+Through hole angled pin header, 1x15, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x15 2.00mm single row
+0
+15
+15
+Connector_PinHeader_2.00mm
+PinHeader_1x15_P2.00mm_Vertical
+Through hole straight pin header, 1x15, 2.00mm pitch, single row
+Through hole pin header THT 1x15 2.00mm single row
+0
+15
+15
+Connector_PinHeader_2.00mm
+PinHeader_1x15_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x15, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x15 2.00mm single row style1 pin1 left
+0
+15
+15
+Connector_PinHeader_2.00mm
+PinHeader_1x15_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x15, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x15 2.00mm single row style2 pin1 right
+0
+15
+15
+Connector_PinHeader_2.00mm
+PinHeader_1x16_P2.00mm_Horizontal
+Through hole angled pin header, 1x16, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x16 2.00mm single row
+0
+16
+16
+Connector_PinHeader_2.00mm
+PinHeader_1x16_P2.00mm_Vertical
+Through hole straight pin header, 1x16, 2.00mm pitch, single row
+Through hole pin header THT 1x16 2.00mm single row
+0
+16
+16
+Connector_PinHeader_2.00mm
+PinHeader_1x16_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x16, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x16 2.00mm single row style1 pin1 left
+0
+16
+16
+Connector_PinHeader_2.00mm
+PinHeader_1x16_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x16, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x16 2.00mm single row style2 pin1 right
+0
+16
+16
+Connector_PinHeader_2.00mm
+PinHeader_1x17_P2.00mm_Horizontal
+Through hole angled pin header, 1x17, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x17 2.00mm single row
+0
+17
+17
+Connector_PinHeader_2.00mm
+PinHeader_1x17_P2.00mm_Vertical
+Through hole straight pin header, 1x17, 2.00mm pitch, single row
+Through hole pin header THT 1x17 2.00mm single row
+0
+17
+17
+Connector_PinHeader_2.00mm
+PinHeader_1x17_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x17, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x17 2.00mm single row style1 pin1 left
+0
+17
+17
+Connector_PinHeader_2.00mm
+PinHeader_1x17_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x17, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x17 2.00mm single row style2 pin1 right
+0
+17
+17
+Connector_PinHeader_2.00mm
+PinHeader_1x18_P2.00mm_Horizontal
+Through hole angled pin header, 1x18, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x18 2.00mm single row
+0
+18
+18
+Connector_PinHeader_2.00mm
+PinHeader_1x18_P2.00mm_Vertical
+Through hole straight pin header, 1x18, 2.00mm pitch, single row
+Through hole pin header THT 1x18 2.00mm single row
+0
+18
+18
+Connector_PinHeader_2.00mm
+PinHeader_1x18_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x18, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x18 2.00mm single row style1 pin1 left
+0
+18
+18
+Connector_PinHeader_2.00mm
+PinHeader_1x18_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x18, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x18 2.00mm single row style2 pin1 right
+0
+18
+18
+Connector_PinHeader_2.00mm
+PinHeader_1x19_P2.00mm_Horizontal
+Through hole angled pin header, 1x19, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x19 2.00mm single row
+0
+19
+19
+Connector_PinHeader_2.00mm
+PinHeader_1x19_P2.00mm_Vertical
+Through hole straight pin header, 1x19, 2.00mm pitch, single row
+Through hole pin header THT 1x19 2.00mm single row
+0
+19
+19
+Connector_PinHeader_2.00mm
+PinHeader_1x19_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x19, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x19 2.00mm single row style1 pin1 left
+0
+19
+19
+Connector_PinHeader_2.00mm
+PinHeader_1x19_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x19, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x19 2.00mm single row style2 pin1 right
+0
+19
+19
+Connector_PinHeader_2.00mm
+PinHeader_1x20_P2.00mm_Horizontal
+Through hole angled pin header, 1x20, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x20 2.00mm single row
+0
+20
+20
+Connector_PinHeader_2.00mm
+PinHeader_1x20_P2.00mm_Vertical
+Through hole straight pin header, 1x20, 2.00mm pitch, single row
+Through hole pin header THT 1x20 2.00mm single row
+0
+20
+20
+Connector_PinHeader_2.00mm
+PinHeader_1x20_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x20, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x20 2.00mm single row style1 pin1 left
+0
+20
+20
+Connector_PinHeader_2.00mm
+PinHeader_1x20_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x20, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x20 2.00mm single row style2 pin1 right
+0
+20
+20
+Connector_PinHeader_2.00mm
+PinHeader_1x21_P2.00mm_Horizontal
+Through hole angled pin header, 1x21, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x21 2.00mm single row
+0
+21
+21
+Connector_PinHeader_2.00mm
+PinHeader_1x21_P2.00mm_Vertical
+Through hole straight pin header, 1x21, 2.00mm pitch, single row
+Through hole pin header THT 1x21 2.00mm single row
+0
+21
+21
+Connector_PinHeader_2.00mm
+PinHeader_1x21_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x21, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x21 2.00mm single row style1 pin1 left
+0
+21
+21
+Connector_PinHeader_2.00mm
+PinHeader_1x21_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x21, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x21 2.00mm single row style2 pin1 right
+0
+21
+21
+Connector_PinHeader_2.00mm
+PinHeader_1x22_P2.00mm_Horizontal
+Through hole angled pin header, 1x22, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x22 2.00mm single row
+0
+22
+22
+Connector_PinHeader_2.00mm
+PinHeader_1x22_P2.00mm_Vertical
+Through hole straight pin header, 1x22, 2.00mm pitch, single row
+Through hole pin header THT 1x22 2.00mm single row
+0
+22
+22
+Connector_PinHeader_2.00mm
+PinHeader_1x22_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x22, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x22 2.00mm single row style1 pin1 left
+0
+22
+22
+Connector_PinHeader_2.00mm
+PinHeader_1x22_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x22, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x22 2.00mm single row style2 pin1 right
+0
+22
+22
+Connector_PinHeader_2.00mm
+PinHeader_1x23_P2.00mm_Horizontal
+Through hole angled pin header, 1x23, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x23 2.00mm single row
+0
+23
+23
+Connector_PinHeader_2.00mm
+PinHeader_1x23_P2.00mm_Vertical
+Through hole straight pin header, 1x23, 2.00mm pitch, single row
+Through hole pin header THT 1x23 2.00mm single row
+0
+23
+23
+Connector_PinHeader_2.00mm
+PinHeader_1x23_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x23, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x23 2.00mm single row style1 pin1 left
+0
+23
+23
+Connector_PinHeader_2.00mm
+PinHeader_1x23_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x23, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x23 2.00mm single row style2 pin1 right
+0
+23
+23
+Connector_PinHeader_2.00mm
+PinHeader_1x24_P2.00mm_Horizontal
+Through hole angled pin header, 1x24, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x24 2.00mm single row
+0
+24
+24
+Connector_PinHeader_2.00mm
+PinHeader_1x24_P2.00mm_Vertical
+Through hole straight pin header, 1x24, 2.00mm pitch, single row
+Through hole pin header THT 1x24 2.00mm single row
+0
+24
+24
+Connector_PinHeader_2.00mm
+PinHeader_1x24_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x24, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x24 2.00mm single row style1 pin1 left
+0
+24
+24
+Connector_PinHeader_2.00mm
+PinHeader_1x24_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x24, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x24 2.00mm single row style2 pin1 right
+0
+24
+24
+Connector_PinHeader_2.00mm
+PinHeader_1x25_P2.00mm_Horizontal
+Through hole angled pin header, 1x25, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x25 2.00mm single row
+0
+25
+25
+Connector_PinHeader_2.00mm
+PinHeader_1x25_P2.00mm_Vertical
+Through hole straight pin header, 1x25, 2.00mm pitch, single row
+Through hole pin header THT 1x25 2.00mm single row
+0
+25
+25
+Connector_PinHeader_2.00mm
+PinHeader_1x25_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x25, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x25 2.00mm single row style1 pin1 left
+0
+25
+25
+Connector_PinHeader_2.00mm
+PinHeader_1x25_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x25, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x25 2.00mm single row style2 pin1 right
+0
+25
+25
+Connector_PinHeader_2.00mm
+PinHeader_1x26_P2.00mm_Horizontal
+Through hole angled pin header, 1x26, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x26 2.00mm single row
+0
+26
+26
+Connector_PinHeader_2.00mm
+PinHeader_1x26_P2.00mm_Vertical
+Through hole straight pin header, 1x26, 2.00mm pitch, single row
+Through hole pin header THT 1x26 2.00mm single row
+0
+26
+26
+Connector_PinHeader_2.00mm
+PinHeader_1x26_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x26, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x26 2.00mm single row style1 pin1 left
+0
+26
+26
+Connector_PinHeader_2.00mm
+PinHeader_1x26_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x26, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x26 2.00mm single row style2 pin1 right
+0
+26
+26
+Connector_PinHeader_2.00mm
+PinHeader_1x27_P2.00mm_Horizontal
+Through hole angled pin header, 1x27, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x27 2.00mm single row
+0
+27
+27
+Connector_PinHeader_2.00mm
+PinHeader_1x27_P2.00mm_Vertical
+Through hole straight pin header, 1x27, 2.00mm pitch, single row
+Through hole pin header THT 1x27 2.00mm single row
+0
+27
+27
+Connector_PinHeader_2.00mm
+PinHeader_1x27_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x27, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x27 2.00mm single row style1 pin1 left
+0
+27
+27
+Connector_PinHeader_2.00mm
+PinHeader_1x27_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x27, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x27 2.00mm single row style2 pin1 right
+0
+27
+27
+Connector_PinHeader_2.00mm
+PinHeader_1x28_P2.00mm_Horizontal
+Through hole angled pin header, 1x28, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x28 2.00mm single row
+0
+28
+28
+Connector_PinHeader_2.00mm
+PinHeader_1x28_P2.00mm_Vertical
+Through hole straight pin header, 1x28, 2.00mm pitch, single row
+Through hole pin header THT 1x28 2.00mm single row
+0
+28
+28
+Connector_PinHeader_2.00mm
+PinHeader_1x28_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x28, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x28 2.00mm single row style1 pin1 left
+0
+28
+28
+Connector_PinHeader_2.00mm
+PinHeader_1x28_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x28, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x28 2.00mm single row style2 pin1 right
+0
+28
+28
+Connector_PinHeader_2.00mm
+PinHeader_1x29_P2.00mm_Horizontal
+Through hole angled pin header, 1x29, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x29 2.00mm single row
+0
+29
+29
+Connector_PinHeader_2.00mm
+PinHeader_1x29_P2.00mm_Vertical
+Through hole straight pin header, 1x29, 2.00mm pitch, single row
+Through hole pin header THT 1x29 2.00mm single row
+0
+29
+29
+Connector_PinHeader_2.00mm
+PinHeader_1x29_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x29, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x29 2.00mm single row style1 pin1 left
+0
+29
+29
+Connector_PinHeader_2.00mm
+PinHeader_1x29_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x29, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x29 2.00mm single row style2 pin1 right
+0
+29
+29
+Connector_PinHeader_2.00mm
+PinHeader_1x30_P2.00mm_Horizontal
+Through hole angled pin header, 1x30, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x30 2.00mm single row
+0
+30
+30
+Connector_PinHeader_2.00mm
+PinHeader_1x30_P2.00mm_Vertical
+Through hole straight pin header, 1x30, 2.00mm pitch, single row
+Through hole pin header THT 1x30 2.00mm single row
+0
+30
+30
+Connector_PinHeader_2.00mm
+PinHeader_1x30_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x30, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x30 2.00mm single row style1 pin1 left
+0
+30
+30
+Connector_PinHeader_2.00mm
+PinHeader_1x30_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x30, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x30 2.00mm single row style2 pin1 right
+0
+30
+30
+Connector_PinHeader_2.00mm
+PinHeader_1x31_P2.00mm_Horizontal
+Through hole angled pin header, 1x31, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x31 2.00mm single row
+0
+31
+31
+Connector_PinHeader_2.00mm
+PinHeader_1x31_P2.00mm_Vertical
+Through hole straight pin header, 1x31, 2.00mm pitch, single row
+Through hole pin header THT 1x31 2.00mm single row
+0
+31
+31
+Connector_PinHeader_2.00mm
+PinHeader_1x31_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x31, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x31 2.00mm single row style1 pin1 left
+0
+31
+31
+Connector_PinHeader_2.00mm
+PinHeader_1x31_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x31, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x31 2.00mm single row style2 pin1 right
+0
+31
+31
+Connector_PinHeader_2.00mm
+PinHeader_1x32_P2.00mm_Horizontal
+Through hole angled pin header, 1x32, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x32 2.00mm single row
+0
+32
+32
+Connector_PinHeader_2.00mm
+PinHeader_1x32_P2.00mm_Vertical
+Through hole straight pin header, 1x32, 2.00mm pitch, single row
+Through hole pin header THT 1x32 2.00mm single row
+0
+32
+32
+Connector_PinHeader_2.00mm
+PinHeader_1x32_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x32, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x32 2.00mm single row style1 pin1 left
+0
+32
+32
+Connector_PinHeader_2.00mm
+PinHeader_1x32_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x32, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x32 2.00mm single row style2 pin1 right
+0
+32
+32
+Connector_PinHeader_2.00mm
+PinHeader_1x33_P2.00mm_Horizontal
+Through hole angled pin header, 1x33, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x33 2.00mm single row
+0
+33
+33
+Connector_PinHeader_2.00mm
+PinHeader_1x33_P2.00mm_Vertical
+Through hole straight pin header, 1x33, 2.00mm pitch, single row
+Through hole pin header THT 1x33 2.00mm single row
+0
+33
+33
+Connector_PinHeader_2.00mm
+PinHeader_1x33_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x33, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x33 2.00mm single row style1 pin1 left
+0
+33
+33
+Connector_PinHeader_2.00mm
+PinHeader_1x33_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x33, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x33 2.00mm single row style2 pin1 right
+0
+33
+33
+Connector_PinHeader_2.00mm
+PinHeader_1x34_P2.00mm_Horizontal
+Through hole angled pin header, 1x34, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x34 2.00mm single row
+0
+34
+34
+Connector_PinHeader_2.00mm
+PinHeader_1x34_P2.00mm_Vertical
+Through hole straight pin header, 1x34, 2.00mm pitch, single row
+Through hole pin header THT 1x34 2.00mm single row
+0
+34
+34
+Connector_PinHeader_2.00mm
+PinHeader_1x34_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x34, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x34 2.00mm single row style1 pin1 left
+0
+34
+34
+Connector_PinHeader_2.00mm
+PinHeader_1x34_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x34, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x34 2.00mm single row style2 pin1 right
+0
+34
+34
+Connector_PinHeader_2.00mm
+PinHeader_1x35_P2.00mm_Horizontal
+Through hole angled pin header, 1x35, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x35 2.00mm single row
+0
+35
+35
+Connector_PinHeader_2.00mm
+PinHeader_1x35_P2.00mm_Vertical
+Through hole straight pin header, 1x35, 2.00mm pitch, single row
+Through hole pin header THT 1x35 2.00mm single row
+0
+35
+35
+Connector_PinHeader_2.00mm
+PinHeader_1x35_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x35, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x35 2.00mm single row style1 pin1 left
+0
+35
+35
+Connector_PinHeader_2.00mm
+PinHeader_1x35_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x35, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x35 2.00mm single row style2 pin1 right
+0
+35
+35
+Connector_PinHeader_2.00mm
+PinHeader_1x36_P2.00mm_Horizontal
+Through hole angled pin header, 1x36, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x36 2.00mm single row
+0
+36
+36
+Connector_PinHeader_2.00mm
+PinHeader_1x36_P2.00mm_Vertical
+Through hole straight pin header, 1x36, 2.00mm pitch, single row
+Through hole pin header THT 1x36 2.00mm single row
+0
+36
+36
+Connector_PinHeader_2.00mm
+PinHeader_1x36_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x36, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x36 2.00mm single row style1 pin1 left
+0
+36
+36
+Connector_PinHeader_2.00mm
+PinHeader_1x36_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x36, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x36 2.00mm single row style2 pin1 right
+0
+36
+36
+Connector_PinHeader_2.00mm
+PinHeader_1x37_P2.00mm_Horizontal
+Through hole angled pin header, 1x37, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x37 2.00mm single row
+0
+37
+37
+Connector_PinHeader_2.00mm
+PinHeader_1x37_P2.00mm_Vertical
+Through hole straight pin header, 1x37, 2.00mm pitch, single row
+Through hole pin header THT 1x37 2.00mm single row
+0
+37
+37
+Connector_PinHeader_2.00mm
+PinHeader_1x37_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x37, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x37 2.00mm single row style1 pin1 left
+0
+37
+37
+Connector_PinHeader_2.00mm
+PinHeader_1x37_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x37, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x37 2.00mm single row style2 pin1 right
+0
+37
+37
+Connector_PinHeader_2.00mm
+PinHeader_1x38_P2.00mm_Horizontal
+Through hole angled pin header, 1x38, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x38 2.00mm single row
+0
+38
+38
+Connector_PinHeader_2.00mm
+PinHeader_1x38_P2.00mm_Vertical
+Through hole straight pin header, 1x38, 2.00mm pitch, single row
+Through hole pin header THT 1x38 2.00mm single row
+0
+38
+38
+Connector_PinHeader_2.00mm
+PinHeader_1x38_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x38, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x38 2.00mm single row style1 pin1 left
+0
+38
+38
+Connector_PinHeader_2.00mm
+PinHeader_1x38_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x38, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x38 2.00mm single row style2 pin1 right
+0
+38
+38
+Connector_PinHeader_2.00mm
+PinHeader_1x39_P2.00mm_Horizontal
+Through hole angled pin header, 1x39, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x39 2.00mm single row
+0
+39
+39
+Connector_PinHeader_2.00mm
+PinHeader_1x39_P2.00mm_Vertical
+Through hole straight pin header, 1x39, 2.00mm pitch, single row
+Through hole pin header THT 1x39 2.00mm single row
+0
+39
+39
+Connector_PinHeader_2.00mm
+PinHeader_1x39_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x39, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x39 2.00mm single row style1 pin1 left
+0
+39
+39
+Connector_PinHeader_2.00mm
+PinHeader_1x39_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x39, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x39 2.00mm single row style2 pin1 right
+0
+39
+39
+Connector_PinHeader_2.00mm
+PinHeader_1x40_P2.00mm_Horizontal
+Through hole angled pin header, 1x40, 2.00mm pitch, 4.2mm pin length, single row
+Through hole angled pin header THT 1x40 2.00mm single row
+0
+40
+40
+Connector_PinHeader_2.00mm
+PinHeader_1x40_P2.00mm_Vertical
+Through hole straight pin header, 1x40, 2.00mm pitch, single row
+Through hole pin header THT 1x40 2.00mm single row
+0
+40
+40
+Connector_PinHeader_2.00mm
+PinHeader_1x40_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x40, 2.00mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x40 2.00mm single row style1 pin1 left
+0
+40
+40
+Connector_PinHeader_2.00mm
+PinHeader_1x40_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x40, 2.00mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x40 2.00mm single row style2 pin1 right
+0
+40
+40
+Connector_PinHeader_2.00mm
+PinHeader_2x01_P2.00mm_Horizontal
+Through hole angled pin header, 2x01, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x01 2.00mm double row
+0
+2
+2
+Connector_PinHeader_2.00mm
+PinHeader_2x01_P2.00mm_Vertical
+Through hole straight pin header, 2x01, 2.00mm pitch, double rows
+Through hole pin header THT 2x01 2.00mm double row
+0
+2
+2
+Connector_PinHeader_2.00mm
+PinHeader_2x01_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x01, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x01 2.00mm double row
+0
+2
+2
+Connector_PinHeader_2.00mm
+PinHeader_2x02_P2.00mm_Horizontal
+Through hole angled pin header, 2x02, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x02 2.00mm double row
+0
+4
+4
+Connector_PinHeader_2.00mm
+PinHeader_2x02_P2.00mm_Vertical
+Through hole straight pin header, 2x02, 2.00mm pitch, double rows
+Through hole pin header THT 2x02 2.00mm double row
+0
+4
+4
+Connector_PinHeader_2.00mm
+PinHeader_2x02_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x02, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x02 2.00mm double row
+0
+4
+4
+Connector_PinHeader_2.00mm
+PinHeader_2x03_P2.00mm_Horizontal
+Through hole angled pin header, 2x03, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x03 2.00mm double row
+0
+6
+6
+Connector_PinHeader_2.00mm
+PinHeader_2x03_P2.00mm_Vertical
+Through hole straight pin header, 2x03, 2.00mm pitch, double rows
+Through hole pin header THT 2x03 2.00mm double row
+0
+6
+6
+Connector_PinHeader_2.00mm
+PinHeader_2x03_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x03, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x03 2.00mm double row
+0
+6
+6
+Connector_PinHeader_2.00mm
+PinHeader_2x04_P2.00mm_Horizontal
+Through hole angled pin header, 2x04, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x04 2.00mm double row
+0
+8
+8
+Connector_PinHeader_2.00mm
+PinHeader_2x04_P2.00mm_Vertical
+Through hole straight pin header, 2x04, 2.00mm pitch, double rows
+Through hole pin header THT 2x04 2.00mm double row
+0
+8
+8
+Connector_PinHeader_2.00mm
+PinHeader_2x04_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x04, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x04 2.00mm double row
+0
+8
+8
+Connector_PinHeader_2.00mm
+PinHeader_2x05_P2.00mm_Horizontal
+Through hole angled pin header, 2x05, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x05 2.00mm double row
+0
+10
+10
+Connector_PinHeader_2.00mm
+PinHeader_2x05_P2.00mm_Vertical
+Through hole straight pin header, 2x05, 2.00mm pitch, double rows
+Through hole pin header THT 2x05 2.00mm double row
+0
+10
+10
+Connector_PinHeader_2.00mm
+PinHeader_2x05_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x05, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x05 2.00mm double row
+0
+10
+10
+Connector_PinHeader_2.00mm
+PinHeader_2x06_P2.00mm_Horizontal
+Through hole angled pin header, 2x06, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x06 2.00mm double row
+0
+12
+12
+Connector_PinHeader_2.00mm
+PinHeader_2x06_P2.00mm_Vertical
+Through hole straight pin header, 2x06, 2.00mm pitch, double rows
+Through hole pin header THT 2x06 2.00mm double row
+0
+12
+12
+Connector_PinHeader_2.00mm
+PinHeader_2x06_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x06, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x06 2.00mm double row
+0
+12
+12
+Connector_PinHeader_2.00mm
+PinHeader_2x07_P2.00mm_Horizontal
+Through hole angled pin header, 2x07, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x07 2.00mm double row
+0
+14
+14
+Connector_PinHeader_2.00mm
+PinHeader_2x07_P2.00mm_Vertical
+Through hole straight pin header, 2x07, 2.00mm pitch, double rows
+Through hole pin header THT 2x07 2.00mm double row
+0
+14
+14
+Connector_PinHeader_2.00mm
+PinHeader_2x07_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x07, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x07 2.00mm double row
+0
+14
+14
+Connector_PinHeader_2.00mm
+PinHeader_2x08_P2.00mm_Horizontal
+Through hole angled pin header, 2x08, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x08 2.00mm double row
+0
+16
+16
+Connector_PinHeader_2.00mm
+PinHeader_2x08_P2.00mm_Vertical
+Through hole straight pin header, 2x08, 2.00mm pitch, double rows
+Through hole pin header THT 2x08 2.00mm double row
+0
+16
+16
+Connector_PinHeader_2.00mm
+PinHeader_2x08_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x08, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x08 2.00mm double row
+0
+16
+16
+Connector_PinHeader_2.00mm
+PinHeader_2x09_P2.00mm_Horizontal
+Through hole angled pin header, 2x09, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x09 2.00mm double row
+0
+18
+18
+Connector_PinHeader_2.00mm
+PinHeader_2x09_P2.00mm_Vertical
+Through hole straight pin header, 2x09, 2.00mm pitch, double rows
+Through hole pin header THT 2x09 2.00mm double row
+0
+18
+18
+Connector_PinHeader_2.00mm
+PinHeader_2x09_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x09, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x09 2.00mm double row
+0
+18
+18
+Connector_PinHeader_2.00mm
+PinHeader_2x10_P2.00mm_Horizontal
+Through hole angled pin header, 2x10, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x10 2.00mm double row
+0
+20
+20
+Connector_PinHeader_2.00mm
+PinHeader_2x10_P2.00mm_Vertical
+Through hole straight pin header, 2x10, 2.00mm pitch, double rows
+Through hole pin header THT 2x10 2.00mm double row
+0
+20
+20
+Connector_PinHeader_2.00mm
+PinHeader_2x10_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x10, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x10 2.00mm double row
+0
+20
+20
+Connector_PinHeader_2.00mm
+PinHeader_2x11_P2.00mm_Horizontal
+Through hole angled pin header, 2x11, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x11 2.00mm double row
+0
+22
+22
+Connector_PinHeader_2.00mm
+PinHeader_2x11_P2.00mm_Vertical
+Through hole straight pin header, 2x11, 2.00mm pitch, double rows
+Through hole pin header THT 2x11 2.00mm double row
+0
+22
+22
+Connector_PinHeader_2.00mm
+PinHeader_2x11_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x11, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x11 2.00mm double row
+0
+22
+22
+Connector_PinHeader_2.00mm
+PinHeader_2x12_P2.00mm_Horizontal
+Through hole angled pin header, 2x12, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x12 2.00mm double row
+0
+24
+24
+Connector_PinHeader_2.00mm
+PinHeader_2x12_P2.00mm_Vertical
+Through hole straight pin header, 2x12, 2.00mm pitch, double rows
+Through hole pin header THT 2x12 2.00mm double row
+0
+24
+24
+Connector_PinHeader_2.00mm
+PinHeader_2x12_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x12, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x12 2.00mm double row
+0
+24
+24
+Connector_PinHeader_2.00mm
+PinHeader_2x13_P2.00mm_Horizontal
+Through hole angled pin header, 2x13, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x13 2.00mm double row
+0
+26
+26
+Connector_PinHeader_2.00mm
+PinHeader_2x13_P2.00mm_Vertical
+Through hole straight pin header, 2x13, 2.00mm pitch, double rows
+Through hole pin header THT 2x13 2.00mm double row
+0
+26
+26
+Connector_PinHeader_2.00mm
+PinHeader_2x13_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x13, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x13 2.00mm double row
+0
+26
+26
+Connector_PinHeader_2.00mm
+PinHeader_2x14_P2.00mm_Horizontal
+Through hole angled pin header, 2x14, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x14 2.00mm double row
+0
+28
+28
+Connector_PinHeader_2.00mm
+PinHeader_2x14_P2.00mm_Vertical
+Through hole straight pin header, 2x14, 2.00mm pitch, double rows
+Through hole pin header THT 2x14 2.00mm double row
+0
+28
+28
+Connector_PinHeader_2.00mm
+PinHeader_2x14_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x14, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x14 2.00mm double row
+0
+28
+28
+Connector_PinHeader_2.00mm
+PinHeader_2x15_P2.00mm_Horizontal
+Through hole angled pin header, 2x15, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x15 2.00mm double row
+0
+30
+30
+Connector_PinHeader_2.00mm
+PinHeader_2x15_P2.00mm_Vertical
+Through hole straight pin header, 2x15, 2.00mm pitch, double rows
+Through hole pin header THT 2x15 2.00mm double row
+0
+30
+30
+Connector_PinHeader_2.00mm
+PinHeader_2x15_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x15, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x15 2.00mm double row
+0
+30
+30
+Connector_PinHeader_2.00mm
+PinHeader_2x16_P2.00mm_Horizontal
+Through hole angled pin header, 2x16, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x16 2.00mm double row
+0
+32
+32
+Connector_PinHeader_2.00mm
+PinHeader_2x16_P2.00mm_Vertical
+Through hole straight pin header, 2x16, 2.00mm pitch, double rows
+Through hole pin header THT 2x16 2.00mm double row
+0
+32
+32
+Connector_PinHeader_2.00mm
+PinHeader_2x16_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x16, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x16 2.00mm double row
+0
+32
+32
+Connector_PinHeader_2.00mm
+PinHeader_2x17_P2.00mm_Horizontal
+Through hole angled pin header, 2x17, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x17 2.00mm double row
+0
+34
+34
+Connector_PinHeader_2.00mm
+PinHeader_2x17_P2.00mm_Vertical
+Through hole straight pin header, 2x17, 2.00mm pitch, double rows
+Through hole pin header THT 2x17 2.00mm double row
+0
+34
+34
+Connector_PinHeader_2.00mm
+PinHeader_2x17_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x17, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x17 2.00mm double row
+0
+34
+34
+Connector_PinHeader_2.00mm
+PinHeader_2x18_P2.00mm_Horizontal
+Through hole angled pin header, 2x18, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x18 2.00mm double row
+0
+36
+36
+Connector_PinHeader_2.00mm
+PinHeader_2x18_P2.00mm_Vertical
+Through hole straight pin header, 2x18, 2.00mm pitch, double rows
+Through hole pin header THT 2x18 2.00mm double row
+0
+36
+36
+Connector_PinHeader_2.00mm
+PinHeader_2x18_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x18, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x18 2.00mm double row
+0
+36
+36
+Connector_PinHeader_2.00mm
+PinHeader_2x19_P2.00mm_Horizontal
+Through hole angled pin header, 2x19, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x19 2.00mm double row
+0
+38
+38
+Connector_PinHeader_2.00mm
+PinHeader_2x19_P2.00mm_Vertical
+Through hole straight pin header, 2x19, 2.00mm pitch, double rows
+Through hole pin header THT 2x19 2.00mm double row
+0
+38
+38
+Connector_PinHeader_2.00mm
+PinHeader_2x19_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x19, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x19 2.00mm double row
+0
+38
+38
+Connector_PinHeader_2.00mm
+PinHeader_2x20_P2.00mm_Horizontal
+Through hole angled pin header, 2x20, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x20 2.00mm double row
+0
+40
+40
+Connector_PinHeader_2.00mm
+PinHeader_2x20_P2.00mm_Vertical
+Through hole straight pin header, 2x20, 2.00mm pitch, double rows
+Through hole pin header THT 2x20 2.00mm double row
+0
+40
+40
+Connector_PinHeader_2.00mm
+PinHeader_2x20_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x20, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x20 2.00mm double row
+0
+40
+40
+Connector_PinHeader_2.00mm
+PinHeader_2x21_P2.00mm_Horizontal
+Through hole angled pin header, 2x21, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x21 2.00mm double row
+0
+42
+42
+Connector_PinHeader_2.00mm
+PinHeader_2x21_P2.00mm_Vertical
+Through hole straight pin header, 2x21, 2.00mm pitch, double rows
+Through hole pin header THT 2x21 2.00mm double row
+0
+42
+42
+Connector_PinHeader_2.00mm
+PinHeader_2x21_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x21, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x21 2.00mm double row
+0
+42
+42
+Connector_PinHeader_2.00mm
+PinHeader_2x22_P2.00mm_Horizontal
+Through hole angled pin header, 2x22, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x22 2.00mm double row
+0
+44
+44
+Connector_PinHeader_2.00mm
+PinHeader_2x22_P2.00mm_Vertical
+Through hole straight pin header, 2x22, 2.00mm pitch, double rows
+Through hole pin header THT 2x22 2.00mm double row
+0
+44
+44
+Connector_PinHeader_2.00mm
+PinHeader_2x22_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x22, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x22 2.00mm double row
+0
+44
+44
+Connector_PinHeader_2.00mm
+PinHeader_2x23_P2.00mm_Horizontal
+Through hole angled pin header, 2x23, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x23 2.00mm double row
+0
+46
+46
+Connector_PinHeader_2.00mm
+PinHeader_2x23_P2.00mm_Vertical
+Through hole straight pin header, 2x23, 2.00mm pitch, double rows
+Through hole pin header THT 2x23 2.00mm double row
+0
+46
+46
+Connector_PinHeader_2.00mm
+PinHeader_2x23_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x23, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x23 2.00mm double row
+0
+46
+46
+Connector_PinHeader_2.00mm
+PinHeader_2x24_P2.00mm_Horizontal
+Through hole angled pin header, 2x24, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x24 2.00mm double row
+0
+48
+48
+Connector_PinHeader_2.00mm
+PinHeader_2x24_P2.00mm_Vertical
+Through hole straight pin header, 2x24, 2.00mm pitch, double rows
+Through hole pin header THT 2x24 2.00mm double row
+0
+48
+48
+Connector_PinHeader_2.00mm
+PinHeader_2x24_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x24, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x24 2.00mm double row
+0
+48
+48
+Connector_PinHeader_2.00mm
+PinHeader_2x25_P2.00mm_Horizontal
+Through hole angled pin header, 2x25, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x25 2.00mm double row
+0
+50
+50
+Connector_PinHeader_2.00mm
+PinHeader_2x25_P2.00mm_Vertical
+Through hole straight pin header, 2x25, 2.00mm pitch, double rows
+Through hole pin header THT 2x25 2.00mm double row
+0
+50
+50
+Connector_PinHeader_2.00mm
+PinHeader_2x25_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x25, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x25 2.00mm double row
+0
+50
+50
+Connector_PinHeader_2.00mm
+PinHeader_2x26_P2.00mm_Horizontal
+Through hole angled pin header, 2x26, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x26 2.00mm double row
+0
+52
+52
+Connector_PinHeader_2.00mm
+PinHeader_2x26_P2.00mm_Vertical
+Through hole straight pin header, 2x26, 2.00mm pitch, double rows
+Through hole pin header THT 2x26 2.00mm double row
+0
+52
+52
+Connector_PinHeader_2.00mm
+PinHeader_2x26_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x26, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x26 2.00mm double row
+0
+52
+52
+Connector_PinHeader_2.00mm
+PinHeader_2x27_P2.00mm_Horizontal
+Through hole angled pin header, 2x27, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x27 2.00mm double row
+0
+54
+54
+Connector_PinHeader_2.00mm
+PinHeader_2x27_P2.00mm_Vertical
+Through hole straight pin header, 2x27, 2.00mm pitch, double rows
+Through hole pin header THT 2x27 2.00mm double row
+0
+54
+54
+Connector_PinHeader_2.00mm
+PinHeader_2x27_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x27, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x27 2.00mm double row
+0
+54
+54
+Connector_PinHeader_2.00mm
+PinHeader_2x28_P2.00mm_Horizontal
+Through hole angled pin header, 2x28, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x28 2.00mm double row
+0
+56
+56
+Connector_PinHeader_2.00mm
+PinHeader_2x28_P2.00mm_Vertical
+Through hole straight pin header, 2x28, 2.00mm pitch, double rows
+Through hole pin header THT 2x28 2.00mm double row
+0
+56
+56
+Connector_PinHeader_2.00mm
+PinHeader_2x28_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x28, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x28 2.00mm double row
+0
+56
+56
+Connector_PinHeader_2.00mm
+PinHeader_2x29_P2.00mm_Horizontal
+Through hole angled pin header, 2x29, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x29 2.00mm double row
+0
+58
+58
+Connector_PinHeader_2.00mm
+PinHeader_2x29_P2.00mm_Vertical
+Through hole straight pin header, 2x29, 2.00mm pitch, double rows
+Through hole pin header THT 2x29 2.00mm double row
+0
+58
+58
+Connector_PinHeader_2.00mm
+PinHeader_2x29_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x29, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x29 2.00mm double row
+0
+58
+58
+Connector_PinHeader_2.00mm
+PinHeader_2x30_P2.00mm_Horizontal
+Through hole angled pin header, 2x30, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x30 2.00mm double row
+0
+60
+60
+Connector_PinHeader_2.00mm
+PinHeader_2x30_P2.00mm_Vertical
+Through hole straight pin header, 2x30, 2.00mm pitch, double rows
+Through hole pin header THT 2x30 2.00mm double row
+0
+60
+60
+Connector_PinHeader_2.00mm
+PinHeader_2x30_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x30, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x30 2.00mm double row
+0
+60
+60
+Connector_PinHeader_2.00mm
+PinHeader_2x31_P2.00mm_Horizontal
+Through hole angled pin header, 2x31, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x31 2.00mm double row
+0
+62
+62
+Connector_PinHeader_2.00mm
+PinHeader_2x31_P2.00mm_Vertical
+Through hole straight pin header, 2x31, 2.00mm pitch, double rows
+Through hole pin header THT 2x31 2.00mm double row
+0
+62
+62
+Connector_PinHeader_2.00mm
+PinHeader_2x31_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x31, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x31 2.00mm double row
+0
+62
+62
+Connector_PinHeader_2.00mm
+PinHeader_2x32_P2.00mm_Horizontal
+Through hole angled pin header, 2x32, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x32 2.00mm double row
+0
+64
+64
+Connector_PinHeader_2.00mm
+PinHeader_2x32_P2.00mm_Vertical
+Through hole straight pin header, 2x32, 2.00mm pitch, double rows
+Through hole pin header THT 2x32 2.00mm double row
+0
+64
+64
+Connector_PinHeader_2.00mm
+PinHeader_2x32_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x32, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x32 2.00mm double row
+0
+64
+64
+Connector_PinHeader_2.00mm
+PinHeader_2x33_P2.00mm_Horizontal
+Through hole angled pin header, 2x33, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x33 2.00mm double row
+0
+66
+66
+Connector_PinHeader_2.00mm
+PinHeader_2x33_P2.00mm_Vertical
+Through hole straight pin header, 2x33, 2.00mm pitch, double rows
+Through hole pin header THT 2x33 2.00mm double row
+0
+66
+66
+Connector_PinHeader_2.00mm
+PinHeader_2x33_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x33, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x33 2.00mm double row
+0
+66
+66
+Connector_PinHeader_2.00mm
+PinHeader_2x34_P2.00mm_Horizontal
+Through hole angled pin header, 2x34, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x34 2.00mm double row
+0
+68
+68
+Connector_PinHeader_2.00mm
+PinHeader_2x34_P2.00mm_Vertical
+Through hole straight pin header, 2x34, 2.00mm pitch, double rows
+Through hole pin header THT 2x34 2.00mm double row
+0
+68
+68
+Connector_PinHeader_2.00mm
+PinHeader_2x34_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x34, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x34 2.00mm double row
+0
+68
+68
+Connector_PinHeader_2.00mm
+PinHeader_2x35_P2.00mm_Horizontal
+Through hole angled pin header, 2x35, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x35 2.00mm double row
+0
+70
+70
+Connector_PinHeader_2.00mm
+PinHeader_2x35_P2.00mm_Vertical
+Through hole straight pin header, 2x35, 2.00mm pitch, double rows
+Through hole pin header THT 2x35 2.00mm double row
+0
+70
+70
+Connector_PinHeader_2.00mm
+PinHeader_2x35_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x35, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x35 2.00mm double row
+0
+70
+70
+Connector_PinHeader_2.00mm
+PinHeader_2x36_P2.00mm_Horizontal
+Through hole angled pin header, 2x36, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x36 2.00mm double row
+0
+72
+72
+Connector_PinHeader_2.00mm
+PinHeader_2x36_P2.00mm_Vertical
+Through hole straight pin header, 2x36, 2.00mm pitch, double rows
+Through hole pin header THT 2x36 2.00mm double row
+0
+72
+72
+Connector_PinHeader_2.00mm
+PinHeader_2x36_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x36, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x36 2.00mm double row
+0
+72
+72
+Connector_PinHeader_2.00mm
+PinHeader_2x37_P2.00mm_Horizontal
+Through hole angled pin header, 2x37, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x37 2.00mm double row
+0
+74
+74
+Connector_PinHeader_2.00mm
+PinHeader_2x37_P2.00mm_Vertical
+Through hole straight pin header, 2x37, 2.00mm pitch, double rows
+Through hole pin header THT 2x37 2.00mm double row
+0
+74
+74
+Connector_PinHeader_2.00mm
+PinHeader_2x37_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x37, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x37 2.00mm double row
+0
+74
+74
+Connector_PinHeader_2.00mm
+PinHeader_2x38_P2.00mm_Horizontal
+Through hole angled pin header, 2x38, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x38 2.00mm double row
+0
+76
+76
+Connector_PinHeader_2.00mm
+PinHeader_2x38_P2.00mm_Vertical
+Through hole straight pin header, 2x38, 2.00mm pitch, double rows
+Through hole pin header THT 2x38 2.00mm double row
+0
+76
+76
+Connector_PinHeader_2.00mm
+PinHeader_2x38_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x38, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x38 2.00mm double row
+0
+76
+76
+Connector_PinHeader_2.00mm
+PinHeader_2x39_P2.00mm_Horizontal
+Through hole angled pin header, 2x39, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x39 2.00mm double row
+0
+78
+78
+Connector_PinHeader_2.00mm
+PinHeader_2x39_P2.00mm_Vertical
+Through hole straight pin header, 2x39, 2.00mm pitch, double rows
+Through hole pin header THT 2x39 2.00mm double row
+0
+78
+78
+Connector_PinHeader_2.00mm
+PinHeader_2x39_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x39, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x39 2.00mm double row
+0
+78
+78
+Connector_PinHeader_2.00mm
+PinHeader_2x40_P2.00mm_Horizontal
+Through hole angled pin header, 2x40, 2.00mm pitch, 4.2mm pin length, double rows
+Through hole angled pin header THT 2x40 2.00mm double row
+0
+80
+80
+Connector_PinHeader_2.00mm
+PinHeader_2x40_P2.00mm_Vertical
+Through hole straight pin header, 2x40, 2.00mm pitch, double rows
+Through hole pin header THT 2x40 2.00mm double row
+0
+80
+80
+Connector_PinHeader_2.00mm
+PinHeader_2x40_P2.00mm_Vertical_SMD
+surface-mounted straight pin header, 2x40, 2.00mm pitch, double rows
+Surface mounted pin header SMD 2x40 2.00mm double row
+0
+80
+80
+Connector_PinHeader_2.54mm
+PinHeader_1x01_P2.54mm_Horizontal
+Through hole angled pin header, 1x01, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x01 2.54mm single row
+0
+1
+1
+Connector_PinHeader_2.54mm
+PinHeader_1x01_P2.54mm_Vertical
+Through hole straight pin header, 1x01, 2.54mm pitch, single row
+Through hole pin header THT 1x01 2.54mm single row
+0
+1
+1
+Connector_PinHeader_2.54mm
+PinHeader_1x02_P2.54mm_Horizontal
+Through hole angled pin header, 1x02, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x02 2.54mm single row
+0
+2
+2
+Connector_PinHeader_2.54mm
+PinHeader_1x02_P2.54mm_Vertical
+Through hole straight pin header, 1x02, 2.54mm pitch, single row
+Through hole pin header THT 1x02 2.54mm single row
+0
+2
+2
+Connector_PinHeader_2.54mm
+PinHeader_1x02_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x02, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x02 2.54mm single row style1 pin1 left
+0
+2
+2
+Connector_PinHeader_2.54mm
+PinHeader_1x02_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x02, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x02 2.54mm single row style2 pin1 right
+0
+2
+2
+Connector_PinHeader_2.54mm
+PinHeader_1x03_P2.54mm_Horizontal
+Through hole angled pin header, 1x03, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x03 2.54mm single row
+0
+3
+3
+Connector_PinHeader_2.54mm
+PinHeader_1x03_P2.54mm_Vertical
+Through hole straight pin header, 1x03, 2.54mm pitch, single row
+Through hole pin header THT 1x03 2.54mm single row
+0
+3
+3
+Connector_PinHeader_2.54mm
+PinHeader_1x03_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x03, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x03 2.54mm single row style1 pin1 left
+0
+3
+3
+Connector_PinHeader_2.54mm
+PinHeader_1x03_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x03, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x03 2.54mm single row style2 pin1 right
+0
+3
+3
+Connector_PinHeader_2.54mm
+PinHeader_1x04_P2.54mm_Horizontal
+Through hole angled pin header, 1x04, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x04 2.54mm single row
+0
+4
+4
+Connector_PinHeader_2.54mm
+PinHeader_1x04_P2.54mm_Vertical
+Through hole straight pin header, 1x04, 2.54mm pitch, single row
+Through hole pin header THT 1x04 2.54mm single row
+0
+4
+4
+Connector_PinHeader_2.54mm
+PinHeader_1x04_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x04, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x04 2.54mm single row style1 pin1 left
+0
+4
+4
+Connector_PinHeader_2.54mm
+PinHeader_1x04_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x04, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x04 2.54mm single row style2 pin1 right
+0
+4
+4
+Connector_PinHeader_2.54mm
+PinHeader_1x05_P2.54mm_Horizontal
+Through hole angled pin header, 1x05, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x05 2.54mm single row
+0
+5
+5
+Connector_PinHeader_2.54mm
+PinHeader_1x05_P2.54mm_Vertical
+Through hole straight pin header, 1x05, 2.54mm pitch, single row
+Through hole pin header THT 1x05 2.54mm single row
+0
+5
+5
+Connector_PinHeader_2.54mm
+PinHeader_1x05_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x05, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x05 2.54mm single row style1 pin1 left
+0
+5
+5
+Connector_PinHeader_2.54mm
+PinHeader_1x05_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x05, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x05 2.54mm single row style2 pin1 right
+0
+5
+5
+Connector_PinHeader_2.54mm
+PinHeader_1x06_P2.54mm_Horizontal
+Through hole angled pin header, 1x06, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x06 2.54mm single row
+0
+6
+6
+Connector_PinHeader_2.54mm
+PinHeader_1x06_P2.54mm_Vertical
+Through hole straight pin header, 1x06, 2.54mm pitch, single row
+Through hole pin header THT 1x06 2.54mm single row
+0
+6
+6
+Connector_PinHeader_2.54mm
+PinHeader_1x06_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x06, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x06 2.54mm single row style1 pin1 left
+0
+6
+6
+Connector_PinHeader_2.54mm
+PinHeader_1x06_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x06, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x06 2.54mm single row style2 pin1 right
+0
+6
+6
+Connector_PinHeader_2.54mm
+PinHeader_1x07_P2.54mm_Horizontal
+Through hole angled pin header, 1x07, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x07 2.54mm single row
+0
+7
+7
+Connector_PinHeader_2.54mm
+PinHeader_1x07_P2.54mm_Vertical
+Through hole straight pin header, 1x07, 2.54mm pitch, single row
+Through hole pin header THT 1x07 2.54mm single row
+0
+7
+7
+Connector_PinHeader_2.54mm
+PinHeader_1x07_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x07, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x07 2.54mm single row style1 pin1 left
+0
+7
+7
+Connector_PinHeader_2.54mm
+PinHeader_1x07_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x07, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x07 2.54mm single row style2 pin1 right
+0
+7
+7
+Connector_PinHeader_2.54mm
+PinHeader_1x08_P2.54mm_Horizontal
+Through hole angled pin header, 1x08, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x08 2.54mm single row
+0
+8
+8
+Connector_PinHeader_2.54mm
+PinHeader_1x08_P2.54mm_Vertical
+Through hole straight pin header, 1x08, 2.54mm pitch, single row
+Through hole pin header THT 1x08 2.54mm single row
+0
+8
+8
+Connector_PinHeader_2.54mm
+PinHeader_1x08_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x08, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x08 2.54mm single row style1 pin1 left
+0
+8
+8
+Connector_PinHeader_2.54mm
+PinHeader_1x08_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x08, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x08 2.54mm single row style2 pin1 right
+0
+8
+8
+Connector_PinHeader_2.54mm
+PinHeader_1x09_P2.54mm_Horizontal
+Through hole angled pin header, 1x09, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x09 2.54mm single row
+0
+9
+9
+Connector_PinHeader_2.54mm
+PinHeader_1x09_P2.54mm_Vertical
+Through hole straight pin header, 1x09, 2.54mm pitch, single row
+Through hole pin header THT 1x09 2.54mm single row
+0
+9
+9
+Connector_PinHeader_2.54mm
+PinHeader_1x09_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x09, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x09 2.54mm single row style1 pin1 left
+0
+9
+9
+Connector_PinHeader_2.54mm
+PinHeader_1x09_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x09, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x09 2.54mm single row style2 pin1 right
+0
+9
+9
+Connector_PinHeader_2.54mm
+PinHeader_1x10_P2.54mm_Horizontal
+Through hole angled pin header, 1x10, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x10 2.54mm single row
+0
+10
+10
+Connector_PinHeader_2.54mm
+PinHeader_1x10_P2.54mm_Vertical
+Through hole straight pin header, 1x10, 2.54mm pitch, single row
+Through hole pin header THT 1x10 2.54mm single row
+0
+10
+10
+Connector_PinHeader_2.54mm
+PinHeader_1x10_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x10, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x10 2.54mm single row style1 pin1 left
+0
+10
+10
+Connector_PinHeader_2.54mm
+PinHeader_1x10_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x10, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x10 2.54mm single row style2 pin1 right
+0
+10
+10
+Connector_PinHeader_2.54mm
+PinHeader_1x11_P2.54mm_Horizontal
+Through hole angled pin header, 1x11, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x11 2.54mm single row
+0
+11
+11
+Connector_PinHeader_2.54mm
+PinHeader_1x11_P2.54mm_Vertical
+Through hole straight pin header, 1x11, 2.54mm pitch, single row
+Through hole pin header THT 1x11 2.54mm single row
+0
+11
+11
+Connector_PinHeader_2.54mm
+PinHeader_1x11_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x11, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x11 2.54mm single row style1 pin1 left
+0
+11
+11
+Connector_PinHeader_2.54mm
+PinHeader_1x11_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x11, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x11 2.54mm single row style2 pin1 right
+0
+11
+11
+Connector_PinHeader_2.54mm
+PinHeader_1x12_P2.54mm_Horizontal
+Through hole angled pin header, 1x12, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x12 2.54mm single row
+0
+12
+12
+Connector_PinHeader_2.54mm
+PinHeader_1x12_P2.54mm_Vertical
+Through hole straight pin header, 1x12, 2.54mm pitch, single row
+Through hole pin header THT 1x12 2.54mm single row
+0
+12
+12
+Connector_PinHeader_2.54mm
+PinHeader_1x12_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x12, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x12 2.54mm single row style1 pin1 left
+0
+12
+12
+Connector_PinHeader_2.54mm
+PinHeader_1x12_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x12, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x12 2.54mm single row style2 pin1 right
+0
+12
+12
+Connector_PinHeader_2.54mm
+PinHeader_1x13_P2.54mm_Horizontal
+Through hole angled pin header, 1x13, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x13 2.54mm single row
+0
+13
+13
+Connector_PinHeader_2.54mm
+PinHeader_1x13_P2.54mm_Vertical
+Through hole straight pin header, 1x13, 2.54mm pitch, single row
+Through hole pin header THT 1x13 2.54mm single row
+0
+13
+13
+Connector_PinHeader_2.54mm
+PinHeader_1x13_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x13, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x13 2.54mm single row style1 pin1 left
+0
+13
+13
+Connector_PinHeader_2.54mm
+PinHeader_1x13_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x13, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x13 2.54mm single row style2 pin1 right
+0
+13
+13
+Connector_PinHeader_2.54mm
+PinHeader_1x14_P2.54mm_Horizontal
+Through hole angled pin header, 1x14, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x14 2.54mm single row
+0
+14
+14
+Connector_PinHeader_2.54mm
+PinHeader_1x14_P2.54mm_Vertical
+Through hole straight pin header, 1x14, 2.54mm pitch, single row
+Through hole pin header THT 1x14 2.54mm single row
+0
+14
+14
+Connector_PinHeader_2.54mm
+PinHeader_1x14_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x14, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x14 2.54mm single row style1 pin1 left
+0
+14
+14
+Connector_PinHeader_2.54mm
+PinHeader_1x14_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x14, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x14 2.54mm single row style2 pin1 right
+0
+14
+14
+Connector_PinHeader_2.54mm
+PinHeader_1x15_P2.54mm_Horizontal
+Through hole angled pin header, 1x15, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x15 2.54mm single row
+0
+15
+15
+Connector_PinHeader_2.54mm
+PinHeader_1x15_P2.54mm_Vertical
+Through hole straight pin header, 1x15, 2.54mm pitch, single row
+Through hole pin header THT 1x15 2.54mm single row
+0
+15
+15
+Connector_PinHeader_2.54mm
+PinHeader_1x15_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x15, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x15 2.54mm single row style1 pin1 left
+0
+15
+15
+Connector_PinHeader_2.54mm
+PinHeader_1x15_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x15, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x15 2.54mm single row style2 pin1 right
+0
+15
+15
+Connector_PinHeader_2.54mm
+PinHeader_1x16_P2.54mm_Horizontal
+Through hole angled pin header, 1x16, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x16 2.54mm single row
+0
+16
+16
+Connector_PinHeader_2.54mm
+PinHeader_1x16_P2.54mm_Vertical
+Through hole straight pin header, 1x16, 2.54mm pitch, single row
+Through hole pin header THT 1x16 2.54mm single row
+0
+16
+16
+Connector_PinHeader_2.54mm
+PinHeader_1x16_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x16, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x16 2.54mm single row style1 pin1 left
+0
+16
+16
+Connector_PinHeader_2.54mm
+PinHeader_1x16_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x16, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x16 2.54mm single row style2 pin1 right
+0
+16
+16
+Connector_PinHeader_2.54mm
+PinHeader_1x17_P2.54mm_Horizontal
+Through hole angled pin header, 1x17, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x17 2.54mm single row
+0
+17
+17
+Connector_PinHeader_2.54mm
+PinHeader_1x17_P2.54mm_Vertical
+Through hole straight pin header, 1x17, 2.54mm pitch, single row
+Through hole pin header THT 1x17 2.54mm single row
+0
+17
+17
+Connector_PinHeader_2.54mm
+PinHeader_1x17_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x17, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x17 2.54mm single row style1 pin1 left
+0
+17
+17
+Connector_PinHeader_2.54mm
+PinHeader_1x17_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x17, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x17 2.54mm single row style2 pin1 right
+0
+17
+17
+Connector_PinHeader_2.54mm
+PinHeader_1x18_P2.54mm_Horizontal
+Through hole angled pin header, 1x18, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x18 2.54mm single row
+0
+18
+18
+Connector_PinHeader_2.54mm
+PinHeader_1x18_P2.54mm_Vertical
+Through hole straight pin header, 1x18, 2.54mm pitch, single row
+Through hole pin header THT 1x18 2.54mm single row
+0
+18
+18
+Connector_PinHeader_2.54mm
+PinHeader_1x18_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x18, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x18 2.54mm single row style1 pin1 left
+0
+18
+18
+Connector_PinHeader_2.54mm
+PinHeader_1x18_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x18, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x18 2.54mm single row style2 pin1 right
+0
+18
+18
+Connector_PinHeader_2.54mm
+PinHeader_1x19_P2.54mm_Horizontal
+Through hole angled pin header, 1x19, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x19 2.54mm single row
+0
+19
+19
+Connector_PinHeader_2.54mm
+PinHeader_1x19_P2.54mm_Vertical
+Through hole straight pin header, 1x19, 2.54mm pitch, single row
+Through hole pin header THT 1x19 2.54mm single row
+0
+19
+19
+Connector_PinHeader_2.54mm
+PinHeader_1x19_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x19, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x19 2.54mm single row style1 pin1 left
+0
+19
+19
+Connector_PinHeader_2.54mm
+PinHeader_1x19_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x19, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x19 2.54mm single row style2 pin1 right
+0
+19
+19
+Connector_PinHeader_2.54mm
+PinHeader_1x20_P2.54mm_Horizontal
+Through hole angled pin header, 1x20, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x20 2.54mm single row
+0
+20
+20
+Connector_PinHeader_2.54mm
+PinHeader_1x20_P2.54mm_Vertical
+Through hole straight pin header, 1x20, 2.54mm pitch, single row
+Through hole pin header THT 1x20 2.54mm single row
+0
+20
+20
+Connector_PinHeader_2.54mm
+PinHeader_1x20_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x20, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x20 2.54mm single row style1 pin1 left
+0
+20
+20
+Connector_PinHeader_2.54mm
+PinHeader_1x20_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x20, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x20 2.54mm single row style2 pin1 right
+0
+20
+20
+Connector_PinHeader_2.54mm
+PinHeader_1x21_P2.54mm_Horizontal
+Through hole angled pin header, 1x21, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x21 2.54mm single row
+0
+21
+21
+Connector_PinHeader_2.54mm
+PinHeader_1x21_P2.54mm_Vertical
+Through hole straight pin header, 1x21, 2.54mm pitch, single row
+Through hole pin header THT 1x21 2.54mm single row
+0
+21
+21
+Connector_PinHeader_2.54mm
+PinHeader_1x21_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x21, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x21 2.54mm single row style1 pin1 left
+0
+21
+21
+Connector_PinHeader_2.54mm
+PinHeader_1x21_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x21, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x21 2.54mm single row style2 pin1 right
+0
+21
+21
+Connector_PinHeader_2.54mm
+PinHeader_1x22_P2.54mm_Horizontal
+Through hole angled pin header, 1x22, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x22 2.54mm single row
+0
+22
+22
+Connector_PinHeader_2.54mm
+PinHeader_1x22_P2.54mm_Vertical
+Through hole straight pin header, 1x22, 2.54mm pitch, single row
+Through hole pin header THT 1x22 2.54mm single row
+0
+22
+22
+Connector_PinHeader_2.54mm
+PinHeader_1x22_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x22, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x22 2.54mm single row style1 pin1 left
+0
+22
+22
+Connector_PinHeader_2.54mm
+PinHeader_1x22_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x22, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x22 2.54mm single row style2 pin1 right
+0
+22
+22
+Connector_PinHeader_2.54mm
+PinHeader_1x23_P2.54mm_Horizontal
+Through hole angled pin header, 1x23, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x23 2.54mm single row
+0
+23
+23
+Connector_PinHeader_2.54mm
+PinHeader_1x23_P2.54mm_Vertical
+Through hole straight pin header, 1x23, 2.54mm pitch, single row
+Through hole pin header THT 1x23 2.54mm single row
+0
+23
+23
+Connector_PinHeader_2.54mm
+PinHeader_1x23_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x23, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x23 2.54mm single row style1 pin1 left
+0
+23
+23
+Connector_PinHeader_2.54mm
+PinHeader_1x23_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x23, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x23 2.54mm single row style2 pin1 right
+0
+23
+23
+Connector_PinHeader_2.54mm
+PinHeader_1x24_P2.54mm_Horizontal
+Through hole angled pin header, 1x24, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x24 2.54mm single row
+0
+24
+24
+Connector_PinHeader_2.54mm
+PinHeader_1x24_P2.54mm_Vertical
+Through hole straight pin header, 1x24, 2.54mm pitch, single row
+Through hole pin header THT 1x24 2.54mm single row
+0
+24
+24
+Connector_PinHeader_2.54mm
+PinHeader_1x24_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x24, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x24 2.54mm single row style1 pin1 left
+0
+24
+24
+Connector_PinHeader_2.54mm
+PinHeader_1x24_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x24, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x24 2.54mm single row style2 pin1 right
+0
+24
+24
+Connector_PinHeader_2.54mm
+PinHeader_1x25_P2.54mm_Horizontal
+Through hole angled pin header, 1x25, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x25 2.54mm single row
+0
+25
+25
+Connector_PinHeader_2.54mm
+PinHeader_1x25_P2.54mm_Vertical
+Through hole straight pin header, 1x25, 2.54mm pitch, single row
+Through hole pin header THT 1x25 2.54mm single row
+0
+25
+25
+Connector_PinHeader_2.54mm
+PinHeader_1x25_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x25, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x25 2.54mm single row style1 pin1 left
+0
+25
+25
+Connector_PinHeader_2.54mm
+PinHeader_1x25_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x25, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x25 2.54mm single row style2 pin1 right
+0
+25
+25
+Connector_PinHeader_2.54mm
+PinHeader_1x26_P2.54mm_Horizontal
+Through hole angled pin header, 1x26, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x26 2.54mm single row
+0
+26
+26
+Connector_PinHeader_2.54mm
+PinHeader_1x26_P2.54mm_Vertical
+Through hole straight pin header, 1x26, 2.54mm pitch, single row
+Through hole pin header THT 1x26 2.54mm single row
+0
+26
+26
+Connector_PinHeader_2.54mm
+PinHeader_1x26_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x26, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x26 2.54mm single row style1 pin1 left
+0
+26
+26
+Connector_PinHeader_2.54mm
+PinHeader_1x26_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x26, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x26 2.54mm single row style2 pin1 right
+0
+26
+26
+Connector_PinHeader_2.54mm
+PinHeader_1x27_P2.54mm_Horizontal
+Through hole angled pin header, 1x27, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x27 2.54mm single row
+0
+27
+27
+Connector_PinHeader_2.54mm
+PinHeader_1x27_P2.54mm_Vertical
+Through hole straight pin header, 1x27, 2.54mm pitch, single row
+Through hole pin header THT 1x27 2.54mm single row
+0
+27
+27
+Connector_PinHeader_2.54mm
+PinHeader_1x27_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x27, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x27 2.54mm single row style1 pin1 left
+0
+27
+27
+Connector_PinHeader_2.54mm
+PinHeader_1x27_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x27, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x27 2.54mm single row style2 pin1 right
+0
+27
+27
+Connector_PinHeader_2.54mm
+PinHeader_1x28_P2.54mm_Horizontal
+Through hole angled pin header, 1x28, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x28 2.54mm single row
+0
+28
+28
+Connector_PinHeader_2.54mm
+PinHeader_1x28_P2.54mm_Vertical
+Through hole straight pin header, 1x28, 2.54mm pitch, single row
+Through hole pin header THT 1x28 2.54mm single row
+0
+28
+28
+Connector_PinHeader_2.54mm
+PinHeader_1x28_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x28, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x28 2.54mm single row style1 pin1 left
+0
+28
+28
+Connector_PinHeader_2.54mm
+PinHeader_1x28_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x28, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x28 2.54mm single row style2 pin1 right
+0
+28
+28
+Connector_PinHeader_2.54mm
+PinHeader_1x29_P2.54mm_Horizontal
+Through hole angled pin header, 1x29, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x29 2.54mm single row
+0
+29
+29
+Connector_PinHeader_2.54mm
+PinHeader_1x29_P2.54mm_Vertical
+Through hole straight pin header, 1x29, 2.54mm pitch, single row
+Through hole pin header THT 1x29 2.54mm single row
+0
+29
+29
+Connector_PinHeader_2.54mm
+PinHeader_1x29_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x29, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x29 2.54mm single row style1 pin1 left
+0
+29
+29
+Connector_PinHeader_2.54mm
+PinHeader_1x29_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x29, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x29 2.54mm single row style2 pin1 right
+0
+29
+29
+Connector_PinHeader_2.54mm
+PinHeader_1x30_P2.54mm_Horizontal
+Through hole angled pin header, 1x30, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x30 2.54mm single row
+0
+30
+30
+Connector_PinHeader_2.54mm
+PinHeader_1x30_P2.54mm_Vertical
+Through hole straight pin header, 1x30, 2.54mm pitch, single row
+Through hole pin header THT 1x30 2.54mm single row
+0
+30
+30
+Connector_PinHeader_2.54mm
+PinHeader_1x30_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x30, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x30 2.54mm single row style1 pin1 left
+0
+30
+30
+Connector_PinHeader_2.54mm
+PinHeader_1x30_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x30, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x30 2.54mm single row style2 pin1 right
+0
+30
+30
+Connector_PinHeader_2.54mm
+PinHeader_1x31_P2.54mm_Horizontal
+Through hole angled pin header, 1x31, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x31 2.54mm single row
+0
+31
+31
+Connector_PinHeader_2.54mm
+PinHeader_1x31_P2.54mm_Vertical
+Through hole straight pin header, 1x31, 2.54mm pitch, single row
+Through hole pin header THT 1x31 2.54mm single row
+0
+31
+31
+Connector_PinHeader_2.54mm
+PinHeader_1x31_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x31, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x31 2.54mm single row style1 pin1 left
+0
+31
+31
+Connector_PinHeader_2.54mm
+PinHeader_1x31_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x31, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x31 2.54mm single row style2 pin1 right
+0
+31
+31
+Connector_PinHeader_2.54mm
+PinHeader_1x32_P2.54mm_Horizontal
+Through hole angled pin header, 1x32, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x32 2.54mm single row
+0
+32
+32
+Connector_PinHeader_2.54mm
+PinHeader_1x32_P2.54mm_Vertical
+Through hole straight pin header, 1x32, 2.54mm pitch, single row
+Through hole pin header THT 1x32 2.54mm single row
+0
+32
+32
+Connector_PinHeader_2.54mm
+PinHeader_1x32_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x32, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x32 2.54mm single row style1 pin1 left
+0
+32
+32
+Connector_PinHeader_2.54mm
+PinHeader_1x32_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x32, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x32 2.54mm single row style2 pin1 right
+0
+32
+32
+Connector_PinHeader_2.54mm
+PinHeader_1x33_P2.54mm_Horizontal
+Through hole angled pin header, 1x33, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x33 2.54mm single row
+0
+33
+33
+Connector_PinHeader_2.54mm
+PinHeader_1x33_P2.54mm_Vertical
+Through hole straight pin header, 1x33, 2.54mm pitch, single row
+Through hole pin header THT 1x33 2.54mm single row
+0
+33
+33
+Connector_PinHeader_2.54mm
+PinHeader_1x33_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x33, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x33 2.54mm single row style1 pin1 left
+0
+33
+33
+Connector_PinHeader_2.54mm
+PinHeader_1x33_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x33, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x33 2.54mm single row style2 pin1 right
+0
+33
+33
+Connector_PinHeader_2.54mm
+PinHeader_1x34_P2.54mm_Horizontal
+Through hole angled pin header, 1x34, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x34 2.54mm single row
+0
+34
+34
+Connector_PinHeader_2.54mm
+PinHeader_1x34_P2.54mm_Vertical
+Through hole straight pin header, 1x34, 2.54mm pitch, single row
+Through hole pin header THT 1x34 2.54mm single row
+0
+34
+34
+Connector_PinHeader_2.54mm
+PinHeader_1x34_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x34, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x34 2.54mm single row style1 pin1 left
+0
+34
+34
+Connector_PinHeader_2.54mm
+PinHeader_1x34_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x34, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x34 2.54mm single row style2 pin1 right
+0
+34
+34
+Connector_PinHeader_2.54mm
+PinHeader_1x35_P2.54mm_Horizontal
+Through hole angled pin header, 1x35, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x35 2.54mm single row
+0
+35
+35
+Connector_PinHeader_2.54mm
+PinHeader_1x35_P2.54mm_Vertical
+Through hole straight pin header, 1x35, 2.54mm pitch, single row
+Through hole pin header THT 1x35 2.54mm single row
+0
+35
+35
+Connector_PinHeader_2.54mm
+PinHeader_1x35_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x35, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x35 2.54mm single row style1 pin1 left
+0
+35
+35
+Connector_PinHeader_2.54mm
+PinHeader_1x35_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x35, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x35 2.54mm single row style2 pin1 right
+0
+35
+35
+Connector_PinHeader_2.54mm
+PinHeader_1x36_P2.54mm_Horizontal
+Through hole angled pin header, 1x36, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x36 2.54mm single row
+0
+36
+36
+Connector_PinHeader_2.54mm
+PinHeader_1x36_P2.54mm_Vertical
+Through hole straight pin header, 1x36, 2.54mm pitch, single row
+Through hole pin header THT 1x36 2.54mm single row
+0
+36
+36
+Connector_PinHeader_2.54mm
+PinHeader_1x36_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x36, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x36 2.54mm single row style1 pin1 left
+0
+36
+36
+Connector_PinHeader_2.54mm
+PinHeader_1x36_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x36, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x36 2.54mm single row style2 pin1 right
+0
+36
+36
+Connector_PinHeader_2.54mm
+PinHeader_1x37_P2.54mm_Horizontal
+Through hole angled pin header, 1x37, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x37 2.54mm single row
+0
+37
+37
+Connector_PinHeader_2.54mm
+PinHeader_1x37_P2.54mm_Vertical
+Through hole straight pin header, 1x37, 2.54mm pitch, single row
+Through hole pin header THT 1x37 2.54mm single row
+0
+37
+37
+Connector_PinHeader_2.54mm
+PinHeader_1x37_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x37, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x37 2.54mm single row style1 pin1 left
+0
+37
+37
+Connector_PinHeader_2.54mm
+PinHeader_1x37_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x37, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x37 2.54mm single row style2 pin1 right
+0
+37
+37
+Connector_PinHeader_2.54mm
+PinHeader_1x38_P2.54mm_Horizontal
+Through hole angled pin header, 1x38, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x38 2.54mm single row
+0
+38
+38
+Connector_PinHeader_2.54mm
+PinHeader_1x38_P2.54mm_Vertical
+Through hole straight pin header, 1x38, 2.54mm pitch, single row
+Through hole pin header THT 1x38 2.54mm single row
+0
+38
+38
+Connector_PinHeader_2.54mm
+PinHeader_1x38_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x38, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x38 2.54mm single row style1 pin1 left
+0
+38
+38
+Connector_PinHeader_2.54mm
+PinHeader_1x38_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x38, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x38 2.54mm single row style2 pin1 right
+0
+38
+38
+Connector_PinHeader_2.54mm
+PinHeader_1x39_P2.54mm_Horizontal
+Through hole angled pin header, 1x39, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x39 2.54mm single row
+0
+39
+39
+Connector_PinHeader_2.54mm
+PinHeader_1x39_P2.54mm_Vertical
+Through hole straight pin header, 1x39, 2.54mm pitch, single row
+Through hole pin header THT 1x39 2.54mm single row
+0
+39
+39
+Connector_PinHeader_2.54mm
+PinHeader_1x39_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x39, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x39 2.54mm single row style1 pin1 left
+0
+39
+39
+Connector_PinHeader_2.54mm
+PinHeader_1x39_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x39, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x39 2.54mm single row style2 pin1 right
+0
+39
+39
+Connector_PinHeader_2.54mm
+PinHeader_1x40_P2.54mm_Horizontal
+Through hole angled pin header, 1x40, 2.54mm pitch, 6mm pin length, single row
+Through hole angled pin header THT 1x40 2.54mm single row
+0
+40
+40
+Connector_PinHeader_2.54mm
+PinHeader_1x40_P2.54mm_Vertical
+Through hole straight pin header, 1x40, 2.54mm pitch, single row
+Through hole pin header THT 1x40 2.54mm single row
+0
+40
+40
+Connector_PinHeader_2.54mm
+PinHeader_1x40_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight pin header, 1x40, 2.54mm pitch, single row, style 1 (pin 1 left)
+Surface mounted pin header SMD 1x40 2.54mm single row style1 pin1 left
+0
+40
+40
+Connector_PinHeader_2.54mm
+PinHeader_1x40_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight pin header, 1x40, 2.54mm pitch, single row, style 2 (pin 1 right)
+Surface mounted pin header SMD 1x40 2.54mm single row style2 pin1 right
+0
+40
+40
+Connector_PinHeader_2.54mm
+PinHeader_2x01_P2.54mm_Horizontal
+Through hole angled pin header, 2x01, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x01 2.54mm double row
+0
+2
+2
+Connector_PinHeader_2.54mm
+PinHeader_2x01_P2.54mm_Vertical
+Through hole straight pin header, 2x01, 2.54mm pitch, double rows
+Through hole pin header THT 2x01 2.54mm double row
+0
+2
+2
+Connector_PinHeader_2.54mm
+PinHeader_2x01_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x01, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x01 2.54mm double row
+0
+2
+2
+Connector_PinHeader_2.54mm
+PinHeader_2x02_P2.54mm_Horizontal
+Through hole angled pin header, 2x02, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x02 2.54mm double row
+0
+4
+4
+Connector_PinHeader_2.54mm
+PinHeader_2x02_P2.54mm_Vertical
+Through hole straight pin header, 2x02, 2.54mm pitch, double rows
+Through hole pin header THT 2x02 2.54mm double row
+0
+4
+4
+Connector_PinHeader_2.54mm
+PinHeader_2x02_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x02, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x02 2.54mm double row
+0
+4
+4
+Connector_PinHeader_2.54mm
+PinHeader_2x03_P2.54mm_Horizontal
+Through hole angled pin header, 2x03, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x03 2.54mm double row
+0
+6
+6
+Connector_PinHeader_2.54mm
+PinHeader_2x03_P2.54mm_Vertical
+Through hole straight pin header, 2x03, 2.54mm pitch, double rows
+Through hole pin header THT 2x03 2.54mm double row
+0
+6
+6
+Connector_PinHeader_2.54mm
+PinHeader_2x03_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x03, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x03 2.54mm double row
+0
+6
+6
+Connector_PinHeader_2.54mm
+PinHeader_2x04_P2.54mm_Horizontal
+Through hole angled pin header, 2x04, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x04 2.54mm double row
+0
+8
+8
+Connector_PinHeader_2.54mm
+PinHeader_2x04_P2.54mm_Vertical
+Through hole straight pin header, 2x04, 2.54mm pitch, double rows
+Through hole pin header THT 2x04 2.54mm double row
+0
+8
+8
+Connector_PinHeader_2.54mm
+PinHeader_2x04_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x04, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x04 2.54mm double row
+0
+8
+8
+Connector_PinHeader_2.54mm
+PinHeader_2x05_P2.54mm_Horizontal
+Through hole angled pin header, 2x05, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x05 2.54mm double row
+0
+10
+10
+Connector_PinHeader_2.54mm
+PinHeader_2x05_P2.54mm_Vertical
+Through hole straight pin header, 2x05, 2.54mm pitch, double rows
+Through hole pin header THT 2x05 2.54mm double row
+0
+10
+10
+Connector_PinHeader_2.54mm
+PinHeader_2x05_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x05, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x05 2.54mm double row
+0
+10
+10
+Connector_PinHeader_2.54mm
+PinHeader_2x06_P2.54mm_Horizontal
+Through hole angled pin header, 2x06, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x06 2.54mm double row
+0
+12
+12
+Connector_PinHeader_2.54mm
+PinHeader_2x06_P2.54mm_Vertical
+Through hole straight pin header, 2x06, 2.54mm pitch, double rows
+Through hole pin header THT 2x06 2.54mm double row
+0
+12
+12
+Connector_PinHeader_2.54mm
+PinHeader_2x06_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x06, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x06 2.54mm double row
+0
+12
+12
+Connector_PinHeader_2.54mm
+PinHeader_2x07_P2.54mm_Horizontal
+Through hole angled pin header, 2x07, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x07 2.54mm double row
+0
+14
+14
+Connector_PinHeader_2.54mm
+PinHeader_2x07_P2.54mm_Vertical
+Through hole straight pin header, 2x07, 2.54mm pitch, double rows
+Through hole pin header THT 2x07 2.54mm double row
+0
+14
+14
+Connector_PinHeader_2.54mm
+PinHeader_2x07_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x07, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x07 2.54mm double row
+0
+14
+14
+Connector_PinHeader_2.54mm
+PinHeader_2x08_P2.54mm_Horizontal
+Through hole angled pin header, 2x08, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x08 2.54mm double row
+0
+16
+16
+Connector_PinHeader_2.54mm
+PinHeader_2x08_P2.54mm_Vertical
+Through hole straight pin header, 2x08, 2.54mm pitch, double rows
+Through hole pin header THT 2x08 2.54mm double row
+0
+16
+16
+Connector_PinHeader_2.54mm
+PinHeader_2x08_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x08, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x08 2.54mm double row
+0
+16
+16
+Connector_PinHeader_2.54mm
+PinHeader_2x09_P2.54mm_Horizontal
+Through hole angled pin header, 2x09, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x09 2.54mm double row
+0
+18
+18
+Connector_PinHeader_2.54mm
+PinHeader_2x09_P2.54mm_Vertical
+Through hole straight pin header, 2x09, 2.54mm pitch, double rows
+Through hole pin header THT 2x09 2.54mm double row
+0
+18
+18
+Connector_PinHeader_2.54mm
+PinHeader_2x09_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x09, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x09 2.54mm double row
+0
+18
+18
+Connector_PinHeader_2.54mm
+PinHeader_2x10_P2.54mm_Horizontal
+Through hole angled pin header, 2x10, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x10 2.54mm double row
+0
+20
+20
+Connector_PinHeader_2.54mm
+PinHeader_2x10_P2.54mm_Vertical
+Through hole straight pin header, 2x10, 2.54mm pitch, double rows
+Through hole pin header THT 2x10 2.54mm double row
+0
+20
+20
+Connector_PinHeader_2.54mm
+PinHeader_2x10_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x10, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x10 2.54mm double row
+0
+20
+20
+Connector_PinHeader_2.54mm
+PinHeader_2x11_P2.54mm_Horizontal
+Through hole angled pin header, 2x11, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x11 2.54mm double row
+0
+22
+22
+Connector_PinHeader_2.54mm
+PinHeader_2x11_P2.54mm_Vertical
+Through hole straight pin header, 2x11, 2.54mm pitch, double rows
+Through hole pin header THT 2x11 2.54mm double row
+0
+22
+22
+Connector_PinHeader_2.54mm
+PinHeader_2x11_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x11, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x11 2.54mm double row
+0
+22
+22
+Connector_PinHeader_2.54mm
+PinHeader_2x12_P2.54mm_Horizontal
+Through hole angled pin header, 2x12, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x12 2.54mm double row
+0
+24
+24
+Connector_PinHeader_2.54mm
+PinHeader_2x12_P2.54mm_Vertical
+Through hole straight pin header, 2x12, 2.54mm pitch, double rows
+Through hole pin header THT 2x12 2.54mm double row
+0
+24
+24
+Connector_PinHeader_2.54mm
+PinHeader_2x12_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x12, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x12 2.54mm double row
+0
+24
+24
+Connector_PinHeader_2.54mm
+PinHeader_2x13_P2.54mm_Horizontal
+Through hole angled pin header, 2x13, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x13 2.54mm double row
+0
+26
+26
+Connector_PinHeader_2.54mm
+PinHeader_2x13_P2.54mm_Vertical
+Through hole straight pin header, 2x13, 2.54mm pitch, double rows
+Through hole pin header THT 2x13 2.54mm double row
+0
+26
+26
+Connector_PinHeader_2.54mm
+PinHeader_2x13_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x13, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x13 2.54mm double row
+0
+26
+26
+Connector_PinHeader_2.54mm
+PinHeader_2x14_P2.54mm_Horizontal
+Through hole angled pin header, 2x14, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x14 2.54mm double row
+0
+28
+28
+Connector_PinHeader_2.54mm
+PinHeader_2x14_P2.54mm_Vertical
+Through hole straight pin header, 2x14, 2.54mm pitch, double rows
+Through hole pin header THT 2x14 2.54mm double row
+0
+28
+28
+Connector_PinHeader_2.54mm
+PinHeader_2x14_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x14, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x14 2.54mm double row
+0
+28
+28
+Connector_PinHeader_2.54mm
+PinHeader_2x15_P2.54mm_Horizontal
+Through hole angled pin header, 2x15, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x15 2.54mm double row
+0
+30
+30
+Connector_PinHeader_2.54mm
+PinHeader_2x15_P2.54mm_Vertical
+Through hole straight pin header, 2x15, 2.54mm pitch, double rows
+Through hole pin header THT 2x15 2.54mm double row
+0
+30
+30
+Connector_PinHeader_2.54mm
+PinHeader_2x15_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x15, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x15 2.54mm double row
+0
+30
+30
+Connector_PinHeader_2.54mm
+PinHeader_2x16_P2.54mm_Horizontal
+Through hole angled pin header, 2x16, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x16 2.54mm double row
+0
+32
+32
+Connector_PinHeader_2.54mm
+PinHeader_2x16_P2.54mm_Vertical
+Through hole straight pin header, 2x16, 2.54mm pitch, double rows
+Through hole pin header THT 2x16 2.54mm double row
+0
+32
+32
+Connector_PinHeader_2.54mm
+PinHeader_2x16_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x16, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x16 2.54mm double row
+0
+32
+32
+Connector_PinHeader_2.54mm
+PinHeader_2x17_P2.54mm_Horizontal
+Through hole angled pin header, 2x17, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x17 2.54mm double row
+0
+34
+34
+Connector_PinHeader_2.54mm
+PinHeader_2x17_P2.54mm_Vertical
+Through hole straight pin header, 2x17, 2.54mm pitch, double rows
+Through hole pin header THT 2x17 2.54mm double row
+0
+34
+34
+Connector_PinHeader_2.54mm
+PinHeader_2x17_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x17, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x17 2.54mm double row
+0
+34
+34
+Connector_PinHeader_2.54mm
+PinHeader_2x18_P2.54mm_Horizontal
+Through hole angled pin header, 2x18, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x18 2.54mm double row
+0
+36
+36
+Connector_PinHeader_2.54mm
+PinHeader_2x18_P2.54mm_Vertical
+Through hole straight pin header, 2x18, 2.54mm pitch, double rows
+Through hole pin header THT 2x18 2.54mm double row
+0
+36
+36
+Connector_PinHeader_2.54mm
+PinHeader_2x18_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x18, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x18 2.54mm double row
+0
+36
+36
+Connector_PinHeader_2.54mm
+PinHeader_2x19_P2.54mm_Horizontal
+Through hole angled pin header, 2x19, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x19 2.54mm double row
+0
+38
+38
+Connector_PinHeader_2.54mm
+PinHeader_2x19_P2.54mm_Vertical
+Through hole straight pin header, 2x19, 2.54mm pitch, double rows
+Through hole pin header THT 2x19 2.54mm double row
+0
+38
+38
+Connector_PinHeader_2.54mm
+PinHeader_2x19_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x19, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x19 2.54mm double row
+0
+38
+38
+Connector_PinHeader_2.54mm
+PinHeader_2x20_P2.54mm_Horizontal
+Through hole angled pin header, 2x20, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x20 2.54mm double row
+0
+40
+40
+Connector_PinHeader_2.54mm
+PinHeader_2x20_P2.54mm_Vertical
+Through hole straight pin header, 2x20, 2.54mm pitch, double rows
+Through hole pin header THT 2x20 2.54mm double row
+0
+40
+40
+Connector_PinHeader_2.54mm
+PinHeader_2x20_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x20, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x20 2.54mm double row
+0
+40
+40
+Connector_PinHeader_2.54mm
+PinHeader_2x21_P2.54mm_Horizontal
+Through hole angled pin header, 2x21, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x21 2.54mm double row
+0
+42
+42
+Connector_PinHeader_2.54mm
+PinHeader_2x21_P2.54mm_Vertical
+Through hole straight pin header, 2x21, 2.54mm pitch, double rows
+Through hole pin header THT 2x21 2.54mm double row
+0
+42
+42
+Connector_PinHeader_2.54mm
+PinHeader_2x21_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x21, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x21 2.54mm double row
+0
+42
+42
+Connector_PinHeader_2.54mm
+PinHeader_2x22_P2.54mm_Horizontal
+Through hole angled pin header, 2x22, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x22 2.54mm double row
+0
+44
+44
+Connector_PinHeader_2.54mm
+PinHeader_2x22_P2.54mm_Vertical
+Through hole straight pin header, 2x22, 2.54mm pitch, double rows
+Through hole pin header THT 2x22 2.54mm double row
+0
+44
+44
+Connector_PinHeader_2.54mm
+PinHeader_2x22_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x22, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x22 2.54mm double row
+0
+44
+44
+Connector_PinHeader_2.54mm
+PinHeader_2x23_P2.54mm_Horizontal
+Through hole angled pin header, 2x23, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x23 2.54mm double row
+0
+46
+46
+Connector_PinHeader_2.54mm
+PinHeader_2x23_P2.54mm_Vertical
+Through hole straight pin header, 2x23, 2.54mm pitch, double rows
+Through hole pin header THT 2x23 2.54mm double row
+0
+46
+46
+Connector_PinHeader_2.54mm
+PinHeader_2x23_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x23, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x23 2.54mm double row
+0
+46
+46
+Connector_PinHeader_2.54mm
+PinHeader_2x24_P2.54mm_Horizontal
+Through hole angled pin header, 2x24, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x24 2.54mm double row
+0
+48
+48
+Connector_PinHeader_2.54mm
+PinHeader_2x24_P2.54mm_Vertical
+Through hole straight pin header, 2x24, 2.54mm pitch, double rows
+Through hole pin header THT 2x24 2.54mm double row
+0
+48
+48
+Connector_PinHeader_2.54mm
+PinHeader_2x24_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x24, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x24 2.54mm double row
+0
+48
+48
+Connector_PinHeader_2.54mm
+PinHeader_2x25_P2.54mm_Horizontal
+Through hole angled pin header, 2x25, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x25 2.54mm double row
+0
+50
+50
+Connector_PinHeader_2.54mm
+PinHeader_2x25_P2.54mm_Vertical
+Through hole straight pin header, 2x25, 2.54mm pitch, double rows
+Through hole pin header THT 2x25 2.54mm double row
+0
+50
+50
+Connector_PinHeader_2.54mm
+PinHeader_2x25_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x25, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x25 2.54mm double row
+0
+50
+50
+Connector_PinHeader_2.54mm
+PinHeader_2x26_P2.54mm_Horizontal
+Through hole angled pin header, 2x26, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x26 2.54mm double row
+0
+52
+52
+Connector_PinHeader_2.54mm
+PinHeader_2x26_P2.54mm_Vertical
+Through hole straight pin header, 2x26, 2.54mm pitch, double rows
+Through hole pin header THT 2x26 2.54mm double row
+0
+52
+52
+Connector_PinHeader_2.54mm
+PinHeader_2x26_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x26, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x26 2.54mm double row
+0
+52
+52
+Connector_PinHeader_2.54mm
+PinHeader_2x27_P2.54mm_Horizontal
+Through hole angled pin header, 2x27, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x27 2.54mm double row
+0
+54
+54
+Connector_PinHeader_2.54mm
+PinHeader_2x27_P2.54mm_Vertical
+Through hole straight pin header, 2x27, 2.54mm pitch, double rows
+Through hole pin header THT 2x27 2.54mm double row
+0
+54
+54
+Connector_PinHeader_2.54mm
+PinHeader_2x27_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x27, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x27 2.54mm double row
+0
+54
+54
+Connector_PinHeader_2.54mm
+PinHeader_2x28_P2.54mm_Horizontal
+Through hole angled pin header, 2x28, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x28 2.54mm double row
+0
+56
+56
+Connector_PinHeader_2.54mm
+PinHeader_2x28_P2.54mm_Vertical
+Through hole straight pin header, 2x28, 2.54mm pitch, double rows
+Through hole pin header THT 2x28 2.54mm double row
+0
+56
+56
+Connector_PinHeader_2.54mm
+PinHeader_2x28_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x28, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x28 2.54mm double row
+0
+56
+56
+Connector_PinHeader_2.54mm
+PinHeader_2x29_P2.54mm_Horizontal
+Through hole angled pin header, 2x29, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x29 2.54mm double row
+0
+58
+58
+Connector_PinHeader_2.54mm
+PinHeader_2x29_P2.54mm_Vertical
+Through hole straight pin header, 2x29, 2.54mm pitch, double rows
+Through hole pin header THT 2x29 2.54mm double row
+0
+58
+58
+Connector_PinHeader_2.54mm
+PinHeader_2x29_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x29, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x29 2.54mm double row
+0
+58
+58
+Connector_PinHeader_2.54mm
+PinHeader_2x30_P2.54mm_Horizontal
+Through hole angled pin header, 2x30, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x30 2.54mm double row
+0
+60
+60
+Connector_PinHeader_2.54mm
+PinHeader_2x30_P2.54mm_Vertical
+Through hole straight pin header, 2x30, 2.54mm pitch, double rows
+Through hole pin header THT 2x30 2.54mm double row
+0
+60
+60
+Connector_PinHeader_2.54mm
+PinHeader_2x30_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x30, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x30 2.54mm double row
+0
+60
+60
+Connector_PinHeader_2.54mm
+PinHeader_2x31_P2.54mm_Horizontal
+Through hole angled pin header, 2x31, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x31 2.54mm double row
+0
+62
+62
+Connector_PinHeader_2.54mm
+PinHeader_2x31_P2.54mm_Vertical
+Through hole straight pin header, 2x31, 2.54mm pitch, double rows
+Through hole pin header THT 2x31 2.54mm double row
+0
+62
+62
+Connector_PinHeader_2.54mm
+PinHeader_2x31_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x31, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x31 2.54mm double row
+0
+62
+62
+Connector_PinHeader_2.54mm
+PinHeader_2x32_P2.54mm_Horizontal
+Through hole angled pin header, 2x32, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x32 2.54mm double row
+0
+64
+64
+Connector_PinHeader_2.54mm
+PinHeader_2x32_P2.54mm_Vertical
+Through hole straight pin header, 2x32, 2.54mm pitch, double rows
+Through hole pin header THT 2x32 2.54mm double row
+0
+64
+64
+Connector_PinHeader_2.54mm
+PinHeader_2x32_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x32, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x32 2.54mm double row
+0
+64
+64
+Connector_PinHeader_2.54mm
+PinHeader_2x33_P2.54mm_Horizontal
+Through hole angled pin header, 2x33, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x33 2.54mm double row
+0
+66
+66
+Connector_PinHeader_2.54mm
+PinHeader_2x33_P2.54mm_Vertical
+Through hole straight pin header, 2x33, 2.54mm pitch, double rows
+Through hole pin header THT 2x33 2.54mm double row
+0
+66
+66
+Connector_PinHeader_2.54mm
+PinHeader_2x33_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x33, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x33 2.54mm double row
+0
+66
+66
+Connector_PinHeader_2.54mm
+PinHeader_2x34_P2.54mm_Horizontal
+Through hole angled pin header, 2x34, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x34 2.54mm double row
+0
+68
+68
+Connector_PinHeader_2.54mm
+PinHeader_2x34_P2.54mm_Vertical
+Through hole straight pin header, 2x34, 2.54mm pitch, double rows
+Through hole pin header THT 2x34 2.54mm double row
+0
+68
+68
+Connector_PinHeader_2.54mm
+PinHeader_2x34_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x34, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x34 2.54mm double row
+0
+68
+68
+Connector_PinHeader_2.54mm
+PinHeader_2x35_P2.54mm_Horizontal
+Through hole angled pin header, 2x35, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x35 2.54mm double row
+0
+70
+70
+Connector_PinHeader_2.54mm
+PinHeader_2x35_P2.54mm_Vertical
+Through hole straight pin header, 2x35, 2.54mm pitch, double rows
+Through hole pin header THT 2x35 2.54mm double row
+0
+70
+70
+Connector_PinHeader_2.54mm
+PinHeader_2x35_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x35, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x35 2.54mm double row
+0
+70
+70
+Connector_PinHeader_2.54mm
+PinHeader_2x36_P2.54mm_Horizontal
+Through hole angled pin header, 2x36, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x36 2.54mm double row
+0
+72
+72
+Connector_PinHeader_2.54mm
+PinHeader_2x36_P2.54mm_Vertical
+Through hole straight pin header, 2x36, 2.54mm pitch, double rows
+Through hole pin header THT 2x36 2.54mm double row
+0
+72
+72
+Connector_PinHeader_2.54mm
+PinHeader_2x36_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x36, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x36 2.54mm double row
+0
+72
+72
+Connector_PinHeader_2.54mm
+PinHeader_2x37_P2.54mm_Horizontal
+Through hole angled pin header, 2x37, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x37 2.54mm double row
+0
+74
+74
+Connector_PinHeader_2.54mm
+PinHeader_2x37_P2.54mm_Vertical
+Through hole straight pin header, 2x37, 2.54mm pitch, double rows
+Through hole pin header THT 2x37 2.54mm double row
+0
+74
+74
+Connector_PinHeader_2.54mm
+PinHeader_2x37_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x37, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x37 2.54mm double row
+0
+74
+74
+Connector_PinHeader_2.54mm
+PinHeader_2x38_P2.54mm_Horizontal
+Through hole angled pin header, 2x38, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x38 2.54mm double row
+0
+76
+76
+Connector_PinHeader_2.54mm
+PinHeader_2x38_P2.54mm_Vertical
+Through hole straight pin header, 2x38, 2.54mm pitch, double rows
+Through hole pin header THT 2x38 2.54mm double row
+0
+76
+76
+Connector_PinHeader_2.54mm
+PinHeader_2x38_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x38, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x38 2.54mm double row
+0
+76
+76
+Connector_PinHeader_2.54mm
+PinHeader_2x39_P2.54mm_Horizontal
+Through hole angled pin header, 2x39, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x39 2.54mm double row
+0
+78
+78
+Connector_PinHeader_2.54mm
+PinHeader_2x39_P2.54mm_Vertical
+Through hole straight pin header, 2x39, 2.54mm pitch, double rows
+Through hole pin header THT 2x39 2.54mm double row
+0
+78
+78
+Connector_PinHeader_2.54mm
+PinHeader_2x39_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x39, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x39 2.54mm double row
+0
+78
+78
+Connector_PinHeader_2.54mm
+PinHeader_2x40_P2.54mm_Horizontal
+Through hole angled pin header, 2x40, 2.54mm pitch, 6mm pin length, double rows
+Through hole angled pin header THT 2x40 2.54mm double row
+0
+80
+80
+Connector_PinHeader_2.54mm
+PinHeader_2x40_P2.54mm_Vertical
+Through hole straight pin header, 2x40, 2.54mm pitch, double rows
+Through hole pin header THT 2x40 2.54mm double row
+0
+80
+80
+Connector_PinHeader_2.54mm
+PinHeader_2x40_P2.54mm_Vertical_SMD
+surface-mounted straight pin header, 2x40, 2.54mm pitch, double rows
+Surface mounted pin header SMD 2x40 2.54mm double row
+0
+80
+80
+Connector_PinSocket_1.00mm
+PinSocket_1x02_P1.00mm_Vertical
+Through hole straight socket strip, 1x02, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x02 1.00mm single row
+0
+2
+2
+Connector_PinSocket_1.00mm
+PinSocket_1x02_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x02, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x02 1.00mm single row style1 pin1 left
+0
+2
+2
+Connector_PinSocket_1.00mm
+PinSocket_1x02_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x02, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x02 1.00mm single row style2 pin1 right
+0
+2
+2
+Connector_PinSocket_1.00mm
+PinSocket_1x03_P1.00mm_Vertical
+Through hole straight socket strip, 1x03, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x03 1.00mm single row
+0
+3
+3
+Connector_PinSocket_1.00mm
+PinSocket_1x03_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x03, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x03 1.00mm single row style1 pin1 left
+0
+3
+3
+Connector_PinSocket_1.00mm
+PinSocket_1x03_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x03, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x03 1.00mm single row style2 pin1 right
+0
+3
+3
+Connector_PinSocket_1.00mm
+PinSocket_1x04_P1.00mm_Vertical
+Through hole straight socket strip, 1x04, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x04 1.00mm single row
+0
+4
+4
+Connector_PinSocket_1.00mm
+PinSocket_1x04_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x04, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x04 1.00mm single row style1 pin1 left
+0
+4
+4
+Connector_PinSocket_1.00mm
+PinSocket_1x04_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x04, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x04 1.00mm single row style2 pin1 right
+0
+4
+4
+Connector_PinSocket_1.00mm
+PinSocket_1x05_P1.00mm_Vertical
+Through hole straight socket strip, 1x05, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x05 1.00mm single row
+0
+5
+5
+Connector_PinSocket_1.00mm
+PinSocket_1x05_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x05, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x05 1.00mm single row style1 pin1 left
+0
+5
+5
+Connector_PinSocket_1.00mm
+PinSocket_1x05_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x05, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x05 1.00mm single row style2 pin1 right
+0
+5
+5
+Connector_PinSocket_1.00mm
+PinSocket_1x06_P1.00mm_Vertical
+Through hole straight socket strip, 1x06, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x06 1.00mm single row
+0
+6
+6
+Connector_PinSocket_1.00mm
+PinSocket_1x06_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x06, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x06 1.00mm single row style1 pin1 left
+0
+6
+6
+Connector_PinSocket_1.00mm
+PinSocket_1x06_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x06, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x06 1.00mm single row style2 pin1 right
+0
+6
+6
+Connector_PinSocket_1.00mm
+PinSocket_1x07_P1.00mm_Vertical
+Through hole straight socket strip, 1x07, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x07 1.00mm single row
+0
+7
+7
+Connector_PinSocket_1.00mm
+PinSocket_1x07_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x07, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x07 1.00mm single row style1 pin1 left
+0
+7
+7
+Connector_PinSocket_1.00mm
+PinSocket_1x07_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x07, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x07 1.00mm single row style2 pin1 right
+0
+7
+7
+Connector_PinSocket_1.00mm
+PinSocket_1x08_P1.00mm_Vertical
+Through hole straight socket strip, 1x08, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x08 1.00mm single row
+0
+8
+8
+Connector_PinSocket_1.00mm
+PinSocket_1x08_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x08, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x08 1.00mm single row style1 pin1 left
+0
+8
+8
+Connector_PinSocket_1.00mm
+PinSocket_1x08_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x08, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x08 1.00mm single row style2 pin1 right
+0
+8
+8
+Connector_PinSocket_1.00mm
+PinSocket_1x09_P1.00mm_Vertical
+Through hole straight socket strip, 1x09, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x09 1.00mm single row
+0
+9
+9
+Connector_PinSocket_1.00mm
+PinSocket_1x09_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x09, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x09 1.00mm single row style1 pin1 left
+0
+9
+9
+Connector_PinSocket_1.00mm
+PinSocket_1x09_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x09, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x09 1.00mm single row style2 pin1 right
+0
+9
+9
+Connector_PinSocket_1.00mm
+PinSocket_1x10_P1.00mm_Vertical
+Through hole straight socket strip, 1x10, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x10 1.00mm single row
+0
+10
+10
+Connector_PinSocket_1.00mm
+PinSocket_1x10_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x10, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x10 1.00mm single row style1 pin1 left
+0
+10
+10
+Connector_PinSocket_1.00mm
+PinSocket_1x10_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x10, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x10 1.00mm single row style2 pin1 right
+0
+10
+10
+Connector_PinSocket_1.00mm
+PinSocket_1x11_P1.00mm_Vertical
+Through hole straight socket strip, 1x11, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x11 1.00mm single row
+0
+11
+11
+Connector_PinSocket_1.00mm
+PinSocket_1x11_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x11, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x11 1.00mm single row style1 pin1 left
+0
+11
+11
+Connector_PinSocket_1.00mm
+PinSocket_1x11_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x11, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x11 1.00mm single row style2 pin1 right
+0
+11
+11
+Connector_PinSocket_1.00mm
+PinSocket_1x12_P1.00mm_Vertical
+Through hole straight socket strip, 1x12, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x12 1.00mm single row
+0
+12
+12
+Connector_PinSocket_1.00mm
+PinSocket_1x12_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x12, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x12 1.00mm single row style1 pin1 left
+0
+12
+12
+Connector_PinSocket_1.00mm
+PinSocket_1x12_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x12, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x12 1.00mm single row style2 pin1 right
+0
+12
+12
+Connector_PinSocket_1.00mm
+PinSocket_1x13_P1.00mm_Vertical
+Through hole straight socket strip, 1x13, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x13 1.00mm single row
+0
+13
+13
+Connector_PinSocket_1.00mm
+PinSocket_1x13_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x13, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x13 1.00mm single row style1 pin1 left
+0
+13
+13
+Connector_PinSocket_1.00mm
+PinSocket_1x13_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x13, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x13 1.00mm single row style2 pin1 right
+0
+13
+13
+Connector_PinSocket_1.00mm
+PinSocket_1x14_P1.00mm_Vertical
+Through hole straight socket strip, 1x14, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x14 1.00mm single row
+0
+14
+14
+Connector_PinSocket_1.00mm
+PinSocket_1x14_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x14, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x14 1.00mm single row style1 pin1 left
+0
+14
+14
+Connector_PinSocket_1.00mm
+PinSocket_1x14_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x14, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x14 1.00mm single row style2 pin1 right
+0
+14
+14
+Connector_PinSocket_1.00mm
+PinSocket_1x15_P1.00mm_Vertical
+Through hole straight socket strip, 1x15, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x15 1.00mm single row
+0
+15
+15
+Connector_PinSocket_1.00mm
+PinSocket_1x15_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x15, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x15 1.00mm single row style1 pin1 left
+0
+15
+15
+Connector_PinSocket_1.00mm
+PinSocket_1x15_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x15, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x15 1.00mm single row style2 pin1 right
+0
+15
+15
+Connector_PinSocket_1.00mm
+PinSocket_1x16_P1.00mm_Vertical
+Through hole straight socket strip, 1x16, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x16 1.00mm single row
+0
+16
+16
+Connector_PinSocket_1.00mm
+PinSocket_1x16_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x16, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x16 1.00mm single row style1 pin1 left
+0
+16
+16
+Connector_PinSocket_1.00mm
+PinSocket_1x16_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x16, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x16 1.00mm single row style2 pin1 right
+0
+16
+16
+Connector_PinSocket_1.00mm
+PinSocket_1x17_P1.00mm_Vertical
+Through hole straight socket strip, 1x17, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x17 1.00mm single row
+0
+17
+17
+Connector_PinSocket_1.00mm
+PinSocket_1x17_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x17, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x17 1.00mm single row style1 pin1 left
+0
+17
+17
+Connector_PinSocket_1.00mm
+PinSocket_1x17_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x17, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x17 1.00mm single row style2 pin1 right
+0
+17
+17
+Connector_PinSocket_1.00mm
+PinSocket_1x18_P1.00mm_Vertical
+Through hole straight socket strip, 1x18, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x18 1.00mm single row
+0
+18
+18
+Connector_PinSocket_1.00mm
+PinSocket_1x18_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x18, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x18 1.00mm single row style1 pin1 left
+0
+18
+18
+Connector_PinSocket_1.00mm
+PinSocket_1x18_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x18, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x18 1.00mm single row style2 pin1 right
+0
+18
+18
+Connector_PinSocket_1.00mm
+PinSocket_1x19_P1.00mm_Vertical
+Through hole straight socket strip, 1x19, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x19 1.00mm single row
+0
+19
+19
+Connector_PinSocket_1.00mm
+PinSocket_1x19_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x19, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x19 1.00mm single row style1 pin1 left
+0
+19
+19
+Connector_PinSocket_1.00mm
+PinSocket_1x19_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x19, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x19 1.00mm single row style2 pin1 right
+0
+19
+19
+Connector_PinSocket_1.00mm
+PinSocket_1x20_P1.00mm_Vertical
+Through hole straight socket strip, 1x20, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x20 1.00mm single row
+0
+20
+20
+Connector_PinSocket_1.00mm
+PinSocket_1x20_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x20, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x20 1.00mm single row style1 pin1 left
+0
+20
+20
+Connector_PinSocket_1.00mm
+PinSocket_1x20_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x20, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x20 1.00mm single row style2 pin1 right
+0
+20
+20
+Connector_PinSocket_1.00mm
+PinSocket_1x21_P1.00mm_Vertical
+Through hole straight socket strip, 1x21, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x21 1.00mm single row
+0
+21
+21
+Connector_PinSocket_1.00mm
+PinSocket_1x21_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x21, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x21 1.00mm single row style1 pin1 left
+0
+21
+21
+Connector_PinSocket_1.00mm
+PinSocket_1x21_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x21, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x21 1.00mm single row style2 pin1 right
+0
+21
+21
+Connector_PinSocket_1.00mm
+PinSocket_1x22_P1.00mm_Vertical
+Through hole straight socket strip, 1x22, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x22 1.00mm single row
+0
+22
+22
+Connector_PinSocket_1.00mm
+PinSocket_1x22_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x22, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x22 1.00mm single row style1 pin1 left
+0
+22
+22
+Connector_PinSocket_1.00mm
+PinSocket_1x22_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x22, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x22 1.00mm single row style2 pin1 right
+0
+22
+22
+Connector_PinSocket_1.00mm
+PinSocket_1x23_P1.00mm_Vertical
+Through hole straight socket strip, 1x23, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x23 1.00mm single row
+0
+23
+23
+Connector_PinSocket_1.00mm
+PinSocket_1x23_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x23, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x23 1.00mm single row style1 pin1 left
+0
+23
+23
+Connector_PinSocket_1.00mm
+PinSocket_1x23_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x23, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x23 1.00mm single row style2 pin1 right
+0
+23
+23
+Connector_PinSocket_1.00mm
+PinSocket_1x24_P1.00mm_Vertical
+Through hole straight socket strip, 1x24, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x24 1.00mm single row
+0
+24
+24
+Connector_PinSocket_1.00mm
+PinSocket_1x24_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x24, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x24 1.00mm single row style1 pin1 left
+0
+24
+24
+Connector_PinSocket_1.00mm
+PinSocket_1x24_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x24, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x24 1.00mm single row style2 pin1 right
+0
+24
+24
+Connector_PinSocket_1.00mm
+PinSocket_1x25_P1.00mm_Vertical
+Through hole straight socket strip, 1x25, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x25 1.00mm single row
+0
+25
+25
+Connector_PinSocket_1.00mm
+PinSocket_1x25_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x25, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x25 1.00mm single row style1 pin1 left
+0
+25
+25
+Connector_PinSocket_1.00mm
+PinSocket_1x25_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x25, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x25 1.00mm single row style2 pin1 right
+0
+25
+25
+Connector_PinSocket_1.00mm
+PinSocket_1x26_P1.00mm_Vertical
+Through hole straight socket strip, 1x26, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x26 1.00mm single row
+0
+26
+26
+Connector_PinSocket_1.00mm
+PinSocket_1x26_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x26, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x26 1.00mm single row style1 pin1 left
+0
+26
+26
+Connector_PinSocket_1.00mm
+PinSocket_1x26_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x26, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x26 1.00mm single row style2 pin1 right
+0
+26
+26
+Connector_PinSocket_1.00mm
+PinSocket_1x27_P1.00mm_Vertical
+Through hole straight socket strip, 1x27, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x27 1.00mm single row
+0
+27
+27
+Connector_PinSocket_1.00mm
+PinSocket_1x27_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x27, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x27 1.00mm single row style1 pin1 left
+0
+27
+27
+Connector_PinSocket_1.00mm
+PinSocket_1x27_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x27, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x27 1.00mm single row style2 pin1 right
+0
+27
+27
+Connector_PinSocket_1.00mm
+PinSocket_1x28_P1.00mm_Vertical
+Through hole straight socket strip, 1x28, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x28 1.00mm single row
+0
+28
+28
+Connector_PinSocket_1.00mm
+PinSocket_1x28_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x28, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x28 1.00mm single row style1 pin1 left
+0
+28
+28
+Connector_PinSocket_1.00mm
+PinSocket_1x28_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x28, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x28 1.00mm single row style2 pin1 right
+0
+28
+28
+Connector_PinSocket_1.00mm
+PinSocket_1x29_P1.00mm_Vertical
+Through hole straight socket strip, 1x29, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x29 1.00mm single row
+0
+29
+29
+Connector_PinSocket_1.00mm
+PinSocket_1x29_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x29, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x29 1.00mm single row style1 pin1 left
+0
+29
+29
+Connector_PinSocket_1.00mm
+PinSocket_1x29_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x29, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x29 1.00mm single row style2 pin1 right
+0
+29
+29
+Connector_PinSocket_1.00mm
+PinSocket_1x30_P1.00mm_Vertical
+Through hole straight socket strip, 1x30, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x30 1.00mm single row
+0
+30
+30
+Connector_PinSocket_1.00mm
+PinSocket_1x30_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x30, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x30 1.00mm single row style1 pin1 left
+0
+30
+30
+Connector_PinSocket_1.00mm
+PinSocket_1x30_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x30, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x30 1.00mm single row style2 pin1 right
+0
+30
+30
+Connector_PinSocket_1.00mm
+PinSocket_1x31_P1.00mm_Vertical
+Through hole straight socket strip, 1x31, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x31 1.00mm single row
+0
+31
+31
+Connector_PinSocket_1.00mm
+PinSocket_1x31_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x31, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x31 1.00mm single row style1 pin1 left
+0
+31
+31
+Connector_PinSocket_1.00mm
+PinSocket_1x31_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x31, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x31 1.00mm single row style2 pin1 right
+0
+31
+31
+Connector_PinSocket_1.00mm
+PinSocket_1x32_P1.00mm_Vertical
+Through hole straight socket strip, 1x32, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x32 1.00mm single row
+0
+32
+32
+Connector_PinSocket_1.00mm
+PinSocket_1x32_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x32, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x32 1.00mm single row style1 pin1 left
+0
+32
+32
+Connector_PinSocket_1.00mm
+PinSocket_1x32_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x32, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x32 1.00mm single row style2 pin1 right
+0
+32
+32
+Connector_PinSocket_1.00mm
+PinSocket_1x33_P1.00mm_Vertical
+Through hole straight socket strip, 1x33, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x33 1.00mm single row
+0
+33
+33
+Connector_PinSocket_1.00mm
+PinSocket_1x33_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x33, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x33 1.00mm single row style1 pin1 left
+0
+33
+33
+Connector_PinSocket_1.00mm
+PinSocket_1x33_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x33, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x33 1.00mm single row style2 pin1 right
+0
+33
+33
+Connector_PinSocket_1.00mm
+PinSocket_1x34_P1.00mm_Vertical
+Through hole straight socket strip, 1x34, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x34 1.00mm single row
+0
+34
+34
+Connector_PinSocket_1.00mm
+PinSocket_1x34_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x34, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x34 1.00mm single row style1 pin1 left
+0
+34
+34
+Connector_PinSocket_1.00mm
+PinSocket_1x34_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x34, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x34 1.00mm single row style2 pin1 right
+0
+34
+34
+Connector_PinSocket_1.00mm
+PinSocket_1x35_P1.00mm_Vertical
+Through hole straight socket strip, 1x35, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x35 1.00mm single row
+0
+35
+35
+Connector_PinSocket_1.00mm
+PinSocket_1x35_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x35, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x35 1.00mm single row style1 pin1 left
+0
+35
+35
+Connector_PinSocket_1.00mm
+PinSocket_1x35_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x35, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x35 1.00mm single row style2 pin1 right
+0
+35
+35
+Connector_PinSocket_1.00mm
+PinSocket_1x36_P1.00mm_Vertical
+Through hole straight socket strip, 1x36, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x36 1.00mm single row
+0
+36
+36
+Connector_PinSocket_1.00mm
+PinSocket_1x36_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x36, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x36 1.00mm single row style1 pin1 left
+0
+36
+36
+Connector_PinSocket_1.00mm
+PinSocket_1x36_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x36, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x36 1.00mm single row style2 pin1 right
+0
+36
+36
+Connector_PinSocket_1.00mm
+PinSocket_1x37_P1.00mm_Vertical
+Through hole straight socket strip, 1x37, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x37 1.00mm single row
+0
+37
+37
+Connector_PinSocket_1.00mm
+PinSocket_1x37_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x37, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x37 1.00mm single row style1 pin1 left
+0
+37
+37
+Connector_PinSocket_1.00mm
+PinSocket_1x37_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x37, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x37 1.00mm single row style2 pin1 right
+0
+37
+37
+Connector_PinSocket_1.00mm
+PinSocket_1x38_P1.00mm_Vertical
+Through hole straight socket strip, 1x38, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x38 1.00mm single row
+0
+38
+38
+Connector_PinSocket_1.00mm
+PinSocket_1x38_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x38, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x38 1.00mm single row style1 pin1 left
+0
+38
+38
+Connector_PinSocket_1.00mm
+PinSocket_1x38_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x38, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x38 1.00mm single row style2 pin1 right
+0
+38
+38
+Connector_PinSocket_1.00mm
+PinSocket_1x39_P1.00mm_Vertical
+Through hole straight socket strip, 1x39, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x39 1.00mm single row
+0
+39
+39
+Connector_PinSocket_1.00mm
+PinSocket_1x39_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x39, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x39 1.00mm single row style1 pin1 left
+0
+39
+39
+Connector_PinSocket_1.00mm
+PinSocket_1x39_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x39, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x39 1.00mm single row style2 pin1 right
+0
+39
+39
+Connector_PinSocket_1.00mm
+PinSocket_1x40_P1.00mm_Vertical
+Through hole straight socket strip, 1x40, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated
+Through hole socket strip THT 1x40 1.00mm single row
+0
+40
+40
+Connector_PinSocket_1.00mm
+PinSocket_1x40_P1.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x40, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x40 1.00mm single row style1 pin1 left
+0
+40
+40
+Connector_PinSocket_1.00mm
+PinSocket_1x40_P1.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x40, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated
+Surface mounted socket strip SMD 1x40 1.00mm single row style2 pin1 right
+0
+40
+40
+Connector_PinSocket_1.00mm
+PinSocket_2x02_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x02, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x02 1.00mm double row
+0
+4
+4
+Connector_PinSocket_1.00mm
+PinSocket_2x03_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x03, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x03 1.00mm double row
+0
+6
+6
+Connector_PinSocket_1.00mm
+PinSocket_2x04_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x04, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x04 1.00mm double row
+0
+8
+8
+Connector_PinSocket_1.00mm
+PinSocket_2x05_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x05, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x05 1.00mm double row
+0
+10
+10
+Connector_PinSocket_1.00mm
+PinSocket_2x06_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x06, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x06 1.00mm double row
+0
+12
+12
+Connector_PinSocket_1.00mm
+PinSocket_2x07_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x07, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x07 1.00mm double row
+0
+14
+14
+Connector_PinSocket_1.00mm
+PinSocket_2x08_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x08, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x08 1.00mm double row
+0
+16
+16
+Connector_PinSocket_1.00mm
+PinSocket_2x09_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x09, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x09 1.00mm double row
+0
+18
+18
+Connector_PinSocket_1.00mm
+PinSocket_2x10_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x10, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x10 1.00mm double row
+0
+20
+20
+Connector_PinSocket_1.00mm
+PinSocket_2x11_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x11, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x11 1.00mm double row
+0
+22
+22
+Connector_PinSocket_1.00mm
+PinSocket_2x12_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x12, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x12 1.00mm double row
+0
+24
+24
+Connector_PinSocket_1.00mm
+PinSocket_2x13_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x13, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x13 1.00mm double row
+0
+26
+26
+Connector_PinSocket_1.00mm
+PinSocket_2x14_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x14, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x14 1.00mm double row
+0
+28
+28
+Connector_PinSocket_1.00mm
+PinSocket_2x15_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x15, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x15 1.00mm double row
+0
+30
+30
+Connector_PinSocket_1.00mm
+PinSocket_2x16_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x16, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x16 1.00mm double row
+0
+32
+32
+Connector_PinSocket_1.00mm
+PinSocket_2x17_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x17, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x17 1.00mm double row
+0
+34
+34
+Connector_PinSocket_1.00mm
+PinSocket_2x18_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x18, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x18 1.00mm double row
+0
+36
+36
+Connector_PinSocket_1.00mm
+PinSocket_2x19_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x19, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x19 1.00mm double row
+0
+38
+38
+Connector_PinSocket_1.00mm
+PinSocket_2x20_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x20, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x20 1.00mm double row
+0
+40
+40
+Connector_PinSocket_1.00mm
+PinSocket_2x21_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x21, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x21 1.00mm double row
+0
+42
+42
+Connector_PinSocket_1.00mm
+PinSocket_2x22_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x22, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x22 1.00mm double row
+0
+44
+44
+Connector_PinSocket_1.00mm
+PinSocket_2x23_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x23, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x23 1.00mm double row
+0
+46
+46
+Connector_PinSocket_1.00mm
+PinSocket_2x24_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x24, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x24 1.00mm double row
+0
+48
+48
+Connector_PinSocket_1.00mm
+PinSocket_2x25_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x25, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x25 1.00mm double row
+0
+50
+50
+Connector_PinSocket_1.00mm
+PinSocket_2x26_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x26, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x26 1.00mm double row
+0
+52
+52
+Connector_PinSocket_1.00mm
+PinSocket_2x27_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x27, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x27 1.00mm double row
+0
+54
+54
+Connector_PinSocket_1.00mm
+PinSocket_2x28_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x28, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x28 1.00mm double row
+0
+56
+56
+Connector_PinSocket_1.00mm
+PinSocket_2x29_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x29, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x29 1.00mm double row
+0
+58
+58
+Connector_PinSocket_1.00mm
+PinSocket_2x30_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x30, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x30 1.00mm double row
+0
+60
+60
+Connector_PinSocket_1.00mm
+PinSocket_2x31_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x31, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x31 1.00mm double row
+0
+62
+62
+Connector_PinSocket_1.00mm
+PinSocket_2x32_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x32, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x32 1.00mm double row
+0
+64
+64
+Connector_PinSocket_1.00mm
+PinSocket_2x33_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x33, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x33 1.00mm double row
+0
+66
+66
+Connector_PinSocket_1.00mm
+PinSocket_2x34_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x34, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x34 1.00mm double row
+0
+68
+68
+Connector_PinSocket_1.00mm
+PinSocket_2x35_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x35, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x35 1.00mm double row
+0
+70
+70
+Connector_PinSocket_1.00mm
+PinSocket_2x36_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x36, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x36 1.00mm double row
+0
+72
+72
+Connector_PinSocket_1.00mm
+PinSocket_2x37_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x37, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x37 1.00mm double row
+0
+74
+74
+Connector_PinSocket_1.00mm
+PinSocket_2x38_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x38, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x38 1.00mm double row
+0
+76
+76
+Connector_PinSocket_1.00mm
+PinSocket_2x39_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x39, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x39 1.00mm double row
+0
+78
+78
+Connector_PinSocket_1.00mm
+PinSocket_2x40_P1.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x40, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated
+Surface mounted socket strip SMD 2x40 1.00mm double row
+0
+80
+80
+Connector_PinSocket_1.27mm
+PinSocket_1x01_P1.27mm_Vertical
+Through hole straight socket strip, 1x01, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x01 1.27mm single row
+0
+1
+1
+Connector_PinSocket_1.27mm
+PinSocket_1x02_P1.27mm_Vertical
+Through hole straight socket strip, 1x02, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x02 1.27mm single row
+0
+2
+2
+Connector_PinSocket_1.27mm
+PinSocket_1x02_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x02, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x02 1.27mm single row style1 pin1 left
+0
+2
+2
+Connector_PinSocket_1.27mm
+PinSocket_1x02_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x02, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x02 1.27mm single row style2 pin1 right
+0
+2
+2
+Connector_PinSocket_1.27mm
+PinSocket_1x03_P1.27mm_Vertical
+Through hole straight socket strip, 1x03, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x03 1.27mm single row
+0
+3
+3
+Connector_PinSocket_1.27mm
+PinSocket_1x03_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x03, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x03 1.27mm single row style1 pin1 left
+0
+3
+3
+Connector_PinSocket_1.27mm
+PinSocket_1x03_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x03, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x03 1.27mm single row style2 pin1 right
+0
+3
+3
+Connector_PinSocket_1.27mm
+PinSocket_1x04_P1.27mm_Vertical
+Through hole straight socket strip, 1x04, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x04 1.27mm single row
+0
+4
+4
+Connector_PinSocket_1.27mm
+PinSocket_1x04_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x04, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x04 1.27mm single row style1 pin1 left
+0
+4
+4
+Connector_PinSocket_1.27mm
+PinSocket_1x04_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x04, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x04 1.27mm single row style2 pin1 right
+0
+4
+4
+Connector_PinSocket_1.27mm
+PinSocket_1x05_P1.27mm_Vertical
+Through hole straight socket strip, 1x05, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x05 1.27mm single row
+0
+5
+5
+Connector_PinSocket_1.27mm
+PinSocket_1x05_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x05, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x05 1.27mm single row style1 pin1 left
+0
+5
+5
+Connector_PinSocket_1.27mm
+PinSocket_1x05_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x05, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x05 1.27mm single row style2 pin1 right
+0
+5
+5
+Connector_PinSocket_1.27mm
+PinSocket_1x06_P1.27mm_Vertical
+Through hole straight socket strip, 1x06, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x06 1.27mm single row
+0
+6
+6
+Connector_PinSocket_1.27mm
+PinSocket_1x06_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x06, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x06 1.27mm single row style1 pin1 left
+0
+6
+6
+Connector_PinSocket_1.27mm
+PinSocket_1x06_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x06, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x06 1.27mm single row style2 pin1 right
+0
+6
+6
+Connector_PinSocket_1.27mm
+PinSocket_1x07_P1.27mm_Vertical
+Through hole straight socket strip, 1x07, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x07 1.27mm single row
+0
+7
+7
+Connector_PinSocket_1.27mm
+PinSocket_1x07_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x07, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x07 1.27mm single row style1 pin1 left
+0
+7
+7
+Connector_PinSocket_1.27mm
+PinSocket_1x07_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x07, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x07 1.27mm single row style2 pin1 right
+0
+7
+7
+Connector_PinSocket_1.27mm
+PinSocket_1x08_P1.27mm_Vertical
+Through hole straight socket strip, 1x08, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x08 1.27mm single row
+0
+8
+8
+Connector_PinSocket_1.27mm
+PinSocket_1x08_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x08, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x08 1.27mm single row style1 pin1 left
+0
+8
+8
+Connector_PinSocket_1.27mm
+PinSocket_1x08_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x08, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x08 1.27mm single row style2 pin1 right
+0
+8
+8
+Connector_PinSocket_1.27mm
+PinSocket_1x09_P1.27mm_Vertical
+Through hole straight socket strip, 1x09, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x09 1.27mm single row
+0
+9
+9
+Connector_PinSocket_1.27mm
+PinSocket_1x09_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x09, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x09 1.27mm single row style1 pin1 left
+0
+9
+9
+Connector_PinSocket_1.27mm
+PinSocket_1x09_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x09, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x09 1.27mm single row style2 pin1 right
+0
+9
+9
+Connector_PinSocket_1.27mm
+PinSocket_1x10_P1.27mm_Vertical
+Through hole straight socket strip, 1x10, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x10 1.27mm single row
+0
+10
+10
+Connector_PinSocket_1.27mm
+PinSocket_1x10_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x10, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x10 1.27mm single row style1 pin1 left
+0
+10
+10
+Connector_PinSocket_1.27mm
+PinSocket_1x10_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x10, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x10 1.27mm single row style2 pin1 right
+0
+10
+10
+Connector_PinSocket_1.27mm
+PinSocket_1x11_P1.27mm_Vertical
+Through hole straight socket strip, 1x11, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x11 1.27mm single row
+0
+11
+11
+Connector_PinSocket_1.27mm
+PinSocket_1x11_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x11, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x11 1.27mm single row style1 pin1 left
+0
+11
+11
+Connector_PinSocket_1.27mm
+PinSocket_1x11_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x11, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x11 1.27mm single row style2 pin1 right
+0
+11
+11
+Connector_PinSocket_1.27mm
+PinSocket_1x12_P1.27mm_Vertical
+Through hole straight socket strip, 1x12, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x12 1.27mm single row
+0
+12
+12
+Connector_PinSocket_1.27mm
+PinSocket_1x12_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x12, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x12 1.27mm single row style1 pin1 left
+0
+12
+12
+Connector_PinSocket_1.27mm
+PinSocket_1x12_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x12, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x12 1.27mm single row style2 pin1 right
+0
+12
+12
+Connector_PinSocket_1.27mm
+PinSocket_1x13_P1.27mm_Vertical
+Through hole straight socket strip, 1x13, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x13 1.27mm single row
+0
+13
+13
+Connector_PinSocket_1.27mm
+PinSocket_1x13_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x13, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x13 1.27mm single row style1 pin1 left
+0
+13
+13
+Connector_PinSocket_1.27mm
+PinSocket_1x13_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x13, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x13 1.27mm single row style2 pin1 right
+0
+13
+13
+Connector_PinSocket_1.27mm
+PinSocket_1x14_P1.27mm_Vertical
+Through hole straight socket strip, 1x14, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x14 1.27mm single row
+0
+14
+14
+Connector_PinSocket_1.27mm
+PinSocket_1x14_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x14, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x14 1.27mm single row style1 pin1 left
+0
+14
+14
+Connector_PinSocket_1.27mm
+PinSocket_1x14_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x14, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x14 1.27mm single row style2 pin1 right
+0
+14
+14
+Connector_PinSocket_1.27mm
+PinSocket_1x15_P1.27mm_Vertical
+Through hole straight socket strip, 1x15, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x15 1.27mm single row
+0
+15
+15
+Connector_PinSocket_1.27mm
+PinSocket_1x15_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x15, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x15 1.27mm single row style1 pin1 left
+0
+15
+15
+Connector_PinSocket_1.27mm
+PinSocket_1x15_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x15, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x15 1.27mm single row style2 pin1 right
+0
+15
+15
+Connector_PinSocket_1.27mm
+PinSocket_1x16_P1.27mm_Vertical
+Through hole straight socket strip, 1x16, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x16 1.27mm single row
+0
+16
+16
+Connector_PinSocket_1.27mm
+PinSocket_1x16_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x16, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x16 1.27mm single row style1 pin1 left
+0
+16
+16
+Connector_PinSocket_1.27mm
+PinSocket_1x16_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x16, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x16 1.27mm single row style2 pin1 right
+0
+16
+16
+Connector_PinSocket_1.27mm
+PinSocket_1x17_P1.27mm_Vertical
+Through hole straight socket strip, 1x17, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x17 1.27mm single row
+0
+17
+17
+Connector_PinSocket_1.27mm
+PinSocket_1x17_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x17, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x17 1.27mm single row style1 pin1 left
+0
+17
+17
+Connector_PinSocket_1.27mm
+PinSocket_1x17_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x17, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x17 1.27mm single row style2 pin1 right
+0
+17
+17
+Connector_PinSocket_1.27mm
+PinSocket_1x18_P1.27mm_Vertical
+Through hole straight socket strip, 1x18, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x18 1.27mm single row
+0
+18
+18
+Connector_PinSocket_1.27mm
+PinSocket_1x18_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x18, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x18 1.27mm single row style1 pin1 left
+0
+18
+18
+Connector_PinSocket_1.27mm
+PinSocket_1x18_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x18, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x18 1.27mm single row style2 pin1 right
+0
+18
+18
+Connector_PinSocket_1.27mm
+PinSocket_1x19_P1.27mm_Vertical
+Through hole straight socket strip, 1x19, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x19 1.27mm single row
+0
+19
+19
+Connector_PinSocket_1.27mm
+PinSocket_1x19_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x19, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x19 1.27mm single row style1 pin1 left
+0
+19
+19
+Connector_PinSocket_1.27mm
+PinSocket_1x19_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x19, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x19 1.27mm single row style2 pin1 right
+0
+19
+19
+Connector_PinSocket_1.27mm
+PinSocket_1x20_P1.27mm_Vertical
+Through hole straight socket strip, 1x20, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x20 1.27mm single row
+0
+20
+20
+Connector_PinSocket_1.27mm
+PinSocket_1x20_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x20, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x20 1.27mm single row style1 pin1 left
+0
+20
+20
+Connector_PinSocket_1.27mm
+PinSocket_1x20_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x20, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x20 1.27mm single row style2 pin1 right
+0
+20
+20
+Connector_PinSocket_1.27mm
+PinSocket_1x21_P1.27mm_Vertical
+Through hole straight socket strip, 1x21, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x21 1.27mm single row
+0
+21
+21
+Connector_PinSocket_1.27mm
+PinSocket_1x21_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x21, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x21 1.27mm single row style1 pin1 left
+0
+21
+21
+Connector_PinSocket_1.27mm
+PinSocket_1x21_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x21, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x21 1.27mm single row style2 pin1 right
+0
+21
+21
+Connector_PinSocket_1.27mm
+PinSocket_1x22_P1.27mm_Vertical
+Through hole straight socket strip, 1x22, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x22 1.27mm single row
+0
+22
+22
+Connector_PinSocket_1.27mm
+PinSocket_1x22_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x22, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x22 1.27mm single row style1 pin1 left
+0
+22
+22
+Connector_PinSocket_1.27mm
+PinSocket_1x22_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x22, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x22 1.27mm single row style2 pin1 right
+0
+22
+22
+Connector_PinSocket_1.27mm
+PinSocket_1x23_P1.27mm_Vertical
+Through hole straight socket strip, 1x23, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x23 1.27mm single row
+0
+23
+23
+Connector_PinSocket_1.27mm
+PinSocket_1x23_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x23, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x23 1.27mm single row style1 pin1 left
+0
+23
+23
+Connector_PinSocket_1.27mm
+PinSocket_1x23_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x23, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x23 1.27mm single row style2 pin1 right
+0
+23
+23
+Connector_PinSocket_1.27mm
+PinSocket_1x24_P1.27mm_Vertical
+Through hole straight socket strip, 1x24, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x24 1.27mm single row
+0
+24
+24
+Connector_PinSocket_1.27mm
+PinSocket_1x24_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x24, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x24 1.27mm single row style1 pin1 left
+0
+24
+24
+Connector_PinSocket_1.27mm
+PinSocket_1x24_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x24, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x24 1.27mm single row style2 pin1 right
+0
+24
+24
+Connector_PinSocket_1.27mm
+PinSocket_1x25_P1.27mm_Vertical
+Through hole straight socket strip, 1x25, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x25 1.27mm single row
+0
+25
+25
+Connector_PinSocket_1.27mm
+PinSocket_1x25_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x25, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x25 1.27mm single row style1 pin1 left
+0
+25
+25
+Connector_PinSocket_1.27mm
+PinSocket_1x25_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x25, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x25 1.27mm single row style2 pin1 right
+0
+25
+25
+Connector_PinSocket_1.27mm
+PinSocket_1x26_P1.27mm_Vertical
+Through hole straight socket strip, 1x26, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x26 1.27mm single row
+0
+26
+26
+Connector_PinSocket_1.27mm
+PinSocket_1x26_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x26, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x26 1.27mm single row style1 pin1 left
+0
+26
+26
+Connector_PinSocket_1.27mm
+PinSocket_1x26_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x26, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x26 1.27mm single row style2 pin1 right
+0
+26
+26
+Connector_PinSocket_1.27mm
+PinSocket_1x27_P1.27mm_Vertical
+Through hole straight socket strip, 1x27, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x27 1.27mm single row
+0
+27
+27
+Connector_PinSocket_1.27mm
+PinSocket_1x27_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x27, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x27 1.27mm single row style1 pin1 left
+0
+27
+27
+Connector_PinSocket_1.27mm
+PinSocket_1x27_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x27, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x27 1.27mm single row style2 pin1 right
+0
+27
+27
+Connector_PinSocket_1.27mm
+PinSocket_1x28_P1.27mm_Vertical
+Through hole straight socket strip, 1x28, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x28 1.27mm single row
+0
+28
+28
+Connector_PinSocket_1.27mm
+PinSocket_1x28_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x28, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x28 1.27mm single row style1 pin1 left
+0
+28
+28
+Connector_PinSocket_1.27mm
+PinSocket_1x28_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x28, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x28 1.27mm single row style2 pin1 right
+0
+28
+28
+Connector_PinSocket_1.27mm
+PinSocket_1x29_P1.27mm_Vertical
+Through hole straight socket strip, 1x29, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x29 1.27mm single row
+0
+29
+29
+Connector_PinSocket_1.27mm
+PinSocket_1x29_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x29, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x29 1.27mm single row style1 pin1 left
+0
+29
+29
+Connector_PinSocket_1.27mm
+PinSocket_1x29_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x29, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x29 1.27mm single row style2 pin1 right
+0
+29
+29
+Connector_PinSocket_1.27mm
+PinSocket_1x30_P1.27mm_Vertical
+Through hole straight socket strip, 1x30, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x30 1.27mm single row
+0
+30
+30
+Connector_PinSocket_1.27mm
+PinSocket_1x30_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x30, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x30 1.27mm single row style1 pin1 left
+0
+30
+30
+Connector_PinSocket_1.27mm
+PinSocket_1x30_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x30, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x30 1.27mm single row style2 pin1 right
+0
+30
+30
+Connector_PinSocket_1.27mm
+PinSocket_1x31_P1.27mm_Vertical
+Through hole straight socket strip, 1x31, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x31 1.27mm single row
+0
+31
+31
+Connector_PinSocket_1.27mm
+PinSocket_1x31_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x31, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x31 1.27mm single row style1 pin1 left
+0
+31
+31
+Connector_PinSocket_1.27mm
+PinSocket_1x31_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x31, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x31 1.27mm single row style2 pin1 right
+0
+31
+31
+Connector_PinSocket_1.27mm
+PinSocket_1x32_P1.27mm_Vertical
+Through hole straight socket strip, 1x32, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x32 1.27mm single row
+0
+32
+32
+Connector_PinSocket_1.27mm
+PinSocket_1x32_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x32, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x32 1.27mm single row style1 pin1 left
+0
+32
+32
+Connector_PinSocket_1.27mm
+PinSocket_1x32_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x32, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x32 1.27mm single row style2 pin1 right
+0
+32
+32
+Connector_PinSocket_1.27mm
+PinSocket_1x33_P1.27mm_Vertical
+Through hole straight socket strip, 1x33, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x33 1.27mm single row
+0
+33
+33
+Connector_PinSocket_1.27mm
+PinSocket_1x33_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x33, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x33 1.27mm single row style1 pin1 left
+0
+33
+33
+Connector_PinSocket_1.27mm
+PinSocket_1x33_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x33, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x33 1.27mm single row style2 pin1 right
+0
+33
+33
+Connector_PinSocket_1.27mm
+PinSocket_1x34_P1.27mm_Vertical
+Through hole straight socket strip, 1x34, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x34 1.27mm single row
+0
+34
+34
+Connector_PinSocket_1.27mm
+PinSocket_1x34_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x34, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x34 1.27mm single row style1 pin1 left
+0
+34
+34
+Connector_PinSocket_1.27mm
+PinSocket_1x34_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x34, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x34 1.27mm single row style2 pin1 right
+0
+34
+34
+Connector_PinSocket_1.27mm
+PinSocket_1x35_P1.27mm_Vertical
+Through hole straight socket strip, 1x35, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x35 1.27mm single row
+0
+35
+35
+Connector_PinSocket_1.27mm
+PinSocket_1x35_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x35, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x35 1.27mm single row style1 pin1 left
+0
+35
+35
+Connector_PinSocket_1.27mm
+PinSocket_1x35_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x35, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x35 1.27mm single row style2 pin1 right
+0
+35
+35
+Connector_PinSocket_1.27mm
+PinSocket_1x36_P1.27mm_Vertical
+Through hole straight socket strip, 1x36, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x36 1.27mm single row
+0
+36
+36
+Connector_PinSocket_1.27mm
+PinSocket_1x36_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x36, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x36 1.27mm single row style1 pin1 left
+0
+36
+36
+Connector_PinSocket_1.27mm
+PinSocket_1x36_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x36, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x36 1.27mm single row style2 pin1 right
+0
+36
+36
+Connector_PinSocket_1.27mm
+PinSocket_1x37_P1.27mm_Vertical
+Through hole straight socket strip, 1x37, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x37 1.27mm single row
+0
+37
+37
+Connector_PinSocket_1.27mm
+PinSocket_1x37_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x37, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x37 1.27mm single row style1 pin1 left
+0
+37
+37
+Connector_PinSocket_1.27mm
+PinSocket_1x37_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x37, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x37 1.27mm single row style2 pin1 right
+0
+37
+37
+Connector_PinSocket_1.27mm
+PinSocket_1x38_P1.27mm_Vertical
+Through hole straight socket strip, 1x38, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x38 1.27mm single row
+0
+38
+38
+Connector_PinSocket_1.27mm
+PinSocket_1x38_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x38, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x38 1.27mm single row style1 pin1 left
+0
+38
+38
+Connector_PinSocket_1.27mm
+PinSocket_1x38_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x38, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x38 1.27mm single row style2 pin1 right
+0
+38
+38
+Connector_PinSocket_1.27mm
+PinSocket_1x39_P1.27mm_Vertical
+Through hole straight socket strip, 1x39, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x39 1.27mm single row
+0
+39
+39
+Connector_PinSocket_1.27mm
+PinSocket_1x39_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x39, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x39 1.27mm single row style1 pin1 left
+0
+39
+39
+Connector_PinSocket_1.27mm
+PinSocket_1x39_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x39, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x39 1.27mm single row style2 pin1 right
+0
+39
+39
+Connector_PinSocket_1.27mm
+PinSocket_1x40_P1.27mm_Vertical
+Through hole straight socket strip, 1x40, 1.27mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x40 1.27mm single row
+0
+40
+40
+Connector_PinSocket_1.27mm
+PinSocket_1x40_P1.27mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x40, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x40 1.27mm single row style1 pin1 left
+0
+40
+40
+Connector_PinSocket_1.27mm
+PinSocket_1x40_P1.27mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x40, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated
+Surface mounted socket strip SMD 1x40 1.27mm single row style2 pin1 right
+0
+40
+40
+Connector_PinSocket_1.27mm
+PinSocket_2x01_P1.27mm_Vertical
+Through hole straight socket strip, 2x01, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x01 1.27mm double row
+0
+2
+2
+Connector_PinSocket_1.27mm
+PinSocket_2x01_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x01, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x01 1.27mm double row
+0
+2
+2
+Connector_PinSocket_1.27mm
+PinSocket_2x02_P1.27mm_Vertical
+Through hole straight socket strip, 2x02, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x02 1.27mm double row
+0
+4
+4
+Connector_PinSocket_1.27mm
+PinSocket_2x02_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x02, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x02 1.27mm double row
+0
+4
+4
+Connector_PinSocket_1.27mm
+PinSocket_2x03_P1.27mm_Horizontal
+Through hole angled socket strip, 2x03, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x03 1.27mm double row
+0
+6
+6
+Connector_PinSocket_1.27mm
+PinSocket_2x03_P1.27mm_Vertical
+Through hole straight socket strip, 2x03, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x03 1.27mm double row
+0
+6
+6
+Connector_PinSocket_1.27mm
+PinSocket_2x03_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x03, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x03 1.27mm double row
+0
+6
+6
+Connector_PinSocket_1.27mm
+PinSocket_2x04_P1.27mm_Horizontal
+Through hole angled socket strip, 2x04, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x04 1.27mm double row
+0
+8
+8
+Connector_PinSocket_1.27mm
+PinSocket_2x04_P1.27mm_Vertical
+Through hole straight socket strip, 2x04, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x04 1.27mm double row
+0
+8
+8
+Connector_PinSocket_1.27mm
+PinSocket_2x04_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x04, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x04 1.27mm double row
+0
+8
+8
+Connector_PinSocket_1.27mm
+PinSocket_2x05_P1.27mm_Horizontal
+Through hole angled socket strip, 2x05, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x05 1.27mm double row
+0
+10
+10
+Connector_PinSocket_1.27mm
+PinSocket_2x05_P1.27mm_Vertical
+Through hole straight socket strip, 2x05, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x05 1.27mm double row
+0
+10
+10
+Connector_PinSocket_1.27mm
+PinSocket_2x05_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x05, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x05 1.27mm double row
+0
+10
+10
+Connector_PinSocket_1.27mm
+PinSocket_2x06_P1.27mm_Horizontal
+Through hole angled socket strip, 2x06, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x06 1.27mm double row
+0
+12
+12
+Connector_PinSocket_1.27mm
+PinSocket_2x06_P1.27mm_Vertical
+Through hole straight socket strip, 2x06, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x06 1.27mm double row
+0
+12
+12
+Connector_PinSocket_1.27mm
+PinSocket_2x06_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x06, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x06 1.27mm double row
+0
+12
+12
+Connector_PinSocket_1.27mm
+PinSocket_2x07_P1.27mm_Horizontal
+Through hole angled socket strip, 2x07, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x07 1.27mm double row
+0
+14
+14
+Connector_PinSocket_1.27mm
+PinSocket_2x07_P1.27mm_Vertical
+Through hole straight socket strip, 2x07, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x07 1.27mm double row
+0
+14
+14
+Connector_PinSocket_1.27mm
+PinSocket_2x07_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x07, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x07 1.27mm double row
+0
+14
+14
+Connector_PinSocket_1.27mm
+PinSocket_2x08_P1.27mm_Horizontal
+Through hole angled socket strip, 2x08, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x08 1.27mm double row
+0
+16
+16
+Connector_PinSocket_1.27mm
+PinSocket_2x08_P1.27mm_Vertical
+Through hole straight socket strip, 2x08, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x08 1.27mm double row
+0
+16
+16
+Connector_PinSocket_1.27mm
+PinSocket_2x08_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x08, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x08 1.27mm double row
+0
+16
+16
+Connector_PinSocket_1.27mm
+PinSocket_2x09_P1.27mm_Horizontal
+Through hole angled socket strip, 2x09, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x09 1.27mm double row
+0
+18
+18
+Connector_PinSocket_1.27mm
+PinSocket_2x09_P1.27mm_Vertical
+Through hole straight socket strip, 2x09, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x09 1.27mm double row
+0
+18
+18
+Connector_PinSocket_1.27mm
+PinSocket_2x09_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x09, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x09 1.27mm double row
+0
+18
+18
+Connector_PinSocket_1.27mm
+PinSocket_2x10_P1.27mm_Horizontal
+Through hole angled socket strip, 2x10, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x10 1.27mm double row
+0
+20
+20
+Connector_PinSocket_1.27mm
+PinSocket_2x10_P1.27mm_Vertical
+Through hole straight socket strip, 2x10, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x10 1.27mm double row
+0
+20
+20
+Connector_PinSocket_1.27mm
+PinSocket_2x10_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x10, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x10 1.27mm double row
+0
+20
+20
+Connector_PinSocket_1.27mm
+PinSocket_2x11_P1.27mm_Horizontal
+Through hole angled socket strip, 2x11, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x11 1.27mm double row
+0
+22
+22
+Connector_PinSocket_1.27mm
+PinSocket_2x11_P1.27mm_Vertical
+Through hole straight socket strip, 2x11, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x11 1.27mm double row
+0
+22
+22
+Connector_PinSocket_1.27mm
+PinSocket_2x11_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x11, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x11 1.27mm double row
+0
+22
+22
+Connector_PinSocket_1.27mm
+PinSocket_2x12_P1.27mm_Horizontal
+Through hole angled socket strip, 2x12, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x12 1.27mm double row
+0
+24
+24
+Connector_PinSocket_1.27mm
+PinSocket_2x12_P1.27mm_Vertical
+Through hole straight socket strip, 2x12, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x12 1.27mm double row
+0
+24
+24
+Connector_PinSocket_1.27mm
+PinSocket_2x12_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x12, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x12 1.27mm double row
+0
+24
+24
+Connector_PinSocket_1.27mm
+PinSocket_2x13_P1.27mm_Horizontal
+Through hole angled socket strip, 2x13, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x13 1.27mm double row
+0
+26
+26
+Connector_PinSocket_1.27mm
+PinSocket_2x13_P1.27mm_Vertical
+Through hole straight socket strip, 2x13, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x13 1.27mm double row
+0
+26
+26
+Connector_PinSocket_1.27mm
+PinSocket_2x13_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x13, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x13 1.27mm double row
+0
+26
+26
+Connector_PinSocket_1.27mm
+PinSocket_2x14_P1.27mm_Horizontal
+Through hole angled socket strip, 2x14, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x14 1.27mm double row
+0
+28
+28
+Connector_PinSocket_1.27mm
+PinSocket_2x14_P1.27mm_Vertical
+Through hole straight socket strip, 2x14, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x14 1.27mm double row
+0
+28
+28
+Connector_PinSocket_1.27mm
+PinSocket_2x14_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x14, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x14 1.27mm double row
+0
+28
+28
+Connector_PinSocket_1.27mm
+PinSocket_2x15_P1.27mm_Horizontal
+Through hole angled socket strip, 2x15, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x15 1.27mm double row
+0
+30
+30
+Connector_PinSocket_1.27mm
+PinSocket_2x15_P1.27mm_Vertical
+Through hole straight socket strip, 2x15, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x15 1.27mm double row
+0
+30
+30
+Connector_PinSocket_1.27mm
+PinSocket_2x15_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x15, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x15 1.27mm double row
+0
+30
+30
+Connector_PinSocket_1.27mm
+PinSocket_2x16_P1.27mm_Horizontal
+Through hole angled socket strip, 2x16, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x16 1.27mm double row
+0
+32
+32
+Connector_PinSocket_1.27mm
+PinSocket_2x16_P1.27mm_Vertical
+Through hole straight socket strip, 2x16, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x16 1.27mm double row
+0
+32
+32
+Connector_PinSocket_1.27mm
+PinSocket_2x16_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x16, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x16 1.27mm double row
+0
+32
+32
+Connector_PinSocket_1.27mm
+PinSocket_2x17_P1.27mm_Horizontal
+Through hole angled socket strip, 2x17, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x17 1.27mm double row
+0
+34
+34
+Connector_PinSocket_1.27mm
+PinSocket_2x17_P1.27mm_Vertical
+Through hole straight socket strip, 2x17, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x17 1.27mm double row
+0
+34
+34
+Connector_PinSocket_1.27mm
+PinSocket_2x17_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x17, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x17 1.27mm double row
+0
+34
+34
+Connector_PinSocket_1.27mm
+PinSocket_2x18_P1.27mm_Horizontal
+Through hole angled socket strip, 2x18, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x18 1.27mm double row
+0
+36
+36
+Connector_PinSocket_1.27mm
+PinSocket_2x18_P1.27mm_Vertical
+Through hole straight socket strip, 2x18, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x18 1.27mm double row
+0
+36
+36
+Connector_PinSocket_1.27mm
+PinSocket_2x18_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x18, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x18 1.27mm double row
+0
+36
+36
+Connector_PinSocket_1.27mm
+PinSocket_2x19_P1.27mm_Horizontal
+Through hole angled socket strip, 2x19, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x19 1.27mm double row
+0
+38
+38
+Connector_PinSocket_1.27mm
+PinSocket_2x19_P1.27mm_Vertical
+Through hole straight socket strip, 2x19, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x19 1.27mm double row
+0
+38
+38
+Connector_PinSocket_1.27mm
+PinSocket_2x19_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x19, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x19 1.27mm double row
+0
+38
+38
+Connector_PinSocket_1.27mm
+PinSocket_2x20_P1.27mm_Horizontal
+Through hole angled socket strip, 2x20, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x20 1.27mm double row
+0
+40
+40
+Connector_PinSocket_1.27mm
+PinSocket_2x20_P1.27mm_Vertical
+Through hole straight socket strip, 2x20, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x20 1.27mm double row
+0
+40
+40
+Connector_PinSocket_1.27mm
+PinSocket_2x20_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x20, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x20 1.27mm double row
+0
+40
+40
+Connector_PinSocket_1.27mm
+PinSocket_2x21_P1.27mm_Horizontal
+Through hole angled socket strip, 2x21, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x21 1.27mm double row
+0
+42
+42
+Connector_PinSocket_1.27mm
+PinSocket_2x21_P1.27mm_Vertical
+Through hole straight socket strip, 2x21, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x21 1.27mm double row
+0
+42
+42
+Connector_PinSocket_1.27mm
+PinSocket_2x21_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x21, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x21 1.27mm double row
+0
+42
+42
+Connector_PinSocket_1.27mm
+PinSocket_2x22_P1.27mm_Horizontal
+Through hole angled socket strip, 2x22, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x22 1.27mm double row
+0
+44
+44
+Connector_PinSocket_1.27mm
+PinSocket_2x22_P1.27mm_Vertical
+Through hole straight socket strip, 2x22, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x22 1.27mm double row
+0
+44
+44
+Connector_PinSocket_1.27mm
+PinSocket_2x22_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x22, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x22 1.27mm double row
+0
+44
+44
+Connector_PinSocket_1.27mm
+PinSocket_2x23_P1.27mm_Horizontal
+Through hole angled socket strip, 2x23, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x23 1.27mm double row
+0
+46
+46
+Connector_PinSocket_1.27mm
+PinSocket_2x23_P1.27mm_Vertical
+Through hole straight socket strip, 2x23, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x23 1.27mm double row
+0
+46
+46
+Connector_PinSocket_1.27mm
+PinSocket_2x23_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x23, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x23 1.27mm double row
+0
+46
+46
+Connector_PinSocket_1.27mm
+PinSocket_2x24_P1.27mm_Horizontal
+Through hole angled socket strip, 2x24, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x24 1.27mm double row
+0
+48
+48
+Connector_PinSocket_1.27mm
+PinSocket_2x24_P1.27mm_Vertical
+Through hole straight socket strip, 2x24, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x24 1.27mm double row
+0
+48
+48
+Connector_PinSocket_1.27mm
+PinSocket_2x24_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x24, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x24 1.27mm double row
+0
+48
+48
+Connector_PinSocket_1.27mm
+PinSocket_2x25_P1.27mm_Horizontal
+Through hole angled socket strip, 2x25, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x25 1.27mm double row
+0
+50
+50
+Connector_PinSocket_1.27mm
+PinSocket_2x25_P1.27mm_Vertical
+Through hole straight socket strip, 2x25, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x25 1.27mm double row
+0
+50
+50
+Connector_PinSocket_1.27mm
+PinSocket_2x25_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x25, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x25 1.27mm double row
+0
+50
+50
+Connector_PinSocket_1.27mm
+PinSocket_2x26_P1.27mm_Horizontal
+Through hole angled socket strip, 2x26, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x26 1.27mm double row
+0
+52
+52
+Connector_PinSocket_1.27mm
+PinSocket_2x26_P1.27mm_Vertical
+Through hole straight socket strip, 2x26, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x26 1.27mm double row
+0
+52
+52
+Connector_PinSocket_1.27mm
+PinSocket_2x26_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x26, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x26 1.27mm double row
+0
+52
+52
+Connector_PinSocket_1.27mm
+PinSocket_2x27_P1.27mm_Horizontal
+Through hole angled socket strip, 2x27, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x27 1.27mm double row
+0
+54
+54
+Connector_PinSocket_1.27mm
+PinSocket_2x27_P1.27mm_Vertical
+Through hole straight socket strip, 2x27, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x27 1.27mm double row
+0
+54
+54
+Connector_PinSocket_1.27mm
+PinSocket_2x27_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x27, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x27 1.27mm double row
+0
+54
+54
+Connector_PinSocket_1.27mm
+PinSocket_2x28_P1.27mm_Horizontal
+Through hole angled socket strip, 2x28, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x28 1.27mm double row
+0
+56
+56
+Connector_PinSocket_1.27mm
+PinSocket_2x28_P1.27mm_Vertical
+Through hole straight socket strip, 2x28, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x28 1.27mm double row
+0
+56
+56
+Connector_PinSocket_1.27mm
+PinSocket_2x28_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x28, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x28 1.27mm double row
+0
+56
+56
+Connector_PinSocket_1.27mm
+PinSocket_2x29_P1.27mm_Horizontal
+Through hole angled socket strip, 2x29, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x29 1.27mm double row
+0
+58
+58
+Connector_PinSocket_1.27mm
+PinSocket_2x29_P1.27mm_Vertical
+Through hole straight socket strip, 2x29, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x29 1.27mm double row
+0
+58
+58
+Connector_PinSocket_1.27mm
+PinSocket_2x29_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x29, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x29 1.27mm double row
+0
+58
+58
+Connector_PinSocket_1.27mm
+PinSocket_2x30_P1.27mm_Horizontal
+Through hole angled socket strip, 2x30, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x30 1.27mm double row
+0
+60
+60
+Connector_PinSocket_1.27mm
+PinSocket_2x30_P1.27mm_Vertical
+Through hole straight socket strip, 2x30, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x30 1.27mm double row
+0
+60
+60
+Connector_PinSocket_1.27mm
+PinSocket_2x30_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x30, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x30 1.27mm double row
+0
+60
+60
+Connector_PinSocket_1.27mm
+PinSocket_2x31_P1.27mm_Horizontal
+Through hole angled socket strip, 2x31, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x31 1.27mm double row
+0
+62
+62
+Connector_PinSocket_1.27mm
+PinSocket_2x31_P1.27mm_Vertical
+Through hole straight socket strip, 2x31, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x31 1.27mm double row
+0
+62
+62
+Connector_PinSocket_1.27mm
+PinSocket_2x31_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x31, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x31 1.27mm double row
+0
+62
+62
+Connector_PinSocket_1.27mm
+PinSocket_2x32_P1.27mm_Horizontal
+Through hole angled socket strip, 2x32, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x32 1.27mm double row
+0
+64
+64
+Connector_PinSocket_1.27mm
+PinSocket_2x32_P1.27mm_Vertical
+Through hole straight socket strip, 2x32, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x32 1.27mm double row
+0
+64
+64
+Connector_PinSocket_1.27mm
+PinSocket_2x32_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x32, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x32 1.27mm double row
+0
+64
+64
+Connector_PinSocket_1.27mm
+PinSocket_2x33_P1.27mm_Horizontal
+Through hole angled socket strip, 2x33, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x33 1.27mm double row
+0
+66
+66
+Connector_PinSocket_1.27mm
+PinSocket_2x33_P1.27mm_Vertical
+Through hole straight socket strip, 2x33, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x33 1.27mm double row
+0
+66
+66
+Connector_PinSocket_1.27mm
+PinSocket_2x33_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x33, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x33 1.27mm double row
+0
+66
+66
+Connector_PinSocket_1.27mm
+PinSocket_2x34_P1.27mm_Horizontal
+Through hole angled socket strip, 2x34, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x34 1.27mm double row
+0
+68
+68
+Connector_PinSocket_1.27mm
+PinSocket_2x34_P1.27mm_Vertical
+Through hole straight socket strip, 2x34, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x34 1.27mm double row
+0
+68
+68
+Connector_PinSocket_1.27mm
+PinSocket_2x34_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x34, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x34 1.27mm double row
+0
+68
+68
+Connector_PinSocket_1.27mm
+PinSocket_2x35_P1.27mm_Horizontal
+Through hole angled socket strip, 2x35, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x35 1.27mm double row
+0
+70
+70
+Connector_PinSocket_1.27mm
+PinSocket_2x35_P1.27mm_Vertical
+Through hole straight socket strip, 2x35, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x35 1.27mm double row
+0
+70
+70
+Connector_PinSocket_1.27mm
+PinSocket_2x35_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x35, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x35 1.27mm double row
+0
+70
+70
+Connector_PinSocket_1.27mm
+PinSocket_2x36_P1.27mm_Horizontal
+Through hole angled socket strip, 2x36, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x36 1.27mm double row
+0
+72
+72
+Connector_PinSocket_1.27mm
+PinSocket_2x36_P1.27mm_Vertical
+Through hole straight socket strip, 2x36, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x36 1.27mm double row
+0
+72
+72
+Connector_PinSocket_1.27mm
+PinSocket_2x36_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x36, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x36 1.27mm double row
+0
+72
+72
+Connector_PinSocket_1.27mm
+PinSocket_2x37_P1.27mm_Horizontal
+Through hole angled socket strip, 2x37, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x37 1.27mm double row
+0
+74
+74
+Connector_PinSocket_1.27mm
+PinSocket_2x37_P1.27mm_Vertical
+Through hole straight socket strip, 2x37, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x37 1.27mm double row
+0
+74
+74
+Connector_PinSocket_1.27mm
+PinSocket_2x37_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x37, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x37 1.27mm double row
+0
+74
+74
+Connector_PinSocket_1.27mm
+PinSocket_2x38_P1.27mm_Horizontal
+Through hole angled socket strip, 2x38, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x38 1.27mm double row
+0
+76
+76
+Connector_PinSocket_1.27mm
+PinSocket_2x38_P1.27mm_Vertical
+Through hole straight socket strip, 2x38, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x38 1.27mm double row
+0
+76
+76
+Connector_PinSocket_1.27mm
+PinSocket_2x38_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x38, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x38 1.27mm double row
+0
+76
+76
+Connector_PinSocket_1.27mm
+PinSocket_2x39_P1.27mm_Horizontal
+Through hole angled socket strip, 2x39, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x39 1.27mm double row
+0
+78
+78
+Connector_PinSocket_1.27mm
+PinSocket_2x39_P1.27mm_Vertical
+Through hole straight socket strip, 2x39, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x39 1.27mm double row
+0
+78
+78
+Connector_PinSocket_1.27mm
+PinSocket_2x39_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x39, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x39 1.27mm double row
+0
+78
+78
+Connector_PinSocket_1.27mm
+PinSocket_2x40_P1.27mm_Horizontal
+Through hole angled socket strip, 2x40, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x40 1.27mm double row
+0
+80
+80
+Connector_PinSocket_1.27mm
+PinSocket_2x40_P1.27mm_Vertical
+Through hole straight socket strip, 2x40, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x40 1.27mm double row
+0
+80
+80
+Connector_PinSocket_1.27mm
+PinSocket_2x40_P1.27mm_Vertical_SMD
+surface-mounted straight socket strip, 2x40, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated
+Surface mounted socket strip SMD 2x40 1.27mm double row
+0
+80
+80
+Connector_PinSocket_1.27mm
+PinSocket_2x41_P1.27mm_Horizontal
+Through hole angled socket strip, 2x41, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x41 1.27mm double row
+0
+82
+82
+Connector_PinSocket_1.27mm
+PinSocket_2x42_P1.27mm_Horizontal
+Through hole angled socket strip, 2x42, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x42 1.27mm double row
+0
+84
+84
+Connector_PinSocket_1.27mm
+PinSocket_2x43_P1.27mm_Horizontal
+Through hole angled socket strip, 2x43, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x43 1.27mm double row
+0
+86
+86
+Connector_PinSocket_1.27mm
+PinSocket_2x44_P1.27mm_Horizontal
+Through hole angled socket strip, 2x44, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x44 1.27mm double row
+0
+88
+88
+Connector_PinSocket_1.27mm
+PinSocket_2x45_P1.27mm_Horizontal
+Through hole angled socket strip, 2x45, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x45 1.27mm double row
+0
+90
+90
+Connector_PinSocket_1.27mm
+PinSocket_2x46_P1.27mm_Horizontal
+Through hole angled socket strip, 2x46, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x46 1.27mm double row
+0
+92
+92
+Connector_PinSocket_1.27mm
+PinSocket_2x47_P1.27mm_Horizontal
+Through hole angled socket strip, 2x47, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x47 1.27mm double row
+0
+94
+94
+Connector_PinSocket_1.27mm
+PinSocket_2x48_P1.27mm_Horizontal
+Through hole angled socket strip, 2x48, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x48 1.27mm double row
+0
+96
+96
+Connector_PinSocket_1.27mm
+PinSocket_2x49_P1.27mm_Horizontal
+Through hole angled socket strip, 2x49, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x49 1.27mm double row
+0
+98
+98
+Connector_PinSocket_1.27mm
+PinSocket_2x50_P1.27mm_Horizontal
+Through hole angled socket strip, 2x50, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated
+Through hole angled socket strip THT 2x50 1.27mm double row
+0
+100
+100
+Connector_PinSocket_2.00mm
+PinSocket_1x01_P2.00mm_Horizontal
+Through hole angled socket strip, 1x01, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x01 2.00mm single row
+0
+1
+1
+Connector_PinSocket_2.00mm
+PinSocket_1x01_P2.00mm_Vertical
+Through hole straight socket strip, 1x01, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x01 2.00mm single row
+0
+1
+1
+Connector_PinSocket_2.00mm
+PinSocket_1x02_P2.00mm_Horizontal
+Through hole angled socket strip, 1x02, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x02 2.00mm single row
+0
+2
+2
+Connector_PinSocket_2.00mm
+PinSocket_1x02_P2.00mm_Vertical
+Through hole straight socket strip, 1x02, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x02 2.00mm single row
+0
+2
+2
+Connector_PinSocket_2.00mm
+PinSocket_1x02_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x02, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x02 2.00mm single row style1 pin1 left
+0
+2
+2
+Connector_PinSocket_2.00mm
+PinSocket_1x02_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x02, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x02 2.00mm single row style2 pin1 right
+0
+2
+2
+Connector_PinSocket_2.00mm
+PinSocket_1x03_P2.00mm_Horizontal
+Through hole angled socket strip, 1x03, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x03 2.00mm single row
+0
+3
+3
+Connector_PinSocket_2.00mm
+PinSocket_1x03_P2.00mm_Vertical
+Through hole straight socket strip, 1x03, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x03 2.00mm single row
+0
+3
+3
+Connector_PinSocket_2.00mm
+PinSocket_1x03_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x03, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x03 2.00mm single row style1 pin1 left
+0
+3
+3
+Connector_PinSocket_2.00mm
+PinSocket_1x03_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x03, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x03 2.00mm single row style2 pin1 right
+0
+3
+3
+Connector_PinSocket_2.00mm
+PinSocket_1x04_P2.00mm_Horizontal
+Through hole angled socket strip, 1x04, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x04 2.00mm single row
+0
+4
+4
+Connector_PinSocket_2.00mm
+PinSocket_1x04_P2.00mm_Vertical
+Through hole straight socket strip, 1x04, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x04 2.00mm single row
+0
+4
+4
+Connector_PinSocket_2.00mm
+PinSocket_1x04_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x04, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x04 2.00mm single row style1 pin1 left
+0
+4
+4
+Connector_PinSocket_2.00mm
+PinSocket_1x04_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x04, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x04 2.00mm single row style2 pin1 right
+0
+4
+4
+Connector_PinSocket_2.00mm
+PinSocket_1x05_P2.00mm_Horizontal
+Through hole angled socket strip, 1x05, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x05 2.00mm single row
+0
+5
+5
+Connector_PinSocket_2.00mm
+PinSocket_1x05_P2.00mm_Vertical
+Through hole straight socket strip, 1x05, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x05 2.00mm single row
+0
+5
+5
+Connector_PinSocket_2.00mm
+PinSocket_1x05_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x05, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x05 2.00mm single row style1 pin1 left
+0
+5
+5
+Connector_PinSocket_2.00mm
+PinSocket_1x05_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x05, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x05 2.00mm single row style2 pin1 right
+0
+5
+5
+Connector_PinSocket_2.00mm
+PinSocket_1x06_P2.00mm_Horizontal
+Through hole angled socket strip, 1x06, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x06 2.00mm single row
+0
+6
+6
+Connector_PinSocket_2.00mm
+PinSocket_1x06_P2.00mm_Vertical
+Through hole straight socket strip, 1x06, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x06 2.00mm single row
+0
+6
+6
+Connector_PinSocket_2.00mm
+PinSocket_1x06_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x06, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x06 2.00mm single row style1 pin1 left
+0
+6
+6
+Connector_PinSocket_2.00mm
+PinSocket_1x06_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x06, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x06 2.00mm single row style2 pin1 right
+0
+6
+6
+Connector_PinSocket_2.00mm
+PinSocket_1x07_P2.00mm_Horizontal
+Through hole angled socket strip, 1x07, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x07 2.00mm single row
+0
+7
+7
+Connector_PinSocket_2.00mm
+PinSocket_1x07_P2.00mm_Vertical
+Through hole straight socket strip, 1x07, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x07 2.00mm single row
+0
+7
+7
+Connector_PinSocket_2.00mm
+PinSocket_1x07_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x07, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x07 2.00mm single row style1 pin1 left
+0
+7
+7
+Connector_PinSocket_2.00mm
+PinSocket_1x07_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x07, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x07 2.00mm single row style2 pin1 right
+0
+7
+7
+Connector_PinSocket_2.00mm
+PinSocket_1x08_P2.00mm_Horizontal
+Through hole angled socket strip, 1x08, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x08 2.00mm single row
+0
+8
+8
+Connector_PinSocket_2.00mm
+PinSocket_1x08_P2.00mm_Vertical
+Through hole straight socket strip, 1x08, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x08 2.00mm single row
+0
+8
+8
+Connector_PinSocket_2.00mm
+PinSocket_1x08_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x08, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x08 2.00mm single row style1 pin1 left
+0
+8
+8
+Connector_PinSocket_2.00mm
+PinSocket_1x08_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x08, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x08 2.00mm single row style2 pin1 right
+0
+8
+8
+Connector_PinSocket_2.00mm
+PinSocket_1x09_P2.00mm_Horizontal
+Through hole angled socket strip, 1x09, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x09 2.00mm single row
+0
+9
+9
+Connector_PinSocket_2.00mm
+PinSocket_1x09_P2.00mm_Vertical
+Through hole straight socket strip, 1x09, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x09 2.00mm single row
+0
+9
+9
+Connector_PinSocket_2.00mm
+PinSocket_1x09_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x09, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x09 2.00mm single row style1 pin1 left
+0
+9
+9
+Connector_PinSocket_2.00mm
+PinSocket_1x09_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x09, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x09 2.00mm single row style2 pin1 right
+0
+9
+9
+Connector_PinSocket_2.00mm
+PinSocket_1x10_P2.00mm_Horizontal
+Through hole angled socket strip, 1x10, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x10 2.00mm single row
+0
+10
+10
+Connector_PinSocket_2.00mm
+PinSocket_1x10_P2.00mm_Vertical
+Through hole straight socket strip, 1x10, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x10 2.00mm single row
+0
+10
+10
+Connector_PinSocket_2.00mm
+PinSocket_1x10_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x10, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x10 2.00mm single row style1 pin1 left
+0
+10
+10
+Connector_PinSocket_2.00mm
+PinSocket_1x10_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x10, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x10 2.00mm single row style2 pin1 right
+0
+10
+10
+Connector_PinSocket_2.00mm
+PinSocket_1x11_P2.00mm_Horizontal
+Through hole angled socket strip, 1x11, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x11 2.00mm single row
+0
+11
+11
+Connector_PinSocket_2.00mm
+PinSocket_1x11_P2.00mm_Vertical
+Through hole straight socket strip, 1x11, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x11 2.00mm single row
+0
+11
+11
+Connector_PinSocket_2.00mm
+PinSocket_1x11_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x11, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x11 2.00mm single row style1 pin1 left
+0
+11
+11
+Connector_PinSocket_2.00mm
+PinSocket_1x11_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x11, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x11 2.00mm single row style2 pin1 right
+0
+11
+11
+Connector_PinSocket_2.00mm
+PinSocket_1x12_P2.00mm_Horizontal
+Through hole angled socket strip, 1x12, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x12 2.00mm single row
+0
+12
+12
+Connector_PinSocket_2.00mm
+PinSocket_1x12_P2.00mm_Vertical
+Through hole straight socket strip, 1x12, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x12 2.00mm single row
+0
+12
+12
+Connector_PinSocket_2.00mm
+PinSocket_1x12_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x12, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x12 2.00mm single row style1 pin1 left
+0
+12
+12
+Connector_PinSocket_2.00mm
+PinSocket_1x12_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x12, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x12 2.00mm single row style2 pin1 right
+0
+12
+12
+Connector_PinSocket_2.00mm
+PinSocket_1x13_P2.00mm_Horizontal
+Through hole angled socket strip, 1x13, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x13 2.00mm single row
+0
+13
+13
+Connector_PinSocket_2.00mm
+PinSocket_1x13_P2.00mm_Vertical
+Through hole straight socket strip, 1x13, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x13 2.00mm single row
+0
+13
+13
+Connector_PinSocket_2.00mm
+PinSocket_1x13_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x13, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x13 2.00mm single row style1 pin1 left
+0
+13
+13
+Connector_PinSocket_2.00mm
+PinSocket_1x13_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x13, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x13 2.00mm single row style2 pin1 right
+0
+13
+13
+Connector_PinSocket_2.00mm
+PinSocket_1x14_P2.00mm_Horizontal
+Through hole angled socket strip, 1x14, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x14 2.00mm single row
+0
+14
+14
+Connector_PinSocket_2.00mm
+PinSocket_1x14_P2.00mm_Vertical
+Through hole straight socket strip, 1x14, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x14 2.00mm single row
+0
+14
+14
+Connector_PinSocket_2.00mm
+PinSocket_1x14_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x14, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x14 2.00mm single row style1 pin1 left
+0
+14
+14
+Connector_PinSocket_2.00mm
+PinSocket_1x14_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x14, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x14 2.00mm single row style2 pin1 right
+0
+14
+14
+Connector_PinSocket_2.00mm
+PinSocket_1x15_P2.00mm_Horizontal
+Through hole angled socket strip, 1x15, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x15 2.00mm single row
+0
+15
+15
+Connector_PinSocket_2.00mm
+PinSocket_1x15_P2.00mm_Vertical
+Through hole straight socket strip, 1x15, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x15 2.00mm single row
+0
+15
+15
+Connector_PinSocket_2.00mm
+PinSocket_1x15_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x15, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x15 2.00mm single row style1 pin1 left
+0
+15
+15
+Connector_PinSocket_2.00mm
+PinSocket_1x15_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x15, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x15 2.00mm single row style2 pin1 right
+0
+15
+15
+Connector_PinSocket_2.00mm
+PinSocket_1x16_P2.00mm_Horizontal
+Through hole angled socket strip, 1x16, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x16 2.00mm single row
+0
+16
+16
+Connector_PinSocket_2.00mm
+PinSocket_1x16_P2.00mm_Vertical
+Through hole straight socket strip, 1x16, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x16 2.00mm single row
+0
+16
+16
+Connector_PinSocket_2.00mm
+PinSocket_1x16_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x16, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x16 2.00mm single row style1 pin1 left
+0
+16
+16
+Connector_PinSocket_2.00mm
+PinSocket_1x16_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x16, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x16 2.00mm single row style2 pin1 right
+0
+16
+16
+Connector_PinSocket_2.00mm
+PinSocket_1x17_P2.00mm_Horizontal
+Through hole angled socket strip, 1x17, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x17 2.00mm single row
+0
+17
+17
+Connector_PinSocket_2.00mm
+PinSocket_1x17_P2.00mm_Vertical
+Through hole straight socket strip, 1x17, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x17 2.00mm single row
+0
+17
+17
+Connector_PinSocket_2.00mm
+PinSocket_1x17_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x17, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x17 2.00mm single row style1 pin1 left
+0
+17
+17
+Connector_PinSocket_2.00mm
+PinSocket_1x17_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x17, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x17 2.00mm single row style2 pin1 right
+0
+17
+17
+Connector_PinSocket_2.00mm
+PinSocket_1x18_P2.00mm_Horizontal
+Through hole angled socket strip, 1x18, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x18 2.00mm single row
+0
+18
+18
+Connector_PinSocket_2.00mm
+PinSocket_1x18_P2.00mm_Vertical
+Through hole straight socket strip, 1x18, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x18 2.00mm single row
+0
+18
+18
+Connector_PinSocket_2.00mm
+PinSocket_1x18_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x18, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x18 2.00mm single row style1 pin1 left
+0
+18
+18
+Connector_PinSocket_2.00mm
+PinSocket_1x18_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x18, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x18 2.00mm single row style2 pin1 right
+0
+18
+18
+Connector_PinSocket_2.00mm
+PinSocket_1x19_P2.00mm_Horizontal
+Through hole angled socket strip, 1x19, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x19 2.00mm single row
+0
+19
+19
+Connector_PinSocket_2.00mm
+PinSocket_1x19_P2.00mm_Vertical
+Through hole straight socket strip, 1x19, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x19 2.00mm single row
+0
+19
+19
+Connector_PinSocket_2.00mm
+PinSocket_1x19_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x19, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x19 2.00mm single row style1 pin1 left
+0
+19
+19
+Connector_PinSocket_2.00mm
+PinSocket_1x19_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x19, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x19 2.00mm single row style2 pin1 right
+0
+19
+19
+Connector_PinSocket_2.00mm
+PinSocket_1x20_P2.00mm_Horizontal
+Through hole angled socket strip, 1x20, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x20 2.00mm single row
+0
+20
+20
+Connector_PinSocket_2.00mm
+PinSocket_1x20_P2.00mm_Vertical
+Through hole straight socket strip, 1x20, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x20 2.00mm single row
+0
+20
+20
+Connector_PinSocket_2.00mm
+PinSocket_1x20_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x20, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x20 2.00mm single row style1 pin1 left
+0
+20
+20
+Connector_PinSocket_2.00mm
+PinSocket_1x20_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x20, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x20 2.00mm single row style2 pin1 right
+0
+20
+20
+Connector_PinSocket_2.00mm
+PinSocket_1x21_P2.00mm_Horizontal
+Through hole angled socket strip, 1x21, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x21 2.00mm single row
+0
+21
+21
+Connector_PinSocket_2.00mm
+PinSocket_1x21_P2.00mm_Vertical
+Through hole straight socket strip, 1x21, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x21 2.00mm single row
+0
+21
+21
+Connector_PinSocket_2.00mm
+PinSocket_1x21_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x21, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x21 2.00mm single row style1 pin1 left
+0
+21
+21
+Connector_PinSocket_2.00mm
+PinSocket_1x21_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x21, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x21 2.00mm single row style2 pin1 right
+0
+21
+21
+Connector_PinSocket_2.00mm
+PinSocket_1x22_P2.00mm_Horizontal
+Through hole angled socket strip, 1x22, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x22 2.00mm single row
+0
+22
+22
+Connector_PinSocket_2.00mm
+PinSocket_1x22_P2.00mm_Vertical
+Through hole straight socket strip, 1x22, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x22 2.00mm single row
+0
+22
+22
+Connector_PinSocket_2.00mm
+PinSocket_1x22_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x22, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x22 2.00mm single row style1 pin1 left
+0
+22
+22
+Connector_PinSocket_2.00mm
+PinSocket_1x22_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x22, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x22 2.00mm single row style2 pin1 right
+0
+22
+22
+Connector_PinSocket_2.00mm
+PinSocket_1x23_P2.00mm_Horizontal
+Through hole angled socket strip, 1x23, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x23 2.00mm single row
+0
+23
+23
+Connector_PinSocket_2.00mm
+PinSocket_1x23_P2.00mm_Vertical
+Through hole straight socket strip, 1x23, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x23 2.00mm single row
+0
+23
+23
+Connector_PinSocket_2.00mm
+PinSocket_1x23_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x23, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x23 2.00mm single row style1 pin1 left
+0
+23
+23
+Connector_PinSocket_2.00mm
+PinSocket_1x23_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x23, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x23 2.00mm single row style2 pin1 right
+0
+23
+23
+Connector_PinSocket_2.00mm
+PinSocket_1x24_P2.00mm_Horizontal
+Through hole angled socket strip, 1x24, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x24 2.00mm single row
+0
+24
+24
+Connector_PinSocket_2.00mm
+PinSocket_1x24_P2.00mm_Vertical
+Through hole straight socket strip, 1x24, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x24 2.00mm single row
+0
+24
+24
+Connector_PinSocket_2.00mm
+PinSocket_1x24_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x24, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x24 2.00mm single row style1 pin1 left
+0
+24
+24
+Connector_PinSocket_2.00mm
+PinSocket_1x24_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x24, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x24 2.00mm single row style2 pin1 right
+0
+24
+24
+Connector_PinSocket_2.00mm
+PinSocket_1x25_P2.00mm_Horizontal
+Through hole angled socket strip, 1x25, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x25 2.00mm single row
+0
+25
+25
+Connector_PinSocket_2.00mm
+PinSocket_1x25_P2.00mm_Vertical
+Through hole straight socket strip, 1x25, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x25 2.00mm single row
+0
+25
+25
+Connector_PinSocket_2.00mm
+PinSocket_1x25_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x25, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x25 2.00mm single row style1 pin1 left
+0
+25
+25
+Connector_PinSocket_2.00mm
+PinSocket_1x25_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x25, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x25 2.00mm single row style2 pin1 right
+0
+25
+25
+Connector_PinSocket_2.00mm
+PinSocket_1x26_P2.00mm_Horizontal
+Through hole angled socket strip, 1x26, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x26 2.00mm single row
+0
+26
+26
+Connector_PinSocket_2.00mm
+PinSocket_1x26_P2.00mm_Vertical
+Through hole straight socket strip, 1x26, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x26 2.00mm single row
+0
+26
+26
+Connector_PinSocket_2.00mm
+PinSocket_1x26_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x26, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x26 2.00mm single row style1 pin1 left
+0
+26
+26
+Connector_PinSocket_2.00mm
+PinSocket_1x26_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x26, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x26 2.00mm single row style2 pin1 right
+0
+26
+26
+Connector_PinSocket_2.00mm
+PinSocket_1x27_P2.00mm_Horizontal
+Through hole angled socket strip, 1x27, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x27 2.00mm single row
+0
+27
+27
+Connector_PinSocket_2.00mm
+PinSocket_1x27_P2.00mm_Vertical
+Through hole straight socket strip, 1x27, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x27 2.00mm single row
+0
+27
+27
+Connector_PinSocket_2.00mm
+PinSocket_1x27_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x27, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x27 2.00mm single row style1 pin1 left
+0
+27
+27
+Connector_PinSocket_2.00mm
+PinSocket_1x27_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x27, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x27 2.00mm single row style2 pin1 right
+0
+27
+27
+Connector_PinSocket_2.00mm
+PinSocket_1x28_P2.00mm_Horizontal
+Through hole angled socket strip, 1x28, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x28 2.00mm single row
+0
+28
+28
+Connector_PinSocket_2.00mm
+PinSocket_1x28_P2.00mm_Vertical
+Through hole straight socket strip, 1x28, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x28 2.00mm single row
+0
+28
+28
+Connector_PinSocket_2.00mm
+PinSocket_1x28_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x28, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x28 2.00mm single row style1 pin1 left
+0
+28
+28
+Connector_PinSocket_2.00mm
+PinSocket_1x28_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x28, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x28 2.00mm single row style2 pin1 right
+0
+28
+28
+Connector_PinSocket_2.00mm
+PinSocket_1x29_P2.00mm_Horizontal
+Through hole angled socket strip, 1x29, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x29 2.00mm single row
+0
+29
+29
+Connector_PinSocket_2.00mm
+PinSocket_1x29_P2.00mm_Vertical
+Through hole straight socket strip, 1x29, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x29 2.00mm single row
+0
+29
+29
+Connector_PinSocket_2.00mm
+PinSocket_1x29_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x29, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x29 2.00mm single row style1 pin1 left
+0
+29
+29
+Connector_PinSocket_2.00mm
+PinSocket_1x29_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x29, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x29 2.00mm single row style2 pin1 right
+0
+29
+29
+Connector_PinSocket_2.00mm
+PinSocket_1x30_P2.00mm_Horizontal
+Through hole angled socket strip, 1x30, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x30 2.00mm single row
+0
+30
+30
+Connector_PinSocket_2.00mm
+PinSocket_1x30_P2.00mm_Vertical
+Through hole straight socket strip, 1x30, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x30 2.00mm single row
+0
+30
+30
+Connector_PinSocket_2.00mm
+PinSocket_1x30_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x30, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x30 2.00mm single row style1 pin1 left
+0
+30
+30
+Connector_PinSocket_2.00mm
+PinSocket_1x30_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x30, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x30 2.00mm single row style2 pin1 right
+0
+30
+30
+Connector_PinSocket_2.00mm
+PinSocket_1x31_P2.00mm_Horizontal
+Through hole angled socket strip, 1x31, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x31 2.00mm single row
+0
+31
+31
+Connector_PinSocket_2.00mm
+PinSocket_1x31_P2.00mm_Vertical
+Through hole straight socket strip, 1x31, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x31 2.00mm single row
+0
+31
+31
+Connector_PinSocket_2.00mm
+PinSocket_1x31_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x31, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x31 2.00mm single row style1 pin1 left
+0
+31
+31
+Connector_PinSocket_2.00mm
+PinSocket_1x31_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x31, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x31 2.00mm single row style2 pin1 right
+0
+31
+31
+Connector_PinSocket_2.00mm
+PinSocket_1x32_P2.00mm_Horizontal
+Through hole angled socket strip, 1x32, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x32 2.00mm single row
+0
+32
+32
+Connector_PinSocket_2.00mm
+PinSocket_1x32_P2.00mm_Vertical
+Through hole straight socket strip, 1x32, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x32 2.00mm single row
+0
+32
+32
+Connector_PinSocket_2.00mm
+PinSocket_1x32_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x32, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x32 2.00mm single row style1 pin1 left
+0
+32
+32
+Connector_PinSocket_2.00mm
+PinSocket_1x32_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x32, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x32 2.00mm single row style2 pin1 right
+0
+32
+32
+Connector_PinSocket_2.00mm
+PinSocket_1x33_P2.00mm_Horizontal
+Through hole angled socket strip, 1x33, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x33 2.00mm single row
+0
+33
+33
+Connector_PinSocket_2.00mm
+PinSocket_1x33_P2.00mm_Vertical
+Through hole straight socket strip, 1x33, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x33 2.00mm single row
+0
+33
+33
+Connector_PinSocket_2.00mm
+PinSocket_1x33_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x33, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x33 2.00mm single row style1 pin1 left
+0
+33
+33
+Connector_PinSocket_2.00mm
+PinSocket_1x33_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x33, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x33 2.00mm single row style2 pin1 right
+0
+33
+33
+Connector_PinSocket_2.00mm
+PinSocket_1x34_P2.00mm_Horizontal
+Through hole angled socket strip, 1x34, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x34 2.00mm single row
+0
+34
+34
+Connector_PinSocket_2.00mm
+PinSocket_1x34_P2.00mm_Vertical
+Through hole straight socket strip, 1x34, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x34 2.00mm single row
+0
+34
+34
+Connector_PinSocket_2.00mm
+PinSocket_1x34_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x34, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x34 2.00mm single row style1 pin1 left
+0
+34
+34
+Connector_PinSocket_2.00mm
+PinSocket_1x34_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x34, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x34 2.00mm single row style2 pin1 right
+0
+34
+34
+Connector_PinSocket_2.00mm
+PinSocket_1x35_P2.00mm_Horizontal
+Through hole angled socket strip, 1x35, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x35 2.00mm single row
+0
+35
+35
+Connector_PinSocket_2.00mm
+PinSocket_1x35_P2.00mm_Vertical
+Through hole straight socket strip, 1x35, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x35 2.00mm single row
+0
+35
+35
+Connector_PinSocket_2.00mm
+PinSocket_1x35_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x35, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x35 2.00mm single row style1 pin1 left
+0
+35
+35
+Connector_PinSocket_2.00mm
+PinSocket_1x35_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x35, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x35 2.00mm single row style2 pin1 right
+0
+35
+35
+Connector_PinSocket_2.00mm
+PinSocket_1x36_P2.00mm_Horizontal
+Through hole angled socket strip, 1x36, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x36 2.00mm single row
+0
+36
+36
+Connector_PinSocket_2.00mm
+PinSocket_1x36_P2.00mm_Vertical
+Through hole straight socket strip, 1x36, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x36 2.00mm single row
+0
+36
+36
+Connector_PinSocket_2.00mm
+PinSocket_1x36_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x36, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x36 2.00mm single row style1 pin1 left
+0
+36
+36
+Connector_PinSocket_2.00mm
+PinSocket_1x36_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x36, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x36 2.00mm single row style2 pin1 right
+0
+36
+36
+Connector_PinSocket_2.00mm
+PinSocket_1x37_P2.00mm_Horizontal
+Through hole angled socket strip, 1x37, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x37 2.00mm single row
+0
+37
+37
+Connector_PinSocket_2.00mm
+PinSocket_1x37_P2.00mm_Vertical
+Through hole straight socket strip, 1x37, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x37 2.00mm single row
+0
+37
+37
+Connector_PinSocket_2.00mm
+PinSocket_1x37_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x37, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x37 2.00mm single row style1 pin1 left
+0
+37
+37
+Connector_PinSocket_2.00mm
+PinSocket_1x37_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x37, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x37 2.00mm single row style2 pin1 right
+0
+37
+37
+Connector_PinSocket_2.00mm
+PinSocket_1x38_P2.00mm_Horizontal
+Through hole angled socket strip, 1x38, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x38 2.00mm single row
+0
+38
+38
+Connector_PinSocket_2.00mm
+PinSocket_1x38_P2.00mm_Vertical
+Through hole straight socket strip, 1x38, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x38 2.00mm single row
+0
+38
+38
+Connector_PinSocket_2.00mm
+PinSocket_1x38_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x38, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x38 2.00mm single row style1 pin1 left
+0
+38
+38
+Connector_PinSocket_2.00mm
+PinSocket_1x38_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x38, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x38 2.00mm single row style2 pin1 right
+0
+38
+38
+Connector_PinSocket_2.00mm
+PinSocket_1x39_P2.00mm_Horizontal
+Through hole angled socket strip, 1x39, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x39 2.00mm single row
+0
+39
+39
+Connector_PinSocket_2.00mm
+PinSocket_1x39_P2.00mm_Vertical
+Through hole straight socket strip, 1x39, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x39 2.00mm single row
+0
+39
+39
+Connector_PinSocket_2.00mm
+PinSocket_1x39_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x39, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x39 2.00mm single row style1 pin1 left
+0
+39
+39
+Connector_PinSocket_2.00mm
+PinSocket_1x39_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x39, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x39 2.00mm single row style2 pin1 right
+0
+39
+39
+Connector_PinSocket_2.00mm
+PinSocket_1x40_P2.00mm_Horizontal
+Through hole angled socket strip, 1x40, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x40 2.00mm single row
+0
+40
+40
+Connector_PinSocket_2.00mm
+PinSocket_1x40_P2.00mm_Vertical
+Through hole straight socket strip, 1x40, 2.00mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x40 2.00mm single row
+0
+40
+40
+Connector_PinSocket_2.00mm
+PinSocket_1x40_P2.00mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x40, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x40 2.00mm single row style1 pin1 left
+0
+40
+40
+Connector_PinSocket_2.00mm
+PinSocket_1x40_P2.00mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x40, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated
+Surface mounted socket strip SMD 1x40 2.00mm single row style2 pin1 right
+0
+40
+40
+Connector_PinSocket_2.00mm
+PinSocket_2x01_P2.00mm_Horizontal
+Through hole angled socket strip, 2x01, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x01 2.00mm double row
+0
+2
+2
+Connector_PinSocket_2.00mm
+PinSocket_2x01_P2.00mm_Vertical
+Through hole straight socket strip, 2x01, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x01 2.00mm double row
+0
+2
+2
+Connector_PinSocket_2.00mm
+PinSocket_2x01_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x01, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x01 2.00mm double row
+0
+2
+2
+Connector_PinSocket_2.00mm
+PinSocket_2x02_P2.00mm_Horizontal
+Through hole angled socket strip, 2x02, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x02 2.00mm double row
+0
+4
+4
+Connector_PinSocket_2.00mm
+PinSocket_2x02_P2.00mm_Vertical
+Through hole straight socket strip, 2x02, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x02 2.00mm double row
+0
+4
+4
+Connector_PinSocket_2.00mm
+PinSocket_2x02_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x02, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x02 2.00mm double row
+0
+4
+4
+Connector_PinSocket_2.00mm
+PinSocket_2x03_P2.00mm_Horizontal
+Through hole angled socket strip, 2x03, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x03 2.00mm double row
+0
+6
+6
+Connector_PinSocket_2.00mm
+PinSocket_2x03_P2.00mm_Vertical
+Through hole straight socket strip, 2x03, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x03 2.00mm double row
+0
+6
+6
+Connector_PinSocket_2.00mm
+PinSocket_2x03_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x03, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x03 2.00mm double row
+0
+6
+6
+Connector_PinSocket_2.00mm
+PinSocket_2x04_P2.00mm_Horizontal
+Through hole angled socket strip, 2x04, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x04 2.00mm double row
+0
+8
+8
+Connector_PinSocket_2.00mm
+PinSocket_2x04_P2.00mm_Vertical
+Through hole straight socket strip, 2x04, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x04 2.00mm double row
+0
+8
+8
+Connector_PinSocket_2.00mm
+PinSocket_2x04_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x04, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x04 2.00mm double row
+0
+8
+8
+Connector_PinSocket_2.00mm
+PinSocket_2x05_P2.00mm_Horizontal
+Through hole angled socket strip, 2x05, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x05 2.00mm double row
+0
+10
+10
+Connector_PinSocket_2.00mm
+PinSocket_2x05_P2.00mm_Vertical
+Through hole straight socket strip, 2x05, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x05 2.00mm double row
+0
+10
+10
+Connector_PinSocket_2.00mm
+PinSocket_2x05_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x05, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x05 2.00mm double row
+0
+10
+10
+Connector_PinSocket_2.00mm
+PinSocket_2x06_P2.00mm_Horizontal
+Through hole angled socket strip, 2x06, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x06 2.00mm double row
+0
+12
+12
+Connector_PinSocket_2.00mm
+PinSocket_2x06_P2.00mm_Vertical
+Through hole straight socket strip, 2x06, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x06 2.00mm double row
+0
+12
+12
+Connector_PinSocket_2.00mm
+PinSocket_2x06_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x06, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x06 2.00mm double row
+0
+12
+12
+Connector_PinSocket_2.00mm
+PinSocket_2x07_P2.00mm_Horizontal
+Through hole angled socket strip, 2x07, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x07 2.00mm double row
+0
+14
+14
+Connector_PinSocket_2.00mm
+PinSocket_2x07_P2.00mm_Vertical
+Through hole straight socket strip, 2x07, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x07 2.00mm double row
+0
+14
+14
+Connector_PinSocket_2.00mm
+PinSocket_2x07_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x07, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x07 2.00mm double row
+0
+14
+14
+Connector_PinSocket_2.00mm
+PinSocket_2x08_P2.00mm_Horizontal
+Through hole angled socket strip, 2x08, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x08 2.00mm double row
+0
+16
+16
+Connector_PinSocket_2.00mm
+PinSocket_2x08_P2.00mm_Vertical
+Through hole straight socket strip, 2x08, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x08 2.00mm double row
+0
+16
+16
+Connector_PinSocket_2.00mm
+PinSocket_2x08_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x08, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x08 2.00mm double row
+0
+16
+16
+Connector_PinSocket_2.00mm
+PinSocket_2x09_P2.00mm_Horizontal
+Through hole angled socket strip, 2x09, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x09 2.00mm double row
+0
+18
+18
+Connector_PinSocket_2.00mm
+PinSocket_2x09_P2.00mm_Vertical
+Through hole straight socket strip, 2x09, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x09 2.00mm double row
+0
+18
+18
+Connector_PinSocket_2.00mm
+PinSocket_2x09_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x09, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x09 2.00mm double row
+0
+18
+18
+Connector_PinSocket_2.00mm
+PinSocket_2x10_P2.00mm_Horizontal
+Through hole angled socket strip, 2x10, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x10 2.00mm double row
+0
+20
+20
+Connector_PinSocket_2.00mm
+PinSocket_2x10_P2.00mm_Vertical
+Through hole straight socket strip, 2x10, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x10 2.00mm double row
+0
+20
+20
+Connector_PinSocket_2.00mm
+PinSocket_2x10_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x10, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x10 2.00mm double row
+0
+20
+20
+Connector_PinSocket_2.00mm
+PinSocket_2x11_P2.00mm_Horizontal
+Through hole angled socket strip, 2x11, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x11 2.00mm double row
+0
+22
+22
+Connector_PinSocket_2.00mm
+PinSocket_2x11_P2.00mm_Vertical
+Through hole straight socket strip, 2x11, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x11 2.00mm double row
+0
+22
+22
+Connector_PinSocket_2.00mm
+PinSocket_2x11_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x11, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x11 2.00mm double row
+0
+22
+22
+Connector_PinSocket_2.00mm
+PinSocket_2x12_P2.00mm_Horizontal
+Through hole angled socket strip, 2x12, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x12 2.00mm double row
+0
+24
+24
+Connector_PinSocket_2.00mm
+PinSocket_2x12_P2.00mm_Vertical
+Through hole straight socket strip, 2x12, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x12 2.00mm double row
+0
+24
+24
+Connector_PinSocket_2.00mm
+PinSocket_2x12_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x12, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x12 2.00mm double row
+0
+24
+24
+Connector_PinSocket_2.00mm
+PinSocket_2x13_P2.00mm_Horizontal
+Through hole angled socket strip, 2x13, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x13 2.00mm double row
+0
+26
+26
+Connector_PinSocket_2.00mm
+PinSocket_2x13_P2.00mm_Vertical
+Through hole straight socket strip, 2x13, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x13 2.00mm double row
+0
+26
+26
+Connector_PinSocket_2.00mm
+PinSocket_2x13_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x13, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x13 2.00mm double row
+0
+26
+26
+Connector_PinSocket_2.00mm
+PinSocket_2x14_P2.00mm_Horizontal
+Through hole angled socket strip, 2x14, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x14 2.00mm double row
+0
+28
+28
+Connector_PinSocket_2.00mm
+PinSocket_2x14_P2.00mm_Vertical
+Through hole straight socket strip, 2x14, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x14 2.00mm double row
+0
+28
+28
+Connector_PinSocket_2.00mm
+PinSocket_2x14_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x14, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x14 2.00mm double row
+0
+28
+28
+Connector_PinSocket_2.00mm
+PinSocket_2x15_P2.00mm_Horizontal
+Through hole angled socket strip, 2x15, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x15 2.00mm double row
+0
+30
+30
+Connector_PinSocket_2.00mm
+PinSocket_2x15_P2.00mm_Vertical
+Through hole straight socket strip, 2x15, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x15 2.00mm double row
+0
+30
+30
+Connector_PinSocket_2.00mm
+PinSocket_2x15_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x15, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x15 2.00mm double row
+0
+30
+30
+Connector_PinSocket_2.00mm
+PinSocket_2x16_P2.00mm_Horizontal
+Through hole angled socket strip, 2x16, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x16 2.00mm double row
+0
+32
+32
+Connector_PinSocket_2.00mm
+PinSocket_2x16_P2.00mm_Vertical
+Through hole straight socket strip, 2x16, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x16 2.00mm double row
+0
+32
+32
+Connector_PinSocket_2.00mm
+PinSocket_2x16_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x16, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x16 2.00mm double row
+0
+32
+32
+Connector_PinSocket_2.00mm
+PinSocket_2x17_P2.00mm_Horizontal
+Through hole angled socket strip, 2x17, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x17 2.00mm double row
+0
+34
+34
+Connector_PinSocket_2.00mm
+PinSocket_2x17_P2.00mm_Vertical
+Through hole straight socket strip, 2x17, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x17 2.00mm double row
+0
+34
+34
+Connector_PinSocket_2.00mm
+PinSocket_2x17_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x17, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x17 2.00mm double row
+0
+34
+34
+Connector_PinSocket_2.00mm
+PinSocket_2x18_P2.00mm_Horizontal
+Through hole angled socket strip, 2x18, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x18 2.00mm double row
+0
+36
+36
+Connector_PinSocket_2.00mm
+PinSocket_2x18_P2.00mm_Vertical
+Through hole straight socket strip, 2x18, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x18 2.00mm double row
+0
+36
+36
+Connector_PinSocket_2.00mm
+PinSocket_2x18_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x18, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x18 2.00mm double row
+0
+36
+36
+Connector_PinSocket_2.00mm
+PinSocket_2x19_P2.00mm_Horizontal
+Through hole angled socket strip, 2x19, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x19 2.00mm double row
+0
+38
+38
+Connector_PinSocket_2.00mm
+PinSocket_2x19_P2.00mm_Vertical
+Through hole straight socket strip, 2x19, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x19 2.00mm double row
+0
+38
+38
+Connector_PinSocket_2.00mm
+PinSocket_2x19_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x19, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x19 2.00mm double row
+0
+38
+38
+Connector_PinSocket_2.00mm
+PinSocket_2x20_P2.00mm_Horizontal
+Through hole angled socket strip, 2x20, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x20 2.00mm double row
+0
+40
+40
+Connector_PinSocket_2.00mm
+PinSocket_2x20_P2.00mm_Vertical
+Through hole straight socket strip, 2x20, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x20 2.00mm double row
+0
+40
+40
+Connector_PinSocket_2.00mm
+PinSocket_2x20_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x20, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x20 2.00mm double row
+0
+40
+40
+Connector_PinSocket_2.00mm
+PinSocket_2x21_P2.00mm_Horizontal
+Through hole angled socket strip, 2x21, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x21 2.00mm double row
+0
+42
+42
+Connector_PinSocket_2.00mm
+PinSocket_2x21_P2.00mm_Vertical
+Through hole straight socket strip, 2x21, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x21 2.00mm double row
+0
+42
+42
+Connector_PinSocket_2.00mm
+PinSocket_2x21_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x21, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x21 2.00mm double row
+0
+42
+42
+Connector_PinSocket_2.00mm
+PinSocket_2x22_P2.00mm_Horizontal
+Through hole angled socket strip, 2x22, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x22 2.00mm double row
+0
+44
+44
+Connector_PinSocket_2.00mm
+PinSocket_2x22_P2.00mm_Vertical
+Through hole straight socket strip, 2x22, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x22 2.00mm double row
+0
+44
+44
+Connector_PinSocket_2.00mm
+PinSocket_2x22_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x22, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x22 2.00mm double row
+0
+44
+44
+Connector_PinSocket_2.00mm
+PinSocket_2x23_P2.00mm_Horizontal
+Through hole angled socket strip, 2x23, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x23 2.00mm double row
+0
+46
+46
+Connector_PinSocket_2.00mm
+PinSocket_2x23_P2.00mm_Vertical
+Through hole straight socket strip, 2x23, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x23 2.00mm double row
+0
+46
+46
+Connector_PinSocket_2.00mm
+PinSocket_2x23_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x23, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x23 2.00mm double row
+0
+46
+46
+Connector_PinSocket_2.00mm
+PinSocket_2x24_P2.00mm_Horizontal
+Through hole angled socket strip, 2x24, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x24 2.00mm double row
+0
+48
+48
+Connector_PinSocket_2.00mm
+PinSocket_2x24_P2.00mm_Vertical
+Through hole straight socket strip, 2x24, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x24 2.00mm double row
+0
+48
+48
+Connector_PinSocket_2.00mm
+PinSocket_2x24_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x24, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x24 2.00mm double row
+0
+48
+48
+Connector_PinSocket_2.00mm
+PinSocket_2x25_P2.00mm_Horizontal
+Through hole angled socket strip, 2x25, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x25 2.00mm double row
+0
+50
+50
+Connector_PinSocket_2.00mm
+PinSocket_2x25_P2.00mm_Vertical
+Through hole straight socket strip, 2x25, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x25 2.00mm double row
+0
+50
+50
+Connector_PinSocket_2.00mm
+PinSocket_2x25_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x25, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x25 2.00mm double row
+0
+50
+50
+Connector_PinSocket_2.00mm
+PinSocket_2x26_P2.00mm_Horizontal
+Through hole angled socket strip, 2x26, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x26 2.00mm double row
+0
+52
+52
+Connector_PinSocket_2.00mm
+PinSocket_2x26_P2.00mm_Vertical
+Through hole straight socket strip, 2x26, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x26 2.00mm double row
+0
+52
+52
+Connector_PinSocket_2.00mm
+PinSocket_2x26_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x26, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x26 2.00mm double row
+0
+52
+52
+Connector_PinSocket_2.00mm
+PinSocket_2x27_P2.00mm_Horizontal
+Through hole angled socket strip, 2x27, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x27 2.00mm double row
+0
+54
+54
+Connector_PinSocket_2.00mm
+PinSocket_2x27_P2.00mm_Vertical
+Through hole straight socket strip, 2x27, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x27 2.00mm double row
+0
+54
+54
+Connector_PinSocket_2.00mm
+PinSocket_2x27_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x27, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x27 2.00mm double row
+0
+54
+54
+Connector_PinSocket_2.00mm
+PinSocket_2x28_P2.00mm_Horizontal
+Through hole angled socket strip, 2x28, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x28 2.00mm double row
+0
+56
+56
+Connector_PinSocket_2.00mm
+PinSocket_2x28_P2.00mm_Vertical
+Through hole straight socket strip, 2x28, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x28 2.00mm double row
+0
+56
+56
+Connector_PinSocket_2.00mm
+PinSocket_2x28_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x28, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x28 2.00mm double row
+0
+56
+56
+Connector_PinSocket_2.00mm
+PinSocket_2x29_P2.00mm_Horizontal
+Through hole angled socket strip, 2x29, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x29 2.00mm double row
+0
+58
+58
+Connector_PinSocket_2.00mm
+PinSocket_2x29_P2.00mm_Vertical
+Through hole straight socket strip, 2x29, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x29 2.00mm double row
+0
+58
+58
+Connector_PinSocket_2.00mm
+PinSocket_2x29_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x29, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x29 2.00mm double row
+0
+58
+58
+Connector_PinSocket_2.00mm
+PinSocket_2x30_P2.00mm_Horizontal
+Through hole angled socket strip, 2x30, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x30 2.00mm double row
+0
+60
+60
+Connector_PinSocket_2.00mm
+PinSocket_2x30_P2.00mm_Vertical
+Through hole straight socket strip, 2x30, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x30 2.00mm double row
+0
+60
+60
+Connector_PinSocket_2.00mm
+PinSocket_2x30_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x30, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x30 2.00mm double row
+0
+60
+60
+Connector_PinSocket_2.00mm
+PinSocket_2x31_P2.00mm_Horizontal
+Through hole angled socket strip, 2x31, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x31 2.00mm double row
+0
+62
+62
+Connector_PinSocket_2.00mm
+PinSocket_2x31_P2.00mm_Vertical
+Through hole straight socket strip, 2x31, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x31 2.00mm double row
+0
+62
+62
+Connector_PinSocket_2.00mm
+PinSocket_2x31_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x31, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x31 2.00mm double row
+0
+62
+62
+Connector_PinSocket_2.00mm
+PinSocket_2x32_P2.00mm_Horizontal
+Through hole angled socket strip, 2x32, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x32 2.00mm double row
+0
+64
+64
+Connector_PinSocket_2.00mm
+PinSocket_2x32_P2.00mm_Vertical
+Through hole straight socket strip, 2x32, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x32 2.00mm double row
+0
+64
+64
+Connector_PinSocket_2.00mm
+PinSocket_2x32_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x32, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x32 2.00mm double row
+0
+64
+64
+Connector_PinSocket_2.00mm
+PinSocket_2x33_P2.00mm_Horizontal
+Through hole angled socket strip, 2x33, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x33 2.00mm double row
+0
+66
+66
+Connector_PinSocket_2.00mm
+PinSocket_2x33_P2.00mm_Vertical
+Through hole straight socket strip, 2x33, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x33 2.00mm double row
+0
+66
+66
+Connector_PinSocket_2.00mm
+PinSocket_2x33_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x33, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x33 2.00mm double row
+0
+66
+66
+Connector_PinSocket_2.00mm
+PinSocket_2x34_P2.00mm_Horizontal
+Through hole angled socket strip, 2x34, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x34 2.00mm double row
+0
+68
+68
+Connector_PinSocket_2.00mm
+PinSocket_2x34_P2.00mm_Vertical
+Through hole straight socket strip, 2x34, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x34 2.00mm double row
+0
+68
+68
+Connector_PinSocket_2.00mm
+PinSocket_2x34_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x34, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x34 2.00mm double row
+0
+68
+68
+Connector_PinSocket_2.00mm
+PinSocket_2x35_P2.00mm_Horizontal
+Through hole angled socket strip, 2x35, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x35 2.00mm double row
+0
+70
+70
+Connector_PinSocket_2.00mm
+PinSocket_2x35_P2.00mm_Vertical
+Through hole straight socket strip, 2x35, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x35 2.00mm double row
+0
+70
+70
+Connector_PinSocket_2.00mm
+PinSocket_2x35_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x35, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x35 2.00mm double row
+0
+70
+70
+Connector_PinSocket_2.00mm
+PinSocket_2x36_P2.00mm_Horizontal
+Through hole angled socket strip, 2x36, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x36 2.00mm double row
+0
+72
+72
+Connector_PinSocket_2.00mm
+PinSocket_2x36_P2.00mm_Vertical
+Through hole straight socket strip, 2x36, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x36 2.00mm double row
+0
+72
+72
+Connector_PinSocket_2.00mm
+PinSocket_2x36_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x36, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x36 2.00mm double row
+0
+72
+72
+Connector_PinSocket_2.00mm
+PinSocket_2x37_P2.00mm_Horizontal
+Through hole angled socket strip, 2x37, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x37 2.00mm double row
+0
+74
+74
+Connector_PinSocket_2.00mm
+PinSocket_2x37_P2.00mm_Vertical
+Through hole straight socket strip, 2x37, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x37 2.00mm double row
+0
+74
+74
+Connector_PinSocket_2.00mm
+PinSocket_2x37_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x37, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x37 2.00mm double row
+0
+74
+74
+Connector_PinSocket_2.00mm
+PinSocket_2x38_P2.00mm_Horizontal
+Through hole angled socket strip, 2x38, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x38 2.00mm double row
+0
+76
+76
+Connector_PinSocket_2.00mm
+PinSocket_2x38_P2.00mm_Vertical
+Through hole straight socket strip, 2x38, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x38 2.00mm double row
+0
+76
+76
+Connector_PinSocket_2.00mm
+PinSocket_2x38_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x38, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x38 2.00mm double row
+0
+76
+76
+Connector_PinSocket_2.00mm
+PinSocket_2x39_P2.00mm_Horizontal
+Through hole angled socket strip, 2x39, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x39 2.00mm double row
+0
+78
+78
+Connector_PinSocket_2.00mm
+PinSocket_2x39_P2.00mm_Vertical
+Through hole straight socket strip, 2x39, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x39 2.00mm double row
+0
+78
+78
+Connector_PinSocket_2.00mm
+PinSocket_2x39_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x39, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x39 2.00mm double row
+0
+78
+78
+Connector_PinSocket_2.00mm
+PinSocket_2x40_P2.00mm_Horizontal
+Through hole angled socket strip, 2x40, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x40 2.00mm double row
+0
+80
+80
+Connector_PinSocket_2.00mm
+PinSocket_2x40_P2.00mm_Vertical
+Through hole straight socket strip, 2x40, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x40 2.00mm double row
+0
+80
+80
+Connector_PinSocket_2.00mm
+PinSocket_2x40_P2.00mm_Vertical_SMD
+surface-mounted straight socket strip, 2x40, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x40 2.00mm double row
+0
+80
+80
+Connector_PinSocket_2.54mm
+PinSocket_1x01_P2.54mm_Horizontal
+Through hole angled socket strip, 1x01, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x01 2.54mm single row
+0
+1
+1
+Connector_PinSocket_2.54mm
+PinSocket_1x01_P2.54mm_Vertical
+Through hole straight socket strip, 1x01, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x01 2.54mm single row
+0
+1
+1
+Connector_PinSocket_2.54mm
+PinSocket_1x02_P2.54mm_Horizontal
+Through hole angled socket strip, 1x02, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x02 2.54mm single row
+0
+2
+2
+Connector_PinSocket_2.54mm
+PinSocket_1x02_P2.54mm_Vertical
+Through hole straight socket strip, 1x02, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x02 2.54mm single row
+0
+2
+2
+Connector_PinSocket_2.54mm
+PinSocket_1x02_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x02, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x02 2.54mm single row style1 pin1 left
+0
+2
+2
+Connector_PinSocket_2.54mm
+PinSocket_1x02_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x02, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x02 2.54mm single row style2 pin1 right
+0
+2
+2
+Connector_PinSocket_2.54mm
+PinSocket_1x03_P2.54mm_Horizontal
+Through hole angled socket strip, 1x03, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x03 2.54mm single row
+0
+3
+3
+Connector_PinSocket_2.54mm
+PinSocket_1x03_P2.54mm_Vertical
+Through hole straight socket strip, 1x03, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x03 2.54mm single row
+0
+3
+3
+Connector_PinSocket_2.54mm
+PinSocket_1x03_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x03, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x03 2.54mm single row style1 pin1 left
+0
+3
+3
+Connector_PinSocket_2.54mm
+PinSocket_1x03_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x03, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x03 2.54mm single row style2 pin1 right
+0
+3
+3
+Connector_PinSocket_2.54mm
+PinSocket_1x04_P2.54mm_Horizontal
+Through hole angled socket strip, 1x04, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x04 2.54mm single row
+0
+4
+4
+Connector_PinSocket_2.54mm
+PinSocket_1x04_P2.54mm_Vertical
+Through hole straight socket strip, 1x04, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x04 2.54mm single row
+0
+4
+4
+Connector_PinSocket_2.54mm
+PinSocket_1x04_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x04, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x04 2.54mm single row style1 pin1 left
+0
+4
+4
+Connector_PinSocket_2.54mm
+PinSocket_1x04_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x04, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x04 2.54mm single row style2 pin1 right
+0
+4
+4
+Connector_PinSocket_2.54mm
+PinSocket_1x05_P2.54mm_Horizontal
+Through hole angled socket strip, 1x05, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x05 2.54mm single row
+0
+5
+5
+Connector_PinSocket_2.54mm
+PinSocket_1x05_P2.54mm_Vertical
+Through hole straight socket strip, 1x05, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x05 2.54mm single row
+0
+5
+5
+Connector_PinSocket_2.54mm
+PinSocket_1x05_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x05, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x05 2.54mm single row style1 pin1 left
+0
+5
+5
+Connector_PinSocket_2.54mm
+PinSocket_1x05_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x05, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x05 2.54mm single row style2 pin1 right
+0
+5
+5
+Connector_PinSocket_2.54mm
+PinSocket_1x06_P2.54mm_Horizontal
+Through hole angled socket strip, 1x06, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x06 2.54mm single row
+0
+6
+6
+Connector_PinSocket_2.54mm
+PinSocket_1x06_P2.54mm_Vertical
+Through hole straight socket strip, 1x06, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x06 2.54mm single row
+0
+6
+6
+Connector_PinSocket_2.54mm
+PinSocket_1x06_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x06, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x06 2.54mm single row style1 pin1 left
+0
+6
+6
+Connector_PinSocket_2.54mm
+PinSocket_1x06_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x06, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x06 2.54mm single row style2 pin1 right
+0
+6
+6
+Connector_PinSocket_2.54mm
+PinSocket_1x07_P2.54mm_Horizontal
+Through hole angled socket strip, 1x07, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x07 2.54mm single row
+0
+7
+7
+Connector_PinSocket_2.54mm
+PinSocket_1x07_P2.54mm_Vertical
+Through hole straight socket strip, 1x07, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x07 2.54mm single row
+0
+7
+7
+Connector_PinSocket_2.54mm
+PinSocket_1x07_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x07, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x07 2.54mm single row style1 pin1 left
+0
+7
+7
+Connector_PinSocket_2.54mm
+PinSocket_1x07_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x07, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x07 2.54mm single row style2 pin1 right
+0
+7
+7
+Connector_PinSocket_2.54mm
+PinSocket_1x08_P2.54mm_Horizontal
+Through hole angled socket strip, 1x08, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x08 2.54mm single row
+0
+8
+8
+Connector_PinSocket_2.54mm
+PinSocket_1x08_P2.54mm_Vertical
+Through hole straight socket strip, 1x08, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x08 2.54mm single row
+0
+8
+8
+Connector_PinSocket_2.54mm
+PinSocket_1x08_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x08, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x08 2.54mm single row style1 pin1 left
+0
+8
+8
+Connector_PinSocket_2.54mm
+PinSocket_1x08_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x08, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x08 2.54mm single row style2 pin1 right
+0
+8
+8
+Connector_PinSocket_2.54mm
+PinSocket_1x09_P2.54mm_Horizontal
+Through hole angled socket strip, 1x09, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x09 2.54mm single row
+0
+9
+9
+Connector_PinSocket_2.54mm
+PinSocket_1x09_P2.54mm_Vertical
+Through hole straight socket strip, 1x09, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x09 2.54mm single row
+0
+9
+9
+Connector_PinSocket_2.54mm
+PinSocket_1x09_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x09, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x09 2.54mm single row style1 pin1 left
+0
+9
+9
+Connector_PinSocket_2.54mm
+PinSocket_1x09_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x09, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x09 2.54mm single row style2 pin1 right
+0
+9
+9
+Connector_PinSocket_2.54mm
+PinSocket_1x10_P2.54mm_Horizontal
+Through hole angled socket strip, 1x10, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x10 2.54mm single row
+0
+10
+10
+Connector_PinSocket_2.54mm
+PinSocket_1x10_P2.54mm_Vertical
+Through hole straight socket strip, 1x10, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x10 2.54mm single row
+0
+10
+10
+Connector_PinSocket_2.54mm
+PinSocket_1x10_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x10, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x10 2.54mm single row style1 pin1 left
+0
+10
+10
+Connector_PinSocket_2.54mm
+PinSocket_1x10_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x10, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x10 2.54mm single row style2 pin1 right
+0
+10
+10
+Connector_PinSocket_2.54mm
+PinSocket_1x11_P2.54mm_Horizontal
+Through hole angled socket strip, 1x11, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x11 2.54mm single row
+0
+11
+11
+Connector_PinSocket_2.54mm
+PinSocket_1x11_P2.54mm_Vertical
+Through hole straight socket strip, 1x11, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x11 2.54mm single row
+0
+11
+11
+Connector_PinSocket_2.54mm
+PinSocket_1x11_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x11, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x11 2.54mm single row style1 pin1 left
+0
+11
+11
+Connector_PinSocket_2.54mm
+PinSocket_1x11_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x11, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x11 2.54mm single row style2 pin1 right
+0
+11
+11
+Connector_PinSocket_2.54mm
+PinSocket_1x12_P2.54mm_Horizontal
+Through hole angled socket strip, 1x12, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x12 2.54mm single row
+0
+12
+12
+Connector_PinSocket_2.54mm
+PinSocket_1x12_P2.54mm_Vertical
+Through hole straight socket strip, 1x12, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x12 2.54mm single row
+0
+12
+12
+Connector_PinSocket_2.54mm
+PinSocket_1x12_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x12, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x12 2.54mm single row style1 pin1 left
+0
+12
+12
+Connector_PinSocket_2.54mm
+PinSocket_1x12_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x12, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x12 2.54mm single row style2 pin1 right
+0
+12
+12
+Connector_PinSocket_2.54mm
+PinSocket_1x13_P2.54mm_Horizontal
+Through hole angled socket strip, 1x13, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x13 2.54mm single row
+0
+13
+13
+Connector_PinSocket_2.54mm
+PinSocket_1x13_P2.54mm_Vertical
+Through hole straight socket strip, 1x13, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x13 2.54mm single row
+0
+13
+13
+Connector_PinSocket_2.54mm
+PinSocket_1x13_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x13, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x13 2.54mm single row style1 pin1 left
+0
+13
+13
+Connector_PinSocket_2.54mm
+PinSocket_1x13_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x13, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x13 2.54mm single row style2 pin1 right
+0
+13
+13
+Connector_PinSocket_2.54mm
+PinSocket_1x14_P2.54mm_Horizontal
+Through hole angled socket strip, 1x14, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x14 2.54mm single row
+0
+14
+14
+Connector_PinSocket_2.54mm
+PinSocket_1x14_P2.54mm_Vertical
+Through hole straight socket strip, 1x14, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x14 2.54mm single row
+0
+14
+14
+Connector_PinSocket_2.54mm
+PinSocket_1x14_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x14, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x14 2.54mm single row style1 pin1 left
+0
+14
+14
+Connector_PinSocket_2.54mm
+PinSocket_1x14_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x14, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x14 2.54mm single row style2 pin1 right
+0
+14
+14
+Connector_PinSocket_2.54mm
+PinSocket_1x15_P2.54mm_Horizontal
+Through hole angled socket strip, 1x15, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x15 2.54mm single row
+0
+15
+15
+Connector_PinSocket_2.54mm
+PinSocket_1x15_P2.54mm_Vertical
+Through hole straight socket strip, 1x15, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x15 2.54mm single row
+0
+15
+15
+Connector_PinSocket_2.54mm
+PinSocket_1x15_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x15, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x15 2.54mm single row style1 pin1 left
+0
+15
+15
+Connector_PinSocket_2.54mm
+PinSocket_1x15_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x15, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x15 2.54mm single row style2 pin1 right
+0
+15
+15
+Connector_PinSocket_2.54mm
+PinSocket_1x16_P2.54mm_Horizontal
+Through hole angled socket strip, 1x16, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x16 2.54mm single row
+0
+16
+16
+Connector_PinSocket_2.54mm
+PinSocket_1x16_P2.54mm_Vertical
+Through hole straight socket strip, 1x16, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x16 2.54mm single row
+0
+16
+16
+Connector_PinSocket_2.54mm
+PinSocket_1x16_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x16, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x16 2.54mm single row style1 pin1 left
+0
+16
+16
+Connector_PinSocket_2.54mm
+PinSocket_1x16_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x16, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x16 2.54mm single row style2 pin1 right
+0
+16
+16
+Connector_PinSocket_2.54mm
+PinSocket_1x17_P2.54mm_Horizontal
+Through hole angled socket strip, 1x17, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x17 2.54mm single row
+0
+17
+17
+Connector_PinSocket_2.54mm
+PinSocket_1x17_P2.54mm_Vertical
+Through hole straight socket strip, 1x17, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x17 2.54mm single row
+0
+17
+17
+Connector_PinSocket_2.54mm
+PinSocket_1x17_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x17, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x17 2.54mm single row style1 pin1 left
+0
+17
+17
+Connector_PinSocket_2.54mm
+PinSocket_1x17_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x17, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x17 2.54mm single row style2 pin1 right
+0
+17
+17
+Connector_PinSocket_2.54mm
+PinSocket_1x18_P2.54mm_Horizontal
+Through hole angled socket strip, 1x18, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x18 2.54mm single row
+0
+18
+18
+Connector_PinSocket_2.54mm
+PinSocket_1x18_P2.54mm_Vertical
+Through hole straight socket strip, 1x18, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x18 2.54mm single row
+0
+18
+18
+Connector_PinSocket_2.54mm
+PinSocket_1x18_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x18, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x18 2.54mm single row style1 pin1 left
+0
+18
+18
+Connector_PinSocket_2.54mm
+PinSocket_1x18_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x18, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x18 2.54mm single row style2 pin1 right
+0
+18
+18
+Connector_PinSocket_2.54mm
+PinSocket_1x19_P2.54mm_Horizontal
+Through hole angled socket strip, 1x19, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x19 2.54mm single row
+0
+19
+19
+Connector_PinSocket_2.54mm
+PinSocket_1x19_P2.54mm_Vertical
+Through hole straight socket strip, 1x19, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x19 2.54mm single row
+0
+19
+19
+Connector_PinSocket_2.54mm
+PinSocket_1x19_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x19, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x19 2.54mm single row style1 pin1 left
+0
+19
+19
+Connector_PinSocket_2.54mm
+PinSocket_1x19_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x19, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x19 2.54mm single row style2 pin1 right
+0
+19
+19
+Connector_PinSocket_2.54mm
+PinSocket_1x20_P2.54mm_Horizontal
+Through hole angled socket strip, 1x20, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x20 2.54mm single row
+0
+20
+20
+Connector_PinSocket_2.54mm
+PinSocket_1x20_P2.54mm_Vertical
+Through hole straight socket strip, 1x20, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x20 2.54mm single row
+0
+20
+20
+Connector_PinSocket_2.54mm
+PinSocket_1x20_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x20, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x20 2.54mm single row style1 pin1 left
+0
+20
+20
+Connector_PinSocket_2.54mm
+PinSocket_1x20_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x20, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x20 2.54mm single row style2 pin1 right
+0
+20
+20
+Connector_PinSocket_2.54mm
+PinSocket_1x21_P2.54mm_Horizontal
+Through hole angled socket strip, 1x21, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x21 2.54mm single row
+0
+21
+21
+Connector_PinSocket_2.54mm
+PinSocket_1x21_P2.54mm_Vertical
+Through hole straight socket strip, 1x21, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x21 2.54mm single row
+0
+21
+21
+Connector_PinSocket_2.54mm
+PinSocket_1x21_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x21, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x21 2.54mm single row style1 pin1 left
+0
+21
+21
+Connector_PinSocket_2.54mm
+PinSocket_1x21_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x21, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x21 2.54mm single row style2 pin1 right
+0
+21
+21
+Connector_PinSocket_2.54mm
+PinSocket_1x22_P2.54mm_Horizontal
+Through hole angled socket strip, 1x22, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x22 2.54mm single row
+0
+22
+22
+Connector_PinSocket_2.54mm
+PinSocket_1x22_P2.54mm_Vertical
+Through hole straight socket strip, 1x22, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x22 2.54mm single row
+0
+22
+22
+Connector_PinSocket_2.54mm
+PinSocket_1x22_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x22, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x22 2.54mm single row style1 pin1 left
+0
+22
+22
+Connector_PinSocket_2.54mm
+PinSocket_1x22_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x22, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x22 2.54mm single row style2 pin1 right
+0
+22
+22
+Connector_PinSocket_2.54mm
+PinSocket_1x23_P2.54mm_Horizontal
+Through hole angled socket strip, 1x23, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x23 2.54mm single row
+0
+23
+23
+Connector_PinSocket_2.54mm
+PinSocket_1x23_P2.54mm_Vertical
+Through hole straight socket strip, 1x23, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x23 2.54mm single row
+0
+23
+23
+Connector_PinSocket_2.54mm
+PinSocket_1x23_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x23, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x23 2.54mm single row style1 pin1 left
+0
+23
+23
+Connector_PinSocket_2.54mm
+PinSocket_1x23_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x23, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x23 2.54mm single row style2 pin1 right
+0
+23
+23
+Connector_PinSocket_2.54mm
+PinSocket_1x24_P2.54mm_Horizontal
+Through hole angled socket strip, 1x24, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x24 2.54mm single row
+0
+24
+24
+Connector_PinSocket_2.54mm
+PinSocket_1x24_P2.54mm_Vertical
+Through hole straight socket strip, 1x24, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x24 2.54mm single row
+0
+24
+24
+Connector_PinSocket_2.54mm
+PinSocket_1x24_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x24, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x24 2.54mm single row style1 pin1 left
+0
+24
+24
+Connector_PinSocket_2.54mm
+PinSocket_1x24_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x24, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x24 2.54mm single row style2 pin1 right
+0
+24
+24
+Connector_PinSocket_2.54mm
+PinSocket_1x25_P2.54mm_Horizontal
+Through hole angled socket strip, 1x25, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x25 2.54mm single row
+0
+25
+25
+Connector_PinSocket_2.54mm
+PinSocket_1x25_P2.54mm_Vertical
+Through hole straight socket strip, 1x25, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x25 2.54mm single row
+0
+25
+25
+Connector_PinSocket_2.54mm
+PinSocket_1x25_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x25, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x25 2.54mm single row style1 pin1 left
+0
+25
+25
+Connector_PinSocket_2.54mm
+PinSocket_1x25_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x25, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x25 2.54mm single row style2 pin1 right
+0
+25
+25
+Connector_PinSocket_2.54mm
+PinSocket_1x26_P2.54mm_Horizontal
+Through hole angled socket strip, 1x26, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x26 2.54mm single row
+0
+26
+26
+Connector_PinSocket_2.54mm
+PinSocket_1x26_P2.54mm_Vertical
+Through hole straight socket strip, 1x26, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x26 2.54mm single row
+0
+26
+26
+Connector_PinSocket_2.54mm
+PinSocket_1x26_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x26, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x26 2.54mm single row style1 pin1 left
+0
+26
+26
+Connector_PinSocket_2.54mm
+PinSocket_1x26_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x26, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x26 2.54mm single row style2 pin1 right
+0
+26
+26
+Connector_PinSocket_2.54mm
+PinSocket_1x27_P2.54mm_Horizontal
+Through hole angled socket strip, 1x27, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x27 2.54mm single row
+0
+27
+27
+Connector_PinSocket_2.54mm
+PinSocket_1x27_P2.54mm_Vertical
+Through hole straight socket strip, 1x27, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x27 2.54mm single row
+0
+27
+27
+Connector_PinSocket_2.54mm
+PinSocket_1x27_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x27, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x27 2.54mm single row style1 pin1 left
+0
+27
+27
+Connector_PinSocket_2.54mm
+PinSocket_1x27_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x27, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x27 2.54mm single row style2 pin1 right
+0
+27
+27
+Connector_PinSocket_2.54mm
+PinSocket_1x28_P2.54mm_Horizontal
+Through hole angled socket strip, 1x28, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x28 2.54mm single row
+0
+28
+28
+Connector_PinSocket_2.54mm
+PinSocket_1x28_P2.54mm_Vertical
+Through hole straight socket strip, 1x28, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x28 2.54mm single row
+0
+28
+28
+Connector_PinSocket_2.54mm
+PinSocket_1x28_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x28, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x28 2.54mm single row style1 pin1 left
+0
+28
+28
+Connector_PinSocket_2.54mm
+PinSocket_1x28_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x28, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x28 2.54mm single row style2 pin1 right
+0
+28
+28
+Connector_PinSocket_2.54mm
+PinSocket_1x29_P2.54mm_Horizontal
+Through hole angled socket strip, 1x29, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x29 2.54mm single row
+0
+29
+29
+Connector_PinSocket_2.54mm
+PinSocket_1x29_P2.54mm_Vertical
+Through hole straight socket strip, 1x29, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x29 2.54mm single row
+0
+29
+29
+Connector_PinSocket_2.54mm
+PinSocket_1x29_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x29, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x29 2.54mm single row style1 pin1 left
+0
+29
+29
+Connector_PinSocket_2.54mm
+PinSocket_1x29_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x29, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x29 2.54mm single row style2 pin1 right
+0
+29
+29
+Connector_PinSocket_2.54mm
+PinSocket_1x30_P2.54mm_Horizontal
+Through hole angled socket strip, 1x30, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x30 2.54mm single row
+0
+30
+30
+Connector_PinSocket_2.54mm
+PinSocket_1x30_P2.54mm_Vertical
+Through hole straight socket strip, 1x30, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x30 2.54mm single row
+0
+30
+30
+Connector_PinSocket_2.54mm
+PinSocket_1x30_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x30, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x30 2.54mm single row style1 pin1 left
+0
+30
+30
+Connector_PinSocket_2.54mm
+PinSocket_1x30_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x30, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x30 2.54mm single row style2 pin1 right
+0
+30
+30
+Connector_PinSocket_2.54mm
+PinSocket_1x31_P2.54mm_Horizontal
+Through hole angled socket strip, 1x31, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x31 2.54mm single row
+0
+31
+31
+Connector_PinSocket_2.54mm
+PinSocket_1x31_P2.54mm_Vertical
+Through hole straight socket strip, 1x31, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x31 2.54mm single row
+0
+31
+31
+Connector_PinSocket_2.54mm
+PinSocket_1x31_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x31, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x31 2.54mm single row style1 pin1 left
+0
+31
+31
+Connector_PinSocket_2.54mm
+PinSocket_1x31_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x31, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x31 2.54mm single row style2 pin1 right
+0
+31
+31
+Connector_PinSocket_2.54mm
+PinSocket_1x32_P2.54mm_Horizontal
+Through hole angled socket strip, 1x32, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x32 2.54mm single row
+0
+32
+32
+Connector_PinSocket_2.54mm
+PinSocket_1x32_P2.54mm_Vertical
+Through hole straight socket strip, 1x32, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x32 2.54mm single row
+0
+32
+32
+Connector_PinSocket_2.54mm
+PinSocket_1x32_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x32, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x32 2.54mm single row style1 pin1 left
+0
+32
+32
+Connector_PinSocket_2.54mm
+PinSocket_1x32_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x32, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x32 2.54mm single row style2 pin1 right
+0
+32
+32
+Connector_PinSocket_2.54mm
+PinSocket_1x33_P2.54mm_Horizontal
+Through hole angled socket strip, 1x33, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x33 2.54mm single row
+0
+33
+33
+Connector_PinSocket_2.54mm
+PinSocket_1x33_P2.54mm_Vertical
+Through hole straight socket strip, 1x33, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x33 2.54mm single row
+0
+33
+33
+Connector_PinSocket_2.54mm
+PinSocket_1x33_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x33, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x33 2.54mm single row style1 pin1 left
+0
+33
+33
+Connector_PinSocket_2.54mm
+PinSocket_1x33_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x33, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x33 2.54mm single row style2 pin1 right
+0
+33
+33
+Connector_PinSocket_2.54mm
+PinSocket_1x34_P2.54mm_Horizontal
+Through hole angled socket strip, 1x34, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x34 2.54mm single row
+0
+34
+34
+Connector_PinSocket_2.54mm
+PinSocket_1x34_P2.54mm_Vertical
+Through hole straight socket strip, 1x34, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x34 2.54mm single row
+0
+34
+34
+Connector_PinSocket_2.54mm
+PinSocket_1x34_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x34, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x34 2.54mm single row style1 pin1 left
+0
+34
+34
+Connector_PinSocket_2.54mm
+PinSocket_1x34_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x34, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x34 2.54mm single row style2 pin1 right
+0
+34
+34
+Connector_PinSocket_2.54mm
+PinSocket_1x35_P2.54mm_Horizontal
+Through hole angled socket strip, 1x35, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x35 2.54mm single row
+0
+35
+35
+Connector_PinSocket_2.54mm
+PinSocket_1x35_P2.54mm_Vertical
+Through hole straight socket strip, 1x35, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x35 2.54mm single row
+0
+35
+35
+Connector_PinSocket_2.54mm
+PinSocket_1x35_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x35, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x35 2.54mm single row style1 pin1 left
+0
+35
+35
+Connector_PinSocket_2.54mm
+PinSocket_1x35_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x35, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x35 2.54mm single row style2 pin1 right
+0
+35
+35
+Connector_PinSocket_2.54mm
+PinSocket_1x36_P2.54mm_Horizontal
+Through hole angled socket strip, 1x36, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x36 2.54mm single row
+0
+36
+36
+Connector_PinSocket_2.54mm
+PinSocket_1x36_P2.54mm_Vertical
+Through hole straight socket strip, 1x36, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x36 2.54mm single row
+0
+36
+36
+Connector_PinSocket_2.54mm
+PinSocket_1x36_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x36, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x36 2.54mm single row style1 pin1 left
+0
+36
+36
+Connector_PinSocket_2.54mm
+PinSocket_1x36_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x36, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x36 2.54mm single row style2 pin1 right
+0
+36
+36
+Connector_PinSocket_2.54mm
+PinSocket_1x37_P2.54mm_Horizontal
+Through hole angled socket strip, 1x37, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x37 2.54mm single row
+0
+37
+37
+Connector_PinSocket_2.54mm
+PinSocket_1x37_P2.54mm_Vertical
+Through hole straight socket strip, 1x37, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x37 2.54mm single row
+0
+37
+37
+Connector_PinSocket_2.54mm
+PinSocket_1x37_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x37, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x37 2.54mm single row style1 pin1 left
+0
+37
+37
+Connector_PinSocket_2.54mm
+PinSocket_1x37_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x37, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x37 2.54mm single row style2 pin1 right
+0
+37
+37
+Connector_PinSocket_2.54mm
+PinSocket_1x38_P2.54mm_Horizontal
+Through hole angled socket strip, 1x38, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x38 2.54mm single row
+0
+38
+38
+Connector_PinSocket_2.54mm
+PinSocket_1x38_P2.54mm_Vertical
+Through hole straight socket strip, 1x38, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x38 2.54mm single row
+0
+38
+38
+Connector_PinSocket_2.54mm
+PinSocket_1x38_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x38, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x38 2.54mm single row style1 pin1 left
+0
+38
+38
+Connector_PinSocket_2.54mm
+PinSocket_1x38_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x38, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x38 2.54mm single row style2 pin1 right
+0
+38
+38
+Connector_PinSocket_2.54mm
+PinSocket_1x39_P2.54mm_Horizontal
+Through hole angled socket strip, 1x39, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x39 2.54mm single row
+0
+39
+39
+Connector_PinSocket_2.54mm
+PinSocket_1x39_P2.54mm_Vertical
+Through hole straight socket strip, 1x39, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x39 2.54mm single row
+0
+39
+39
+Connector_PinSocket_2.54mm
+PinSocket_1x39_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x39, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x39 2.54mm single row style1 pin1 left
+0
+39
+39
+Connector_PinSocket_2.54mm
+PinSocket_1x39_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x39, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x39 2.54mm single row style2 pin1 right
+0
+39
+39
+Connector_PinSocket_2.54mm
+PinSocket_1x40_P2.54mm_Horizontal
+Through hole angled socket strip, 1x40, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 1x40 2.54mm single row
+0
+40
+40
+Connector_PinSocket_2.54mm
+PinSocket_1x40_P2.54mm_Vertical
+Through hole straight socket strip, 1x40, 2.54mm pitch, single row (from Kicad 4.0.7), script generated
+Through hole socket strip THT 1x40 2.54mm single row
+0
+40
+40
+Connector_PinSocket_2.54mm
+PinSocket_1x40_P2.54mm_Vertical_SMD_Pin1Left
+surface-mounted straight socket strip, 1x40, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x40 2.54mm single row style1 pin1 left
+0
+40
+40
+Connector_PinSocket_2.54mm
+PinSocket_1x40_P2.54mm_Vertical_SMD_Pin1Right
+surface-mounted straight socket strip, 1x40, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated
+Surface mounted socket strip SMD 1x40 2.54mm single row style2 pin1 right
+0
+40
+40
+Connector_PinSocket_2.54mm
+PinSocket_2x01_P2.54mm_Horizontal
+Through hole angled socket strip, 2x01, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x01 2.54mm double row
+0
+2
+2
+Connector_PinSocket_2.54mm
+PinSocket_2x01_P2.54mm_Vertical
+Through hole straight socket strip, 2x01, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x01 2.54mm double row
+0
+2
+2
+Connector_PinSocket_2.54mm
+PinSocket_2x01_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x01, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x01 2.54mm double row
+0
+2
+2
+Connector_PinSocket_2.54mm
+PinSocket_2x02_P2.54mm_Horizontal
+Through hole angled socket strip, 2x02, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x02 2.54mm double row
+0
+4
+4
+Connector_PinSocket_2.54mm
+PinSocket_2x02_P2.54mm_Vertical
+Through hole straight socket strip, 2x02, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x02 2.54mm double row
+0
+4
+4
+Connector_PinSocket_2.54mm
+PinSocket_2x02_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x02, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x02 2.54mm double row
+0
+4
+4
+Connector_PinSocket_2.54mm
+PinSocket_2x03_P2.54mm_Horizontal
+Through hole angled socket strip, 2x03, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x03 2.54mm double row
+0
+6
+6
+Connector_PinSocket_2.54mm
+PinSocket_2x03_P2.54mm_Vertical
+Through hole straight socket strip, 2x03, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x03 2.54mm double row
+0
+6
+6
+Connector_PinSocket_2.54mm
+PinSocket_2x03_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x03, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x03 2.54mm double row
+0
+6
+6
+Connector_PinSocket_2.54mm
+PinSocket_2x04_P2.54mm_Horizontal
+Through hole angled socket strip, 2x04, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x04 2.54mm double row
+0
+8
+8
+Connector_PinSocket_2.54mm
+PinSocket_2x04_P2.54mm_Vertical
+Through hole straight socket strip, 2x04, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x04 2.54mm double row
+0
+8
+8
+Connector_PinSocket_2.54mm
+PinSocket_2x04_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x04, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x04 2.54mm double row
+0
+8
+8
+Connector_PinSocket_2.54mm
+PinSocket_2x05_P2.54mm_Horizontal
+Through hole angled socket strip, 2x05, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x05 2.54mm double row
+0
+10
+10
+Connector_PinSocket_2.54mm
+PinSocket_2x05_P2.54mm_Vertical
+Through hole straight socket strip, 2x05, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x05 2.54mm double row
+0
+10
+10
+Connector_PinSocket_2.54mm
+PinSocket_2x05_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x05, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x05 2.54mm double row
+0
+10
+10
+Connector_PinSocket_2.54mm
+PinSocket_2x06_P2.54mm_Horizontal
+Through hole angled socket strip, 2x06, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x06 2.54mm double row
+0
+12
+12
+Connector_PinSocket_2.54mm
+PinSocket_2x06_P2.54mm_Vertical
+Through hole straight socket strip, 2x06, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x06 2.54mm double row
+0
+12
+12
+Connector_PinSocket_2.54mm
+PinSocket_2x06_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x06, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x06 2.54mm double row
+0
+12
+12
+Connector_PinSocket_2.54mm
+PinSocket_2x07_P2.54mm_Horizontal
+Through hole angled socket strip, 2x07, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x07 2.54mm double row
+0
+14
+14
+Connector_PinSocket_2.54mm
+PinSocket_2x07_P2.54mm_Vertical
+Through hole straight socket strip, 2x07, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x07 2.54mm double row
+0
+14
+14
+Connector_PinSocket_2.54mm
+PinSocket_2x07_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x07, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x07 2.54mm double row
+0
+14
+14
+Connector_PinSocket_2.54mm
+PinSocket_2x08_P2.54mm_Horizontal
+Through hole angled socket strip, 2x08, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x08 2.54mm double row
+0
+16
+16
+Connector_PinSocket_2.54mm
+PinSocket_2x08_P2.54mm_Vertical
+Through hole straight socket strip, 2x08, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x08 2.54mm double row
+0
+16
+16
+Connector_PinSocket_2.54mm
+PinSocket_2x08_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x08, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x08 2.54mm double row
+0
+16
+16
+Connector_PinSocket_2.54mm
+PinSocket_2x09_P2.54mm_Horizontal
+Through hole angled socket strip, 2x09, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x09 2.54mm double row
+0
+18
+18
+Connector_PinSocket_2.54mm
+PinSocket_2x09_P2.54mm_Vertical
+Through hole straight socket strip, 2x09, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x09 2.54mm double row
+0
+18
+18
+Connector_PinSocket_2.54mm
+PinSocket_2x09_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x09, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x09 2.54mm double row
+0
+18
+18
+Connector_PinSocket_2.54mm
+PinSocket_2x10_P2.54mm_Horizontal
+Through hole angled socket strip, 2x10, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x10 2.54mm double row
+0
+20
+20
+Connector_PinSocket_2.54mm
+PinSocket_2x10_P2.54mm_Vertical
+Through hole straight socket strip, 2x10, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x10 2.54mm double row
+0
+20
+20
+Connector_PinSocket_2.54mm
+PinSocket_2x10_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x10, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x10 2.54mm double row
+0
+20
+20
+Connector_PinSocket_2.54mm
+PinSocket_2x11_P2.54mm_Horizontal
+Through hole angled socket strip, 2x11, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x11 2.54mm double row
+0
+22
+22
+Connector_PinSocket_2.54mm
+PinSocket_2x11_P2.54mm_Vertical
+Through hole straight socket strip, 2x11, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x11 2.54mm double row
+0
+22
+22
+Connector_PinSocket_2.54mm
+PinSocket_2x11_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x11, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x11 2.54mm double row
+0
+22
+22
+Connector_PinSocket_2.54mm
+PinSocket_2x12_P2.54mm_Horizontal
+Through hole angled socket strip, 2x12, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x12 2.54mm double row
+0
+24
+24
+Connector_PinSocket_2.54mm
+PinSocket_2x12_P2.54mm_Vertical
+Through hole straight socket strip, 2x12, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x12 2.54mm double row
+0
+24
+24
+Connector_PinSocket_2.54mm
+PinSocket_2x12_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x12, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x12 2.54mm double row
+0
+24
+24
+Connector_PinSocket_2.54mm
+PinSocket_2x13_P2.54mm_Horizontal
+Through hole angled socket strip, 2x13, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x13 2.54mm double row
+0
+26
+26
+Connector_PinSocket_2.54mm
+PinSocket_2x13_P2.54mm_Vertical
+Through hole straight socket strip, 2x13, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x13 2.54mm double row
+0
+26
+26
+Connector_PinSocket_2.54mm
+PinSocket_2x13_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x13, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x13 2.54mm double row
+0
+26
+26
+Connector_PinSocket_2.54mm
+PinSocket_2x14_P2.54mm_Horizontal
+Through hole angled socket strip, 2x14, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x14 2.54mm double row
+0
+28
+28
+Connector_PinSocket_2.54mm
+PinSocket_2x14_P2.54mm_Vertical
+Through hole straight socket strip, 2x14, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x14 2.54mm double row
+0
+28
+28
+Connector_PinSocket_2.54mm
+PinSocket_2x14_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x14, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x14 2.54mm double row
+0
+28
+28
+Connector_PinSocket_2.54mm
+PinSocket_2x15_P2.54mm_Horizontal
+Through hole angled socket strip, 2x15, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x15 2.54mm double row
+0
+30
+30
+Connector_PinSocket_2.54mm
+PinSocket_2x15_P2.54mm_Vertical
+Through hole straight socket strip, 2x15, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x15 2.54mm double row
+0
+30
+30
+Connector_PinSocket_2.54mm
+PinSocket_2x15_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x15, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x15 2.54mm double row
+0
+30
+30
+Connector_PinSocket_2.54mm
+PinSocket_2x16_P2.54mm_Horizontal
+Through hole angled socket strip, 2x16, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x16 2.54mm double row
+0
+32
+32
+Connector_PinSocket_2.54mm
+PinSocket_2x16_P2.54mm_Vertical
+Through hole straight socket strip, 2x16, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x16 2.54mm double row
+0
+32
+32
+Connector_PinSocket_2.54mm
+PinSocket_2x16_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x16, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x16 2.54mm double row
+0
+32
+32
+Connector_PinSocket_2.54mm
+PinSocket_2x17_P2.54mm_Horizontal
+Through hole angled socket strip, 2x17, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x17 2.54mm double row
+0
+34
+34
+Connector_PinSocket_2.54mm
+PinSocket_2x17_P2.54mm_Vertical
+Through hole straight socket strip, 2x17, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x17 2.54mm double row
+0
+34
+34
+Connector_PinSocket_2.54mm
+PinSocket_2x17_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x17, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x17 2.54mm double row
+0
+34
+34
+Connector_PinSocket_2.54mm
+PinSocket_2x18_P2.54mm_Horizontal
+Through hole angled socket strip, 2x18, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x18 2.54mm double row
+0
+36
+36
+Connector_PinSocket_2.54mm
+PinSocket_2x18_P2.54mm_Vertical
+Through hole straight socket strip, 2x18, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x18 2.54mm double row
+0
+36
+36
+Connector_PinSocket_2.54mm
+PinSocket_2x18_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x18, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x18 2.54mm double row
+0
+36
+36
+Connector_PinSocket_2.54mm
+PinSocket_2x19_P2.54mm_Horizontal
+Through hole angled socket strip, 2x19, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x19 2.54mm double row
+0
+38
+38
+Connector_PinSocket_2.54mm
+PinSocket_2x19_P2.54mm_Vertical
+Through hole straight socket strip, 2x19, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x19 2.54mm double row
+0
+38
+38
+Connector_PinSocket_2.54mm
+PinSocket_2x19_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x19, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x19 2.54mm double row
+0
+38
+38
+Connector_PinSocket_2.54mm
+PinSocket_2x20_P2.54mm_Horizontal
+Through hole angled socket strip, 2x20, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x20 2.54mm double row
+0
+40
+40
+Connector_PinSocket_2.54mm
+PinSocket_2x20_P2.54mm_Vertical
+Through hole straight socket strip, 2x20, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x20 2.54mm double row
+0
+40
+40
+Connector_PinSocket_2.54mm
+PinSocket_2x20_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x20, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x20 2.54mm double row
+0
+40
+40
+Connector_PinSocket_2.54mm
+PinSocket_2x21_P2.54mm_Horizontal
+Through hole angled socket strip, 2x21, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x21 2.54mm double row
+0
+42
+42
+Connector_PinSocket_2.54mm
+PinSocket_2x21_P2.54mm_Vertical
+Through hole straight socket strip, 2x21, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x21 2.54mm double row
+0
+42
+42
+Connector_PinSocket_2.54mm
+PinSocket_2x21_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x21, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x21 2.54mm double row
+0
+42
+42
+Connector_PinSocket_2.54mm
+PinSocket_2x22_P2.54mm_Horizontal
+Through hole angled socket strip, 2x22, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x22 2.54mm double row
+0
+44
+44
+Connector_PinSocket_2.54mm
+PinSocket_2x22_P2.54mm_Vertical
+Through hole straight socket strip, 2x22, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x22 2.54mm double row
+0
+44
+44
+Connector_PinSocket_2.54mm
+PinSocket_2x22_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x22, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x22 2.54mm double row
+0
+44
+44
+Connector_PinSocket_2.54mm
+PinSocket_2x23_P2.54mm_Horizontal
+Through hole angled socket strip, 2x23, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x23 2.54mm double row
+0
+46
+46
+Connector_PinSocket_2.54mm
+PinSocket_2x23_P2.54mm_Vertical
+Through hole straight socket strip, 2x23, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x23 2.54mm double row
+0
+46
+46
+Connector_PinSocket_2.54mm
+PinSocket_2x23_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x23, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x23 2.54mm double row
+0
+46
+46
+Connector_PinSocket_2.54mm
+PinSocket_2x24_P2.54mm_Horizontal
+Through hole angled socket strip, 2x24, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x24 2.54mm double row
+0
+48
+48
+Connector_PinSocket_2.54mm
+PinSocket_2x24_P2.54mm_Vertical
+Through hole straight socket strip, 2x24, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x24 2.54mm double row
+0
+48
+48
+Connector_PinSocket_2.54mm
+PinSocket_2x24_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x24, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x24 2.54mm double row
+0
+48
+48
+Connector_PinSocket_2.54mm
+PinSocket_2x25_P2.54mm_Horizontal
+Through hole angled socket strip, 2x25, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x25 2.54mm double row
+0
+50
+50
+Connector_PinSocket_2.54mm
+PinSocket_2x25_P2.54mm_Vertical
+Through hole straight socket strip, 2x25, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x25 2.54mm double row
+0
+50
+50
+Connector_PinSocket_2.54mm
+PinSocket_2x25_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x25, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x25 2.54mm double row
+0
+50
+50
+Connector_PinSocket_2.54mm
+PinSocket_2x26_P2.54mm_Horizontal
+Through hole angled socket strip, 2x26, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x26 2.54mm double row
+0
+52
+52
+Connector_PinSocket_2.54mm
+PinSocket_2x26_P2.54mm_Vertical
+Through hole straight socket strip, 2x26, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x26 2.54mm double row
+0
+52
+52
+Connector_PinSocket_2.54mm
+PinSocket_2x26_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x26, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x26 2.54mm double row
+0
+52
+52
+Connector_PinSocket_2.54mm
+PinSocket_2x27_P2.54mm_Horizontal
+Through hole angled socket strip, 2x27, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x27 2.54mm double row
+0
+54
+54
+Connector_PinSocket_2.54mm
+PinSocket_2x27_P2.54mm_Vertical
+Through hole straight socket strip, 2x27, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x27 2.54mm double row
+0
+54
+54
+Connector_PinSocket_2.54mm
+PinSocket_2x27_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x27, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x27 2.54mm double row
+0
+54
+54
+Connector_PinSocket_2.54mm
+PinSocket_2x28_P2.54mm_Horizontal
+Through hole angled socket strip, 2x28, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x28 2.54mm double row
+0
+56
+56
+Connector_PinSocket_2.54mm
+PinSocket_2x28_P2.54mm_Vertical
+Through hole straight socket strip, 2x28, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x28 2.54mm double row
+0
+56
+56
+Connector_PinSocket_2.54mm
+PinSocket_2x28_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x28, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x28 2.54mm double row
+0
+56
+56
+Connector_PinSocket_2.54mm
+PinSocket_2x29_P2.54mm_Horizontal
+Through hole angled socket strip, 2x29, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x29 2.54mm double row
+0
+58
+58
+Connector_PinSocket_2.54mm
+PinSocket_2x29_P2.54mm_Vertical
+Through hole straight socket strip, 2x29, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x29 2.54mm double row
+0
+58
+58
+Connector_PinSocket_2.54mm
+PinSocket_2x29_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x29, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x29 2.54mm double row
+0
+58
+58
+Connector_PinSocket_2.54mm
+PinSocket_2x30_P2.54mm_Horizontal
+Through hole angled socket strip, 2x30, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x30 2.54mm double row
+0
+60
+60
+Connector_PinSocket_2.54mm
+PinSocket_2x30_P2.54mm_Vertical
+Through hole straight socket strip, 2x30, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x30 2.54mm double row
+0
+60
+60
+Connector_PinSocket_2.54mm
+PinSocket_2x30_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x30, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x30 2.54mm double row
+0
+60
+60
+Connector_PinSocket_2.54mm
+PinSocket_2x31_P2.54mm_Horizontal
+Through hole angled socket strip, 2x31, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x31 2.54mm double row
+0
+62
+62
+Connector_PinSocket_2.54mm
+PinSocket_2x31_P2.54mm_Vertical
+Through hole straight socket strip, 2x31, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x31 2.54mm double row
+0
+62
+62
+Connector_PinSocket_2.54mm
+PinSocket_2x31_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x31, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x31 2.54mm double row
+0
+62
+62
+Connector_PinSocket_2.54mm
+PinSocket_2x32_P2.54mm_Horizontal
+Through hole angled socket strip, 2x32, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x32 2.54mm double row
+0
+64
+64
+Connector_PinSocket_2.54mm
+PinSocket_2x32_P2.54mm_Vertical
+Through hole straight socket strip, 2x32, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x32 2.54mm double row
+0
+64
+64
+Connector_PinSocket_2.54mm
+PinSocket_2x32_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x32, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x32 2.54mm double row
+0
+64
+64
+Connector_PinSocket_2.54mm
+PinSocket_2x33_P2.54mm_Horizontal
+Through hole angled socket strip, 2x33, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x33 2.54mm double row
+0
+66
+66
+Connector_PinSocket_2.54mm
+PinSocket_2x33_P2.54mm_Vertical
+Through hole straight socket strip, 2x33, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x33 2.54mm double row
+0
+66
+66
+Connector_PinSocket_2.54mm
+PinSocket_2x33_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x33, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x33 2.54mm double row
+0
+66
+66
+Connector_PinSocket_2.54mm
+PinSocket_2x34_P2.54mm_Horizontal
+Through hole angled socket strip, 2x34, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x34 2.54mm double row
+0
+68
+68
+Connector_PinSocket_2.54mm
+PinSocket_2x34_P2.54mm_Vertical
+Through hole straight socket strip, 2x34, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x34 2.54mm double row
+0
+68
+68
+Connector_PinSocket_2.54mm
+PinSocket_2x34_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x34, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x34 2.54mm double row
+0
+68
+68
+Connector_PinSocket_2.54mm
+PinSocket_2x35_P2.54mm_Horizontal
+Through hole angled socket strip, 2x35, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x35 2.54mm double row
+0
+70
+70
+Connector_PinSocket_2.54mm
+PinSocket_2x35_P2.54mm_Vertical
+Through hole straight socket strip, 2x35, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x35 2.54mm double row
+0
+70
+70
+Connector_PinSocket_2.54mm
+PinSocket_2x35_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x35, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x35 2.54mm double row
+0
+70
+70
+Connector_PinSocket_2.54mm
+PinSocket_2x36_P2.54mm_Horizontal
+Through hole angled socket strip, 2x36, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x36 2.54mm double row
+0
+72
+72
+Connector_PinSocket_2.54mm
+PinSocket_2x36_P2.54mm_Vertical
+Through hole straight socket strip, 2x36, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x36 2.54mm double row
+0
+72
+72
+Connector_PinSocket_2.54mm
+PinSocket_2x36_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x36, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x36 2.54mm double row
+0
+72
+72
+Connector_PinSocket_2.54mm
+PinSocket_2x37_P2.54mm_Horizontal
+Through hole angled socket strip, 2x37, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x37 2.54mm double row
+0
+74
+74
+Connector_PinSocket_2.54mm
+PinSocket_2x37_P2.54mm_Vertical
+Through hole straight socket strip, 2x37, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x37 2.54mm double row
+0
+74
+74
+Connector_PinSocket_2.54mm
+PinSocket_2x37_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x37, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x37 2.54mm double row
+0
+74
+74
+Connector_PinSocket_2.54mm
+PinSocket_2x38_P2.54mm_Horizontal
+Through hole angled socket strip, 2x38, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x38 2.54mm double row
+0
+76
+76
+Connector_PinSocket_2.54mm
+PinSocket_2x38_P2.54mm_Vertical
+Through hole straight socket strip, 2x38, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x38 2.54mm double row
+0
+76
+76
+Connector_PinSocket_2.54mm
+PinSocket_2x38_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x38, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x38 2.54mm double row
+0
+76
+76
+Connector_PinSocket_2.54mm
+PinSocket_2x39_P2.54mm_Horizontal
+Through hole angled socket strip, 2x39, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x39 2.54mm double row
+0
+78
+78
+Connector_PinSocket_2.54mm
+PinSocket_2x39_P2.54mm_Vertical
+Through hole straight socket strip, 2x39, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x39 2.54mm double row
+0
+78
+78
+Connector_PinSocket_2.54mm
+PinSocket_2x39_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x39, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x39 2.54mm double row
+0
+78
+78
+Connector_PinSocket_2.54mm
+PinSocket_2x40_P2.54mm_Horizontal
+Through hole angled socket strip, 2x40, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated
+Through hole angled socket strip THT 2x40 2.54mm double row
+0
+80
+80
+Connector_PinSocket_2.54mm
+PinSocket_2x40_P2.54mm_Vertical
+Through hole straight socket strip, 2x40, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Through hole socket strip THT 2x40 2.54mm double row
+0
+80
+80
+Connector_PinSocket_2.54mm
+PinSocket_2x40_P2.54mm_Vertical_SMD
+surface-mounted straight socket strip, 2x40, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated
+Surface mounted socket strip SMD 2x40 2.54mm double row
+0
+80
+80
+Connector_RJ
+RJ12_Amphenol_54601
+RJ12 connector  https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/c-bmj-0082.pdf
+RJ12 connector
+0
+6
+6
+Connector_RJ
+RJ25_Wayconn_MJEA-660X1_Horizontal
+RJ25 6P6C Socket 90 degrees, https://wayconn.com/wp-content/themes/way/datasheet/MJEA-660X1XXX_RJ25_6P6C_PCB_RA.pdf
+RJ12 RJ18 RJ25 jack connector 6P6C
+0
+6
+6
+Connector_RJ
+RJ45_Abracon_ARJP11A-MA_Horizontal
+Shielded RJ45 ethernet connector with transformer and POE (https://abracon.com/Magnetics/lan/ARJP11A.PDF)
+ethernet 8p8c transformer poe rj45
+0
+15
+14
+Connector_RJ
+RJ45_Amphenol_54602-x08_Horizontal
+8 Pol Shallow Latch Connector, Modjack, RJ45 (https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/c-bmj-0102.pdf)
+RJ45
+0
+8
+8
+Connector_RJ
+RJ45_Amphenol_RJHSE538X
+Shielded, 2 LED, https://www.amphenolcanada.com/ProductSearch/drawings/AC/RJHSE538X.pdf
+RJ45 8p8c ethernet cat5
+0
+14
+13
+Connector_RJ
+RJ45_Amphenol_RJHSE538X-02
+Shielded, 2 LED, 2 Ports, http://www.amphenolinfocom.eu/NavData/Drawings/RJHSE-538X-02-REVC.pdf
+RJ45 8p8c dual ethernet cat5
+0
+26
+25
+Connector_RJ
+RJ45_Amphenol_RJHSE5380
+Shielded, https://www.amphenolcanada.com/ProductSearch/drawings/AC/RJHSE538X.pdf
+RJ45 8p8c ethernet cat5
+0
+10
+9
+Connector_RJ
+RJ45_Amphenol_RJHSE5380-08
+Shielded, https://www.amphenolcanada.com/ProductSearch/drawings/AC/RJHSE538X08.pdf
+RJ45 8p8c ethernet cat5
+0
+68
+65
+Connector_RJ
+RJ45_Amphenol_RJMG1BD3B8K1ANR
+1 Port RJ45 Magjack Connector Through Hole 10/100 Base-T, AutoMDIX, https://www.amphenolcanada.com/ProductSearch/Drawings/AC/RJMG1BD3B8K1ANR.PDF
+RJ45 Magjack
+0
+14
+13
+Connector_RJ
+RJ45_BEL_SS74301-00x_Vertical
+https://belfuse.com/resources/drawings/stewartconnector/dr-stw-ss-74301-001-ss-74301-002-ss-74301-005.pdf
+RJ45 Vertical Shield LED Green Yellow
+0
+14
+13
+Connector_RJ
+RJ45_Cetus_J1B1211CCD_Horizontal
+1 Port RJ45 Magjack Connector Through Hole 10/100 Base-T, Cetus, used and distributed by WIZnet (https://wizwiki.net/wiki/lib/exe/fetch.php?media=products:wiz550web:wiz550webds_kr:j1b1211ccd.pdf)
+RJ45 Magjack
+0
+14
+13
+Connector_RJ
+RJ45_Hanrun_HR911105A
+http://www.kosmodrom.com.ua/pdf/HR911105A.pdf
+RJ45 Magjack
+0
+14
+13
+Connector_RJ
+RJ45_OST_PJ012-8P8CX_Vertical
+RJ45 vertical connector http://www.on-shore.com/wp-content/uploads/2015/09/PJ012-8P8CX.pdf
+RJ45 PJ012
+0
+8
+8
+Connector_RJ
+RJ45_Plug_Metz_AJP92A8813
+plug, ethernet, 8P8C, RJ45 Plug
+AJP92A8813 8P8C RJ45 ethernet plug
+0
+8
+8
+Connector_RJ
+RJ45_Pulse_JK0654219NL_Horizontal
+10/100/1000 Base-T RJ45 single port with LEDs https://media.digikey.com/pdf/Data%20Sheets/Pulse%20PDFs/JK%20Series.pdf#page=2
+RJ45 8p8c ethernet
+0
+18
+17
+Connector_RJ
+RJ45_Pulse_JXD6-0001NL_Horizontal
+RJ45 ethernet transformer with magnetics (https://productfinder.pulseeng.com/doc_type/WEB301/doc_num/JXD6-0001NL/doc_part/JXD6-0001NL.pdf)
+ethernet 8p8c transformer magjack
+0
+12
+11
+Connector_RJ
+RJ45_Wuerth_7499010121A_Horizontal
+10/100Base-TX RJ45 ethernet magnetic transformer connector horizontal https://katalog.we-online.de/pbs/datasheet/7499010121A.pdf
+RJ45 ethernet magnetic
+0
+14
+13
+Connector_RJ
+RJ45_Wuerth_7499151120_Horizontal
+Wuerth 7499151120, LAN-Transformer WE-RJ45LAN 10/100/1000 BaseT, Dual Ethernet Jack (http://katalog.we-online.de/pbs/datasheet/7499151120.pdf)
+ethernet lan connector
+0
+32
+29
+Connector_RJ
+RJ45_Wuerth_74980111211_Horizontal
+RJ45 LAN Transformer 10/100BaseT (https://katalog.we-online.de/pbs/datasheet/74980111211.pdf)
+lan magnetics transformer
+0
+14
+13
+Connector_SATA_SAS
+SAS-mini_TEConnectivity_1888174_Vertical
+36pin mini SAS connector, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=1888174&DocType=Customer+Drawing&DocLang=English
+SAS mini connector
+0
+44
+44
+Connector_SATA_SAS
+SATA_Amphenol_10029364-001LF_Horizontal
+https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/10029364.pdf
+SATA
+0
+24
+23
+Connector_Samtec
+Samtec_FMC_ASP-134486-01_10x40_P1.27mm_Vertical
+http://suddendocs.samtec.com/prints/asp-134486-01-mkt.pdf
+FMC HPC
+0
+400
+400
+Connector_Samtec
+Samtec_FMC_ASP-134602-01_10x40_P1.27mm_Vertical
+https://www.marutsu.co.jp/contents/shop/marutsu/ds/asp-134602-01.pdf
+FMC HPC
+0
+400
+400
+Connector_Samtec
+Samtec_FMC_ASP-134604-01_4x40_Vertical
+http://www.samtec.com/standards/vita.aspx
+FMC LPC VITA 
+0
+162
+160
+Connector_Samtec
+Samtec_LSHM-105-xx.x-x-DV-N_2x05_P0.50mm_Vertical
+Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-105-xx.x-x-DV-N, 5 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec  side entry
+0
+10
+10
+Connector_Samtec
+Samtec_LSHM-105-xx.x-x-DV-S_2x05-1SH_P0.50mm_Vertical
+Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-105-xx.x-x-DV-S, 5 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec  side entry
+0
+12
+11
+Connector_Samtec
+Samtec_LSHM-110-xx.x-x-DV-N_2x10_P0.50mm_Vertical
+Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-110-xx.x-x-DV-N, 10 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec  side entry
+0
+20
+20
+Connector_Samtec
+Samtec_LSHM-110-xx.x-x-DV-S_2x10-1SH_P0.50mm_Vertical
+Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-110-xx.x-x-DV-S, 10 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec  side entry
+0
+22
+21
+Connector_Samtec
+Samtec_LSHM-120-xx.x-x-DV-N_2x20_P0.50mm_Vertical
+Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-120-xx.x-x-DV-N, 20 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec  side entry
+0
+40
+40
+Connector_Samtec
+Samtec_LSHM-120-xx.x-x-DV-S_2x20-1SH_P0.50mm_Vertical
+Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-120-xx.x-x-DV-S, 20 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec  side entry
+0
+42
+41
+Connector_Samtec
+Samtec_LSHM-130-xx.x-x-DV-N_2x30_P0.50mm_Vertical
+Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-130-xx.x-x-DV-N, 30 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec  side entry
+0
+60
+60
+Connector_Samtec
+Samtec_LSHM-130-xx.x-x-DV-S_2x30-1SH_P0.50mm_Vertical
+Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-130-xx.x-x-DV-S, 30 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec  side entry
+0
+62
+61
+Connector_Samtec
+Samtec_LSHM-140-xx.x-x-DV-N_2x40_P0.50mm_Vertical
+Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-140-xx.x-x-DV-N, 40 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec  side entry
+0
+80
+80
+Connector_Samtec
+Samtec_LSHM-140-xx.x-x-DV-S_2x40-1SH_P0.50mm_Vertical
+Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-140-xx.x-x-DV-S, 40 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec  side entry
+0
+82
+81
+Connector_Samtec
+Samtec_LSHM-150-xx.x-x-DV-N_2x50_P0.50mm_Vertical
+Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-150-xx.x-x-DV-N, 50 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec  side entry
+0
+100
+100
+Connector_Samtec
+Samtec_LSHM-150-xx.x-x-DV-S_2x50-1SH_P0.50mm_Vertical
+Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-150-xx.x-x-DV-S, 50 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec  side entry
+0
+102
+101
+Connector_Samtec_HLE_SMD
+Samtec_HLE-102-02-xxx-DV-BE-LC_2x02_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-102-02-xxx-DV-BE-LC, 2 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+4
+4
+Connector_Samtec_HLE_SMD
+Samtec_HLE-102-02-xxx-DV-BE_2x02_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-102-02-xxx-DV-BE, 2 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+4
+4
+Connector_Samtec_HLE_SMD
+Samtec_HLE-102-02-xxx-DV-LC_2x02_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-102-02-xxx-DV-LC, 2 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+4
+4
+Connector_Samtec_HLE_SMD
+Samtec_HLE-102-02-xxx-DV_2x02_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-102-02-xxx-DV, 2 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+4
+4
+Connector_Samtec_HLE_SMD
+Samtec_HLE-103-02-xxx-DV-BE-LC_2x03_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-103-02-xxx-DV-BE-LC, 3 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+6
+6
+Connector_Samtec_HLE_SMD
+Samtec_HLE-103-02-xxx-DV-BE_2x03_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-103-02-xxx-DV-BE, 3 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+6
+6
+Connector_Samtec_HLE_SMD
+Samtec_HLE-103-02-xxx-DV-LC_2x03_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-103-02-xxx-DV-LC, 3 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+6
+6
+Connector_Samtec_HLE_SMD
+Samtec_HLE-103-02-xxx-DV_2x03_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-103-02-xxx-DV, 3 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+6
+6
+Connector_Samtec_HLE_SMD
+Samtec_HLE-104-02-xxx-DV-A_2x04_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xxx-DV-A, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+8
+8
+Connector_Samtec_HLE_SMD
+Samtec_HLE-104-02-xxx-DV-BE-A_2x04_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xxx-DV-BE-A, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+8
+8
+Connector_Samtec_HLE_SMD
+Samtec_HLE-104-02-xxx-DV-BE-LC_2x04_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xxx-DV-BE-LC, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+8
+8
+Connector_Samtec_HLE_SMD
+Samtec_HLE-104-02-xxx-DV-BE_2x04_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xxx-DV-BE, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+8
+8
+Connector_Samtec_HLE_SMD
+Samtec_HLE-104-02-xxx-DV-LC_2x04_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xxx-DV-LC, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+8
+8
+Connector_Samtec_HLE_SMD
+Samtec_HLE-104-02-xxx-DV_2x04_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xxx-DV, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+8
+8
+Connector_Samtec_HLE_SMD
+Samtec_HLE-105-02-xxx-DV-A_2x05_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xxx-DV-A, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+10
+10
+Connector_Samtec_HLE_SMD
+Samtec_HLE-105-02-xxx-DV-BE-A_2x05_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xxx-DV-BE-A, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+10
+10
+Connector_Samtec_HLE_SMD
+Samtec_HLE-105-02-xxx-DV-BE-LC_2x05_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xxx-DV-BE-LC, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+10
+10
+Connector_Samtec_HLE_SMD
+Samtec_HLE-105-02-xxx-DV-BE_2x05_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xxx-DV-BE, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+10
+10
+Connector_Samtec_HLE_SMD
+Samtec_HLE-105-02-xxx-DV-LC_2x05_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xxx-DV-LC, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+10
+10
+Connector_Samtec_HLE_SMD
+Samtec_HLE-105-02-xxx-DV_2x05_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xxx-DV, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+10
+10
+Connector_Samtec_HLE_SMD
+Samtec_HLE-106-02-xxx-DV-A_2x06_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xxx-DV-A, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+12
+12
+Connector_Samtec_HLE_SMD
+Samtec_HLE-106-02-xxx-DV-BE-A_2x06_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xxx-DV-BE-A, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+12
+12
+Connector_Samtec_HLE_SMD
+Samtec_HLE-106-02-xxx-DV-BE-LC_2x06_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xxx-DV-BE-LC, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+12
+12
+Connector_Samtec_HLE_SMD
+Samtec_HLE-106-02-xxx-DV-BE_2x06_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xxx-DV-BE, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+12
+12
+Connector_Samtec_HLE_SMD
+Samtec_HLE-106-02-xxx-DV-LC_2x06_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xxx-DV-LC, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+12
+12
+Connector_Samtec_HLE_SMD
+Samtec_HLE-106-02-xxx-DV_2x06_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xxx-DV, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+12
+12
+Connector_Samtec_HLE_SMD
+Samtec_HLE-107-02-xxx-DV-A_2x07_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xxx-DV-A, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+14
+14
+Connector_Samtec_HLE_SMD
+Samtec_HLE-107-02-xxx-DV-BE-A_2x07_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xxx-DV-BE-A, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+14
+14
+Connector_Samtec_HLE_SMD
+Samtec_HLE-107-02-xxx-DV-BE-LC_2x07_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xxx-DV-BE-LC, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+14
+14
+Connector_Samtec_HLE_SMD
+Samtec_HLE-107-02-xxx-DV-BE_2x07_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xxx-DV-BE, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+14
+14
+Connector_Samtec_HLE_SMD
+Samtec_HLE-107-02-xxx-DV-LC_2x07_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xxx-DV-LC, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+14
+14
+Connector_Samtec_HLE_SMD
+Samtec_HLE-107-02-xxx-DV_2x07_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xxx-DV, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+14
+14
+Connector_Samtec_HLE_SMD
+Samtec_HLE-108-02-xxx-DV-A_2x08_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xxx-DV-A, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+16
+16
+Connector_Samtec_HLE_SMD
+Samtec_HLE-108-02-xxx-DV-BE-A_2x08_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xxx-DV-BE-A, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+16
+16
+Connector_Samtec_HLE_SMD
+Samtec_HLE-108-02-xxx-DV-BE-LC_2x08_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xxx-DV-BE-LC, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+16
+16
+Connector_Samtec_HLE_SMD
+Samtec_HLE-108-02-xxx-DV-BE_2x08_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xxx-DV-BE, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+16
+16
+Connector_Samtec_HLE_SMD
+Samtec_HLE-108-02-xxx-DV-LC_2x08_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xxx-DV-LC, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+16
+16
+Connector_Samtec_HLE_SMD
+Samtec_HLE-108-02-xxx-DV_2x08_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xxx-DV, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+16
+16
+Connector_Samtec_HLE_SMD
+Samtec_HLE-109-02-xxx-DV-A_2x09_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xxx-DV-A, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+18
+18
+Connector_Samtec_HLE_SMD
+Samtec_HLE-109-02-xxx-DV-BE-A_2x09_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xxx-DV-BE-A, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+18
+18
+Connector_Samtec_HLE_SMD
+Samtec_HLE-109-02-xxx-DV-BE-LC_2x09_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xxx-DV-BE-LC, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+18
+18
+Connector_Samtec_HLE_SMD
+Samtec_HLE-109-02-xxx-DV-BE_2x09_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xxx-DV-BE, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+18
+18
+Connector_Samtec_HLE_SMD
+Samtec_HLE-109-02-xxx-DV-LC_2x09_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xxx-DV-LC, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+18
+18
+Connector_Samtec_HLE_SMD
+Samtec_HLE-109-02-xxx-DV_2x09_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xxx-DV, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+18
+18
+Connector_Samtec_HLE_SMD
+Samtec_HLE-110-02-xxx-DV-A_2x10_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xxx-DV-A, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+20
+20
+Connector_Samtec_HLE_SMD
+Samtec_HLE-110-02-xxx-DV-BE-A_2x10_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xxx-DV-BE-A, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+20
+20
+Connector_Samtec_HLE_SMD
+Samtec_HLE-110-02-xxx-DV-BE-LC_2x10_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xxx-DV-BE-LC, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+20
+20
+Connector_Samtec_HLE_SMD
+Samtec_HLE-110-02-xxx-DV-BE_2x10_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xxx-DV-BE, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+20
+20
+Connector_Samtec_HLE_SMD
+Samtec_HLE-110-02-xxx-DV-LC_2x10_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xxx-DV-LC, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+20
+20
+Connector_Samtec_HLE_SMD
+Samtec_HLE-110-02-xxx-DV_2x10_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xxx-DV, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+20
+20
+Connector_Samtec_HLE_SMD
+Samtec_HLE-111-02-xxx-DV-A_2x11_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xxx-DV-A, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+22
+22
+Connector_Samtec_HLE_SMD
+Samtec_HLE-111-02-xxx-DV-BE-A_2x11_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xxx-DV-BE-A, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+22
+22
+Connector_Samtec_HLE_SMD
+Samtec_HLE-111-02-xxx-DV-BE-LC_2x11_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xxx-DV-BE-LC, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+22
+22
+Connector_Samtec_HLE_SMD
+Samtec_HLE-111-02-xxx-DV-BE_2x11_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xxx-DV-BE, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+22
+22
+Connector_Samtec_HLE_SMD
+Samtec_HLE-111-02-xxx-DV-LC_2x11_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xxx-DV-LC, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+22
+22
+Connector_Samtec_HLE_SMD
+Samtec_HLE-111-02-xxx-DV_2x11_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xxx-DV, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+22
+22
+Connector_Samtec_HLE_SMD
+Samtec_HLE-112-02-xxx-DV-A_2x12_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xxx-DV-A, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+24
+24
+Connector_Samtec_HLE_SMD
+Samtec_HLE-112-02-xxx-DV-BE-A_2x12_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xxx-DV-BE-A, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+24
+24
+Connector_Samtec_HLE_SMD
+Samtec_HLE-112-02-xxx-DV-BE-LC_2x12_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xxx-DV-BE-LC, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+24
+24
+Connector_Samtec_HLE_SMD
+Samtec_HLE-112-02-xxx-DV-BE_2x12_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xxx-DV-BE, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+24
+24
+Connector_Samtec_HLE_SMD
+Samtec_HLE-112-02-xxx-DV-LC_2x12_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xxx-DV-LC, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+24
+24
+Connector_Samtec_HLE_SMD
+Samtec_HLE-112-02-xxx-DV_2x12_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xxx-DV, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+24
+24
+Connector_Samtec_HLE_SMD
+Samtec_HLE-113-02-xxx-DV-A_2x13_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xxx-DV-A, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+26
+26
+Connector_Samtec_HLE_SMD
+Samtec_HLE-113-02-xxx-DV-BE-A_2x13_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xxx-DV-BE-A, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+26
+26
+Connector_Samtec_HLE_SMD
+Samtec_HLE-113-02-xxx-DV-BE-LC_2x13_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xxx-DV-BE-LC, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+26
+26
+Connector_Samtec_HLE_SMD
+Samtec_HLE-113-02-xxx-DV-BE_2x13_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xxx-DV-BE, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+26
+26
+Connector_Samtec_HLE_SMD
+Samtec_HLE-113-02-xxx-DV-LC_2x13_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xxx-DV-LC, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+26
+26
+Connector_Samtec_HLE_SMD
+Samtec_HLE-113-02-xxx-DV_2x13_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xxx-DV, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+26
+26
+Connector_Samtec_HLE_SMD
+Samtec_HLE-114-02-xxx-DV-A_2x14_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xxx-DV-A, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+28
+28
+Connector_Samtec_HLE_SMD
+Samtec_HLE-114-02-xxx-DV-BE-A_2x14_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xxx-DV-BE-A, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+28
+28
+Connector_Samtec_HLE_SMD
+Samtec_HLE-114-02-xxx-DV-BE-LC_2x14_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xxx-DV-BE-LC, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+28
+28
+Connector_Samtec_HLE_SMD
+Samtec_HLE-114-02-xxx-DV-BE_2x14_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xxx-DV-BE, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+28
+28
+Connector_Samtec_HLE_SMD
+Samtec_HLE-114-02-xxx-DV-LC_2x14_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xxx-DV-LC, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+28
+28
+Connector_Samtec_HLE_SMD
+Samtec_HLE-114-02-xxx-DV_2x14_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xxx-DV, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+28
+28
+Connector_Samtec_HLE_SMD
+Samtec_HLE-115-02-xxx-DV-A_2x15_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xxx-DV-A, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+30
+30
+Connector_Samtec_HLE_SMD
+Samtec_HLE-115-02-xxx-DV-BE-A_2x15_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xxx-DV-BE-A, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+30
+30
+Connector_Samtec_HLE_SMD
+Samtec_HLE-115-02-xxx-DV-BE-LC_2x15_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xxx-DV-BE-LC, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+30
+30
+Connector_Samtec_HLE_SMD
+Samtec_HLE-115-02-xxx-DV-BE_2x15_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xxx-DV-BE, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+30
+30
+Connector_Samtec_HLE_SMD
+Samtec_HLE-115-02-xxx-DV-LC_2x15_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xxx-DV-LC, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+30
+30
+Connector_Samtec_HLE_SMD
+Samtec_HLE-115-02-xxx-DV_2x15_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xxx-DV, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+30
+30
+Connector_Samtec_HLE_SMD
+Samtec_HLE-116-02-xxx-DV-A_2x16_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xxx-DV-A, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+32
+32
+Connector_Samtec_HLE_SMD
+Samtec_HLE-116-02-xxx-DV-BE-A_2x16_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xxx-DV-BE-A, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+32
+32
+Connector_Samtec_HLE_SMD
+Samtec_HLE-116-02-xxx-DV-BE-LC_2x16_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xxx-DV-BE-LC, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+32
+32
+Connector_Samtec_HLE_SMD
+Samtec_HLE-116-02-xxx-DV-BE_2x16_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xxx-DV-BE, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+32
+32
+Connector_Samtec_HLE_SMD
+Samtec_HLE-116-02-xxx-DV-LC_2x16_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xxx-DV-LC, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+32
+32
+Connector_Samtec_HLE_SMD
+Samtec_HLE-116-02-xxx-DV_2x16_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xxx-DV, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+32
+32
+Connector_Samtec_HLE_SMD
+Samtec_HLE-117-02-xxx-DV-A_2x17_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xxx-DV-A, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+34
+34
+Connector_Samtec_HLE_SMD
+Samtec_HLE-117-02-xxx-DV-BE-A_2x17_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xxx-DV-BE-A, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+34
+34
+Connector_Samtec_HLE_SMD
+Samtec_HLE-117-02-xxx-DV-BE-LC_2x17_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xxx-DV-BE-LC, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+34
+34
+Connector_Samtec_HLE_SMD
+Samtec_HLE-117-02-xxx-DV-BE_2x17_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xxx-DV-BE, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+34
+34
+Connector_Samtec_HLE_SMD
+Samtec_HLE-117-02-xxx-DV-LC_2x17_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xxx-DV-LC, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+34
+34
+Connector_Samtec_HLE_SMD
+Samtec_HLE-117-02-xxx-DV_2x17_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xxx-DV, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+34
+34
+Connector_Samtec_HLE_SMD
+Samtec_HLE-118-02-xxx-DV-A_2x18_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xxx-DV-A, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+36
+36
+Connector_Samtec_HLE_SMD
+Samtec_HLE-118-02-xxx-DV-BE-A_2x18_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xxx-DV-BE-A, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+36
+36
+Connector_Samtec_HLE_SMD
+Samtec_HLE-118-02-xxx-DV-BE-LC_2x18_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xxx-DV-BE-LC, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+36
+36
+Connector_Samtec_HLE_SMD
+Samtec_HLE-118-02-xxx-DV-BE_2x18_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xxx-DV-BE, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+36
+36
+Connector_Samtec_HLE_SMD
+Samtec_HLE-118-02-xxx-DV-LC_2x18_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xxx-DV-LC, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+36
+36
+Connector_Samtec_HLE_SMD
+Samtec_HLE-118-02-xxx-DV_2x18_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xxx-DV, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+36
+36
+Connector_Samtec_HLE_SMD
+Samtec_HLE-119-02-xxx-DV-A_2x19_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xxx-DV-A, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+38
+38
+Connector_Samtec_HLE_SMD
+Samtec_HLE-119-02-xxx-DV-BE-A_2x19_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xxx-DV-BE-A, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+38
+38
+Connector_Samtec_HLE_SMD
+Samtec_HLE-119-02-xxx-DV-BE-LC_2x19_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xxx-DV-BE-LC, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+38
+38
+Connector_Samtec_HLE_SMD
+Samtec_HLE-119-02-xxx-DV-BE_2x19_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xxx-DV-BE, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+38
+38
+Connector_Samtec_HLE_SMD
+Samtec_HLE-119-02-xxx-DV-LC_2x19_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xxx-DV-LC, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+38
+38
+Connector_Samtec_HLE_SMD
+Samtec_HLE-119-02-xxx-DV_2x19_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xxx-DV, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+38
+38
+Connector_Samtec_HLE_SMD
+Samtec_HLE-120-02-xxx-DV-A_2x20_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xxx-DV-A, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+40
+40
+Connector_Samtec_HLE_SMD
+Samtec_HLE-120-02-xxx-DV-BE-A_2x20_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xxx-DV-BE-A, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+40
+40
+Connector_Samtec_HLE_SMD
+Samtec_HLE-120-02-xxx-DV-BE-LC_2x20_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xxx-DV-BE-LC, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+40
+40
+Connector_Samtec_HLE_SMD
+Samtec_HLE-120-02-xxx-DV-BE_2x20_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xxx-DV-BE, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+40
+40
+Connector_Samtec_HLE_SMD
+Samtec_HLE-120-02-xxx-DV-LC_2x20_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xxx-DV-LC, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+40
+40
+Connector_Samtec_HLE_SMD
+Samtec_HLE-120-02-xxx-DV_2x20_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xxx-DV, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+40
+40
+Connector_Samtec_HLE_SMD
+Samtec_HLE-121-02-xxx-DV-A_2x21_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xxx-DV-A, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+42
+42
+Connector_Samtec_HLE_SMD
+Samtec_HLE-121-02-xxx-DV-BE-A_2x21_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xxx-DV-BE-A, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+42
+42
+Connector_Samtec_HLE_SMD
+Samtec_HLE-121-02-xxx-DV-BE-LC_2x21_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xxx-DV-BE-LC, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+42
+42
+Connector_Samtec_HLE_SMD
+Samtec_HLE-121-02-xxx-DV-BE_2x21_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xxx-DV-BE, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+42
+42
+Connector_Samtec_HLE_SMD
+Samtec_HLE-121-02-xxx-DV-LC_2x21_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xxx-DV-LC, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+42
+42
+Connector_Samtec_HLE_SMD
+Samtec_HLE-121-02-xxx-DV_2x21_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xxx-DV, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+42
+42
+Connector_Samtec_HLE_SMD
+Samtec_HLE-122-02-xxx-DV-A_2x22_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xxx-DV-A, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+44
+44
+Connector_Samtec_HLE_SMD
+Samtec_HLE-122-02-xxx-DV-BE-A_2x22_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xxx-DV-BE-A, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+44
+44
+Connector_Samtec_HLE_SMD
+Samtec_HLE-122-02-xxx-DV-BE-LC_2x22_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xxx-DV-BE-LC, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+44
+44
+Connector_Samtec_HLE_SMD
+Samtec_HLE-122-02-xxx-DV-BE_2x22_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xxx-DV-BE, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+44
+44
+Connector_Samtec_HLE_SMD
+Samtec_HLE-122-02-xxx-DV-LC_2x22_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xxx-DV-LC, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+44
+44
+Connector_Samtec_HLE_SMD
+Samtec_HLE-122-02-xxx-DV_2x22_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xxx-DV, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+44
+44
+Connector_Samtec_HLE_SMD
+Samtec_HLE-123-02-xxx-DV-A_2x23_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xxx-DV-A, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+46
+46
+Connector_Samtec_HLE_SMD
+Samtec_HLE-123-02-xxx-DV-BE-A_2x23_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xxx-DV-BE-A, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+46
+46
+Connector_Samtec_HLE_SMD
+Samtec_HLE-123-02-xxx-DV-BE-LC_2x23_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xxx-DV-BE-LC, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+46
+46
+Connector_Samtec_HLE_SMD
+Samtec_HLE-123-02-xxx-DV-BE_2x23_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xxx-DV-BE, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+46
+46
+Connector_Samtec_HLE_SMD
+Samtec_HLE-123-02-xxx-DV-LC_2x23_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xxx-DV-LC, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+46
+46
+Connector_Samtec_HLE_SMD
+Samtec_HLE-123-02-xxx-DV_2x23_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xxx-DV, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+46
+46
+Connector_Samtec_HLE_SMD
+Samtec_HLE-124-02-xxx-DV-A_2x24_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xxx-DV-A, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+48
+48
+Connector_Samtec_HLE_SMD
+Samtec_HLE-124-02-xxx-DV-BE-A_2x24_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xxx-DV-BE-A, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+48
+48
+Connector_Samtec_HLE_SMD
+Samtec_HLE-124-02-xxx-DV-BE-LC_2x24_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xxx-DV-BE-LC, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+48
+48
+Connector_Samtec_HLE_SMD
+Samtec_HLE-124-02-xxx-DV-BE_2x24_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xxx-DV-BE, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+48
+48
+Connector_Samtec_HLE_SMD
+Samtec_HLE-124-02-xxx-DV-LC_2x24_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xxx-DV-LC, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+48
+48
+Connector_Samtec_HLE_SMD
+Samtec_HLE-124-02-xxx-DV_2x24_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xxx-DV, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+48
+48
+Connector_Samtec_HLE_SMD
+Samtec_HLE-125-02-xxx-DV-A_2x25_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xxx-DV-A, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+50
+50
+Connector_Samtec_HLE_SMD
+Samtec_HLE-125-02-xxx-DV-BE-A_2x25_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xxx-DV-BE-A, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+50
+50
+Connector_Samtec_HLE_SMD
+Samtec_HLE-125-02-xxx-DV-BE-LC_2x25_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xxx-DV-BE-LC, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+50
+50
+Connector_Samtec_HLE_SMD
+Samtec_HLE-125-02-xxx-DV-BE_2x25_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xxx-DV-BE, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+50
+50
+Connector_Samtec_HLE_SMD
+Samtec_HLE-125-02-xxx-DV-LC_2x25_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xxx-DV-LC, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+50
+50
+Connector_Samtec_HLE_SMD
+Samtec_HLE-125-02-xxx-DV_2x25_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xxx-DV, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+50
+50
+Connector_Samtec_HLE_SMD
+Samtec_HLE-126-02-xxx-DV-A_2x26_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV-A, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+52
+52
+Connector_Samtec_HLE_SMD
+Samtec_HLE-126-02-xxx-DV-BE-A_2x26_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV-BE-A, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+52
+52
+Connector_Samtec_HLE_SMD
+Samtec_HLE-126-02-xxx-DV-BE-LC_2x26_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV-BE-LC, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+52
+52
+Connector_Samtec_HLE_SMD
+Samtec_HLE-126-02-xxx-DV-BE_2x26_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV-BE, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+52
+52
+Connector_Samtec_HLE_SMD
+Samtec_HLE-126-02-xxx-DV-LC_2x26_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV-LC, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+52
+52
+Connector_Samtec_HLE_SMD
+Samtec_HLE-126-02-xxx-DV_2x26_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+52
+52
+Connector_Samtec_HLE_SMD
+Samtec_HLE-127-02-xxx-DV-A_2x27_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xxx-DV-A, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+54
+54
+Connector_Samtec_HLE_SMD
+Samtec_HLE-127-02-xxx-DV-BE-A_2x27_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xxx-DV-BE-A, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+54
+54
+Connector_Samtec_HLE_SMD
+Samtec_HLE-127-02-xxx-DV-BE-LC_2x27_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xxx-DV-BE-LC, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+54
+54
+Connector_Samtec_HLE_SMD
+Samtec_HLE-127-02-xxx-DV-BE_2x27_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xxx-DV-BE, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+54
+54
+Connector_Samtec_HLE_SMD
+Samtec_HLE-127-02-xxx-DV-LC_2x27_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xxx-DV-LC, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+54
+54
+Connector_Samtec_HLE_SMD
+Samtec_HLE-127-02-xxx-DV_2x27_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xxx-DV, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+54
+54
+Connector_Samtec_HLE_SMD
+Samtec_HLE-128-02-xxx-DV-A_2x28_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xxx-DV-A, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+56
+56
+Connector_Samtec_HLE_SMD
+Samtec_HLE-128-02-xxx-DV-BE-A_2x28_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xxx-DV-BE-A, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+56
+56
+Connector_Samtec_HLE_SMD
+Samtec_HLE-128-02-xxx-DV-BE-LC_2x28_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xxx-DV-BE-LC, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+56
+56
+Connector_Samtec_HLE_SMD
+Samtec_HLE-128-02-xxx-DV-BE_2x28_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xxx-DV-BE, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+56
+56
+Connector_Samtec_HLE_SMD
+Samtec_HLE-128-02-xxx-DV-LC_2x28_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xxx-DV-LC, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+56
+56
+Connector_Samtec_HLE_SMD
+Samtec_HLE-128-02-xxx-DV_2x28_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xxx-DV, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+56
+56
+Connector_Samtec_HLE_SMD
+Samtec_HLE-129-02-xxx-DV-A_2x29_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xxx-DV-A, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+58
+58
+Connector_Samtec_HLE_SMD
+Samtec_HLE-129-02-xxx-DV-BE-A_2x29_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xxx-DV-BE-A, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+58
+58
+Connector_Samtec_HLE_SMD
+Samtec_HLE-129-02-xxx-DV-BE-LC_2x29_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xxx-DV-BE-LC, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+58
+58
+Connector_Samtec_HLE_SMD
+Samtec_HLE-129-02-xxx-DV-BE_2x29_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xxx-DV-BE, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+58
+58
+Connector_Samtec_HLE_SMD
+Samtec_HLE-129-02-xxx-DV-LC_2x29_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xxx-DV-LC, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+58
+58
+Connector_Samtec_HLE_SMD
+Samtec_HLE-129-02-xxx-DV_2x29_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xxx-DV, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+58
+58
+Connector_Samtec_HLE_SMD
+Samtec_HLE-130-02-xxx-DV-A_2x30_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xxx-DV-A, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+60
+60
+Connector_Samtec_HLE_SMD
+Samtec_HLE-130-02-xxx-DV-BE-A_2x30_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xxx-DV-BE-A, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+60
+60
+Connector_Samtec_HLE_SMD
+Samtec_HLE-130-02-xxx-DV-BE-LC_2x30_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xxx-DV-BE-LC, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+60
+60
+Connector_Samtec_HLE_SMD
+Samtec_HLE-130-02-xxx-DV-BE_2x30_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xxx-DV-BE, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+60
+60
+Connector_Samtec_HLE_SMD
+Samtec_HLE-130-02-xxx-DV-LC_2x30_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xxx-DV-LC, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+60
+60
+Connector_Samtec_HLE_SMD
+Samtec_HLE-130-02-xxx-DV_2x30_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xxx-DV, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+60
+60
+Connector_Samtec_HLE_SMD
+Samtec_HLE-131-02-xxx-DV-A_2x31_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV-A, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+62
+62
+Connector_Samtec_HLE_SMD
+Samtec_HLE-131-02-xxx-DV-BE-A_2x31_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV-BE-A, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+62
+62
+Connector_Samtec_HLE_SMD
+Samtec_HLE-131-02-xxx-DV-BE-LC_2x31_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV-BE-LC, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+62
+62
+Connector_Samtec_HLE_SMD
+Samtec_HLE-131-02-xxx-DV-BE_2x31_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV-BE, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+62
+62
+Connector_Samtec_HLE_SMD
+Samtec_HLE-131-02-xxx-DV-LC_2x31_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV-LC, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+62
+62
+Connector_Samtec_HLE_SMD
+Samtec_HLE-131-02-xxx-DV_2x31_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+62
+62
+Connector_Samtec_HLE_SMD
+Samtec_HLE-132-02-xxx-DV-A_2x32_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xxx-DV-A, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+64
+64
+Connector_Samtec_HLE_SMD
+Samtec_HLE-132-02-xxx-DV-BE-A_2x32_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xxx-DV-BE-A, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+64
+64
+Connector_Samtec_HLE_SMD
+Samtec_HLE-132-02-xxx-DV-BE-LC_2x32_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xxx-DV-BE-LC, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+64
+64
+Connector_Samtec_HLE_SMD
+Samtec_HLE-132-02-xxx-DV-BE_2x32_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xxx-DV-BE, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+64
+64
+Connector_Samtec_HLE_SMD
+Samtec_HLE-132-02-xxx-DV-LC_2x32_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xxx-DV-LC, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+64
+64
+Connector_Samtec_HLE_SMD
+Samtec_HLE-132-02-xxx-DV_2x32_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xxx-DV, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+64
+64
+Connector_Samtec_HLE_SMD
+Samtec_HLE-133-02-xxx-DV-A_2x33_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xxx-DV-A, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+66
+66
+Connector_Samtec_HLE_SMD
+Samtec_HLE-133-02-xxx-DV-BE-A_2x33_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xxx-DV-BE-A, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+66
+66
+Connector_Samtec_HLE_SMD
+Samtec_HLE-133-02-xxx-DV-BE-LC_2x33_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xxx-DV-BE-LC, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+66
+66
+Connector_Samtec_HLE_SMD
+Samtec_HLE-133-02-xxx-DV-BE_2x33_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xxx-DV-BE, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+66
+66
+Connector_Samtec_HLE_SMD
+Samtec_HLE-133-02-xxx-DV-LC_2x33_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xxx-DV-LC, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+66
+66
+Connector_Samtec_HLE_SMD
+Samtec_HLE-133-02-xxx-DV_2x33_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xxx-DV, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+66
+66
+Connector_Samtec_HLE_SMD
+Samtec_HLE-134-02-xxx-DV-A_2x34_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xxx-DV-A, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+68
+68
+Connector_Samtec_HLE_SMD
+Samtec_HLE-134-02-xxx-DV-BE-A_2x34_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xxx-DV-BE-A, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+68
+68
+Connector_Samtec_HLE_SMD
+Samtec_HLE-134-02-xxx-DV-BE-LC_2x34_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xxx-DV-BE-LC, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+68
+68
+Connector_Samtec_HLE_SMD
+Samtec_HLE-134-02-xxx-DV-BE_2x34_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xxx-DV-BE, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+68
+68
+Connector_Samtec_HLE_SMD
+Samtec_HLE-134-02-xxx-DV-LC_2x34_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xxx-DV-LC, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+68
+68
+Connector_Samtec_HLE_SMD
+Samtec_HLE-134-02-xxx-DV_2x34_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xxx-DV, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+68
+68
+Connector_Samtec_HLE_SMD
+Samtec_HLE-135-02-xxx-DV-A_2x35_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xxx-DV-A, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+70
+70
+Connector_Samtec_HLE_SMD
+Samtec_HLE-135-02-xxx-DV-BE-A_2x35_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xxx-DV-BE-A, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+70
+70
+Connector_Samtec_HLE_SMD
+Samtec_HLE-135-02-xxx-DV-BE-LC_2x35_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xxx-DV-BE-LC, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+70
+70
+Connector_Samtec_HLE_SMD
+Samtec_HLE-135-02-xxx-DV-BE_2x35_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xxx-DV-BE, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+70
+70
+Connector_Samtec_HLE_SMD
+Samtec_HLE-135-02-xxx-DV-LC_2x35_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xxx-DV-LC, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+70
+70
+Connector_Samtec_HLE_SMD
+Samtec_HLE-135-02-xxx-DV_2x35_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xxx-DV, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+70
+70
+Connector_Samtec_HLE_SMD
+Samtec_HLE-136-02-xxx-DV-A_2x36_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xxx-DV-A, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+72
+72
+Connector_Samtec_HLE_SMD
+Samtec_HLE-136-02-xxx-DV-BE-A_2x36_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xxx-DV-BE-A, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+72
+72
+Connector_Samtec_HLE_SMD
+Samtec_HLE-136-02-xxx-DV-BE-LC_2x36_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xxx-DV-BE-LC, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+72
+72
+Connector_Samtec_HLE_SMD
+Samtec_HLE-136-02-xxx-DV-BE_2x36_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xxx-DV-BE, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+72
+72
+Connector_Samtec_HLE_SMD
+Samtec_HLE-136-02-xxx-DV-LC_2x36_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xxx-DV-LC, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+72
+72
+Connector_Samtec_HLE_SMD
+Samtec_HLE-136-02-xxx-DV_2x36_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xxx-DV, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+72
+72
+Connector_Samtec_HLE_SMD
+Samtec_HLE-137-02-xxx-DV-A_2x37_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xxx-DV-A, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+74
+74
+Connector_Samtec_HLE_SMD
+Samtec_HLE-137-02-xxx-DV-BE-A_2x37_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xxx-DV-BE-A, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+74
+74
+Connector_Samtec_HLE_SMD
+Samtec_HLE-137-02-xxx-DV-BE-LC_2x37_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xxx-DV-BE-LC, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+74
+74
+Connector_Samtec_HLE_SMD
+Samtec_HLE-137-02-xxx-DV-BE_2x37_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xxx-DV-BE, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+74
+74
+Connector_Samtec_HLE_SMD
+Samtec_HLE-137-02-xxx-DV-LC_2x37_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xxx-DV-LC, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+74
+74
+Connector_Samtec_HLE_SMD
+Samtec_HLE-137-02-xxx-DV_2x37_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xxx-DV, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+74
+74
+Connector_Samtec_HLE_SMD
+Samtec_HLE-138-02-xxx-DV-A_2x38_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xxx-DV-A, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+76
+76
+Connector_Samtec_HLE_SMD
+Samtec_HLE-138-02-xxx-DV-BE-A_2x38_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xxx-DV-BE-A, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+76
+76
+Connector_Samtec_HLE_SMD
+Samtec_HLE-138-02-xxx-DV-BE-LC_2x38_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xxx-DV-BE-LC, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+76
+76
+Connector_Samtec_HLE_SMD
+Samtec_HLE-138-02-xxx-DV-BE_2x38_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xxx-DV-BE, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+76
+76
+Connector_Samtec_HLE_SMD
+Samtec_HLE-138-02-xxx-DV-LC_2x38_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xxx-DV-LC, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+76
+76
+Connector_Samtec_HLE_SMD
+Samtec_HLE-138-02-xxx-DV_2x38_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xxx-DV, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+76
+76
+Connector_Samtec_HLE_SMD
+Samtec_HLE-139-02-xxx-DV-A_2x39_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xxx-DV-A, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+78
+78
+Connector_Samtec_HLE_SMD
+Samtec_HLE-139-02-xxx-DV-BE-A_2x39_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xxx-DV-BE-A, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+78
+78
+Connector_Samtec_HLE_SMD
+Samtec_HLE-139-02-xxx-DV-BE-LC_2x39_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xxx-DV-BE-LC, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+78
+78
+Connector_Samtec_HLE_SMD
+Samtec_HLE-139-02-xxx-DV-BE_2x39_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xxx-DV-BE, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+78
+78
+Connector_Samtec_HLE_SMD
+Samtec_HLE-139-02-xxx-DV-LC_2x39_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xxx-DV-LC, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+78
+78
+Connector_Samtec_HLE_SMD
+Samtec_HLE-139-02-xxx-DV_2x39_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xxx-DV, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+78
+78
+Connector_Samtec_HLE_SMD
+Samtec_HLE-140-02-xxx-DV-A_2x40_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV-A, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+80
+80
+Connector_Samtec_HLE_SMD
+Samtec_HLE-140-02-xxx-DV-BE-A_2x40_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV-BE-A, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+80
+80
+Connector_Samtec_HLE_SMD
+Samtec_HLE-140-02-xxx-DV-BE-LC_2x40_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV-BE-LC, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+80
+80
+Connector_Samtec_HLE_SMD
+Samtec_HLE-140-02-xxx-DV-BE_2x40_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV-BE, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+80
+80
+Connector_Samtec_HLE_SMD
+Samtec_HLE-140-02-xxx-DV-LC_2x40_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV-LC, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+80
+80
+Connector_Samtec_HLE_SMD
+Samtec_HLE-140-02-xxx-DV_2x40_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+80
+80
+Connector_Samtec_HLE_SMD
+Samtec_HLE-141-02-xxx-DV-A_2x41_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xxx-DV-A, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+82
+82
+Connector_Samtec_HLE_SMD
+Samtec_HLE-141-02-xxx-DV-BE-A_2x41_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xxx-DV-BE-A, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+82
+82
+Connector_Samtec_HLE_SMD
+Samtec_HLE-141-02-xxx-DV-BE-LC_2x41_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xxx-DV-BE-LC, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+82
+82
+Connector_Samtec_HLE_SMD
+Samtec_HLE-141-02-xxx-DV-BE_2x41_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xxx-DV-BE, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+82
+82
+Connector_Samtec_HLE_SMD
+Samtec_HLE-141-02-xxx-DV-LC_2x41_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xxx-DV-LC, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+82
+82
+Connector_Samtec_HLE_SMD
+Samtec_HLE-141-02-xxx-DV_2x41_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xxx-DV, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+82
+82
+Connector_Samtec_HLE_SMD
+Samtec_HLE-142-02-xxx-DV-A_2x42_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xxx-DV-A, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+84
+84
+Connector_Samtec_HLE_SMD
+Samtec_HLE-142-02-xxx-DV-BE-A_2x42_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xxx-DV-BE-A, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+84
+84
+Connector_Samtec_HLE_SMD
+Samtec_HLE-142-02-xxx-DV-BE-LC_2x42_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xxx-DV-BE-LC, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+84
+84
+Connector_Samtec_HLE_SMD
+Samtec_HLE-142-02-xxx-DV-BE_2x42_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xxx-DV-BE, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+84
+84
+Connector_Samtec_HLE_SMD
+Samtec_HLE-142-02-xxx-DV-LC_2x42_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xxx-DV-LC, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+84
+84
+Connector_Samtec_HLE_SMD
+Samtec_HLE-142-02-xxx-DV_2x42_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xxx-DV, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+84
+84
+Connector_Samtec_HLE_SMD
+Samtec_HLE-143-02-xxx-DV-A_2x43_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xxx-DV-A, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+86
+86
+Connector_Samtec_HLE_SMD
+Samtec_HLE-143-02-xxx-DV-BE-A_2x43_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xxx-DV-BE-A, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+86
+86
+Connector_Samtec_HLE_SMD
+Samtec_HLE-143-02-xxx-DV-BE-LC_2x43_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xxx-DV-BE-LC, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+86
+86
+Connector_Samtec_HLE_SMD
+Samtec_HLE-143-02-xxx-DV-BE_2x43_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xxx-DV-BE, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+86
+86
+Connector_Samtec_HLE_SMD
+Samtec_HLE-143-02-xxx-DV-LC_2x43_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xxx-DV-LC, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+86
+86
+Connector_Samtec_HLE_SMD
+Samtec_HLE-143-02-xxx-DV_2x43_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xxx-DV, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+86
+86
+Connector_Samtec_HLE_SMD
+Samtec_HLE-144-02-xxx-DV-A_2x44_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xxx-DV-A, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+88
+88
+Connector_Samtec_HLE_SMD
+Samtec_HLE-144-02-xxx-DV-BE-A_2x44_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xxx-DV-BE-A, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+88
+88
+Connector_Samtec_HLE_SMD
+Samtec_HLE-144-02-xxx-DV-BE-LC_2x44_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xxx-DV-BE-LC, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+88
+88
+Connector_Samtec_HLE_SMD
+Samtec_HLE-144-02-xxx-DV-BE_2x44_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xxx-DV-BE, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+88
+88
+Connector_Samtec_HLE_SMD
+Samtec_HLE-144-02-xxx-DV-LC_2x44_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xxx-DV-LC, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+88
+88
+Connector_Samtec_HLE_SMD
+Samtec_HLE-144-02-xxx-DV_2x44_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xxx-DV, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+88
+88
+Connector_Samtec_HLE_SMD
+Samtec_HLE-145-02-xxx-DV-A_2x45_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xxx-DV-A, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+90
+90
+Connector_Samtec_HLE_SMD
+Samtec_HLE-145-02-xxx-DV-BE-A_2x45_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xxx-DV-BE-A, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+90
+90
+Connector_Samtec_HLE_SMD
+Samtec_HLE-145-02-xxx-DV-BE-LC_2x45_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xxx-DV-BE-LC, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+90
+90
+Connector_Samtec_HLE_SMD
+Samtec_HLE-145-02-xxx-DV-BE_2x45_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xxx-DV-BE, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+90
+90
+Connector_Samtec_HLE_SMD
+Samtec_HLE-145-02-xxx-DV-LC_2x45_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xxx-DV-LC, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+90
+90
+Connector_Samtec_HLE_SMD
+Samtec_HLE-145-02-xxx-DV_2x45_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xxx-DV, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+90
+90
+Connector_Samtec_HLE_SMD
+Samtec_HLE-146-02-xxx-DV-A_2x46_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xxx-DV-A, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+92
+92
+Connector_Samtec_HLE_SMD
+Samtec_HLE-146-02-xxx-DV-BE-A_2x46_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xxx-DV-BE-A, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+92
+92
+Connector_Samtec_HLE_SMD
+Samtec_HLE-146-02-xxx-DV-BE-LC_2x46_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xxx-DV-BE-LC, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+92
+92
+Connector_Samtec_HLE_SMD
+Samtec_HLE-146-02-xxx-DV-BE_2x46_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xxx-DV-BE, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+92
+92
+Connector_Samtec_HLE_SMD
+Samtec_HLE-146-02-xxx-DV-LC_2x46_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xxx-DV-LC, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+92
+92
+Connector_Samtec_HLE_SMD
+Samtec_HLE-146-02-xxx-DV_2x46_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xxx-DV, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+92
+92
+Connector_Samtec_HLE_SMD
+Samtec_HLE-147-02-xxx-DV-A_2x47_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xxx-DV-A, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+94
+94
+Connector_Samtec_HLE_SMD
+Samtec_HLE-147-02-xxx-DV-BE-A_2x47_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xxx-DV-BE-A, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+94
+94
+Connector_Samtec_HLE_SMD
+Samtec_HLE-147-02-xxx-DV-BE-LC_2x47_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xxx-DV-BE-LC, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+94
+94
+Connector_Samtec_HLE_SMD
+Samtec_HLE-147-02-xxx-DV-BE_2x47_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xxx-DV-BE, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+94
+94
+Connector_Samtec_HLE_SMD
+Samtec_HLE-147-02-xxx-DV-LC_2x47_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xxx-DV-LC, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+94
+94
+Connector_Samtec_HLE_SMD
+Samtec_HLE-147-02-xxx-DV_2x47_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xxx-DV, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+94
+94
+Connector_Samtec_HLE_SMD
+Samtec_HLE-148-02-xxx-DV-A_2x48_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xxx-DV-A, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+96
+96
+Connector_Samtec_HLE_SMD
+Samtec_HLE-148-02-xxx-DV-BE-A_2x48_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xxx-DV-BE-A, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+96
+96
+Connector_Samtec_HLE_SMD
+Samtec_HLE-148-02-xxx-DV-BE-LC_2x48_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xxx-DV-BE-LC, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+96
+96
+Connector_Samtec_HLE_SMD
+Samtec_HLE-148-02-xxx-DV-BE_2x48_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xxx-DV-BE, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+96
+96
+Connector_Samtec_HLE_SMD
+Samtec_HLE-148-02-xxx-DV-LC_2x48_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xxx-DV-LC, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+96
+96
+Connector_Samtec_HLE_SMD
+Samtec_HLE-148-02-xxx-DV_2x48_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xxx-DV, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+96
+96
+Connector_Samtec_HLE_SMD
+Samtec_HLE-149-02-xxx-DV-A_2x49_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xxx-DV-A, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+98
+98
+Connector_Samtec_HLE_SMD
+Samtec_HLE-149-02-xxx-DV-BE-A_2x49_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xxx-DV-BE-A, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+98
+98
+Connector_Samtec_HLE_SMD
+Samtec_HLE-149-02-xxx-DV-BE-LC_2x49_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xxx-DV-BE-LC, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+98
+98
+Connector_Samtec_HLE_SMD
+Samtec_HLE-149-02-xxx-DV-BE_2x49_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xxx-DV-BE, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+98
+98
+Connector_Samtec_HLE_SMD
+Samtec_HLE-149-02-xxx-DV-LC_2x49_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xxx-DV-LC, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+98
+98
+Connector_Samtec_HLE_SMD
+Samtec_HLE-149-02-xxx-DV_2x49_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xxx-DV, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+98
+98
+Connector_Samtec_HLE_SMD
+Samtec_HLE-150-02-xxx-DV-A_2x50_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xxx-DV-A, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+100
+100
+Connector_Samtec_HLE_SMD
+Samtec_HLE-150-02-xxx-DV-BE-A_2x50_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xxx-DV-BE-A, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+100
+100
+Connector_Samtec_HLE_SMD
+Samtec_HLE-150-02-xxx-DV-BE-LC_2x50_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xxx-DV-BE-LC, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+100
+100
+Connector_Samtec_HLE_SMD
+Samtec_HLE-150-02-xxx-DV-BE_2x50_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xxx-DV-BE, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+100
+100
+Connector_Samtec_HLE_SMD
+Samtec_HLE-150-02-xxx-DV-LC_2x50_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xxx-DV-LC, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+100
+100
+Connector_Samtec_HLE_SMD
+Samtec_HLE-150-02-xxx-DV_2x50_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xxx-DV, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+100
+100
+Connector_Samtec_HLE_THT
+Samtec_HLE-104-02-xx-DV-PE-LC_2x04_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xx-DV-PE-LC, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+8
+8
+Connector_Samtec_HLE_THT
+Samtec_HLE-104-02-xx-DV-PE_2x04_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xx-DV-PE (compatible alternatives: HLE-104-02-xx-DV-PE-BE), 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+8
+8
+Connector_Samtec_HLE_THT
+Samtec_HLE-104-02-xx-DV-TE_2x04_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xx-DV-TE, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+8
+8
+Connector_Samtec_HLE_THT
+Samtec_HLE-105-02-xx-DV-PE-LC_2x05_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xx-DV-PE-LC, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+10
+10
+Connector_Samtec_HLE_THT
+Samtec_HLE-105-02-xx-DV-PE_2x05_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xx-DV-PE (compatible alternatives: HLE-105-02-xx-DV-PE-BE), 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+10
+10
+Connector_Samtec_HLE_THT
+Samtec_HLE-105-02-xx-DV-TE_2x05_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xx-DV-TE, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+10
+10
+Connector_Samtec_HLE_THT
+Samtec_HLE-106-02-xx-DV-PE-LC_2x06_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xx-DV-PE-LC, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+12
+12
+Connector_Samtec_HLE_THT
+Samtec_HLE-106-02-xx-DV-PE_2x06_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xx-DV-PE (compatible alternatives: HLE-106-02-xx-DV-PE-BE), 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+12
+12
+Connector_Samtec_HLE_THT
+Samtec_HLE-106-02-xx-DV-TE_2x06_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xx-DV-TE, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+12
+12
+Connector_Samtec_HLE_THT
+Samtec_HLE-107-02-xx-DV-PE-LC_2x07_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xx-DV-PE-LC, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+14
+14
+Connector_Samtec_HLE_THT
+Samtec_HLE-107-02-xx-DV-PE_2x07_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xx-DV-PE (compatible alternatives: HLE-107-02-xx-DV-PE-BE), 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+14
+14
+Connector_Samtec_HLE_THT
+Samtec_HLE-107-02-xx-DV-TE_2x07_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xx-DV-TE, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+14
+14
+Connector_Samtec_HLE_THT
+Samtec_HLE-108-02-xx-DV-PE-LC_2x08_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xx-DV-PE-LC, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+16
+16
+Connector_Samtec_HLE_THT
+Samtec_HLE-108-02-xx-DV-PE_2x08_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xx-DV-PE (compatible alternatives: HLE-108-02-xx-DV-PE-BE), 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+16
+16
+Connector_Samtec_HLE_THT
+Samtec_HLE-108-02-xx-DV-TE_2x08_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xx-DV-TE, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+16
+16
+Connector_Samtec_HLE_THT
+Samtec_HLE-109-02-xx-DV-PE-LC_2x09_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xx-DV-PE-LC, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+18
+18
+Connector_Samtec_HLE_THT
+Samtec_HLE-109-02-xx-DV-PE_2x09_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xx-DV-PE (compatible alternatives: HLE-109-02-xx-DV-PE-BE), 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+18
+18
+Connector_Samtec_HLE_THT
+Samtec_HLE-109-02-xx-DV-TE_2x09_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xx-DV-TE, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+18
+18
+Connector_Samtec_HLE_THT
+Samtec_HLE-110-02-xx-DV-PE-LC_2x10_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xx-DV-PE-LC, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+20
+20
+Connector_Samtec_HLE_THT
+Samtec_HLE-110-02-xx-DV-PE_2x10_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xx-DV-PE (compatible alternatives: HLE-110-02-xx-DV-PE-BE), 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+20
+20
+Connector_Samtec_HLE_THT
+Samtec_HLE-110-02-xx-DV-TE_2x10_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xx-DV-TE, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+20
+20
+Connector_Samtec_HLE_THT
+Samtec_HLE-111-02-xx-DV-PE-LC_2x11_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xx-DV-PE-LC, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+22
+22
+Connector_Samtec_HLE_THT
+Samtec_HLE-111-02-xx-DV-PE_2x11_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xx-DV-PE (compatible alternatives: HLE-111-02-xx-DV-PE-BE), 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+22
+22
+Connector_Samtec_HLE_THT
+Samtec_HLE-111-02-xx-DV-TE_2x11_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xx-DV-TE, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+22
+22
+Connector_Samtec_HLE_THT
+Samtec_HLE-112-02-xx-DV-PE-LC_2x12_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xx-DV-PE-LC, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+24
+24
+Connector_Samtec_HLE_THT
+Samtec_HLE-112-02-xx-DV-PE_2x12_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xx-DV-PE (compatible alternatives: HLE-112-02-xx-DV-PE-BE), 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+24
+24
+Connector_Samtec_HLE_THT
+Samtec_HLE-112-02-xx-DV-TE_2x12_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xx-DV-TE, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+24
+24
+Connector_Samtec_HLE_THT
+Samtec_HLE-113-02-xx-DV-PE-LC_2x13_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xx-DV-PE-LC, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+26
+26
+Connector_Samtec_HLE_THT
+Samtec_HLE-113-02-xx-DV-PE_2x13_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xx-DV-PE (compatible alternatives: HLE-113-02-xx-DV-PE-BE), 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+26
+26
+Connector_Samtec_HLE_THT
+Samtec_HLE-113-02-xx-DV-TE_2x13_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xx-DV-TE, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+26
+26
+Connector_Samtec_HLE_THT
+Samtec_HLE-114-02-xx-DV-PE-LC_2x14_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xx-DV-PE-LC, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+28
+28
+Connector_Samtec_HLE_THT
+Samtec_HLE-114-02-xx-DV-PE_2x14_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xx-DV-PE (compatible alternatives: HLE-114-02-xx-DV-PE-BE), 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+28
+28
+Connector_Samtec_HLE_THT
+Samtec_HLE-114-02-xx-DV-TE_2x14_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xx-DV-TE, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+28
+28
+Connector_Samtec_HLE_THT
+Samtec_HLE-115-02-xx-DV-PE-LC_2x15_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xx-DV-PE-LC, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+30
+30
+Connector_Samtec_HLE_THT
+Samtec_HLE-115-02-xx-DV-PE_2x15_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xx-DV-PE (compatible alternatives: HLE-115-02-xx-DV-PE-BE), 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+30
+30
+Connector_Samtec_HLE_THT
+Samtec_HLE-115-02-xx-DV-TE_2x15_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xx-DV-TE, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+30
+30
+Connector_Samtec_HLE_THT
+Samtec_HLE-116-02-xx-DV-PE-LC_2x16_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xx-DV-PE-LC, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+32
+32
+Connector_Samtec_HLE_THT
+Samtec_HLE-116-02-xx-DV-PE_2x16_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xx-DV-PE (compatible alternatives: HLE-116-02-xx-DV-PE-BE), 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+32
+32
+Connector_Samtec_HLE_THT
+Samtec_HLE-116-02-xx-DV-TE_2x16_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xx-DV-TE, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+32
+32
+Connector_Samtec_HLE_THT
+Samtec_HLE-117-02-xx-DV-PE-LC_2x17_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xx-DV-PE-LC, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+34
+34
+Connector_Samtec_HLE_THT
+Samtec_HLE-117-02-xx-DV-PE_2x17_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xx-DV-PE (compatible alternatives: HLE-117-02-xx-DV-PE-BE), 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+34
+34
+Connector_Samtec_HLE_THT
+Samtec_HLE-117-02-xx-DV-TE_2x17_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xx-DV-TE, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+34
+34
+Connector_Samtec_HLE_THT
+Samtec_HLE-118-02-xx-DV-PE-LC_2x18_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xx-DV-PE-LC, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+36
+36
+Connector_Samtec_HLE_THT
+Samtec_HLE-118-02-xx-DV-PE_2x18_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xx-DV-PE (compatible alternatives: HLE-118-02-xx-DV-PE-BE), 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+36
+36
+Connector_Samtec_HLE_THT
+Samtec_HLE-118-02-xx-DV-TE_2x18_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xx-DV-TE, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+36
+36
+Connector_Samtec_HLE_THT
+Samtec_HLE-119-02-xx-DV-PE-LC_2x19_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xx-DV-PE-LC, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+38
+38
+Connector_Samtec_HLE_THT
+Samtec_HLE-119-02-xx-DV-PE_2x19_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xx-DV-PE (compatible alternatives: HLE-119-02-xx-DV-PE-BE), 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+38
+38
+Connector_Samtec_HLE_THT
+Samtec_HLE-119-02-xx-DV-TE_2x19_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xx-DV-TE, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+38
+38
+Connector_Samtec_HLE_THT
+Samtec_HLE-120-02-xx-DV-PE-LC_2x20_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xx-DV-PE-LC, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+40
+40
+Connector_Samtec_HLE_THT
+Samtec_HLE-120-02-xx-DV-PE_2x20_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xx-DV-PE (compatible alternatives: HLE-120-02-xx-DV-PE-BE), 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+40
+40
+Connector_Samtec_HLE_THT
+Samtec_HLE-120-02-xx-DV-TE_2x20_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xx-DV-TE, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+40
+40
+Connector_Samtec_HLE_THT
+Samtec_HLE-121-02-xx-DV-PE-LC_2x21_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xx-DV-PE-LC, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+42
+42
+Connector_Samtec_HLE_THT
+Samtec_HLE-121-02-xx-DV-PE_2x21_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xx-DV-PE (compatible alternatives: HLE-121-02-xx-DV-PE-BE), 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+42
+42
+Connector_Samtec_HLE_THT
+Samtec_HLE-121-02-xx-DV-TE_2x21_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xx-DV-TE, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+42
+42
+Connector_Samtec_HLE_THT
+Samtec_HLE-122-02-xx-DV-PE-LC_2x22_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xx-DV-PE-LC, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+44
+44
+Connector_Samtec_HLE_THT
+Samtec_HLE-122-02-xx-DV-PE_2x22_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xx-DV-PE (compatible alternatives: HLE-122-02-xx-DV-PE-BE), 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+44
+44
+Connector_Samtec_HLE_THT
+Samtec_HLE-122-02-xx-DV-TE_2x22_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xx-DV-TE, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+44
+44
+Connector_Samtec_HLE_THT
+Samtec_HLE-123-02-xx-DV-PE-LC_2x23_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xx-DV-PE-LC, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+46
+46
+Connector_Samtec_HLE_THT
+Samtec_HLE-123-02-xx-DV-PE_2x23_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xx-DV-PE (compatible alternatives: HLE-123-02-xx-DV-PE-BE), 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+46
+46
+Connector_Samtec_HLE_THT
+Samtec_HLE-123-02-xx-DV-TE_2x23_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xx-DV-TE, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+46
+46
+Connector_Samtec_HLE_THT
+Samtec_HLE-124-02-xx-DV-PE-LC_2x24_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xx-DV-PE-LC, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+48
+48
+Connector_Samtec_HLE_THT
+Samtec_HLE-124-02-xx-DV-PE_2x24_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xx-DV-PE (compatible alternatives: HLE-124-02-xx-DV-PE-BE), 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+48
+48
+Connector_Samtec_HLE_THT
+Samtec_HLE-124-02-xx-DV-TE_2x24_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xx-DV-TE, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+48
+48
+Connector_Samtec_HLE_THT
+Samtec_HLE-125-02-xx-DV-PE-LC_2x25_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xx-DV-PE-LC, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+50
+50
+Connector_Samtec_HLE_THT
+Samtec_HLE-125-02-xx-DV-PE_2x25_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xx-DV-PE (compatible alternatives: HLE-125-02-xx-DV-PE-BE), 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+50
+50
+Connector_Samtec_HLE_THT
+Samtec_HLE-125-02-xx-DV-TE_2x25_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xx-DV-TE, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+50
+50
+Connector_Samtec_HLE_THT
+Samtec_HLE-126-02-xx-DV-PE-LC_2x26_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xx-DV-PE-LC, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+52
+52
+Connector_Samtec_HLE_THT
+Samtec_HLE-126-02-xx-DV-PE_2x26_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xx-DV-PE (compatible alternatives: HLE-126-02-xx-DV-PE-BE), 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+52
+52
+Connector_Samtec_HLE_THT
+Samtec_HLE-126-02-xx-DV-TE_2x26_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xx-DV-TE, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+52
+52
+Connector_Samtec_HLE_THT
+Samtec_HLE-127-02-xx-DV-PE-LC_2x27_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xx-DV-PE-LC, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+54
+54
+Connector_Samtec_HLE_THT
+Samtec_HLE-127-02-xx-DV-PE_2x27_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xx-DV-PE (compatible alternatives: HLE-127-02-xx-DV-PE-BE), 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+54
+54
+Connector_Samtec_HLE_THT
+Samtec_HLE-127-02-xx-DV-TE_2x27_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xx-DV-TE, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+54
+54
+Connector_Samtec_HLE_THT
+Samtec_HLE-128-02-xx-DV-PE-LC_2x28_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xx-DV-PE-LC, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+56
+56
+Connector_Samtec_HLE_THT
+Samtec_HLE-128-02-xx-DV-PE_2x28_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xx-DV-PE (compatible alternatives: HLE-128-02-xx-DV-PE-BE), 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+56
+56
+Connector_Samtec_HLE_THT
+Samtec_HLE-128-02-xx-DV-TE_2x28_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xx-DV-TE, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+56
+56
+Connector_Samtec_HLE_THT
+Samtec_HLE-129-02-xx-DV-PE-LC_2x29_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xx-DV-PE-LC, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+58
+58
+Connector_Samtec_HLE_THT
+Samtec_HLE-129-02-xx-DV-PE_2x29_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xx-DV-PE (compatible alternatives: HLE-129-02-xx-DV-PE-BE), 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+58
+58
+Connector_Samtec_HLE_THT
+Samtec_HLE-129-02-xx-DV-TE_2x29_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xx-DV-TE, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+58
+58
+Connector_Samtec_HLE_THT
+Samtec_HLE-130-02-xx-DV-PE-LC_2x30_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xx-DV-PE-LC, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+60
+60
+Connector_Samtec_HLE_THT
+Samtec_HLE-130-02-xx-DV-PE_2x30_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xx-DV-PE (compatible alternatives: HLE-130-02-xx-DV-PE-BE), 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+60
+60
+Connector_Samtec_HLE_THT
+Samtec_HLE-130-02-xx-DV-TE_2x30_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xx-DV-TE, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+60
+60
+Connector_Samtec_HLE_THT
+Samtec_HLE-131-02-xx-DV-PE-LC_2x31_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xx-DV-PE-LC, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+62
+62
+Connector_Samtec_HLE_THT
+Samtec_HLE-131-02-xx-DV-PE_2x31_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xx-DV-PE (compatible alternatives: HLE-131-02-xx-DV-PE-BE), 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+62
+62
+Connector_Samtec_HLE_THT
+Samtec_HLE-131-02-xx-DV-TE_2x31_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xx-DV-TE, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+62
+62
+Connector_Samtec_HLE_THT
+Samtec_HLE-132-02-xx-DV-PE-LC_2x32_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xx-DV-PE-LC, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+64
+64
+Connector_Samtec_HLE_THT
+Samtec_HLE-132-02-xx-DV-PE_2x32_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xx-DV-PE (compatible alternatives: HLE-132-02-xx-DV-PE-BE), 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+64
+64
+Connector_Samtec_HLE_THT
+Samtec_HLE-132-02-xx-DV-TE_2x32_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xx-DV-TE, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+64
+64
+Connector_Samtec_HLE_THT
+Samtec_HLE-133-02-xx-DV-PE-LC_2x33_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xx-DV-PE-LC, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+66
+66
+Connector_Samtec_HLE_THT
+Samtec_HLE-133-02-xx-DV-PE_2x33_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xx-DV-PE (compatible alternatives: HLE-133-02-xx-DV-PE-BE), 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+66
+66
+Connector_Samtec_HLE_THT
+Samtec_HLE-133-02-xx-DV-TE_2x33_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xx-DV-TE, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+66
+66
+Connector_Samtec_HLE_THT
+Samtec_HLE-134-02-xx-DV-PE-LC_2x34_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xx-DV-PE-LC, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+68
+68
+Connector_Samtec_HLE_THT
+Samtec_HLE-134-02-xx-DV-PE_2x34_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xx-DV-PE (compatible alternatives: HLE-134-02-xx-DV-PE-BE), 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+68
+68
+Connector_Samtec_HLE_THT
+Samtec_HLE-134-02-xx-DV-TE_2x34_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xx-DV-TE, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+68
+68
+Connector_Samtec_HLE_THT
+Samtec_HLE-135-02-xx-DV-PE-LC_2x35_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xx-DV-PE-LC, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+70
+70
+Connector_Samtec_HLE_THT
+Samtec_HLE-135-02-xx-DV-PE_2x35_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xx-DV-PE (compatible alternatives: HLE-135-02-xx-DV-PE-BE), 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+70
+70
+Connector_Samtec_HLE_THT
+Samtec_HLE-135-02-xx-DV-TE_2x35_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xx-DV-TE, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+70
+70
+Connector_Samtec_HLE_THT
+Samtec_HLE-136-02-xx-DV-PE-LC_2x36_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xx-DV-PE-LC, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+72
+72
+Connector_Samtec_HLE_THT
+Samtec_HLE-136-02-xx-DV-PE_2x36_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xx-DV-PE (compatible alternatives: HLE-136-02-xx-DV-PE-BE), 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+72
+72
+Connector_Samtec_HLE_THT
+Samtec_HLE-136-02-xx-DV-TE_2x36_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xx-DV-TE, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+72
+72
+Connector_Samtec_HLE_THT
+Samtec_HLE-137-02-xx-DV-PE-LC_2x37_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xx-DV-PE-LC, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+74
+74
+Connector_Samtec_HLE_THT
+Samtec_HLE-137-02-xx-DV-PE_2x37_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xx-DV-PE (compatible alternatives: HLE-137-02-xx-DV-PE-BE), 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+74
+74
+Connector_Samtec_HLE_THT
+Samtec_HLE-137-02-xx-DV-TE_2x37_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xx-DV-TE, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+74
+74
+Connector_Samtec_HLE_THT
+Samtec_HLE-138-02-xx-DV-PE-LC_2x38_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xx-DV-PE-LC, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+76
+76
+Connector_Samtec_HLE_THT
+Samtec_HLE-138-02-xx-DV-PE_2x38_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xx-DV-PE (compatible alternatives: HLE-138-02-xx-DV-PE-BE), 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+76
+76
+Connector_Samtec_HLE_THT
+Samtec_HLE-138-02-xx-DV-TE_2x38_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xx-DV-TE, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+76
+76
+Connector_Samtec_HLE_THT
+Samtec_HLE-139-02-xx-DV-PE-LC_2x39_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xx-DV-PE-LC, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+78
+78
+Connector_Samtec_HLE_THT
+Samtec_HLE-139-02-xx-DV-PE_2x39_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xx-DV-PE (compatible alternatives: HLE-139-02-xx-DV-PE-BE), 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+78
+78
+Connector_Samtec_HLE_THT
+Samtec_HLE-139-02-xx-DV-TE_2x39_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xx-DV-TE, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+78
+78
+Connector_Samtec_HLE_THT
+Samtec_HLE-140-02-xx-DV-PE-LC_2x40_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xx-DV-PE-LC, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+80
+80
+Connector_Samtec_HLE_THT
+Samtec_HLE-140-02-xx-DV-PE_2x40_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xx-DV-PE (compatible alternatives: HLE-140-02-xx-DV-PE-BE), 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+80
+80
+Connector_Samtec_HLE_THT
+Samtec_HLE-140-02-xx-DV-TE_2x40_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xx-DV-TE, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+80
+80
+Connector_Samtec_HLE_THT
+Samtec_HLE-141-02-xx-DV-PE-LC_2x41_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xx-DV-PE-LC, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+82
+82
+Connector_Samtec_HLE_THT
+Samtec_HLE-141-02-xx-DV-PE_2x41_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xx-DV-PE (compatible alternatives: HLE-141-02-xx-DV-PE-BE), 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+82
+82
+Connector_Samtec_HLE_THT
+Samtec_HLE-141-02-xx-DV-TE_2x41_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xx-DV-TE, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+82
+82
+Connector_Samtec_HLE_THT
+Samtec_HLE-142-02-xx-DV-PE-LC_2x42_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xx-DV-PE-LC, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+84
+84
+Connector_Samtec_HLE_THT
+Samtec_HLE-142-02-xx-DV-PE_2x42_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xx-DV-PE (compatible alternatives: HLE-142-02-xx-DV-PE-BE), 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+84
+84
+Connector_Samtec_HLE_THT
+Samtec_HLE-142-02-xx-DV-TE_2x42_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xx-DV-TE, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+84
+84
+Connector_Samtec_HLE_THT
+Samtec_HLE-143-02-xx-DV-PE-LC_2x43_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xx-DV-PE-LC, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+86
+86
+Connector_Samtec_HLE_THT
+Samtec_HLE-143-02-xx-DV-PE_2x43_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xx-DV-PE (compatible alternatives: HLE-143-02-xx-DV-PE-BE), 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+86
+86
+Connector_Samtec_HLE_THT
+Samtec_HLE-143-02-xx-DV-TE_2x43_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xx-DV-TE, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+86
+86
+Connector_Samtec_HLE_THT
+Samtec_HLE-144-02-xx-DV-PE-LC_2x44_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xx-DV-PE-LC, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+88
+88
+Connector_Samtec_HLE_THT
+Samtec_HLE-144-02-xx-DV-PE_2x44_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xx-DV-PE (compatible alternatives: HLE-144-02-xx-DV-PE-BE), 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+88
+88
+Connector_Samtec_HLE_THT
+Samtec_HLE-144-02-xx-DV-TE_2x44_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xx-DV-TE, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+88
+88
+Connector_Samtec_HLE_THT
+Samtec_HLE-145-02-xx-DV-PE-LC_2x45_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xx-DV-PE-LC, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+90
+90
+Connector_Samtec_HLE_THT
+Samtec_HLE-145-02-xx-DV-PE_2x45_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xx-DV-PE (compatible alternatives: HLE-145-02-xx-DV-PE-BE), 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+90
+90
+Connector_Samtec_HLE_THT
+Samtec_HLE-145-02-xx-DV-TE_2x45_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xx-DV-TE, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+90
+90
+Connector_Samtec_HLE_THT
+Samtec_HLE-146-02-xx-DV-PE-LC_2x46_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xx-DV-PE-LC, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+92
+92
+Connector_Samtec_HLE_THT
+Samtec_HLE-146-02-xx-DV-PE_2x46_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xx-DV-PE (compatible alternatives: HLE-146-02-xx-DV-PE-BE), 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+92
+92
+Connector_Samtec_HLE_THT
+Samtec_HLE-146-02-xx-DV-TE_2x46_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xx-DV-TE, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+92
+92
+Connector_Samtec_HLE_THT
+Samtec_HLE-147-02-xx-DV-PE-LC_2x47_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xx-DV-PE-LC, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+94
+94
+Connector_Samtec_HLE_THT
+Samtec_HLE-147-02-xx-DV-PE_2x47_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xx-DV-PE (compatible alternatives: HLE-147-02-xx-DV-PE-BE), 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+94
+94
+Connector_Samtec_HLE_THT
+Samtec_HLE-147-02-xx-DV-TE_2x47_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xx-DV-TE, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+94
+94
+Connector_Samtec_HLE_THT
+Samtec_HLE-148-02-xx-DV-PE-LC_2x48_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xx-DV-PE-LC, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+96
+96
+Connector_Samtec_HLE_THT
+Samtec_HLE-148-02-xx-DV-PE_2x48_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xx-DV-PE (compatible alternatives: HLE-148-02-xx-DV-PE-BE), 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+96
+96
+Connector_Samtec_HLE_THT
+Samtec_HLE-148-02-xx-DV-TE_2x48_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xx-DV-TE, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+96
+96
+Connector_Samtec_HLE_THT
+Samtec_HLE-149-02-xx-DV-PE-LC_2x49_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xx-DV-PE-LC, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+98
+98
+Connector_Samtec_HLE_THT
+Samtec_HLE-149-02-xx-DV-PE_2x49_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xx-DV-PE (compatible alternatives: HLE-149-02-xx-DV-PE-BE), 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+98
+98
+Connector_Samtec_HLE_THT
+Samtec_HLE-149-02-xx-DV-TE_2x49_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xx-DV-TE, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+98
+98
+Connector_Samtec_HLE_THT
+Samtec_HLE-150-02-xx-DV-PE-LC_2x50_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xx-DV-PE-LC, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+100
+100
+Connector_Samtec_HLE_THT
+Samtec_HLE-150-02-xx-DV-PE_2x50_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xx-DV-PE (compatible alternatives: HLE-150-02-xx-DV-PE-BE), 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+100
+100
+Connector_Samtec_HLE_THT
+Samtec_HLE-150-02-xx-DV-TE_2x50_P2.54mm_Horizontal
+Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xx-DV-TE, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator
+connector Samtec HLE top entry
+0
+100
+100
+Connector_Stocko
+Stocko_MKS_1651-6-0-202_1x2_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+2
+2
+Connector_Stocko
+Stocko_MKS_1652-6-0-202_1x2_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+2
+2
+Connector_Stocko
+Stocko_MKS_1653-6-0-303_1x3_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+3
+3
+Connector_Stocko
+Stocko_MKS_1654-6-0-404_1x4_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+4
+4
+Connector_Stocko
+Stocko_MKS_1655-6-0-505_1x5_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+5
+5
+Connector_Stocko
+Stocko_MKS_1656-6-0-606_1x6_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+6
+6
+Connector_Stocko
+Stocko_MKS_1657-6-0-707_1x7_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+7
+7
+Connector_Stocko
+Stocko_MKS_1658-6-0-808_1x8_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+8
+8
+Connector_Stocko
+Stocko_MKS_1659-6-0-909_1x9_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+9
+9
+Connector_Stocko
+Stocko_MKS_1660-6-0-1010_1x10_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+10
+10
+Connector_Stocko
+Stocko_MKS_1661-6-0-1111_1x11_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+11
+11
+Connector_Stocko
+Stocko_MKS_1662-6-0-1212_1x12_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+12
+12
+Connector_Stocko
+Stocko_MKS_1663-6-0-1313_1x13_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+13
+13
+Connector_Stocko
+Stocko_MKS_1664-6-0-1414_1x14_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+14
+14
+Connector_Stocko
+Stocko_MKS_1665-6-0-1515_1x15_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+15
+15
+Connector_Stocko
+Stocko_MKS_1666-6-0-1616_1x16_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+16
+16
+Connector_Stocko
+Stocko_MKS_1667-6-0-1717_1x17_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+17
+17
+Connector_Stocko
+Stocko_MKS_1668-6-0-1818_1x18_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+18
+18
+Connector_Stocko
+Stocko_MKS_1669-6-0-1919_1x19_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+19
+19
+Connector_Stocko
+Stocko_MKS_1670-6-0-2020_1x20_P2.50mm_Vertical
+Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator
+Stocko RFK MKS 16xx
+0
+20
+20
+Connector_TE-Connectivity
+TE_1-826576-3_1x13_P3.96mm_Vertical
+TE, 1-826576-3, 13 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator
+connector TE 826576 vertical
+0
+13
+13
+Connector_TE-Connectivity
+TE_1-826576-5_1x15_P3.96mm_Vertical
+TE, 1-826576-5, 15 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator
+connector TE 826576 vertical
+0
+15
+15
+Connector_TE-Connectivity
+TE_1-826576-6_1x16_P3.96mm_Vertical
+TE, 1-826576-6, 16 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator
+connector TE 826576 vertical
+0
+16
+16
+Connector_TE-Connectivity
+TE_1-826576-7_1x17_P3.96mm_Vertical
+TE, 1-826576-7, 17 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator
+connector TE 826576 vertical
+0
+17
+17
+Connector_TE-Connectivity
+TE_1-826576-8_1x18_P3.96mm_Vertical
+TE, 1-826576-8, 18 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator
+connector TE 826576 vertical
+0
+18
+18
+Connector_TE-Connectivity
+TE_2-826576-0_1x20_P3.96mm_Vertical
+TE, 2-826576-0, 20 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator
+connector TE 826576 vertical
+0
+20
+20
+Connector_TE-Connectivity
+TE_3-826576-6_1x36_P3.96mm_Vertical
+TE, 3-826576-6, 36 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator
+connector TE 826576 vertical
+0
+36
+36
+Connector_TE-Connectivity
+TE_826576-2_1x02_P3.96mm_Vertical
+TE, 826576-2, 2 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator
+connector TE 826576 vertical
+0
+2
+2
+Connector_TE-Connectivity
+TE_826576-3_1x03_P3.96mm_Vertical
+TE, 826576-3, 3 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator
+connector TE 826576 vertical
+0
+3
+3
+Connector_TE-Connectivity
+TE_826576-5_1x05_P3.96mm_Vertical
+TE, 826576-5, 5 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator
+connector TE 826576 vertical
+0
+5
+5
+Connector_TE-Connectivity
+TE_826576-6_1x06_P3.96mm_Vertical
+TE, 826576-6, 6 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator
+connector TE 826576 vertical
+0
+6
+6
+Connector_TE-Connectivity
+TE_826576-7_1x07_P3.96mm_Vertical
+TE, 826576-7, 7 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator
+connector TE 826576 vertical
+0
+7
+7
+Connector_TE-Connectivity
+TE_826576-8_1x08_P3.96mm_Vertical
+TE, 826576-8, 8 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator
+connector TE 826576 vertical
+0
+8
+8
+Connector_TE-Connectivity
+TE_826576-9_1x09_P3.96mm_Vertical
+TE, 826576-9, 9 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator
+connector TE 826576 vertical
+0
+9
+9
+Connector_TE-Connectivity
+TE_AMPSEAL_1-776087-x_3Rows_23_P0.4mm_Horizontal
+Connector
+TE 776087
+0
+23
+23
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-770182-x_3x03_P4.14mm_Vertical
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770182-x, 3 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK side entry
+0
+9
+9
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-770186-x_3x04_P4.14mm_Vertical
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770186-x, 4 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK side entry
+0
+12
+12
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-770190-x_3x05_P4.14mm_Vertical
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770190-x, 5 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK side entry
+0
+15
+15
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-770621-x_2x06_P4.14mm_Vertical
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770621-x, 6 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK side entry
+0
+12
+12
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-770858-x_2x05_P4.14mm_Vertical
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770858-x, 5 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK side entry
+0
+10
+10
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-770866-x_1x02_P4.14mm_Vertical
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770866-x, 2 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK side entry
+0
+2
+2
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-770870-x_1x03_P4.14mm_Vertical
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770870-x, 3 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK side entry
+0
+3
+3
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-770874-x_2x02_P4.14mm_Vertical
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770874-x, 2 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK side entry
+0
+4
+4
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-770875-x_2x03_P4.14mm_Vertical
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770875-x, 3 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK side entry
+0
+6
+6
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-770966-x_1x02_P4.14mm_Horizontal
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770966-x, 2 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK top entry
+0
+2
+2
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-770967-x_1x03_P4.14mm_Horizontal
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770967-x, 3 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK top entry
+0
+3
+3
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-770968-x_2x02_P4.14mm_Horizontal
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770968-x, 2 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK top entry
+0
+4
+4
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-770969-x_2x03_P4.14mm_Horizontal
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770969-x, 3 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK top entry
+0
+6
+6
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-770970-x_2x04_P4.14mm_Horizontal
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770970-x, 4 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK top entry
+0
+8
+8
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-770971-x_2x05_P4.14mm_Horizontal
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770971-x, 5 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK top entry
+0
+10
+10
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-770972-x_2x06_P4.14mm_Horizontal
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770972-x, 6 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK top entry
+0
+12
+12
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-770973-x_2x07_P4.14mm_Horizontal
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770973-x, 7 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK top entry
+0
+14
+14
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-770974-x_2x08_P4.14mm_Horizontal
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770974-x, 8 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK top entry
+0
+16
+16
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-794067-x_2x07_P4.14mm_Vertical
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794067-x, 7 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK side entry
+0
+14
+14
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-794068-x_2x08_P4.14mm_Vertical
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794068-x, 8 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK side entry
+0
+16
+16
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-794069-x_2x09_P4.14mm_Vertical
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794069-x, 9 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK side entry
+0
+18
+18
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-794070-x_2x10_P4.14mm_Vertical
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794070-x, 10 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK side entry
+0
+20
+20
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-794071-x_2x11_P4.14mm_Vertical
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794071-x, 11 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK side entry
+0
+22
+22
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-794072-x_2x12_P4.14mm_Vertical
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794072-x, 12 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK side entry
+0
+24
+24
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-794073-x_2x04_P4.14mm_Vertical
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794073-x, 4 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK side entry
+0
+8
+8
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-794105-x_2x09_P4.14mm_Horizontal
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794105-x, 9 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK top entry
+0
+18
+18
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-794106-x_2x10_P4.14mm_Horizontal
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794106-x, 10 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK top entry
+0
+20
+20
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-794107-x_2x11_P4.14mm_Horizontal
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794107-x, 11 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK top entry
+0
+22
+22
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-794108-x_2x12_P4.14mm_Horizontal
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794108-x, 12 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK top entry
+0
+24
+24
+Connector_TE-Connectivity
+TE_MATE-N-LOK_1-794374-x_1x01_P4.14mm_Horizontal
+Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794374-x, 1 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator
+connector TE MATE-N-LOK top entry
+0
+1
+1
+Connector_TE-Connectivity
+TE_MATE-N-LOK_350211-1_1x04_P5.08mm_Vertical
+https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F350211%7FU5%7Fpdf%7FEnglish%7FENG_CD_350211_U5.pdf%7F350211-1
+connector TE MATE-N-LOK top entry ATA PATA IDE 5.25 inch floppy drive power
+0
+4
+4
+Connector_USB
+USB3_A_Molex_48393-001
+USB 3.0, type A, right angle (http://www.molex.com/pdm_docs/sd/483930003_sd.pdf)
+USB 3.0 type A right angle
+0
+13
+10
+Connector_USB
+USB3_A_Plug_Wuerth_692112030100_Horizontal
+USB type A Plug, Horizontal, http://katalog.we-online.de/em/datasheet/692112030100.pdf
+usb A plug horizontal
+0
+11
+10
+Connector_USB
+USB_A_CNCTech_1001-011-01101_Horizontal
+http://cnctech.us/pdfs/1001-011-01101.pdf
+USB-A
+0
+6
+5
+Connector_USB
+USB_A_Molex_105057_Vertical
+https://www.molex.com/pdm_docs/sd/1050570001_sd.pdf
+USB A Vertical
+0
+7
+5
+Connector_USB
+USB_A_Stewart_SS-52100-001_Horizontal
+USB A connector https://belfuse.com/resources/drawings/stewartconnector/dr-stw-ss-52100-001.pdf
+USB_A Female Connector receptacle
+0
+6
+5
+Connector_USB
+USB_A_Wuerth_61400826021_Horizontal_Stacked
+Stacked USB A connector http://katalog.we-online.de/em/datasheet/61400826021.pdf
+Wuerth stacked USB_A
+0
+12
+9
+Connector_USB
+USB_B_Amphenol_MUSB-D511_Vertical_Rugged
+A,phenol MUSB_D511, USB B female connector, straight, rugged, https://www.amphenolcanada.com/ProductSearch/drawings/AC/MUSBD511XX.pdf
+USB_B_MUSB_Straight female connector straight rugged MUSB D511
+0
+6
+5
+Connector_USB
+USB_B_OST_USB-B1HSxx_Horizontal
+USB B receptacle, Horizontal, through-hole, http://www.on-shore.com/wp-content/uploads/2015/09/usb-b1hsxx.pdf
+USB-B receptacle horizontal through-hole
+0
+6
+5
+Connector_USB
+USB_B_TE_5787834_Vertical
+http://www.mouser.com/ds/2/418/NG_CD_5787834_A4-669110.pdf
+USB_B USB B vertical female connector
+0
+6
+5
+Connector_USB
+USB_C_Plug_JAE_DX07P024AJ1
+Universal Serial Bus (USB) Shielded I/O Plug, Type C, Right Angle, Surface Mount, https://www.jae.com/en/searchfilter/?topics_keyword=DX07P024AJ1&mainItemSelect=1
+USB Type-C Plug Edge Mount
+0
+30
+25
+Connector_USB
+USB_C_Plug_Molex_105444
+Universal Serial Bus (USB) Shielded I/O Plug, Type C, Right Angle, Surface Mount, http://www.molex.com/pdm_docs/sd/1054440001_sd.pdf
+USB Type-C Plug Edge Mount
+0
+24
+23
+Connector_USB
+USB_C_Receptacle_Amphenol_12401548E4-2A
+USB TYPE C, RA RCPT PCB, Hybrid, https://www.amphenolcanada.com/StockAvailabilityPrice.aspx?From=&PartNum=12401548E4%7e2A
+USB C Type-C Receptacle Hybrid
+0
+28
+25
+Connector_USB
+USB_C_Receptacle_Amphenol_12401548E4-2A_CircularHoles
+USB TYPE C, RA RCPT PCB, Hybrid, https://www.amphenolcanada.com/StockAvailabilityPrice.aspx?From=&PartNum=12401548E4%7e2A
+USB C Type-C Receptacle Hybrid
+0
+28
+25
+Connector_USB
+USB_C_Receptacle_Amphenol_12401610E4-2A
+USB TYPE C, RA RCPT PCB, SMT, https://www.amphenolcanada.com/StockAvailabilityPrice.aspx?From=&PartNum=12401610E4%7e2A
+USB C Type-C Receptacle SMD
+0
+28
+25
+Connector_USB
+USB_C_Receptacle_Amphenol_12401610E4-2A_CircularHoles
+USB TYPE C, RA RCPT PCB, SMT, https://www.amphenolcanada.com/StockAvailabilityPrice.aspx?From=&PartNum=12401610E4%7e2A
+USB C Type-C Receptacle SMD
+0
+28
+25
+Connector_USB
+USB_C_Receptacle_GCT_USB4085
+USB 2.0 Type C Receptacle, https://gct.co/Files/Drawings/USB4085.pdf
+USB Type-C Receptacle Through-hole Right angle
+0
+20
+17
+Connector_USB
+USB_C_Receptacle_HRO_TYPE-C-31-M-12
+USB Type-C receptacle for USB 2.0 and PD, http://www.krhro.com/uploads/soft/180320/1-1P320120243.pdf
+usb usb-c 2.0 pd
+0
+20
+17
+Connector_USB
+USB_C_Receptacle_JAE_DX07S024WJ1R350
+http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ117219.pdf
+USB C Type-C Receptacle SMD
+0
+30
+25
+Connector_USB
+USB_C_Receptacle_JAE_DX07S024WJ3R400
+USB TYPE C, VERT RCPT PCB, SMT, http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ117928.pdf
+USB C Type-C Receptacle SMD
+0
+28
+25
+Connector_USB
+USB_C_Receptacle_Palconn_UTC16-G
+http://www.palpilot.com/wp-content/uploads/2017/05/UTC027-GKN-OR-Rev-A.pdf
+USB C Type-C Receptacle USB2.0
+0
+20
+17
+Connector_USB
+USB_Micro-AB_Molex_47590-0001
+Micro USB AB receptable, right-angle inverted (https://www.molex.com/pdm_docs/sd/475900001_sd.pdf)
+Micro AB USB SMD
+0
+14
+6
+Connector_USB
+USB_Micro-B_Amphenol_10103594-0001LF_Horizontal
+Micro USB Type B 10103594-0001LF, http://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/10103594.pdf
+USB USB_B USB_micro USB_OTG
+0
+17
+6
+Connector_USB
+USB_Micro-B_GCT_USB3076-30-A
+GCT Micro USB https://gct.co/files/drawings/usb3076.pdf
+Micro-USB SMD Typ-B GCT
+0
+11
+6
+Connector_USB
+USB_Micro-B_Molex-105017-0001
+http://www.molex.com/pdm_docs/sd/1050170001_sd.pdf
+Micro-USB SMD Typ-B
+0
+13
+6
+Connector_USB
+USB_Micro-B_Molex-105133-0001
+Molex Vertical Micro USB Typ-B (http://www.molex.com/pdm_docs/sd/1051330001_sd.pdf)
+Micro-USB SMD Typ-B Vertical
+0
+8
+6
+Connector_USB
+USB_Micro-B_Molex-105133-0031
+Molex Vertical Micro USB Typ-B (http://www.molex.com/pdm_docs/sd/1051330031_sd.pdf)
+Micro-USB SMD Typ-B Vertical
+0
+8
+6
+Connector_USB
+USB_Micro-B_Molex_47346-0001
+Micro USB B receptable with flange, bottom-mount, SMD, right-angle (http://www.molex.com/pdm_docs/sd/473460001_sd.pdf)
+Micro B USB SMD
+0
+11
+6
+Connector_USB
+USB_Micro-B_Wuerth_614105150721_Vertical
+USB Micro-B receptacle, through-hole, vertical, http://katalog.we-online.de/em/datasheet/614105150721.pdf
+usb micro receptacle vertical
+0
+7
+6
+Connector_USB
+USB_Micro-B_Wuerth_614105150721_Vertical_CircularHoles
+USB Micro-B receptacle, through-hole, vertical, http://katalog.we-online.de/em/datasheet/614105150721.pdf
+usb micro receptacle vertical
+0
+7
+6
+Connector_USB
+USB_Micro-B_Wuerth_629105150521
+USB Micro-B receptacle, http://www.mouser.com/ds/2/445/629105150521-469306.pdf
+usb micro receptacle
+0
+9
+6
+Connector_USB
+USB_Micro-B_Wuerth_629105150521_CircularHoles
+USB Micro-B receptacle, http://www.mouser.com/ds/2/445/629105150521-469306.pdf
+usb micro receptacle
+0
+9
+6
+Connector_USB
+USB_Mini-B_AdamTech_MUSB-B5-S-VT-TSMT-1_SMD_Vertical
+http://www.adam-tech.com/upload/MUSB-B5-S-VT-TSMT-1.pdf
+USB Mini-B
+0
+7
+6
+Connector_USB
+USB_Mini-B_Lumberg_2486_01_Horizontal
+USB Mini-B 5-pin SMD connector, http://downloads.lumberg.com/datenblaetter/en/2486_01.pdf
+USB USB_B USB_Mini connector
+0
+9
+6
+Connector_USB
+USB_Mini-B_Tensility_54-00023_Vertical
+http://www.tensility.com/pdffiles/54-00023.pdf
+usb mini receptacle vertical
+0
+7
+6
+Connector_USB
+USB_Mini-B_Tensility_54-00023_Vertical_CircularHoles
+http://www.tensility.com/pdffiles/54-00023.pdf
+usb mini receptacle vertical
+0
+7
+6
+Connector_USB
+USB_Mini-B_Wuerth_65100516121_Horizontal
+Mini USB 2.0 Type B SMT Horizontal 5 Contacts (https://katalog.we-online.de/em/datasheet/65100516121.pdf)
+Mini USB 2.0 Type B
+0
+9
+6
+Connector_Wago
+Wago_734-132_1x02_P3.50mm_Vertical
+Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-132 , 2 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  side entry
+0
+2
+2
+Connector_Wago
+Wago_734-133_1x03_P3.50mm_Vertical
+Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-133 , 3 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  side entry
+0
+3
+3
+Connector_Wago
+Wago_734-134_1x04_P3.50mm_Vertical
+Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-134 , 4 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  side entry
+0
+4
+4
+Connector_Wago
+Wago_734-135_1x05_P3.50mm_Vertical
+Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-135 , 5 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  side entry
+0
+5
+5
+Connector_Wago
+Wago_734-136_1x06_P3.50mm_Vertical
+Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-136 , 6 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  side entry
+0
+6
+6
+Connector_Wago
+Wago_734-137_1x07_P3.50mm_Vertical
+Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-137 , 7 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  side entry
+0
+7
+7
+Connector_Wago
+Wago_734-138_1x08_P3.50mm_Vertical
+Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-138 , 8 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  side entry
+0
+8
+8
+Connector_Wago
+Wago_734-139_1x09_P3.50mm_Vertical
+Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-139 , 9 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  side entry
+0
+9
+9
+Connector_Wago
+Wago_734-140_1x10_P3.50mm_Vertical
+Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-140 , 10 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  side entry
+0
+10
+10
+Connector_Wago
+Wago_734-141_1x11_P3.50mm_Vertical
+Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-141 , 11 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  side entry
+0
+11
+11
+Connector_Wago
+Wago_734-142_1x12_P3.50mm_Vertical
+Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-142 , 12 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  side entry
+0
+12
+12
+Connector_Wago
+Wago_734-143_1x13_P3.50mm_Vertical
+Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-143 , 13 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  side entry
+0
+13
+13
+Connector_Wago
+Wago_734-144_1x14_P3.50mm_Vertical
+Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-144 , 14 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  side entry
+0
+14
+14
+Connector_Wago
+Wago_734-146_1x16_P3.50mm_Vertical
+Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-146 , 16 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  side entry
+0
+16
+16
+Connector_Wago
+Wago_734-148_1x18_P3.50mm_Vertical
+Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-148 , 18 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  side entry
+0
+18
+18
+Connector_Wago
+Wago_734-150_1x20_P3.50mm_Vertical
+Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-150 , 20 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  side entry
+0
+20
+20
+Connector_Wago
+Wago_734-154_1x24_P3.50mm_Vertical
+Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-154 , 24 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  side entry
+0
+24
+24
+Connector_Wago
+Wago_734-162_1x02_P3.50mm_Horizontal
+Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-162 , 2 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  top entry
+0
+2
+2
+Connector_Wago
+Wago_734-163_1x03_P3.50mm_Horizontal
+Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-163 , 3 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  top entry
+0
+3
+3
+Connector_Wago
+Wago_734-164_1x04_P3.50mm_Horizontal
+Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-164 , 4 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  top entry
+0
+4
+4
+Connector_Wago
+Wago_734-165_1x05_P3.50mm_Horizontal
+Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-165 , 5 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  top entry
+0
+5
+5
+Connector_Wago
+Wago_734-166_1x06_P3.50mm_Horizontal
+Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-166 , 6 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  top entry
+0
+6
+6
+Connector_Wago
+Wago_734-167_1x07_P3.50mm_Horizontal
+Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-167 , 7 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  top entry
+0
+7
+7
+Connector_Wago
+Wago_734-168_1x08_P3.50mm_Horizontal
+Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-168 , 8 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  top entry
+0
+8
+8
+Connector_Wago
+Wago_734-169_1x09_P3.50mm_Horizontal
+Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-169 , 9 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  top entry
+0
+9
+9
+Connector_Wago
+Wago_734-170_1x10_P3.50mm_Horizontal
+Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-170 , 10 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  top entry
+0
+10
+10
+Connector_Wago
+Wago_734-171_1x11_P3.50mm_Horizontal
+Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-171 , 11 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  top entry
+0
+11
+11
+Connector_Wago
+Wago_734-172_1x12_P3.50mm_Horizontal
+Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-172 , 12 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  top entry
+0
+12
+12
+Connector_Wago
+Wago_734-173_1x13_P3.50mm_Horizontal
+Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-173 , 13 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  top entry
+0
+13
+13
+Connector_Wago
+Wago_734-174_1x14_P3.50mm_Horizontal
+Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-174 , 14 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  top entry
+0
+14
+14
+Connector_Wago
+Wago_734-176_1x16_P3.50mm_Horizontal
+Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-176 , 16 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  top entry
+0
+16
+16
+Connector_Wago
+Wago_734-178_1x18_P3.50mm_Horizontal
+Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-178 , 18 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  top entry
+0
+18
+18
+Connector_Wago
+Wago_734-180_1x20_P3.50mm_Horizontal
+Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-180 , 20 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  top entry
+0
+20
+20
+Connector_Wago
+Wago_734-184_1x24_P3.50mm_Horizontal
+Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-184 , 24 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator
+connector Wago  top entry
+0
+24
+24
+Connector_Wire
+SolderWirePad_1x01_Drill0.8mm
+Wire solder connection
+connector
+0
+1
+1
+Connector_Wire
+SolderWirePad_1x01_Drill1.2mm
+Wire solder connection
+connector
+0
+1
+1
+Connector_Wire
+SolderWirePad_1x01_Drill1.5mm
+Wire solder connection
+connector
+0
+1
+1
+Connector_Wire
+SolderWirePad_1x01_Drill1mm
+Wire solder connection
+connector
+0
+1
+1
+Connector_Wire
+SolderWirePad_1x01_Drill2.5mm
+Wire solder connection
+connector
+0
+1
+1
+Connector_Wire
+SolderWirePad_1x01_Drill2mm
+Wire solder connection
+connector
+0
+1
+1
+Connector_Wire
+SolderWirePad_1x01_SMD_5x10mm
+Wire Pad, Square, SMD Pad,  5mm x 10mm,
+MesurementPoint Square SMDPad 5mmx10mm 
+0
+1
+1
+Connector_Wire
+SolderWirePad_1x02_P3.81mm_Drill0.8mm
+Wire solder connection
+connector
+0
+2
+2
+Connector_Wire
+SolderWirePad_1x02_P3.81mm_Drill1.2mm
+Wire solder connection
+connector
+0
+2
+2
+Connector_Wire
+SolderWirePad_1x02_P3.81mm_Drill1mm
+Wire solder connection
+connector
+0
+2
+2
+Connector_Wire
+SolderWirePad_1x02_P5.08mm_Drill1.5mm
+Wire solder connection
+connector
+0
+2
+2
+Connector_Wire
+SolderWirePad_1x02_P7.62mm_Drill2.5mm
+Wire solder connection
+connector
+0
+2
+2
+Connector_Wire
+SolderWirePad_1x02_P7.62mm_Drill2mm
+Wire solder connection
+connector
+0
+2
+2
+Connector_Wire
+SolderWirePad_1x03_P3.81mm_Drill1.2mm
+Wire solder connection
+connector
+0
+3
+3
+Connector_Wire
+SolderWirePad_1x03_P3.175mm_Drill0.8mm
+Wire solder connection
+connector
+0
+3
+3
+Connector_Wire
+SolderWirePad_1x03_P3.175mm_Drill1mm
+Wire solder connection
+connector
+0
+3
+3
+Connector_Wire
+SolderWirePad_1x03_P4.445mm_Drill1.5mm
+Wire solder connection
+connector
+0
+3
+3
+Connector_Wire
+SolderWirePad_1x03_P5.715mm_Drill2mm
+Wire solder connection
+connector
+0
+3
+3
+Connector_Wire
+SolderWirePad_1x03_P7.62mm_Drill2.5mm
+Wire solder connection
+connector
+0
+3
+3
+Connector_Wire
+SolderWirePad_1x04_P3.81mm_Drill1.2mm
+Wire solder connection
+connector
+0
+4
+4
+Connector_Wire
+SolderWirePad_1x04_P3.81mm_Drill1mm
+Wire solder connection
+connector
+0
+4
+4
+Connector_Wire
+SolderWirePad_1x04_P3.175mm_Drill0.8mm
+Wire solder connection
+connector
+0
+4
+4
+Connector_Wire
+SolderWirePad_1x04_P5.08mm_Drill1.5mm
+Wire solder connection
+connector
+0
+4
+4
+Connector_Wire
+SolderWirePad_1x04_P6.35mm_Drill2mm
+Wire solder connection
+connector
+0
+4
+4
+Connector_Wire
+SolderWirePad_1x04_P7.62mm_Drill2.5mm
+Wire solder connection
+connector
+0
+4
+4
+Connector_Wire
+SolderWirePad_2x02_P2.54mm_Drill0.8mm
+Wire solder connection
+connector
+0
+4
+4
+Connector_Wire
+SolderWirePad_2x02_P3.81mm_Drill1.2mm
+Wire solder connection
+connector
+0
+4
+4
+Connector_Wire
+SolderWirePad_2x02_P3.81mm_Drill1mm
+Wire solder connection
+connector
+0
+4
+4
+Connector_Wire
+SolderWirePad_2x02_P5.08mm_Drill1.5mm
+Wire solder connection
+connector
+0
+4
+4
+Connector_Wire
+SolderWirePad_2x02_P6.35mm_Drill2mm
+Wire solder connection
+connector
+0
+4
+4
+Connector_Wire
+SolderWirePad_2x02_P7.62mm_Drill2.5mm
+Wire solder connection
+connector
+0
+4
+4
+Connector_Wuerth
+Wuerth_WR-WTB_64800211622_1x02_P1.50mm_Vertical
+Wuerth WR-WTB series connector, 64800211622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator
+connector Wuerth WR-WTB vertical
+0
+2
+2
+Connector_Wuerth
+Wuerth_WR-WTB_64800311622_1x03_P1.50mm_Vertical
+Wuerth WR-WTB series connector, 64800311622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator
+connector Wuerth WR-WTB vertical
+0
+3
+3
+Connector_Wuerth
+Wuerth_WR-WTB_64800411622_1x04_P1.50mm_Vertical
+Wuerth WR-WTB series connector, 64800411622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator
+connector Wuerth WR-WTB vertical
+0
+4
+4
+Connector_Wuerth
+Wuerth_WR-WTB_64800511622_1x05_P1.50mm_Vertical
+Wuerth WR-WTB series connector, 64800511622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator
+connector Wuerth WR-WTB vertical
+0
+5
+5
+Connector_Wuerth
+Wuerth_WR-WTB_64800611622_1x06_P1.50mm_Vertical
+Wuerth WR-WTB series connector, 64800611622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator
+connector Wuerth WR-WTB vertical
+0
+6
+6
+Connector_Wuerth
+Wuerth_WR-WTB_64800711622_1x07_P1.50mm_Vertical
+Wuerth WR-WTB series connector, 64800711622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator
+connector Wuerth WR-WTB vertical
+0
+7
+7
+Connector_Wuerth
+Wuerth_WR-WTB_64800811622_1x08_P1.50mm_Vertical
+Wuerth WR-WTB series connector, 64800811622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator
+connector Wuerth WR-WTB vertical
+0
+8
+8
+Connector_Wuerth
+Wuerth_WR-WTB_64800911622_1x09_P1.50mm_Vertical
+Wuerth WR-WTB series connector, 64800911622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator
+connector Wuerth WR-WTB vertical
+0
+9
+9
+Connector_Wuerth
+Wuerth_WR-WTB_64801011622_1x10_P1.50mm_Vertical
+Wuerth WR-WTB series connector, 64801011622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator
+connector Wuerth WR-WTB vertical
+0
+10
+10
+Converter_ACDC
+Converter_ACDC_CUI_PBO-3-Sxx_THT_Vertical
+ACDC-Converter, 3W, CUI PBO-3, THT https://www.cui.com/product/resource/pbo-3.pdf
+Converter AC-DC THT Vertical
+0
+6
+6
+Converter_ACDC
+Converter_ACDC_Hahn_HS-400xx_THT
+ACDC-Converter, 3W, Hahn-HS-400xx, THT https://www.schukat.com/schukat/schukat_cms_de.nsf/index/FrameView?OpenDocument&art=HS40009&wg=M7942
+Hahn ACDC-Converter THT
+0
+4
+4
+Converter_ACDC
+Converter_ACDC_HiLink_HLK-PMxx
+ACDC-Converter, 3W, HiLink, HLK-PMxx, THT, http://www.hlktech.net/product_detail.php?ProId=54
+ACDC-Converter 3W THT HiLink board mount module
+0
+4
+4
+Converter_ACDC
+Converter_ACDC_MeanWell_IRM-02-xx_SMD
+ACDC-Converter, 3W, Meanwell, IRM-02, SMD, https://www.meanwell.com/Upload/PDF/IRM-02/IRM-02-SPEC.PDF
+ACDC-Converter 3W
+0
+14
+14
+Converter_ACDC
+Converter_ACDC_MeanWell_IRM-02-xx_THT
+ACDC-Converter, 2W, Meanwell, IRM-02, THT, https://www.meanwell.co.uk/media/productPDF/IRM-02-spec.pdf
+ACDC-Converter 2W THT
+0
+4
+4
+Converter_ACDC
+Converter_ACDC_MeanWell_IRM-03-xx_SMD
+ACDC-Converter, 3W, Meanwell, IRM-03, SMD, http://www.meanwell.com/webapp/product/search.aspx?prod=IRM-03
+ACDC-Converter 3W
+0
+14
+14
+Converter_ACDC
+Converter_ACDC_MeanWell_IRM-03-xx_THT
+ACDC-Converter, 3W, Meanwell, IRM-03, THT, https://www.meanwell.com/Upload/PDF/IRM-03/IRM-03-SPEC.PDF
+ACDC-Converter 3W THT
+0
+5
+5
+Converter_ACDC
+Converter_ACDC_MeanWell_IRM-05-xx_THT
+http://www.meanwell.com/webapp/product/search.aspx?prod=IRM-05
+ACDC-Converter 5W   Meanwell IRM-05
+0
+4
+4
+Converter_ACDC
+Converter_ACDC_MeanWell_IRM-10-xx_THT
+http://www.meanwell.com/webapp/product/search.aspx?prod=IRM-10
+ACDC-Converter 10W   Meanwell IRM-10
+0
+4
+4
+Converter_ACDC
+Converter_ACDC_MeanWell_IRM-20-xx_THT
+ACDC-Converter, 20W, Meanwell, IRM-20, THT http://www.meanwell.com/webapp/product/search.aspx?prod=IRM-20
+ACDC-Converter 20W   Meanwell IRM-20
+0
+4
+4
+Converter_ACDC
+Converter_ACDC_RECOM_RAC01-xxSGB_THT
+https://www.recom-power.com/pdf/Powerline-AC-DC/RAC01-GB.pdf
+recom power ac dc rac01xxgb rac01-05sgb rac01-12sgb
+0
+4
+4
+Converter_ACDC
+Converter_ACDC_RECOM_RAC04-xxSGx_THT
+https://www.recom-power.com/pdf/Powerline-AC-DC/RAC04-GA.pdf
+recom power ac dc
+0
+5
+5
+Converter_ACDC
+Converter_ACDC_RECOM_RAC05-xxSK_THT
+https://www.recom-power.com/pdf/Powerline-AC-DC/RAC05-K.pdf
+recom power ac dc
+0
+5
+5
+Converter_ACDC
+Converter_ACDC_TRACO_TMG-15_THT
+ACDC-Converter, TRACO, TMG Series 15 https://www.tracopower.com/products/tmg.pdf
+ACDC-Converter TRACO TMG Series 15
+0
+4
+4
+Converter_ACDC
+Converter_ACDC_TRACO_TMLM-04_THT
+ACDC-Converter, TRACO, TMLM Series 04 https://www.tracopower.com/products/tmlm.pdf
+ACDC-Converter TRACO TMLM Series 04
+0
+7
+7
+Converter_ACDC
+Converter_ACDC_TRACO_TMLM-05_THT
+ACDC-Converter, TRACO TMLM 05,https://www.tracopower.com/products/tmlm.pdf
+ACDC-Converter TRACO TMLM 05
+0
+4
+4
+Converter_ACDC
+Converter_ACDC_TRACO_TMLM-10-20_THT
+ACDC-Converter, TRACO TMLM 10, TRACO TMLM 20, https://www.tracopower.com/products/tmlm.pdf
+ACDC-Converter TRACO TMLM 10 and TMLM 20
+0
+4
+4
+Converter_ACDC
+Converter_ACDC_Vigortronix_VTX-214-010-xxx_THT
+Vigortronix VTX-214-010-xxx serie of ACDC converter, http://www.vigortronix.com/10WattACDCPCBPowerModule.aspx
+Vigortronix VTX-214-010-xxx serie of ACDC converter
+0
+4
+4
+Converter_ACDC
+Converter_ACDC_Vigortronix_VTX-214-015-1xx_THT
+Vigortronix VTX-214-010-xxx serie of ACDC converter, http://www.vigortronix.com/10WattACDCPCBPowerModule.aspx
+Vigortronix VTX-214-010-xxx serie of ACDC converter
+0
+5
+5
+Converter_DCDC
+Converter_DCDC_Artesyn_ATA_SMD
+DCDC-Converter, Artesyn, ATA Series, 3W Single and Dual Output, 1500VDC Isolation, 24.0x13.7x8.0mm https://www.artesyn.com/power/assets/ata_series_ds_01apr2015_79c25814fd.pdf https://www.artesyn.com/power/assets/trn_dc-dc_ata_3w_series_releas1430412818_techref.pdf
+DCDC SMD
+0
+7
+7
+Converter_DCDC
+Converter_DCDC_Bothhand_CFUDxxxx_THT
+DCDC-Converter, BOTHHAND, Type CFxxxx-Serie,  (Very dodgy url but was the only at hand), 
+DCDC-Converter BOTHHAND Type CFxxxx-Serie
+0
+10
+10
+Converter_DCDC
+Converter_DCDC_Bothhand_CFUSxxxxEH_THT
+DCDC-Converter, BOTHHAND, Type CFxxxx-Serie,  (Very dodgy url but was the only at hand), 
+DCDC-Converter BOTHHAND Type CFxxxx-Serie
+0
+9
+9
+Converter_DCDC
+Converter_DCDC_Bothhand_CFUSxxxx_THT
+DCDC-Converter, BOTHHAND, Type CFxxxx-Serie,  (Very dodgy url but was the only at hand), 
+DCDC-Converter BOTHHAND Type CFxxxx-Serie
+0
+8
+8
+Converter_DCDC
+Converter_DCDC_Cincon_EC5BExx_Dual_THT
+DCDC-Converter, CINCON, EC5BExx, 18-36VDC to Dual output, http://www.cincon.com/upload/media/data%20sheets/Data%20Sheet%20(DC)/B%20CASE/SPEC-EC5BE-V24.pdf
+DCDC-Converter CINCON EC5BExx 18-36VDC to Dual output
+0
+6
+6
+Converter_DCDC
+Converter_DCDC_Cincon_EC5BExx_Single_THT
+DCDC-Converter, CINCON, EC5BExx, 18-36VDC to dual output, http://www.cincon.com/upload/media/data%20sheets/Data%20Sheet%20(DC)/B%20CASE/SPEC-EC5BE-V24.pdf
+DCDC-Converter CINCON EC5BExx 18-36VDC to dual output
+0
+4
+4
+Converter_DCDC
+Converter_DCDC_Cincon_EC6Cxx_Dual-Triple_THT
+DCDC-Converter, CINCON, EC6Cxx, dual or tripple output, http://www.cincon.com/upload/media/data%20sheets/Data%20Sheet%20(DC)/C%20CASE/SPEC-EC6C-V12.pdf
+DCDC-Converter CINCON EC6Cxx dual or tripple output
+0
+7
+7
+Converter_DCDC
+Converter_DCDC_Cincon_EC6Cxx_Single_THT
+DCDC-Converter, CINCON, EC6Cxx, single output, http://www.cincon.com/upload/media/data%20sheets/Data%20Sheet%20(DC)/C%20CASE/SPEC-EC6C-V12.pdf
+DCDC-Converter CINCON EC6Cxx single output
+0
+6
+6
+Converter_DCDC
+Converter_DCDC_MeanWell_NID30_THT
+Meanwell DCDC non-isolated converter SIP module, http://www.meanwell.com/webapp/product/search.aspx?prod=nid30
+DCDC non-isolated converter 
+0
+11
+11
+Converter_DCDC
+Converter_DCDC_MeanWell_NID60_THT
+MeanWell NID60, http://www.meanwell.com/Upload/PDF/NID60/NID60-SPEC.PDF
+MeanWell NID60
+0
+11
+11
+Converter_DCDC
+Converter_DCDC_Murata_MGJ2DxxxxxxSC_THT
+Murata MGJ2DxxxxxxSC, 19.5x9.8x12.5mm, 5.2kVDC Isolated, 2W, SIP package style, https://power.murata.com/data/power/ncl/kdc_mgj2.pdf
+Murata MGJ2DxxxxxxSC
+0
+5
+5
+Converter_DCDC
+Converter_DCDC_Murata_MGJ3
+Murata MGJ3, 5.2kVDC Isolated 3W Gate Drive, 15V/5V/5V Configurable, 22.61x23.11x14.19mm, https://power.murata.com/datasheet?/data/power/ncl/kdc_mgj3.pdf
+DCDC SMD
+0
+7
+7
+Converter_DCDC
+Converter_DCDC_Murata_NCS1SxxxxSC_THT
+Murata NCS1SxxxxSC https://power.murata.com/data/power/ncl/kdc_ncs1.pdf (Script generated with StandardBox.py) (Murata NCS1SxxxxSC https://power.murata.com/data/power/ncl/kdc_ncs1.pdf)
+Murata NCS1SxxxxSC
+0
+5
+5
+Converter_DCDC
+Converter_DCDC_RECOM_R-78B-2.0_THT
+DCDC-Converter, RECOM, RECOM_R-78B-2.0, SIP-3, pitch 2.54mm, package size 11.5x8.5x17.5mm^3, https://www.recom-power.com/pdf/Innoline/R-78Bxx-2.0.pdf
+dc-dc recom buck sip-3 pitch 2.54mm
+0
+3
+3
+Converter_DCDC
+Converter_DCDC_RECOM_R-78E-0.5_THT
+DCDC-Converter, RECOM, RECOM_R-78E-0.5, SIP-3, pitch 2.54mm, package size 11.6x8.5x10.4mm^3, https://www.recom-power.com/pdf/Innoline/R-78Exx-0.5.pdf
+dc-dc recom buck sip-3 pitch 2.54mm
+0
+3
+3
+Converter_DCDC
+Converter_DCDC_RECOM_R-78HB-0.5L_THT
+DCDC-Converter, RECOM, RECOM_R-78HB-0.5L, SIP-3, Horizontally Mounted, pitch 2.54mm, package size 11.5x8.5x17.5mm^3, https://www.recom-power.com/pdf/Innoline/R-78HBxx-0.5_L.pdf
+dc-dc recom buck sip-3 pitch 2.54mm
+0
+3
+3
+Converter_DCDC
+Converter_DCDC_RECOM_R-78HB-0.5_THT
+DCDC-Converter, RECOM, RECOM_R-78HB-0.5, SIP-3, pitch 2.54mm, package size 11.5x8.5x17.5mm^3, https://www.recom-power.com/pdf/Innoline/R-78HBxx-0.5_L.pdf
+dc-dc recom buck sip-3 pitch 2.54mm
+0
+3
+3
+Converter_DCDC
+Converter_DCDC_RECOM_R-78S-0.1_THT
+DCDC-Converter, RECOM, RECOM_R-78S-0.1, SIP-4, pitch 2.54mm, package size 11.6x8.5x10.4mm^3, https://www.recom-power.com/pdf/Innoline/R-78Sxx-0.1.pdf
+dc-dc recom buck sip-4 pitch 2.54mm
+0
+4
+4
+Converter_DCDC
+Converter_DCDC_RECOM_R5xxxDA_THT
+DCDC-Converter, RECOM, RECOM_R5xxxDA, SIP-12, Horizontally Mounted, pitch 2.54mm, package size 32.2x9.1x15mm^3, https://www.recom-power.com/pdf/Innoline/R-5xxxPA_DA.pdf
+dc-dc recom buck sip-12 pitch 2.54mm
+0
+12
+12
+Converter_DCDC
+Converter_DCDC_RECOM_R5xxxPA_THT
+DCDC-Converter, RECOM, RECOM_R5xxxPA, SIP-12, pitch 2.54mm, package size 32.2x9.1x15mm^3, https://www.recom-power.com/pdf/Innoline/R-5xxxPA_DA.pdf
+dc-dc recom buck sip-12 pitch 2.54mm
+0
+12
+12
+Converter_DCDC
+Converter_DCDC_RECOM_RPMx.x-x.0
+https://www.recom-power.com/pdf/Innoline/RPM-6.0.pdf
+dc-dc recom buck lga-25 pitch 2.29mm
+0
+25
+25
+Converter_DCDC
+Converter_DCDC_TRACO_TEN10-xxxx_Dual_THT
+DCDC-Converter, TRACO, TEN10-xxxx, single output, https://assets.tracopower.com/20171102100522/TEN10/documents/ten10-datasheet.pdf
+DCDC-Converter TRACO TEN10-xxxx single output
+0
+5
+5
+Converter_DCDC
+Converter_DCDC_TRACO_TEN10-xxxx_Single_THT
+DCDC-Converter, TRACO, TEN10-xxxx, single output, https://assets.tracopower.com/20171102100522/TEN10/documents/ten10-datasheet.pdf
+DCDC-Converter TRACO TEN10-xxxx single output
+0
+4
+4
+Converter_DCDC
+Converter_DCDC_TRACO_TEN10-xxxx_THT
+DCDC-Converter, TRACO, TEN10-xxxx, https://assets.tracopower.com/20171102100522/TEN10/documents/ten10-datasheet.pdf
+DCDC-Converter TRACO TEN10-xxxx
+0
+4
+4
+Converter_DCDC
+Converter_DCDC_TRACO_TEN20-xxxx-N4_THT
+DCDC-Converter TRACO TEN20 Generic, https://assets.tracopower.com/20171102100522/TEN20/documents/ten20-datasheet.pdf
+DCDC-Converter TRACO TEN20 Generic
+0
+5
+5
+Converter_DCDC
+Converter_DCDC_TRACO_TEN20-xxxx_THT
+DCDC-Converter TRACO TEN20 Generic, https://assets.tracopower.com/20171102100522/TEN20/documents/ten20-datasheet.pdf
+DCDC-Converter TRACO TEN20 Generic
+0
+6
+6
+Converter_DCDC
+Converter_DCDC_TRACO_TMR-1-xxxx_Dual_THT
+DCDC-Converter, TRACO, TMR 1-xxxx, Dual output, Rev. March 21.2016
+DCDC-Converter TRACO TMR1-xxxx Dual_output
+0
+5
+5
+Converter_DCDC
+Converter_DCDC_TRACO_TMR-1-xxxx_Single_THT
+DCDC-Converter, TRACO, TMR 1-xxxx, Single output, Rev. March 21.2016
+DCDC-Converter TRACO TMR1-xxxx Single_output
+0
+4
+4
+Converter_DCDC
+Converter_DCDC_TRACO_TMR-1SM_SMD
+http://assets.tracopower.com/TMR1SM/documents/tmr1sm-datasheet.pdf
+DCDC SMD TRACO TMR-1SM
+0
+7
+7
+Converter_DCDC
+Converter_DCDC_TRACO_TMR-2xxxxWI_THT
+https://www.tracopower.com/products/tmr2wi.pdf
+DCDC-Converter TRACO TMRxxxxWI Single/Dual_output
+0
+7
+7
+Converter_DCDC
+Converter_DCDC_TRACO_TMR-xxxx_THT
+DCDC-Converter, TRACO, TMR xxxx, Single/Dual output, http://www.datasheetlib.com/datasheet/135136/tmr-2-2410e_traco-power.html?page=3#datasheet
+DCDC-Converter TRACO TMRxxxx Single/Dual_output
+0
+7
+7
+Converter_DCDC
+Converter_DCDC_TRACO_TSR-1_THT
+DCDC-Converter, TRACO, TSR 1-xxxx
+DCDC-Converter TRACO TSR-1
+0
+3
+3
+Converter_DCDC
+Converter_DCDC_XP_POWER-IA48xxD_THT
+XP_POWER  IA48xxD, DIP, (https://www.xppower.com/pdfs/SF_IA.pdf), generated with kicad-footprint-generator
+XP_POWER  IA48xxD DIP DCDC-Converter
+0
+6
+6
+Converter_DCDC
+Converter_DCDC_XP_POWER-IA48xxS_THT
+XP_POWER  IA48xxS, SIP, (https://www.xppower.com/pdfs/SF_IA.pdf), generated with kicad-footprint-generator
+XP_POWER  IA48xxS SIP DCDC-Converter
+0
+5
+5
+Converter_DCDC
+Converter_DCDC_XP_POWER-IAxxxxD_THT
+XP_POWER  IAxxxxD, DIP, (https://www.xppower.com/pdfs/SF_IA.pdf), generated with kicad-footprint-generator
+XP_POWER  IAxxxxD DIP DCDC-Converter
+0
+6
+6
+Converter_DCDC
+Converter_DCDC_XP_POWER-IAxxxxS_THT
+XP_POWER  IAxxxxS, SIP, (https://www.xppower.com/pdfs/SF_IA.pdf), generated with kicad-footprint-generator
+XP_POWER  IAxxxxS SIP DCDC-Converter
+0
+5
+5
+Converter_DCDC
+Converter_DCDC_XP_POWER-IHxxxxDH_THT
+XP_POWER  IHxxxxDH, DIP, (https://www.xppower.com/pdfs/SF_IH.pdf), generated with kicad-footprint-generator
+XP_POWER  IHxxxxDH DIP DCDC-Converter
+0
+6
+6
+Converter_DCDC
+Converter_DCDC_XP_POWER-IHxxxxD_THT
+XP_POWER  IHxxxxD, DIP, (https://www.xppower.com/pdfs/SF_IH.pdf), generated with kicad-footprint-generator
+XP_POWER  IHxxxxD DIP DCDC-Converter
+0
+6
+6
+Converter_DCDC
+Converter_DCDC_XP_POWER-IHxxxxSH_THT
+XP_POWER  IHxxxxSH, SIP, (https://www.xppower.com/pdfs/SF_IH.pdf), generated with kicad-footprint-generator
+XP_POWER  IHxxxxSH SIP DCDC-Converter
+0
+5
+5
+Converter_DCDC
+Converter_DCDC_XP_POWER-IHxxxxS_THT
+XP_POWER  IHxxxxS, SIP, (https://www.xppower.com/pdfs/SF_IH.pdf), generated with kicad-footprint-generator
+XP_POWER  IHxxxxS SIP DCDC-Converter
+0
+5
+5
+Converter_DCDC
+Converter_DCDC_XP_POWER-ISU02_SMD
+DCDC-Converter, XP POWER, ISU02 Series, 2W Single and Dual Output, 1500VDC Isolation, 19.0x17.0x8.7mm https://www.xppower.com/Portals/0/pdfs/SF_ISU02.pdf
+DCDC SMD XP POWER ISU02
+0
+7
+7
+Converter_DCDC
+Converter_DCDC_XP_POWER-ITQxxxxS-H_THT
+XP_POWER  ITQxxxxS-H, SIP, (https://www.xppower.com/pdfs/SF_ITQ.pdf), generated with kicad-footprint-generator
+XP_POWER  ITQxxxxS-H SIP DCDC-Converter
+0
+6
+6
+Converter_DCDC
+Converter_DCDC_XP_POWER-ITXxxxxSA_THT
+XP_POWER  ITXxxxxSA, SIP, (https://www.xppower.com/pdfs/SF_ITX.pdf), generated with kicad-footprint-generator
+XP_POWER  ITXxxxxSA SIP DCDC-Converter
+0
+5
+5
+Converter_DCDC
+Converter_DCDC_XP_POWER-ITxxxxxS_THT
+XP_POWER  ITxxxxxS, SIP, (https://www.xppower.com/pdfs/SF_ITX.pdf https://www.xppower.com/pdfs/SF_ITQ.pdf), generated with kicad-footprint-generator
+XP_POWER  ITxxxxxS SIP DCDC-Converter
+0
+5
+5
+Converter_DCDC
+Converter_DCDC_XP_POWER_JTExxxxDxx_THT
+DCDC-Converter, XP POWER, Type JTE06 Series,  Dual Output
+DCDC-Converter XP_POWER JTE06 Dual
+0
+8
+8
+Converter_DCDC
+Converter_DCDC_muRata_CRE1xxxxxx3C_THT
+Isolated 1W single output DC/DC, http://power.murata.com/data/power/ncl/kdc_cre1.pdf
+Isolated 1W single output DC/DC
+0
+4
+4
+Converter_DCDC
+Converter_DCDC_muRata_CRE1xxxxxxDC_THT
+Isloated DC-DC, http://power.murata.com/data/power/ncl/kdc_cre1.pdf
+Isloated DC-DC
+0
+4
+4
+Converter_DCDC
+Converter_DCDC_muRata_CRE1xxxxxxSC_THT
+http://power.murata.com/data/power/ncl/kdc_cre1.pdf
+murata dc-dc transformer
+0
+4
+4
+Converter_DCDC
+Converter_DCDC_muRata_NMAxxxxDC_THT
+Isolated 1W DCDC-Converter, http://power.murata.com/data/power/ncl/kdc_nma.pdf
+Isolated 1W DCDC-Converter
+0
+6
+6
+Converter_DCDC
+Converter_DCDC_muRata_NMAxxxxSC_THT
+muRata NMAxxxxSC footprint based on SIP7, http://power.murata.com/data/power/ncl/kdc_nma.pdf
+muRata NMAxxxxSC DCDC-Converter
+0
+5
+5
+Converter_DCDC
+Converter_DCDC_muRata_NXE2SxxxxMC_THT
+Isolated 2W Single Output SM DC/DC Converters, http://power.murata.com/data/power/ncl/kdc_nxe2.pdf
+Isolated 2W Single Output SM DC/DC Converters
+0
+5
+5
+Converter_DCDC
+Converter_DCDC_muRata_OKI-78SR_Horizontal
+https://power.murata.com/data/power/oki-78sr.pdf
+78sr3.3 78sr5 78sr9 78sr12 78srXX
+0
+3
+3
+Converter_DCDC
+Converter_DCDC_muRata_OKI-78SR_Vertical
+https://power.murata.com/data/power/oki-78sr.pdf
+78sr3.3 78sr5 78sr9 78sr12 78srXX
+0
+3
+3
+Crystal
+Crystal_AT310_D3.0mm_L10.0mm_Horizontal
+Crystal THT AT310 10.0mm-10.5mm length 3.0mm diameter http://www.cinetech.com.tw/upload/2011/04/20110401165201.pdf
+['AT310']
+0
+2
+2
+Crystal
+Crystal_AT310_D3.0mm_L10.0mm_Horizontal_1EP_style1
+Crystal THT AT310 10.0mm-10.5mm length 3.0mm diameter http://www.cinetech.com.tw/upload/2011/04/20110401165201.pdf
+['AT310']
+0
+3
+3
+Crystal
+Crystal_AT310_D3.0mm_L10.0mm_Horizontal_1EP_style2
+Crystal THT AT310 10.0mm-10.5mm length 3.0mm diameter http://www.cinetech.com.tw/upload/2011/04/20110401165201.pdf
+['AT310']
+0
+5
+3
+Crystal
+Crystal_AT310_D3.0mm_L10.0mm_Vertical
+Crystal THT AT310 10.0mm-10.5mm length 3.0mm diameter http://www.cinetech.com.tw/upload/2011/04/20110401165201.pdf
+['AT310']
+0
+2
+2
+Crystal
+Crystal_C26-LF_D2.1mm_L6.5mm_Horizontal
+Crystal THT C26-LF 6.5mm length 2.06mm diameter
+['C26-LF']
+0
+2
+2
+Crystal
+Crystal_C26-LF_D2.1mm_L6.5mm_Horizontal_1EP_style1
+Crystal THT C26-LF 6.5mm length 2.06mm diameter
+['C26-LF']
+0
+3
+3
+Crystal
+Crystal_C26-LF_D2.1mm_L6.5mm_Horizontal_1EP_style2
+Crystal THT C26-LF 6.5mm length 2.06mm diameter
+['C26-LF']
+0
+5
+3
+Crystal
+Crystal_C26-LF_D2.1mm_L6.5mm_Vertical
+Crystal THT C26-LF 6.5mm length 2.06mm diameter
+['C26-LF']
+0
+2
+2
+Crystal
+Crystal_C38-LF_D3.0mm_L8.0mm_Horizontal
+Crystal THT C38-LF 8.0mm length 3.0mm diameter
+['C38-LF']
+0
+2
+2
+Crystal
+Crystal_C38-LF_D3.0mm_L8.0mm_Horizontal_1EP_style1
+Crystal THT C38-LF 8.0mm length 3.0mm diameter
+['C38-LF']
+0
+3
+3
+Crystal
+Crystal_C38-LF_D3.0mm_L8.0mm_Horizontal_1EP_style2
+Crystal THT C38-LF 8.0mm length 3.0mm diameter
+['C38-LF']
+0
+5
+3
+Crystal
+Crystal_C38-LF_D3.0mm_L8.0mm_Vertical
+Crystal THT C38-LF 8.0mm length 3.0mm diameter
+['C38-LF']
+0
+2
+2
+Crystal
+Crystal_DS10_D1.0mm_L4.3mm_Horizontal
+Crystal THT DS10 4.3mm length 1.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf
+['DS10']
+0
+2
+2
+Crystal
+Crystal_DS10_D1.0mm_L4.3mm_Horizontal_1EP_style1
+Crystal THT DS10 4.3mm length 1.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf
+['DS10']
+0
+3
+3
+Crystal
+Crystal_DS10_D1.0mm_L4.3mm_Horizontal_1EP_style2
+Crystal THT DS10 4.3mm length 1.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf
+['DS10']
+0
+5
+3
+Crystal
+Crystal_DS10_D1.0mm_L4.3mm_Vertical
+Crystal THT DS10 4.3mm length 1.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf
+['DS10']
+0
+2
+2
+Crystal
+Crystal_DS15_D1.5mm_L5.0mm_Horizontal
+Crystal THT DS15 5.0mm length 1.5mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf
+['DS15']
+0
+2
+2
+Crystal
+Crystal_DS15_D1.5mm_L5.0mm_Horizontal_1EP_style1
+Crystal THT DS15 5.0mm length 1.5mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf
+['DS15']
+0
+3
+3
+Crystal
+Crystal_DS15_D1.5mm_L5.0mm_Horizontal_1EP_style2
+Crystal THT DS15 5.0mm length 1.5mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf
+['DS15']
+0
+5
+3
+Crystal
+Crystal_DS15_D1.5mm_L5.0mm_Vertical
+Crystal THT DS15 5.0mm length 1.5mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf
+['DS15']
+0
+2
+2
+Crystal
+Crystal_DS26_D2.0mm_L6.0mm_Horizontal
+Crystal THT DS26 6.0mm length 2.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf
+['DS26']
+0
+2
+2
+Crystal
+Crystal_DS26_D2.0mm_L6.0mm_Horizontal_1EP_style1
+Crystal THT DS26 6.0mm length 2.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf
+['DS26']
+0
+3
+3
+Crystal
+Crystal_DS26_D2.0mm_L6.0mm_Horizontal_1EP_style2
+Crystal THT DS26 6.0mm length 2.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf
+['DS26']
+0
+5
+3
+Crystal
+Crystal_DS26_D2.0mm_L6.0mm_Vertical
+Crystal THT DS26 6.0mm length 2.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf
+['DS26']
+0
+2
+2
+Crystal
+Crystal_HC18-U_Horizontal
+Crystal THT HC-18/U http://5hertz.com/pdfs/04404_D.pdf
+THT crystal
+0
+2
+2
+Crystal
+Crystal_HC18-U_Horizontal_1EP_style1
+Crystal THT HC-18/U http://5hertz.com/pdfs/04404_D.pdf
+THT crystal
+0
+3
+3
+Crystal
+Crystal_HC18-U_Horizontal_1EP_style2
+Crystal THT HC-18/U http://5hertz.com/pdfs/04404_D.pdf
+THT crystal
+0
+5
+3
+Crystal
+Crystal_HC18-U_Vertical
+Crystal THT HC-18/U, http://5hertz.com/pdfs/04404_D.pdf
+THT crystalHC-18/U
+0
+2
+2
+Crystal
+Crystal_HC33-U_Horizontal
+Crystal THT HC-33/U http://pdi.bentech-taiwan.com/PDI/GEN20SPEV20HC3320U.pdf
+THT crystal
+0
+2
+2
+Crystal
+Crystal_HC33-U_Horizontal_1EP_style1
+Crystal THT HC-33/U http://pdi.bentech-taiwan.com/PDI/GEN20SPEV20HC3320U.pdf
+THT crystal
+0
+3
+3
+Crystal
+Crystal_HC33-U_Horizontal_1EP_style2
+Crystal THT HC-33/U http://pdi.bentech-taiwan.com/PDI/GEN20SPEV20HC3320U.pdf
+THT crystal
+0
+5
+3
+Crystal
+Crystal_HC33-U_Vertical
+Crystal THT HC-33/U, http://pdi.bentech-taiwan.com/PDI/GEN20SPEV20HC3320U.pdf
+THT crystalHC-33/U
+0
+2
+2
+Crystal
+Crystal_HC35-U
+Crystal, Quarz, HC35/U, http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/TO71xx.pdf
+Crystal Quarz HC35/U
+0
+3
+3
+Crystal
+Crystal_HC49-4H_Vertical
+Crystal THT HC-49-4H http://5hertz.com/pdfs/04404_D.pdf
+THT crystalHC-49-4H
+0
+2
+2
+Crystal
+Crystal_HC49-U-3Pin_Vertical
+Crystal THT HC-49/U, 3pin-version, http://www.raltron.com/products/pdfspecs/crystal_hc_49_45_51.pdf
+THT crystalHC-49/U
+0
+3
+3
+Crystal
+Crystal_HC49-U_Horizontal
+Crystal THT HC-49/U http://5hertz.com/pdfs/04404_D.pdf
+THT crystal
+0
+2
+2
+Crystal
+Crystal_HC49-U_Horizontal_1EP_style1
+Crystal THT HC-49/U http://5hertz.com/pdfs/04404_D.pdf
+THT crystal
+0
+3
+3
+Crystal
+Crystal_HC49-U_Horizontal_1EP_style2
+Crystal THT HC-49/U http://5hertz.com/pdfs/04404_D.pdf
+THT crystal
+0
+5
+3
+Crystal
+Crystal_HC49-U_Vertical
+Crystal THT HC-49/U http://5hertz.com/pdfs/04404_D.pdf
+THT crystalHC-49/U
+0
+2
+2
+Crystal
+Crystal_HC50_Horizontal
+Crystal THT HC-50 http://www.crovencrystals.com/croven_pdf/HC-50_Crystal_Holder_Rev_00.pdf
+THT crystal
+0
+2
+2
+Crystal
+Crystal_HC50_Horizontal_1EP_style1
+Crystal THT HC-50 http://www.crovencrystals.com/croven_pdf/HC-50_Crystal_Holder_Rev_00.pdf
+THT crystal
+0
+3
+3
+Crystal
+Crystal_HC50_Horizontal_1EP_style2
+Crystal THT HC-50 http://www.crovencrystals.com/croven_pdf/HC-50_Crystal_Holder_Rev_00.pdf
+THT crystal
+0
+5
+3
+Crystal
+Crystal_HC50_Vertical
+Crystal THT HC-50, http://www.crovencrystals.com/croven_pdf/HC-50_Crystal_Holder_Rev_00.pdf
+THT crystalHC-50
+0
+2
+2
+Crystal
+Crystal_HC51-U_Vertical
+Crystal THT HC-51/U, http://www.crovencrystals.com/croven_pdf/HC-51_Crystal_Holder_Rev_00.pdf
+THT crystalHC-51/U
+0
+2
+2
+Crystal
+Crystal_HC51_Horizontal
+Crystal THT HC-51 http://www.crovencrystals.com/croven_pdf/HC-51_Crystal_Holder_Rev_00.pdf
+THT crystal
+0
+2
+2
+Crystal
+Crystal_HC51_Horizontal_1EP_style1
+Crystal THT HC-51 http://www.crovencrystals.com/croven_pdf/HC-51_Crystal_Holder_Rev_00.pdf
+THT crystal
+0
+3
+3
+Crystal
+Crystal_HC51_Horizontal_1EP_style2
+Crystal THT HC-51 http://www.crovencrystals.com/croven_pdf/HC-51_Crystal_Holder_Rev_00.pdf
+THT crystal
+0
+5
+3
+Crystal
+Crystal_HC52-6mm_Horizontal
+Crystal THT HC-51/6mm http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf
+THT crystal
+0
+2
+2
+Crystal
+Crystal_HC52-6mm_Horizontal_1EP_style1
+Crystal THT HC-51/6mm http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf
+THT crystal
+0
+3
+3
+Crystal
+Crystal_HC52-6mm_Horizontal_1EP_style2
+Crystal THT HC-51/6mm http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf
+THT crystal
+0
+5
+3
+Crystal
+Crystal_HC52-6mm_Vertical
+Crystal THT HC-52/6mm, http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf
+THT crystalHC-49/U
+0
+2
+2
+Crystal
+Crystal_HC52-8mm_Horizontal
+Crystal THT HC-51/8mm http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf
+THT crystal
+0
+2
+2
+Crystal
+Crystal_HC52-8mm_Horizontal_1EP_style1
+Crystal THT HC-51/8mm http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf
+THT crystal
+0
+3
+3
+Crystal
+Crystal_HC52-8mm_Horizontal_1EP_style2
+Crystal THT HC-51/8mm http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf
+THT crystal
+0
+5
+3
+Crystal
+Crystal_HC52-8mm_Vertical
+Crystal THT HC-52/8mm, http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf
+THT crystalHC-49/U
+0
+2
+2
+Crystal
+Crystal_HC52-U-3Pin_Vertical
+Crystal THT HC-52/U, http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf
+THT crystalHC-52/U
+0
+3
+3
+Crystal
+Crystal_HC52-U_Horizontal
+Crystal THT HC-51/U http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf
+THT crystal
+0
+2
+2
+Crystal
+Crystal_HC52-U_Horizontal_1EP_style1
+Crystal THT HC-51/U http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf
+THT crystal
+0
+3
+3
+Crystal
+Crystal_HC52-U_Horizontal_1EP_style2
+Crystal THT HC-51/U http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf
+THT crystal
+0
+5
+3
+Crystal
+Crystal_HC52-U_Vertical
+Crystal THT HC-52/U, http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf
+THT crystal HC-52/U
+0
+2
+2
+Crystal
+Crystal_Round_D1.0mm_Vertical
+Crystal THT DS10 1.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf
+['DS10']
+0
+2
+2
+Crystal
+Crystal_Round_D1.5mm_Vertical
+Crystal THT DS15 5.0mm length 1.5mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf
+['DS15']
+0
+2
+2
+Crystal
+Crystal_Round_D2.0mm_Vertical
+Crystal THT DS26 6.0mm length 2.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf
+['DS26']
+0
+2
+2
+Crystal
+Crystal_Round_D3.0mm_Vertical
+Crystal THT C38-LF 8.0mm length 3.0mm diameter
+['C38-LF']
+0
+2
+2
+Crystal
+Crystal_SMD_0603-2Pin_6.0x3.5mm
+SMD Crystal SERIES SMD0603/2 http://www.petermann-technik.de/fileadmin/petermann/pdf/SMD0603-2.pdf, 6.0x3.5mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_0603-2Pin_6.0x3.5mm_HandSoldering
+SMD Crystal SERIES SMD0603/2 http://www.petermann-technik.de/fileadmin/petermann/pdf/SMD0603-2.pdf, hand-soldering, 6.0x3.5mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_0603-4Pin_6.0x3.5mm
+SMD Crystal SERIES SMD0603/4 http://www.petermann-technik.de/fileadmin/petermann/pdf/SMD0603-4.pdf, 6.0x3.5mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_0603-4Pin_6.0x3.5mm_HandSoldering
+SMD Crystal SERIES SMD0603/4 http://www.petermann-technik.de/fileadmin/petermann/pdf/SMD0603-4.pdf, hand-soldering, 6.0x3.5mm^2 package
+SMD SMT crystal hand-soldering
+0
+4
+4
+Crystal
+Crystal_SMD_2012-2Pin_2.0x1.2mm
+SMD Crystal 2012/2 http://txccrystal.com/images/pdf/9ht11.pdf, 2.0x1.2mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_2012-2Pin_2.0x1.2mm_HandSoldering
+SMD Crystal 2012/2 http://txccrystal.com/images/pdf/9ht11.pdf, hand-soldering, 2.0x1.2mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_2016-4Pin_2.0x1.6mm
+SMD Crystal SERIES SMD2016/4 http://www.q-crystal.com/upload/5/2015552223166229.pdf, 2.0x1.6mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_2520-4Pin_2.5x2.0mm
+SMD Crystal SERIES SMD2520/4 http://www.newxtal.com/UploadFiles/Images/2012-11-12-09-29-09-776.pdf, 2.5x2.0mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_3215-2Pin_3.2x1.5mm
+SMD Crystal FC-135 https://support.epson.biz/td/api/doc_check.php?dl=brief_FC-135R_en.pdf
+SMD SMT Crystal
+0
+2
+2
+Crystal
+Crystal_SMD_3225-4Pin_3.2x2.5mm
+SMD Crystal SERIES SMD3225/4 http://www.txccrystal.com/images/pdf/7m-accuracy.pdf, 3.2x2.5mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_3225-4Pin_3.2x2.5mm_HandSoldering
+SMD Crystal SERIES SMD3225/4 http://www.txccrystal.com/images/pdf/7m-accuracy.pdf, hand-soldering, 3.2x2.5mm^2 package
+SMD SMT crystal hand-soldering
+0
+4
+4
+Crystal
+Crystal_SMD_5032-2Pin_5.0x3.2mm
+SMD Crystal SERIES SMD2520/2 http://www.icbase.com/File/PDF/HKC/HKC00061008.pdf, 5.0x3.2mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_5032-2Pin_5.0x3.2mm_HandSoldering
+SMD Crystal SERIES SMD2520/2 http://www.icbase.com/File/PDF/HKC/HKC00061008.pdf, hand-soldering, 5.0x3.2mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_5032-4Pin_5.0x3.2mm
+SMD Crystal SERIES SMD2520/4 http://www.icbase.com/File/PDF/HKC/HKC00061008.pdf, 5.0x3.2mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_7050-2Pin_7.0x5.0mm
+SMD Crystal SERIES SMD7050/4 https://www.foxonline.com/pdfs/FQ7050.pdf, 7.0x5.0mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_7050-2Pin_7.0x5.0mm_HandSoldering
+SMD Crystal SERIES SMD7050/4 https://www.foxonline.com/pdfs/FQ7050.pdf, hand-soldering, 7.0x5.0mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_7050-4Pin_7.0x5.0mm
+SMD Crystal SERIES SMD7050/4 https://www.foxonline.com/pdfs/FQ7050.pdf, 7.0x5.0mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_Abracon_ABM3-2Pin_5.0x3.2mm
+Abracon Miniature Ceramic Smd Crystal ABM3 http://www.abracon.com/Resonators/abm3.pdf, 5.0x3.2mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_Abracon_ABM3-2Pin_5.0x3.2mm_HandSoldering
+Abracon Miniature Ceramic Smd Crystal ABM3 http://www.abracon.com/Resonators/abm3.pdf, hand-soldering, 5.0x3.2mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_Abracon_ABM3B-4Pin_5.0x3.2mm
+Abracon Miniature Ceramic Smd Crystal ABM3B http://www.abracon.com/Resonators/abm3b.pdf, 5.0x3.2mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_Abracon_ABM3C-4Pin_5.0x3.2mm
+Abracon Miniature Ceramic Smd Crystal ABM3C http://www.abracon.com/Resonators/abm3c.pdf, 5.0x3.2mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_Abracon_ABM7-2Pin_6.0x3.5mm
+SMD Crystal Abracon ABM7, https://abracon.com/Resonators/abm7.pdf
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_Abracon_ABM8G-4Pin_3.2x2.5mm
+Abracon Miniature Ceramic Smd Crystal ABM8G http://www.abracon.com/Resonators/ABM8G.pdf, 3.2x2.5mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_Abracon_ABM10-4Pin_2.5x2.0mm
+Abracon Miniature Ceramic Smd Crystal ABM10 http://www.abracon.com/Resonators/ABM10.pdf
+SMD SMT crystal Abracon ABM10
+0
+4
+4
+Crystal
+Crystal_SMD_Abracon_ABS25-4Pin_8.0x3.8mm
+Abracon Miniature Ceramic SMD Crystal ABS25 https://abracon.com/Resonators/abs25.pdf, 8.0x3.8mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_ECS_CSM3X-2Pin_7.6x4.1mm
+http://www.ecsxtal.com/store/pdf/CSM-3X.pdf
+Crystal CSM-3X
+0
+2
+2
+Crystal
+Crystal_SMD_EuroQuartz_EQ161-2Pin_3.2x1.5mm
+SMD Crystal EuroQuartz EQ161 series http://cdn-reichelt.de/documents/datenblatt/B400/PG32768C.pdf, 3.2x1.5mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_EuroQuartz_EQ161-2Pin_3.2x1.5mm_HandSoldering
+SMD Crystal EuroQuartz EQ161 series http://cdn-reichelt.de/documents/datenblatt/B400/PG32768C.pdf, hand-soldering, 3.2x1.5mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_EuroQuartz_MJ-4Pin_5.0x3.2mm
+SMD Crystal EuroQuartz MJ series http://cdn-reichelt.de/documents/datenblatt/B400/MJ.pdf, 5.0x3.2mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_EuroQuartz_MJ-4Pin_5.0x3.2mm_HandSoldering
+SMD Crystal EuroQuartz MJ series http://cdn-reichelt.de/documents/datenblatt/B400/MJ.pdf, hand-soldering, 5.0x3.2mm^2 package
+SMD SMT crystal hand-soldering
+0
+4
+4
+Crystal
+Crystal_SMD_EuroQuartz_MQ-4Pin_7.0x5.0mm
+SMD Crystal EuroQuartz MQ series http://cdn-reichelt.de/documents/datenblatt/B400/MQ.pdf, 7.0x5.0mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_EuroQuartz_MQ-4Pin_7.0x5.0mm_HandSoldering
+SMD Crystal EuroQuartz MQ series http://cdn-reichelt.de/documents/datenblatt/B400/MQ.pdf, hand-soldering, 7.0x5.0mm^2 package
+SMD SMT crystal hand-soldering
+0
+4
+4
+Crystal
+Crystal_SMD_EuroQuartz_MQ2-2Pin_7.0x5.0mm
+SMD Crystal EuroQuartz MQ2 series http://cdn-reichelt.de/documents/datenblatt/B400/MQ.pdf, 7.0x5.0mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_EuroQuartz_MQ2-2Pin_7.0x5.0mm_HandSoldering
+SMD Crystal EuroQuartz MQ2 series http://cdn-reichelt.de/documents/datenblatt/B400/MQ.pdf, hand-soldering, 7.0x5.0mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_EuroQuartz_MT-4Pin_3.2x2.5mm
+SMD Crystal EuroQuartz MT series http://cdn-reichelt.de/documents/datenblatt/B400/MT.pdf, 3.2x2.5mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_EuroQuartz_MT-4Pin_3.2x2.5mm_HandSoldering
+SMD Crystal EuroQuartz MT series http://cdn-reichelt.de/documents/datenblatt/B400/MT.pdf, hand-soldering, 3.2x2.5mm^2 package
+SMD SMT crystal hand-soldering
+0
+4
+4
+Crystal
+Crystal_SMD_EuroQuartz_X22-4Pin_2.5x2.0mm
+SMD Crystal EuroQuartz X22 series http://cdn-reichelt.de/documents/datenblatt/B400/DS_X22.pdf, 2.5x2.0mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_EuroQuartz_X22-4Pin_2.5x2.0mm_HandSoldering
+SMD Crystal EuroQuartz X22 series http://cdn-reichelt.de/documents/datenblatt/B400/DS_X22.pdf, hand-soldering, 2.5x2.0mm^2 package
+SMD SMT crystal hand-soldering
+0
+4
+4
+Crystal
+Crystal_SMD_FOX_FE-2Pin_7.5x5.0mm
+crystal Ceramic Resin Sealed SMD http://www.foxonline.com/pdfs/fe.pdf, 7.5x5.0mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_FOX_FE-2Pin_7.5x5.0mm_HandSoldering
+crystal Ceramic Resin Sealed SMD http://www.foxonline.com/pdfs/fe.pdf, hand-soldering, 7.5x5.0mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_FOX_FQ7050-2Pin_7.0x5.0mm
+FOX SMD Crystal SERIES SMD7050/4 https://www.foxonline.com/pdfs/FQ7050.pdf, 7.0x5.0mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_FOX_FQ7050-2Pin_7.0x5.0mm_HandSoldering
+FOX SMD Crystal SERIES SMD7050/4 https://www.foxonline.com/pdfs/FQ7050.pdf, hand-soldering, 7.0x5.0mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_FOX_FQ7050-4Pin_7.0x5.0mm
+FOX SMD Crystal SERIES SMD7050/4 https://www.foxonline.com/pdfs/FQ7050.pdf, 7.0x5.0mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_FrontierElectronics_FM206
+SMD Watch Crystal FrontierElectronics FM206 6.0mm length 1.9mm diameter http://www.chinafronter.com/wp-content/uploads/2013/12/FM206.pdf
+['FM206']
+0
+3
+3
+Crystal
+Crystal_SMD_G8-2Pin_3.2x1.5mm
+SMD Crystal G8, 3.2x1.5mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_G8-2Pin_3.2x1.5mm_HandSoldering
+SMD Crystal G8, hand-soldering, 3.2x1.5mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_HC49-SD
+SMD Crystal HC-49-SD http://cdn-reichelt.de/documents/datenblatt/B400/xxx-HC49-SMD.pdf, 11.4x4.7mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_HC49-SD_HandSoldering
+SMD Crystal HC-49-SD http://cdn-reichelt.de/documents/datenblatt/B400/xxx-HC49-SMD.pdf, hand-soldering, 11.4x4.7mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_MicroCrystal_CC1V-T1A-2Pin_8.0x3.7mm
+SMD Crystal MicroCrystal CC1V-T1A series https://www.microcrystal.com/fileadmin/Media/Products/32kHz/Datasheet/CC1V-T1A.pdf, 8.0x3.7mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_MicroCrystal_CC1V-T1A-2Pin_8.0x3.7mm_HandSoldering
+SMD Crystal MicroCrystal CC1V-T1A series https://www.microcrystal.com/fileadmin/Media/Products/32kHz/Datasheet/CC1V-T1A.pdf, hand-soldering, 8.0x3.7mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_MicroCrystal_CC4V-T1A-2Pin_5.0x1.9mm
+SMD Crystal MicroCrystal CC4V-T1A series http://cdn-reichelt.de/documents/datenblatt/B400/CC4V-T1A.pdf, 5.0x1.9mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_MicroCrystal_CC4V-T1A-2Pin_5.0x1.9mm_HandSoldering
+SMD Crystal MicroCrystal CC4V-T1A series http://cdn-reichelt.de/documents/datenblatt/B400/CC4V-T1A.pdf, hand-soldering, 5.0x1.9mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_MicroCrystal_CC5V-T1A-2Pin_4.1x1.5mm
+SMD Crystal MicroCrystal CC5V-T1A series http://cdn-reichelt.de/documents/datenblatt/B400/CC5V-T1A.pdf, 4.1x1.5mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_MicroCrystal_CC5V-T1A-2Pin_4.1x1.5mm_HandSoldering
+SMD Crystal MicroCrystal CC5V-T1A series http://cdn-reichelt.de/documents/datenblatt/B400/CC5V-T1A.pdf, hand-soldering, 4.1x1.5mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_MicroCrystal_CC7V-T1A-2Pin_3.2x1.5mm
+SMD Crystal MicroCrystal CC7V-T1A/CM7V-T1A series https://www.microcrystal.com/fileadmin/Media/Products/32kHz/Datasheet/CC7V-T1A.pdf, 3.2x1.5mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_MicroCrystal_CC7V-T1A-2Pin_3.2x1.5mm_HandSoldering
+SMD Crystal MicroCrystal CC7V-T1A/CM7V-T1A series http://www.microcrystal.com/images/_Product-Documentation/01_TF_ceramic_Packages/01_Datasheet/CC1V-T1A.pdf, hand-soldering, 3.2x1.5mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_MicroCrystal_CC8V-T1A-2Pin_2.0x1.2mm
+SMD Crystal MicroCrystal CC8V-T1A/CM8V-T1A series https://www.microcrystal.com/fileadmin/Media/Products/32kHz/Datasheet/CC8V-T1A.pdf, 2.0x1.2mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_MicroCrystal_CC8V-T1A-2Pin_2.0x1.2mm_HandSoldering
+SMD Crystal MicroCrystal CC8V-T1A/CM8V-T1A series http://www.microcrystal.com/images/_Product-Documentation/01_TF_ceramic_Packages/01_Datasheet/CC8V-T1A.pdf, hand-soldering, 2.0x1.2mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_MicroCrystal_CM9V-T1A-2Pin_1.6x1.0mm
+SMD Crystal MicroCrystal CM9V-T1A series https://www.microcrystal.com/fileadmin/Media/Products/32kHz/Datasheet/CM9V-T1A.pdf, 1.6x1.0mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_MicroCrystal_CM9V-T1A-2Pin_1.6x1.0mm_HandSoldering
+SMD Crystal MicroCrystal CM9V-T1A series http://www.microcrystal.com/images/_Product-Documentation/01_TF_ceramic_Packages/01_Datasheet/CM9V-T1A.pdf, hand-soldering, 1.6x1.0mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_MicroCrystal_MS1V-T1K
+SMD Watch Crystal MicroCrystal MS1V-T1K 6.1mm length 2.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/MS1V-T1K.pdf
+['MS1V-T1K']
+0
+3
+3
+Crystal
+Crystal_SMD_MicroCrystal_MS3V-T1R
+SMD Watch Crystal MicroCrystal MS3V-T1R 5.2mm length 1.4mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/MS3V-T1R.pdf
+['MS3V-T1R']
+0
+3
+3
+Crystal
+Crystal_SMD_Qantek_QC5CB-2Pin_5x3.2mm
+SMD Crystal Qantek QC5CB, https://www.qantek.com/tl_files/products/crystals/QC5CB.pdf
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_SeikoEpson_FA238-4Pin_3.2x2.5mm
+crystal Epson Toyocom FA-238 https://support.epson.biz/td/api/doc_check.php?dl=brief_fa-238v_en.pdf, 3.2x2.5mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_SeikoEpson_FA238-4Pin_3.2x2.5mm_HandSoldering
+crystal Epson Toyocom FA-238 series https://support.epson.biz/td/api/doc_check.php?dl=brief_fa-238v_en.pdf, hand-soldering, 3.2x2.5mm^2 package
+SMD SMT crystal hand-soldering
+0
+4
+4
+Crystal
+Crystal_SMD_SeikoEpson_FA238V-4Pin_3.2x2.5mm
+crystal Epson Toyocom FA-238 series https://support.epson.biz/td/api/doc_check.php?dl=brief_fa-238v_en.pdf, 3.2x2.5mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_SeikoEpson_FA238V-4Pin_3.2x2.5mm_HandSoldering
+crystal Epson Toyocom FA-238 series http://www.mouser.com/ds/2/137/1721499-465440.pdf, hand-soldering, 3.2x2.5mm^2 package
+SMD SMT crystal hand-soldering
+0
+4
+4
+Crystal
+Crystal_SMD_SeikoEpson_MA406-4Pin_11.7x4.0mm
+SMD Crystal Seiko Epson MC-506 http://media.digikey.com/pdf/Data%20Sheets/Epson%20PDFs/MA-505,506.pdf, 11.7x4.0mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_SeikoEpson_MA406-4Pin_11.7x4.0mm_HandSoldering
+SMD Crystal Seiko Epson MC-506 http://media.digikey.com/pdf/Data%20Sheets/Epson%20PDFs/MA-505,506.pdf, hand-soldering, 11.7x4.0mm^2 package
+SMD SMT crystal hand-soldering
+0
+4
+4
+Crystal
+Crystal_SMD_SeikoEpson_MA505-2Pin_12.7x5.1mm
+SMD Crystal Seiko Epson MC-505 http://media.digikey.com/pdf/Data%20Sheets/Epson%20PDFs/MA-505,506.pdf, 12.7x5.1mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_SeikoEpson_MA505-2Pin_12.7x5.1mm_HandSoldering
+SMD Crystal Seiko Epson MC-505 http://media.digikey.com/pdf/Data%20Sheets/Epson%20PDFs/MA-505,506.pdf, hand-soldering, 12.7x5.1mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_SeikoEpson_MA506-4Pin_12.7x5.1mm
+SMD Crystal Seiko Epson MC-506 http://media.digikey.com/pdf/Data%20Sheets/Epson%20PDFs/MA-505,506.pdf, 12.7x5.1mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_SeikoEpson_MA506-4Pin_12.7x5.1mm_HandSoldering
+SMD Crystal Seiko Epson MC-506 http://media.digikey.com/pdf/Data%20Sheets/Epson%20PDFs/MA-505,506.pdf, hand-soldering, 12.7x5.1mm^2 package
+SMD SMT crystal hand-soldering
+0
+4
+4
+Crystal
+Crystal_SMD_SeikoEpson_MC146-4Pin_6.7x1.5mm
+SMD Crystal Seiko Epson MC-146 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-156_en.pdf, 6.7x1.5mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_SeikoEpson_MC146-4Pin_6.7x1.5mm_HandSoldering
+SMD Crystal Seiko Epson MC-146 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-156_en.pdf, hand-soldering, 6.7x1.5mm^2 package
+SMD SMT crystal hand-soldering
+0
+4
+4
+Crystal
+Crystal_SMD_SeikoEpson_MC156-4Pin_7.1x2.5mm
+SMD Crystal Seiko Epson MC-156 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-156_en.pdf, 7.1x2.5mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_SeikoEpson_MC156-4Pin_7.1x2.5mm_HandSoldering
+SMD Crystal Seiko Epson MC-156 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-156_en.pdf, hand-soldering, 7.1x2.5mm^2 package
+SMD SMT crystal hand-soldering
+0
+4
+4
+Crystal
+Crystal_SMD_SeikoEpson_MC306-4Pin_8.0x3.2mm
+SMD Crystal Seiko Epson MC-306 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306_en.pdf, 8.0x3.2mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_SeikoEpson_MC306-4Pin_8.0x3.2mm_HandSoldering
+SMD Crystal Seiko Epson MC-306 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306_en.pdf, hand-soldering, 8.0x3.2mm^2 package
+SMD SMT crystal hand-soldering
+0
+4
+4
+Crystal
+Crystal_SMD_SeikoEpson_MC405-2Pin_9.6x4.1mm
+SMD Crystal Seiko Epson MC-405 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306_en.pdf, 9.6x4.1mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_SeikoEpson_MC405-2Pin_9.6x4.1mm_HandSoldering
+SMD Crystal Seiko Epson MC-405 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306_en.pdf, hand-soldering, 9.6x4.1mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_SeikoEpson_MC406-4Pin_9.6x4.1mm
+SMD Crystal Seiko Epson MC-406 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306_en.pdf, 9.6x4.1mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_SeikoEpson_MC406-4Pin_9.6x4.1mm_HandSoldering
+SMD Crystal Seiko Epson MC-406 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306_en.pdf, hand-soldering, 9.6x4.1mm^2 package
+SMD SMT crystal hand-soldering
+0
+4
+4
+Crystal
+Crystal_SMD_SeikoEpson_TSX3225-4Pin_3.2x2.5mm
+crystal Epson Toyocom TSX-3225 series https://support.epson.biz/td/api/doc_check.php?dl=brief_fa-238v_en.pdf, 3.2x2.5mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_SeikoEpson_TSX3225-4Pin_3.2x2.5mm_HandSoldering
+crystal Epson Toyocom TSX-3225 series https://support.epson.biz/td/api/doc_check.php?dl=brief_fa-238v_en.pdf, hand-soldering, 3.2x2.5mm^2 package
+SMD SMT crystal hand-soldering
+0
+4
+4
+Crystal
+Crystal_SMD_TXC_7A-2Pin_5x3.2mm
+SMD Crystal TXC 7A http://txccrystal.com/images/pdf/7a.pdf
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_TXC_7M-4Pin_3.2x2.5mm
+SMD Crystal TXC 7M http://www.txccrystal.com/images/pdf/7m-accuracy.pdf, 3.2x2.5mm^2 package
+SMD SMT crystal
+0
+4
+4
+Crystal
+Crystal_SMD_TXC_7M-4Pin_3.2x2.5mm_HandSoldering
+SMD Crystal TXC 7M http://www.txccrystal.com/images/pdf/7m-accuracy.pdf, hand-soldering, 3.2x2.5mm^2 package
+SMD SMT crystal hand-soldering
+0
+4
+4
+Crystal
+Crystal_SMD_TXC_9HT11-2Pin_2.0x1.2mm
+SMD Crystal TXC 9HT11 http://txccrystal.com/images/pdf/9ht11.pdf, 2.0x1.2mm^2 package
+SMD SMT crystal
+0
+2
+2
+Crystal
+Crystal_SMD_TXC_9HT11-2Pin_2.0x1.2mm_HandSoldering
+SMD Crystal TXC 9HT11 http://txccrystal.com/images/pdf/9ht11.pdf, hand-soldering, 2.0x1.2mm^2 package
+SMD SMT crystal hand-soldering
+0
+2
+2
+Crystal
+Crystal_SMD_TXC_AX_8045-2Pin_8.0x4.5mm
+http://www.txccrystal.com/images/pdf/ax-automotive.pdf
+SMD SMT crystal
+0
+2
+2
+Crystal
+Resonator-2Pin_W6.0mm_H3.0mm
+Ceramic Resomator/Filter 6.0x3.0mm^2, length*width=6.0x3.0mm^2 package, package length=6.0mm, package width=3.0mm, 2 pins
+THT ceramic resonator filter
+0
+2
+2
+Crystal
+Resonator-2Pin_W7.0mm_H2.5mm
+Ceramic Resomator/Filter 7.0x2.5mm^2, length*width=7.0x2.5mm^2 package, package length=7.0mm, package width=2.5mm, 2 pins
+THT ceramic resonator filter
+0
+2
+2
+Crystal
+Resonator-2Pin_W8.0mm_H3.5mm
+Ceramic Resomator/Filter 8.0x3.5mm^2, length*width=8.0x3.5mm^2 package, package length=8.0mm, package width=3.5mm, 2 pins
+THT ceramic resonator filter
+0
+2
+2
+Crystal
+Resonator-2Pin_W10.0mm_H5.0mm
+Ceramic Resomator/Filter 10.0x5.0 RedFrequency MG/MT/MX series, http://www.red-frequency.com/download/datenblatt/redfrequency-datenblatt-ir-zta.pdf, length*width=10.0x5.0mm^2 package, package length=10.0mm, package width=5.0mm, 2 pins
+THT ceramic resonator filter
+0
+2
+2
+Crystal
+Resonator-3Pin_W6.0mm_H3.0mm
+Ceramic Resomator/Filter 6.0x3.0mm^2, length*width=6.0x3.0mm^2 package, package length=6.0mm, package width=3.0mm, 3 pins
+THT ceramic resonator filter
+0
+3
+3
+Crystal
+Resonator-3Pin_W7.0mm_H2.5mm
+Ceramic Resomator/Filter 7.0x2.5mm^2, length*width=7.0x2.5mm^2 package, package length=7.0mm, package width=2.5mm, 3 pins
+THT ceramic resonator filter
+0
+3
+3
+Crystal
+Resonator-3Pin_W8.0mm_H3.5mm
+Ceramic Resomator/Filter 8.0x3.5mm^2, length*width=8.0x3.5mm^2 package, package length=8.0mm, package width=3.5mm, 3 pins
+THT ceramic resonator filter
+0
+3
+3
+Crystal
+Resonator-3Pin_W10.0mm_H5.0mm
+Ceramic Resomator/Filter 10.0x5.0mm^2 RedFrequency MG/MT/MX series, http://www.red-frequency.com/download/datenblatt/redfrequency-datenblatt-ir-zta.pdf, length*width=10.0x5.0mm^2 package, package length=10.0mm, package width=5.0mm, 3 pins
+THT ceramic resonator filter
+0
+3
+3
+Crystal
+Resonator_SMD-3Pin_7.2x3.0mm
+SMD Resomator/Filter 7.2x3.0mm, Murata CSTCC8M00G53-R0; 8MHz resonator, SMD, Farnell (Element 14) #1170435, http://www.farnell.com/datasheets/19296.pdf?_ga=1.247244932.122297557.1475167906, 7.2x3.0mm^2 package
+SMD SMT ceramic resonator filter filter
+0
+3
+3
+Crystal
+Resonator_SMD-3Pin_7.2x3.0mm_HandSoldering
+SMD Resomator/Filter 7.2x3.0mm, Murata CSTCC8M00G53-R0; 8MHz resonator, SMD, Farnell (Element 14) #1170435, http://www.farnell.com/datasheets/19296.pdf?_ga=1.247244932.122297557.1475167906, hand-soldering, 7.2x3.0mm^2 package
+SMD SMT ceramic resonator filter filter hand-soldering
+0
+3
+3
+Crystal
+Resonator_SMD_muRata_CDSCB-2Pin_4.5x2.0mm
+SMD Resomator/Filter Murata CDSCB, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, 4.5x2.0mm^2 package
+SMD SMT ceramic resonator filter filter
+0
+2
+2
+Crystal
+Resonator_SMD_muRata_CDSCB-2Pin_4.5x2.0mm_HandSoldering
+SMD Resomator/Filter Murata CDSCB, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, hand-soldering, 4.5x2.0mm^2 package
+SMD SMT ceramic resonator filter filter hand-soldering
+0
+2
+2
+Crystal
+Resonator_SMD_muRata_CSTxExxV-3Pin_3.0x1.1mm
+SMD Resomator/Filter Murata CSTCE, https://www.murata.com/en-eu/products/productdata/8801162264606/SPEC-CSTNE16M0VH3C000R0.pdf
+SMD SMT ceramic resonator filter
+0
+3
+3
+Crystal
+Resonator_SMD_muRata_CSTxExxV-3Pin_3.0x1.1mm_HandSoldering
+SMD Resomator/Filter Murata CSTCE, https://www.murata.com/en-eu/products/productdata/8801162264606/SPEC-CSTNE16M0VH3C000R0.pdf
+SMD SMT ceramic resonator filter
+0
+3
+3
+Crystal
+Resonator_SMD_muRata_SFECV-3Pin_6.9x2.9mm
+SMD Resomator/Filter Murata SFECV, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, 6.9x2.9mm^2 package
+SMD SMT ceramic resonator filter filter
+0
+3
+3
+Crystal
+Resonator_SMD_muRata_SFECV-3Pin_6.9x2.9mm_HandSoldering
+SMD Resomator/Filter Murata SFECV, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, hand-soldering, 6.9x2.9mm^2 package
+SMD SMT ceramic resonator filter filter hand-soldering
+0
+3
+3
+Crystal
+Resonator_SMD_muRata_SFSKA-3Pin_7.9x3.8mm
+SMD Resomator/Filter Murata SFSKA, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, 7.9x3.8mm^2 package
+SMD SMT ceramic resonator filter filter
+0
+3
+3
+Crystal
+Resonator_SMD_muRata_SFSKA-3Pin_7.9x3.8mm_HandSoldering
+SMD Resomator/Filter Murata SFSKA, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, hand-soldering, 7.9x3.8mm^2 package
+SMD SMT ceramic resonator filter filter hand-soldering
+0
+3
+3
+Crystal
+Resonator_SMD_muRata_TPSKA-3Pin_7.9x3.8mm
+SMD Resomator/Filter Murata TPSKA, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, 7.9x3.8mm^2 package
+SMD SMT ceramic resonator filter filter
+0
+3
+3
+Crystal
+Resonator_SMD_muRata_TPSKA-3Pin_7.9x3.8mm_HandSoldering
+SMD Resomator/Filter Murata TPSKA, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, hand-soldering, 7.9x3.8mm^2 package
+SMD SMT ceramic resonator filter filter hand-soldering
+0
+3
+3
+Crystal
+Resonator_muRata_CSTLSxxxG-3Pin_W8.0mm_H3.0mm
+Ceramic Resomator/Filter Murata CSTLSxxxG, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/timingdevice/ceralock/p17e.ashx, length*width=8.0x3.0mm^2 package, package length=8.0mm, package width=3.0mm, 3 pins
+THT ceramic resonator filter CSTLSxxxG
+0
+3
+3
+Crystal
+Resonator_muRata_CSTLSxxxX-3Pin_W5.5mm_H3.0mm
+Ceramic Resomator/Filter Murata CSTLSxxxX, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/timingdevice/ceralock/p17e.ashx, length*width=5.5x3.0mm^2 package, package length=5.5mm, package width=3.0mm, 3 pins
+THT ceramic resonator filter CSTLSxxxX
+0
+3
+3
+Crystal
+Resonator_muRata_DSN6-3Pin_W7.0mm_H2.5mm
+Ceramic Resomator/Filter Murata DSN6, http://cdn-reichelt.de/documents/datenblatt/B400/DSN6NC51H.pdf, length*width=7.0x2.5mm^2 package, package length=7.0mm, package width=2.5mm, 3 pins
+THT ceramic resonator filter DSN6
+0
+3
+3
+Crystal
+Resonator_muRata_DSS6-3Pin_W7.0mm_H2.5mm
+Ceramic Resomator/Filter Murata DSS6, http://cdn-reichelt.de/documents/datenblatt/B400/DSN6NC51H.pdf, length*width=7.0x2.5mm^2 package, package length=7.0mm, package width=2.5mm, 3 pins
+THT ceramic resonator filter DSS6
+0
+3
+3
+Diode_SMD
+D_0201_0603Metric
+Diode SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator
+diode
+0
+4
+2
+Diode_SMD
+D_0402_1005Metric
+Diode SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+Diode_SMD
+D_0603_1608Metric
+Diode SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+Diode_SMD
+D_0603_1608Metric_Castellated
+Diode SMD 0603 (1608 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode castellated
+0
+2
+2
+Diode_SMD
+D_0603_1608Metric_Pad1.05x0.95mm_HandSolder
+Diode SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode handsolder
+0
+2
+2
+Diode_SMD
+D_0805_2012Metric
+Diode SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator
+diode
+0
+2
+2
+Diode_SMD
+D_0805_2012Metric_Castellated
+Diode SMD 0805 (2012 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator
+diode castellated
+0
+2
+2
+Diode_SMD
+D_0805_2012Metric_Pad1.15x1.40mm_HandSolder
+Diode SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator
+diode handsolder
+0
+2
+2
+Diode_SMD
+D_01005_0402Metric
+Diode SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator
+diode
+0
+4
+2
+Diode_SMD
+D_1206_3216Metric
+Diode SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+Diode_SMD
+D_1206_3216Metric_Castellated
+Diode SMD 1206 (3216 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode castellated
+0
+2
+2
+Diode_SMD
+D_1206_3216Metric_Pad1.42x1.75mm_HandSolder
+Diode SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode handsolder
+0
+2
+2
+Diode_SMD
+D_1210_3225Metric
+Diode SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+Diode_SMD
+D_1210_3225Metric_Castellated
+Diode SMD 1210 (3225 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode castellated
+0
+2
+2
+Diode_SMD
+D_1210_3225Metric_Pad1.42x2.65mm_HandSolder
+Diode SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode handsolder
+0
+2
+2
+Diode_SMD
+D_1806_4516Metric
+Diode SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+Diode_SMD
+D_1806_4516Metric_Castellated
+Diode SMD 1806 (4516 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator
+diode castellated
+0
+2
+2
+Diode_SMD
+D_1806_4516Metric_Pad1.57x1.80mm_HandSolder
+Diode SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator
+diode handsolder
+0
+2
+2
+Diode_SMD
+D_1812_4532Metric
+Diode SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+Diode_SMD
+D_1812_4532Metric_Castellated
+Diode SMD 1812 (4532 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator
+diode castellated
+0
+2
+2
+Diode_SMD
+D_1812_4532Metric_Pad1.30x3.40mm_HandSolder
+Diode SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator
+diode handsolder
+0
+2
+2
+Diode_SMD
+D_2010_5025Metric
+Diode SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+Diode_SMD
+D_2010_5025Metric_Castellated
+Diode SMD 2010 (5025 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode castellated
+0
+2
+2
+Diode_SMD
+D_2010_5025Metric_Pad1.52x2.65mm_HandSolder
+Diode SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode handsolder
+0
+2
+2
+Diode_SMD
+D_2114_3652Metric
+Diode SMD 2114 (3652 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+Diode_SMD
+D_2114_3652Metric_Castellated
+Diode SMD 2114 (3652 Metric), castellated end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator
+diode castellated
+0
+2
+2
+Diode_SMD
+D_2114_3652Metric_Pad1.85x3.75mm_HandSolder
+Diode SMD 2114 (3652 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator
+diode handsolder
+0
+2
+2
+Diode_SMD
+D_2512_6332Metric
+Diode SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+Diode_SMD
+D_2512_6332Metric_Castellated
+Diode SMD 2512 (6332 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode castellated
+0
+2
+2
+Diode_SMD
+D_2512_6332Metric_Pad1.52x3.35mm_HandSolder
+Diode SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode handsolder
+0
+2
+2
+Diode_SMD
+D_2816_7142Metric
+Diode SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+Diode_SMD
+D_2816_7142Metric_Castellated
+Diode SMD 2816 (7142 Metric), castellated end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator
+diode castellated
+0
+2
+2
+Diode_SMD
+D_2816_7142Metric_Pad3.20x4.45mm_HandSolder
+Diode SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator
+diode handsolder
+0
+2
+2
+Diode_SMD
+D_3220_8050Metric
+Diode SMD 3220 (8050 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+Diode_SMD
+D_3220_8050Metric_Castellated
+Diode SMD 3220 (8050 Metric), castellated end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator
+diode castellated
+0
+2
+2
+Diode_SMD
+D_3220_8050Metric_Pad2.65x5.15mm_HandSolder
+Diode SMD 3220 (8050 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator
+diode handsolder
+0
+2
+2
+Diode_SMD
+D_MELF
+Diode, MELF,,
+Diode MELF 
+0
+2
+2
+Diode_SMD
+D_MELF-RM10_Universal_Handsoldering
+Diode, Universal, MELF, RM10, Handsoldering, SMD, Thruhole,
+Diode Universal MELF RM10 Handsoldering SMD Thruhole 
+0
+2
+2
+Diode_SMD
+D_MELF_Handsoldering
+Diode MELF Handsoldering
+Diode MELF Handsoldering
+0
+2
+2
+Diode_SMD
+D_MicroMELF
+Diode, MicroMELF, Reflow Soldering, http://www.vishay.com/docs/85597/bzm55.pdf
+MicroMELF Diode
+0
+2
+2
+Diode_SMD
+D_MicroMELF_Handsoldering
+Diode, MicroMELF, Hand Soldering, http://www.vishay.com/docs/85597/bzm55.pdf
+MicroMELF Diode
+0
+2
+2
+Diode_SMD
+D_MiniMELF
+Diode Mini-MELF
+Diode Mini-MELF
+0
+2
+2
+Diode_SMD
+D_MiniMELF_Handsoldering
+Diode Mini-MELF Handsoldering
+Diode Mini-MELF Handsoldering
+0
+2
+2
+Diode_SMD
+D_PowerDI-5
+PowerDI,Diode,Vishay,https://www.diodes.com/assets/Package-Files/PowerDI5.pdf
+PowerDI diode vishay
+0
+3
+2
+Diode_SMD
+D_PowerDI-123
+http://www.diodes.com/_files/datasheets/ds30497.pdf
+PowerDI diode vishay
+0
+2
+2
+Diode_SMD
+D_Powermite2_AK
+Microsemi Powermite 2 SMD power package (https://www.microsemi.com/packaging-information/partpackage/details?pid=5341)
+PowerMite2
+0
+2
+2
+Diode_SMD
+D_Powermite2_KA
+Microsemi Powermite 2 SMD power package (https://www.microsemi.com/packaging-information/partpackage/details?pid=5341)
+PowerMite2
+0
+2
+2
+Diode_SMD
+D_Powermite3
+Microsemi Powermite 3 SMD power package (https://www.microsemi.com/packaging-information/partpackage/details?pid=5340)
+PowerMite3
+0
+3
+3
+Diode_SMD
+D_Powermite_AK
+Microsemi Powermite SMD power package (https://www.microsemi.com/packaging-information/partpackage/details?pid=5339, https://www.onsemi.com/pub/Collateral/457-04.PDF)
+Powermite
+0
+2
+2
+Diode_SMD
+D_Powermite_KA
+Microsemi Powermite SMD power package (https://www.microsemi.com/packaging-information/partpackage/details?pid=5339, https://www.onsemi.com/pub/Collateral/457-04.PDF)
+Powermite
+0
+2
+2
+Diode_SMD
+D_QFN_3.3x3.3mm_P0.65mm
+QFN, diode, 3.3x3.3x1mm (https://www.wolfspeed.com/media/downloads/846/C3D1P7060Q.pdf)
+diode qfn 3.3
+0
+3
+2
+Diode_SMD
+D_SC-80
+JEITA SC-80
+SC-80
+0
+2
+2
+Diode_SMD
+D_SC-80_HandSoldering
+JEITA SC-80
+SC-80
+0
+2
+2
+Diode_SMD
+D_SMA
+Diode SMA (DO-214AC)
+Diode SMA (DO-214AC)
+0
+2
+2
+Diode_SMD
+D_SMA-SMB_Universal_Handsoldering
+Diode, Universal, SMA (DO-214AC) or SMB (DO-214AA), Handsoldering,
+Diode Universal SMA (DO-214AC) SMB (DO-214AA) Handsoldering 
+0
+2
+2
+Diode_SMD
+D_SMA_Handsoldering
+Diode SMA (DO-214AC) Handsoldering
+Diode SMA (DO-214AC) Handsoldering
+0
+2
+2
+Diode_SMD
+D_SMB
+Diode SMB (DO-214AA)
+Diode SMB (DO-214AA)
+0
+2
+2
+Diode_SMD
+D_SMB-SMC_Universal_Handsoldering
+Diode, Universal, SMB(DO-214AA) or SMC (DO-214AB), Handsoldering,
+Diode Universal SMB(DO-214AA) SMC (DO-214AB) Handsoldering 
+0
+2
+2
+Diode_SMD
+D_SMB_Handsoldering
+Diode SMB (DO-214AA) Handsoldering
+Diode SMB (DO-214AA) Handsoldering
+0
+2
+2
+Diode_SMD
+D_SMB_Modified
+Diode SMB (DO-214AA) Modified (http://www.littelfuse.com/~/media/electronics/datasheets/sidactors/littelfuse_sidactor_battrax_positive_negative_modified_do_214_datasheet.pdf.pdf)
+Diode SMB (DO-214AA)
+0
+3
+3
+Diode_SMD
+D_SMC
+Diode SMC (DO-214AB)
+Diode SMC (DO-214AB)
+0
+2
+2
+Diode_SMD
+D_SMC-RM10_Universal_Handsoldering
+Diode, Universal, SMC (DO-214AB), RM10, Handsoldering, SMD, Thruhole
+Diode Universal SMC (DO-214AB) RM10 Handsoldering SMD Thruhole
+0
+2
+2
+Diode_SMD
+D_SMC_Handsoldering
+Diode SMC (DO-214AB) Handsoldering
+Diode SMC (DO-214AB) Handsoldering
+0
+2
+2
+Diode_SMD
+D_SMF
+Diode SMF (DO-219AB), http://www.vishay.com/docs/95572/smf_do-219ab.pdf
+Diode SMF (DO-214AB)
+0
+2
+2
+Diode_SMD
+D_SOD-110
+SOD-110
+SOD-110
+0
+2
+2
+Diode_SMD
+D_SOD-123
+SOD-123
+SOD-123
+0
+2
+2
+Diode_SMD
+D_SOD-123F
+D_SOD-123F
+D_SOD-123F
+0
+2
+2
+Diode_SMD
+D_SOD-128
+D_SOD-128 (CFP5 SlimSMAW), https://assets.nexperia.com/documents/outline-drawing/SOD128.pdf
+D_SOD-128
+0
+2
+2
+Diode_SMD
+D_SOD-323
+SOD-323
+SOD-323
+0
+2
+2
+Diode_SMD
+D_SOD-323F
+SOD-323F http://www.nxp.com/documents/outline_drawing/SOD323F.pdf
+SOD-323F
+0
+2
+2
+Diode_SMD
+D_SOD-323_HandSoldering
+SOD-323
+SOD-323
+0
+2
+2
+Diode_SMD
+D_SOD-523
+http://www.diodes.com/datasheets/ap02001.pdf p.144
+Diode SOD523
+0
+2
+2
+Diode_SMD
+D_SOT-23_ANK
+SOT-23, Single Diode
+SOT-23
+0
+3
+2
+Diode_SMD
+D_SOT-23_NKA
+SOT-23, Single Diode
+SOT-23
+0
+3
+2
+Diode_SMD
+D_TUMD2
+ROHM - TUMD2
+TUMD2
+0
+2
+2
+Diode_SMD
+Diode_Bridge_Bourns_CD-DF4xxS
+8.1x10.5mm, 4A, single phase bridge rectifier, https://www.bourns.com/docs/Product-Datasheets/CD-DF4xxSL.pdf
+Surface Mount Bridge Rectifier Diode
+0
+4
+4
+Diode_SMD
+Diode_Bridge_Diotec_ABS
+SMD diode bridge ABS (Diotec), see https://diotec.com/tl_files/diotec/files/pdf/datasheets/abs2.pdf
+ABS MBLS
+0
+4
+4
+Diode_SMD
+Diode_Bridge_Diotec_MicroDil_3.0x3.0x1.8mm
+SMD package Diotec Diotec MicroDil, body 3.0x3.0x1.8mm (e.g. diode bridge), see https://diotec.com/tl_files/diotec/files/pdf/datasheets/mys40.pdf
+Diotec MicroDil diode bridge
+0
+4
+4
+Diode_SMD
+Diode_Bridge_Diotec_SO-DIL-Slim
+SMD diode bridge Diotec SO-DIL Slim, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/b40fs.pdf
+DFS SO-DIL Slim
+0
+4
+4
+Diode_SMD
+Diode_Bridge_Vishay_DFS
+SMD diode bridge DFS, see http://www.vishay.com/docs/88854/padlayouts.pdf
+DFS
+0
+4
+4
+Diode_SMD
+Diode_Bridge_Vishay_DFSFlat
+SMD diode bridge Low Profile DFS "Flat", see http://www.vishay.com/docs/88874/dfl15005.pdf
+DFS
+0
+4
+4
+Diode_SMD
+Diode_Bridge_Vishay_MBLS
+SMD diode bridge MBLS, see http://www.vishay.com/docs/89959/mbl104s.pdf http://www.vishay.com/docs/88854/padlayouts.pdf
+DFS
+0
+4
+4
+Diode_SMD
+Littelfuse_PolyZen-LS
+http://m.littelfuse.com/~/media/electronics/datasheets/polyzen_devices/littelfuse_polyzen_standard_polyzen_catalog_datasheet.pdf.pdf
+Diode Polymer Protected Zener Diode Littelfuse LS
+0
+3
+3
+Diode_THT
+D_5KPW_P7.62mm_Vertical_AnodeUp
+Diode, 5KPW series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=9*8mm^2, , http://www.diodes.com/_files/packages/8686949.gif
+Diode 5KPW series Axial Vertical pin pitch 7.62mm  length 9mm diameter 8mm
+0
+2
+2
+Diode_THT
+D_5KPW_P7.62mm_Vertical_KathodeUp
+Diode, 5KPW series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=9*8mm^2, , http://www.diodes.com/_files/packages/8686949.gif
+Diode 5KPW series Axial Vertical pin pitch 7.62mm  length 9mm diameter 8mm
+0
+2
+2
+Diode_THT
+D_5KPW_P12.70mm_Horizontal
+Diode, 5KPW series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9*8mm^2, , http://www.diodes.com/_files/packages/8686949.gif
+Diode 5KPW series Axial Horizontal pin pitch 12.7mm  length 9mm diameter 8mm
+0
+2
+2
+Diode_THT
+D_5KP_P7.62mm_Vertical_AnodeUp
+Diode, 5KP series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=7.62*9.53mm^2, , http://www.diodes.com/_files/packages/8686949.gif
+Diode 5KP series Axial Vertical pin pitch 7.62mm  length 7.62mm diameter 9.53mm
+0
+2
+2
+Diode_THT
+D_5KP_P7.62mm_Vertical_KathodeUp
+Diode, 5KP series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=7.62*9.53mm^2, , http://www.diodes.com/_files/packages/8686949.gif
+Diode 5KP series Axial Vertical pin pitch 7.62mm  length 7.62mm diameter 9.53mm
+0
+2
+2
+Diode_THT
+D_5KP_P10.16mm_Horizontal
+Diode, 5KP series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=7.62*9.53mm^2, , http://www.diodes.com/_files/packages/8686949.gif
+Diode 5KP series Axial Horizontal pin pitch 10.16mm  length 7.62mm diameter 9.53mm
+0
+2
+2
+Diode_THT
+D_5KP_P12.70mm_Horizontal
+Diode, 5KP series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=7.62*9.53mm^2, , http://www.diodes.com/_files/packages/8686949.gif
+Diode 5KP series Axial Horizontal pin pitch 12.7mm  length 7.62mm diameter 9.53mm
+0
+2
+2
+Diode_THT
+D_5W_P5.08mm_Vertical_AnodeUp
+Diode, 5W series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=8.9*3.7mm^2, , http://www.diodes.com/_files/packages/8686949.gif
+Diode 5W series Axial Vertical pin pitch 5.08mm  length 8.9mm diameter 3.7mm
+0
+2
+2
+Diode_THT
+D_5W_P5.08mm_Vertical_KathodeUp
+Diode, 5W series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=8.9*3.7mm^2, , http://www.diodes.com/_files/packages/8686949.gif
+Diode 5W series Axial Vertical pin pitch 5.08mm  length 8.9mm diameter 3.7mm
+0
+2
+2
+Diode_THT
+D_5W_P10.16mm_Horizontal
+Diode, 5W series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=8.9*3.7mm^2, , http://www.diodes.com/_files/packages/8686949.gif
+Diode 5W series Axial Horizontal pin pitch 10.16mm  length 8.9mm diameter 3.7mm
+0
+2
+2
+Diode_THT
+D_5W_P12.70mm_Horizontal
+Diode, 5W series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=8.9*3.7mm^2, , http://www.diodes.com/_files/packages/8686949.gif
+Diode 5W series Axial Horizontal pin pitch 12.7mm  length 8.9mm diameter 3.7mm
+0
+2
+2
+Diode_THT
+D_A-405_P2.54mm_Vertical_AnodeUp
+Diode, A-405 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf
+Diode A-405 series Axial Vertical pin pitch 2.54mm  length 5.2mm diameter 2.7mm
+0
+2
+2
+Diode_THT
+D_A-405_P2.54mm_Vertical_KathodeUp
+Diode, A-405 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf
+Diode A-405 series Axial Vertical pin pitch 2.54mm  length 5.2mm diameter 2.7mm
+0
+2
+2
+Diode_THT
+D_A-405_P5.08mm_Vertical_AnodeUp
+Diode, A-405 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf
+Diode A-405 series Axial Vertical pin pitch 5.08mm  length 5.2mm diameter 2.7mm
+0
+2
+2
+Diode_THT
+D_A-405_P5.08mm_Vertical_KathodeUp
+Diode, A-405 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf
+Diode A-405 series Axial Vertical pin pitch 5.08mm  length 5.2mm diameter 2.7mm
+0
+2
+2
+Diode_THT
+D_A-405_P7.62mm_Horizontal
+Diode, A-405 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf
+Diode A-405 series Axial Horizontal pin pitch 7.62mm  length 5.2mm diameter 2.7mm
+0
+2
+2
+Diode_THT
+D_A-405_P10.16mm_Horizontal
+Diode, A-405 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf
+Diode A-405 series Axial Horizontal pin pitch 10.16mm  length 5.2mm diameter 2.7mm
+0
+2
+2
+Diode_THT
+D_A-405_P12.70mm_Horizontal
+Diode, A-405 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf
+Diode A-405 series Axial Horizontal pin pitch 12.7mm  length 5.2mm diameter 2.7mm
+0
+2
+2
+Diode_THT
+D_DO-15_P2.54mm_Vertical_AnodeUp
+Diode, DO-15 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf
+Diode DO-15 series Axial Vertical pin pitch 2.54mm  length 7.6mm diameter 3.6mm
+0
+2
+2
+Diode_THT
+D_DO-15_P2.54mm_Vertical_KathodeUp
+Diode, DO-15 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf
+Diode DO-15 series Axial Vertical pin pitch 2.54mm  length 7.6mm diameter 3.6mm
+0
+2
+2
+Diode_THT
+D_DO-15_P3.81mm_Vertical_AnodeUp
+Diode, DO-15 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf
+Diode DO-15 series Axial Vertical pin pitch 3.81mm  length 7.6mm diameter 3.6mm
+0
+2
+2
+Diode_THT
+D_DO-15_P3.81mm_Vertical_KathodeUp
+Diode, DO-15 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf
+Diode DO-15 series Axial Vertical pin pitch 3.81mm  length 7.6mm diameter 3.6mm
+0
+2
+2
+Diode_THT
+D_DO-15_P5.08mm_Vertical_AnodeUp
+Diode, DO-15 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf
+Diode DO-15 series Axial Vertical pin pitch 5.08mm  length 7.6mm diameter 3.6mm
+0
+2
+2
+Diode_THT
+D_DO-15_P5.08mm_Vertical_KathodeUp
+Diode, DO-15 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf
+Diode DO-15 series Axial Vertical pin pitch 5.08mm  length 7.6mm diameter 3.6mm
+0
+2
+2
+Diode_THT
+D_DO-15_P10.16mm_Horizontal
+Diode, DO-15 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf
+Diode DO-15 series Axial Horizontal pin pitch 10.16mm  length 7.6mm diameter 3.6mm
+0
+2
+2
+Diode_THT
+D_DO-15_P12.70mm_Horizontal
+Diode, DO-15 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf
+Diode DO-15 series Axial Horizontal pin pitch 12.7mm  length 7.6mm diameter 3.6mm
+0
+2
+2
+Diode_THT
+D_DO-15_P15.24mm_Horizontal
+Diode, DO-15 series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf
+Diode DO-15 series Axial Horizontal pin pitch 15.24mm  length 7.6mm diameter 3.6mm
+0
+2
+2
+Diode_THT
+D_DO-27_P5.08mm_Vertical_AnodeUp
+Diode, DO-27 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.52*5.33mm^2, , http://www.slottechforum.com/slotinfo/Techstuff/CD2%20Diodes%20and%20Transistors/Cases/Diode%20DO-27.jpg
+Diode DO-27 series Axial Vertical pin pitch 5.08mm  length 9.52mm diameter 5.33mm
+0
+2
+2
+Diode_THT
+D_DO-27_P5.08mm_Vertical_KathodeUp
+Diode, DO-27 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.52*5.33mm^2, , http://www.slottechforum.com/slotinfo/Techstuff/CD2%20Diodes%20and%20Transistors/Cases/Diode%20DO-27.jpg
+Diode DO-27 series Axial Vertical pin pitch 5.08mm  length 9.52mm diameter 5.33mm
+0
+2
+2
+Diode_THT
+D_DO-27_P12.70mm_Horizontal
+Diode, DO-27 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9.52*5.33mm^2, , http://www.slottechforum.com/slotinfo/Techstuff/CD2%20Diodes%20and%20Transistors/Cases/Diode%20DO-27.jpg
+Diode DO-27 series Axial Horizontal pin pitch 12.7mm  length 9.52mm diameter 5.33mm
+0
+2
+2
+Diode_THT
+D_DO-27_P15.24mm_Horizontal
+Diode, DO-27 series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=9.52*5.33mm^2, , http://www.slottechforum.com/slotinfo/Techstuff/CD2%20Diodes%20and%20Transistors/Cases/Diode%20DO-27.jpg
+Diode DO-27 series Axial Horizontal pin pitch 15.24mm  length 9.52mm diameter 5.33mm
+0
+2
+2
+Diode_THT
+D_DO-34_SOD68_P2.54mm_Vertical_AnodeUp
+Diode, DO-34_SOD68 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf
+Diode DO-34_SOD68 series Axial Vertical pin pitch 2.54mm  length 3.04mm diameter 1.6mm
+0
+2
+2
+Diode_THT
+D_DO-34_SOD68_P2.54mm_Vertical_KathodeUp
+Diode, DO-34_SOD68 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf
+Diode DO-34_SOD68 series Axial Vertical pin pitch 2.54mm  length 3.04mm diameter 1.6mm
+0
+2
+2
+Diode_THT
+D_DO-34_SOD68_P5.08mm_Vertical_AnodeUp
+Diode, DO-34_SOD68 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf
+Diode DO-34_SOD68 series Axial Vertical pin pitch 5.08mm  length 3.04mm diameter 1.6mm
+0
+2
+2
+Diode_THT
+D_DO-34_SOD68_P5.08mm_Vertical_KathodeUp
+Diode, DO-34_SOD68 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf
+Diode DO-34_SOD68 series Axial Vertical pin pitch 5.08mm  length 3.04mm diameter 1.6mm
+0
+2
+2
+Diode_THT
+D_DO-34_SOD68_P7.62mm_Horizontal
+Diode, DO-34_SOD68 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf
+Diode DO-34_SOD68 series Axial Horizontal pin pitch 7.62mm  length 3.04mm diameter 1.6mm
+0
+2
+2
+Diode_THT
+D_DO-34_SOD68_P10.16mm_Horizontal
+Diode, DO-34_SOD68 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf
+Diode DO-34_SOD68 series Axial Horizontal pin pitch 10.16mm  length 3.04mm diameter 1.6mm
+0
+2
+2
+Diode_THT
+D_DO-34_SOD68_P12.70mm_Horizontal
+Diode, DO-34_SOD68 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf
+Diode DO-34_SOD68 series Axial Horizontal pin pitch 12.7mm  length 3.04mm diameter 1.6mm
+0
+2
+2
+Diode_THT
+D_DO-35_SOD27_P2.54mm_Vertical_AnodeUp
+Diode, DO-35_SOD27 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf
+Diode DO-35_SOD27 series Axial Vertical pin pitch 2.54mm  length 4mm diameter 2mm
+0
+2
+2
+Diode_THT
+D_DO-35_SOD27_P2.54mm_Vertical_KathodeUp
+Diode, DO-35_SOD27 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf
+Diode DO-35_SOD27 series Axial Vertical pin pitch 2.54mm  length 4mm diameter 2mm
+0
+2
+2
+Diode_THT
+D_DO-35_SOD27_P3.81mm_Vertical_AnodeUp
+Diode, DO-35_SOD27 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf
+Diode DO-35_SOD27 series Axial Vertical pin pitch 3.81mm  length 4mm diameter 2mm
+0
+2
+2
+Diode_THT
+D_DO-35_SOD27_P3.81mm_Vertical_KathodeUp
+Diode, DO-35_SOD27 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf
+Diode DO-35_SOD27 series Axial Vertical pin pitch 3.81mm  length 4mm diameter 2mm
+0
+2
+2
+Diode_THT
+D_DO-35_SOD27_P5.08mm_Vertical_AnodeUp
+Diode, DO-35_SOD27 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf
+Diode DO-35_SOD27 series Axial Vertical pin pitch 5.08mm  length 4mm diameter 2mm
+0
+2
+2
+Diode_THT
+D_DO-35_SOD27_P5.08mm_Vertical_KathodeUp
+Diode, DO-35_SOD27 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf
+Diode DO-35_SOD27 series Axial Vertical pin pitch 5.08mm  length 4mm diameter 2mm
+0
+2
+2
+Diode_THT
+D_DO-35_SOD27_P7.62mm_Horizontal
+Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf
+Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm  length 4mm diameter 2mm
+0
+2
+2
+Diode_THT
+D_DO-35_SOD27_P10.16mm_Horizontal
+Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf
+Diode DO-35_SOD27 series Axial Horizontal pin pitch 10.16mm  length 4mm diameter 2mm
+0
+2
+2
+Diode_THT
+D_DO-35_SOD27_P12.70mm_Horizontal
+Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf
+Diode DO-35_SOD27 series Axial Horizontal pin pitch 12.7mm  length 4mm diameter 2mm
+0
+2
+2
+Diode_THT
+D_DO-41_SOD81_P2.54mm_Vertical_AnodeUp
+Diode, DO-41_SOD81 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf
+Diode DO-41_SOD81 series Axial Vertical pin pitch 2.54mm  length 5.2mm diameter 2.7mm
+0
+2
+2
+Diode_THT
+D_DO-41_SOD81_P2.54mm_Vertical_KathodeUp
+Diode, DO-41_SOD81 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf
+Diode DO-41_SOD81 series Axial Vertical pin pitch 2.54mm  length 5.2mm diameter 2.7mm
+0
+2
+2
+Diode_THT
+D_DO-41_SOD81_P3.81mm_Vertical_AnodeUp
+Diode, DO-41_SOD81 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=5.2*2.7mm^2, , https://www.diodes.com/assets/Package-Files/DO-41-Plastic.pdf
+Diode DO-41_SOD81 series Axial Vertical pin pitch 3.81mm  length 5.2mm diameter 2.7mm
+0
+2
+2
+Diode_THT
+D_DO-41_SOD81_P3.81mm_Vertical_KathodeUp
+Diode, DO-41_SOD81 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=5.2*2.7mm^2, , https://www.diodes.com/assets/Package-Files/DO-41-Plastic.pdf
+Diode DO-41_SOD81 series Axial Vertical pin pitch 3.81mm  length 5.2mm diameter 2.7mm
+0
+2
+2
+Diode_THT
+D_DO-41_SOD81_P5.08mm_Vertical_AnodeUp
+Diode, DO-41_SOD81 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf
+Diode DO-41_SOD81 series Axial Vertical pin pitch 5.08mm  length 5.2mm diameter 2.7mm
+0
+2
+2
+Diode_THT
+D_DO-41_SOD81_P5.08mm_Vertical_KathodeUp
+Diode, DO-41_SOD81 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf
+Diode DO-41_SOD81 series Axial Vertical pin pitch 5.08mm  length 5.2mm diameter 2.7mm
+0
+2
+2
+Diode_THT
+D_DO-41_SOD81_P7.62mm_Horizontal
+Diode, DO-41_SOD81 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf
+Diode DO-41_SOD81 series Axial Horizontal pin pitch 7.62mm  length 5.2mm diameter 2.7mm
+0
+2
+2
+Diode_THT
+D_DO-41_SOD81_P10.16mm_Horizontal
+Diode, DO-41_SOD81 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf
+Diode DO-41_SOD81 series Axial Horizontal pin pitch 10.16mm  length 5.2mm diameter 2.7mm
+0
+2
+2
+Diode_THT
+D_DO-41_SOD81_P12.70mm_Horizontal
+Diode, DO-41_SOD81 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf
+Diode DO-41_SOD81 series Axial Horizontal pin pitch 12.7mm  length 5.2mm diameter 2.7mm
+0
+2
+2
+Diode_THT
+D_DO-201AD_P3.81mm_Vertical_AnodeUp
+Diode, DO-201AD series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=9.5*5.2mm^2, , http://www.diodes.com/_files/packages/DO-201AD.pdf
+Diode DO-201AD series Axial Vertical pin pitch 3.81mm  length 9.5mm diameter 5.2mm
+0
+2
+2
+Diode_THT
+D_DO-201AD_P3.81mm_Vertical_KathodeUp
+Diode, DO-201AD series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=9.5*5.2mm^2, , http://www.diodes.com/_files/packages/DO-201AD.pdf
+Diode DO-201AD series Axial Vertical pin pitch 3.81mm  length 9.5mm diameter 5.2mm
+0
+2
+2
+Diode_THT
+D_DO-201AD_P5.08mm_Vertical_AnodeUp
+Diode, DO-201AD series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.5*5.2mm^2, , http://www.diodes.com/_files/packages/DO-201AD.pdf
+Diode DO-201AD series Axial Vertical pin pitch 5.08mm  length 9.5mm diameter 5.2mm
+0
+2
+2
+Diode_THT
+D_DO-201AD_P5.08mm_Vertical_KathodeUp
+Diode, DO-201AD series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.5*5.2mm^2, , http://www.diodes.com/_files/packages/DO-201AD.pdf
+Diode DO-201AD series Axial Vertical pin pitch 5.08mm  length 9.5mm diameter 5.2mm
+0
+2
+2
+Diode_THT
+D_DO-201AD_P12.70mm_Horizontal
+Diode, DO-201AD series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9.5*5.2mm^2, , http://www.diodes.com/_files/packages/DO-201AD.pdf
+Diode DO-201AD series Axial Horizontal pin pitch 12.7mm  length 9.5mm diameter 5.2mm
+0
+2
+2
+Diode_THT
+D_DO-201AD_P15.24mm_Horizontal
+Diode, DO-201AD series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=9.5*5.2mm^2, , http://www.diodes.com/_files/packages/DO-201AD.pdf
+Diode DO-201AD series Axial Horizontal pin pitch 15.24mm  length 9.5mm diameter 5.2mm
+0
+2
+2
+Diode_THT
+D_DO-201AE_P3.81mm_Vertical_AnodeUp
+Diode, DO-201AE series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=9*5.3mm^2, , http://www.farnell.com/datasheets/529758.pdf
+Diode DO-201AE series Axial Vertical pin pitch 3.81mm  length 9mm diameter 5.3mm
+0
+2
+2
+Diode_THT
+D_DO-201AE_P3.81mm_Vertical_KathodeUp
+Diode, DO-201AE series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=9*5.3mm^2, , http://www.farnell.com/datasheets/529758.pdf
+Diode DO-201AE series Axial Vertical pin pitch 3.81mm  length 9mm diameter 5.3mm
+0
+2
+2
+Diode_THT
+D_DO-201AE_P5.08mm_Vertical_AnodeUp
+Diode, DO-201AE series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9*5.3mm^2, , http://www.farnell.com/datasheets/529758.pdf
+Diode DO-201AE series Axial Vertical pin pitch 5.08mm  length 9mm diameter 5.3mm
+0
+2
+2
+Diode_THT
+D_DO-201AE_P5.08mm_Vertical_KathodeUp
+Diode, DO-201AE series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9*5.3mm^2, , http://www.farnell.com/datasheets/529758.pdf
+Diode DO-201AE series Axial Vertical pin pitch 5.08mm  length 9mm diameter 5.3mm
+0
+2
+2
+Diode_THT
+D_DO-201AE_P12.70mm_Horizontal
+Diode, DO-201AE series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9*5.3mm^2, , http://www.farnell.com/datasheets/529758.pdf
+Diode DO-201AE series Axial Horizontal pin pitch 12.7mm  length 9mm diameter 5.3mm
+0
+2
+2
+Diode_THT
+D_DO-201AE_P15.24mm_Horizontal
+Diode, DO-201AE series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=9*5.3mm^2, , http://www.farnell.com/datasheets/529758.pdf
+Diode DO-201AE series Axial Horizontal pin pitch 15.24mm  length 9mm diameter 5.3mm
+0
+2
+2
+Diode_THT
+D_DO-201_P3.81mm_Vertical_AnodeUp
+Diode, DO-201 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=9.53*5.21mm^2, , http://www.diodes.com/_files/packages/DO-201.pdf
+Diode DO-201 series Axial Vertical pin pitch 3.81mm  length 9.53mm diameter 5.21mm
+0
+2
+2
+Diode_THT
+D_DO-201_P3.81mm_Vertical_KathodeUp
+Diode, DO-201 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=9.53*5.21mm^2, , http://www.diodes.com/_files/packages/DO-201.pdf
+Diode DO-201 series Axial Vertical pin pitch 3.81mm  length 9.53mm diameter 5.21mm
+0
+2
+2
+Diode_THT
+D_DO-201_P5.08mm_Vertical_AnodeUp
+Diode, DO-201 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.53*5.21mm^2, , http://www.diodes.com/_files/packages/DO-201.pdf
+Diode DO-201 series Axial Vertical pin pitch 5.08mm  length 9.53mm diameter 5.21mm
+0
+2
+2
+Diode_THT
+D_DO-201_P5.08mm_Vertical_KathodeUp
+Diode, DO-201 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.53*5.21mm^2, , http://www.diodes.com/_files/packages/DO-201.pdf
+Diode DO-201 series Axial Vertical pin pitch 5.08mm  length 9.53mm diameter 5.21mm
+0
+2
+2
+Diode_THT
+D_DO-201_P12.70mm_Horizontal
+Diode, DO-201 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9.53*5.21mm^2, , http://www.diodes.com/_files/packages/DO-201.pdf
+Diode DO-201 series Axial Horizontal pin pitch 12.7mm  length 9.53mm diameter 5.21mm
+0
+2
+2
+Diode_THT
+D_DO-201_P15.24mm_Horizontal
+Diode, DO-201 series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=9.53*5.21mm^2, , http://www.diodes.com/_files/packages/DO-201.pdf
+Diode DO-201 series Axial Horizontal pin pitch 15.24mm  length 9.53mm diameter 5.21mm
+0
+2
+2
+Diode_THT
+D_P600_R-6_P7.62mm_Vertical_AnodeUp
+Diode, P600_R-6 series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=9.1*9.1mm^2, , http://www.vishay.com/docs/88692/p600a.pdf, http://www.diodes.com/_files/packages/R-6.pdf
+Diode P600_R-6 series Axial Vertical pin pitch 7.62mm  length 9.1mm diameter 9.1mm
+0
+2
+2
+Diode_THT
+D_P600_R-6_P7.62mm_Vertical_KathodeUp
+Diode, P600_R-6 series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=9.1*9.1mm^2, , http://www.vishay.com/docs/88692/p600a.pdf, http://www.diodes.com/_files/packages/R-6.pdf
+Diode P600_R-6 series Axial Vertical pin pitch 7.62mm  length 9.1mm diameter 9.1mm
+0
+2
+2
+Diode_THT
+D_P600_R-6_P12.70mm_Horizontal
+Diode, P600_R-6 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9.1*9.1mm^2, , http://www.vishay.com/docs/88692/p600a.pdf, http://www.diodes.com/_files/packages/R-6.pdf
+Diode P600_R-6 series Axial Horizontal pin pitch 12.7mm  length 9.1mm diameter 9.1mm
+0
+2
+2
+Diode_THT
+D_P600_R-6_P20.00mm_Horizontal
+Diode, P600_R-6 series, Axial, Horizontal, pin pitch=20mm, , length*diameter=9.1*9.1mm^2, , http://www.vishay.com/docs/88692/p600a.pdf, http://www.diodes.com/_files/packages/R-6.pdf
+Diode P600_R-6 series Axial Horizontal pin pitch 20mm  length 9.1mm diameter 9.1mm
+0
+2
+2
+Diode_THT
+D_T-1_P2.54mm_Vertical_AnodeUp
+Diode, T-1 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=3.2*2.6mm^2, , http://www.diodes.com/_files/packages/T-1.pdf
+Diode T-1 series Axial Vertical pin pitch 2.54mm  length 3.2mm diameter 2.6mm
+0
+2
+2
+Diode_THT
+D_T-1_P2.54mm_Vertical_KathodeUp
+Diode, T-1 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=3.2*2.6mm^2, , http://www.diodes.com/_files/packages/T-1.pdf
+Diode T-1 series Axial Vertical pin pitch 2.54mm  length 3.2mm diameter 2.6mm
+0
+2
+2
+Diode_THT
+D_T-1_P5.08mm_Horizontal
+Diode, T-1 series, Axial, Horizontal, pin pitch=5.08mm, , length*diameter=3.2*2.6mm^2, , http://www.diodes.com/_files/packages/T-1.pdf
+Diode T-1 series Axial Horizontal pin pitch 5.08mm  length 3.2mm diameter 2.6mm
+0
+2
+2
+Diode_THT
+D_T-1_P10.16mm_Horizontal
+Diode, T-1 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=3.2*2.6mm^2, , http://www.diodes.com/_files/packages/T-1.pdf
+Diode T-1 series Axial Horizontal pin pitch 10.16mm  length 3.2mm diameter 2.6mm
+0
+2
+2
+Diode_THT
+D_T-1_P12.70mm_Horizontal
+Diode, T-1 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=3.2*2.6mm^2, , http://www.diodes.com/_files/packages/T-1.pdf
+Diode T-1 series Axial Horizontal pin pitch 12.7mm  length 3.2mm diameter 2.6mm
+0
+2
+2
+Diode_THT
+Diode_Bridge_15.1x15.1x6.3mm_P10.9mm
+Single phase bridge rectifier case 15.1x15.1mm, pitch 10.9mm, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/pb1000.pdf
+Diode Bridge PB10xxS
+0
+4
+4
+Diode_THT
+Diode_Bridge_15.2x15.2x6.3mm_P10.9mm
+Single phase bridge rectifier case 15.2x15.2mm, pitch 10.9mm, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/kbpc600.pdf
+Diode Bridge KBPC6xx
+0
+4
+4
+Diode_THT
+Diode_Bridge_15.7x15.7x6.3mm_P10.8mm
+Single phase bridge rectifier case 15.7x15.7
+Diode Bridge
+0
+4
+4
+Diode_THT
+Diode_Bridge_16.7x16.7x6.3mm_P10.8mm
+Single phase bridge rectifier case 16.7x16.7
+Diode Bridge
+0
+4
+4
+Diode_THT
+Diode_Bridge_19.0x3.5x10.0mm_P5.0mm
+Vishay GBU rectifier package, 5.08mm pitch, see http://www.vishay.com/docs/88606/g3sba20.pdf
+Vishay GBU rectifier diode bridge
+0
+4
+4
+Diode_THT
+Diode_Bridge_19.0x19.0x6.8mm_P12.7mm
+Single phase bridge rectifier case 19x19mm, pitch 12.7mm, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/pb1000.pdf
+Diode Bridge PB10xx
+0
+4
+4
+Diode_THT
+Diode_Bridge_28.6x28.6x7.3mm_P18.0mm_P11.6mm
+Single phase bridge rectifier case 28.6x28.6mm, pitch 18.0mm & 11.6mm, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/kbpc1500fw.pdf
+Diode Bridge KBPCxxxxWP
+0
+4
+4
+Diode_THT
+Diode_Bridge_32.0x5.6x17.0mm_P10.0mm_P7.5mm
+Diotec 32x5.6x17mm rectifier package, 7.5mm/10mm pitch, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/b40c3700.pdf
+Diotec rectifier diode bridge
+0
+4
+4
+Diode_THT
+Diode_Bridge_DIP-4_W5.08mm_P2.54mm
+4-lead dip package for diode bridges, row spacing 5.08mm, pin-spacing 2.54mm, see http://www.vishay.com/docs/88898/b2m.pdf
+DIL DIP PDIP 5.08mm 2.54
+0
+4
+4
+Diode_THT
+Diode_Bridge_DIP-4_W7.62mm_P5.08mm
+4-lead dip package for diode bridges, row spacing 7.62 mm (300 mils), see http://cdn-reichelt.de/documents/datenblatt/A400/HDBL101G_20SERIES-TSC.pdf
+DIL DIP PDIP 5.08mm 7.62mm 300mil
+0
+4
+4
+Diode_THT
+Diode_Bridge_Round_D8.9mm
+4-lead round diode bridge package, diameter 8.9mm, pin pitch 5.08mm, see http://cdn-reichelt.de/documents/datenblatt/A400/W005M-W10M_SEP.PDF
+diode bridge 8.9mm 8.85mm WOB pitch 5.08mm
+0
+4
+4
+Diode_THT
+Diode_Bridge_Round_D9.0mm
+4-lead round diode bridge package, diameter 9.0mm, pin pitch 5.0mm, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/b40r.pdf
+diode bridge 9.0mm 8.85mm WOB pitch 5.0mm
+0
+4
+4
+Diode_THT
+Diode_Bridge_Round_D9.8mm
+4-lead round diode bridge package, diameter 9.8mm, pin pitch 5.08mm, see http://www.vishay.com/docs/88769/woo5g.pdf
+diode bridge 9.8mm WOG pitch 5.08mm
+0
+4
+4
+Diode_THT
+Diode_Bridge_Vishay_GBL
+Vishay GBL rectifier package, 5.08mm pitch, see http://www.vishay.com/docs/88609/gbl005.pdf
+Vishay GBL rectifier diode bridge
+0
+4
+4
+Diode_THT
+Diode_Bridge_Vishay_GBU
+Vishay GBU rectifier package, 5.08mm pitch, see http://www.vishay.com/docs/88606/g3sba20.pdf
+Vishay GBU rectifier diode bridge
+0
+4
+4
+Diode_THT
+Diode_Bridge_Vishay_KBL
+Vishay KBL rectifier package, 5.08mm pitch, see http://www.vishay.com/docs/88655/kbl005.pdf
+Vishay KBL rectifier diode bridge
+0
+4
+4
+Diode_THT
+Diode_Bridge_Vishay_KBPC1
+Single phase bridge rectifier case KBPC1, see http://www.vishay.com/docs/93585/vs-kbpc1series.pdf
+Diode Bridge
+0
+4
+4
+Diode_THT
+Diode_Bridge_Vishay_KBPC6
+Single phase bridge rectifier case KBPC6, see http://www.vishay.com/docs/93585/vs-kbpc1series.pdf
+Diode Bridge
+0
+4
+4
+Diode_THT
+Diode_Bridge_Vishay_KBU
+Vishay KBU rectifier package, 5.08mm pitch, see http://www.vishay.com/docs/88656/kbu4.pdf
+Vishay KBU rectifier diode bridge
+0
+4
+4
+Display
+AG12864E
+STN/FSTN LCD 128x64 dot https://www.digchip.com/datasheets/parts/datasheet/1121/AG-12864E-pdf.php
+AG12864E Graphics Display 128x64 Ampire
+0
+24
+20
+Display
+Adafruit_SSD1306
+Adafruit SSD1306 OLED 1.3 inch 128x64 I2C & SPI https://learn.adafruit.com/monochrome-oled-breakouts/downloads
+Adafruit SSD1306 OLED 1.3 inch 128x64 I2C & SPI 
+0
+8
+8
+Display
+Adafruit_SSD1306_No_Mounting_Holes
+Adafruit SSD1306 OLED 1.3 inch 128x64 I2C & SPI https://learn.adafruit.com/monochrome-oled-breakouts/downloads
+Adafruit SSD1306 OLED 1.3 inch 128x64 I2C & SPI 
+0
+8
+8
+Display
+CR2013-MI2120
+CR2013-MI2120 ILI9341 LCD Breakout http://pan.baidu.com/s/11Y990
+CR2013-MI2120 ILI9341 LCD Breakout
+0
+18
+14
+Display
+EA-eDIP128B-XXX
+LCD-graphical display with LED backlight 128x64 RS-232 I2C or SPI http://www.lcd-module.com/fileadmin/eng/pdf/grafik/edip128-6e.pdf
+LCD-graphical display with LED backlight 128x64 RS-232 I2C or SPI
+0
+32
+32
+Display
+EA_DOGS104X-A
+LCD 4x10 character 3.3V VDD I2C or SPI http://www.lcd-module.com/fileadmin/eng/pdf/doma/dogs104e.pdf
+LCD 4x10 character 3.3V VDD I2C or SPI
+0
+14
+14
+Display
+EA_DOGXL160-7
+Grapchical,Display,LCD,160x104 http://www.lcd-module.com/eng/pdf/grafik/dogxl160-7e.pdf
+EA_DOGXL160-7
+0
+22
+22
+Display
+EA_DOGXL160-7_Backlight
+Grapchical,Display,LCD,160x104 http://www.lcd-module.com/eng/pdf/grafik/dogxl160-7e.pdf
+EA_DOGXL160-7_Backlight
+0
+22
+22
+Display
+EA_T123X-I2C
+http://www.lcd-module.de/pdf/doma/t123-i2c.pdf
+3 Line 12 character wide alpha numeric LCD
+0
+6
+6
+Display
+EA_eDIP160-XXX
+LCD-graphical display with LED backlight 160x104 RS-232 I2C or SPI http://www.lcd-module.com/fileadmin/eng/pdf/grafik/edip160-7e.pdf
+LCD-graphical display with LED backlight 160x104 RS-232 I2C or SPI
+0
+40
+40
+Display
+EA_eDIP240-XXX
+LCD graphical display LED backlight 240x128 http://www.lcd-module.com/fileadmin/eng/pdf/grafik/edip240-7e.pdf
+LCD graphical display LED backlight 240x128
+0
+40
+40
+Display
+EA_eDIP320X-XXX
+LCD display 320x340 RS-232 I2C or SPI http://www.lcd-module.com/fileadmin/eng/pdf/grafik/edip320-8e.pdf
+LCD display 320x340 RS-232 I2C or SPI
+0
+48
+48
+Display
+EA_eDIPTFT32-XXX
+TFT-graphic display 320x240 16 bit colour with led backlight http://www.lcd-module.com/fileadmin/eng/pdf/grafik/ediptft32-ae.pdf
+TFT-graphic display 320x240 16 bit colour with led backlight
+0
+40
+40
+Display
+EA_eDIPTFT43-ATC
+http://www.lcd-module.com/fileadmin/eng/pdf/grafik/ediptft43-ae.pdf
+TFT graphical display 480x272 16-bit colour with LED backlight
+0
+40
+40
+Display
+EA_eDIPTFT43-XXX
+TFT graphical display 480x272 16-bit colour with LED backlight http://www.lcd-module.com/fileadmin/eng/pdf/grafik/ediptft43-ae.pdf
+TFT graphical display 480x272 16-bit colour with LED backlight
+0
+40
+40
+Display
+EA_eDIPTFT57-XXX
+http://www.lcd-module.com/fileadmin/eng/pdf/grafik/ediptft57-ae.pdf
+TFT-graphic display 640x480 16 bit colour
+0
+48
+48
+Display
+EA_eDIPTFT70-ATC
+TFT-graphical display 800x480 16-bit colours with capacitive touch panel http://www.lcd-module.com/fileadmin/eng/pdf/grafik/ediptft70-ae.pdf
+TFT-graphical display 800x480 16-bit colours with capacitive touch panel
+0
+48
+48
+Display
+EA_eDIPTFT70-XXX
+TFT-graphical display 800x480 16-bit colours http://www.lcd-module.com/fileadmin/eng/pdf/grafik/ediptft70-ae.pdf
+TFT-graphical display 800x480 16-bit colours and touch display
+0
+48
+48
+Display
+HDSM-441B_HDSM-443B
+2 Digit 7 segemnt blue LED, right hand decimal, https://docs.broadcom.com/docs/AV02-1589EN
+2 Digit 7 segment blue LED
+0
+10
+10
+Display
+HDSM-541B_HDSM-543B
+2 digit 7 segement blue LED with right hand decimal, https://docs.broadcom.com/docs/AV02-1588EN
+2 digit 7 segement blue LED with right hand decimal
+0
+10
+10
+Display
+HDSP-48xx
+10-Element Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN
+10-Element Bar Graph Array
+0
+20
+20
+Display
+HDSP-4830
+10-Element Red Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN
+10-Element Red Bar Graph Array
+0
+20
+20
+Display
+HDSP-4832
+10-Element Red Yellow Green Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN
+10-Element Red Yellow Green Bar Graph Array
+0
+20
+20
+Display
+HDSP-4836
+10-Element Red Yellow Green Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN
+10-Element Red Yellow Green Bar Graph Array
+0
+20
+20
+Display
+HDSP-4840
+10-Element Yellow Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN
+10-Element Yellow Bar Graph Array
+0
+20
+20
+Display
+HDSP-4850
+10-Element Green Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN
+10-Element Green Bar Graph Array
+0
+20
+20
+Display
+HLCP-J100
+10-Element Red Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN
+10-Element Red Bar Graph Array
+0
+20
+20
+Display
+HY1602E
+http://www.icbank.com/data/ICBShop/board/HY1602E.pdf
+LCD 16x2 Alphanumeric 16pin
+0
+20
+16
+Display
+LCD-016N002L
+16 x 2 Character LCD, http://www.vishay.com/product?docid=37299
+LCD-016N002L 16 x 2 Character LCD
+0
+24
+20
+Display
+LM16255
+LCD LM16255 16x2 character http://www.datasheetlib.com/datasheet/259542/lm16255_sharp-electronics.html
+LCD 12x2
+0
+14
+14
+Display
+NHD-0420H1Z
+NHD-0420H1Z LCD http://www.newhavendisplay.com/specs/NHD-0420H1Z-FSW-GBW-33V3.pdf
+NHD-0420H1Z LCD
+0
+16
+16
+Display
+RC1602A
+http://www.raystar-optronics.com/down.php?ProID=18
+LCD 16x2 Alphanumeric 16pin
+0
+22
+18
+Display
+WC1602A
+LCD 16x2 http://www.wincomlcd.com/pdf/WC1602A-SFYLYHTC06.pdf
+LCD 16x2 Alphanumeric 16pin
+0
+20
+16
+Display_7Segment
+7SEGMENT-LED__HDSM531_HDSM533_SMD
+7-Segment Display, HDSM53x, https://docs.broadcom.com/docs/AV02-0713EN
+7segment LED HDSM531 HDSM533
+0
+10
+10
+Display_7Segment
+7SegmentLED_LTS6760_LTS6780
+7-Segment Display, LTS67x0, http://optoelectronics.liteon.com/upload/download/DS30-2001-355/S6760jd.pdf
+7Segment LED LTS6760 LTS6780
+0
+10
+10
+Display_7Segment
+AD-121F2
+Single Digit 7-segment RGB LED Display, 1-inch digit height, common anode, http://usasyck.com/products/AD-121F2_cat_e.pdf
+RGB LED digit
+0
+22
+22
+Display_7Segment
+AFF_2x7SEG-DIGIT_10mm
+Afficheur 7 segments 10mm DIGIT
+AFFICHEUR
+0
+16
+16
+Display_7Segment
+CA56-12CGKWA
+4 digit 7 segment green LED, http://www.kingbright.com/attachments/file/psearch/000/00/00/CA56-12CGKWA(Ver.9A).pdf
+4 digit 7 segment green LED
+0
+12
+12
+Display_7Segment
+CA56-12EWA
+4 digit 7 segment green LED, http://www.kingbrightusa.com/images/catalog/SPEC/CA56-12EWA.pdf
+4 digit 7 segment green LED
+0
+12
+12
+Display_7Segment
+CA56-12SEKWA
+4 digit 7 segment green LED, http://www.kingbright.com/attachments/file/psearch/000/00/00/CA56-12SEKWA(Ver.7A).pdf
+4 digit 7 segment green LED
+0
+12
+12
+Display_7Segment
+CA56-12SRWA
+4 digit 7 segment green LED, http://www.kingbrightusa.com/images/catalog/SPEC/CA56-12SRWA.pdf
+4 digit 7 segment green LED
+0
+12
+12
+Display_7Segment
+CA56-12SURKWA
+4 digit 7 segment green LED, http://www.kingbright.com/attachments/file/psearch/000/00/00/CA56-12SURKWA(Ver.8A).pdf
+4 digit 7 segment green LED
+0
+12
+12
+Display_7Segment
+CA56-12SYKWA
+4 digit 7 segment green LED, http://www.kingbright.com/attachments/file/psearch/000/00/00/CA56-12SYKWA(Ver.6A).pdf
+4 digit 7 segment green LED
+0
+12
+12
+Display_7Segment
+CC56-12GWA
+4 digit 7 segment green LED, http://www.kingbrightusa.com/images/catalog/SPEC/CA56-11GWA.pdf
+4 digit 7 segment green LED
+0
+12
+12
+Display_7Segment
+CC56-12YWA
+4 digit 7 segment green LED, http://www.kingbrightusa.com/images/catalog/SPEC/CC56-12YWA.pdf
+4 digit 7 segment green LED
+0
+12
+12
+Display_7Segment
+DA04-11CGKWA
+http://www.kingbright.com/attachments/file/psearch/000/00/00/DA04-11CGKWA(Ver.6A).pdf
+Dubble digit green 7 segment LED display
+0
+16
+16
+Display_7Segment
+DA04-11SEKWA
+http://www.kingbright.com/attachments/file/psearch/000/00/00/DA04-11SEKWA(Ver.9A).pdf
+Dubble digit super bright orange 7 segment LED display
+0
+16
+16
+Display_7Segment
+DA04-11SURKWA
+http://www.kingbright.com/attachments/file/psearch/000/00/00/DA04-11SURKWA(Ver.10A).pdf
+Dubble digit hyper red 7 segment LED display
+0
+16
+16
+Display_7Segment
+DA04-11SYKWA
+http://www.kingbright.com/attachments/file/psearch/000/00/00/DA04-11SYKWA(Ver.6A).pdf
+Dubble digit super bright yellow 7 segment LED display
+0
+16
+16
+Display_7Segment
+DA56-11CGKWA
+http://www.kingbright.com/attachments/file/psearch/000/00/00/DA56-11CGKWA(Ver.16A).pdf
+Double digit seven segment green LED display
+0
+18
+18
+Display_7Segment
+DA56-11SEKWA
+http://www.kingbright.com/attachments/file/psearch/000/00/00/DA56-11SEKWA(Ver.9A).pdf
+Double digit seven segment super bright orange LED display
+0
+18
+18
+Display_7Segment
+DA56-11SURKWA
+http://www.kingbright.com/attachments/file/psearch/000/00/00/DA56-11SURKWA(Ver.11A).pdf
+Double digit seven segment hyper red LED display
+0
+18
+18
+Display_7Segment
+DA56-11SYKWA
+http://www.kingbright.com/attachments/file/psearch/000/00/00/DA56-11SYKWA(Ver.11A).pdf
+Double digit seven segment super bright yellow LED display
+0
+18
+18
+Display_7Segment
+DE113-XX-XX
+http://www.display-elektronik.de/filter/DE113-RS-20_635.pdf
+3 1/5 digit LOW BAT + 7-Segment LCD
+0
+40
+40
+Display_7Segment
+DE114-RS-20
+http://www.display-elektronik.de/filter/DE113-RS-20_635.pdf
+3 1/5 digit reflective LCD LOW-BAT + 7-Segment
+0
+40
+40
+Display_7Segment
+DE122-XX-XX
+http://www.display-elektronik.de/filter/DE122-RS-20_635.pdf
+6 digit 7 segment LCD 
+0
+50
+50
+Display_7Segment
+DE170-XX-XX
+http://www.display-elektronik.de/filter/DE170-RS-20_75.pdf
+3 1/5 digit reflective arrow bat + 7 segment LCD 
+0
+40
+40
+Display_7Segment
+ELD_426XXXX
+http://www.everlight.com/file/ProductFile/D426SYGWA-S530-E2.pdf
+Double digit 7 segment brilliant yellow green LED
+0
+10
+10
+Display_7Segment
+HDSP-7401
+One digit 7 segment yellow, https://docs.broadcom.com/docs/AV02-2553EN
+One digit 7 segment yellow
+0
+10
+10
+Display_7Segment
+HDSP-7507
++-1 overflow 7 segment high efficiency red, https://docs.broadcom.com/docs/AV02-2553EN
++-1 overflow 7 segment high efficiency red
+0
+10
+10
+Display_7Segment
+HDSP-7801
+One digit 7 segment green, https://docs.broadcom.com/docs/AV02-2553EN
+One digit 7 segment green
+0
+10
+10
+Display_7Segment
+HDSP-7807
++-1 overflow 7 segment green, https://docs.broadcom.com/docs/AV02-2553EN
++-1 overflow 7 segment green
+0
+10
+10
+Display_7Segment
+HDSP-A151
+One digit 7 segment red, https://docs.broadcom.com/docs/AV02-2553EN
+One digit 7 segment high efficiency red
+0
+10
+10
+Display_7Segment
+HDSP-A401
+One digit 7 segment orange, common anode, https://docs.broadcom.com/docs/AV02-2553EN
+One digit 7 segment orange common anode
+0
+10
+10
+Display_7Segment
+KCSC02-105
+http://www.kingbright.com/attachments/file/psearch/000/00/00/KCSC02-105(Ver.9A).pdf
+Single digit 7 segement hyper red LED
+0
+10
+10
+Display_7Segment
+KCSC02-106
+http://www.kingbright.com/attachments/file/psearch/000/00/00/KCSC02-106(Ver.10A).pdf
+Single digit 7 segement super bright orange LED
+0
+10
+10
+Display_7Segment
+KCSC02-107
+http://www.kingbright.com/attachments/file/psearch/000/00/00/KCSC02-107(Ver.9A).pdf
+Single digit 7 segement super bright yellow LED
+0
+10
+10
+Display_7Segment
+KCSC02-123
+http://www.kingbright.com/attachments/file/psearch/000/00/00/KCSC02-123(Ver.10A).pdf
+Single digit 7 segement super bright yellow LED
+0
+10
+10
+Display_7Segment
+KCSC02-136
+http://www.kingbright.com/attachments/file/psearch/000/00/00/KCSC02-136(Ver.6B).pdf
+Single digit 7 segement super bright yellow LED
+0
+10
+10
+Display_7Segment
+MAN71A
+https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php
+One digit 7 segment red LED with right dot
+0
+14
+14
+Display_7Segment
+MAN72A
+https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php
+One digit 7 segment red LED with left dot
+0
+14
+14
+Display_7Segment
+MAN73A
+https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php
+Overflow +- 1 red LED
+0
+14
+14
+Display_7Segment
+MAN3410A
+https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php
+One digit 7 segment green LED with dot
+0
+14
+14
+Display_7Segment
+MAN3420A
+https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php
+One digit 7 segment green LED with left dot
+0
+14
+14
+Display_7Segment
+MAN3610A
+https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php
+One digit 7 segment orange LED with right dot
+0
+14
+14
+Display_7Segment
+MAN3620A
+https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php
+One digit 7 segment orange LED with left dot
+0
+14
+14
+Display_7Segment
+MAN3630A
+https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php
+Overflow +- 1 orange LED
+0
+14
+14
+Display_7Segment
+MAN3810A
+https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php
+One digit 7 segment yellow LED with right dot
+0
+14
+14
+Display_7Segment
+MAN3820A
+https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php
+One digit 7 segment yellow LED with left dot
+0
+14
+14
+Display_7Segment
+SA15-11xxx
+http://www.kingbrightusa.com/images/catalog/SPEC/SA15-11SRWA.pdf
+SA15-11xxx single digit 7 segment display 38.1mm 1.5inch
+0
+10
+10
+Display_7Segment
+SBC18-11SURKCGKWA
+http://www.kingbright.com/attachments/file/psearch/000/00/00/SBC18-11SURKCGKWA(Ver.6A).pdf
+single digit 7 segemnt red/green LED
+0
+10
+10
+Display_7Segment
+Sx39-1xxxxx
+Single digit 7 segment LED display in red, yellow or green colour http://www.kingbrightusa.com/images/catalog/SPEC/sa39-11ewa.pdf
+One digit LED 7 segment SA39-11 SC39-11 SA39-12 SC39-12
+0
+10
+10
+ERA-6ARW512V
+RESC2012X60N
+
+
+0
+2
+2
+Ferrite_THT
+LairdTech_28C0236-0JW-10
+Ferrite, vertical, LairdTech 28C0236-0JW-10, https://assets.lairdtech.com/home/brandworld/files/28C0236-0JW-10.pdf, JW Miller core https://www.bourns.com/products/magnetic-products/j.w.-miller-through-hole-ferrite-beads-emi-filters
+Ferrite vertical LairdTech 28C0236-0JW-10
+0
+2
+2
+Fiducial
+Fiducial_0.5mm_Mask1.5mm
+Circular Fiducial, 0.5mm bare copper, 1.5mm soldermask opening
+fiducial
+0
+1
+0
+Fiducial
+Fiducial_0.5mm_Mask1mm
+Circular Fiducial, 0.5mm bare copper, 1mm soldermask opening (Level C)
+fiducial
+0
+1
+0
+Fiducial
+Fiducial_0.75mm_Mask1.5mm
+Circular Fiducial, 0.75mm bare copper, 1.5mm soldermask opening (Level B)
+fiducial
+0
+1
+0
+Fiducial
+Fiducial_0.75mm_Mask2.25mm
+Circular Fiducial, 0.75mm bare copper, 2.25mm soldermask opening
+fiducial
+0
+1
+0
+Fiducial
+Fiducial_1.5mm_Mask3mm
+Circular Fiducial, 1.5mm bare copper, 3mm soldermask opening
+fiducial
+0
+1
+0
+Fiducial
+Fiducial_1.5mm_Mask4.5mm
+Circular Fiducial, 1.5mm bare copper, 4.5mm soldermask opening
+fiducial
+0
+1
+0
+Fiducial
+Fiducial_1mm_Mask2mm
+Circular Fiducial, 1mm bare copper, 2mm soldermask opening (Level A)
+fiducial
+0
+1
+0
+Fiducial
+Fiducial_1mm_Mask3mm
+Circular Fiducial, 1mm bare copper, 3mm soldermask opening (recommended)
+fiducial
+0
+1
+0
+Filter
+Filter_1109-5_1.1x0.9mm
+5-pin SAW filter package - 1.1x0.9 mm Body; (see https://www.murata.com/~/media/webrenewal/support/library/catalog/products/filter/rf/p73e.ashx?la=en-gb)
+Filter 5
+0
+5
+5
+Filter
+Filter_1411-5_1.4x1.1mm
+5-pin filter package - 1.4x1.1 mm Body; (see https://global.kyocera.com/prdct/electro/product/pdf/sf14_tdlte.pdf)
+Filter 5
+0
+5
+5
+Filter
+Filter_Bourns_SRF0905_6.0x9.2mm
+https://www.bourns.com/docs/Product-Datasheets/SRF0905.pdf
+Line Filter
+0
+4
+4
+Filter
+Filter_Mini-Circuits_FV1206
+Mini-Circuits Filter SMD 1206 https://ww2.minicircuits.com/case_style/FV1206.pdf
+Mini-Circuits Filter SMD 1206
+0
+6
+4
+Filter
+Filter_Mini-Circuits_FV1206-1
+Mini-Circuits Filter SMD 1206 https://ww2.minicircuits.com/case_style/FV1206-1.pdf
+Mini-Circuits Filter SMD 1206
+0
+6
+6
+Filter
+Filter_Mini-Circuits_FV1206-4
+Mini-Circuits Filter SMD 1206 https://ww2.minicircuits.com/case_style/FV1206-4.pdf
+Mini-Circuits Filter SMD 1206
+0
+8
+4
+Filter
+Filter_Mini-Circuits_FV1206-5
+Mini-Circuits Filter SMD 1206 https://ww2.minicircuits.com/case_style/FV1206-5.pdf
+Mini-Circuits Filter SMD 1206
+0
+8
+4
+Filter
+Filter_Mini-Circuits_FV1206-6
+Mini-Circuits Filter SMD 1206 https://ww2.minicircuits.com/case_style/FV1206-6.pdf
+Mini-Circuits Filter SMD 1206
+0
+14
+8
+Filter
+Filter_Mini-Circuits_FV1206-7
+Mini-Circuits Filter SMD 1206 https://ww2.minicircuits.com/case_style/FV1206-7.pdf
+Mini-Circuits Filter SMD 1206
+0
+5
+3
+Filter
+Filter_Murata_BNX025
+https://www.murata.com/en-us/products/productdata/8796778004510/QNFH9101.pdf?1496719830000
+EMI Filter
+0
+6
+4
+Filter
+Filter_Murata_BNX025_ThermalVias
+https://www.murata.com/en-us/products/productdata/8796778004510/QNFH9101.pdf?1496719830000
+EMI Filter
+0
+19
+4
+Filter
+Filter_Schaffner_FN405
+Compact PCB mounting EMI filter (https://www.schaffner.com/de/produkte/download/product/datasheet/fn-405-pcb-mounting-filter/)
+EMI filter
+0
+5
+5
+Filter
+Filter_Schaffner_FN406
+Ultra Compact EMC Filter (https://www.schaffner.com/products/download/product/datasheet/fn-406-ultra-compact-emc-filter/)
+emi filter
+0
+5
+5
+Fuse
+Fuse_0201_0603Metric
+Fuse SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator
+resistor
+0
+4
+2
+Fuse
+Fuse_0402_1005Metric
+Fuse SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Fuse
+Fuse_0603_1608Metric
+Fuse SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Fuse
+Fuse_0603_1608Metric_Pad1.05x0.95mm_HandSolder
+Fuse SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Fuse
+Fuse_0805_2012Metric
+Fuse SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Fuse
+Fuse_0805_2012Metric_Pad1.15x1.40mm_HandSolder
+Fuse SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Fuse
+Fuse_01005_0402Metric
+Fuse SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator
+resistor
+0
+4
+2
+Fuse
+Fuse_1206_3216Metric
+Fuse SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Fuse
+Fuse_1206_3216Metric_Pad1.42x1.75mm_HandSolder
+Fuse SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Fuse
+Fuse_1210_3225Metric
+Fuse SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Fuse
+Fuse_1210_3225Metric_Pad1.42x2.65mm_HandSolder
+Fuse SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Fuse
+Fuse_1806_4516Metric
+Fuse SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Fuse
+Fuse_1806_4516Metric_Pad1.57x1.80mm_HandSolder
+Fuse SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Fuse
+Fuse_1812_4532Metric
+Fuse SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Fuse
+Fuse_1812_4532Metric_Pad1.30x3.40mm_HandSolder
+Fuse SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Fuse
+Fuse_2010_5025Metric
+Fuse SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Fuse
+Fuse_2010_5025Metric_Pad1.52x2.65mm_HandSolder
+Fuse SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Fuse
+Fuse_2512_6332Metric
+Fuse SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Fuse
+Fuse_2512_6332Metric_Pad1.52x3.35mm_HandSolder
+Fuse SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Fuse
+Fuse_2816_7142Metric
+Fuse SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Fuse
+Fuse_2816_7142Metric_Pad3.20x4.45mm_HandSolder
+Fuse SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Fuse
+Fuse_2920_7451Metric
+Fuse SMD 2920 (7451 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://www.megastar.com/products/fusetronic/polyswitch/PDF/smd2920.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Fuse
+Fuse_2920_7451Metric_Pad2.10x5.45mm_HandSolder
+Fuse SMD 2920 (7451 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: http://www.megastar.com/products/fusetronic/polyswitch/PDF/smd2920.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Fuse
+Fuse_BelFuse_0ZRE0005FF_L8.3mm_W3.8mm
+Fuse 0ZRE0005FF, BelFuse, Radial Leaded PTC, https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf
+0ZRE BelFuse radial PTC
+0
+2
+2
+Fuse
+Fuse_BelFuse_0ZRE0008FF_L8.3mm_W3.8mm
+Fuse 0ZRE0008FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf
+0ZRE BelFuse radial PTC
+0
+2
+2
+Fuse
+Fuse_BelFuse_0ZRE0012FF_L8.3mm_W3.8mm
+Fuse 0ZRE0012FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf
+0ZRE BelFuse radial PTC
+0
+2
+2
+Fuse
+Fuse_BelFuse_0ZRE0016FF_L9.9mm_W3.8mm
+Fuse 0ZRE0016FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf
+0ZRE BelFuse radial PTC
+0
+2
+2
+Fuse
+Fuse_BelFuse_0ZRE0025FF_L9.6mm_W3.8mm
+Fuse 0ZRE0025FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf
+0ZRE BelFuse radial PTC
+0
+2
+2
+Fuse
+Fuse_BelFuse_0ZRE0033FF_L11.4mm_W3.8mm
+Fuse 0ZRE0033FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf
+0ZRE BelFuse radial PTC
+0
+2
+2
+Fuse
+Fuse_BelFuse_0ZRE0040FF_L11.5mm_W3.8mm
+Fuse 0ZRE0040FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf
+0ZRE BelFuse radial PTC
+0
+2
+2
+Fuse
+Fuse_BelFuse_0ZRE0055FF_L14.0mm_W4.1mm
+Fuse 0ZRE0055FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf
+0ZRE BelFuse radial PTC
+0
+2
+2
+Fuse
+Fuse_BelFuse_0ZRE0075FF_L11.5mm_W4.8mm
+Fuse 0ZRE0075FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf
+0ZRE BelFuse radial PTC
+0
+2
+2
+Fuse
+Fuse_BelFuse_0ZRE0100FF_L18.7mm_W5.1mm
+Fuse 0ZRE0100FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf
+0ZRE BelFuse radial PTC
+0
+2
+2
+Fuse
+Fuse_BelFuse_0ZRE0125FF_L21.2mm_W5.3mm
+Fuse 0ZRE0125FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf
+0ZRE BelFuse radial PTC
+0
+2
+2
+Fuse
+Fuse_BelFuse_0ZRE0150FF_L23.4mm_W5.3mm
+Fuse 0ZRE0150FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf
+0ZRE BelFuse radial PTC
+0
+2
+2
+Fuse
+Fuse_BelFuse_0ZRE0200FF_L24.9mm_W6.1mm
+Fuse 0ZRE0200FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf
+0ZRE BelFuse radial PTC
+0
+2
+2
+Fuse
+Fuse_Blade_ATO_directSolder
+car blade fuse direct solder
+car blade fuse
+0
+2
+2
+Fuse
+Fuse_Blade_Mini_directSolder
+car blade fuse mini, direct solder
+car blade fuse mini
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RG300
+PTC Resettable Fuse, Ihold = 3.0A, Itrip=5.1A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RG400
+PTC Resettable Fuse, Ihold = 4.0A, Itrip=6.8A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RG500
+PTC Resettable Fuse, Ihold = 5.0A, Itrip=8.5A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RG600
+PTC Resettable Fuse, Ihold = 6.0A, Itrip=10.2A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RG650
+PTC Resettable Fuse, Ihold = 6.5A, Itrip=11.1A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RG700
+PTC Resettable Fuse, Ihold = 7.0A, Itrip=11.9A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RG800
+PTC Resettable Fuse, Ihold = 8.0A, Itrip=13.6A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RG900
+PTC Resettable Fuse, Ihold = 9.0A, Itrip=15.3A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RG1000
+PTC Resettable Fuse, Ihold = 10.0A, Itrip=17.0A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RG1100
+PTC Resettable Fuse, Ihold = 11.0A, Itrip=18.7A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RHT050
+PTC Resettable Fuse, Ihold = 0.5A, Itrip=0.92A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RHT070
+PTC Resettable Fuse, Ihold = 0.7A, Itrip=1.4A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RHT100
+PTC Resettable Fuse, Ihold = 1.0A, Itrip=1.8A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RHT200
+PTC Resettable Fuse, Ihold = 2.0A, Itrip=3.8A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RHT300
+PTC Resettable Fuse, Ihold = 3.0A, Itrip=6.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RHT400
+PTC Resettable Fuse, Ihold = 4.0A, Itrip=7.5A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RHT500
+PTC Resettable Fuse, Ihold = 5.0A, Itrip=9.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RHT550
+PTC Resettable Fuse, Ihold = 5.5A, Itrip=10.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RHT600
+PTC Resettable Fuse, Ihold = 6.0A, Itrip=10.8A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RHT650
+PTC Resettable Fuse, Ihold = 6.5A, Itrip=12.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RHT700
+PTC Resettable Fuse, Ihold = 7.0A, Itrip=13.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RHT750
+PTC Resettable Fuse, Ihold = 7.5A, Itrip=13.1A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RHT800
+PTC Resettable Fuse, Ihold = 8.0A, Itrip=15.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RHT900
+PTC Resettable Fuse, Ihold = 9.0A, Itrip=16.5A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RHT1000
+PTC Resettable Fuse, Ihold = 10.0A, Itrip=18.5A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RHT1100
+PTC Resettable Fuse, Ihold = 11.0A, Itrip=20.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-RHT1300
+PTC Resettable Fuse, Ihold = 13.0A, Itrip=24.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf
+ptc resettable fuse polyfuse THT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-SM_7.98x5.44mm
+https://www.bourns.com/docs/Product-Datasheets/mfsm.pdf
+bourns ptc resettable fuse polyfuse MF-SM MF-SMHT
+0
+2
+2
+Fuse
+Fuse_Bourns_MF-SM_9.5x6.71mm
+https://www.bourns.com/docs/Product-Datasheets/mfsm.pdf
+bourns ptc resettable fuse polyfuse MF-SM MF-SMHT
+0
+2
+2
+Fuse
+Fuse_Littelfuse-LVR100
+Littelfuse, resettable fuse, PTC, polyswitch LVR100, Ih 1A http://www.littelfuse.com/~/media/electronics/datasheets/resettable_ptcs/littelfuse_ptc_lvr_catalog_datasheet.pdf.pdf
+LVR100 PTC resettable polyswitch 
+0
+2
+2
+Fuse
+Fuse_Littelfuse-LVR125
+Littelfuse, resettable fuse, PTC, polyswitch LVR125, Ih 1.25A, http://www.littelfuse.com/~/media/electronics/datasheets/resettable_ptcs/littelfuse_ptc_lvr_catalog_datasheet.pdf.pdf
+LVR125 PTC resettable polyswitch 
+0
+2
+2
+Fuse
+Fuse_Littelfuse-LVR200
+Littelfuse, resettable fuse, PTC, polyswitch LVR200, Ih 2A, http://www.littelfuse.com/~/media/electronics/datasheets/resettable_ptcs/littelfuse_ptc_lvr_catalog_datasheet.pdf.pdf
+LVR200 PTC resettable polyswitch 
+0
+2
+2
+Fuse
+Fuse_Littelfuse-NANO2-451_453
+Littelfuse NANO2 https://www.littelfuse.com/~/media/electronics/datasheets/fuses/littelfuse_fuse_451_453_datasheet.pdf.pdf
+Fuse Nano2
+0
+2
+2
+Fuse
+Fuse_Littelfuse_372_D8.50mm
+Fuse, Littelfuse, 372, 8.5x8mm, https://www.littelfuse.com/~/media/electronics/datasheets/fuses/littelfuse_fuse_372_datasheet.pdf.pdf
+fuse tht radial
+0
+2
+2
+Fuse
+Fuse_Littelfuse_395Series
+Fuse, TE5, Littelfuse/Wickmann, No. 460, No560,
+Fuse TE5 Littelfuse/Wickmann No. 460 No560 
+0
+2
+2
+Fuse
+Fuse_Schurter_UMT250
+Surface Mount Fuse, 3 x 10.1 mm, Time-Lag T, 250 VAC, 125 VDC (https://us.schurter.com/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_UMT_250.pdf)
+Schurter fuse smd
+0
+2
+2
+Fuse
+Fuse_SunFuse-6HP
+SunFuse Ceramic Slow Blow Fuse 6H_6HP.PDF
+UL/CSA 6x32mm Ceramic Slow Blow Fuse
+0
+2
+2
+Fuse
+Fuseholder_Blade_ATO_Littelfuse_Pudenz_2_Pin
+Fuseholder ATO Blade littelfuse Pudenz 2 Pin
+Fuseholder ATO Blade littelfuse Pudenz 2 Pin
+0
+2
+2
+Fuse
+Fuseholder_Blade_Mini_Keystone_3568
+fuse holder, car blade fuse mini, http://www.keyelco.com/product-pdf.cfm?p=306
+car blade fuse mini
+0
+4
+2
+Fuse
+Fuseholder_Cylinder-5x20mm_Bulgin_FX0456_Vertical_Closed
+Fuseholder, 5x20, closed, vertical, Bulgin, FX0456, https://www.bulgin.com/products/pub/media/bulgin/data/Fuseholders.pdf
+Fuseholder 5x20 closed vertical Bulgin FX0456 Sicherungshalter 
+0
+2
+2
+Fuse
+Fuseholder_Cylinder-5x20mm_Bulgin_FX0457_Horizontal_Closed
+Fuseholder, 5x20, closed, horizontal, Bulgin, FX0457, Sicherungshalter,
+Fuseholder 5x20 closed horizontal Bulgin FX0457 Sicherungshalter 
+0
+2
+2
+Fuse
+Fuseholder_Cylinder-5x20mm_EATON_H15-V-1_Vertical_Closed
+PCB fuse holders for 5 mm x 20 mm fuses; 250V; 10A (http://www.cooperindustries.com/content/dam/public/bussmann/Electronics/Resources/product-datasheets/bus-elx-ds-4426-h15.pdf)
+fuse holder vertical 5x20mm
+0
+2
+2
+Fuse
+Fuseholder_Cylinder-5x20mm_EATON_HBV_Vertical_Closed
+5 mm x 20 mm fuse holders; Vertical w/ Stability Pins; 250V; 6.3-16A (http://www.cooperindustries.com/content/dam/public/bussmann/Electronics/Resources/product-datasheets/Bus_Elx_DS_2118_HB_PCB_Series.pdf)
+fuse holder vertical 5x20mm
+0
+2
+2
+Fuse
+Fuseholder_Cylinder-5x20mm_EATON_HBW_Vertical_Closed
+5 mm x 20 mm fuse holders; Vertical w/o Stability Pins; 250V; 6.3-16A (http://www.cooperindustries.com/content/dam/public/bussmann/Electronics/Resources/product-datasheets/Bus_Elx_DS_2118_HB_PCB_Series.pdf)
+fuse holder vertical 5x20mm
+0
+2
+2
+Fuse
+Fuseholder_Cylinder-5x20mm_Schurter_0031_8201_Horizontal_Open
+Fuseholder horizontal open, 5x20mm, 500V, 16A, Schurter 0031.8201, https://us.schurter.com/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_OGN.pdf
+Fuseholder horizontal open 5x20 Schurter 0031.8201
+0
+2
+2
+Fuse
+Fuseholder_Cylinder-5x20mm_Schurter_FAB_0031-355x_Horizontal_Closed
+Fuseholder 5x20mm horizontal Shurter model FAB, Suitable for order numbers 0031.3551 and 0031.3558  (https://www.schurter.com/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_FAB.pdf)
+Fuseholder 5x20mm closed horizontal
+0
+2
+2
+Fuse
+Fuseholder_Cylinder-5x20mm_Schurter_FPG4_Vertical_Closed
+Shock-Safe Fuseholder, 5 x 20 mm, Slotted Cap/Fingergrip, vertical, IEC 60335-1; 250VAC/10A VDE; 500V/16A UL/CSA (https://us.schurter.com/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_FPG4.pdf)
+fuse holder vertical 5x20mm
+0
+4
+2
+Fuse
+Fuseholder_Cylinder-5x20mm_Schurter_FUP_0031.2510_Horizontal_Closed
+Shock-Safe closed Fuseholder, Schurter FUP Series, 5.0 x 20mm, Slotted Cap, horizontal, 500 VAC 4W/16A (VDE), 600V 30A (UL/CSA), order numbers: 0031.2510 (0031.2500 + 0031.2323), http://www.schurter.ch/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_FUP.pdf
+Fuseholder 5x20mm horizontal closed
+0
+3
+2
+Fuse
+Fuseholder_Cylinder-5x20mm_Stelvio-Kontek_PTF78_Horizontal_Open
+https://www.tme.eu/en/Document/3b48dbe2b9714a62652c97b08fcd464b/PTF78.pdf
+Fuseholder horizontal open 5x20 Stelvio-Kontek PTF/78
+0
+2
+2
+Fuse
+Fuseholder_Cylinder-6.3x32mm_Schurter_0031-8002_Horizontal_Open
+Fuseholder, horizontal, open, 6.3x32, Schurter, 0031.8002, https://www.schurter.com/en/datasheet/typ_OG__Holder__6.3x32.pdf
+Fuseholder horizontal open 6.3x32 Schurter 0031.8002
+0
+2
+2
+Fuse
+Fuseholder_Cylinder-6.3x32mm_Schurter_FUP_0031.2520_Horizontal_Closed
+Shock-Safe closed Fuseholder, Schurter FUP Series, 6.3 x 32 mm, Slotted Cap, horizontal, 500 VAC 4W/16A (VDE), 600V 30A (UL/CSA), order numbers: 0031.2520 (0031.2500 + 0031.2321), http://www.schurter.ch/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_FUP.pdf
+Fuseholder 6.3x32mm horizontal closed
+0
+3
+2
+Fuse
+Fuseholder_TR5_Littelfuse_No560_No460
+Fuse, Fuseholder, TR5, Littelfuse/Wickmann, No. 460, No560, https://www.littelfuse.com/~/media/electronics/datasheets/fuse_holders/littelfuse_fuse_holder_559_560_datasheet.pdf.pdf
+Fuse Fuseholder TR5 Littelfuse/Wickmann No. 460 No560 
+0
+2
+2
+Heatsink
+Heatsink_35x26mm_1xFixation3mm_Fischer-SK486-35
+Heatsink, 35mm x 26mm, 1x Fixation 3mm, Fischer SK486-35
+heatsink
+0
+1
+1
+Heatsink
+Heatsink_38x38mm_SpringFixation
+Heatsink, 38x38mm, Spring Fixation, diagonal,
+heatsink
+0
+4
+1
+Heatsink
+Heatsink_62x40mm_2xFixation3mm
+Heatsink, 62 x 40mm, 2x 3mm Drills,
+heatsink
+0
+2
+1
+Heatsink
+Heatsink_125x35x50mm_3xFixationM3
+Heatsink, 125x35x50mm, 3 fixation holes 3.2mm
+heatsink
+0
+0
+0
+Heatsink
+Heatsink_AAVID_573300D00010G_TO-263
+Heatsink, 12.70mm x 26.16mm x 10.16, SMD, 18K/W, TO-263, D2 Pak, https://www.shopaavid.com/Product/573300D00000G
+Heatsink AAVID TO-263 D2 Pak
+0
+2
+1
+Heatsink
+Heatsink_Aavid-TV5G_TO220_Horizontal
+Heatsink TV5G TO-220 Horizontal, https://www.shopaavid.com/Product/TV-5G
+Heatsink TV5G TO-220 Horizontal 
+0
+0
+0
+Heatsink
+Heatsink_Fischer_FK24413D2PAK_26x13mm
+26x13 mm SMD heatsink for TO-252 TO-263 TO-268, https://www.fischerelektronik.de/pim/upload/fischerData/cadpdf/base/fk_244_13_d2_pak.pdf
+heatsink TO-252 TO-263 TO-268
+0
+2
+1
+Heatsink
+Heatsink_Fischer_SK104-STC-STIC_35x13mm_2xDrill2.5mm
+Heatsink, 35mm x 13mm, 2x Fixation 2,5mm Drill, Soldering, Fischer SK104-STC-STIC,
+Heatsink fischer TO-220
+0
+2
+1
+Heatsink
+Heatsink_Fischer_SK104-STCB_35x13mm__2xDrill3.5mm_ScrewM3
+Heatsink, 35mm x 13mm, 2x Fixation 2,5mm Drill, Soldering, Fischer SK104-STC-STIC,
+Heatsink fischer TO-220
+0
+2
+1
+Heatsink
+Heatsink_Fischer_SK129-STS_42x25mm_2xDrill2.5mm
+Heatsink, Fischer SK129
+heatsink fischer
+0
+2
+1
+Heatsink
+Heatsink_SheetType_50x7mm_2Fixations
+Heatsink, Sheet type, 50x7mm, 2 fixations (solder),
+Heatsink sheet
+0
+2
+1
+Heatsink
+Heatsink_Stonecold_HS-132_32x14mm_2xFixation1.5mm
+Heatsink, StoneCold HS
+heatsink
+0
+2
+1
+Inductor_SMD
+L_6.3x6.3_H3
+Choke, SMD, 6.3x6.3mm 3mm height
+Choke SMD
+0
+2
+2
+Inductor_SMD
+L_7.3x7.3_H3.5
+Choke, SMD, 7.3x7.3mm 3.5mm height
+Choke SMD
+0
+2
+2
+Inductor_SMD
+L_7.3x7.3_H4.5
+Choke, SMD, 7.3x7.3mm 4.5mm height
+Choke SMD
+0
+2
+2
+Inductor_SMD
+L_10.4x10.4_H4.8
+Choke, SMD, 10.4x10.4mm 4.8mm height
+Choke SMD
+0
+2
+2
+Inductor_SMD
+L_12x12mm_H4.5mm
+Choke, SMD, 12x12mm 4.5mm height
+Choke SMD
+0
+2
+2
+Inductor_SMD
+L_12x12mm_H6mm
+Choke, SMD, 12x12mm 6mm height
+Choke SMD
+0
+2
+2
+Inductor_SMD
+L_12x12mm_H8mm
+Choke, SMD, 12x12mm 8mm height
+Choke SMD
+0
+2
+2
+Inductor_SMD
+L_0201_0603Metric
+Inductor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator
+inductor
+0
+4
+2
+Inductor_SMD
+L_0402_1005Metric
+Inductor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+inductor
+0
+2
+2
+Inductor_SMD
+L_0603_1608Metric
+Inductor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+inductor
+0
+2
+2
+Inductor_SMD
+L_0603_1608Metric_Pad1.05x0.95mm_HandSolder
+Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+inductor handsolder
+0
+2
+2
+Inductor_SMD
+L_0805_2012Metric
+Inductor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator
+inductor
+0
+2
+2
+Inductor_SMD
+L_0805_2012Metric_Pad1.15x1.40mm_HandSolder
+Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator
+inductor handsolder
+0
+2
+2
+Inductor_SMD
+L_01005_0402Metric
+Inductor SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator
+inductor
+0
+4
+2
+Inductor_SMD
+L_1008_2520Metric
+Inductor SMD 1008 (2520 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://ecsxtal.com/store/pdf/ECS-MPI2520-SMD-POWER-INDUCTOR.pdf), generated with kicad-footprint-generator
+inductor
+0
+2
+2
+Inductor_SMD
+L_1206_3216Metric
+Inductor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+inductor
+0
+2
+2
+Inductor_SMD
+L_1206_3216Metric_Pad1.42x1.75mm_HandSolder
+Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+inductor handsolder
+0
+2
+2
+Inductor_SMD
+L_1210_3225Metric
+Inductor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+inductor
+0
+2
+2
+Inductor_SMD
+L_1210_3225Metric_Pad1.42x2.65mm_HandSolder
+Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+inductor handsolder
+0
+2
+2
+Inductor_SMD
+L_1806_4516Metric
+Inductor SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator
+inductor
+0
+2
+2
+Inductor_SMD
+L_1806_4516Metric_Pad1.57x1.80mm_HandSolder
+Capacitor SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator
+inductor handsolder
+0
+2
+2
+Inductor_SMD
+L_1812_4532Metric
+Inductor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator
+inductor
+0
+2
+2
+Inductor_SMD
+L_1812_4532Metric_Pad1.30x3.40mm_HandSolder
+Capacitor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator
+inductor handsolder
+0
+2
+2
+Inductor_SMD
+L_2010_5025Metric
+Inductor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+inductor
+0
+2
+2
+Inductor_SMD
+L_2010_5025Metric_Pad1.52x2.65mm_HandSolder
+Capacitor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+inductor handsolder
+0
+2
+2
+Inductor_SMD
+L_2512_6332Metric
+Inductor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+inductor
+0
+2
+2
+Inductor_SMD
+L_2512_6332Metric_Pad1.52x3.35mm_HandSolder
+Capacitor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+inductor handsolder
+0
+2
+2
+Inductor_SMD
+L_2816_7142Metric
+Inductor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator
+inductor
+0
+2
+2
+Inductor_SMD
+L_2816_7142Metric_Pad3.20x4.45mm_HandSolder
+Capacitor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator
+inductor handsolder
+0
+2
+2
+Inductor_SMD
+L_Abracon_ASPI-0630LR
+smd shielded power inductor https://abracon.com/Magnetics/power/ASPI-0630LR.pdf
+inductor abracon smd shielded
+0
+2
+2
+Inductor_SMD
+L_Abracon_ASPI-3012S
+smd shielded power inductor http://www.abracon.com/Magnetics/power/ASPI-3012S.pdf
+inductor abracon smd shielded
+0
+2
+2
+Inductor_SMD
+L_Bourns-SRN1060
+Bourns SRN1060 series SMD inductor https://www.bourns.com/docs/Product-Datasheets/SRN1060.pdf
+Bourns SRN1060 SMD inductor
+0
+2
+2
+Inductor_SMD
+L_Bourns-SRN4018
+Bourns SRN4018 series SMD inductor, https://www.bourns.com/docs/Product-Datasheets/SRN4018.pdf
+Bourns SRN4018 SMD inductor
+0
+2
+2
+Inductor_SMD
+L_Bourns-SRN6028
+Bourns SRN6028 series SMD inductor
+Bourns SRN6028 SMD inductor
+0
+2
+2
+Inductor_SMD
+L_Bourns-SRN8040_8x8.15mm
+Bourns SRN8040 series SMD inductor 8x8.15mm, https://www.bourns.com/docs/Product-Datasheets/SRN8040.pdf
+Bourns SRN8040 SMD inductor
+0
+2
+2
+Inductor_SMD
+L_Bourns-SRR1005
+Bourns SRR1005 series SMD inductor
+Bourns SRR1005 SMD inductor
+0
+2
+2
+Inductor_SMD
+L_Bourns-SRU1028_10.0x10.0mm
+Bourns SRU1028 series SMD inductor, https://www.bourns.com/docs/Product-Datasheets/SRU1028.pdf
+Bourns SRU1028 SMD inductor
+0
+2
+2
+Inductor_SMD
+L_Bourns-SRU8043
+Bourns SRU8043 series SMD inductor
+Bourns SRU8043 SMD inductor
+0
+2
+2
+Inductor_SMD
+L_Bourns_SDR1806
+https://www.bourns.com/docs/Product-Datasheets/SDR1806.pdf
+Bourns SDR1806
+0
+2
+2
+Inductor_SMD
+L_Bourns_SRN6045TA
+http://www.bourns.com/docs/product-datasheets/srn6045ta.pdf
+Semi-shielded Power Inductor
+0
+2
+2
+Inductor_SMD
+L_Bourns_SRN8040TA
+https://www.bourns.com/docs/product-datasheets/srn8040ta.pdf
+Inductor
+0
+2
+2
+Inductor_SMD
+L_Bourns_SRP1245A
+Bourns SRP1245A series SMD inductor http://www.bourns.com/docs/Product-Datasheets/SRP1245A.pdf
+Bourns SRP1245A SMD inductor
+0
+2
+2
+Inductor_SMD
+L_Bourns_SRP2313AA
+Bourns SRR1260 series SMD inductor http://www.bourns.com/docs/product-datasheets/srp2313aa.pdf
+Bourns SRR1260 SMD inductor
+0
+4
+2
+Inductor_SMD
+L_Bourns_SRP7028A_7.3x6.6mm
+Shielded Power Inductors (https://www.bourns.com/docs/product-datasheets/srp7028a.pdf)
+Shielded Inductors Bourns SMD SRP7028A
+0
+2
+2
+Inductor_SMD
+L_Bourns_SRR1210A
+Bourns SRR1210A series SMD inductor https://www.bourns.com/docs/Product-Datasheets/SRR1210A.pdf
+Bourns SRR1210A SMD inductor
+0
+2
+2
+Inductor_SMD
+L_Bourns_SRR1260
+Bourns SRR1260 series SMD inductor http://www.bourns.com/docs/Product-Datasheets/SRR1260.pdf
+Bourns SRR1260 SMD inductor
+0
+2
+2
+Inductor_SMD
+L_Coilcraft_LPS4018
+SMD Inductor Coilcraft LPS4018 https://www.coilcraft.com/pdfs/lps4018.pdf
+L Coilcraft LPS4018
+0
+2
+2
+Inductor_SMD
+L_Coilcraft_LPS5030
+Shielded Power Inductor SMD, Coilcraft LPS5030, https://www.coilcraft.com/pdfs/lps5030.pdf, StepUp generated footprint
+inductor
+0
+2
+2
+Inductor_SMD
+L_Coilcraft_XAL60xx_6.36x6.56mm
+Coilcraft XAL60xx series, https://www.coilcraft.com/pdfs/xal60xx.pdf
+L Coilcraft XAL60xx
+0
+2
+2
+Inductor_SMD
+L_Coilcraft_XAL5030
+L_Coilcraft_XAL5030
+L Coilcraft XAL5030
+0
+2
+2
+Inductor_SMD
+L_Coilcraft_XxL4020
+L_Coilcraft_XxL4020 https://www.coilcraft.com/pdfs/xfl4020.pdf
+L Coilcraft XxL4020
+0
+2
+2
+Inductor_SMD
+L_Coilcraft_XxL4030
+L_Coilcraft_XxL4030 https://www.coilcraft.com/pdfs/xfl4030.pdf
+L Coilcraft XxL4030
+0
+2
+2
+Inductor_SMD
+L_Coilcraft_XxL4040
+L_Coilcraft_XxL4040 https://www.coilcraft.com/pdfs/xal4000.pdf
+L Coilcraft XxL4040
+0
+2
+2
+Inductor_SMD
+L_CommonMode_Delevan_4222
+API Delevan, Surface Mount Common Mode Bead, 4222 4222R, http://www.delevan.com/seriesPDFs/4222.pdf
+surface mount common mode bead
+0
+4
+4
+Inductor_SMD
+L_CommonMode_Wuerth_WE-SL2
+http://katalog.we-online.de/en/pbs/WE-SL2?sid=5fbec16187#vs_t1:c1_ct:1
+Wuerth WE-SL2
+0
+4
+4
+Inductor_SMD
+L_Fastron_PISN
+Choke, Drossel, PISN, SMD, Fastron,
+Choke Drossel PISN SMD Fastron 
+0
+2
+2
+Inductor_SMD
+L_Fastron_PISN_Handsoldering
+Choke, Drossel, PISN, SMD, Fastron,
+Choke Drossel PISN SMD Fastron 
+0
+2
+2
+Inductor_SMD
+L_Fastron_PISR
+Choke, Drossel, PISR, Fastron, SMD,
+Choke Drossel PISR Fastron SMD 
+0
+2
+2
+Inductor_SMD
+L_Fastron_PISR_Handsoldering
+Choke, Drossel, PISR, Fastron, SMD,
+Choke Drossel PISR Fastron SMD 
+0
+2
+2
+Inductor_SMD
+L_Murata_DEM35xxC
+https://www.murata.com/~/media/webrenewal/products/inductor/chip/tokoproducts/wirewoundferritetypeforpl/m_dem3518c.ashx
+Inductor SMD DEM35xxC
+0
+2
+2
+Inductor_SMD
+L_Murata_LQH2MCNxxxx02_2.0x1.6mm
+Inductor, Murata, LQH2MCN_02 series, 1.6x2.0x0.9mm (https://search.murata.co.jp/Ceramy/image/img/P02/JELF243A-0053.pdf)
+chip coil inductor Murata LQH2MC
+0
+2
+2
+Inductor_SMD
+L_Murata_LQH55DN_5.7x5.0mm
+Inductor, SMD, 5.7x5.0x4.7mm, https://search.murata.co.jp/Ceramy/image/img/P02/JELF243A-0045.pdf
+inductor smd
+0
+2
+2
+Inductor_SMD
+L_Neosid_Air-Coil_SML_1turn_HDM0131A
+Neosid, Air-Coil, SML, 1turn, HDM0131A,
+Neosid Air-Coil SML 1turn HDM0131A
+0
+2
+2
+Inductor_SMD
+L_Neosid_Air-Coil_SML_2turn_HAM0231A
+Neosid, Air-Coil, SML, 2turn, HAM0231A,
+Neosid Air-Coil SML 2turn HAM0231A
+0
+2
+2
+Inductor_SMD
+L_Neosid_Air-Coil_SML_2turn_HDM0231A
+Neosid, Air-Coil, SML, 2turn, HDM0231A,
+Neosid Air-Coil SML 2turn HDM0231A
+0
+2
+2
+Inductor_SMD
+L_Neosid_Air-Coil_SML_3turn_HAM0331A
+Neosid, Air-Coil, SML, 2turn, HAM0331A,
+Neosid Air-Coil SML 3turn HAM0331A
+0
+2
+2
+Inductor_SMD
+L_Neosid_Air-Coil_SML_3turn_HDM0331A
+Neosid, Air-Coil, SML, 3turn, HDM0331A,
+Neosid Air-Coil SML 3turn HDM0331A
+0
+2
+2
+Inductor_SMD
+L_Neosid_Air-Coil_SML_4turn_HAM0431A
+Neosid, Air-Coil, SML, 4turn, HAM0431A,
+Neosid Air-Coil SML 4turn HAM0431A
+0
+2
+2
+Inductor_SMD
+L_Neosid_Air-Coil_SML_4turn_HDM0431A
+Neosid, Air-Coil, SML, 4turn, HDM0431A,
+Neosid Air-Coil SML 4turn HDM0431A
+0
+2
+2
+Inductor_SMD
+L_Neosid_Air-Coil_SML_5turn_HAM0531A
+Neosid, Air-Coil, SML, 5turn, HAM0531A,
+Neosid Air-Coil SML 5turn HAM0531A
+0
+2
+2
+Inductor_SMD
+L_Neosid_Air-Coil_SML_5turn_HDM0531A
+Neosid, Air-Coil, SML, 5turn, HDM0531A,
+Neosid Air-Coil SML 5turn HDM0531A
+0
+2
+2
+Inductor_SMD
+L_Neosid_Air-Coil_SML_6-10turn_HAM0631A-HAM1031A
+Neosid, Air-Coil, SML, 6-10turn, HAM0631A-HAM1031A,
+Neosid Air-Coil SML 6-10turn HAM0631A-HAM1031A
+0
+2
+2
+Inductor_SMD
+L_Neosid_Air-Coil_SML_6-10turn_HDM0431A-HDM1031A
+Neosid, Air-Coil, SML, 6-10turn, HDM0431A-HDM1031A,
+Neosid Air-Coil SML 6-10turn HDM0431A-HDM1031A
+0
+2
+2
+Inductor_SMD
+L_Neosid_Air-Coil_SML_6turn_HAM0631A
+Neosid, Air-Coil, SML, 6turn, HAM0631A,
+Neosid Air-Coil SML 6turn HAM0631A
+0
+2
+2
+Inductor_SMD
+L_Neosid_MicroCoil_Ms36-L
+Neosid, Micro Coil, Inductor, Ms36-L, SMD, Fixed inductor, anti clockwise, https://neosid.de/en/products/inductors/rod-core-chokes/smd-rod-core-chokes/52026/ms-36/7-h?c=94
+Neosid Micro Coil Inductor Ms36-L SMD Fixed inductor anti clockwise
+0
+2
+2
+Inductor_SMD
+L_Neosid_Ms42
+Neosid, Inductor, SMs42, Fixed inductor, SMD, magneticaly shielded, https://neosid.de/import-data/product-pdf/neoFestind_Ms42.pdf
+Neosid Inductor SMs42 Fixed inductor SMD magneticaly shielded
+0
+2
+2
+Inductor_SMD
+L_Neosid_Ms50
+Neosid, Power Inductor, Ms50, SMD, Fixed inductor, https://neosid.de/import-data/product-pdf/neoFestind_Ms50.pdf
+Neosid Power Inductor Ms50 SMD Fixed inductor
+0
+2
+2
+Inductor_SMD
+L_Neosid_Ms50T
+Neosid, Power Inductor, Ms50T, SMD, Fixed inductor,  high temperature, https://neosid.de/import-data/product-pdf/neoFestind_Ms50T.pdf
+Neosid Power Inductor Ms50T SMD Fixed inductor high temperature
+0
+2
+2
+Inductor_SMD
+L_Neosid_Ms85
+Neosid, Ms85, Ms85T, SMD Inductor, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_Ms85.pdf
+Neosid Ms85 Ms85T SMD Inductor Fixed inductor SMD
+0
+2
+2
+Inductor_SMD
+L_Neosid_Ms85T
+Neosid, Ms85, Ms85T, SMD Inductor, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_Ms85T.pdf
+Neosid Ms85 Ms85T SMD Inductor Fixed inductor SMD
+0
+2
+2
+Inductor_SMD
+L_Neosid_Ms95
+Neosid,Inductor,Ms95, Ms95a, Ms95T, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_Ms95.pdf
+NeosidInductorMs95 Ms95a Ms95T Fixed inductor SMD
+0
+2
+2
+Inductor_SMD
+L_Neosid_Ms95T
+Neosid,Inductor,Ms95, Ms95a, Ms95T, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_Ms95T.pdf
+NeosidInductorMs95 Ms95a Ms95T Fixed inductor SMD
+0
+2
+2
+Inductor_SMD
+L_Neosid_Ms95a
+Neosid,Inductor,Ms95, Ms95a, Ms95T, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_Ms95a.pdf
+NeosidInductorMs95 Ms95a Ms95T Fixed inductor SMD
+0
+2
+2
+Inductor_SMD
+L_Neosid_SM-NE95H
+Neosid, Inductor,SM-NE95H, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMNE95H.pdf
+Neosid Inductor SM-NE95H Fixed inductor SMD
+0
+2
+2
+Inductor_SMD
+L_Neosid_SM-NE127
+Neosid, Inductor, SM-NE127, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMNE127.pdf
+Neosid Inductor SM-NE127 Fixed inductor SMD
+0
+2
+2
+Inductor_SMD
+L_Neosid_SM-NE127_HandSoldering
+Neosid, Inductor, SM-NE127, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMNE127.pdf
+Neosid Inductor SM-NE127 Fixed inductor SMD
+0
+2
+2
+Inductor_SMD
+L_Neosid_SM-NE150
+Neosid, Inductor, SM-NE150, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMNE150.pdf
+Neosid Inductor SM-NE150 Fixed inductor SMD
+0
+2
+2
+Inductor_SMD
+L_Neosid_SM-PIC0512H
+Neosid, Inductor, PIC0512H, Power Inductor, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMPIC0512H.pdf
+Neosid Inductor PIC0512H Power Inductor Fixed inductor SMD
+0
+2
+2
+Inductor_SMD
+L_Neosid_SM-PIC0602H
+Neosid, Power Inductor, SM-PIC0602H, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMPIC0602H.pdf
+Neosid Power Inductor SM-PIC0602H Fixed inductor SMD
+0
+2
+2
+Inductor_SMD
+L_Neosid_SM-PIC0612H
+Neosid, Power Inductor, SM-PIC0612H, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMPIC0612H.pdf
+Neosid Power Inductor SM-PIC0612H Fixed inductor SMD
+0
+2
+2
+Inductor_SMD
+L_Neosid_SM-PIC1004H
+Neosid, Inductor, SM-PIC1004H, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMPIC1004H.pdf
+Neosid Inductor SM-PIC1004H Fixed inductor SMD
+0
+2
+2
+Inductor_SMD
+L_Neosid_SMS-ME3010
+Neosid, Inductor, SMS-ME3010, Fixed inductor, SMD, magnetically shielded, https://neosid.de/import-data/product-pdf/neoFestind_SMSME3010.pdf
+Neosid Inductor SMS-ME3010 Fixed inductor SMD magnetically shielded
+0
+2
+2
+Inductor_SMD
+L_Neosid_SMS-ME3015
+Neosid, Power Inductor, SMS-ME3015, Fixed inductor, SMD, magnetically shielded, https://neosid.de/import-data/product-pdf/neoFestind_SMSME3015.pdf
+Neosid Power Inductor SMS-ME3015 Fixed inductor SMD magnetically shielded
+0
+2
+2
+Inductor_SMD
+L_Neosid_SMs42
+Neosid, Inductor, SMs42, Fixed inductor, SMD, magneticaly shielded, https://neosid.de/import-data/product-pdf/neoFestind_ma_SMs42.pdf
+Neosid Inductor SMs42 Fixed inductor SMD magneticaly shielded
+0
+2
+2
+Inductor_SMD
+L_Neosid_SMs50
+Neosid, Inductor, SMs50, Fixed inductor, SMD, magneticaly shielded, https://neosid.de/import-data/product-pdf/neoFestind_ma_SMs50.pdf
+Neosid Inductor SMs50 Fixed inductor SMD magneticaly shielded
+0
+2
+2
+Inductor_SMD
+L_Neosid_SMs85
+Neosid, Inductor, SMs85, Fixed inductor, SMD, magnetically shielded, https://neosid.de/import-data/product-pdf/neoFestind_ma_SMs85.pdf
+Neosid Inductor SMs85 Fixed inductor SMD magnetically shielded
+0
+2
+2
+Inductor_SMD
+L_Neosid_SMs95_SMs95p
+Neosid, Inductor, SMs95, Fixed inductor, SMD, magnetically shielded, https://neosid.de/import-data/product-pdf/neoFestind_SMs95SMs95p.pdf
+Neosid Inductor SMs95 Fixed inductor SMD magnetically shielded
+0
+2
+2
+Inductor_SMD
+L_Pulse_PA4320
+Inductor SMD Pulse PA4320 http://productfinder.pulseeng.com/products/datasheets/P787.pdf
+Inductor SMD Pulse PA4320
+0
+2
+2
+Inductor_SMD
+L_Sagami_CER1242B
+Inductor, Sagami, h=4.5mm, http://www.sagami-elec.co.jp/file/CER1242B-CER1257B-CER1277B.pdf
+inductor sagami cer12xxb smd
+0
+2
+2
+Inductor_SMD
+L_Sagami_CER1257B
+Inductor, Sagami, h=6.0mm, http://www.sagami-elec.co.jp/file/CER1242B-CER1257B-CER1277B.pdf
+inductor sagami cer12xxb smd
+0
+2
+2
+Inductor_SMD
+L_Sagami_CER1277B
+Inductor, Sagami, h=8.0mm, http://www.sagami-elec.co.jp/file/CER1242B-CER1257B-CER1277B.pdf
+inductor sagami cer12xxb smd
+0
+2
+2
+Inductor_SMD
+L_Sagami_CWR1242C
+Sagami power inductor, CWR1242C, H=4.5mm (http://www.sagami-elec.co.jp/file/16Car_SMDCwr.pdf)
+inductor sagami cwr12xx smd
+0
+4
+2
+Inductor_SMD
+L_Sagami_CWR1257C
+Sagami power inductor, CWR1242C, H=6.0mm (http://www.sagami-elec.co.jp/file/16Car_SMDCwr.pdf)
+inductor sagami cwr12xx smd
+0
+4
+2
+Inductor_SMD
+L_Sagami_CWR1277C
+Sagami power inductor, CWR1242C, H=7.7mm (http://www.sagami-elec.co.jp/file/16Car_SMDCwr.pdf)
+inductor sagami cwr12xx smd
+0
+4
+2
+Inductor_SMD
+L_SigTra_SC3316F
+http://www.signaltransformer.com/sites/all/pdf/smd/P080_SC3316F.pdf
+Choke 
+0
+2
+2
+Inductor_SMD
+L_Sumida_CDMC6D28_7.25x6.5mm
+SMD Power Inductor (http://products.sumida.com/products/pdf/CDMC6D28.pdf)
+Inductor Sumida SMD CDMC6D28
+0
+2
+2
+Inductor_SMD
+L_Sunlord_MWSA0518_5.4x5.2mm
+Inductor, Sunlord, MWSA0518, 5.4mmx5.2mm
+inductor Sunlord smd
+0
+2
+2
+Inductor_SMD
+L_TDK_NLV25_2.5x2.0mm
+TDK NLV25, 2.5x2.0x1.8mm, https://product.tdk.com/info/en/catalog/datasheets/inductor_commercial_standard_nlv25-ef_en.pdf
+tdk nlv25 nlcv25 nlfv25
+0
+2
+2
+Inductor_SMD
+L_TDK_NLV32_3.2x2.5mm
+TDK NLV32, 3.2x2.5x2.2mm, https://product.tdk.com/info/en/catalog/datasheets/inductor_commercial_standard_nlv32-ef_en.pdf
+tdk nlv32 nlcv32 nlfv32
+0
+2
+2
+Inductor_SMD
+L_TDK_SLF6025
+Inductor, TDK, SLF6025, 6.0mmx6.0mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/document/catalog/smd/inductor_commercial_power_slf6025_en.pdf)
+Inductor TDK_SLF6025
+0
+2
+2
+Inductor_SMD
+L_TDK_SLF6028
+Inductor, TDK, SLF6028, 6.0mmx6.0mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/document/catalog/smd/inductor_commercial_power_slf6028_en.pdf)
+Inductor TDK_SLF6028
+0
+2
+2
+Inductor_SMD
+L_TDK_SLF6045
+Inductor, TDK, SLF6045, 6.0mmx6.0mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/document/catalog/smd/inductor_commercial_power_slf6045_en.pdf)
+Inductor TDK_SLF6045
+0
+2
+2
+Inductor_SMD
+L_TDK_SLF7032
+Inductor, TDK, SLF7032, 7.0mmx7.0mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/document/catalog/smd/inductor_commercial_power_slf7032_en.pdf)
+Inductor TDK_SLF7032
+0
+2
+2
+Inductor_SMD
+L_TDK_SLF7045
+Inductor, TDK, SLF7045, 7.0mmx7.0mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/document/catalog/smd/inductor_commercial_power_slf7045_en.pdf)
+Inductor TDK_SLF7045
+0
+2
+2
+Inductor_SMD
+L_TDK_SLF7055
+Inductor, TDK, SLF7055, 7.0mmx7.0mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/document/catalog/smd/inductor_commercial_power_slf7055_en.pdf)
+Inductor TDK_SLF7055
+0
+2
+2
+Inductor_SMD
+L_TDK_SLF10145
+Inductor, TDK, SLF10145, 10.1mmx10.1mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/catalog/datasheets/inductor_automotive_power_slf10145-h_en.pdf)
+Inductor TDK_SLF10145
+0
+2
+2
+Inductor_SMD
+L_TDK_SLF10165
+Inductor, TDK, SLF10165, 10.1mmx10.1mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/catalog/datasheets/inductor_commercial_power_slf10165_en.pdf)
+Inductor TDK_SLF10165
+0
+2
+2
+Inductor_SMD
+L_TDK_SLF12555
+Inductor, TDK, SLF12555, 12.5mmx12.5mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/catalog/datasheets/inductor_commercial_power_slf12555_en.pdf)
+Inductor SLF12555
+0
+2
+2
+Inductor_SMD
+L_TDK_SLF12565
+Inductor, TDK, SLF12565, 12.5mmx12.5mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/catalog/datasheets/inductor_automotive_power_slf12565-h_en.pdf)
+Inductor SLF12565
+0
+2
+2
+Inductor_SMD
+L_TDK_SLF12575
+Inductor, TDK, SLF12575, 12.5mmx12.5mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/catalog/datasheets/inductor_automotive_power_slf12575-h_en.pdf)
+Inductor SLF12575
+0
+2
+2
+Inductor_SMD
+L_TDK_VLF10040
+Inductor,TDK, TDK-VLP-8040, 8.6mmx8.6mm
+inductor TDK VLP smd VLF10040
+0
+2
+2
+Inductor_SMD
+L_TDK_VLP8040
+Inductor,TDK, TDK-VLP-8040, 8.6mmx8.6mm
+inductor TDK VLP smd VLP8040
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_MD-1616
+Inductor, Taiyo Yuden, MD series, Taiyo-Yuden_MD-1616, 1.6mmx1.6mm
+inductor taiyo-yuden md smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_MD-2020
+Inductor, Taiyo Yuden, MD series, Taiyo-Yuden_MD-2020, 2.0mmx2.0mm
+inductor taiyo-yuden md smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_MD-3030
+Inductor, Taiyo Yuden, MD series, Taiyo-Yuden_MD-3030, 3.0mmx3.0mm
+inductor taiyo-yuden md smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_MD-4040
+Inductor, Taiyo Yuden, MD series, Taiyo-Yuden_MD-4040, 4.0mmx4.0mm
+inductor taiyo-yuden md smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_MD-5050
+Inductor, Taiyo Yuden, MD series, Taiyo-Yuden_MD-5050, 5.0mmx5.0mm
+inductor taiyo-yuden md smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_NR-20xx
+Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-20xx, 2.0mmx2.0mm
+inductor taiyo-yuden nr smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_NR-20xx_HandSoldering
+Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-20xx, 2.0mmx2.0mm
+inductor taiyo-yuden nr smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_NR-24xx
+Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-24xx, 2.4mmx2.4mm
+inductor taiyo-yuden nr smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_NR-24xx_HandSoldering
+Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-24xx, 2.4mmx2.4mm
+inductor taiyo-yuden nr smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_NR-30xx
+Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-30xx, 3.0mmx3.0mm
+inductor taiyo-yuden nr smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_NR-30xx_HandSoldering
+Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-30xx, 3.0mmx3.0mm
+inductor taiyo-yuden nr smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_NR-40xx
+Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-40xx, 4.0mmx4.0mm
+inductor taiyo-yuden nr smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_NR-40xx_HandSoldering
+Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-40xx, 4.0mmx4.0mm
+inductor taiyo-yuden nr smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_NR-50xx
+Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-50xx, 4.9mmx4.9mm
+inductor taiyo-yuden nr smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_NR-50xx_HandSoldering
+Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-50xx, 4.9mmx4.9mm
+inductor taiyo-yuden nr smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_NR-60xx
+Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-60xx, 6.0mmx6.0mm
+inductor taiyo-yuden nr smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_NR-60xx_HandSoldering
+Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-60xx, 6.0mmx6.0mm
+inductor taiyo-yuden nr smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_NR-80xx
+Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-80xx, 8.0mmx8.0mm
+inductor taiyo-yuden nr smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_NR-80xx_HandSoldering
+Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-80xx, 8.0mmx8.0mm
+inductor taiyo-yuden nr smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_NR-10050_9.8x10.0mm
+Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-10050, 9.8mmx10.0mm, https://ds.yuden.co.jp/TYCOMPAS/or/specSheet?pn=NR10050T1R3N
+inductor taiyo-yuden nr smd
+0
+2
+2
+Inductor_SMD
+L_Taiyo-Yuden_NR-10050_9.8x10.0mm_HandSoldering
+Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-10050, 9.8mmx10.0mm, https://ds.yuden.co.jp/TYCOMPAS/or/specSheet?pn=NR10050T1R3N
+inductor taiyo-yuden nr smd
+0
+2
+2
+Inductor_SMD
+L_TracoPower_TCK-141
+Choke, SMD, 4.0x4.0mm 2.1mm height, https://www.tracopower.com/products/tck141.pdf
+Choke SMD
+0
+2
+2
+Inductor_SMD
+L_Vishay_IHLP-1212
+Inductor, Vishay, IHLP series, 3.0mmx3.0mm
+inductor vishay ihlp smd
+0
+2
+2
+Inductor_SMD
+L_Vishay_IHLP-1616
+Inductor, Vishay, IHLP series, 4.1mmx4.1mm
+inductor vishay ihlp smd
+0
+2
+2
+Inductor_SMD
+L_Vishay_IHLP-2020
+Inductor, Vishay, IHLP series, 5.1mmx5.1mm
+inductor vishay ihlp smd
+0
+2
+2
+Inductor_SMD
+L_Vishay_IHLP-2525
+Inductor, Vishay, IHLP series, 6.3mmx6.3mm
+inductor vishay ihlp smd
+0
+2
+2
+Inductor_SMD
+L_Vishay_IHLP-4040
+Inductor, Vishay, IHLP series, 10.2mmx10.2mm
+inductor vishay ihlp smd
+0
+2
+2
+Inductor_SMD
+L_Vishay_IHLP-5050
+Inductor, Vishay, IHLP series, 12.7mmx12.7mm
+inductor vishay ihlp smd
+0
+2
+2
+Inductor_SMD
+L_Vishay_IHLP-6767
+Inductor, Vishay, IHLP series, 17.0mmx17.0mm
+inductor vishay ihlp smd
+0
+2
+2
+Inductor_SMD
+L_Vishay_IHSM-3825
+Inductor, Vishay, Vishay_IHSM-3825, http://www.vishay.com/docs/34018/ihsm3825.pdf, 11.2mmx6.3mm
+inductor vishay icsm smd
+0
+2
+2
+Inductor_SMD
+L_Vishay_IHSM-4825
+Inductor, Vishay, Vishay_IHSM-4825, http://www.vishay.com/docs/34019/ihsm4825.pdf, 13.7mmx6.3mm
+inductor vishay icsm smd
+0
+2
+2
+Inductor_SMD
+L_Vishay_IHSM-5832
+Inductor, Vishay, Vishay_IHSM-5832, http://www.vishay.com/docs/34020/ihsm5832.pdf, 16.3mmx8.1mm
+inductor vishay icsm smd
+0
+2
+2
+Inductor_SMD
+L_Vishay_IHSM-7832
+Inductor, Vishay, Vishay_IHSM-7832, http://www.vishay.com/docs/34021/ihsm7832.pdf, 19.8mmx8.1mm
+inductor vishay icsm smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCI-1030
+Inductor, Wuerth Elektronik, Wuerth_HCI-1030, 10.6mmx10.6mm
+inductor Wuerth hci smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCI-1040
+Inductor, Wuerth Elektronik, Wuerth_HCI-1040, 10.2mmx10.2mm
+inductor Wuerth hci smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCI-1050
+Inductor, Wuerth Elektronik, Wuerth_HCI-1050, 10.2mmx10.2mm
+inductor Wuerth hci smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCI-1335
+Inductor, Wuerth Elektronik, Wuerth_HCI-1335, 12.8mmx12.8mm
+inductor Wuerth hci smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCI-1350
+Inductor, Wuerth Elektronik, Wuerth_HCI-1350, 12.8mmx12.8mm
+inductor Wuerth hci smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCI-1365
+Inductor, Wuerth Elektronik, Wuerth_HCI-1365, 12.8mmx12.8mm
+inductor Wuerth hci smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCI-1890
+Inductor, Wuerth Elektronik, Wuerth_HCI-1890, 18.2mmx18.2mm
+inductor Wuerth hci smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCI-2212
+Inductor, Wuerth Elektronik, Wuerth_HCI-2212, 22.5mmx22.0mm
+inductor Wuerth hci smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCI-5040
+Inductor, Wuerth Elektronik, Wuerth_HCI-5040, 5.5mmx5.2mm
+inductor Wuerth hci smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCI-7030
+Inductor, Wuerth Elektronik, Wuerth_HCI-7030, 6.9mmx6.9mm
+inductor Wuerth hci smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCI-7040
+Inductor, Wuerth Elektronik, Wuerth_HCI-7040, 6.9mmx6.9mm
+inductor Wuerth hci smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCI-7050
+Inductor, Wuerth Elektronik, Wuerth_HCI-7050, 6.9mmx6.9mm
+inductor Wuerth hci smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCM-1050
+Inductor, Wuerth Elektronik, Wuerth_HCM-1050, 10.2mmx7.0mm
+inductor Wuerth hcm smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCM-1052
+Inductor, Wuerth Elektronik, Wuerth_HCM-1052, 10.5mmx10.3mm
+inductor Wuerth hcm smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCM-1070
+Inductor, Wuerth Elektronik, Wuerth_HCM-1070, 10.1mmx7.0mm
+inductor Wuerth hcm smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCM-1078
+Inductor, Wuerth Elektronik, Wuerth_HCM-1078, 9.4mmx6.2mm
+inductor Wuerth hcm smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCM-1190
+Inductor, Wuerth Elektronik, Wuerth_HCM-1190, 10.5mmx11.0mm
+inductor Wuerth hcm smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCM-1240
+Inductor, Wuerth Elektronik, Wuerth_HCM-1240, 10.0mmx11.8mm
+inductor Wuerth hcm smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCM-1350
+Inductor, Wuerth Elektronik, Wuerth_HCM-1350, 13.5mmx13.3mm
+inductor Wuerth hcm smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCM-1390
+Inductor, Wuerth Elektronik, Wuerth_HCM-1390, 12.5mmx13.0mm
+inductor Wuerth hcm smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCM-7050
+Inductor, Wuerth Elektronik, Wuerth_HCM-7050, 7.2mmx7.0mm
+inductor Wuerth hcm smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_HCM-7070
+Inductor, Wuerth Elektronik, Wuerth_HCM-7070, 7.4mmx7.2mm
+inductor Wuerth hcm smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_MAPI-1610
+Inductor, Wuerth Elektronik, Wuerth_MAPI-1610, 1.6mmx1.6mm
+inductor Wuerth smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_MAPI-2010
+Inductor, Wuerth Elektronik, Wuerth_MAPI-2010, 2.0mmx1.6mm
+inductor Wuerth smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_MAPI-2506
+Inductor, Wuerth Elektronik, Wuerth_MAPI-2506, 2.5mmx2.0mm
+inductor Wuerth smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_MAPI-2508
+Inductor, Wuerth Elektronik, Wuerth_MAPI-2508, 2.5mmx2.0mm
+inductor Wuerth smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_MAPI-2510
+Inductor, Wuerth Elektronik, Wuerth_MAPI-2510, 2.5mmx2.0mm
+inductor Wuerth smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_MAPI-2512
+Inductor, Wuerth Elektronik, Wuerth_MAPI-2512, 2.5mmx2.0mm
+inductor Wuerth smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_MAPI-3010
+Inductor, Wuerth Elektronik, Wuerth_MAPI-3010, 3.0mmx3.0mm
+inductor Wuerth smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_MAPI-3012
+Inductor, Wuerth Elektronik, Wuerth_MAPI-3012, 3.0mmx3.0mm
+inductor Wuerth smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_MAPI-3015
+Inductor, Wuerth Elektronik, Wuerth_MAPI-3015, 3.0mmx3.0mm
+inductor Wuerth smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_MAPI-3020
+Inductor, Wuerth Elektronik, Wuerth_MAPI-3020, 3.0mmx3.0mm
+inductor Wuerth smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_MAPI-4020
+Inductor, Wuerth Elektronik, Wuerth_MAPI-4020, 4.0mmx4.0mm
+inductor Wuerth smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_MAPI-4030
+Inductor, Wuerth Elektronik, Wuerth_MAPI-4030, 4.0mmx4.0mm
+inductor Wuerth smd
+0
+2
+2
+Inductor_SMD
+L_Wuerth_WE-DD-Typ-L-Typ-XL-Typ-XXL
+Shielded Coupled Inductor, Wuerth Elektronik, WE-DD, SMD, Typ L, Typ XL, Typ XXL, https://katalog.we-online.com/pbs/datasheet/744874001.pdf
+Choke Coupled Double Inductor SMD Wuerth WE-DD TypL TypXL TypXXL 
+0
+4
+4
+Inductor_SMD
+L_Wuerth_WE-DD-Typ-M-Typ-S
+Shielded Coupled Inductor, Wuerth Elektronik, WE-DD, SMD, Typ M, Typ S, https://katalog.we-online.com/pbs/datasheet/744878001.pdf, https://katalog.we-online.de/pbs/datasheet/744877001.pdf
+Choke Coupled Double Inductor SMD Wuerth WE-DD TypM TypS
+0
+4
+4
+Inductor_SMD
+L_Wuerth_WE-PD-Typ-7345
+Shielded Power Inductor, Wuerth Elektronik, WE-PD, SMD, 7345, https://katalog.we-online.com/pbs/datasheet/744777001.pdf
+Choke Shielded Power Inductor WE-PD 7345 Wuerth
+0
+2
+2
+Inductor_SMD
+L_Wuerth_WE-PD-Typ-LS
+Shielded Power Inductor, Wuerth Elektronik, WE-PD, SMD, Typ LS, https://katalog.we-online.com/pbs/datasheet/7447715906.pdf
+Choke Shielded Power Inductor WE-PD TypLS Wuerth
+0
+2
+2
+Inductor_SMD
+L_Wuerth_WE-PD-Typ-LS_Handsoldering
+Shielded Power Inductor, Wuerth Elektronik, WE-PD, SMD, Typ LS, Handsoldering, https://katalog.we-online.com/pbs/datasheet/7447715906.pdf
+Choke Shielded Power Inductor WE-PD TypLS Wuerth
+0
+2
+2
+Inductor_SMD
+L_Wuerth_WE-PD-Typ-M-Typ-S
+Shielded Power Inductor, Wuerth Elektronik, WE-PD, SMT, Typ M, Typ S, https://katalog.we-online.com/pbs/datasheet/744778005.pdf
+Choke Shielded Power Inductor WE-PD TypM TypS Wuerth
+0
+2
+2
+Inductor_SMD
+L_Wuerth_WE-PD-Typ-M-Typ-S_Handsoldering
+Shielded Power Inductor, Wuerth Elektronik, WE-PD, SMT, Typ M, Typ S, Handsoldering, https://katalog.we-online.com/pbs/datasheet/744778005.pdf
+Choke Shielded Power Inductor WE-PD TypM TypS Wuerth
+0
+2
+2
+Inductor_SMD
+L_Wuerth_WE-PD2-Typ-L
+Power Inductor, Wuerth Elektronik, WE-PD2, SMD, Typ L, , https://katalog.we-online.com/pbs/datasheet/74477510.pdf
+Choke Power Inductor WE-PD2 TypL Wuerth
+0
+2
+2
+Inductor_SMD
+L_Wuerth_WE-PD2-Typ-MS
+Power Inductor, Wuerth Elektronik, WE-PD2, SMD, Typ MS, https://katalog.we-online.com/pbs/datasheet/744774022.pdf
+Choke Power Inductor WE-PD2 TypMS Wuerth
+0
+2
+2
+Inductor_SMD
+L_Wuerth_WE-PD2-Typ-XL
+Power Inductor, Wuerth Elektronik, WE-PD2, SMT, Typ XL, https://katalog.we-online.com/pbs/datasheet/744776012.pdf
+Choke Power Inductor WE-PD2 TypXL Wuerth
+0
+2
+2
+Inductor_SMD
+L_Wuerth_WE-PD4-Typ-X
+Power Inductor, Wuerth Elektronik, WE-PD4, SMT, Typ X, https://katalog.we-online.de/pbs/datasheet/74458001.pdf
+Choke Power Inductor WE-PD4 TypX Wuerth
+0
+2
+2
+Inductor_SMD
+L_Wuerth_WE-PDF
+Shielded Power Inductor, Wuerth Elektronik, WE-PDF, SMD, https://katalog.we-online.de/pbs/datasheet/7447797022.pdf
+Choke Shielded Power Inductor WE-PDF Wuerth
+0
+2
+2
+Inductor_SMD
+L_Wuerth_WE-PDF_Handsoldering
+Shielded Power Inductor, Wuerth Elektronik, WE-PDF, SMD, Handsoldering, https://katalog.we-online.de/pbs/datasheet/7447797022.pdf
+Choke Shielded Power Inductor WE-PDF Wuerth Handsoldering
+0
+2
+2
+Inductor_SMD
+L_Wuerth_WE-TPC-3816
+L_Wuerth_WE-TPC-3816 StepUp generated footprint, http://katalog.we-online.de/pbs/datasheet/7440310047.pdf
+wurth wuerth smd inductor
+0
+2
+2
+Inductor_THT
+Choke_EPCOS_B82722A
+Current-Compensated Ring Core Double Chokes, EPCOS, B82722A, 22.3mmx22.7mm, https://en.tdk.eu/inf/30/db/ind_2008/b82722a_j.pdf
+chokes epcos tht
+0
+4
+4
+Inductor_THT
+Choke_Schaffner_RN102-04-14.0x14.0mm
+Current-compensated Chokes, Scaffner, RN102-04, 14.0mmx14.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/
+chokes schaffner tht
+0
+4
+4
+Inductor_THT
+Choke_Schaffner_RN112-04-17.7x17.1mm
+Current-compensated Chokes, Scaffner, RN112-04, 17.7mmx17.1mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/
+chokes schaffner tht
+0
+4
+4
+Inductor_THT
+Choke_Schaffner_RN114-04-22.5x21.5mm
+Current-compensated Chokes, Scaffner, RN114-04, 22.5mmx21.5mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/
+chokes schaffner tht
+0
+4
+4
+Inductor_THT
+Choke_Schaffner_RN116-04-22.5x21.5mm
+Current-compensated Chokes, Scaffner, RN116-04, 22.5mmx21.5mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/
+chokes schaffner tht
+0
+4
+4
+Inductor_THT
+Choke_Schaffner_RN122-04-28.0x27.0mm
+Current-compensated Chokes, Scaffner, RN122-04, 28.0mmx27.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/
+chokes schaffner tht
+0
+4
+4
+Inductor_THT
+Choke_Schaffner_RN142-04-33.1x32.5mm
+Current-compensated Chokes, Scaffner, RN142-04, 33.1mmx32.5mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/
+chokes schaffner tht
+0
+4
+4
+Inductor_THT
+Choke_Schaffner_RN143-04-33.1x32.5mm
+Current-compensated Chokes, Scaffner, RN143-04, 33.1mmx32.5mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/
+chokes schaffner tht
+0
+4
+4
+Inductor_THT
+Choke_Schaffner_RN152-04-43.0x41.8mm
+Current-compensated Chokes, Scaffner, RN152-04, 43.0mmx41.8mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/
+chokes schaffner tht
+0
+4
+4
+Inductor_THT
+Choke_Schaffner_RN202-04-8.8x18.2mm
+Current-compensated Chokes, Scaffner, RN202-04, 8.8mmx18.2mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/
+chokes schaffner tht
+0
+4
+4
+Inductor_THT
+Choke_Schaffner_RN204-04-9.0x14.0mm
+Current-compensated Chokes, Scaffner, RN204-04, 9.0mmx14.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/
+chokes schaffner tht
+0
+4
+4
+Inductor_THT
+Choke_Schaffner_RN212-04-12.5x18.0mm
+Current-compensated Chokes, Scaffner, RN212-04, 12.5mmx18.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/
+chokes schaffner tht
+0
+4
+4
+Inductor_THT
+Choke_Schaffner_RN214-04-15.5x23.0mm
+Current-compensated Chokes, Scaffner, RN214-04, 15.5mmx23.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/
+chokes schaffner tht
+0
+4
+4
+Inductor_THT
+Choke_Schaffner_RN216-04-15.5x23.0mm
+Current-compensated Chokes, Scaffner, RN216-04, 15.5mmx23.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/
+chokes schaffner tht
+0
+4
+4
+Inductor_THT
+Choke_Schaffner_RN222-04-18.0x31.0mm
+Current-compensated Chokes, Scaffner, RN222-04, 18.0mmx31.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/
+chokes schaffner tht
+0
+4
+4
+Inductor_THT
+Choke_Schaffner_RN232-04-18.0x31.0mm
+Current-compensated Chokes, Scaffner, RN232-04, 18.0mmx31.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/
+chokes schaffner tht
+0
+4
+4
+Inductor_THT
+Choke_Schaffner_RN242-04-18.0x31.0mm
+Current-compensated Chokes, Scaffner, RN242-04, 18.0mmx31.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/
+chokes schaffner tht
+0
+4
+4
+Inductor_THT
+L_Axial_L5.0mm_D3.6mm_P10.00mm_Horizontal_Murata_BL01RN1A2A2
+Inductor, Murata BL01RN1A2A2, Axial, Horizontal, pin pitch=10.00mm, length*diameter=5*3.6mm, https://www.murata.com/en-global/products/productdetail?partno=BL01RN1A2A2%23
+inductor axial horizontal
+0
+2
+2
+Inductor_THT
+L_Axial_L5.3mm_D2.2mm_P2.54mm_Vertical_Vishay_IM-1
+Inductor, Axial series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=5.3*2.2mm^2, Vishay, IM-1, http://www.vishay.com/docs/34030/im.pdf
+Inductor Axial series Axial Vertical pin pitch 2.54mm  length 5.3mm diameter 2.2mm Vishay IM-1
+0
+2
+2
+Inductor_THT
+L_Axial_L5.3mm_D2.2mm_P7.62mm_Horizontal_Vishay_IM-1
+Inductor, Axial series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=5.3*2.2mm^2, Vishay, IM-1, http://www.vishay.com/docs/34030/im.pdf
+Inductor Axial series Axial Horizontal pin pitch 7.62mm  length 5.3mm diameter 2.2mm Vishay IM-1
+0
+2
+2
+Inductor_THT
+L_Axial_L5.3mm_D2.2mm_P10.16mm_Horizontal_Vishay_IM-1
+Inductor, Axial series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=5.3*2.2mm^2, Vishay, IM-1, http://www.vishay.com/docs/34030/im.pdf
+Inductor Axial series Axial Horizontal pin pitch 10.16mm  length 5.3mm diameter 2.2mm Vishay IM-1
+0
+2
+2
+Inductor_THT
+L_Axial_L6.6mm_D2.7mm_P2.54mm_Vertical_Vishay_IM-2
+Inductor, Axial series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=6.6*2.7mm^2, Vishay, IM-2, http://www.vishay.com/docs/34030/im.pdf
+Inductor Axial series Axial Vertical pin pitch 2.54mm  length 6.6mm diameter 2.7mm Vishay IM-2
+0
+2
+2
+Inductor_THT
+L_Axial_L6.6mm_D2.7mm_P10.16mm_Horizontal_Vishay_IM-2
+Inductor, Axial series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=6.6*2.7mm^2, Vishay, IM-2, http://www.vishay.com/docs/34030/im.pdf
+Inductor Axial series Axial Horizontal pin pitch 10.16mm  length 6.6mm diameter 2.7mm Vishay IM-2
+0
+2
+2
+Inductor_THT
+L_Axial_L7.0mm_D3.3mm_P2.54mm_Vertical_Fastron_MICC
+Inductor, Axial series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=7*3.3mm^2, Fastron, MICC, http://www.fastrongroup.com/image-show/70/MICC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Vertical pin pitch 2.54mm  length 7mm diameter 3.3mm Fastron MICC
+0
+2
+2
+Inductor_THT
+L_Axial_L7.0mm_D3.3mm_P5.08mm_Vertical_Fastron_MICC
+Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=7*3.3mm^2, Fastron, MICC, http://www.fastrongroup.com/image-show/70/MICC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Vertical pin pitch 5.08mm  length 7mm diameter 3.3mm Fastron MICC
+0
+2
+2
+Inductor_THT
+L_Axial_L7.0mm_D3.3mm_P10.16mm_Horizontal_Fastron_MICC
+Inductor, Axial series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=7*3.3mm^2, Fastron, MICC, http://www.fastrongroup.com/image-show/70/MICC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Horizontal pin pitch 10.16mm  length 7mm diameter 3.3mm Fastron MICC
+0
+2
+2
+Inductor_THT
+L_Axial_L7.0mm_D3.3mm_P12.70mm_Horizontal_Fastron_MICC
+Inductor, Axial series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=7*3.3mm^2, Fastron, MICC, http://www.fastrongroup.com/image-show/70/MICC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Horizontal pin pitch 12.7mm  length 7mm diameter 3.3mm Fastron MICC
+0
+2
+2
+Inductor_THT
+L_Axial_L9.5mm_D4.0mm_P2.54mm_Vertical_Fastron_SMCC
+Inductor, Axial series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=9.5*4mm^2, Fastron, SMCC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_SMCC_NEU.pdf, http://cdn-reichelt.de/documents/datenblatt/B400/LEADEDINDUCTORS.pdf
+Inductor Axial series Axial Vertical pin pitch 2.54mm  length 9.5mm diameter 4mm Fastron SMCC
+0
+2
+2
+Inductor_THT
+L_Axial_L9.5mm_D4.0mm_P5.08mm_Vertical_Fastron_SMCC
+Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.5*4mm^2, Fastron, SMCC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_SMCC_NEU.pdf, http://cdn-reichelt.de/documents/datenblatt/B400/LEADEDINDUCTORS.pdf
+Inductor Axial series Axial Vertical pin pitch 5.08mm  length 9.5mm diameter 4mm Fastron SMCC
+0
+2
+2
+Inductor_THT
+L_Axial_L9.5mm_D4.0mm_P12.70mm_Horizontal_Fastron_SMCC
+Inductor, Axial series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9.5*4mm^2, Fastron, SMCC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_SMCC_NEU.pdf, http://cdn-reichelt.de/documents/datenblatt/B400/LEADEDINDUCTORS.pdf
+Inductor Axial series Axial Horizontal pin pitch 12.7mm  length 9.5mm diameter 4mm Fastron SMCC
+0
+2
+2
+Inductor_THT
+L_Axial_L9.5mm_D4.0mm_P15.24mm_Horizontal_Fastron_SMCC
+Inductor, Axial series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=9.5*4mm^2, Fastron, SMCC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_SMCC_NEU.pdf, http://cdn-reichelt.de/documents/datenblatt/B400/LEADEDINDUCTORS.pdf
+Inductor Axial series Axial Horizontal pin pitch 15.24mm  length 9.5mm diameter 4mm Fastron SMCC
+0
+2
+2
+Inductor_THT
+L_Axial_L11.0mm_D4.5mm_P5.08mm_Vertical_Fastron_MECC
+Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=11*4.5mm^2, Fastron, MECC, http://www.fastrongroup.com/image-show/21/MECC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Vertical pin pitch 5.08mm  length 11mm diameter 4.5mm Fastron MECC
+0
+2
+2
+Inductor_THT
+L_Axial_L11.0mm_D4.5mm_P7.62mm_Vertical_Fastron_MECC
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=11*4.5mm^2, Fastron, MECC, http://www.fastrongroup.com/image-show/21/MECC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 11mm diameter 4.5mm Fastron MECC
+0
+2
+2
+Inductor_THT
+L_Axial_L11.0mm_D4.5mm_P15.24mm_Horizontal_Fastron_MECC
+Inductor, Axial series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=11*4.5mm^2, Fastron, MECC, http://www.fastrongroup.com/image-show/21/MECC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Horizontal pin pitch 15.24mm  length 11mm diameter 4.5mm Fastron MECC
+0
+2
+2
+Inductor_THT
+L_Axial_L12.0mm_D5.0mm_P5.08mm_Vertical_Fastron_MISC
+Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=12*5mm^2, Fastron, MISC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_MISC.pdf
+Inductor Axial series Axial Vertical pin pitch 5.08mm  length 12mm diameter 5mm Fastron MISC
+0
+2
+2
+Inductor_THT
+L_Axial_L12.0mm_D5.0mm_P7.62mm_Vertical_Fastron_MISC
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=12*5mm^2, Fastron, MISC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_MISC.pdf
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 12mm diameter 5mm Fastron MISC
+0
+2
+2
+Inductor_THT
+L_Axial_L12.0mm_D5.0mm_P15.24mm_Horizontal_Fastron_MISC
+Inductor, Axial series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=12*5mm^2, Fastron, MISC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_MISC.pdf
+Inductor Axial series Axial Horizontal pin pitch 15.24mm  length 12mm diameter 5mm Fastron MISC
+0
+2
+2
+Inductor_THT
+L_Axial_L12.8mm_D5.8mm_P5.08mm_Vertical_Fastron_HBCC
+Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=12.8*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Vertical pin pitch 5.08mm  length 12.8mm diameter 5.8mm Fastron HBCC
+0
+2
+2
+Inductor_THT
+L_Axial_L12.8mm_D5.8mm_P7.62mm_Vertical_Fastron_HBCC
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=12.8*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 12.8mm diameter 5.8mm Fastron HBCC
+0
+2
+2
+Inductor_THT
+L_Axial_L12.8mm_D5.8mm_P20.32mm_Horizontal_Fastron_HBCC
+Inductor, Axial series, Axial, Horizontal, pin pitch=20.32mm, , length*diameter=12.8*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Horizontal pin pitch 20.32mm  length 12.8mm diameter 5.8mm Fastron HBCC
+0
+2
+2
+Inductor_THT
+L_Axial_L12.8mm_D5.8mm_P25.40mm_Horizontal_Fastron_HBCC
+Inductor, Axial series, Axial, Horizontal, pin pitch=25.4mm, , length*diameter=12.8*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Horizontal pin pitch 25.4mm  length 12.8mm diameter 5.8mm Fastron HBCC
+0
+2
+2
+Inductor_THT
+L_Axial_L13.0mm_D4.5mm_P5.08mm_Vertical_Fastron_HCCC
+Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=13*4.5mm^2, Fastron, HCCC, http://www.fastrongroup.com/image-show/19/HCCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Vertical pin pitch 5.08mm  length 13mm diameter 4.5mm Fastron HCCC
+0
+2
+2
+Inductor_THT
+L_Axial_L13.0mm_D4.5mm_P7.62mm_Vertical_Fastron_HCCC
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=13*4.5mm^2, Fastron, HCCC, http://www.fastrongroup.com/image-show/19/HCCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 13mm diameter 4.5mm Fastron HCCC
+0
+2
+2
+Inductor_THT
+L_Axial_L13.0mm_D4.5mm_P15.24mm_Horizontal_Fastron_HCCC
+Inductor, Axial series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=13*4.5mm^2, Fastron, HCCC, http://www.fastrongroup.com/image-show/19/HCCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Horizontal pin pitch 15.24mm  length 13mm diameter 4.5mm Fastron HCCC
+0
+2
+2
+Inductor_THT
+L_Axial_L14.0mm_D4.5mm_P5.08mm_Vertical_Fastron_LACC
+Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=14*4.5mm^2, Fastron, LACC, http://www.fastrongroup.com/image-show/20/LACC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Vertical pin pitch 5.08mm  length 14mm diameter 4.5mm Fastron LACC
+0
+2
+2
+Inductor_THT
+L_Axial_L14.0mm_D4.5mm_P7.62mm_Vertical_Fastron_LACC
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=14*4.5mm^2, Fastron, LACC, http://www.fastrongroup.com/image-show/20/LACC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 14mm diameter 4.5mm Fastron LACC
+0
+2
+2
+Inductor_THT
+L_Axial_L14.0mm_D4.5mm_P15.24mm_Horizontal_Fastron_LACC
+Inductor, Axial series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=14*4.5mm^2, Fastron, LACC, http://www.fastrongroup.com/image-show/20/LACC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Horizontal pin pitch 15.24mm  length 14mm diameter 4.5mm Fastron LACC
+0
+2
+2
+Inductor_THT
+L_Axial_L14.5mm_D5.8mm_P5.08mm_Vertical_Fastron_HBCC
+Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=14.5*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Vertical pin pitch 5.08mm  length 14.5mm diameter 5.8mm Fastron HBCC
+0
+2
+2
+Inductor_THT
+L_Axial_L14.5mm_D5.8mm_P7.62mm_Vertical_Fastron_HBCC
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=14.5*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 14.5mm diameter 5.8mm Fastron HBCC
+0
+2
+2
+Inductor_THT
+L_Axial_L14.5mm_D5.8mm_P20.32mm_Horizontal_Fastron_HBCC
+Inductor, Axial series, Axial, Horizontal, pin pitch=20.32mm, , length*diameter=14.5*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Horizontal pin pitch 20.32mm  length 14.5mm diameter 5.8mm Fastron HBCC
+0
+2
+2
+Inductor_THT
+L_Axial_L14.5mm_D5.8mm_P25.40mm_Horizontal_Fastron_HBCC
+Inductor, Axial series, Axial, Horizontal, pin pitch=25.4mm, , length*diameter=14.5*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Horizontal pin pitch 25.4mm  length 14.5mm diameter 5.8mm Fastron HBCC
+0
+2
+2
+Inductor_THT
+L_Axial_L16.0mm_D6.3mm_P5.08mm_Vertical_Fastron_VHBCC
+Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=16*6.3mm^2, Fastron, VHBCC, http://www.fastrongroup.com/image-show/25/VHBCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Vertical pin pitch 5.08mm  length 16mm diameter 6.3mm Fastron VHBCC
+0
+2
+2
+Inductor_THT
+L_Axial_L16.0mm_D6.3mm_P7.62mm_Vertical_Fastron_VHBCC
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=16*6.3mm^2, Fastron, VHBCC, http://www.fastrongroup.com/image-show/25/VHBCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 16mm diameter 6.3mm Fastron VHBCC
+0
+2
+2
+Inductor_THT
+L_Axial_L16.0mm_D6.3mm_P20.32mm_Horizontal_Fastron_VHBCC
+Inductor, Axial series, Axial, Horizontal, pin pitch=20.32mm, , length*diameter=16*6.3mm^2, Fastron, VHBCC, http://www.fastrongroup.com/image-show/25/VHBCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Horizontal pin pitch 20.32mm  length 16mm diameter 6.3mm Fastron VHBCC
+0
+2
+2
+Inductor_THT
+L_Axial_L16.0mm_D6.3mm_P25.40mm_Horizontal_Fastron_VHBCC
+Inductor, Axial series, Axial, Horizontal, pin pitch=25.4mm, , length*diameter=16*6.3mm^2, Fastron, VHBCC, http://www.fastrongroup.com/image-show/25/VHBCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Horizontal pin pitch 25.4mm  length 16mm diameter 6.3mm Fastron VHBCC
+0
+2
+2
+Inductor_THT
+L_Axial_L16.0mm_D7.5mm_P5.08mm_Vertical_Fastron_XHBCC
+Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=16*7.5mm^2, Fastron, XHBCC, http://www.fastrongroup.com/image-show/26/XHBCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Vertical pin pitch 5.08mm  length 16mm diameter 7.5mm Fastron XHBCC
+0
+2
+2
+Inductor_THT
+L_Axial_L16.0mm_D7.5mm_P7.62mm_Vertical_Fastron_XHBCC
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=16*7.5mm^2, Fastron, XHBCC, http://www.fastrongroup.com/image-show/26/XHBCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 16mm diameter 7.5mm Fastron XHBCC
+0
+2
+2
+Inductor_THT
+L_Axial_L16.0mm_D7.5mm_P20.32mm_Horizontal_Fastron_XHBCC
+Inductor, Axial series, Axial, Horizontal, pin pitch=20.32mm, , length*diameter=16*7.5mm^2, Fastron, XHBCC, http://www.fastrongroup.com/image-show/26/XHBCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Horizontal pin pitch 20.32mm  length 16mm diameter 7.5mm Fastron XHBCC
+0
+2
+2
+Inductor_THT
+L_Axial_L16.0mm_D7.5mm_P25.40mm_Horizontal_Fastron_XHBCC
+Inductor, Axial series, Axial, Horizontal, pin pitch=25.4mm, , length*diameter=16*7.5mm^2, Fastron, XHBCC, http://www.fastrongroup.com/image-show/26/XHBCC.pdf?type=Complete-DataSheet&productType=series
+Inductor Axial series Axial Horizontal pin pitch 25.4mm  length 16mm diameter 7.5mm Fastron XHBCC
+0
+2
+2
+Inductor_THT
+L_Axial_L16.0mm_D9.5mm_P5.08mm_Vertical_Vishay_IM-10-37
+Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=16*9.5mm^2, Vishay, IM-10-37, http://www.vishay.com/docs/34030/im10.pdf
+Inductor Axial series Axial Vertical pin pitch 5.08mm  length 16mm diameter 9.5mm Vishay IM-10-37
+0
+2
+2
+Inductor_THT
+L_Axial_L16.0mm_D9.5mm_P20.32mm_Horizontal_Vishay_IM-10-37
+Inductor, Axial series, Axial, Horizontal, pin pitch=20.32mm, , length*diameter=16*9.5mm^2, Vishay, IM-10-37, http://www.vishay.com/docs/34030/im10.pdf
+Inductor Axial series Axial Horizontal pin pitch 20.32mm  length 16mm diameter 9.5mm Vishay IM-10-37
+0
+2
+2
+Inductor_THT
+L_Axial_L17.5mm_D12.0mm_P7.62mm_Vertical_Vishay_IM-10-46
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=17.5*12mm^2, Vishay, IM-10-46, http://www.vishay.com/docs/34030/im10.pdf
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 17.5mm diameter 12mm Vishay IM-10-46
+0
+2
+2
+Inductor_THT
+L_Axial_L17.5mm_D12.0mm_P20.32mm_Horizontal_Vishay_IM-10-46
+Inductor, Axial series, Axial, Horizontal, pin pitch=20.32mm, , length*diameter=17.5*12mm^2, Vishay, IM-10-46, http://www.vishay.com/docs/34030/im10.pdf
+Inductor Axial series Axial Horizontal pin pitch 20.32mm  length 17.5mm diameter 12mm Vishay IM-10-46
+0
+2
+2
+Inductor_THT
+L_Axial_L20.0mm_D8.0mm_P5.08mm_Vertical
+Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=20*8mm^2
+Inductor Axial series Axial Vertical pin pitch 5.08mm  length 20mm diameter 8mm
+0
+2
+2
+Inductor_THT
+L_Axial_L20.0mm_D8.0mm_P7.62mm_Vertical
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=20*8mm^2
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 20mm diameter 8mm
+0
+2
+2
+Inductor_THT
+L_Axial_L20.0mm_D8.0mm_P25.40mm_Horizontal
+Inductor, Axial series, Axial, Horizontal, pin pitch=25.4mm, , length*diameter=20*8mm^2
+Inductor Axial series Axial Horizontal pin pitch 25.4mm  length 20mm diameter 8mm
+0
+2
+2
+Inductor_THT
+L_Axial_L20.3mm_D12.1mm_P7.62mm_Vertical_Vishay_IHA-101
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=20.32*12.07mm^2, Vishay, IHA-101, http://www.vishay.com/docs/34014/iha.pdf
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 20.32mm diameter 12.07mm Vishay IHA-101
+0
+2
+2
+Inductor_THT
+L_Axial_L20.3mm_D12.1mm_P28.50mm_Horizontal_Vishay_IHA-101
+Inductor, Axial series, Axial, Horizontal, pin pitch=28.5mm, , length*diameter=20.32*12.07mm^2, Vishay, IHA-101, http://www.vishay.com/docs/34014/iha.pdf
+Inductor Axial series Axial Horizontal pin pitch 28.5mm  length 20.32mm diameter 12.07mm Vishay IHA-101
+0
+2
+2
+Inductor_THT
+L_Axial_L20.3mm_D12.7mm_P7.62mm_Vertical_Vishay_IHA-201
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=20.32*12.7mm^2, Vishay, IHA-201, http://www.vishay.com/docs/34014/iha.pdf
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 20.32mm diameter 12.7mm Vishay IHA-201
+0
+2
+2
+Inductor_THT
+L_Axial_L20.3mm_D12.7mm_P25.40mm_Horizontal_Vishay_IHA-201
+Inductor, Axial series, Axial, Horizontal, pin pitch=25.4mm, , length*diameter=20.32*12.7mm^2, Vishay, IHA-201, http://www.vishay.com/docs/34014/iha.pdf
+Inductor Axial series Axial Horizontal pin pitch 25.4mm  length 20.32mm diameter 12.7mm Vishay IHA-201
+0
+2
+2
+Inductor_THT
+L_Axial_L23.4mm_D12.7mm_P7.62mm_Vertical_Vishay_IHA-203
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=23.37*12.7mm^2, Vishay, IHA-203, http://www.vishay.com/docs/34014/iha.pdf
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 23.37mm diameter 12.7mm Vishay IHA-203
+0
+2
+2
+Inductor_THT
+L_Axial_L23.4mm_D12.7mm_P32.00mm_Horizontal_Vishay_IHA-203
+Inductor, Axial series, Axial, Horizontal, pin pitch=32mm, , length*diameter=23.37*12.7mm^2, Vishay, IHA-203, http://www.vishay.com/docs/34014/iha.pdf
+Inductor Axial series Axial Horizontal pin pitch 32mm  length 23.37mm diameter 12.7mm Vishay IHA-203
+0
+2
+2
+Inductor_THT
+L_Axial_L24.0mm_D7.1mm_P5.08mm_Vertical_Vishay_IM-10-28
+Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=24*7.1mm^2, Vishay, IM-10-28, http://www.vishay.com/docs/34035/im10.pdf
+Inductor Axial series Axial Vertical pin pitch 5.08mm  length 24mm diameter 7.1mm Vishay IM-10-28
+0
+2
+2
+Inductor_THT
+L_Axial_L24.0mm_D7.1mm_P30.48mm_Horizontal_Vishay_IM-10-28
+Inductor, Axial series, Axial, Horizontal, pin pitch=30.48mm, , length*diameter=24*7.1mm^2, Vishay, IM-10-28, http://www.vishay.com/docs/34035/im10.pdf
+Inductor Axial series Axial Horizontal pin pitch 30.48mm  length 24mm diameter 7.1mm Vishay IM-10-28
+0
+2
+2
+Inductor_THT
+L_Axial_L24.0mm_D7.5mm_P5.08mm_Vertical_Fastron_MESC
+Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=24*7.5mm^2, Fastron, MESC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_MESC.pdf
+Inductor Axial series Axial Vertical pin pitch 5.08mm  length 24mm diameter 7.5mm Fastron MESC
+0
+2
+2
+Inductor_THT
+L_Axial_L24.0mm_D7.5mm_P7.62mm_Vertical_Fastron_MESC
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=24*7.5mm^2, Fastron, MESC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_MESC.pdf
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 24mm diameter 7.5mm Fastron MESC
+0
+2
+2
+Inductor_THT
+L_Axial_L24.0mm_D7.5mm_P27.94mm_Horizontal_Fastron_MESC
+Inductor, Axial series, Axial, Horizontal, pin pitch=27.94mm, , length*diameter=24*7.5mm^2, Fastron, MESC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_MESC.pdf
+Inductor Axial series Axial Horizontal pin pitch 27.94mm  length 24mm diameter 7.5mm Fastron MESC
+0
+2
+2
+Inductor_THT
+L_Axial_L26.0mm_D9.0mm_P5.08mm_Vertical_Fastron_77A
+Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=26*9mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf
+Inductor Axial series Axial Vertical pin pitch 5.08mm  length 26mm diameter 9mm Fastron 77A
+0
+2
+2
+Inductor_THT
+L_Axial_L26.0mm_D9.0mm_P7.62mm_Vertical_Fastron_77A
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=26*9mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 26mm diameter 9mm Fastron 77A
+0
+2
+2
+Inductor_THT
+L_Axial_L26.0mm_D9.0mm_P30.48mm_Horizontal_Fastron_77A
+Inductor, Axial series, Axial, Horizontal, pin pitch=30.48mm, , length*diameter=26*9mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf
+Inductor Axial series Axial Horizontal pin pitch 30.48mm  length 26mm diameter 9mm Fastron 77A
+0
+2
+2
+Inductor_THT
+L_Axial_L26.0mm_D10.0mm_P5.08mm_Vertical_Fastron_77A
+Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=26*10mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf
+Inductor Axial series Axial Vertical pin pitch 5.08mm  length 26mm diameter 10mm Fastron 77A
+0
+2
+2
+Inductor_THT
+L_Axial_L26.0mm_D10.0mm_P7.62mm_Vertical_Fastron_77A
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=26*10mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 26mm diameter 10mm Fastron 77A
+0
+2
+2
+Inductor_THT
+L_Axial_L26.0mm_D10.0mm_P30.48mm_Horizontal_Fastron_77A
+Inductor, Axial series, Axial, Horizontal, pin pitch=30.48mm, , length*diameter=26*10mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf
+Inductor Axial series Axial Horizontal pin pitch 30.48mm  length 26mm diameter 10mm Fastron 77A
+0
+2
+2
+Inductor_THT
+L_Axial_L26.0mm_D11.0mm_P5.08mm_Vertical_Fastron_77A
+Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=26*11mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf
+Inductor Axial series Axial Vertical pin pitch 5.08mm  length 26mm diameter 11mm Fastron 77A
+0
+2
+2
+Inductor_THT
+L_Axial_L26.0mm_D11.0mm_P7.62mm_Vertical_Fastron_77A
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=26*11mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 26mm diameter 11mm Fastron 77A
+0
+2
+2
+Inductor_THT
+L_Axial_L26.0mm_D11.0mm_P30.48mm_Horizontal_Fastron_77A
+Inductor, Axial series, Axial, Horizontal, pin pitch=30.48mm, , length*diameter=26*11mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf
+Inductor Axial series Axial Horizontal pin pitch 30.48mm  length 26mm diameter 11mm Fastron 77A
+0
+2
+2
+Inductor_THT
+L_Axial_L26.7mm_D12.1mm_P7.62mm_Vertical_Vishay_IHA-103
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=26.67*12.07mm^2, Vishay, IHA-103, http://www.vishay.com/docs/34014/iha.pdf
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 26.67mm diameter 12.07mm Vishay IHA-103
+0
+2
+2
+Inductor_THT
+L_Axial_L26.7mm_D12.1mm_P35.00mm_Horizontal_Vishay_IHA-103
+Inductor, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=26.67*12.07mm^2, Vishay, IHA-103, http://www.vishay.com/docs/34014/iha.pdf
+Inductor Axial series Axial Horizontal pin pitch 35mm  length 26.67mm diameter 12.07mm Vishay IHA-103
+0
+2
+2
+Inductor_THT
+L_Axial_L26.7mm_D14.0mm_P7.62mm_Vertical_Vishay_IHA-104
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=26.67*13.97mm^2, Vishay, IHA-104, http://www.vishay.com/docs/34014/iha.pdf
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 26.67mm diameter 13.97mm Vishay IHA-104
+0
+2
+2
+Inductor_THT
+L_Axial_L26.7mm_D14.0mm_P35.00mm_Horizontal_Vishay_IHA-104
+Inductor, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=26.67*13.97mm^2, Vishay, IHA-104, http://www.vishay.com/docs/34014/iha.pdf
+Inductor Axial series Axial Horizontal pin pitch 35mm  length 26.67mm diameter 13.97mm Vishay IHA-104
+0
+2
+2
+Inductor_THT
+L_Axial_L29.9mm_D14.0mm_P7.62mm_Vertical_Vishay_IHA-105
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=29.85*13.97mm^2, Vishay, IHA-105, http://www.vishay.com/docs/34014/iha.pdf
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 29.85mm diameter 13.97mm Vishay IHA-105
+0
+2
+2
+Inductor_THT
+L_Axial_L29.9mm_D14.0mm_P38.00mm_Horizontal_Vishay_IHA-105
+Inductor, Axial series, Axial, Horizontal, pin pitch=38mm, , length*diameter=29.85*13.97mm^2, Vishay, IHA-105, http://www.vishay.com/docs/34014/iha.pdf
+Inductor Axial series Axial Horizontal pin pitch 38mm  length 29.85mm diameter 13.97mm Vishay IHA-105
+0
+2
+2
+Inductor_THT
+L_Axial_L30.0mm_D8.0mm_P5.08mm_Vertical_Fastron_77A
+Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=30*8mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf
+Inductor Axial series Axial Vertical pin pitch 5.08mm  length 30mm diameter 8mm Fastron 77A
+0
+2
+2
+Inductor_THT
+L_Axial_L30.0mm_D8.0mm_P7.62mm_Vertical_Fastron_77A
+Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=30*8mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf
+Inductor Axial series Axial Vertical pin pitch 7.62mm  length 30mm diameter 8mm Fastron 77A
+0
+2
+2
+Inductor_THT
+L_Axial_L30.0mm_D8.0mm_P35.56mm_Horizontal_Fastron_77A
+Inductor, Axial series, Axial, Horizontal, pin pitch=35.56mm, , length*diameter=30*8mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf
+Inductor Axial series Axial Horizontal pin pitch 35.56mm  length 30mm diameter 8mm Fastron 77A
+0
+2
+2
+Inductor_THT
+L_CommonMode_Toroid_Vertical_L19.3mm_W10.8mm_Px6.35mm_Py15.24mm_Bourns_8100
+L_CommonMode_Toroid, Vertical series, Radial, pin pitch=6.35*15.24mm^2, , length*width=19.304*10.795mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf
+L_CommonMode_Toroid Vertical series Radial pin pitch 6.35*15.24mm^2  length 19.304mm width 10.795mm Bourns 8100
+0
+4
+4
+Inductor_THT
+L_CommonMode_Toroid_Vertical_L21.0mm_W10.0mm_Px5.08mm_Py12.70mm_muRATA_5100
+L_CommonMode_Toroid, Vertical series, Radial, pin pitch=5.08*12.70mm^2, , length*width=21*10mm^2, muRATA, 5100, http://www.murata-ps.com/data/magnetics/kmp_5100.pdf
+L_CommonMode_Toroid Vertical series Radial pin pitch 5.08*12.70mm^2  length 21mm width 10mm muRATA 5100
+0
+4
+4
+Inductor_THT
+L_CommonMode_Toroid_Vertical_L24.0mm_W16.3mm_Px10.16mm_Py20.32mm_muRATA_5200
+L_CommonMode_Toroid, Vertical series, Radial, pin pitch=10.16*20.32mm^2, , length*width=24*16.3mm^2, muRATA, 5200, http://www.murata-ps.com/data/magnetics/kmp_5200.pdf
+L_CommonMode_Toroid Vertical series Radial pin pitch 10.16*20.32mm^2  length 24mm width 16.3mm muRATA 5200
+0
+4
+4
+Inductor_THT
+L_CommonMode_Toroid_Vertical_L30.5mm_W15.2mm_Px10.16mm_Py20.32mm_Bourns_8100
+L_CommonMode_Toroid, Vertical series, Radial, pin pitch=10.16*20.32mm^2, , length*width=30.479999999999997*15.239999999999998mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf
+L_CommonMode_Toroid Vertical series Radial pin pitch 10.16*20.32mm^2  length 30.479999999999997mm width 15.239999999999998mm Bourns 8100
+0
+4
+4
+Inductor_THT
+L_CommonMode_Toroid_Vertical_L34.3mm_W20.3mm_Px15.24mm_Py22.86mm_Bourns_8100
+L_CommonMode_Toroid, Vertical series, Radial, pin pitch=15.24*22.86mm^2, , length*width=34.29*20.32mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf
+L_CommonMode_Toroid Vertical series Radial pin pitch 15.24*22.86mm^2  length 34.29mm width 20.32mm Bourns 8100
+0
+4
+4
+Inductor_THT
+L_CommonMode_Toroid_Vertical_L36.8mm_W20.3mm_Px15.24mm_Py22.86mm_Bourns_8100
+L_CommonMode_Toroid, Vertical series, Radial, pin pitch=15.24*22.86mm^2, , length*width=36.83*20.32mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf
+L_CommonMode_Toroid Vertical series Radial pin pitch 15.24*22.86mm^2  length 36.83mm width 20.32mm Bourns 8100
+0
+4
+4
+Inductor_THT
+L_CommonMode_Toroid_Vertical_L38.1mm_W20.3mm_Px15.24mm_Py22.86mm_Bourns_8100
+L_CommonMode_Toroid, Vertical series, Radial, pin pitch=15.24*22.86mm^2, , length*width=38.099999999999994*20.32mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf
+L_CommonMode_Toroid Vertical series Radial pin pitch 15.24*22.86mm^2  length 38.099999999999994mm width 20.32mm Bourns 8100
+0
+4
+4
+Inductor_THT
+L_CommonMode_Toroid_Vertical_L39.4mm_W20.3mm_Px15.24mm_Py22.86mm_Bourns_8100
+L_CommonMode_Toroid, Vertical series, Radial, pin pitch=15.24*22.86mm^2, , length*width=39.37*20.32mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf
+L_CommonMode_Toroid Vertical series Radial pin pitch 15.24*22.86mm^2  length 39.37mm width 20.32mm Bourns 8100
+0
+4
+4
+Inductor_THT
+L_CommonMode_Toroid_Vertical_L41.9mm_W20.3mm_Px15.24mm_Py22.86mm_Bourns_8100
+L_CommonMode_Toroid, Vertical series, Radial, pin pitch=15.24*22.86mm^2, , length*width=41.91*20.32mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf
+L_CommonMode_Toroid Vertical series Radial pin pitch 15.24*22.86mm^2  length 41.91mm width 20.32mm Bourns 8100
+0
+4
+4
+Inductor_THT
+L_CommonMode_Toroid_Vertical_L43.2mm_W22.9mm_Px17.78mm_Py30.48mm_Bourns_8100
+L_CommonMode_Toroid, Vertical series, Radial, pin pitch=17.78*30.48mm^2, , length*width=43.18*22.86mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf
+L_CommonMode_Toroid Vertical series Radial pin pitch 17.78*30.48mm^2  length 43.18mm width 22.86mm Bourns 8100
+0
+4
+4
+Inductor_THT
+L_CommonMode_Wuerth_WE-CMB-L
+Wuerth, WE-CMB, Bauform L,
+CommonModeChoke Gleichtaktdrossel 
+0
+4
+4
+Inductor_THT
+L_CommonMode_Wuerth_WE-CMB-M
+Wuerth, WE-CMB, Bauform M,
+CommonModeChoke Gleichtaktdrossel 
+0
+4
+4
+Inductor_THT
+L_CommonMode_Wuerth_WE-CMB-S
+Wuerth, WE-CMB, Bauform S,
+CommonModeChoke Gleichtaktdrossel 
+0
+4
+4
+Inductor_THT
+L_CommonMode_Wuerth_WE-CMB-XL
+Wuerth, WE-CMB, Bauform XL,
+CommonModeChoke Gleichtaktdrossel 
+0
+4
+4
+Inductor_THT
+L_CommonMode_Wuerth_WE-CMB-XS
+Wuerth, WE-CMB, Bauform XS,
+CommonModeChoke Gleichtaktdrossel 
+0
+4
+4
+Inductor_THT
+L_CommonMode_Wuerth_WE-CMB-XXL
+Wuerth, WE-CMB, Bauform XXL,
+CommonModeChoke Gleichtaktdrossel 
+0
+4
+4
+Inductor_THT
+L_Mount_Lodestone_VTM120
+Lodestone Pacific, 30.48mm diameter vertical toroid mount, 16AWG/1.27mm holes, http://www.lodestonepacific.com/CatKpdf/VTM_Series.pdf
+vertical inductor toroid mount
+0
+4
+4
+Inductor_THT
+L_Mount_Lodestone_VTM160
+Lodestone Pacific, 40.64mm diameter vertical toroid mount, 16AWG/1.27mm holes, http://www.lodestonepacific.com/CatKpdf/VTM_Series.pdf
+vertical inductor toroid mount
+0
+4
+4
+Inductor_THT
+L_Mount_Lodestone_VTM254
+Lodestone Pacific, 64.51mm diameter vertical toroid mount, 16AWG/1.27mm holes, http://www.lodestonepacific.com/CatKpdf/VTM_Series.pdf
+vertical inductor toroid mount
+0
+4
+4
+Inductor_THT
+L_Mount_Lodestone_VTM280
+Lodestone Pacific, 71.12mm diameter vertical toroid mount, 16AWG/1.27mm holes, http://www.lodestonepacific.com/CatKpdf/VTM_Series.pdf
+vertical inductor toroid mount
+0
+4
+4
+Inductor_THT
+L_Mount_Lodestone_VTM950-6
+Lodestone Pacific, vertical toroid mount, 11x19mm, 6 pins, http://www.lodestonepacific.com/CatKpdf/VTM950-6.pdf
+vertical inductor toroid mount
+0
+6
+6
+Inductor_THT
+L_Radial_D6.0mm_P4.00mm
+Inductor, Radial series, Radial, pin pitch=4.00mm, , diameter=6.0mm, http://www.abracon.com/Magnetics/radial/AIUR-07.pdf
+Inductor Radial series Radial pin pitch 4.00mm  diameter 6.0mm
+0
+2
+2
+Inductor_THT
+L_Radial_D7.0mm_P3.00mm
+Inductor, Radial series, Radial, pin pitch=3.00mm, , diameter=7mm, http://www.abracon.com/Magnetics/radial/AIUR-16.pdf
+Inductor Radial series Radial pin pitch 3.00mm  diameter 7mm
+0
+2
+2
+Inductor_THT
+L_Radial_D7.2mm_P3.00mm_MuRATA_1700
+Inductor, Radial series, Radial, pin pitch=3.00mm, , diameter=7.2mm, MuRATA, 1700, http://www.murata-ps.com/data/magnetics/kmp_1700.pdf
+Inductor Radial series Radial pin pitch 3.00mm  diameter 7.2mm MuRATA 1700
+0
+2
+2
+Inductor_THT
+L_Radial_D7.5mm_P3.50mm_Fastron_07P
+Inductor, Radial series, Radial, pin pitch=3.50mm, , diameter=7.5mm, Fastron, 07P, http://www.fastrongroup.com/image-show/39/07P.pdf?type=Complete-DataSheet&productType=series
+Inductor Radial series Radial pin pitch 3.50mm  diameter 7.5mm Fastron 07P
+0
+2
+2
+Inductor_THT
+L_Radial_D7.5mm_P5.00mm_Fastron_07P
+Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=7.5mm, Fastron, 07P, http://www.fastrongroup.com/image-show/39/07P.pdf?type=Complete-DataSheet&productType=series
+Inductor Radial series Radial pin pitch 5.00mm  diameter 7.5mm Fastron 07P
+0
+2
+2
+Inductor_THT
+L_Radial_D7.8mm_P5.00mm_Fastron_07HCP
+Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=7.8mm, Fastron, 07HCP, http://www.abracon.com/Magnetics/radial/AISR875.pdf
+Inductor Radial series Radial pin pitch 5.00mm  diameter 7.8mm Fastron 07HCP
+0
+2
+2
+Inductor_THT
+L_Radial_D8.7mm_P5.00mm_Fastron_07HCP
+Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=8.7mm, Fastron, 07HCP, http://cdn-reichelt.de/documents/datenblatt/B400/DS_07HCP.pdf
+Inductor Radial series Radial pin pitch 5.00mm  diameter 8.7mm Fastron 07HCP
+0
+2
+2
+Inductor_THT
+L_Radial_D9.5mm_P5.00mm_Fastron_07HVP
+Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=9.5mm, Fastron, 07HVP, http://www.fastrongroup.com/image-show/107/07HVP%2007HVP_T.pdf?type=Complete-DataSheet&productType=series
+Inductor Radial series Radial pin pitch 5.00mm  diameter 9.5mm Fastron 07HVP
+0
+2
+2
+Inductor_THT
+L_Radial_D10.0mm_P5.00mm_Fastron_07M
+Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=10mm, Fastron, 07M, http://www.fastrongroup.com/image-show/37/07M.pdf?type=Complete-DataSheet&productType=series
+Inductor Radial series Radial pin pitch 5.00mm  diameter 10mm Fastron 07M
+0
+2
+2
+Inductor_THT
+L_Radial_D10.0mm_P5.00mm_Fastron_07P
+Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=10mm, Fastron, 07P, http://www.fastrongroup.com/image-show/37/07M.pdf?type=Complete-DataSheet&productType=series
+Inductor Radial series Radial pin pitch 5.00mm  diameter 10mm Fastron 07P
+0
+2
+2
+Inductor_THT
+L_Radial_D10.0mm_P5.00mm_Neosid_SD12_style3
+Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=10.0mm, Neosid, SD12, style3, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd12.pdf
+Inductor Radial series Radial pin pitch 5.00mm  diameter 10.0mm Neosid SD12 style3
+0
+2
+2
+Inductor_THT
+L_Radial_D10.0mm_P5.00mm_Neosid_SD12k_style3
+Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=10.0mm, Neosid, SD12k, style3, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd12k.pdf
+Inductor Radial series Radial pin pitch 5.00mm  diameter 10.0mm Neosid SD12k style3
+0
+2
+2
+Inductor_THT
+L_Radial_D10.5mm_P4.00x5.00mm_Murata_1200RS
+Inductor, Radial, Pitch=4.00x5.00mm, Diameter=10.5mm, Murata 1200RS, http://www.murata-ps.com/data/magnetics/kmp_1200rs.pdf
+Inductor Radial Murata 1200RS
+0
+4
+2
+Inductor_THT
+L_Radial_D10.5mm_P5.00mm_Abacron_AISR-01
+Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=10.5mm, Abacron, AISR-01, http://www.abracon.com/Magnetics/radial/AISR-01.pdf
+Inductor Radial series Radial pin pitch 5.00mm  diameter 10.5mm Abacron AISR-01
+0
+2
+2
+Inductor_THT
+L_Radial_D12.0mm_P5.00mm_Fastron_11P
+Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=12.0mm, Fastron, 11P, http://cdn-reichelt.de/documents/datenblatt/B400/DS_11P.pdf
+Inductor Radial series Radial pin pitch 5.00mm  diameter 12.0mm Fastron 11P
+0
+2
+2
+Inductor_THT
+L_Radial_D12.0mm_P5.00mm_Neosid_SD12_style2
+Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=12.0mm, Neosid, SD12, style2, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd12.pdf
+Inductor Radial series Radial pin pitch 5.00mm  diameter 12.0mm Neosid SD12 style2
+0
+2
+2
+Inductor_THT
+L_Radial_D12.0mm_P5.00mm_Neosid_SD12k_style2
+Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=12.0mm, Neosid, SD12k, style2, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd12k.pdf
+Inductor Radial series Radial pin pitch 5.00mm  diameter 12.0mm Neosid SD12k style2
+0
+2
+2
+Inductor_THT
+L_Radial_D12.0mm_P6.00mm_MuRATA_1900R
+Inductor, Radial series, Radial, pin pitch=6.00mm, , diameter=12.0mm, MuRATA, 1900R, http://www.murata-ps.com/data/magnetics/kmp_1900r.pdf
+Inductor Radial series Radial pin pitch 6.00mm  diameter 12.0mm MuRATA 1900R
+0
+2
+2
+Inductor_THT
+L_Radial_D12.0mm_P10.00mm_Neosid_SD12_style1
+Inductor, Radial series, Radial, pin pitch=10.00mm, , diameter=12.0mm, Neosid, SD12, style1, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd12.pdf
+Inductor Radial series Radial pin pitch 10.00mm  diameter 12.0mm Neosid SD12 style1
+0
+2
+2
+Inductor_THT
+L_Radial_D12.0mm_P10.00mm_Neosid_SD12k_style1
+Inductor, Radial series, Radial, pin pitch=10.00mm, , diameter=12.0mm, Neosid, SD12k, style1, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd12k.pdf
+Inductor Radial series Radial pin pitch 10.00mm  diameter 12.0mm Neosid SD12k style1
+0
+2
+2
+Inductor_THT
+L_Radial_D12.5mm_P7.00mm_Fastron_09HCP
+Inductor, Radial series, Radial, pin pitch=7.00mm, , diameter=12.5mm, Fastron, 09HCP, http://cdn-reichelt.de/documents/datenblatt/B400/DS_09HCP.pdf
+Inductor Radial series Radial pin pitch 7.00mm  diameter 12.5mm Fastron 09HCP
+0
+2
+2
+Inductor_THT
+L_Radial_D12.5mm_P9.00mm_Fastron_09HCP
+Inductor, Radial series, Radial, pin pitch=9.00mm, , diameter=12.5mm, Fastron, 09HCP, http://cdn-reichelt.de/documents/datenblatt/B400/DS_09HCP.pdf
+Inductor Radial series Radial pin pitch 9.00mm  diameter 12.5mm Fastron 09HCP
+0
+2
+2
+Inductor_THT
+L_Radial_D13.5mm_P7.00mm_Fastron_09HCP
+Inductor, Radial series, Radial, pin pitch=7.00mm, , diameter=13.5mm, Fastron, 09HCP, http://cdn-reichelt.de/documents/datenblatt/B400/DS_09HCP.pdf
+Inductor Radial series Radial pin pitch 7.00mm  diameter 13.5mm Fastron 09HCP
+0
+2
+2
+Inductor_THT
+L_Radial_D14.2mm_P10.00mm_Neosid_SD14
+Inductor, Radial series, Radial, pin pitch=10.00mm, , diameter=14.2mm, Neosid, SD14, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd14.pdf
+Inductor Radial series Radial pin pitch 10.00mm  diameter 14.2mm Neosid SD14
+0
+2
+2
+Inductor_THT
+L_Radial_D16.8mm_P11.43mm_Vishay_IHB-1
+Inductor, Radial series, Radial, pin pitch=11.43mm, , diameter=16.8mm, Vishay, IHB-1, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 11.43mm  diameter 16.8mm Vishay IHB-1
+0
+2
+2
+Inductor_THT
+L_Radial_D16.8mm_P12.07mm_Vishay_IHB-1
+Inductor, Radial series, Radial, pin pitch=12.07mm, , diameter=16.8mm, Vishay, IHB-1, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 12.07mm  diameter 16.8mm Vishay IHB-1
+0
+2
+2
+Inductor_THT
+L_Radial_D16.8mm_P12.70mm_Vishay_IHB-1
+Inductor, Radial series, Radial, pin pitch=12.70mm, , diameter=16.8mm, Vishay, IHB-1, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 12.70mm  diameter 16.8mm Vishay IHB-1
+0
+2
+2
+Inductor_THT
+L_Radial_D18.0mm_P10.00mm
+Inductor, Radial series, Radial, pin pitch=10.00mm, , diameter=18mm, http://www.abracon.com/Magnetics/radial/AIUR-15.pdf
+Inductor Radial series Radial pin pitch 10.00mm  diameter 18mm
+0
+2
+2
+Inductor_THT
+L_Radial_D21.0mm_P14.61mm_Vishay_IHB-2
+Inductor, Radial series, Radial, pin pitch=14.61mm, , diameter=21mm, Vishay, IHB-2, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 14.61mm  diameter 21mm Vishay IHB-2
+0
+2
+2
+Inductor_THT
+L_Radial_D21.0mm_P15.00mm_Vishay_IHB-2
+Inductor, Radial series, Radial, pin pitch=15.00mm, , diameter=21mm, Vishay, IHB-2, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 15.00mm  diameter 21mm Vishay IHB-2
+0
+2
+2
+Inductor_THT
+L_Radial_D21.0mm_P15.24mm_Vishay_IHB-2
+Inductor, Radial series, Radial, pin pitch=15.24mm, , diameter=21mm, Vishay, IHB-2, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 15.24mm  diameter 21mm Vishay IHB-2
+0
+2
+2
+Inductor_THT
+L_Radial_D21.0mm_P15.75mm_Vishay_IHB-2
+Inductor, Radial series, Radial, pin pitch=15.75mm, , diameter=21mm, Vishay, IHB-2, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 15.75mm  diameter 21mm Vishay IHB-2
+0
+2
+2
+Inductor_THT
+L_Radial_D21.0mm_P19.00mm
+Inductor, Radial series, Radial, pin pitch=19.00mm, , diameter=21mm, http://www.abracon.com/Magnetics/radial/AIRD02.pdf
+Inductor Radial series Radial pin pitch 19.00mm  diameter 21mm
+0
+2
+2
+Inductor_THT
+L_Radial_D24.0mm_P24.00mm
+Inductor, Radial series, Radial, pin pitch=24.00mm, , diameter=24mm
+Inductor Radial series Radial pin pitch 24.00mm  diameter 24mm
+0
+2
+2
+Inductor_THT
+L_Radial_D24.4mm_P22.90mm_muRATA_1400series
+Inductor, Radial series, Radial, pin pitch=22.90mm, , diameter=24.4mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf
+Inductor Radial series Radial pin pitch 22.90mm  diameter 24.4mm muRATA 1400series
+0
+2
+2
+Inductor_THT
+L_Radial_D24.4mm_P23.10mm_muRATA_1400series
+Inductor, Radial series, Radial, pin pitch=23.10mm, , diameter=24.4mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf
+Inductor Radial series Radial pin pitch 23.10mm  diameter 24.4mm muRATA 1400series
+0
+2
+2
+Inductor_THT
+L_Radial_D24.4mm_P23.40mm_muRATA_1400series
+Inductor, Radial series, Radial, pin pitch=23.40mm, , diameter=24.4mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf
+Inductor Radial series Radial pin pitch 23.40mm  diameter 24.4mm muRATA 1400series
+0
+2
+2
+Inductor_THT
+L_Radial_D24.4mm_P23.70mm_muRATA_1400series
+Inductor, Radial series, Radial, pin pitch=23.70mm, , diameter=24.4mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf
+Inductor Radial series Radial pin pitch 23.70mm  diameter 24.4mm muRATA 1400series
+0
+2
+2
+Inductor_THT
+L_Radial_D24.4mm_P23.90mm_muRATA_1400series
+Inductor, Radial series, Radial, pin pitch=23.90mm, , diameter=24.4mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf
+Inductor Radial series Radial pin pitch 23.90mm  diameter 24.4mm muRATA 1400series
+0
+2
+2
+Inductor_THT
+L_Radial_D27.9mm_P18.29mm_Vishay_IHB-3
+Inductor, Radial series, Radial, pin pitch=18.29mm, , diameter=27.9mm, Vishay, IHB-3, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 18.29mm  diameter 27.9mm Vishay IHB-3
+0
+2
+2
+Inductor_THT
+L_Radial_D27.9mm_P19.05mm_Vishay_IHB-3
+Inductor, Radial series, Radial, pin pitch=19.05mm, , diameter=27.9mm, Vishay, IHB-3, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 19.05mm  diameter 27.9mm Vishay IHB-3
+0
+2
+2
+Inductor_THT
+L_Radial_D27.9mm_P20.07mm_Vishay_IHB-3
+Inductor, Radial series, Radial, pin pitch=20.07mm, , diameter=27.9mm, Vishay, IHB-3, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 20.07mm  diameter 27.9mm Vishay IHB-3
+0
+2
+2
+Inductor_THT
+L_Radial_D28.0mm_P29.20mm
+Inductor, Radial series, Radial, pin pitch=29.20mm, , diameter=28mm
+Inductor Radial series Radial pin pitch 29.20mm  diameter 28mm
+0
+2
+2
+Inductor_THT
+L_Radial_D29.8mm_P28.30mm_muRATA_1400series
+Inductor, Radial series, Radial, pin pitch=28.30mm, , diameter=29.8mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf
+Inductor Radial series Radial pin pitch 28.30mm  diameter 29.8mm muRATA 1400series
+0
+2
+2
+Inductor_THT
+L_Radial_D29.8mm_P28.50mm_muRATA_1400series
+Inductor, Radial series, Radial, pin pitch=28.50mm, , diameter=29.8mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf
+Inductor Radial series Radial pin pitch 28.50mm  diameter 29.8mm muRATA 1400series
+0
+2
+2
+Inductor_THT
+L_Radial_D29.8mm_P28.80mm_muRATA_1400series
+Inductor, Radial series, Radial, pin pitch=28.80mm, , diameter=29.8mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf
+Inductor Radial series Radial pin pitch 28.80mm  diameter 29.8mm muRATA 1400series
+0
+2
+2
+Inductor_THT
+L_Radial_D29.8mm_P29.00mm_muRATA_1400series
+Inductor, Radial series, Radial, pin pitch=29.00mm, , diameter=29.8mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf
+Inductor Radial series Radial pin pitch 29.00mm  diameter 29.8mm muRATA 1400series
+0
+2
+2
+Inductor_THT
+L_Radial_D29.8mm_P29.30mm_muRATA_1400series
+Inductor, Radial series, Radial, pin pitch=29.30mm, , diameter=29.8mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf
+Inductor Radial series Radial pin pitch 29.30mm  diameter 29.8mm muRATA 1400series
+0
+2
+2
+Inductor_THT
+L_Radial_D40.6mm_P26.16mm_Vishay_IHB-5
+Inductor, Radial series, Radial, pin pitch=26.16mm, , diameter=40.64mm, Vishay, IHB-5, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 26.16mm  diameter 40.64mm Vishay IHB-5
+0
+2
+2
+Inductor_THT
+L_Radial_D40.6mm_P27.18mm_Vishay_IHB-4
+Inductor, Radial series, Radial, pin pitch=27.18mm, , diameter=40.64mm, Vishay, IHB-4, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 27.18mm  diameter 40.64mm Vishay IHB-4
+0
+2
+2
+Inductor_THT
+L_Radial_D40.6mm_P27.94mm_Vishay_IHB-4
+Inductor, Radial series, Radial, pin pitch=27.94mm, , diameter=40.64mm, Vishay, IHB-4, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 27.94mm  diameter 40.64mm Vishay IHB-4
+0
+2
+2
+Inductor_THT
+L_Radial_D40.6mm_P27.94mm_Vishay_IHB-5
+Inductor, Radial series, Radial, pin pitch=27.94mm, , diameter=40.64mm, Vishay, IHB-5, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 27.94mm  diameter 40.64mm Vishay IHB-5
+0
+2
+2
+Inductor_THT
+L_Radial_D40.6mm_P28.70mm_Vishay_IHB-5
+Inductor, Radial series, Radial, pin pitch=28.70mm, , diameter=40.64mm, Vishay, IHB-5, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 28.70mm  diameter 40.64mm Vishay IHB-5
+0
+2
+2
+Inductor_THT
+L_Radial_D50.8mm_P33.27mm_Vishay_IHB-6
+Inductor, Radial series, Radial, pin pitch=33.27mm, , diameter=50.8mm, Vishay, IHB-6, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 33.27mm  diameter 50.8mm Vishay IHB-6
+0
+2
+2
+Inductor_THT
+L_Radial_D50.8mm_P34.29mm_Vishay_IHB-6
+Inductor, Radial series, Radial, pin pitch=34.29mm, , diameter=50.8mm, Vishay, IHB-6, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 34.29mm  diameter 50.8mm Vishay IHB-6
+0
+2
+2
+Inductor_THT
+L_Radial_D50.8mm_P35.81mm_Vishay_IHB-6
+Inductor, Radial series, Radial, pin pitch=35.81mm, , diameter=50.8mm, Vishay, IHB-6, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 35.81mm  diameter 50.8mm Vishay IHB-6
+0
+2
+2
+Inductor_THT
+L_Radial_D50.8mm_P36.32mm_Vishay_IHB-6
+Inductor, Radial series, Radial, pin pitch=36.32mm, , diameter=50.8mm, Vishay, IHB-6, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 36.32mm  diameter 50.8mm Vishay IHB-6
+0
+2
+2
+Inductor_THT
+L_Radial_D50.8mm_P38.86mm_Vishay_IHB-6
+Inductor, Radial series, Radial, pin pitch=38.86mm, , diameter=50.8mm, Vishay, IHB-6, http://www.vishay.com/docs/34015/ihb.pdf
+Inductor Radial series Radial pin pitch 38.86mm  diameter 50.8mm Vishay IHB-6
+0
+2
+2
+Inductor_THT
+L_Radial_L7.5mm_W4.6mm_P5.00mm_Neosid_SD75
+Inductor, Radial series, Radial, pin pitch=5.00mm, , length*width=7.5*4.6mm^2, Neosid, SD75, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd75.pdf
+Inductor Radial series Radial pin pitch 5.00mm  length 7.5mm width 4.6mm Neosid SD75
+0
+2
+2
+Inductor_THT
+L_Radial_L8.0mm_W8.0mm_P5.00mm_Neosid_NE-CPB-07E
+Inductor, Radial series, Radial, pin pitch=5.00mm, , length*width=8*8mm^2, Neosid, NE-CPB-07E, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_NE_CPB07E.pdf
+Inductor Radial series Radial pin pitch 5.00mm  length 8mm width 8mm Neosid NE-CPB-07E
+0
+2
+2
+Inductor_THT
+L_Radial_L8.0mm_W8.0mm_P5.00mm_Neosid_SD8
+Inductor, Radial series, Radial, pin pitch=5.00mm, , length*width=8*8mm^2, Neosid, SD8, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd8.pdf
+Inductor Radial series Radial pin pitch 5.00mm  length 8mm width 8mm Neosid SD8
+0
+2
+2
+Inductor_THT
+L_Radial_L9.1mm_W9.1mm_Px6.35mm_Py6.35mm_Pulse_LP-25
+Inductor, Radial series, Radial, pin pitch=6.35*6.35mm^2, , length*width=9.14*9.14mm^2, Pulse, LP-25, http://datasheet.octopart.com/PE-54044NL-Pulse-datasheet-5313493.pdf
+Inductor Radial series Radial pin pitch 6.35*6.35mm^2  length 9.14mm width 9.14mm Pulse LP-25
+0
+2
+2
+Inductor_THT
+L_Radial_L10.2mm_W10.2mm_Px7.62mm_Py7.62mm_Pulse_LP-30
+Inductor, Radial series, Radial, pin pitch=7.62*7.62mm^2, , length*width=10.16*10.16mm^2, Pulse, LP-30, http://datasheet.octopart.com/PE-54044NL-Pulse-datasheet-5313493.pdf
+Inductor Radial series Radial pin pitch 7.62*7.62mm^2  length 10.16mm width 10.16mm Pulse LP-30
+0
+2
+2
+Inductor_THT
+L_Radial_L11.5mm_W11.5mm_Px6.00mm_Py6.00mm_Neosid_NE-CPB-11EN_Drill1.3mm
+Inductor, Radial series, Radial, pin pitch=6.00*6.00mm^2, , length*width=11.5*11.5mm^2, Neosid, NE-CPB-11EN, Drill1.3mm, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_NE_CPB11EN.pdf
+Inductor Radial series Radial pin pitch 6.00*6.00mm^2  length 11.5mm width 11.5mm Neosid NE-CPB-11EN Drill1.3mm
+0
+2
+2
+Inductor_THT
+L_Radial_L11.5mm_W11.5mm_Px6.00mm_Py6.00mm_Neosid_NE-CPB-11EN_Drill1.5mm
+Inductor, Radial series, Radial, pin pitch=6.00*6.00mm^2, , length*width=11.5*11.5mm^2, Neosid, NE-CPB-11EN, Drill1.5mm, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_NE_CPB11EN.pdf
+Inductor Radial series Radial pin pitch 6.00*6.00mm^2  length 11.5mm width 11.5mm Neosid NE-CPB-11EN Drill1.5mm
+0
+2
+2
+Inductor_THT
+L_Radial_L11.5mm_W11.5mm_Px6.00mm_Py6.00mm_Neosid_NE-CPB-11EN_Drill1.7mm
+Inductor, Radial series, Radial, pin pitch=6.00*6.00mm^2, , length*width=11.5*11.5mm^2, Neosid, NE-CPB-11EN, Drill1.7mm, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_NE_CPB11EN.pdf
+Inductor Radial series Radial pin pitch 6.00*6.00mm^2  length 11.5mm width 11.5mm Neosid NE-CPB-11EN Drill1.7mm
+0
+2
+2
+Inductor_THT
+L_Radial_L11.5mm_W11.5mm_Px6.00mm_Py6.00mm_Neosid_NE-CPB-11EN_Drill1.8mm
+Inductor, Radial series, Radial, pin pitch=6.00*6.00mm^2, , length*width=11.5*11.5mm^2, Neosid, NE-CPB-11EN, Drill1.8mm, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_NE_CPB11EN.pdf
+Inductor Radial series Radial pin pitch 6.00*6.00mm^2  length 11.5mm width 11.5mm Neosid NE-CPB-11EN Drill1.8mm
+0
+2
+2
+Inductor_THT
+L_Radial_L12.6mm_W12.6mm_Px9.52mm_Py9.52mm_Pulse_LP-37
+Inductor, Radial series, Radial, pin pitch=9.52*9.52mm^2, , length*width=12.57*12.57mm^2, Pulse, LP-37, http://datasheet.octopart.com/PE-54044NL-Pulse-datasheet-5313493.pdf
+Inductor Radial series Radial pin pitch 9.52*9.52mm^2  length 12.57mm width 12.57mm Pulse LP-37
+0
+2
+2
+Inductor_THT
+L_Radial_L16.1mm_W16.1mm_Px7.62mm_Py12.70mm_Pulse_LP-44
+Inductor, Radial series, Radial, pin pitch=7.62*12.70mm^2, , length*width=16.13*16.13mm^2, Pulse, LP-44, http://datasheet.octopart.com/PE-54044NL-Pulse-datasheet-5313493.pdf
+Inductor Radial series Radial pin pitch 7.62*12.70mm^2  length 16.13mm width 16.13mm Pulse LP-44
+0
+2
+2
+Inductor_THT
+L_SELF1408
+Self Ferrite 14 - 08
+SELF
+0
+7
+3
+Inductor_THT
+L_SELF1418
+Self Ferrite 14 - 18
+SELF
+0
+10
+4
+Inductor_THT
+L_Toroid_Horizontal_D3.2mm_P6.40mm_Diameter3-5mm_Amidon-T12
+L_Toroid, Horizontal series, Radial, pin pitch=6.40mm, , diameter=3.175mm, Diameter3-5mm, Amidon-T12
+L_Toroid Horizontal series Radial pin pitch 6.40mm  diameter 3.175mm Diameter3-5mm Amidon-T12
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D4.1mm_P8.00mm_Diameter4-5mm_Amidon-T16
+L_Toroid, Horizontal series, Radial, pin pitch=8.00mm, , diameter=4.064mm, Diameter4-5mm, Amidon-T16
+L_Toroid Horizontal series Radial pin pitch 8.00mm  diameter 4.064mm Diameter4-5mm Amidon-T16
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D5.1mm_P9.00mm_Diameter6-5mm_Amidon-T20
+L_Toroid, Horizontal series, Radial, pin pitch=9.00mm, , diameter=5.08mm, Diameter6-5mm, Amidon-T20
+L_Toroid Horizontal series Radial pin pitch 9.00mm  diameter 5.08mm Diameter6-5mm Amidon-T20
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D6.5mm_P10.00mm_Diameter7-5mm_Amidon-T25
+L_Toroid, Horizontal series, Radial, pin pitch=10.00mm, , diameter=6.476999999999999mm, Diameter7-5mm, Amidon-T25
+L_Toroid Horizontal series Radial pin pitch 10.00mm  diameter 6.476999999999999mm Diameter7-5mm Amidon-T25
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D7.8mm_P13.00mm_Diameter9-5mm_Amidon-T30
+L_Toroid, Horizontal series, Radial, pin pitch=13.00mm, , diameter=7.7978mm, Diameter9-5mm, Amidon-T30
+L_Toroid Horizontal series Radial pin pitch 13.00mm  diameter 7.7978mm Diameter9-5mm Amidon-T30
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D9.5mm_P15.00mm_Diameter10-5mm_Amidon-T37
+L_Toroid, Horizontal series, Radial, pin pitch=15.00mm, , diameter=9.524999999999999mm, Diameter10-5mm, Amidon-T37
+L_Toroid Horizontal series Radial pin pitch 15.00mm  diameter 9.524999999999999mm Diameter10-5mm Amidon-T37
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D11.2mm_P17.00mm_Diameter12-5mm_Amidon-T44
+L_Toroid, Horizontal series, Radial, pin pitch=17.00mm, , diameter=11.176mm, Diameter12-5mm, Amidon-T44
+L_Toroid Horizontal series Radial pin pitch 17.00mm  diameter 11.176mm Diameter12-5mm Amidon-T44
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D12.7mm_P20.00mm_Diameter14-5mm_Amidon-T50
+L_Toroid, Horizontal series, Radial, pin pitch=20.00mm, , diameter=12.7mm, Diameter14-5mm, Amidon-T50
+L_Toroid Horizontal series Radial pin pitch 20.00mm  diameter 12.7mm Diameter14-5mm Amidon-T50
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D16.8mm_P14.70mm_Vishay_TJ3
+L_Toroid, Horizontal series, Radial, pin pitch=14.70mm, , diameter=16.8mm, Vishay, TJ3, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Horizontal series Radial pin pitch 14.70mm  diameter 16.8mm Vishay TJ3
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D16.8mm_P14.70mm_Vishay_TJ3_BigPads
+L_Toroid, Horizontal series, Radial, pin pitch=14.70mm, , diameter=16.8mm, Vishay, TJ3, BigPads, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Horizontal series Radial pin pitch 14.70mm  diameter 16.8mm Vishay TJ3 BigPads
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D17.3mm_P15.24mm_Bourns_2000
+L_Toroid, Horizontal series, Radial, pin pitch=15.24mm, , diameter=17.3mm, Bourns, 2000, http://www.bourns.com/docs/Product-Datasheets/2000_series.pdf?sfvrsn=5
+L_Toroid Horizontal series Radial pin pitch 15.24mm  diameter 17.3mm Bourns 2000
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D21.8mm_P19.10mm_Bourns_2100
+L_Toroid, Horizontal series, Radial, pin pitch=19.10mm, , diameter=21.8mm, Bourns, 2100, http://www.bourns.com/docs/Product-Datasheets/2100_series.pdf?sfvrsn=3
+L_Toroid Horizontal series Radial pin pitch 19.10mm  diameter 21.8mm Bourns 2100
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D21.8mm_P19.60mm_Bourns_2100
+L_Toroid, Horizontal series, Radial, pin pitch=19.60mm, , diameter=21.8mm, Bourns, 2100, http://www.bourns.com/docs/Product-Datasheets/2100_series.pdf?sfvrsn=3
+L_Toroid Horizontal series Radial pin pitch 19.60mm  diameter 21.8mm Bourns 2100
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D22.4mm_P19.80mm_Vishay_TJ4
+L_Toroid, Horizontal series, Radial, pin pitch=19.80mm, , diameter=22.4mm, Vishay, TJ4, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Horizontal series Radial pin pitch 19.80mm  diameter 22.4mm Vishay TJ4
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D24.1mm_P21.80mm_Bourns_2200
+L_Toroid, Horizontal series, Radial, pin pitch=21.80mm, , diameter=24.1mm, Bourns, 2200, http://www.bourns.com/docs/Product-Datasheets/2100_series.pdf?sfvrsn=3
+L_Toroid Horizontal series Radial pin pitch 21.80mm  diameter 24.1mm Bourns 2200
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D24.1mm_P23.10mm_Bourns_2200
+L_Toroid, Horizontal series, Radial, pin pitch=23.10mm, , diameter=24.1mm, Bourns, 2200, http://www.bourns.com/docs/Product-Datasheets/2100_series.pdf?sfvrsn=3
+L_Toroid Horizontal series Radial pin pitch 23.10mm  diameter 24.1mm Bourns 2200
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D25.4mm_P22.90mm_Vishay_TJ5
+L_Toroid, Horizontal series, Radial, pin pitch=22.90mm, , diameter=25.4mm, Vishay, TJ5, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Horizontal series Radial pin pitch 22.90mm  diameter 25.4mm Vishay TJ5
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D25.4mm_P22.90mm_Vishay_TJ5_BigPads
+L_Toroid, Horizontal series, Radial, pin pitch=22.90mm, , diameter=25.4mm, Vishay, TJ5, BigPads, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Horizontal series Radial pin pitch 22.90mm  diameter 25.4mm Vishay TJ5 BigPads
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D26.0mm_P5.08mm
+inductor 26mm diameter toroid
+SELF INDUCTOR
+0
+3
+2
+Inductor_THT
+L_Toroid_Horizontal_D28.0mm_P25.10mm_Bourns_2200
+L_Toroid, Horizontal series, Radial, pin pitch=25.10mm, , diameter=28mm, Bourns, 2200, http://www.bourns.com/docs/Product-Datasheets/2100_series.pdf?sfvrsn=3
+L_Toroid Horizontal series Radial pin pitch 25.10mm  diameter 28mm Bourns 2200
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D28.0mm_P26.67mm_Bourns_2200
+L_Toroid, Horizontal series, Radial, pin pitch=26.67mm, , diameter=28mm, Bourns, 2200, http://www.bourns.com/docs/Product-Datasheets/2100_series.pdf?sfvrsn=3
+L_Toroid Horizontal series Radial pin pitch 26.67mm  diameter 28mm Bourns 2200
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D32.5mm_P28.90mm_Bourns_2300
+L_Toroid, Horizontal series, Radial, pin pitch=28.90mm, , diameter=32.5mm, Bourns, 2300, http://www.bourns.com/docs/Product-Datasheets/2300_series.pdf?sfvrsn=3
+L_Toroid Horizontal series Radial pin pitch 28.90mm  diameter 32.5mm Bourns 2300
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D32.5mm_P30.00mm_Bourns_2300
+L_Toroid, Horizontal series, Radial, pin pitch=30.00mm, , diameter=32.5mm, Bourns, 2300, http://www.bourns.com/docs/Product-Datasheets/2300_series.pdf?sfvrsn=3
+L_Toroid Horizontal series Radial pin pitch 30.00mm  diameter 32.5mm Bourns 2300
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D35.1mm_P31.00mm_Vishay_TJ6
+L_Toroid, Horizontal series, Radial, pin pitch=31.00mm, , diameter=35.1mm, Vishay, TJ6, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Horizontal series Radial pin pitch 31.00mm  diameter 35.1mm Vishay TJ6
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D40.0mm_P48.26mm
+L_Toroid, Horizontal series, Radial, pin pitch=48.26mm, , diameter=40mm
+L_Toroid Horizontal series Radial pin pitch 48.26mm  diameter 40mm
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D41.9mm_P37.60mm_Vishay_TJ7
+L_Toroid, Horizontal series, Radial, pin pitch=37.60mm, , diameter=41.9mm, Vishay, TJ7, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Horizontal series Radial pin pitch 37.60mm  diameter 41.9mm Vishay TJ7
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D49.3mm_P44.60mm_Vishay_TJ8
+L_Toroid, Horizontal series, Radial, pin pitch=44.60mm, , diameter=49.3mm, Vishay, TJ8, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Horizontal series Radial pin pitch 44.60mm  diameter 49.3mm Vishay TJ8
+0
+2
+2
+Inductor_THT
+L_Toroid_Horizontal_D69.1mm_P63.20mm_Vishay_TJ9
+L_Toroid, Horizontal series, Radial, pin pitch=63.20mm, , diameter=69.1mm, Vishay, TJ9, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Horizontal series Radial pin pitch 63.20mm  diameter 69.1mm Vishay TJ9
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L10.0mm_W5.0mm_P5.08mm
+L_Toroid, Vertical series, Radial, pin pitch=5.08mm, , length*width=10*5mm^2
+L_Toroid Vertical series Radial pin pitch 5.08mm  length 10mm width 5mm
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L13.0mm_W6.5mm_P5.60mm
+L_Toroid, Vertical series, Radial, pin pitch=5.60mm, , length*width=13*6.5mm^2
+L_Toroid Vertical series Radial pin pitch 5.60mm  length 13mm width 6.5mm
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L14.0mm_W5.6mm_P5.30mm_Bourns_5700
+L_Toroid, Vertical series, Radial, pin pitch=5.30mm, , length*width=14*5.6mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf
+L_Toroid Vertical series Radial pin pitch 5.30mm  length 14mm width 5.6mm Bourns 5700
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L14.0mm_W6.3mm_P4.57mm_Pulse_A
+L_Toroid, Vertical series, Radial, pin pitch=4.57mm, , length*width=13.97*6.35mm^2, Pulse, A, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf
+L_Toroid Vertical series Radial pin pitch 4.57mm  length 13.97mm width 6.35mm Pulse A
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L14.7mm_W8.6mm_P5.58mm_Pulse_KM-1
+L_Toroid, Vertical series, Radial, pin pitch=5.58mm, , length*width=14.73*8.64mm^2, Pulse, KM-1, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf
+L_Toroid Vertical series Radial pin pitch 5.58mm  length 14.73mm width 8.64mm Pulse KM-1
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L16.0mm_W8.0mm_P7.62mm
+L_Toroid, Vertical series, Radial, pin pitch=7.62mm, , length*width=16*8mm^2
+L_Toroid Vertical series Radial pin pitch 7.62mm  length 16mm width 8mm
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L16.3mm_W7.1mm_P7.11mm_Pulse_H
+L_Toroid, Vertical series, Radial, pin pitch=7.11mm, , length*width=16.26*7.11mm^2, Pulse, H, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf
+L_Toroid Vertical series Radial pin pitch 7.11mm  length 16.26mm width 7.11mm Pulse H
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L16.4mm_W7.6mm_P6.60mm_Vishay_TJ3
+L_Toroid, Vertical series, Radial, pin pitch=6.60mm, , length*width=16.4*7.6mm^2, Vishay, TJ3, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Vertical series Radial pin pitch 6.60mm  length 16.4mm width 7.6mm Vishay TJ3
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L16.5mm_W11.4mm_P7.62mm_Pulse_KM-2
+L_Toroid, Vertical series, Radial, pin pitch=7.62mm, , length*width=16.51*11.43mm^2, Pulse, KM-2, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf
+L_Toroid Vertical series Radial pin pitch 7.62mm  length 16.51mm width 11.43mm Pulse KM-2
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L16.8mm_W9.2mm_P7.10mm_Vishay_TJ3
+L_Toroid, Vertical series, Radial, pin pitch=7.10mm, , length*width=16.8*9.2mm^2, Vishay, TJ3, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Vertical series Radial pin pitch 7.10mm  length 16.8mm width 9.2mm Vishay TJ3
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L16.8mm_W9.2mm_P7.10mm_Vishay_TJ3_BigPads
+L_Toroid, Vertical series, Radial, pin pitch=7.10mm, , length*width=16.8*9.2mm^2, Vishay, TJ3, BigPads, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Vertical series Radial pin pitch 7.10mm  length 16.8mm width 9.2mm Vishay TJ3 BigPads
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L17.8mm_W8.1mm_P7.62mm_Bourns_5700
+L_Toroid, Vertical series, Radial, pin pitch=7.62mm, , length*width=17.8*8.1mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf
+L_Toroid Vertical series Radial pin pitch 7.62mm  length 17.8mm width 8.1mm Bourns 5700
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L17.8mm_W9.7mm_P7.11mm_Pulse_B
+L_Toroid, Vertical series, Radial, pin pitch=7.11mm, , length*width=17.78*9.65mm^2, Pulse, B, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf
+L_Toroid Vertical series Radial pin pitch 7.11mm  length 17.78mm width 9.65mm Pulse B
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L19.1mm_W8.1mm_P7.10mm_Bourns_5700
+L_Toroid, Vertical series, Radial, pin pitch=7.10mm, , length*width=19.1*8.1mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf
+L_Toroid Vertical series Radial pin pitch 7.10mm  length 19.1mm width 8.1mm Bourns 5700
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L21.6mm_W8.4mm_P8.38mm_Pulse_G
+L_Toroid, Vertical series, Radial, pin pitch=8.38mm, , length*width=21.59*8.38mm^2, Pulse, G, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf
+L_Toroid Vertical series Radial pin pitch 8.38mm  length 21.59mm width 8.38mm Pulse G
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L21.6mm_W9.1mm_P8.40mm_Bourns_5700
+L_Toroid, Vertical series, Radial, pin pitch=8.40mm, , length*width=21.6*9.1mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf
+L_Toroid Vertical series Radial pin pitch 8.40mm  length 21.6mm width 9.1mm Bourns 5700
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L21.6mm_W9.5mm_P7.11mm_Pulse_C
+L_Toroid, Vertical series, Radial, pin pitch=7.11mm, , length*width=21.59*9.53mm^2, Pulse, C, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf
+L_Toroid Vertical series Radial pin pitch 7.11mm  length 21.59mm width 9.53mm Pulse C
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L21.6mm_W11.4mm_P7.62mm_Pulse_KM-3
+L_Toroid, Vertical series, Radial, pin pitch=7.62mm, , length*width=21.59*11.43mm^2, Pulse, KM-3, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf
+L_Toroid Vertical series Radial pin pitch 7.62mm  length 21.59mm width 11.43mm Pulse KM-3
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L22.4mm_W10.2mm_P7.90mm_Vishay_TJ4
+L_Toroid, Vertical series, Radial, pin pitch=7.90mm, , length*width=22.4*10.2mm^2, Vishay, TJ4, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Vertical series Radial pin pitch 7.90mm  length 22.4mm width 10.2mm Vishay TJ4
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L24.6mm_W15.5mm_P11.44mm_Pulse_KM-4
+L_Toroid, Vertical series, Radial, pin pitch=11.44mm, , length*width=24.64*15.5mm^2, Pulse, KM-4, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf
+L_Toroid Vertical series Radial pin pitch 11.44mm  length 24.64mm width 15.5mm Pulse KM-4
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L25.4mm_W14.7mm_P12.20mm_Vishay_TJ5
+L_Toroid, Vertical series, Radial, pin pitch=12.20mm, , length*width=25.4*14.7mm^2, Vishay, TJ5, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Vertical series Radial pin pitch 12.20mm  length 25.4mm width 14.7mm Vishay TJ5
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L25.4mm_W14.7mm_P12.20mm_Vishay_TJ5_BigPads
+L_Toroid, Vertical series, Radial, pin pitch=12.20mm, , length*width=25.4*14.7mm^2, Vishay, TJ5, BigPads, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Vertical series Radial pin pitch 12.20mm  length 25.4mm width 14.7mm Vishay TJ5 BigPads
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L26.7mm_W14.0mm_P10.16mm_Pulse_D
+L_Toroid, Vertical series, Radial, pin pitch=10.16mm, , length*width=26.67*13.97mm^2, Pulse, D, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf
+L_Toroid Vertical series Radial pin pitch 10.16mm  length 26.67mm width 13.97mm Pulse D
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L28.6mm_W14.3mm_P11.43mm_Bourns_5700
+L_Toroid, Vertical series, Radial, pin pitch=11.43mm, , length*width=28.6*14.3mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf
+L_Toroid Vertical series Radial pin pitch 11.43mm  length 28.6mm width 14.3mm Bourns 5700
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L31.8mm_W15.9mm_P13.50mm_Bourns_5700
+L_Toroid, Vertical series, Radial, pin pitch=13.50mm, , length*width=31.8*15.9mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf
+L_Toroid Vertical series Radial pin pitch 13.50mm  length 31.8mm width 15.9mm Bourns 5700
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L33.0mm_W17.8mm_P12.70mm_Pulse_KM-5
+L_Toroid, Vertical series, Radial, pin pitch=12.70mm, , length*width=33.02*17.78mm^2, Pulse, KM-5, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf
+L_Toroid Vertical series Radial pin pitch 12.70mm  length 33.02mm width 17.78mm Pulse KM-5
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L35.1mm_W21.1mm_P18.50mm_Vishay_TJ6
+L_Toroid, Vertical series, Radial, pin pitch=18.50mm, , length*width=35.1*21.1mm^2, Vishay, TJ6, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Vertical series Radial pin pitch 18.50mm  length 35.1mm width 21.1mm Vishay TJ6
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L35.6mm_W17.8mm_P12.70mm_Pulse_E
+L_Toroid, Vertical series, Radial, pin pitch=12.70mm, , length*width=35.56*17.78mm^2, Pulse, E, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf
+L_Toroid Vertical series Radial pin pitch 12.70mm  length 35.56mm width 17.78mm Pulse E
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L41.9mm_W17.8mm_P12.70mm_Pulse_F
+L_Toroid, Vertical series, Radial, pin pitch=12.70mm, , length*width=41.91*17.78mm^2, Pulse, F, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf
+L_Toroid Vertical series Radial pin pitch 12.70mm  length 41.91mm width 17.78mm Pulse F
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L41.9mm_W19.1mm_P15.80mm_Vishay_TJ7
+L_Toroid, Vertical series, Radial, pin pitch=15.80mm, , length*width=41.9*19.1mm^2, Vishay, TJ7, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Vertical series Radial pin pitch 15.80mm  length 41.9mm width 19.1mm Vishay TJ7
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L46.0mm_W19.1mm_P21.80mm_Bourns_5700
+L_Toroid, Vertical series, Radial, pin pitch=21.80mm, , length*width=46*19.1mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf
+L_Toroid Vertical series Radial pin pitch 21.80mm  length 46mm width 19.1mm Bourns 5700
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L48.8mm_W25.4mm_P20.80mm_Vishay_TJ8
+L_Toroid, Vertical series, Radial, pin pitch=20.80mm, , length*width=48.8*25.4mm^2, Vishay, TJ8, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Vertical series Radial pin pitch 20.80mm  length 48.8mm width 25.4mm Vishay TJ8
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L54.0mm_W23.8mm_P20.10mm_Bourns_5700
+L_Toroid, Vertical series, Radial, pin pitch=20.10mm, , length*width=54*23.8mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf
+L_Toroid Vertical series Radial pin pitch 20.10mm  length 54mm width 23.8mm Bourns 5700
+0
+2
+2
+Inductor_THT
+L_Toroid_Vertical_L67.6mm_W36.1mm_P31.80mm_Vishay_TJ9
+L_Toroid, Vertical series, Radial, pin pitch=31.80mm, , length*width=67.6*36.1mm^2, Vishay, TJ9, http://www.vishay.com/docs/34079/tj.pdf
+L_Toroid Vertical series Radial pin pitch 31.80mm  length 67.6mm width 36.1mm Vishay TJ9
+0
+2
+2
+Jumper
+SolderJumper-2_P1.3mm_Bridged2Bar_Pad1.0x1.5mm
+SMD Solder Jumper, 1x1.5mm Pads, 0.3mm gap, bridged with 2 copper strips
+solder jumper open
+0
+2
+2
+Jumper
+SolderJumper-2_P1.3mm_Bridged2Bar_RoundedPad1.0x1.5mm
+SMD Solder Jumper, 1x1.5mm, rounded Pads, 0.3mm gap, bridged with 2 copper strips
+solder jumper open
+0
+2
+2
+Jumper
+SolderJumper-2_P1.3mm_Bridged_Pad1.0x1.5mm
+SMD Solder Jumper, 1x1.5mm Pads, 0.3mm gap, bridged with 1 copper strip
+solder jumper open
+0
+2
+2
+Jumper
+SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm
+SMD Solder Jumper, 1x1.5mm, rounded Pads, 0.3mm gap, bridged with 1 copper strip
+solder jumper open
+0
+2
+2
+Jumper
+SolderJumper-2_P1.3mm_Open_Pad1.0x1.5mm
+SMD Solder Jumper, 1x1.5mm Pads, 0.3mm gap, open
+solder jumper open
+0
+2
+2
+Jumper
+SolderJumper-2_P1.3mm_Open_RoundedPad1.0x1.5mm
+SMD Solder Jumper, 1x1.5mm, rounded Pads, 0.3mm gap, open
+solder jumper open
+0
+2
+2
+Jumper
+SolderJumper-2_P1.3mm_Open_TrianglePad1.0x1.5mm
+SMD Solder Jumper, 1x1.5mm Triangular Pads, 0.3mm gap, open
+solder jumper open
+0
+2
+2
+Jumper
+SolderJumper-3_P1.3mm_Bridged2Bar12_Pad1.0x1.5mm
+SMD Solder 3-pad Jumper, 1x1.5mm Pads, 0.3mm gap, pads 1-2 Bridged2Bar with 2 copper strip
+solder jumper open
+0
+3
+3
+Jumper
+SolderJumper-3_P1.3mm_Bridged2Bar12_Pad1.0x1.5mm_NumberLabels
+SMD Solder Jumper, 1x1.5mm Pads, 0.3mm gap, pads 1-2 Bridged2Bar with 2 copper strip, labeled with numbers
+solder jumper open
+0
+3
+3
+Jumper
+SolderJumper-3_P1.3mm_Bridged2Bar12_RoundedPad1.0x1.5mm
+SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, pads 1-2 Bridged2Bar with 2 copper strip
+solder jumper open
+0
+3
+3
+Jumper
+SolderJumper-3_P1.3mm_Bridged2Bar12_RoundedPad1.0x1.5mm_NumberLabels
+SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, pads 1-2 Bridged2Bar with 2 copper strip, labeled with numbers
+solder jumper open
+0
+3
+3
+Jumper
+SolderJumper-3_P1.3mm_Bridged12_Pad1.0x1.5mm
+SMD Solder 3-pad Jumper, 1x1.5mm Pads, 0.3mm gap, pads 1-2 bridged with 1 copper strip
+solder jumper open
+0
+3
+3
+Jumper
+SolderJumper-3_P1.3mm_Bridged12_Pad1.0x1.5mm_NumberLabels
+SMD Solder Jumper, 1x1.5mm Pads, 0.3mm gap, pads 1-2 bridged with 1 copper strip, labeled with numbers
+solder jumper open
+0
+3
+3
+Jumper
+SolderJumper-3_P1.3mm_Bridged12_RoundedPad1.0x1.5mm
+SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, pads 1-2 bridged with 1 copper strip
+solder jumper open
+0
+3
+3
+Jumper
+SolderJumper-3_P1.3mm_Bridged12_RoundedPad1.0x1.5mm_NumberLabels
+SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, pads 1-2 bridged with 1 copper strip, labeled with numbers
+solder jumper open
+0
+3
+3
+Jumper
+SolderJumper-3_P1.3mm_Open_Pad1.0x1.5mm
+SMD Solder 3-pad Jumper, 1x1.5mm Pads, 0.3mm gap, open
+solder jumper open
+0
+3
+3
+Jumper
+SolderJumper-3_P1.3mm_Open_Pad1.0x1.5mm_NumberLabels
+SMD Solder Jumper, 1x1.5mm Pads, 0.3mm gap, open, labeled with numbers
+solder jumper open
+0
+3
+3
+Jumper
+SolderJumper-3_P1.3mm_Open_RoundedPad1.0x1.5mm
+SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, open
+solder jumper open
+0
+3
+3
+Jumper
+SolderJumper-3_P1.3mm_Open_RoundedPad1.0x1.5mm_NumberLabels
+SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, open, labeled with numbers
+solder jumper open
+0
+3
+3
+Jumper
+SolderJumper-3_P2.0mm_Open_TrianglePad1.0x1.5mm
+SMD Solder Jumper, 1x1.5mm Triangular Pads, 0.3mm gap, open
+solder jumper open
+0
+5
+3
+Jumper
+SolderJumper-3_P2.0mm_Open_TrianglePad1.0x1.5mm_NumberLabels
+SMD Solder Jumper, 1x1.5mm Triangular Pads, 0.3mm gap, open, labeled with numbers
+solder jumper open
+0
+5
+3
+LED_SMD
+LED-APA102-2020
+http://www.led-color.com/upload/201604/APA102-2020%20SMD%20LED.pdf
+LED RGB SPI
+0
+8
+6
+LED_SMD
+LED-L1T2_LUMILEDS
+http://www.lumileds.com/uploads/438/DS133-pdf
+LUMILEDS LUXEON TX L1T2 LED
+0
+3
+3
+LED_SMD
+LED_1W_3W_R8
+https://www.gme.cz/data/attachments/dsh.518-234.1.pdf
+LED 1W 3W 5W
+0
+3
+3
+LED_SMD
+LED_0201_0603Metric
+LED SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator
+LED
+0
+4
+2
+LED_SMD
+LED_0402_1005Metric
+LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+LED
+0
+2
+2
+LED_SMD
+LED_0603_1608Metric
+LED SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+LED_SMD
+LED_0603_1608Metric_Castellated
+LED SMD 0603 (1608 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+LED castellated
+0
+2
+2
+LED_SMD
+LED_0603_1608Metric_Pad1.05x0.95mm_HandSolder
+LED SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+LED handsolder
+0
+2
+2
+LED_SMD
+LED_0805_2012Metric
+LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator
+diode
+0
+2
+2
+LED_SMD
+LED_0805_2012Metric_Castellated
+LED SMD 0805 (2012 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator
+LED castellated
+0
+2
+2
+LED_SMD
+LED_0805_2012Metric_Pad1.15x1.40mm_HandSolder
+LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator
+LED handsolder
+0
+2
+2
+LED_SMD
+LED_01005_0402Metric
+LED SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator
+LED
+0
+4
+2
+LED_SMD
+LED_1206_3216Metric
+LED SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+LED_SMD
+LED_1206_3216Metric_Castellated
+LED SMD 1206 (3216 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+LED castellated
+0
+2
+2
+LED_SMD
+LED_1206_3216Metric_Pad1.42x1.75mm_HandSolder
+LED SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+LED handsolder
+0
+2
+2
+LED_SMD
+LED_1206_3216Metric_ReverseMount_Hole1.8x2.4mm
+LED SMD 1206 (3216 Metric), reverse mount, square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode reverse
+0
+2
+2
+LED_SMD
+LED_1210_3225Metric
+LED SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+LED_SMD
+LED_1210_3225Metric_Castellated
+LED SMD 1210 (3225 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+LED castellated
+0
+2
+2
+LED_SMD
+LED_1210_3225Metric_Pad1.42x2.65mm_HandSolder
+LED SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+LED handsolder
+0
+2
+2
+LED_SMD
+LED_1806_4516Metric
+LED SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+LED_SMD
+LED_1806_4516Metric_Castellated
+LED SMD 1806 (4516 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator
+LED castellated
+0
+2
+2
+LED_SMD
+LED_1806_4516Metric_Pad1.57x1.80mm_HandSolder
+LED SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator
+LED handsolder
+0
+2
+2
+LED_SMD
+LED_1812_4532Metric
+LED SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+LED_SMD
+LED_1812_4532Metric_Castellated
+LED SMD 1812 (4532 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator
+LED castellated
+0
+2
+2
+LED_SMD
+LED_1812_4532Metric_Pad1.30x3.40mm_HandSolder
+LED SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator
+LED handsolder
+0
+2
+2
+LED_SMD
+LED_2010_5025Metric
+LED SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+LED_SMD
+LED_2010_5025Metric_Castellated
+LED SMD 2010 (5025 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+LED castellated
+0
+2
+2
+LED_SMD
+LED_2010_5025Metric_Pad1.52x2.65mm_HandSolder
+LED SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+LED handsolder
+0
+2
+2
+LED_SMD
+LED_2512_6332Metric
+LED SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+LED_SMD
+LED_2512_6332Metric_Castellated
+LED SMD 2512 (6332 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+LED castellated
+0
+2
+2
+LED_SMD
+LED_2512_6332Metric_Pad1.52x3.35mm_HandSolder
+LED SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+LED handsolder
+0
+2
+2
+LED_SMD
+LED_2816_7142Metric
+LED SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator
+diode
+0
+2
+2
+LED_SMD
+LED_2816_7142Metric_Castellated
+LED SMD 2816 (7142 Metric), castellated end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator
+LED castellated
+0
+2
+2
+LED_SMD
+LED_2816_7142Metric_Pad3.20x4.45mm_HandSolder
+LED SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator
+LED handsolder
+0
+2
+2
+LED_SMD
+LED_Avago_PLCC4_3.2x2.8mm_CW
+https://docs.broadcom.com/docs/AV02-4186EN
+LED Avago PLCC-4 ASMB-MTB0-0A3A2
+0
+4
+4
+LED_SMD
+LED_Avago_PLCC6_3x2.8mm
+https://docs.broadcom.com/docs/AV02-3793EN
+LED Avago PLCC-6 ASMT-YTB7-0AA02
+0
+6
+6
+LED_SMD
+LED_Cree-PLCC4_2x2mm_CW
+2.0mm x 2.0mm PLCC4 LED, http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/HB/Data-Sheets/CLMVBFKA.pdf
+LED Cree PLCC-4
+0
+4
+4
+LED_SMD
+LED_Cree-PLCC4_3.2x2.8mm_CCW
+3.2mm x 2.8mm PLCC4 LED, http://www.cree.com/led-components/media/documents/CLV1AFKB(874).pdf
+LED Cree PLCC-4
+0
+4
+4
+LED_SMD
+LED_Cree-PLCC4_5x5mm_CW
+5.0mm x 5.0mm PLCC4 LED
+LED Cree PLCC-4
+0
+4
+4
+LED_SMD
+LED_Cree-PLCC6_4.7x1.5mm
+4.7mm x 1.5mm PLCC6 LED, http://www.cree.com/led-components/media/documents/1381-QLS6AFKW.pdf
+LED Cree PLCC-6
+0
+6
+6
+LED_SMD
+LED_Cree-XB
+http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/XLamp/Data-and-Binning/XLampXBD.pdf
+LED Cree XB
+0
+5
+3
+LED_SMD
+LED_Cree-XH
+http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/XLamp/Data-and-Binning/ds-XHB.pdf
+LED Cree XH
+0
+8
+2
+LED_SMD
+LED_Cree-XHP35
+http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/XLamp/Data-and-Binning/ds--XHP35.pdf
+LED Cree XHP35
+0
+6
+3
+LED_SMD
+LED_Cree-XHP50_6V
+Cree XHP50, 6V footprint, http://www.cree.com/~/media/Files/Cree/LED%20Components%20and%20Modules/XLamp/Data%20and%20Binning/ds%20XHP50.pdf
+LED Cree XHP50
+0
+17
+3
+LED_SMD
+LED_Cree-XHP50_12V
+Cree XHP50, 12V footprint, http://www.cree.com/~/media/Files/Cree/LED%20Components%20and%20Modules/XLamp/Data%20and%20Binning/ds%20XHP50.pdf
+LED XHP50 Cree
+0
+15
+3
+LED_SMD
+LED_Cree-XHP70_6V
+Cree XHP70 LED, 6V version, http://www.cree.com/~/media/Files/Cree/LED%20Components%20and%20Modules/XLamp/Data%20and%20Binning/ds%20XHP70.pdf
+LED Cree XHP70
+0
+17
+3
+LED_SMD
+LED_Cree-XHP70_12V
+Cree XHP70 LED, 12V version, http://www.cree.com/~/media/Files/Cree/LED%20Components%20and%20Modules/XLamp/Data%20and%20Binning/ds%20XHP70.pdf
+LED Cree XHP70
+0
+15
+3
+LED_SMD
+LED_Cree-XP
+LED Cree-XP http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/XLamp/Data-and-Binning/XLampXPE2.pdf
+LED Cree XP
+0
+6
+3
+LED_SMD
+LED_Cree-XP-G
+LED Cree-XP-G http://www.cree.com/~/media/Files/Cree/LED%20Components%20and%20Modules/XLamp/Data%20and%20Binning/XLampXPG.pdf
+LED Cree XP-G
+0
+6
+3
+LED_SMD
+LED_Cree-XQ
+LED Cree-XQ http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/XLamp/Data-and-Binning/ds-XQB.pdf
+LED Cree XQ
+0
+2
+2
+LED_SMD
+LED_Cree-XQ_HandSoldering
+LED Cree-XQ handsoldering pads http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/XLamp/Data-and-Binning/ds-XQB.pdf
+LED Cree XQ
+0
+2
+2
+LED_SMD
+LED_Dialight_591
+LED SMD 3mm Right Angle series (http://www.dialightsignalsandcomponents.com/Assets/Drawings/2D_Drawings_DrawingDetailedSpec/C17354.pdf)
+LED Dialight 591
+0
+2
+2
+LED_SMD
+LED_Inolux_IN-PI554FCH_PLCC4_5.0x5.0mm_P3.2mm
+http://www.inolux-corp.com/datasheet/SMDLED/Addressable%20LED/IN-PI554FCH.pdf
+RGB LED NeoPixel addressable
+0
+4
+4
+LED_SMD
+LED_Kingbright_AAA3528ESGCT
+Kingbright, dual LED, 3.5 x 2.8 mm Surface Mount LED Lamp (http://www.kingbrightusa.com/images/catalog/SPEC/AAA3528ESGCT.pdf)
+dual led smd
+0
+4
+4
+LED_SMD
+LED_Kingbright_APFA3010_3x1.5mm_Horizontal
+LED RGB, APFA3010, http://www.kingbrightusa.com/images/catalog/SPEC/APFA3010LSEEZGKQBKC.pdf
+LED RGB APFA3010 KINGBRIGHT 3x1.5mm
+0
+4
+4
+LED_SMD
+LED_LiteOn_LTST-C19HE1WT
+LiteOn RGB LED; https://optoelectronics.liteon.com/upload/download/DS22-2008-0044/LTST-C19HE1WT.pdf
+LED RGB Chip SMD
+0
+4
+4
+LED_SMD
+LED_LiteOn_LTST-S326
+http://optoelectronics.liteon.com/upload/download/DS22-2000-287/LTST-S326KGJRKT.PDF
+LED SMD right angle  CCA
+0
+3
+3
+LED_SMD
+LED_Osram_Lx_P47F_D2mm_ReverseMount
+OSRAM, reverse-mount LED, SMD, 2mm diameter, http://www.farnell.com/datasheets/2711587.pdf
+LED ReverseMount Reverse
+0
+4
+2
+LED_SMD
+LED_PLCC-2
+LED PLCC-2 SMD package
+LED PLCC-2 SMD
+0
+2
+2
+LED_SMD
+LED_PLCC_2835
+https://www.luckylight.cn/media/component/data-sheet/R2835BC-B2M-M10.pdf
+LED
+0
+2
+2
+LED_SMD
+LED_PLCC_2835_Handsoldering
+https://www.luckylight.cn/media/component/data-sheet/R2835BC-B2M-M10.pdf
+LED
+0
+2
+2
+LED_SMD
+LED_RGB_1210
+RGB LED 3.2x2.7mm http://www.avagotech.com/docs/AV02-0610EN
+LED 3227
+0
+4
+4
+LED_SMD
+LED_RGB_5050-6
+http://cdn.sparkfun.com/datasheets/Components/LED/5060BRG4.pdf
+RGB LED 5050-6
+0
+6
+6
+LED_SMD
+LED_RGB_Cree-PLCC-6_6x5mm_P2.1mm
+http://www.farnell.com/datasheets/2003905.pdf
+LED RGB PLCC-6 CLP6C-FBK
+0
+6
+6
+LED_SMD
+LED_RGB_Getian_GT-P6PRGB4303
+https://www.gme.sk/img/cache/doc/518/177/vykonova-led-getian-gt-p6prgb4303-datasheet-1.pdf
+LED RGB 
+0
+7
+7
+LED_SMD
+LED_RGB_PLCC-6
+RGB LED PLCC-6
+RGB LED PLCC-6
+0
+6
+6
+LED_SMD
+LED_ROHM_SMLVN6
+https://www.rohm.com/datasheet/SMLVN6RGB1U
+LED ROHM SMLVN6
+0
+6
+6
+LED_SMD
+LED_SK6805_PLCC4_2.4x2.7mm_P1.3mm
+https://cdn-shop.adafruit.com/product-files/3484/3484_Datasheet.pdf
+LED RGB NeoPixel Nano
+0
+4
+4
+LED_SMD
+LED_SK6812MINI_PLCC4_3.5x3.5mm_P1.75mm
+https://cdn-shop.adafruit.com/product-files/2686/SK6812MINI_REV.01-1-2.pdf
+LED RGB NeoPixel Mini
+0
+4
+4
+LED_SMD
+LED_SK6812_EC15_1.5x1.5mm
+http://www.newstar-ledstrip.com/product/20181119172602110.pdf
+LED RGB NeoPixel
+0
+4
+4
+LED_SMD
+LED_SK6812_PLCC4_5.0x5.0mm_P3.2mm
+https://cdn-shop.adafruit.com/product-files/1138/SK6812+LED+datasheet+.pdf
+LED RGB NeoPixel
+0
+4
+4
+LED_SMD
+LED_WS2812B_PLCC4_5.0x5.0mm_P3.2mm
+https://cdn-shop.adafruit.com/datasheets/WS2812B.pdf
+LED RGB NeoPixel
+0
+4
+4
+LED_SMD
+LED_WS2812_PLCC6_5.0x5.0mm_P1.6mm
+https://cdn-shop.adafruit.com/datasheets/WS2812.pdf
+LED RGB NeoPixel
+0
+6
+6
+LED_SMD
+LED_Yuji_5730
+LED,Yuji,5730,https://cdn.shopify.com/s/files/1/0344/6401/files/YJWJ014-1.1_YJ-BC-5730L-G02.pdf
+LED Yuji 5730
+0
+3
+2
+LED_SMD
+LED_miniPLCC_2315
+https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DAV02-2205EN_DS_ASMT-TxBM_2014-05-09.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430858274704&ssbinary=true
+LED
+0
+2
+2
+LED_SMD
+LED_miniPLCC_2315_Handsoldering
+https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DAV02-2205EN_DS_ASMT-TxBM_2014-05-09.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430858274704&ssbinary=true
+LED
+0
+2
+2
+LED_THT
+LED_BL-FL7680RGB
+'Piranha' RGB LED, through hole, common anode, 7.62x7.62mm, BGRA pin order, https://cdn-shop.adafruit.com/datasheets/BL-FL7680RGB.pdf
+RGB LED Piranha Super-Flux BetLux
+0
+4
+4
+LED_THT
+LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O1.27mm_Z1.6mm
+LED, ,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins
+LED   diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins
+0
+2
+2
+LED_THT
+LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O1.27mm_Z4.9mm
+LED, ,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins
+LED   diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins
+0
+2
+2
+LED_THT
+LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O1.27mm_Z8.2mm
+LED, ,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm, 2 pins
+LED   diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm 2 pins
+0
+2
+2
+LED_THT
+LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O3.81mm_Z1.6mm
+LED, ,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins
+LED   diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins
+0
+2
+2
+LED_THT
+LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O3.81mm_Z4.9mm
+LED, ,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins
+LED   diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins
+0
+2
+2
+LED_THT
+LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O3.81mm_Z8.2mm
+LED, ,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm, 2 pins
+LED   diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm 2 pins
+0
+2
+2
+LED_THT
+LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O6.35mm_Z1.6mm
+LED, ,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins
+LED   diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins
+0
+2
+2
+LED_THT
+LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O6.35mm_Z4.9mm
+LED, ,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins
+LED   diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins
+0
+2
+2
+LED_THT
+LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O6.35mm_Z8.2mm
+LED, ,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm, 2 pins,  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm, 2 pins
+LED   diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm 2 pins  diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm 2 pins
+0
+2
+2
+LED_THT
+LED_D1.8mm_W3.3mm_H2.4mm
+LED, Round,  Rectangular size 3.3x2.4mm^2 diameter 1.8mm, 2 pins
+LED Round  Rectangular size 3.3x2.4mm^2 diameter 1.8mm 2 pins
+0
+2
+2
+LED_THT
+LED_D2.0mm_W4.0mm_H2.8mm_FlatTop
+LED, Round, FlatTop,  Rectangular size 4.0x2.8mm^2 diameter 2.0mm, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-1034IDT(Ver.9A).pdf
+LED Round FlatTop  Rectangular size 4.0x2.8mm^2 diameter 2.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D2.0mm_W4.8mm_H2.5mm_FlatTop
+LED, Round, FlatTop,  Rectangular size 4.8x2.5mm^2 diameter 2.0mm, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-13GD(Ver.11B).pdf
+LED Round FlatTop  Rectangular size 4.8x2.5mm^2 diameter 2.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D3.0mm
+LED, diameter 3.0mm, 2 pins
+LED diameter 3.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D3.0mm-3
+LED, diameter 3.0mm, 2 pins, diameter 3.0mm, 3 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-3VSURKCGKC(Ver.8A).pdf
+LED diameter 3.0mm 2 pins diameter 3.0mm 3 pins
+0
+3
+3
+LED_THT
+LED_D3.0mm_Clear
+IR-LED, diameter 3.0mm, 2 pins, color: clear
+IR infrared LED diameter 3.0mm 2 pins clear
+0
+2
+2
+LED_THT
+LED_D3.0mm_FlatTop
+LED, Round, FlatTop, diameter 3.0mm, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-47XEC(Ver.9A).pdf
+LED Round FlatTop diameter 3.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D3.0mm_Horizontal_O1.27mm_Z2.0mm
+LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins
+LED diameter 3.0mm z-position of LED center 2.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D3.0mm_Horizontal_O1.27mm_Z2.0mm_Clear
+LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins
+LED diameter 3.0mm z-position of LED center 2.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D3.0mm_Horizontal_O1.27mm_Z2.0mm_IRBlack
+LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins
+LED diameter 3.0mm z-position of LED center 2.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D3.0mm_Horizontal_O1.27mm_Z2.0mm_IRGrey
+LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins
+LED diameter 3.0mm z-position of LED center 2.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D3.0mm_Horizontal_O1.27mm_Z6.0mm
+LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins
+LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D3.0mm_Horizontal_O1.27mm_Z10.0mm
+LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 10.0mm, 2 pins
+LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 10.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D3.0mm_Horizontal_O3.81mm_Z2.0mm
+LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins
+LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D3.0mm_Horizontal_O3.81mm_Z6.0mm
+LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins
+LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D3.0mm_Horizontal_O3.81mm_Z10.0mm
+LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 10.0mm, 2 pins, diameter 3.0mm z-position of LED center 10.0mm, 2 pins
+LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 10.0mm 2 pins diameter 3.0mm z-position of LED center 10.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D3.0mm_Horizontal_O6.35mm_Z2.0mm
+LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins
+LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D3.0mm_Horizontal_O6.35mm_Z6.0mm
+LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins
+LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D3.0mm_Horizontal_O6.35mm_Z10.0mm
+LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 10.0mm, 2 pins, diameter 3.0mm z-position of LED center 10.0mm, 2 pins, diameter 3.0mm z-position of LED center 10.0mm, 2 pins
+LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 10.0mm 2 pins diameter 3.0mm z-position of LED center 10.0mm 2 pins diameter 3.0mm z-position of LED center 10.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D3.0mm_IRBlack
+IR-ED, diameter 3.0mm, 2 pins, color: black
+IR infrared LED diameter 3.0mm 2 pins black
+0
+2
+2
+LED_THT
+LED_D3.0mm_IRGrey
+IR-LED, diameter 3.0mm, 2 pins, color: grey
+IR infrared LED diameter 3.0mm 2 pins grey
+0
+2
+2
+LED_THT
+LED_D4.0mm
+LED, diameter 4.0mm, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-43GD(Ver.12B).pdf
+LED diameter 4.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D5.0mm
+LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf
+LED diameter 5.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D5.0mm-3
+LED, diameter 5.0mm, 2 pins, diameter 5.0mm, 3 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-59EGC(Ver.17A).pdf
+LED diameter 5.0mm 2 pins diameter 5.0mm 3 pins
+0
+3
+3
+LED_THT
+LED_D5.0mm-3_Horizontal_O3.81mm_Z3.0mm
+LED, diameter 5.0mm z-position of LED center 3.0mm, 3 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins
+LED diameter 5.0mm z-position of LED center 3.0mm 3 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins
+0
+3
+3
+LED_THT
+LED_D5.0mm-4_RGB
+LED, diameter 5.0mm, 2 pins, diameter 5.0mm, 3 pins, diameter 5.0mm, 4 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-154A4SUREQBFZGEW(Ver.9A).pdf
+LED diameter 5.0mm 2 pins diameter 5.0mm 3 pins diameter 5.0mm 4 pins RGB RGBLED
+0
+4
+4
+LED_THT
+LED_D5.0mm-4_RGB_Staggered_Pins
+LED, diameter 5.0mm, 2 pins, diameter 5.0mm, 3 pins, diameter 5.0mm, 4 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-154A4SUREQBFZGEW(Ver.9A).pdf
+LED diameter 5.0mm 2 pins diameter 5.0mm 3 pins diameter 5.0mm 4 pins RGB RGBLED
+0
+4
+4
+LED_THT
+LED_D5.0mm-4_RGB_Wide_Pins
+LED, diameter 5.0mm, 2 pins, diameter 5.0mm, 3 pins, diameter 5.0mm, 4 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-154A4SUREQBFZGEW(Ver.9A).pdf
+LED diameter 5.0mm 2 pins diameter 5.0mm 3 pins diameter 5.0mm 4 pins RGB RGBLED
+0
+4
+4
+LED_THT
+LED_D5.0mm_Clear
+LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf
+LED diameter 5.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D5.0mm_FlatTop
+LED, Round, FlatTop, diameter 5.0mm, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-483GDT(Ver.15B).pdf
+LED Round FlatTop diameter 5.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D5.0mm_Horizontal_O1.27mm_Z3.0mm
+LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins
+LED diameter 5.0mm z-position of LED center 3.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D5.0mm_Horizontal_O1.27mm_Z3.0mm_Clear
+LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins
+LED diameter 5.0mm z-position of LED center 3.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D5.0mm_Horizontal_O1.27mm_Z3.0mm_IRBlack
+LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins
+LED diameter 5.0mm z-position of LED center 3.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D5.0mm_Horizontal_O1.27mm_Z3.0mm_IRGrey
+LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins
+LED diameter 5.0mm z-position of LED center 3.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D5.0mm_Horizontal_O1.27mm_Z9.0mm
+LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins
+LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D5.0mm_Horizontal_O1.27mm_Z15.0mm
+LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 15.0mm, 2 pins
+LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 15.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D5.0mm_Horizontal_O3.81mm_Z3.0mm
+LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins
+LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D5.0mm_Horizontal_O3.81mm_Z9.0mm
+LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins
+LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D5.0mm_Horizontal_O3.81mm_Z15.0mm
+LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 15.0mm, 2 pins, diameter 5.0mm z-position of LED center 15.0mm, 2 pins
+LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 15.0mm 2 pins diameter 5.0mm z-position of LED center 15.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D5.0mm_Horizontal_O6.35mm_Z3.0mm
+LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins
+LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D5.0mm_Horizontal_O6.35mm_Z9.0mm
+LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins
+LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D5.0mm_Horizontal_O6.35mm_Z15.0mm
+LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 15.0mm, 2 pins, diameter 5.0mm z-position of LED center 15.0mm, 2 pins, diameter 5.0mm z-position of LED center 15.0mm, 2 pins
+LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 15.0mm 2 pins diameter 5.0mm z-position of LED center 15.0mm 2 pins diameter 5.0mm z-position of LED center 15.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D5.0mm_IRBlack
+LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf
+LED diameter 5.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D5.0mm_IRGrey
+LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf
+LED diameter 5.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D8.0mm
+LED, diameter 8.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LED8MMGE_LED8MMGN_LED8MMRT%23KIN.pdf
+LED diameter 8.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D8.0mm-3
+LED, diameter 8.0mm, 2 pins, diameter 8.0mm, 3 pins
+LED diameter 8.0mm 2 pins diameter 8.0mm 3 pins
+0
+3
+3
+LED_THT
+LED_D10.0mm
+LED, diameter 10.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LED10-4500RT%23KIN.pdf
+LED diameter 10.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_D10.0mm-3
+LED, diameter 10.0mm, 2 pins, diameter 10.0mm, 3 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-819EGW(Ver.14A).pdf
+LED diameter 10.0mm 2 pins diameter 10.0mm 3 pins
+0
+3
+3
+LED_THT
+LED_D20.0mm
+LED, diameter 20.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/DLC2-6GD%28V6%29.pdf
+LED diameter 20.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_Oval_W5.2mm_H3.8mm
+LED_Oval, Oval,  Oval size 5.2x3.8mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-5603QBC-D(Ver.12B).pdf
+LED_Oval Oval  Oval size 5.2x3.8mm^2 2 pins
+0
+2
+2
+LED_THT
+LED_Rectangular_W3.0mm_H2.0mm
+LED_Rectangular, Rectangular,  Rectangular size 3.0x2.0mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-169XCGDK(Ver.9B).pdf
+LED_Rectangular Rectangular  Rectangular size 3.0x2.0mm^2 2 pins
+0
+2
+2
+LED_THT
+LED_Rectangular_W3.9mm_H1.8mm
+LED_Rectangular, Rectangular,  Rectangular size 3.9x1.8mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-2774GD(Ver.7B).pdf
+LED_Rectangular Rectangular  Rectangular size 3.9x1.8mm^2 2 pins
+0
+2
+2
+LED_THT
+LED_Rectangular_W3.9mm_H1.8mm_FlatTop
+LED_Rectangular, Rectangular,  Rectangular size 3.9x1.8mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-2774GD(Ver.7B).pdf
+LED_Rectangular Rectangular  Rectangular size 3.9x1.8mm^2 2 pins
+0
+2
+2
+LED_THT
+LED_Rectangular_W3.9mm_H1.9mm
+LED_Rectangular, Rectangular,  Rectangular size 3.9x1.9mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-144GDT(Ver.14B).pdf
+LED_Rectangular Rectangular  Rectangular size 3.9x1.9mm^2 2 pins
+0
+2
+2
+LED_THT
+LED_Rectangular_W5.0mm_H2.0mm
+LED_Rectangular, Rectangular,  Rectangular size 5.0x2.0mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-169XCGDK(Ver.9B).pdf
+LED_Rectangular Rectangular  Rectangular size 5.0x2.0mm^2 2 pins
+0
+2
+2
+LED_THT
+LED_Rectangular_W5.0mm_H2.0mm-3Pins
+LED_Rectangular, Rectangular,  Rectangular size 5.0x2.0mm^2, 3 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-169XCGDK(Ver.9B).pdf
+LED_Rectangular Rectangular  Rectangular size 5.0x2.0mm^2 3 pins
+0
+3
+3
+LED_THT
+LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O1.27mm_Z1.0mm
+LED_Rectangular, Rectangular,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins
+LED_Rectangular Rectangular  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O1.27mm_Z3.0mm
+LED_Rectangular, Rectangular,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins
+LED_Rectangular Rectangular  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O1.27mm_Z5.0mm
+LED_Rectangular, Rectangular,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm, 2 pins
+LED_Rectangular Rectangular  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O3.81mm_Z1.0mm
+LED_Rectangular, Rectangular,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins
+LED_Rectangular Rectangular  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O3.81mm_Z3.0mm
+LED_Rectangular, Rectangular,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins
+LED_Rectangular Rectangular  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O3.81mm_Z5.0mm
+LED_Rectangular, Rectangular,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm, 2 pins
+LED_Rectangular Rectangular  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O6.35mm_Z1.0mm
+LED_Rectangular, Rectangular,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins
+LED_Rectangular Rectangular  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O6.35mm_Z3.0mm
+LED_Rectangular, Rectangular,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins
+LED_Rectangular Rectangular  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O6.35mm_Z5.0mm
+LED_Rectangular, Rectangular,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm, 2 pins,  Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm, 2 pins
+LED_Rectangular Rectangular  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm 2 pins  Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm 2 pins
+0
+2
+2
+LED_THT
+LED_Rectangular_W5.0mm_H5.0mm
+LED_Rectangular, Rectangular,  Rectangular size 5.0x5.0mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-169XCGDK(Ver.9B).pdf
+LED_Rectangular Rectangular  Rectangular size 5.0x5.0mm^2 2 pins
+0
+2
+2
+LED_THT
+LED_Rectangular_W7.62mm_H4.55mm_P5.08mm_R3
+Datasheet can be found at https://www.gme.cz/data/attachments/dsh.511-795.1.pdf
+LED automotive super flux 7.62mm
+0
+4
+2
+LED_THT
+LED_SideEmitter_Rectangular_W4.5mm_H1.6mm
+LED_SideEmitter_Rectangular, Rectangular, SideEmitter,  Rectangular size 4.5x1.6mm^2, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LED15MMGE_LED15MMGN%23KIN.pdf
+LED_SideEmitter_Rectangular Rectangular SideEmitter  Rectangular size 4.5x1.6mm^2 2 pins
+0
+2
+2
+LED_THT
+LED_VCCLite_5381H1_6.35x6.35mm
+Red 5381 Series LED VCCLite https://vcclite.com/wp-content/uploads/wpallimport/files/files/5381Series.pdf http://static.vcclite.com/pdf/Mounting%20Hole%20Pattern%202.pdf
+Red 5381 Series LED
+0
+2
+2
+LED_THT
+LED_VCCLite_5381H3_6.35x6.35mm
+Amber 5381 Series LED VCCLite https://vcclite.com/wp-content/uploads/wpallimport/files/files/5381Series.pdf http://static.vcclite.com/pdf/Mounting%20Hole%20Pattern%202.pdf
+Amber 5381 Series LED
+0
+2
+2
+LED_THT
+LED_VCCLite_5381H5_6.35x6.35mm
+Green 5381 Series LED VCCLite https://vcclite.com/wp-content/uploads/wpallimport/files/files/5381Series.pdf http://static.vcclite.com/pdf/Mounting%20Hole%20Pattern%202.pdf
+Green 5381 Series LED
+0
+2
+2
+LED_THT
+LED_VCCLite_5381H7_6.35x6.35mm
+Yellow 5381 Series LED VCCLite https://vcclite.com/wp-content/uploads/wpallimport/files/files/5381Series.pdf http://static.vcclite.com/pdf/Mounting%20Hole%20Pattern%202.pdf
+Yellow 5381 Series LED
+0
+2
+2
+LTC3883IUHPBF
+QFN-32_UH
+
+
+0
+33
+33
+MIC5504-1
+SOT23-5P95_280X145XL45X37N
+
+
+0
+5
+5
+Module
+A20_OLINUXINO_LIME2
+A20 Olinuxino LIME2, 1.2GHz, 512-1024MB RAM, Micro-SD, NAND or eMMC, 1000Mbit Ethernet
+A20 Olimex Olinuxino LIME2 development board
+0
+180
+180
+Module
+Adafruit_HUZZAH_ESP8266_breakout
+32-bit microcontroller module with WiFi, https://www.adafruit.com/product/2471
+ESP8266 WiFi microcontroller
+0
+20
+20
+Module
+Adafruit_HUZZAH_ESP8266_breakout_WithMountingHoles
+32-bit microcontroller module with WiFi, https://www.adafruit.com/product/2471
+ESP8266 WiFi microcontroller
+0
+20
+20
+Module
+Arduino_Nano
+Arduino Nano, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf
+Arduino Nano
+0
+30
+30
+Module
+Arduino_Nano_WithMountingHoles
+Arduino Nano, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf
+Arduino Nano
+0
+30
+30
+Module
+Arduino_UNO_R2
+Arduino UNO R2, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf
+Arduino UNO R2
+0
+30
+30
+Module
+Arduino_UNO_R2_WithMountingHoles
+Arduino UNO R2, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf
+Arduino UNO R2
+0
+30
+30
+Module
+Arduino_UNO_R3
+Arduino UNO R3, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf
+Arduino UNO R3
+0
+32
+32
+Module
+Arduino_UNO_R3_WithMountingHoles
+Arduino UNO R3, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf
+Arduino UNO R3
+0
+32
+32
+Module
+BeagleBoard_PocketBeagle
+PocketBeagle, https://github.com/beagleboard/pocketbeagle/wiki/System-Reference-Manual#71_Expansion_Header_Connectors
+PocketBeagle
+0
+72
+72
+Module
+Maple_Mini
+Maple Mini, http://docs.leaflabs.com/static.leaflabs.com/pub/leaflabs/maple-docs/0.0.12/hardware/maple-mini.html
+Maple Mini
+0
+40
+40
+Module
+Onion_Omega2+
+https://onion.io/omega2/
+Omega Onion module
+0
+32
+32
+Module
+Onion_Omega2S
+https://github.com/OnionIoT/Omega2/raw/master/Documents/Omega2S%20Datasheet.pdf
+onion omega module
+0
+89
+64
+Module
+Pololu_Breakout-16_15.2x20.3mm
+Pololu Breakout 16-pin 15.2x20.3mm 0.6x0.8\
+Pololu Breakout
+0
+16
+16
+Module
+Raspberry_Pi_Zero_Socketed_THT_FaceDown_MountingHoles
+Raspberry Pi Zero using through hole straight pin socket, 2x20, 2.54mm pitch, https://www.raspberrypi.org/documentation/hardware/raspberrypi/mechanical/rpi_MECH_Zero_1p2.pdf
+raspberry pi zero through hole
+0
+40
+40
+Module
+ST_Morpho_Connector_144_STLink
+ST Morpho Connector 144 With STLink
+ST Morpho Connector 144 STLink
+0
+148
+148
+Module
+ST_Morpho_Connector_144_STLink_MountingHoles
+ST Morpho Connector 144 With STLink
+ST Morpho Connector 144 STLink
+0
+148
+148
+Module
+WEMOS_D1_mini_light
+16-pin module, column spacing 22.86 mm (900 mils), https://wiki.wemos.cc/products:d1:d1_mini, https://c1.staticflickr.com/1/734/31400410271_f278b087db_z.jpg
+ESP8266 WiFi microcontroller
+0
+16
+16
+MountingEquipment
+DINRailAdapter_3xM3_PhoenixContact_1201578
+https://www.phoenixcontact.com/online/portal/us?uri=pxc-oc-itemdetail:pid=1201578&library=usen&tab=1
+DIN rail adapter universal three M3 clearance holes
+0
+0
+0
+MountingHole
+MountingHole_2.1mm
+Mounting Hole 2.1mm, no annular
+mounting hole 2.1mm no annular
+0
+0
+0
+MountingHole
+MountingHole_2.2mm_M2
+Mounting Hole 2.2mm, no annular, M2
+mounting hole 2.2mm no annular m2
+0
+0
+0
+MountingHole
+MountingHole_2.2mm_M2_DIN965
+Mounting Hole 2.2mm, no annular, M2, DIN965
+mounting hole 2.2mm no annular m2 din965
+0
+0
+0
+MountingHole
+MountingHole_2.2mm_M2_DIN965_Pad
+Mounting Hole 2.2mm, M2, DIN965
+mounting hole 2.2mm m2 din965
+0
+1
+1
+MountingHole
+MountingHole_2.2mm_M2_ISO7380
+Mounting Hole 2.2mm, no annular, M2, ISO7380
+mounting hole 2.2mm no annular m2 iso7380
+0
+0
+0
+MountingHole
+MountingHole_2.2mm_M2_ISO7380_Pad
+Mounting Hole 2.2mm, M2, ISO7380
+mounting hole 2.2mm m2 iso7380
+0
+1
+1
+MountingHole
+MountingHole_2.2mm_M2_ISO14580
+Mounting Hole 2.2mm, no annular, M2, ISO14580
+mounting hole 2.2mm no annular m2 iso14580
+0
+0
+0
+MountingHole
+MountingHole_2.2mm_M2_ISO14580_Pad
+Mounting Hole 2.2mm, M2, ISO14580
+mounting hole 2.2mm m2 iso14580
+0
+1
+1
+MountingHole
+MountingHole_2.2mm_M2_Pad
+Mounting Hole 2.2mm, M2
+mounting hole 2.2mm m2
+0
+1
+1
+MountingHole
+MountingHole_2.2mm_M2_Pad_Via
+Mounting Hole 2.2mm, M2
+mounting hole 2.2mm m2
+0
+9
+1
+MountingHole
+MountingHole_2.5mm
+Mounting Hole 2.5mm, no annular
+mounting hole 2.5mm no annular
+0
+0
+0
+MountingHole
+MountingHole_2.5mm_Pad
+Mounting Hole 2.5mm
+mounting hole 2.5mm
+0
+1
+1
+MountingHole
+MountingHole_2.5mm_Pad_Via
+Mounting Hole 2.5mm
+mounting hole 2.5mm
+0
+9
+1
+MountingHole
+MountingHole_2.7mm
+Mounting Hole 2.7mm, no annular
+mounting hole 2.7mm no annular
+0
+0
+0
+MountingHole
+MountingHole_2.7mm_M2.5
+Mounting Hole 2.7mm, no annular, M2.5
+mounting hole 2.7mm no annular m2.5
+0
+0
+0
+MountingHole
+MountingHole_2.7mm_M2.5_DIN965
+Mounting Hole 2.7mm, no annular, M2.5, DIN965
+mounting hole 2.7mm no annular m2.5 din965
+0
+0
+0
+MountingHole
+MountingHole_2.7mm_M2.5_DIN965_Pad
+Mounting Hole 2.7mm, M2.5, DIN965
+mounting hole 2.7mm m2.5 din965
+0
+1
+1
+MountingHole
+MountingHole_2.7mm_M2.5_ISO7380
+Mounting Hole 2.7mm, no annular, M2.5, ISO7380
+mounting hole 2.7mm no annular m2.5 iso7380
+0
+0
+0
+MountingHole
+MountingHole_2.7mm_M2.5_ISO7380_Pad
+Mounting Hole 2.7mm, M2.5, ISO7380
+mounting hole 2.7mm m2.5 iso7380
+0
+1
+1
+MountingHole
+MountingHole_2.7mm_M2.5_ISO14580
+Mounting Hole 2.7mm, no annular, M2.5, ISO14580
+mounting hole 2.7mm no annular m2.5 iso14580
+0
+0
+0
+MountingHole
+MountingHole_2.7mm_M2.5_ISO14580_Pad
+Mounting Hole 2.7mm, M2.5, ISO14580
+mounting hole 2.7mm m2.5 iso14580
+0
+1
+1
+MountingHole
+MountingHole_2.7mm_M2.5_Pad
+Mounting Hole 2.7mm, M2.5
+mounting hole 2.7mm m2.5
+0
+1
+1
+MountingHole
+MountingHole_2.7mm_M2.5_Pad_Via
+Mounting Hole 2.7mm
+mounting hole 2.7mm
+0
+9
+1
+MountingHole
+MountingHole_2.7mm_Pad
+Mounting Hole 2.7mm
+mounting hole 2.7mm
+0
+1
+1
+MountingHole
+MountingHole_2.7mm_Pad_Via
+Mounting Hole 2.7mm
+mounting hole 2.7mm
+0
+9
+1
+MountingHole
+MountingHole_2mm
+Mounting Hole 2mm, no annular
+mounting hole 2mm no annular
+0
+0
+0
+MountingHole
+MountingHole_3.2mm_M3
+Mounting Hole 3.2mm, no annular, M3
+mounting hole 3.2mm no annular m3
+0
+0
+0
+MountingHole
+MountingHole_3.2mm_M3_DIN965
+Mounting Hole 3.2mm, no annular, M3, DIN965
+mounting hole 3.2mm no annular m3 din965
+0
+0
+0
+MountingHole
+MountingHole_3.2mm_M3_DIN965_Pad
+Mounting Hole 3.2mm, M3, DIN965
+mounting hole 3.2mm m3 din965
+0
+1
+1
+MountingHole
+MountingHole_3.2mm_M3_ISO7380
+Mounting Hole 3.2mm, no annular, M3, ISO7380
+mounting hole 3.2mm no annular m3 iso7380
+0
+0
+0
+MountingHole
+MountingHole_3.2mm_M3_ISO7380_Pad
+Mounting Hole 3.2mm, M3, ISO7380
+mounting hole 3.2mm m3 iso7380
+0
+1
+1
+MountingHole
+MountingHole_3.2mm_M3_ISO14580
+Mounting Hole 3.2mm, no annular, M3, ISO14580
+mounting hole 3.2mm no annular m3 iso14580
+0
+0
+0
+MountingHole
+MountingHole_3.2mm_M3_ISO14580_Pad
+Mounting Hole 3.2mm, M3, ISO14580
+mounting hole 3.2mm m3 iso14580
+0
+1
+1
+MountingHole
+MountingHole_3.2mm_M3_Pad
+Mounting Hole 3.2mm, M3
+mounting hole 3.2mm m3
+0
+1
+1
+MountingHole
+MountingHole_3.2mm_M3_Pad_Via
+Mounting Hole 3.2mm, M3
+mounting hole 3.2mm m3
+0
+9
+1
+MountingHole
+MountingHole_3.5mm
+Mounting Hole 3.5mm, no annular
+mounting hole 3.5mm no annular
+0
+0
+0
+MountingHole
+MountingHole_3.5mm_Pad
+Mounting Hole 3.5mm
+mounting hole 3.5mm
+0
+1
+1
+MountingHole
+MountingHole_3.5mm_Pad_Via
+Mounting Hole 3.5mm
+mounting hole 3.5mm
+0
+9
+1
+MountingHole
+MountingHole_3.7mm
+Mounting Hole 3.7mm, no annular
+mounting hole 3.7mm no annular
+0
+0
+0
+MountingHole
+MountingHole_3.7mm_Pad
+Mounting Hole 3.7mm
+mounting hole 3.7mm
+0
+1
+1
+MountingHole
+MountingHole_3.7mm_Pad_Via
+Mounting Hole 3.7mm
+mounting hole 3.7mm
+0
+9
+1
+MountingHole
+MountingHole_3mm
+Mounting Hole 3mm, no annular
+mounting hole 3mm no annular
+0
+0
+0
+MountingHole
+MountingHole_3mm_Pad
+Mounting Hole 3mm
+mounting hole 3mm
+0
+1
+1
+MountingHole
+MountingHole_3mm_Pad_Via
+Mounting Hole 3mm
+mounting hole 3mm
+0
+9
+1
+MountingHole
+MountingHole_4.3mm_M4
+Mounting Hole 4.3mm, no annular, M4
+mounting hole 4.3mm no annular m4
+0
+0
+0
+MountingHole
+MountingHole_4.3mm_M4_DIN965
+Mounting Hole 4.3mm, no annular, M4, DIN965
+mounting hole 4.3mm no annular m4 din965
+0
+0
+0
+MountingHole
+MountingHole_4.3mm_M4_DIN965_Pad
+Mounting Hole 4.3mm, M4, DIN965
+mounting hole 4.3mm m4 din965
+0
+1
+1
+MountingHole
+MountingHole_4.3mm_M4_ISO7380
+Mounting Hole 4.3mm, no annular, M4, ISO7380
+mounting hole 4.3mm no annular m4 iso7380
+0
+0
+0
+MountingHole
+MountingHole_4.3mm_M4_ISO7380_Pad
+Mounting Hole 4.3mm, M4, ISO7380
+mounting hole 4.3mm m4 iso7380
+0
+1
+1
+MountingHole
+MountingHole_4.3mm_M4_ISO14580
+Mounting Hole 4.3mm, no annular, M4, ISO14580
+mounting hole 4.3mm no annular m4 iso14580
+0
+0
+0
+MountingHole
+MountingHole_4.3mm_M4_ISO14580_Pad
+Mounting Hole 4.3mm, M4, ISO14580
+mounting hole 4.3mm m4 iso14580
+0
+1
+1
+MountingHole
+MountingHole_4.3mm_M4_Pad
+Mounting Hole 4.3mm, M4
+mounting hole 4.3mm m4
+0
+1
+1
+MountingHole
+MountingHole_4.3mm_M4_Pad_Via
+Mounting Hole 4.3mm, M4
+mounting hole 4.3mm m4
+0
+9
+1
+MountingHole
+MountingHole_4.3x6.2mm_M4_Pad
+Mounting Hole 4.3x6.2mm, M4
+mounting hole 4.3x6.2mm m4
+0
+1
+1
+MountingHole
+MountingHole_4.3x6.2mm_M4_Pad_Via
+Mounting Hole 4.3x6.2mm, M4
+mounting hole 4.3x6.2mm m4
+0
+17
+1
+MountingHole
+MountingHole_4.5mm
+Mounting Hole 4.5mm, no annular
+mounting hole 4.5mm no annular
+0
+0
+0
+MountingHole
+MountingHole_4.5mm_Pad
+Mounting Hole 4.5mm
+mounting hole 4.5mm
+0
+1
+1
+MountingHole
+MountingHole_4.5mm_Pad_Via
+Mounting Hole 4.5mm
+mounting hole 4.5mm
+0
+9
+1
+MountingHole
+MountingHole_4mm
+Mounting Hole 4mm, no annular
+mounting hole 4mm no annular
+0
+0
+0
+MountingHole
+MountingHole_4mm_Pad
+Mounting Hole 4mm
+mounting hole 4mm
+0
+1
+1
+MountingHole
+MountingHole_4mm_Pad_Via
+Mounting Hole 4mm
+mounting hole 4mm
+0
+9
+1
+MountingHole
+MountingHole_5.3mm_M5
+Mounting Hole 5.3mm, no annular, M5
+mounting hole 5.3mm no annular m5
+0
+0
+0
+MountingHole
+MountingHole_5.3mm_M5_DIN965
+Mounting Hole 5.3mm, no annular, M5, DIN965
+mounting hole 5.3mm no annular m5 din965
+0
+0
+0
+MountingHole
+MountingHole_5.3mm_M5_DIN965_Pad
+Mounting Hole 5.3mm, M5, DIN965
+mounting hole 5.3mm m5 din965
+0
+1
+1
+MountingHole
+MountingHole_5.3mm_M5_ISO7380
+Mounting Hole 5.3mm, no annular, M5, ISO7380
+mounting hole 5.3mm no annular m5 iso7380
+0
+0
+0
+MountingHole
+MountingHole_5.3mm_M5_ISO7380_Pad
+Mounting Hole 5.3mm, M5, ISO7380
+mounting hole 5.3mm m5 iso7380
+0
+1
+1
+MountingHole
+MountingHole_5.3mm_M5_ISO14580
+Mounting Hole 5.3mm, no annular, M5, ISO14580
+mounting hole 5.3mm no annular m5 iso14580
+0
+0
+0
+MountingHole
+MountingHole_5.3mm_M5_ISO14580_Pad
+Mounting Hole 5.3mm, M5, ISO14580
+mounting hole 5.3mm m5 iso14580
+0
+1
+1
+MountingHole
+MountingHole_5.3mm_M5_Pad
+Mounting Hole 5.3mm, M5
+mounting hole 5.3mm m5
+0
+1
+1
+MountingHole
+MountingHole_5.3mm_M5_Pad_Via
+Mounting Hole 5.3mm, M5
+mounting hole 5.3mm m5
+0
+9
+1
+MountingHole
+MountingHole_5.5mm
+Mounting Hole 5.5mm, no annular
+mounting hole 5.5mm no annular
+0
+0
+0
+MountingHole
+MountingHole_5.5mm_Pad
+Mounting Hole 5.5mm
+mounting hole 5.5mm
+0
+1
+1
+MountingHole
+MountingHole_5.5mm_Pad_Via
+Mounting Hole 5.5mm
+mounting hole 5.5mm
+0
+9
+1
+MountingHole
+MountingHole_5mm
+Mounting Hole 5mm, no annular
+mounting hole 5mm no annular
+0
+0
+0
+MountingHole
+MountingHole_5mm_Pad
+Mounting Hole 5mm
+mounting hole 5mm
+0
+1
+1
+MountingHole
+MountingHole_5mm_Pad_Via
+Mounting Hole 5mm
+mounting hole 5mm
+0
+9
+1
+MountingHole
+MountingHole_6.4mm_M6
+Mounting Hole 6.4mm, no annular, M6
+mounting hole 6.4mm no annular m6
+0
+0
+0
+MountingHole
+MountingHole_6.4mm_M6_DIN965
+Mounting Hole 6.4mm, no annular, M6, DIN965
+mounting hole 6.4mm no annular m6 din965
+0
+0
+0
+MountingHole
+MountingHole_6.4mm_M6_DIN965_Pad
+Mounting Hole 6.4mm, M6, DIN965
+mounting hole 6.4mm m6 din965
+0
+1
+1
+MountingHole
+MountingHole_6.4mm_M6_ISO7380
+Mounting Hole 6.4mm, no annular, M6, ISO7380
+mounting hole 6.4mm no annular m6 iso7380
+0
+0
+0
+MountingHole
+MountingHole_6.4mm_M6_ISO7380_Pad
+Mounting Hole 6.4mm, M6, ISO7380
+mounting hole 6.4mm m6 iso7380
+0
+1
+1
+MountingHole
+MountingHole_6.4mm_M6_ISO14580
+Mounting Hole 6.4mm, no annular, M6, ISO14580
+mounting hole 6.4mm no annular m6 iso14580
+0
+0
+0
+MountingHole
+MountingHole_6.4mm_M6_ISO14580_Pad
+Mounting Hole 6.4mm, M6, ISO14580
+mounting hole 6.4mm m6 iso14580
+0
+1
+1
+MountingHole
+MountingHole_6.4mm_M6_Pad
+Mounting Hole 6.4mm, M6
+mounting hole 6.4mm m6
+0
+1
+1
+MountingHole
+MountingHole_6.4mm_M6_Pad_Via
+Mounting Hole 6.4mm, M6
+mounting hole 6.4mm m6
+0
+9
+1
+MountingHole
+MountingHole_6.5mm
+Mounting Hole 6.5mm, no annular
+mounting hole 6.5mm no annular
+0
+0
+0
+MountingHole
+MountingHole_6.5mm_Pad
+Mounting Hole 6.5mm
+mounting hole 6.5mm
+0
+1
+1
+MountingHole
+MountingHole_6.5mm_Pad_Via
+Mounting Hole 6.5mm
+mounting hole 6.5mm
+0
+9
+1
+MountingHole
+MountingHole_6mm
+Mounting Hole 6mm, no annular
+mounting hole 6mm no annular
+0
+0
+0
+MountingHole
+MountingHole_6mm_Pad
+Mounting Hole 6mm
+mounting hole 6mm
+0
+1
+1
+MountingHole
+MountingHole_6mm_Pad_Via
+Mounting Hole 6mm
+mounting hole 6mm
+0
+9
+1
+MountingHole
+MountingHole_8.4mm_M8
+Mounting Hole 8.4mm, no annular, M8
+mounting hole 8.4mm no annular m8
+0
+0
+0
+MountingHole
+MountingHole_8.4mm_M8_Pad
+Mounting Hole 8.4mm, M8
+mounting hole 8.4mm m8
+0
+1
+1
+MountingHole
+MountingHole_8.4mm_M8_Pad_Via
+Mounting Hole 8.4mm, M8
+mounting hole 8.4mm m8
+0
+9
+1
+NetTie
+NetTie-2_SMD_Pad0.5mm
+Net tie, 2 pin, 0.5mm square SMD pads
+net tie
+0
+2
+2
+NetTie
+NetTie-2_SMD_Pad2.0mm
+Net tie, 2 pin, 2.0mm square SMD pads
+net tie
+0
+2
+2
+NetTie
+NetTie-2_THT_Pad0.3mm
+Net tie, 2 pin, 0.3mm round THT pads
+net tie
+0
+2
+2
+NetTie
+NetTie-2_THT_Pad1.0mm
+Net tie, 2 pin, 1.0mm round THT pads
+net tie
+0
+2
+2
+NetTie
+NetTie-3_SMD_Pad0.5mm
+Net tie, 3 pin, 0.5mm square SMD pads
+net tie
+0
+3
+3
+NetTie
+NetTie-3_SMD_Pad2.0mm
+Net tie, 3 pin, 2.0mm square SMD pads
+net tie
+0
+3
+3
+NetTie
+NetTie-3_THT_Pad0.3mm
+Net tie, 3 pin, 0.3mm round THT pads
+net tie
+0
+3
+3
+NetTie
+NetTie-3_THT_Pad1.0mm
+Net tie, 3 pin, 1.0mm round THT pads
+net tie
+0
+3
+3
+NetTie
+NetTie-4_SMD_Pad0.5mm
+Net tie, 4 pin, 0.5mm square SMD pads
+net tie
+0
+4
+4
+NetTie
+NetTie-4_SMD_Pad2.0mm
+Net tie, 4 pin, 2.0mm square SMD pads
+net tie
+0
+4
+4
+NetTie
+NetTie-4_THT_Pad0.3mm
+Net tie, 4 pin, 0.3mm round THT pads
+net tie
+0
+4
+4
+NetTie
+NetTie-4_THT_Pad1.0mm
+Net tie, 4 pin, 1.0mm round THT pads
+net tie
+0
+4
+4
+OptoDevice
+ADNS-9800
+Laser Gaming Sensor ADNS-9800
+MOUSE MOUSE_SENSOR LASER_GAMING_SENSOR
+0
+16
+16
+OptoDevice
+AGILENT_HFBR-152x
+Fiberoptic Transmitter TX, HFBR series (https://docs.broadcom.com/docs/AV02-3283EN)
+Fiberoptic Transmitter
+0
+6
+6
+OptoDevice
+AGILENT_HFBR-252x
+Fiberoptic Receiver RX, HFBR series (https://docs.broadcom.com/docs/AV02-3283EN)
+Fiberoptic Transmitter
+0
+6
+6
+OptoDevice
+AMS_TSL2550_SMD
+http://ams.com/eng/content/download/250130/975613/142977
+TSL2550 ambient light sensor
+0
+4
+4
+OptoDevice
+Broadcom_AFBR-16xxZ_Horizontal
+Fiber Optic Transmitter and Receiver, https://docs.broadcom.com/docs/AV02-4369EN
+Fiber Optic Transmitter and Receiver
+0
+6
+6
+OptoDevice
+Broadcom_AFBR-16xxZ_Tilted
+Fiber Optic Transmitter and Receiver, https://docs.broadcom.com/docs/AV02-4369EN
+Fiber Optic Transmitter and Receiver
+0
+6
+6
+OptoDevice
+Broadcom_AFBR-16xxZ_Vertical
+Fiber Optic Transmitter and Receiver, https://docs.broadcom.com/docs/AV02-4369EN
+Fiber Optic Transmitter and Receiver
+0
+6
+6
+OptoDevice
+Broadcom_APDS-9301
+ambient light sensor, i2c interface, 6-pin chipled package, https://docs.broadcom.com/docs/AV02-2315EN
+ambient light sensor chipled
+0
+6
+6
+OptoDevice
+Broadcom_DFN-6_2x2mm_P0.65mm
+Broadcom  DFN, 6 Pin (https://docs.broadcom.com/docs/AV02-4755EN), generated with kicad-footprint-generator ipc_noLead_generator.py
+Broadcom DFN NoLead
+0
+6
+6
+OptoDevice
+Broadcom_LGA-8_2x2mm_P0.53mm
+Broadcom  LGA, 8 Pin (https://docs.broadcom.com/docs/AV02-4755EN), generated with kicad-footprint-generator ipc_noLead_generator.py
+Broadcom LGA NoLead
+0
+8
+8
+OptoDevice
+Everlight_ITR8307
+package for Everlight ITR8307 with PCB cutout, light-direction upwards, see http://www.everlight.com/file/ProductFile/ITR8307.pdf
+refective opto couple photo coupler
+0
+4
+4
+OptoDevice
+Everlight_ITR8307F43
+package for Everlight ITR8307/F43, see https://everlighteurope.com/index.php?controller=attachment&id_attachment=5385
+refective opto couple photo coupler
+0
+4
+4
+OptoDevice
+Everlight_ITR8307_Reverse
+package for Everlight ITR8307 with PCB cutout, light-direction downwards, see http://www.everlight.com/file/ProductFile/ITR8307.pdf
+refective opto couple photo coupler
+0
+4
+4
+OptoDevice
+Finder_34.81
+Relay SPST, Finder Type 34.81 (opto relays/coupler), vertical/standing form, see https://gfinder.findernet.com/public/attachments/34/EN/S34USAEN.pdf
+Relay SPST Finder
+0
+4
+4
+OptoDevice
+Hamamatsu_C12880
+Hamamatsu spectrometer, see http://www.hamamatsu.com/resources/pdf/ssd/c12880ma_kacc1226e.pdf
+opto spectrometer Hamamatsu
+0
+10
+10
+OptoDevice
+Hamamatsu_S13360-30CS
+SiPM, 2pin
+Hamamatsu SiPM
+0
+2
+2
+OptoDevice
+Kingbright_KPS-5130
+http://www.kingbright.com/attachments/file/psearch/000/00/00/KPS-5130PD7C(Ver.14).pdf
+KPS-5130 photodiode RGB sensor
+0
+4
+4
+OptoDevice
+Kingbright_KRC011_Horizontal
+Subminiature Reflective Optical Sensor, http://www.kingbright.com/attachments/file/psearch/000/00/00/KRC011(Ver.15).pdf
+Subminiature Reflective Optical Sensor
+0
+4
+4
+OptoDevice
+Kingbright_KRC011_Vertical
+Subminiature Reflective Optical Sensor, http://www.kingbright.com/attachments/file/psearch/000/00/00/KRC011(Ver.15).pdf
+Subminiature Reflective Optical Sensor
+0
+4
+4
+OptoDevice
+Kodenshi_LG206D
+http://kodenshi.co.jp/products/pdf/sensor/photointerrupter_ic/LG206D.pdf
+Photointerrupter  infrared LED with photo IC
+0
+5
+5
+OptoDevice
+Kodenshi_LG206L
+http://kodenshi.co.jp/products/pdf/sensor/photointerrupter_ic/LG205L.pdf
+Photointerrupter  infrared LED with photo IC
+0
+5
+5
+OptoDevice
+Kodenshi_SG105
+package for Kodenshi SG-105 with PCB cutout, light-direction upwards, see http://www.kodenshi.co.jp/products/pdf/sensor/photointerrupter_ref/SG-105.pdf
+refective opto couple photo coupler
+0
+4
+4
+OptoDevice
+Kodenshi_SG105F
+package for Kodenshi SG-105F, see http://www.kodenshi.co.jp/products/pdf/sensor/photointerrupter_ref/SG-105F.pdf
+refective opto couple photo coupler
+0
+4
+4
+OptoDevice
+Kodenshi_SG105_Reverse
+package for Kodenshi SG-105 with PCB cutout, light-direction downwards, see http://www.kodenshi.co.jp/products/pdf/sensor/photointerrupter_ref/SG-105.pdf
+refective opto couple photo coupler
+0
+4
+4
+OptoDevice
+LaserDiode_TO3.3-D3.3-3
+Laser Diode, TO-3.3mm, 3pin
+Laser Diode TO3.3
+0
+3
+3
+OptoDevice
+LaserDiode_TO5-D9-3
+Laser Diode, TO5-like (D=9mm), 3pin
+Laser Diode TO5-like
+0
+3
+3
+OptoDevice
+LaserDiode_TO18-D5.6-3
+Laser Diode, TO18-like (D=5.6mm), 3pin
+Laser Diode TO18-like
+0
+3
+3
+OptoDevice
+LaserDiode_TO38ICut-3
+Laser Diode, TO-38-ICut, 3pin
+Laser Diode TO38-ICut
+0
+3
+3
+OptoDevice
+LaserDiode_TO56-3
+Laser Diode, TO-56, 3pin
+Laser Diode TO56
+0
+3
+3
+OptoDevice
+Lightpipe_LPF-C012303S
+https://www.lumex.com/spec/LPF-C012303S.pdf
+lightpipe dual tower right angle 3mm
+0
+0
+0
+OptoDevice
+Lightpipe_Mentor_1276.1004
+https://www.mentor-bauelemente.de/katalog/ll/MENTOR-LL.pdf
+spherical light pipe 4 way 3mm PLCC-2 PLCC-4
+0
+0
+0
+OptoDevice
+Lightpipe_Mentor_1276.2004
+https://www.mentor-bauelemente.de/katalog/ll/MENTOR-LL.pdf
+planar light pipe 4 way 3mm PLCC-2 PLCC-4
+0
+0
+0
+OptoDevice
+Lite-On_LTR-303ALS-01
+ambient light sensor, i2c interface, 6-pin chipled package, http://optoelectronics.liteon.com/upload/download/DS86-2013-0004/LTR-303ALS-01_DS_V1.pdf
+ambient light sensor chipled
+0
+6
+6
+OptoDevice
+Luna_NSL-32
+Optoisolator with LED and photoresistor
+optoisolator
+0
+4
+4
+OptoDevice
+Maxim_OLGA-14_3.3x5.6mm_P0.8mm
+https://pdfserv.maximintegrated.com/land_patterns/90-0602.PDF
+OLGA-14 OESIP-14
+0
+14
+14
+OptoDevice
+ONSemi_QSE15x
+3 Lead Plastic Package
+ONSemi QSE158 QSE159
+0
+3
+3
+OptoDevice
+OnSemi_CASE100CY
+OnSemi CASE 100CY, light-direction upwards, see http://www.onsemi.com/pub/Collateral/QRE1113-D.PDF
+refective opto couple photo coupler
+0
+4
+4
+OptoDevice
+Osram_BPW82
+PhotoDiode, BPW82, RM2.54
+PhotoDiode BPW82 RM2.54
+0
+2
+2
+OptoDevice
+Osram_DIL2_4.3x4.65mm_P5.08mm
+PhotoDiode, plastic DIL, 4.3x4.65mm², RM5.08
+PhotoDiode plastic DIL RM5.08
+0
+2
+2
+OptoDevice
+Osram_LPT80A
+PhotoTransistor, sidelooker package, RM2.54
+PhotoTransistor sidelooker package RM2.54
+0
+2
+2
+OptoDevice
+Osram_SFH9x0x
+package for Osram SFH9x0x series of reflective photo interrupters/couplers, see http://www.osram-os.com/Graphics/XPic6/00200860_0.pdf
+reflective photo interrupter SMD
+0
+6
+6
+OptoDevice
+Osram_SFH205
+PhotoDiode, SFH205, RM2.54
+PhotoDiode SFH205 RM2.54
+0
+2
+2
+OptoDevice
+Osram_SFH225
+PhotoDiode, SFH225, RM2.54
+PhotoDiode SFH225 RM2.54
+0
+2
+2
+OptoDevice
+Osram_SMD-DIL2_4.5x4.0mm
+PhotoDiode, plastic SMD DIL, 4.5x4mm²
+PhotoDiode plastic SMD DIL
+0
+2
+2
+OptoDevice
+Osram_SMD-SmartDIL
+PhotoDiode, plastic SMD SmatDIL
+PhotoDiode plastic SMD SmatDIL
+0
+3
+3
+OptoDevice
+Panasonic_APV-AQY_SSOP-4_4.45x2.65mm_P1.27mm
+https://www.panasonic-electric-works.com/cps/rde/xbcr/pew_eu_en/technical_information_photomos_en.pdf
+SSOP4 APV21 AQY22
+0
+4
+4
+OptoDevice
+PerkinElmer_VTL5C
+Axial Vactrol (http://www.qsl.net/wa1ion/vactrol/vactrol.pdf)
+vactrol
+0
+4
+4
+OptoDevice
+PerkinElmer_VTL5Cx2
+Axial Vactrol (http://www.qsl.net/wa1ion/vactrol/vactrol.pdf)
+vactrol
+0
+5
+5
+OptoDevice
+R_LDR_4.9x4.2mm_P2.54mm_Vertical
+Resistor, LDR 4.9x4.2mm
+Resistor LDR4.9x4.2
+0
+2
+2
+OptoDevice
+R_LDR_5.0x4.1mm_P3mm_Vertical
+Resistor, LDR 5x4.1mm, see http://cdn-reichelt.de/documents/datenblatt/A500/A90xxxx%23PE.pdf
+Resistor LDR5x4.1mm
+0
+2
+2
+OptoDevice
+R_LDR_5.1x4.3mm_P3.4mm_Vertical
+Resistor, LDR 5.1x3.4mm, see http://yourduino.com/docs/Photoresistor-5516-datasheet.pdf
+Resistor LDR5.1x3.4mm
+0
+2
+2
+OptoDevice
+R_LDR_5.2x5.2mm_P3.5mm_Horizontal
+Resistor, LDR 5.2x5.2, upright, see http://cdn-reichelt.de/documents/datenblatt/A500/M996011A.pdf
+Resistor LDR5.2x5.2 
+0
+2
+2
+OptoDevice
+R_LDR_7x6mm_P5.1mm_Vertical
+Resistor, LDR 7x6mm
+Resistor LDR7x6mm
+0
+2
+2
+OptoDevice
+R_LDR_10x8.5mm_P7.6mm_Vertical
+Resistor, LDR 10x8.5mm
+Resistor LDR10.8.5mm
+0
+2
+2
+OptoDevice
+R_LDR_11x9.4mm_P8.2mm_Vertical
+Resistor, LDR 11x9.4mm
+Resistor LDR11x9.4mm
+0
+2
+2
+OptoDevice
+R_LDR_12x10.8mm_P9.0mm_Vertical
+Resistor, LDR 12x10.8mm, see http://yourduino.com/docs/Photoresistor-5516-datasheet.pdf
+Resistor LDR12x10.8mm
+0
+2
+2
+OptoDevice
+R_LDR_D6.4mm_P3.4mm_Vertical
+Resistor, LDR D=6.4mm, see http://yourduino.com/docs/Photoresistor-5516-datasheet.pdf
+Resistor LDRD=6.4mm
+0
+2
+2
+OptoDevice
+R_LDR_D13.8mm_P9.0mm_Vertical
+Resistor, diameter 13.8mm pitch 9mm, see http://yourduino.com/docs/Photoresistor-5516-datasheet.pdf
+Resistor LDR 
+0
+2
+2
+OptoDevice
+R_LDR_D20mm_P17.5mm_Vertical
+Resistor, LDR 20mm diameter, pin pitch 17.5mm, see http://yourduino.com/docs/Photoresistor-5516-datasheet.pdf
+Resistor LDR
+0
+2
+2
+OptoDevice
+ST_VL53L0X
+https://www.st.com/resource/en/datasheet/vl53l1x.pdf
+laser-ranging sensor
+0
+12
+12
+OptoDevice
+ST_VL53L1X
+https://www.st.com/resource/en/datasheet/vl53l1x.pdf
+laser-ranging sensor
+0
+12
+12
+OptoDevice
+Sharp_GP2Y0A41SK0F
+http://www.sharp-world.com/products/device/lineup/data/pdf/datasheet/gp2y0a41sk_e.pdf
+Distance Sensor Sharp
+0
+2
+2
+OptoDevice
+Sharp_IS471F
+Sharp OPIC IS471F, see http://pdf.datasheetcatalog.com/datasheet/Sharp/mXvrzty.pdf
+Sharp OPIC IS471F
+0
+4
+4
+OptoDevice
+Sharp_IS485
+Sharp OPIC, IS485, IS486, see http://microrato.ua.pt/main/Actividades/Estagios/Docs/IS485_6.pdf
+Sharp OPIC IS485 IS486
+0
+3
+3
+OptoDevice
+Siemens_SFH900
+package for Siemens SFH900 reflex photo interrupter/coupler/object detector, see https://www.batronix.com/pdf/sfh900.pdf
+Siemens SFH900 reflex photo interrupter coupler object detector
+0
+3
+3
+OptoDevice
+Toshiba_TORX170_TORX173_TORX193_TORX194
+Fiberoptic Reciver, RX, Toshiba, Toslink, TORX170, TORX173, TORX193, TORX194
+Fiberoptic Reciver RX Toshiba Toslink TORX170 TORX173 TORX193 TORX194
+0
+6
+6
+OptoDevice
+Toshiba_TOTX170_TOTX173_TOTX193_TOTX194
+Fiberoptic Reciver, RX, Toshiba, Toslink, TORX170, TORX173, TORX193, TORX194
+Fiberoptic Reciver RX Toshiba Toslink TORX170 TORX173 TORX193 TORX194
+0
+6
+6
+OptoDevice
+Vishay_CAST-3Pin
+IR Receiver Vishay TSOP-xxxx, CAST package, see https://www.vishay.com/docs/82493/tsop311.pdf
+IRReceiverVishayTSOP-xxxx CAST
+0
+3
+3
+OptoDevice
+Vishay_CNY70
+package for Vishay CNY70 refective photo coupler/interrupter
+Vishay CNY70 refective photo coupler
+0
+4
+4
+OptoDevice
+Vishay_MINICAST-3Pin
+IR Receiver Vishay TSOP-xxxx, MINICAST package, see https://www.vishay.com/docs/82669/tsop32s40f.pdf
+IR Receiver Vishay TSOP-xxxx MINICAST
+0
+3
+3
+OptoDevice
+Vishay_MINIMOLD-3Pin
+IR Receiver Vishay TSOP-xxxx, MINIMOLD package, see https://www.vishay.com/docs/82742/tsop331.pdf
+IR Receiver Vishay TSOP-xxxx MINIMOLD
+0
+3
+3
+OptoDevice
+Vishay_MOLD-3Pin
+IR Receiver Vishay TSOP-xxxx, MOLD package, see https://www.vishay.com/docs/82669/tsop32s40f.pdf
+IR Receiver Vishay TSOP-xxxx MOLD
+0
+3
+3
+Oscillator
+Oscillator_DIP-8
+Oscillator, DIP8,http://cdn-reichelt.de/documents/datenblatt/B400/OSZI.pdf
+oscillator
+0
+4
+4
+Oscillator
+Oscillator_DIP-8_LargePads
+Oscillator, DIP8, Large Pads, http://cdn-reichelt.de/documents/datenblatt/B400/OSZI.pdf
+oscillator
+0
+4
+4
+Oscillator
+Oscillator_DIP-14
+Oscillator, DIP14, http://cdn-reichelt.de/documents/datenblatt/B400/OSZI.pdf
+oscillator
+0
+4
+4
+Oscillator
+Oscillator_DIP-14_LargePads
+Oscillator, DIP14, Large Pads, http://cdn-reichelt.de/documents/datenblatt/B400/OSZI.pdf
+oscillator
+0
+4
+4
+Oscillator
+Oscillator_OCXO_Morion_MV267
+http://www.morion.com.ru/catalog_pdf/MV267.pdf
+OCXO
+0
+5
+5
+Oscillator
+Oscillator_OCXO_Morion_MV317
+https://www.morion-us.com/catalog_pdf/mv317.pdf
+OCXO
+0
+5
+5
+Oscillator
+Oscillator_SMD_Abracon_ABLNO
+https://abracon.com/Precisiontiming/ABLNO.pdf
+VCXO XO
+0
+4
+4
+Oscillator
+Oscillator_SMD_Abracon_ASCO-4Pin_1.6x1.2mm
+Miniature Crystal Clock Oscillator Abracon ASCO series, https://abracon.com/Oscillators/ASCO.pdf, 1.6x1.2mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_Abracon_ASDMB-4Pin_2.5x2.0mm
+Miniature Crystal Clock Oscillator Abracon ASDMB series, 2.5x2.0mm package, http://www.abracon.com/Oscillators/ASDMB.pdf
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_Abracon_ASE-4Pin_3.2x2.5mm
+Miniature Crystal Clock Oscillator Abracon ASE series, http://www.abracon.com/Oscillators/ASEseries.pdf, 3.2x2.5mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_Abracon_ASE-4Pin_3.2x2.5mm_HandSoldering
+Miniature Crystal Clock Oscillator Abracon ASE series, http://www.abracon.com/Oscillators/ASEseries.pdf, hand-soldering, 3.2x2.5mm^2 package
+SMD SMT crystal oscillator hand-soldering
+0
+4
+4
+Oscillator
+Oscillator_SMD_Abracon_ASV-4Pin_7.0x5.1mm
+Miniature Crystal Clock Oscillator Abracon ASV series, http://www.abracon.com/Oscillators/ASV.pdf, 7.0x5.1mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_Abracon_ASV-4Pin_7.0x5.1mm_HandSoldering
+Miniature Crystal Clock Oscillator Abracon ASV series, http://www.abracon.com/Oscillators/ASV.pdf, hand-soldering, 7.0x5.1mm^2 package
+SMD SMT crystal oscillator hand-soldering
+0
+4
+4
+Oscillator
+Oscillator_SMD_Diodes_FN-4Pin_7.0x5.0mm
+FN Series Crystal Clock Oscillator (XO) (https://www.diodes.com/assets/Datasheets/FN_3-3V.pdf)
+Oscillator Crystal SMD SMT
+0
+4
+4
+Oscillator
+Oscillator_SMD_ECS_2520MV-xxx-xx-4Pin_2.5x2.0mm
+Miniature Crystal Clock Oscillator ECS 2520MV series, https://www.ecsxtal.com/store/pdf/ECS-2520MV.pdf
+Miniature Crystal Clock Oscillator ECS 2520MV series SMD SMT HCMOS
+0
+4
+4
+Oscillator
+Oscillator_SMD_EuroQuartz_XO32-4Pin_3.2x2.5mm
+Miniature Crystal Clock Oscillator EuroQuartz XO32 series, http://cdn-reichelt.de/documents/datenblatt/B400/XO32.pdf, 3.2x2.5mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_EuroQuartz_XO32-4Pin_3.2x2.5mm_HandSoldering
+Miniature Crystal Clock Oscillator EuroQuartz XO32 series, http://cdn-reichelt.de/documents/datenblatt/B400/XO32.pdf, hand-soldering, 3.2x2.5mm^2 package
+SMD SMT crystal oscillator hand-soldering
+0
+4
+4
+Oscillator
+Oscillator_SMD_EuroQuartz_XO53-4Pin_5.0x3.2mm
+Miniature Crystal Clock Oscillator EuroQuartz XO53 series, http://cdn-reichelt.de/documents/datenblatt/B400/XO53.pdf, 5.0x3.2mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_EuroQuartz_XO53-4Pin_5.0x3.2mm_HandSoldering
+Miniature Crystal Clock Oscillator EuroQuartz XO53 series, http://cdn-reichelt.de/documents/datenblatt/B400/XO53.pdf, hand-soldering, 5.0x3.2mm^2 package
+SMD SMT crystal oscillator hand-soldering
+0
+4
+4
+Oscillator
+Oscillator_SMD_EuroQuartz_XO91-4Pin_7.0x5.0mm
+Miniature Crystal Clock Oscillator EuroQuartz XO91 series, http://cdn-reichelt.de/documents/datenblatt/B400/XO91.pdf, 7.0x5.0mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_EuroQuartz_XO91-4Pin_7.0x5.0mm_HandSoldering
+Miniature Crystal Clock Oscillator EuroQuartz XO91 series, http://cdn-reichelt.de/documents/datenblatt/B400/XO91.pdf, hand-soldering, 7.0x5.0mm^2 package
+SMD SMT crystal oscillator hand-soldering
+0
+4
+4
+Oscillator
+Oscillator_SMD_Fordahl_DFAS1-6Pin_14.8x9.1mm
+Miniature Crystal Clock Oscillator TXCO Fordahl DFA S1-KHZ/LHZ, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 14.8x9.1mm^2 package
+SMD SMT crystal oscillator
+0
+6
+6
+Oscillator
+Oscillator_SMD_Fordahl_DFAS2-4Pin_7.3x5.1mm
+Mminiature Crystal Clock Oscillator TXCO Fordahl DFA S2-KS/LS/US, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 7.3x5.1mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_Fordahl_DFAS2-4Pin_7.3x5.1mm_HandSoldering
+Mminiature Crystal Clock Oscillator TXCO Fordahl DFA S2-KS/LS/US, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 7.3x5.1mm^2 package
+SMD SMT crystal oscillator hand-soldering
+0
+4
+4
+Oscillator
+Oscillator_SMD_Fordahl_DFAS3-4Pin_9.1x7.2mm
+Miniature Crystal Clock Oscillator TXCO Fordahl DFA S3-KS/LS/US, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 9.1x7.2mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_Fordahl_DFAS3-4Pin_9.1x7.2mm_HandSoldering
+Miniature Crystal Clock Oscillator TXCO Fordahl DFA S3-KS/LS/US, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 9.1x7.2mm^2 package
+SMD SMT crystal oscillator hand-soldering
+0
+4
+4
+Oscillator
+Oscillator_SMD_Fordahl_DFAS7-4Pin_19.9x12.9mm
+Miniature Crystal Clock Oscillator TXCO Fordahl DFA S7-K/L, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 19.9x12.9mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_Fordahl_DFAS7-4Pin_19.9x12.9mm_HandSoldering
+Miniature Crystal Clock Oscillator TXCO Fordahl DFA S7-K/L, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 19.9x12.9mm^2 package
+SMD SMT crystal oscillator hand-soldering
+0
+4
+4
+Oscillator
+Oscillator_SMD_Fordahl_DFAS11-4Pin_7.0x5.0mm
+Miniature Crystal Clock Oscillator TXCO Fordahl DFA S11-OV/UOV, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 7.0x5.0mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_Fordahl_DFAS11-4Pin_7.0x5.0mm_HandSoldering
+Miniature Crystal Clock Oscillator TXCO Fordahl DFA S11-OV/UOV, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 7.0x5.0mm^2 package
+SMD SMT crystal oscillator hand-soldering
+0
+4
+4
+Oscillator
+Oscillator_SMD_Fordahl_DFAS15-4Pin_5.0x3.2mm
+Ultraminiature Crystal Clock Oscillator TXCO Fordahl DFA S15-OV/UOV, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 5.0x3.2mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_Fordahl_DFAS15-4Pin_5.0x3.2mm_HandSoldering
+Ultraminiature Crystal Clock Oscillator TXCO Fordahl DFA S15-OV/UOV, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 5.0x3.2mm^2 package
+SMD SMT crystal oscillator hand-soldering
+0
+4
+4
+Oscillator
+Oscillator_SMD_IDT_JS6-6_5.0x3.2mm_P1.27mm
+SMD Crystal Oscillator IDT https://www.idt.com/document/dst/xu-family-datasheet#page=15, 5.0x3.2mm
+SMD SMT crystal oscillator
+0
+6
+6
+Oscillator
+Oscillator_SMD_IDT_JU6-6_7.0x5.0mm_P2.54mm
+SMD Crystal Oscillator IDT https://www.idt.com/document/dst/xu-family-datasheet#page=17, 7.0x5.0mm
+SMD SMT crystal oscillator
+0
+6
+6
+Oscillator
+Oscillator_SMD_IQD_IQXO70-4Pin_7.5x5.0mm
+IQD Crystal Clock Oscillator IQXO-70, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 7.5x5.0mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_IQD_IQXO70-4Pin_7.5x5.0mm_HandSoldering
+IQD Crystal Clock Oscillator IQXO-70, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 7.5x5.0mm^2 package
+SMD SMT crystal oscillator hand-soldering
+0
+4
+4
+Oscillator
+Oscillator_SMD_Kyocera_2520-6Pin_2.5x2.0mm
+https://global.kyocera.com/prdct/electro/product/pdf/kt2520_e.pdf
+2.5mm 2mm SMD
+0
+6
+6
+Oscillator
+Oscillator_SMD_OCXO_ConnorWinfield_OH300
+http://www.conwin.com/datasheets/cx/cx282.pdf
+OCXO
+0
+7
+7
+Oscillator
+Oscillator_SMD_SI570_SI571_HandSoldering
+SI570, SI571, Programmable oscillator, Standard
+SI570 SI571 Programmable oscillator Standard
+0
+8
+8
+Oscillator
+Oscillator_SMD_SI570_SI571_Standard
+SI570, SI571, Programmable oscillator, Standard
+SI570 SI571 Programmable oscillator Standard
+0
+8
+8
+Oscillator
+Oscillator_SMD_SeikoEpson_SG210-4Pin_2.5x2.0mm
+SMD Crystal Oscillator Seiko Epson SG-210 https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-210SED, 2.5x2.0mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_SeikoEpson_SG210-4Pin_2.5x2.0mm_HandSoldering
+SMD Crystal Oscillator Seiko Epson SG-210 https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-210SED, hand-soldering, 2.5x2.0mm^2 package
+SMD SMT crystal oscillator hand-soldering
+0
+4
+4
+Oscillator
+Oscillator_SMD_SeikoEpson_SG3030CM
+SMD Crystal Oscillator Seiko Epson SG-3030CM package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_SeikoEpson_SG8002CA-4Pin_7.0x5.0mm
+SMD Crystal Oscillator Seiko Epson SG-8002CA https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, 7.0x5.0mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_SeikoEpson_SG8002CA-4Pin_7.0x5.0mm_HandSoldering
+SMD Crystal Oscillator Seiko Epson SG-8002CA https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, hand-soldering, 7.0x5.0mm^2 package
+SMD SMT crystal oscillator hand-soldering
+0
+4
+4
+Oscillator
+Oscillator_SMD_SeikoEpson_SG8002CE-4Pin_3.2x2.5mm
+SMD Crystal Oscillator Seiko Epson SG-8002CE https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, 3.2x2.5mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_SeikoEpson_SG8002CE-4Pin_3.2x2.5mm_HandSoldering
+SMD Crystal Oscillator Seiko Epson SG-8002CE https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, hand-soldering, 3.2x2.5mm^2 package
+SMD SMT crystal oscillator hand-soldering
+0
+4
+4
+Oscillator
+Oscillator_SMD_SeikoEpson_SG8002JA-4Pin_14.0x8.7mm
+SMD Crystal Oscillator Seiko Epson SG-8002JA https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, 14.0x8.7mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_SeikoEpson_SG8002JA-4Pin_14.0x8.7mm_HandSoldering
+SMD Crystal Oscillator Seiko Epson SG-8002JA https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, hand-soldering, 14.0x8.7mm^2 package
+SMD SMT crystal oscillator hand-soldering
+0
+4
+4
+Oscillator
+Oscillator_SMD_SeikoEpson_SG8002JC-4Pin_10.5x5.0mm
+SMD Crystal Oscillator Seiko Epson SG-8002JC https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, 10.5x5.0mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_SeikoEpson_SG8002JC-4Pin_10.5x5.0mm_HandSoldering
+SMD Crystal Oscillator Seiko Epson SG-8002JC https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, hand-soldering, 10.5x5.0mm^2 package
+SMD SMT crystal oscillator hand-soldering
+0
+4
+4
+Oscillator
+Oscillator_SMD_SeikoEpson_SG8002LB-4Pin_5.0x3.2mm
+SMD Crystal Oscillator Seiko Epson SG-8002LB https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, 5.0x3.2mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_SeikoEpson_SG8002LB-4Pin_5.0x3.2mm_HandSoldering
+SMD Crystal Oscillator Seiko Epson SG-8002LB https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, hand-soldering, 5.0x3.2mm^2 package
+SMD SMT crystal oscillator hand-soldering
+0
+4
+4
+Oscillator
+Oscillator_SMD_Silicon_Labs_LGA-6_2.5x3.2mm_P1.25mm
+Silicon_Labs  LGA, 6 Pin (https://www.silabs.com/documents/public/data-sheets/si512-13.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+Silicon_Labs LGA NoLead
+0
+6
+6
+Oscillator
+Oscillator_SMD_TCXO_G158
+TCXO
+TCXO
+0
+4
+4
+Oscillator
+Oscillator_SMD_TXC_7C-4Pin_5.0x3.2mm
+Miniature Crystal Clock Oscillator TXC 7C series, http://www.txccorp.com/download/products/osc/7C_o.pdf, 5.0x3.2mm^2 package
+SMD SMT crystal oscillator
+0
+4
+4
+Oscillator
+Oscillator_SMD_TXC_7C-4Pin_5.0x3.2mm_HandSoldering
+Miniature Crystal Clock Oscillator TXC 7C series, http://www.txccorp.com/download/products/osc/7C_o.pdf, hand-soldering, 5.0x3.2mm^2 package
+SMD SMT crystal oscillator hand-soldering
+0
+4
+4
+Oscillator
+Oscillator_SeikoEpson_SG-8002DB
+14-lead dip package, row spacing 7.62 mm (300 mils)
+DIL DIP PDIP 2.54mm 7.62mm 300mil
+0
+4
+4
+Oscillator
+Oscillator_SeikoEpson_SG-8002DC
+8-lead dip package, row spacing 7.62 mm (300 mils)
+DIL DIP PDIP 2.54mm 7.62mm 300mil
+0
+4
+4
+Package_BGA
+Analog_BGA-28_4.0x6.25mm_Layout4x7_P0.8mm_Ball0.45mm_Pad0.4
+Analog BGA-28 4.0mm x 6.25mm package, pitch 0.4mm pad, based on https://www.analog.com/media/en/technical-documentation/data-sheets/8063fa.pdf
+BGA 28 0.8
+0
+28
+28
+Package_BGA
+BGA-9_1.6x1.6mm_Layout3x3_P0.5mm
+BGA-9, http://www.ti.com/lit/ds/symlink/bq27421-g1.pdf
+BGA-9
+0
+9
+9
+Package_BGA
+BGA-16_1.92x1.92mm_Layout4x4_P0.5mm
+BGA-16, http://www.st.com/content/ccc/resource/technical/document/datasheet/group2/bc/cd/62/9e/8f/30/47/69/CD00151267/files/CD00151267.pdf/jcr:content/translations/en.CD00151267.pdf
+BGA-16
+0
+16
+16
+Package_BGA
+BGA-25_6.35x6.35mm_Layout5x5_P1.27mm
+BGA-25, http://cds.linear.com/docs/en/datasheet/4624fc.pdf
+BGA-25 uModule
+0
+25
+25
+Package_BGA
+BGA-36_3.396x3.466mm_Layout6x6_P0.4mm_Ball0.25mm_Pad0.2mm_NSMD
+Altera V36, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00486-00.pdf
+Altera BGA-36 V36 VBGA
+0
+36
+36
+Package_BGA
+BGA-48_8.0x9.0mm_Layout6x8_P0.8mm
+BGA-48 - pitch 0.8 mm
+BGA-48
+0
+48
+48
+Package_BGA
+BGA-64_9.0x9.0mm_Layout10x10_P0.8mm
+BGA-64, 10x10 raster, 9x9mm package, pitch 0.8mm
+BGA-64
+0
+64
+64
+Package_BGA
+BGA-68_5.0x5.0mm_Layout9x9_P0.5mm_Ball0.3mm_Pad0.25mm_NSMD
+Altera MBGA-68, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00344-01.pdf
+Altera BGA-68 M68 MBGA
+0
+68
+68
+Package_BGA
+BGA-81_4.496x4.377mm_Layout9x9_P0.4mm_Ball0.25mm_Pad0.2mm_NSMD
+Altera V81, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00478-01.pdf
+Altera VBGA V81 BGA-81
+0
+81
+81
+Package_BGA
+BGA-90_8.0x13.0mm_Layout2x3x15_P0.8mm
+BGA-90, http://www.issi.com/WW/pdf/42-45S32800J.pdf
+BGA-90
+0
+90
+90
+Package_BGA
+BGA-96_9.0x13.0mm_Layout2x3x16_P0.8mm
+BGA-96, http://www.mouser.com/ds/2/198/43-46TR16640B-81280BL-706483.pdf
+BGA-96
+0
+96
+96
+Package_BGA
+BGA-100_6.0x6.0mm_Layout11x11_P0.5mm_Ball0.3mm_Pad0.25mm_NSMD
+Altera MBGA-100, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00345-01.pdf
+Altera BGA-100 M100 MBGA
+0
+100
+100
+Package_BGA
+BGA-100_11.0x11.0mm_Layout10x10_P1.0mm_Ball0.5mm_Pad0.4mm_NSMD
+BGA-100, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00223-02.pdf
+BGA-100
+0
+100
+100
+Package_BGA
+BGA-121_9.0x9.0mm_Layout11x11_P0.8mm_Ball0.4mm_Pad0.35mm_NSMD
+121-ball, 0.8mm BGA (based on http://www.latticesemi.com/view_document?document_id=213)
+BGA 0.8mm 9mm 121
+0
+121
+121
+Package_BGA
+BGA-121_12.0x12.0mm_Layout11x11_P1.0mm
+BGA-121, http://cds.linear.com/docs/en/packaging/05081891_A_bga121.pdf
+BGA-121
+0
+121
+121
+Package_BGA
+BGA-132_12x18mm_Layout11x17_P0.5mm
+BGA-132 11x17 12x18mm 0.5pitch
+BGA-132
+0
+132
+132
+Package_BGA
+BGA-144_7.0x7.0mm_Layout13x13_P0.5mm_Ball0.3mm_Pad0.25mm_NSMD
+Altera MBGA-144, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00346-00.pdf
+Altera BGA-144 M144 MBGA
+0
+144
+144
+Package_BGA
+BGA-144_13.0x13.0mm_Layout12x12_P1.0mm
+BGA-144, http://www.topline.tv/drawings/pdf/BGA%201,0mm%20pitch/LBGA144T1.0-DC128.pdf
+BGA-144
+0
+144
+144
+Package_BGA
+BGA-152_14x18mm_Layout13x17_P0.5mm
+BGA-152_14x18mm_Layout13x17_P0.5mm
+VBGA-152
+0
+152
+152
+Package_BGA
+BGA-153_8.0x8.0mm_Layout15x15_P0.5mm_Ball0.3mm_Pad0.25mm_NSMD
+Altera MBGA-153, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00471-00.pdf
+Altera BGA-153 M153 MBGA
+0
+153
+153
+Package_BGA
+BGA-169_11.0x11.0mm_Layout13x13_P0.8mm_Ball0.5mm_Pad0.4mm_NSMD
+Altera U169, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00470-01.pdf
+Altera UBGA U169 BGA-169
+0
+169
+169
+Package_BGA
+BGA-256_11.0x11.0mm_Layout20x20_P0.5mm_Ball0.3mm_Pad0.25mm_NSMD
+Altera MBGA-256, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00348-01.pdf
+Altera BGA-256 M256 MBGA
+0
+256
+256
+Package_BGA
+BGA-256_14.0x14.0mm_Layout16x16_P0.8mm_Ball0.45mm_Pad0.32mm_NSMD
+BGA-256, dimensions: https://www.xilinx.com/support/documentation/package_specs/ft256.pdf, design rules: https://www.xilinx.com/support/documentation/user_guides/ug1099-bga-device-design-rules.pdf
+BGA-256
+0
+256
+256
+Package_BGA
+BGA-256_17.0x17.0mm_Layout16x16_P1.0mm_Ball0.5mm_Pad0.4mm_NSMD
+BGA-256, dimensions: https://www.xilinx.com/support/documentation/package_specs/ft256.pdf, design rules: https://www.xilinx.com/support/documentation/user_guides/ug1099-bga-device-design-rules.pdf
+BGA-256
+0
+256
+256
+Package_BGA
+BGA-324_15.0x15.0mm_Layout18x18_P0.8mm_Ball0.5mm_Pad0.4mm_NSMD
+Altera U324, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00474-02.pdf
+Altera UBGA U324 BGA-324
+0
+324
+324
+Package_BGA
+BGA-324_19.0x19.0mm_Layout18x18_P1.0mm_Ball0.5mm_Pad0.4mm_NSMD
+BGA-324, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00233-03.pdf
+BGA-324
+0
+324
+324
+Package_BGA
+BGA-352_35.0x35.0mm_Layout26x26_P1.27mm
+BGA-352, https://www.fujitsu.com/downloads/MICRO/fma/pdfmcu/b352p05.pdf
+BGA-352
+0
+352
+352
+Package_BGA
+BGA-400_21.0x21.0mm_Layout20x20_P1.0mm
+BGA-400, https://www.xilinx.com/support/documentation/package_specs/fg400.pdf
+BGA-400
+0
+400
+400
+Package_BGA
+BGA-484_23.0x23.0mm_Layout22x22_P1.0mm
+BGA-484, https://www.xilinx.com/support/documentation/package_specs/fg484.pdf
+BGA-484
+0
+484
+484
+Package_BGA
+BGA-624_21.0x21.0mm_Layout25x25_P0.8mm
+BGA-624, 25x25 grid, 21x21mm package, pitch 0.8mm; https://www.nxp.com/docs/en/package-information/SOT1529-1.pdf
+BGA 624 0.8
+0
+624
+624
+Package_BGA
+BGA-625_21.0x21.0mm_Layout25x25_P0.8mm
+BGA-625
+BGA-625
+0
+625
+625
+Package_BGA
+BGA-672_27.0x27.0mm_Layout26x26_P1.0mm_Ball0.6mm_Pad0.5mm_NSMD
+Altera BGA-672, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00472-00.pdf
+Altera BGA-672 F672 FBGA
+0
+672
+672
+Package_BGA
+BGA-676_27.0x27.0mm_Layout26x26_P1.0mm_Ball0.6mm_Pad0.5mm_NSMD
+XILINX BGA-676, https://www.xilinx.com/support/documentation/package_specs/fg676.pdf
+XILINX BGA-676 FG676/FGG676
+0
+676
+676
+Package_BGA
+BGA-1023_33.0x33.0mm_Layout32x32_P1.0mm
+BGA-1023
+BGA-1023
+0
+1023
+1023
+Package_BGA
+BGA-1156_35.0x35.0mm_Layout34x34_P1.0mm
+BGA-1156
+BGA-1156
+0
+1156
+1156
+Package_BGA
+BGA-1295_37.5x37.5mm_Layout36x36_P1.0mm
+BGA-1295
+BGA-1295
+0
+1295
+1295
+Package_BGA
+FB-BGA-484_23.0x23.0mm_Layout22x22_P1.0mm
+Xilinx FB-484, https://www.xilinx.com/support/documentation/user_guides/ug1099-bga-device-design-rules.pdf
+FB-BGA-484
+0
+484
+484
+Package_BGA
+FBGA-78_7.5x11mm_Layout2x3x13_P0.8mm
+FBGA-78, https://www.skhynix.com/product/filedata/fileDownload.do?seq=7687
+FBGA-78
+0
+78
+78
+Package_BGA
+Fujitsu_WLP-15_2.28x3.092mm_Layout3x5_P0.4mm
+WLP-15, 3x5 raster, 2.28x3.092mm package, pitch 0.4mm; http://www.fujitsu.com/global/documents/products/devices/semiconductor/fram/lineup/MB85RS1MT-DS501-00022-7v0-E.pdf
+BGA 8 0.4
+0
+8
+8
+Package_BGA
+LFBGA-100_10x10mm_Layout10x10_P0.8mm
+LFBGA-100, 10x10 raster, 10x10mm package, pitch 0.8mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f103tb.pdf
+BGA 100 0.8
+0
+100
+100
+Package_BGA
+LFBGA-144_10x10mm_Layout12x12_P0.8mm
+LFBGA-144, 12x12 raster, 10x10mm package, pitch 0.8mm; see section 6.1 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf
+BGA 144 0.8
+0
+144
+144
+Package_BGA
+LFBGA-169_16x12mm_Layout28x14_P0.5mm_Ball0.3_Pad0.3mm_NSMD
+https://4donline.ihs.com/images/VipMasterIC/IC/SGST/SGSTS20279/SGSTS20279-1.pdf?hkey=EF798316E3902B6ED9A73243A3159BB0
+eMMC Flash LFBGA169
+0
+169
+169
+Package_BGA
+Lattice_caBGA-381_17.0x17.0mm_Layout20x20_P0.8mm_Ball0.4mm_Pad0.4mm_NSMD
+Lattice caBGA-381 footprint for ECP5 FPGAs, based on http://www.latticesemi.com/view_document?document_id=213
+BGA 381 0.8
+0
+381
+381
+Package_BGA
+Lattice_caBGA-381_17.0x17.0mm_Layout20x20_P0.8mm_Ball0.4mm_Pad0.6mm_SMD
+Lattice caBGA-381 footprint for ECP5 FPGAs, based on http://www.latticesemi.com/view_document?document_id=213
+BGA 381 0.8
+0
+381
+381
+Package_BGA
+Linear_BGA-133_15.0x15.0_Layout12x12_P1.27mm
+Analog Devices (Linear Tech), 133-pin BGA uModule, 15.0x15.0x4.92mm, https://www.analog.com/media/en/technical-documentation/data-sheets/4637fc.pdf
+133 pin bga
+0
+134
+134
+Package_BGA
+Maxim_WLP-12
+Maxim_WLP-12 W121B2+1 http://pdfserv.maximintegrated.com/package_dwgs/21-0009.PDF
+Maxim_WLP-12
+0
+12
+12
+Package_BGA
+TFBGA-64_5x5mm_Layout8x8_P0.5mm
+TFBGA-64, 8x8 raster, 5x5mm package, pitch 0.5mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f100v8.pdf
+BGA 64 0.5
+0
+64
+64
+Package_BGA
+TFBGA-100_8x8mm_Layout10x10_P0.8mm
+TFBGA-100, 10x10 raster, 8x8mm package, pitch 0.8mm; see section 6.2 of http://www.st.com/resource/en/datasheet/stm32f746zg.pdf
+BGA 100 0.8
+0
+100
+100
+Package_BGA
+TFBGA-100_9.0x9.0mm_Layout10x10_P0.8mm
+TFBGA-100, 10x10, 9x9mm package, pitch 0.8mm
+TFBGA-100
+0
+100
+100
+Package_BGA
+TFBGA-121_10x10mm_Layout11x11_P0.8mm
+TFBGA-121, 11x11 raster, 10x10mm package, pitch 0.8mm; http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#p495
+BGA 121 0.8
+0
+121
+121
+Package_BGA
+TFBGA-216_13x13mm_Layout15x15_P0.8mm
+TFBGA-216, 15x15 raster, 13x13mm package, pitch 0.8mm; see section 6.8 of http://www.st.com/resource/en/datasheet/stm32f746zg.pdf
+BGA 216 0.8
+0
+216
+216
+Package_BGA
+TFBGA-265_14x14mm_Layout17x17_P0.8mm
+TFBGA-265, 17x17 raster, 14x14mm package, pitch 0.8mm; see section 7.8 of http://www.st.com/resource/en/datasheet/DM00387108.pdf
+BGA 265 0.8
+0
+265
+265
+Package_BGA
+Texas_DSBGA-5_0.822x1.116mm_Layout2x1x2_P0.4mm
+Texas Instruments, DSBGA, 0.822x1.116mm, 5 bump 2x1x2 array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/opa330.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf)
+Texas Instruments DSBGA BGA YFF S-XBGA-N5
+0
+10
+5
+Package_BGA
+Texas_DSBGA-6_0.9x1.4mm_Layout2x3_P0.5mm
+Texas Instruments, DSBGA, 0.9x1.4mm, 6 bump 2x3 (perimeter) array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/ts5a3159a.pdf)
+Texas Instruments DSBGA BGA YZP R-XBGA-N6
+0
+12
+6
+Package_BGA
+Texas_DSBGA-8_0.9x1.9mm_Layout2x4_P0.5mm
+Texas Instruments, DSBGA, 0.9x1.9mm, 8 bump 2x4 (perimeter) array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/txb0102.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf)
+Texas Instruments DSBGA BGA YZP R-XBGA-N8
+0
+16
+8
+Package_BGA
+Texas_DSBGA-8_1.43x1.41mm_Layout3x3_P0.5mm
+Texas Instruments, DSBGA, 1.43x1.41mm, 8 bump 3x3 (perimeter) array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/lmc555.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf)
+Texas Instruments DSBGA BGA YZP R-XBGA-N8
+0
+16
+8
+Package_BGA
+Texas_DSBGA-8_1.5195x1.5195mm_Layout3x3_P0.5mm
+Texas Instruments, DSBGA, 1.5195x1.5195x0.600mm, 8 ball 3x3 area grid, YZR pad definition (http://www.ti.com/lit/ml/mxbg270/mxbg270.pdf)
+BGA 8 0.5
+0
+8
+8
+Package_BGA
+Texas_DSBGA-9_1.4715x1.4715mm_Layout3x3_P0.5mm
+Texas Instruments, DSBGA, 1.4715x1.4715mm, 9 bump 3x3 array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/lm4990.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf)
+Texas Instruments DSBGA BGA YZR0009
+0
+18
+9
+Package_BGA
+Texas_DSBGA-10_1.36x1.86mm_Layout3x4_P0.5mm
+Texas Instruments, DSBGA, 1.36x1.86mm, 10 bump 3x4 (perimeter) array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/txs0104e.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf)
+Texas Instruments DSBGA BGA
+0
+20
+10
+Package_BGA
+Texas_DSBGA-12_1.36x1.86mm_Layout3x4_P0.5mm
+Texas Instruments, DSBGA, 1.36x1.86mm, 12 bump 3x4 (area) array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/txs0104e.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf)
+Texas Instruments DSBGA BGA
+0
+24
+12
+Package_BGA
+Texas_DSBGA-28_1.9x3.0mm_Layout4x7_P0.4mm
+Texas Instruments, DSBGA, 3.0x1.9x0.625mm, 28 ball 7x4 area grid, NSMD pad definition (http://www.ti.com/lit/ds/symlink/bq51050b.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf)
+BGA 28 0.4
+0
+28
+28
+Package_BGA
+Texas_DSBGA-49_3.33x3.488mm_Layout7x7_P0.4mm
+Texas Instruments, DSBGA, 3.33x3.488x0.625mm, 49 ball 7x7 area grid, NSMD pad definition (http://www.ti.com/lit/ds/symlink/msp430f2234.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf)
+texas dsbga 49
+0
+49
+49
+Package_BGA
+Texas_DSBGA-64_3.415x3.535mm_Layout8x8_P0.4mm
+Texas Instruments, DSBGA, 3.415x3.535x0.625mm, 64 ball 8x8 area grid, NSMD pad definition (http://www.ti.com/lit/ds/slas718g/slas718g.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf)
+texas dsbga 64
+0
+64
+64
+Package_BGA
+Texas_MicroStar_Junior_BGA-12_2.0x2.5mm_Layout4x3_P0.5mm
+Texas Instruments, BGA Microstar Junior, 2x2.5mm, 12 bump 4x3 grid, NSMD pad definition (http://www.ti.com/lit/ds/symlink/txb0104.pdf, http://www.ti.com/lit/wp/ssyz015b/ssyz015b.pdf)
+Texas_Junior_BGA-12
+0
+12
+12
+Package_BGA
+Texas_MicroStar_Junior_BGA-80_5.0x5.0mm_Layout9x9_P0.5mm
+Texas Instruments, BGA Microstar Junior, 5x5mm, 80 ball 9x9 grid, NSMD pad definition (http://www.ti.com/lit/ds/symlink/tlv320aic23b.pdf, http://www.ti.com/lit/wp/ssyz015b/ssyz015b.pdf)
+Texas_Junior_BGA-80
+0
+80
+80
+Package_BGA
+Texas_MicroStar_Junior_BGA-113_7.0x7.0mm_Layout12x12_P0.5mm
+Texas Instruments, BGA Microstar Junior, 7x7mm, 113 ball 12x12 grid, NSMD pad definition (http://www.ti.com/lit/ml/mpbg674/mpbg674.pdf, http://www.ti.com/lit/wp/ssyz015b/ssyz015b.pdf)
+Texas_Junior_BGA-113
+0
+113
+113
+Package_BGA
+UCBGA-36_2.5x2.5mm_Layout6x6_P0.4mm
+UCBGA-36, 6x6 raster, 2.5x2.5mm package, pitch 0.4mm; https://www.latticesemi.com/view_document?document_id=213
+BGA 36 0.4
+0
+36
+36
+Package_BGA
+UCBGA-49_3x3mm_Layout7x7_P0.4mm
+UCBGA-49, 7x7 raster, 3x3mm package, pitch 0.4mm; https://www.latticesemi.com/view_document?document_id=213
+BGA 49 0.4
+0
+49
+49
+Package_BGA
+UCBGA-81_4x4mm_Layout9x9_P0.4mm
+UCBGA-81, 9x9 raster, 4x4mm package, pitch 0.4mm; https://www.latticesemi.com/view_document?document_id=213
+BGA 81 0.4
+0
+81
+81
+Package_BGA
+UFBGA-15_3.0x3.0mm_Layout4x4_P0.65mm
+UFBGA-15, 4x4, 3x3mm package, pitch 0.65mm
+UFBGA-15
+0
+15
+15
+Package_BGA
+UFBGA-32_4.0x4.0mm_Layout6x6_P0.5mm
+UFBGA-32, 6x6, 4x4mm package, pitch 0.5mm
+UFBGA-32
+0
+32
+32
+Package_BGA
+UFBGA-64_5x5mm_Layout8x8_P0.5mm
+UFBGA-64, 8x8 raster, 5x5mm package, pitch 0.5mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f051t8.pdf
+BGA 64 0.5
+0
+64
+64
+Package_BGA
+UFBGA-100_7x7mm_Layout12x12_P0.5mm
+UFBGA-100, 12x12 raster, 7x7mm package, pitch 0.5mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f103tb.pdf
+BGA 100 0.5
+0
+100
+100
+Package_BGA
+UFBGA-132_7x7mm_Layout12x12_P0.5mm
+UFBGA-132, 12x12 raster, 7x7mm package, pitch 0.5mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32l152zc.pdf
+BGA 132 0.5
+0
+132
+132
+Package_BGA
+UFBGA-132_7x7mm_P0.5mm
+UFBGA 132 Pins, 0.5mm Pitch, 0.3mm Ball, http://www.st.com/resource/en/datasheet/stm32l486qg.pdf
+ufbga bga small-pitch
+0
+132
+132
+Package_BGA
+UFBGA-144_7x7mm_Layout12x12_P0.5mm
+UFBGA-144, 12x12 raster, 7x7mm package, pitch 0.5mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32f446ze.pdf
+BGA 144 0.5
+0
+144
+144
+Package_BGA
+UFBGA-144_10x10mm_Layout12x12_P0.8mm
+UFBGA-144, 12x12 raster, 10x10mm package, pitch 0.8mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f446ze.pdf
+BGA 144 0.8
+0
+144
+144
+Package_BGA
+UFBGA-169_7x7mm_Layout13x13_P0.5mm
+UFBGA-169, 13x13 raster, 7x7mm package, pitch 0.5mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f429ng.pdf
+BGA 169 0.5
+0
+169
+169
+Package_BGA
+UFBGA-201_10x10mm_Layout15x15_P0.65mm
+UFBGA-201, 15x15 raster, 10x10mm package, pitch 0.65mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f207vg.pdf
+BGA 201 0.65
+0
+201
+201
+Package_BGA
+VFBGA-49_5.0x5.0mm_Layout7x7_P0.65mm
+VFBGA-49, 7x7, 5x5mm package, pitch 0.65mm
+VFBGA-49
+0
+49
+49
+Package_BGA
+VFBGA-100_7.0x7.0mm_Layout10x10_P0.65mm
+VFBGA-100, 10x10, 7x7mm package, pitch 0.65mm
+VFBGA-100
+0
+100
+100
+Package_BGA
+WLP-4_0.73x0.73mm_Layout2x2_P0.35mm_Ball0.22mm_Pad0.2mm_NSMD
+WLP-4, 2x2 raster, 0.73x0.73mm package, pitch 0.35mm; https://datasheets.maximintegrated.com/en/ds/MAX40200.pdf
+BGA 4 0.35
+0
+4
+4
+Package_BGA
+WLP-4_0.83x0.83mm_P0.4mm
+WLP-4_0.83x0.83mm_P0.4mm https://pdfserv.maximintegrated.com/package_dwgs/21-100107.PDF, https://www.maximintegrated.com/en/app-notes/index.mvp/id/1891
+WLP-4
+0
+4
+4
+Package_BGA
+WLP-4_0.86x0.86mm_P0.4mm
+WLP-4_0.86x0.86mm_P0.4mm https://pdfserv.maximintegrated.com/package_dwgs/21-0612.PDF, https://www.maximintegrated.com/en/app-notes/index.mvp/id/1891
+WLP-4
+0
+4
+4
+Package_BGA
+XBGA-121_10x10mm_Layout11x11_P0.8mm
+XBGA-121, 11x11 raster, 10x10mm package, pitch 0.6mm; http://ww1.microchip.com/downloads/en/DeviceDoc/39969b.pdf
+BGA 121 0.8
+0
+121
+121
+Package_BGA
+XFBGA-36_3.5x3.5mm_Layout6x6_P0.5mm
+XFBGA-36, https://www.nxp.com/docs/en/package-information/SOT1555-1.pdf
+XFBGA-36
+0
+36
+36
+Package_BGA
+XFBGA-64_5.0x5.0mm_Layout8x8_P0.5mm
+XFBGA-64, https://www.nxp.com/docs/en/package-information/SOT1555-1.pdf
+XFBGA-64
+0
+64
+64
+Package_BGA
+XFBGA-121_8x8mm_Layout11x11_P0.65mm
+XFBGA-121, https://www.nxp.com/docs/en/package-information/SOT1533-1.pdf
+XFBGA-121
+0
+121
+121
+Package_BGA
+Xilinx_CLG225
+Zynq-7000 BGA, 15x15 grid, 13x13mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=77, NSMD pad definition Appendix A
+BGA 225 0.8 CLG225
+0
+225
+225
+Package_BGA
+Xilinx_CLG400
+Zynq-7000 BGA, 20x20 grid, 17x17mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=78, NSMD pad definition Appendix A
+BGA 400 0.8 CLG400 CL400
+0
+400
+400
+Package_BGA
+Xilinx_CLG484_CLG485
+Zynq-7000 BGA, 22x22 grid, 19x19mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=79, NSMD pad definition Appendix A
+BGA 484 0.8 CLG484 CL484 CLG485 CL485
+0
+484
+484
+Package_BGA
+Xilinx_CPG236
+Artix-7 BGA, 19x19 grid, 10x10mm package, 0.5mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=266, NSMD pad definition Appendix A
+BGA 238 0.5 CP236 CPG236
+0
+238
+238
+Package_BGA
+Xilinx_CPG238
+Artix-7 BGA, 19x19 grid, 10x10mm package, 0.5mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=267, NSMD pad definition Appendix A
+BGA 238 0.5 CPG238
+0
+238
+238
+Package_BGA
+Xilinx_CPGA196
+Spartan-7 BGA, 14x14 grid, 8x8mm package, 0.5mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=260, NSMD pad definition Appendix A
+BGA 196 0.5 CPGA196
+0
+196
+196
+Package_BGA
+Xilinx_CSG324
+Artix-7 BGA, 18x18 grid, 15x15mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=268, NSMD pad definition Appendix A
+BGA 324 0.8 CS324 CSG324
+0
+324
+324
+Package_BGA
+Xilinx_CSG325
+Artix-7 BGA, 18x18 grid, 15x15mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=268, NSMD pad definition Appendix A
+BGA 324 0.8 CS325 CSG235
+0
+324
+324
+Package_BGA
+Xilinx_CSGA225
+Spartan-7 BGA, 15x15 grid, 13x13mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=262, NSMD pad definition Appendix A
+BGA 225 0.8 CSGA225
+0
+225
+225
+Package_BGA
+Xilinx_CSGA324
+Spartan-7 BGA, 18x18 grid, 15x15mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=263, NSMD pad definition Appendix A
+BGA 324 0.8 CSGA324
+0
+324
+324
+Package_BGA
+Xilinx_FBG484
+Artix-7, Kintex-7 and Zynq-7000 BGA, 22x22 grid, 23x23mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=271, ttps://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=281, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=82, NSMD pad definition Appendix A
+BGA 484 1 FB484 FBG484 FBV484
+0
+484
+484
+Package_BGA
+Xilinx_FBG676
+Artix-7, Kintex-7 and Zynq-7000 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=273, https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=284, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=84, NSMD pad definition Appendix A
+BGA 676 1 FB676 FBG676 FBV676
+0
+676
+676
+Package_BGA
+Xilinx_FBG900
+Kintex-7 BGA, 30x30 grid, 31x31mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=289, NSMD pad definition Appendix A
+BGA 900 1 FB900 FBG900 FBV900
+0
+900
+900
+Package_BGA
+Xilinx_FFG676
+Kintex-7 and Zynq-7000 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=292, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=88, NSMD pad definition Appendix A
+BGA 676 1 FF676 FFG676 FFV676
+0
+676
+676
+Package_BGA
+Xilinx_FFG900_FFG901
+Kintex-7 and Zynq-7000 BGA, 30x30 grid, 31x31mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=294, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=90, NSMD pad definition Appendix A
+BGA 900 1 FF900 FFG900 FFV900 FF901 FFG901 FFV901
+0
+900
+900
+Package_BGA
+Xilinx_FFG1156
+Artix-7, Kintex-7 and Zynq-7000 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=277, https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=296, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=91, NSMD pad definition Appendix A
+BGA 1156 1 FF1156 FFG1156 FFV1156
+0
+1156
+1156
+Package_BGA
+Xilinx_FFG1157_FFG1158
+Virtex-7 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=299, NSMD pad definition Appendix A
+BGA 1156 1 FF1157 FFG1157 FFV1157 FF1158 FFG1158 FFV1158
+0
+1156
+1156
+Package_BGA
+Xilinx_FFG1761
+Virtex-7 BGA, 42x42 grid, 42.5x42.5mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=300, NSMD pad definition Appendix A
+BGA 1760 1 FF1761 FFG1761
+0
+1760
+1760
+Package_BGA
+Xilinx_FFG1926_FFG1927_FFG1928_FFG1930
+Virtex-7 BGA, 44x44 grid, 45x45mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=303, NSMD pad definition Appendix A
+BGA 1924 1 FF1926 FFG1926 FF1927 FFG1927 FFV1927 FF1928 FFG1928 FF1930 FFG1930
+0
+1924
+1924
+Package_BGA
+Xilinx_FFV1761
+Virtex-7 BGA, 42x42 grid, 42.5x42.5mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=301, NSMD pad definition Appendix A
+BGA 1760 1 FFV1761
+0
+1760
+1760
+Package_BGA
+Xilinx_FGG484
+Artix-7 BGA, 22x22 grid, 23x23mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=275, NSMD pad definition Appendix A
+BGA 484 1 FG484 FGG484
+0
+484
+484
+Package_BGA
+Xilinx_FGG676
+Artix-7 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=276, NSMD pad definition Appendix A
+BGA 676 1 FG676 FGG676
+0
+676
+676
+Package_BGA
+Xilinx_FGGA484
+Spartan-7 BGA, 22x22 grid, 23x23mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=264, NSMD pad definition Appendix A
+BGA 484 1 FGGA484
+0
+484
+484
+Package_BGA
+Xilinx_FGGA676
+Spartan-7 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=265, NSMD pad definition Appendix A
+BGA 676 1 FGGA676
+0
+676
+676
+Package_BGA
+Xilinx_FHG1761
+Virtex-7 BGA, 42x42 grid, 45x45mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=302, NSMD pad definition Appendix A
+BGA 1760 1 FH1761 FHG1761
+0
+1760
+1760
+Package_BGA
+Xilinx_FLG1925_FLG1926_FLG1928_FLG1930
+Virtex-7 BGA, 44x44 grid, 45x45mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=304, NSMD pad definition Appendix A
+BGA 1924 1 FL1925 FLG1925 FL1926 FLG1926 FL1928 FLG1928 FL1930 FLG1930
+0
+1924
+1924
+Package_BGA
+Xilinx_FTG256
+Artix-7 BGA, 16x16 grid, 17x17mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=269, NSMD pad definition Appendix A
+BGA 256 1 FT256 FTG256
+0
+256
+256
+Package_BGA
+Xilinx_FTGB196
+Spartan-7 BGA, 14x14 grid, 15x15mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=261, NSMD pad definition Appendix A
+BGA 196 1 FTGB196
+0
+196
+196
+Package_BGA
+Xilinx_RB484
+Artix-7 and Zynq-7000 BGA, 22x22 grid, 23x23mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=278, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=92, NSMD pad definition Appendix A
+BGA 484 1 RB484
+0
+484
+484
+Package_BGA
+Xilinx_RB676
+Artix-7 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=280, NSMD pad definition Appendix A
+BGA 676 1 RB676
+0
+676
+676
+Package_BGA
+Xilinx_RF676
+Kintex-7 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=297, NSMD pad definition Appendix A
+BGA 676 1 RF676
+0
+676
+676
+Package_BGA
+Xilinx_RF900
+Kintex-7 and Zynq-7000 BGA, 30x30 grid, 31x31mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=298, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=94, NSMD pad definition Appendix A
+BGA 900 1 RF900
+0
+900
+900
+Package_BGA
+Xilinx_RF1156
+Zynq-7000 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=95, NSMD pad definition Appendix A
+BGA 1156 1 RF1156
+0
+1156
+1156
+Package_BGA
+Xilinx_RF1157_RF1158
+Virtex-7 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=305, NSMD pad definition Appendix A
+BGA 1156 1 RF1157 RF1158
+0
+1156
+1156
+Package_BGA
+Xilinx_RF1761
+Virtex-7 BGA, 42x42 grid, 42.5x42.5mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=306, NSMD pad definition Appendix A
+BGA 1760 1 RF1761
+0
+1760
+1760
+Package_BGA
+Xilinx_RF1930
+Virtex-7 BGA, 44x44 grid, 45x45mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=307, NSMD pad definition Appendix A
+BGA 1924 1 RF1930
+0
+1924
+1924
+Package_BGA
+Xilinx_RFG676
+Zynq-7000 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=93, NSMD pad definition Appendix A
+BGA 676 1 RF676 RFG676
+0
+676
+676
+Package_BGA
+Xilinx_RS484
+Artix-7 BGA, 22x22 grid, 19x19mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=279, NSMD pad definition Appendix A
+BGA 484 0.8 RS484
+0
+484
+484
+Package_BGA
+Xilinx_SBG484
+Artix-7 BGA, 22x22 grid, 19x19mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=270, NSMD pad definition Appendix A
+BGA 484 0.8 SB484 SBG484 SBV484
+0
+484
+484
+Package_BGA
+Xilinx_SBG485
+Zynq-7000 BGA, 22x22 grid, 19x19mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=80, NSMD pad definition Appendix A
+BGA 484 0.8 SBG485 SBV485
+0
+484
+484
+Package_CSP
+Analog_LFCSP-8-1EP_3x3mm_P0.5mm_EP1.53x1.85mm
+LFCSP, exposed pad, Analog Devices (http://www.analog.com/media/en/technical-documentation/data-sheets/ADL5542.pdf)
+LFCSP 8 0.5
+0
+12
+5
+Package_CSP
+LFCSP-8-1EP_3x2mm_P0.5mm_EP1.6x1.65mm
+LFCSP 8pin Pitch 0.5mm, http://www.analog.com/media/en/package-pcb-resources/package/57080735642908cp_8_4.pdf
+LFCSP 8pin thermal pad 3x2mm Pitch 0.5mm
+0
+9
+9
+Package_CSP
+LFCSP-8-1EP_3x3mm_P0.5mm_EP1.45x1.74mm
+LFCSP, 8 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-8/CP_8_13.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+LFCSP DFN_QFN
+0
+13
+9
+Package_CSP
+LFCSP-8_2x2mm_P0.5mm
+LFCSP 8pin Pitch 0.5mm, http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_8_6.pdf
+LFCSP 8pin 2x2mm Pitch 0.5mm
+0
+8
+8
+Package_CSP
+LFCSP-16-1EP_3x3mm_P0.5mm_EP1.6x1.6mm
+LFCSP, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-16/CP_16_22.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+21
+17
+Package_CSP
+LFCSP-16-1EP_3x3mm_P0.5mm_EP1.6x1.6mm_ThermalVias
+LFCSP, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-16/CP_16_22.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+26
+17
+Package_CSP
+LFCSP-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
+LFCSP, 16 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/HMC7992.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+21
+17
+Package_CSP
+LFCSP-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm_ThermalVias
+LFCSP, 16 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/HMC7992.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+26
+17
+Package_CSP
+LFCSP-16-1EP_3x3mm_P0.5mm_EP1.854x1.854mm
+16-Lead Lead Frame Chip Scale Package, 3x3mm, 0.5mm pitch, 1.854mm thermal pad (CP-16-22, http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_16_22.pdf)
+LFCSP 16 0.5
+0
+21
+17
+Package_CSP
+LFCSP-16-1EP_4x4mm_P0.65mm_EP2.1x2.1mm
+LFCSP, 16 pin, 4x4mm, 2.1mm sq pad (http://www.analog.com/media/en/technical-documentation/data-sheets/ADG633.pdf)
+LFCSP 16 0.65
+0
+21
+17
+Package_CSP
+LFCSP-16-1EP_4x4mm_P0.65mm_EP2.4x2.4mm
+LFCSP, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-16/cp-16-40.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+21
+17
+Package_CSP
+LFCSP-16-1EP_4x4mm_P0.65mm_EP2.4x2.4mm_ThermalVias
+LFCSP, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-16/cp-16-40.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+31
+17
+Package_CSP
+LFCSP-20-1EP_4x4mm_P0.5mm_EP2.1x2.1mm
+20-Lead Frame Chip Scale Package - 4x4x0.9 mm Body [LFCSP], (see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_20_6.pdf)
+LFCSP 0.5
+0
+25
+21
+Package_CSP
+LFCSP-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
+LFCSP, 20 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/AD7682_7689.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+LFCSP DFN_QFN
+0
+25
+21
+Package_CSP
+LFCSP-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm_ThermalVias
+LFCSP, 20 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/AD7682_7689.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+LFCSP DFN_QFN
+0
+35
+21
+Package_CSP
+LFCSP-20-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
+LFCSP, 20 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-20/CP_20_8.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+25
+21
+Package_CSP
+LFCSP-20-1EP_4x4mm_P0.5mm_EP2.6x2.6mm_ThermalVias
+LFCSP, 20 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-20/CP_20_8.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+35
+21
+Package_CSP
+LFCSP-24-1EP_4x4mm_P0.5mm_EP2.3x2.3mm
+LFCSP, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_24_14.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+29
+25
+Package_CSP
+LFCSP-24-1EP_4x4mm_P0.5mm_EP2.3x2.3mm_ThermalVias
+LFCSP, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_24_14.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+39
+25
+Package_CSP
+LFCSP-24-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
+LFCSP, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_24_7.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+29
+25
+Package_CSP
+LFCSP-24-1EP_4x4mm_P0.5mm_EP2.5x2.5mm_ThermalVias
+LFCSP, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_24_7.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+39
+25
+Package_CSP
+LFCSP-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm
+LFCSP, 32 Pin (https://www.analog.com/media/en/package-pcb-resources/package/414143737956480539664569cp_32_2.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+42
+33
+Package_CSP
+LFCSP-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm_ThermalVias
+LFCSP, 32 Pin (https://www.analog.com/media/en/package-pcb-resources/package/414143737956480539664569cp_32_2.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+59
+33
+Package_CSP
+LFCSP-32-1EP_5x5mm_P0.5mm_EP3.25x3.25mm
+32-Lead Frame Chip Scale Package LFCSP (5mm x 5mm); (see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-32/CP_32_27.pdf
+LFCSP 0.5
+0
+37
+33
+Package_CSP
+LFCSP-48-1EP_7x7mm_P0.5mm_EP4.1x4.1mm
+LFCSP, 48 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_48_5.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+58
+49
+Package_CSP
+LFCSP-48-1EP_7x7mm_P0.5mm_EP4.1x4.1mm_ThermalVias
+LFCSP, 48 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_48_5.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+75
+49
+Package_CSP
+LFCSP-64-1EP_9x9mm_P0.5mm_EP5.21x5.21mm
+LFCSP, 64 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_64_7.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+69
+65
+Package_CSP
+LFCSP-64-1EP_9x9mm_P0.5mm_EP5.21x5.21mm_ThermalVias
+LFCSP, 64 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_64_7.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+86
+65
+Package_CSP
+LFCSP-72-1EP_10x10mm_P0.5mm_EP5.3x5.3mm
+LFCSP, 72 Pin (http://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1452_1451_1450.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+82
+73
+Package_CSP
+LFCSP-72-1EP_10x10mm_P0.5mm_EP5.3x5.3mm_ThermalVias
+LFCSP, 72 Pin (http://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1452_1451_1450.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP NoLead
+0
+99
+73
+Package_CSP
+LFCSP-72-1EP_10x10mm_P0.5mm_EP6.15x6.15mm
+72-Lead Frame Chip Scale Package - 10x10x0.9 mm Body [LFCSP]; (see https://www.intersil.com/content/dam/Intersil/documents/l72_/l72.10x10c.pdf)
+LFCSP 0.5
+0
+77
+73
+Package_CSP
+LFCSP-VQ-24-1EP_4x4mm_P0.5mm_EP2.642x2.642mm
+LFCSP VQ, 24 pin, exposed pad, 4x4mm body, pitch 0.5mm (http://www.analog.com/media/en/package-pcb-resources/package/56702234806764cp_24_3.pdf, http://www.analog.com/media/en/technical-documentation/data-sheets/ADL5801.pdf)
+LFCSP 0.5
+0
+29
+25
+Package_CSP
+LFCSP-VQ-48-1EP_7x7mm_P0.5mm
+LFCSP VQ, 48 pin, exposed pad, 7x7mm body (http://www.analog.com/media/en/technical-documentation/data-sheets/AD7951.pdf, http://www.analog.com/en/design-center/packaging-quality-symbols-footprints/symbols-and-footprints/AD7951.html)
+LFCSP 48
+0
+49
+49
+Package_CSP
+LFCSP-WD-10-1EP_3x3mm_P0.5mm_EP1.64x2.38mm
+LFCSP-WD, 10 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-10/CP_10_9.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP-WD NoLead
+0
+17
+11
+Package_CSP
+LFCSP-WD-10-1EP_3x3mm_P0.5mm_EP1.64x2.38mm_ThermalVias
+LFCSP-WD, 10 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-10/CP_10_9.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LFCSP-WD NoLead
+0
+24
+11
+Package_CSP
+ST_WLCSP-25_Die425
+WLCSP-25, 5x5 raster, 2.097x2.493mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l031f6.pdf
+BGA 25 0.4
+0
+25
+25
+Package_CSP
+ST_WLCSP-25_Die444
+WLCSP-25, 5x5 raster, 2.423x2.325mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f031k6.pdf
+BGA 25 0.4
+0
+25
+25
+Package_CSP
+ST_WLCSP-25_Die457
+WLCSP-25, 5x5 raster, 2.133x2.070mm package, pitch 0.4mm; see section 7.3 of http://www.st.com/resource/en/datasheet/stm32l011k3.pdf
+BGA 25 0.4
+0
+25
+25
+Package_CSP
+ST_WLCSP-36_Die417
+WLCSP-36, 6x6 raster, 2.61x2.88mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32l052t8.pdf
+BGA 36 0.4
+0
+36
+36
+Package_CSP
+ST_WLCSP-36_Die440
+WLCSP-36, 6x6 raster, 2.605x2.703mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f051t8.pdf
+BGA 36 0.4
+0
+36
+36
+Package_CSP
+ST_WLCSP-36_Die445
+WLCSP-36, 6x6 raster, 2.605x2.703mm package, pitch 0.4mm; see section 7.3 of http://www.st.com/resource/en/datasheet/stm32f042k6.pdf
+BGA 36 0.4
+0
+36
+36
+Package_CSP
+ST_WLCSP-36_Die458
+WLCSP-36, 6x6 raster, 2.553x2.579mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f410t8.pdf
+BGA 36 0.4
+0
+36
+36
+Package_CSP
+ST_WLCSP-49_Die423
+WLCSP-49, 7x7 raster, 2.965x2.965mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f401vc.pdf
+BGA 49 0.4
+0
+49
+49
+Package_CSP
+ST_WLCSP-49_Die431
+WLCSP-49, 7x7 raster, 2.999x3.185mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f411vc.pdf
+BGA 49 0.4
+0
+49
+49
+Package_CSP
+ST_WLCSP-49_Die433
+WLCSP-49, 7x7 raster, 3.029x3.029mm package, pitch 0.4mm; see section 7.1.1 of http://www.st.com/resource/en/datasheet/stm32f401ce.pdf
+BGA 49 0.4
+0
+49
+49
+Package_CSP
+ST_WLCSP-49_Die435
+WLCSP-49, 7x7 raster, 3.141x3.127mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/DM00257211.pdf
+BGA 49 0.4
+0
+49
+49
+Package_CSP
+ST_WLCSP-49_Die438
+WLCSP-49, 7x7 raster, 3.89x3.74mm package, pitch 0.5mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f303r8.pdf
+BGA 49 0.5
+0
+49
+49
+Package_CSP
+ST_WLCSP-49_Die439
+WLCSP-49, 7x7 raster, 3.417x3.151mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f301r8.pdf
+BGA 49 0.4
+0
+49
+49
+Package_CSP
+ST_WLCSP-49_Die447
+WLCSP-49, 7x7 raster, 3.294x3.258mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l072kz.pdf
+BGA 49 0.4
+0
+49
+49
+Package_CSP
+ST_WLCSP-49_Die448
+WLCSP-49, 7x7 raster, 3.277x3.109mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32f071v8.pdf
+BGA 49 0.4
+0
+49
+49
+Package_CSP
+ST_WLCSP-63_Die427
+WLCSP-63, 7x9 raster, 3.228x4.164mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l151cc.pdf
+BGA 63 0.4
+0
+63
+63
+Package_CSP
+ST_WLCSP-64_Die414
+WLCSP-64, 8x8 raster, 4.466x4.395mm package, pitch 0.5mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf
+BGA 64 0.5
+0
+64
+64
+Package_CSP
+ST_WLCSP-64_Die427
+WLCSP-64, 8x8 raster, 4.539x4.911mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l152zc.pdf
+BGA 64 0.4
+0
+64
+64
+Package_CSP
+ST_WLCSP-64_Die435
+WLCSP-64, 8x8 raster, 3.141x3.127mm package, pitch 0.35mm; see section 7.5 of http://www.st.com/resource/en/datasheet/DM00257211.pdf
+BGA 64 0.35
+0
+64
+64
+Package_CSP
+ST_WLCSP-64_Die436
+WLCSP-64, 8x8 raster, 4.539x4.911mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l152zd.pdf
+BGA 64 0.4
+0
+64
+64
+Package_CSP
+ST_WLCSP-64_Die441
+WLCSP-64, 8x8 raster, 3.623x3.651mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/DM00213872.pdf
+BGA 64 0.4
+0
+64
+64
+Package_CSP
+ST_WLCSP-64_Die442
+WLCSP-64, 8x8 raster, 3.347x3.585mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32f091vb.pdf
+BGA 64 0.4
+0
+64
+64
+Package_CSP
+ST_WLCSP-64_Die462
+WLCSP-64, 8x8 raster, 3.357x3.657mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/DM00340475.pdf
+BGA 64 0.4
+0
+64
+64
+Package_CSP
+ST_WLCSP-66_Die411
+WLCSP-66, 9x9 raster, 3.639x3.971mm package, pitch 0.4mm; see section 7.2 of http://www.st.com/resource/en/datasheet/stm32f207vg.pdf
+BGA 66 0.4
+0
+66
+66
+Package_CSP
+ST_WLCSP-66_Die432
+WLCSP-66, 8x9 raster, 3.767x4.229mm package, pitch 0.4mm; see section 7.2 of http://www.st.com/resource/en/datasheet/stm32f378vc.pdf
+BGA 66 0.4
+0
+66
+66
+Package_CSP
+ST_WLCSP-72_Die415
+WLCSP-72, 9x9 raster, 4.4084x3.7594mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l476me.pdf
+BGA 72 0.4
+0
+72
+72
+Package_CSP
+ST_WLCSP-81_Die415
+WLCSP-81, 9x9 raster, 4.4084x3.7594mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32l476me.pdf
+BGA 81 0.4
+0
+81
+81
+Package_CSP
+ST_WLCSP-81_Die421
+WLCSP-81, 9x9 raster, 3.693x3.815mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f446ze.pdf
+BGA 81 0.4
+0
+81
+81
+Package_CSP
+ST_WLCSP-81_Die463
+WLCSP-81, 9x9 raster, 4.039x3.951mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/DM00282249.pdf
+BGA 81 0.4
+0
+81
+81
+Package_CSP
+ST_WLCSP-90_Die413
+WLCSP-90, 10x9 raster, 4.223x3.969mm package, pitch 0.4mm; see section 6.1 of http://www.st.com/resource/en/datasheet/stm32f405og.pdf
+BGA 90 0.4
+0
+90
+90
+Package_CSP
+ST_WLCSP-100_Die422
+WLCSP-100, 10x10 raster, 4.201x4.663mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32f302vc.pdf
+BGA 100 0.4
+0
+100
+100
+Package_CSP
+ST_WLCSP-100_Die446
+WLCSP-100, 10x10 raster, 4.775x5.041mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f303zd.pdf
+BGA 100 0.4
+0
+100
+100
+Package_CSP
+ST_WLCSP-100_Die452
+WLCSP-100, 10x10 raster, 4.201x4.663mm package, pitch 0.4mm; see section 7.7 of http://www.st.com/resource/en/datasheet/DM00330506.pdf
+BGA 100 0.4
+0
+100
+100
+Package_CSP
+ST_WLCSP-100_Die461
+WLCSP-100, 10x10 raster, 4.618x4.142mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/DM00284211.pdf
+BGA 100 0.4
+0
+100
+100
+Package_CSP
+ST_WLCSP-104_Die437
+WLCSP-104, 9x12 raster, 4.095x5.094mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l152ze.pdf
+BGA 104 0.4
+0
+104
+104
+Package_CSP
+ST_WLCSP-143_Die419
+WLCSP-143, 11x13 raster, 4.521x5.547mm package, pitch 0.4mm; see section 7.2 of http://www.st.com/resource/en/datasheet/stm32f429ng.pdf
+BGA 143 0.4
+0
+143
+143
+Package_CSP
+ST_WLCSP-143_Die449
+WLCSP-143, 11x13 raster, 4.539x5.849mm package, pitch 0.4mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f746zg.pdf
+BGA 143 0.4
+0
+143
+143
+Package_CSP
+ST_WLCSP-144_Die470
+WLCSP-144, 12x12 raster, 5.24x5.24mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/DM00366448.pdf
+BGA 144 0.4
+0
+144
+144
+Package_CSP
+ST_WLCSP-168_Die434
+WLCSP-168, 12x14 raster, 4.891x5.692mm package, pitch 0.4mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f469ni.pdf
+BGA 168 0.4
+0
+168
+168
+Package_CSP
+ST_WLCSP-180_Die451
+WLCSP-180, 13x14 raster, 5.537x6.095mm package, pitch 0.4mm; see section 6.6 of http://www.st.com/resource/en/datasheet/DM00273119.pdf
+BGA 180 0.4
+0
+180
+180
+Package_CSP
+WLCSP-6_1.4x1.0mm_P0.4mm
+6pin Pitch 0.4mm
+6pin Pitch 0.4mm WLCSP
+0
+6
+6
+Package_CSP
+WLCSP-8_1.58x1.63x0.35mm_Layout3x5_P0.35x0.4mm_Ball0.25mm_Pad0.25mm_NSMD
+WLCSP/XFBGA 8-pin package, staggered pins, http://www.adestotech.com/wp-content/uploads/DS-AT25DF041B_040.pdf
+WLCSP WLCSP-8 XFBGA XFBGA-8  CSP BGA Chip-Scale Glass-Top
+0
+8
+8
+Package_CSP
+WLCSP-12_1.56x1.56mm_P0.4mm
+WLCSP 12 1.56x1.56 https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMM150-DS001-01.pdf
+BMM150 WLCSP
+0
+12
+12
+Package_CSP
+WLCSP-12_1.403x1.555mm_P0.4mm_Stagger
+WLCSP-12, 6x4 raster staggered array, 1.403x1.555mm package, pitch 0.4mm; http://ww1.microchip.com/downloads/en/devicedoc/atmel-8235-8-bit-avr-microcontroller-attiny20_datasheet.pdf#page=208
+CSP 12 0.2x0.346333
+0
+12
+12
+Package_CSP
+WLCSP-16_4x4_B2.17x2.32mm_P0.5mm
+WLCSP-16, http://www.nxp.com/documents/data_sheet/LPC1102_1104.pdf, http://www.nxp.com/assets/documents/data/en/application-notes/AN3846.pdf
+WLCSP-16 NXP
+0
+16
+16
+Package_CSP
+WLCSP-20_1.934x2.434mm_Layout4x5_P0.4mm
+WLCSP-20, 4x5 raster, 1.934x2.434mm package, pitch 0.4mm; see section 36.2.3 of http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42363-SAM-D11_Datasheet.pdf
+BGA 20 0.4
+0
+20
+20
+Package_CSP
+WLCSP-20_1.994x1.94mm_Layout4x5_P0.4mm
+WLCSP-20, https://www.nxp.com/docs/en/package-information/98ASA00539D.pdf
+WLCSP-20
+0
+20
+20
+Package_CSP
+WLCSP-20_1.994x1.609mm_Layout5x4_P0.4mm
+WLCSP-20, https://www.nxp.com/docs/en/package-information/98ASA00676D.pdf
+WLCSP-20
+0
+20
+20
+Package_CSP
+WLCSP-36_2.82x2.67mm_Layout6x6_P0.4mm
+WLCSP-36, https://www.nxp.com/docs/en/package-information/98ASA00949D.pdf
+WLCSP-36
+0
+36
+36
+Package_CSP
+WLCSP-36_2.374x2.459mm_Layout6x6_P0.35mm
+WLCSP-36, https://www.nxp.com/docs/en/package-information/98ASA00604D.pdf
+WLCSP-36
+0
+36
+36
+Package_CSP
+WLCSP-56_3.170x3.444mm_Layout7x8_P0.4mm
+WLCSP-56, 7x8 raster, 3.170x3.444mm package, pitch 0.4mm; see section 48.2.4 of http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001479B.pdf
+BGA 56 0.4
+0
+56
+56
+Package_CSP
+WLCSP-81_4.41x3.76mm_P0.4mm
+WLCSP-81, 9x9, 0.4mm Pitch, http://www.st.com/content/ccc/resource/technical/document/technical_note/92/30/3c/a1/4c/bb/43/6f/DM00103228.pdf/files/DM00103228.pdf/jcr:content/translations/en.DM00103228.pdf
+WLCSP ST
+0
+81
+81
+Package_CSP
+pSemi_CSP-16_1.64x2.04mm_P0.4mm
+pSemi CSP-16 1.64x2.04x0.285mm (http://www.psemi.com/pdf/datasheets/pe29101ds.pdf, http://www.psemi.com/pdf/app_notes/an77.pdf)
+psemi csp 16
+0
+16
+16
+Package_CSP
+pSemi_CSP-16_1.64x2.04mm_P0.4mm_Pad0.18mm
+pSemi CSP-16 1.64x2.04x0.285mm (http://www.psemi.com/pdf/datasheets/pe29101ds.pdf, http://www.psemi.com/pdf/app_notes/an77.pdf)
+psemi csp 16
+0
+16
+16
+Package_DFN_QFN
+AMS_QFN-4-1EP_2x2mm_P0.95mm_EP0.7x1.6mm
+UFD Package, 4-Lead Plastic QFN (2mm x 2mm), http://ams.com/eng/content/download/950231/2267959/483138
+QFN 0.95
+0
+6
+5
+Package_DFN_QFN
+Cypress_QFN-56-1EP_8x8mm_P0.5mm_EP6.22x6.22mm_ThermalVias
+56-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8x0.9 mm Body [QFN] (see datasheet at http://www.cypress.com/file/138911/download and app note at http://www.cypress.com/file/140006/download)
+QFN 0.5
+0
+87
+57
+Package_DFN_QFN
+DFN-6-1EP_1.2x1.2mm_P0.4mm_EP0.3x0.94mm_PullBack
+DFN, 6 Pin (http://www.onsemi.com/pub/Collateral/NCP133-D.PDF), generated with kicad-footprint-generator ipc_noLead_generator.py
+DFN NoLead
+0
+9
+7
+Package_DFN_QFN
+DFN-6-1EP_2x1.8mm_P0.5mm_EP1.2x1.6mm
+DFN, 6 Pin (https://www.diodes.com/assets/Package-Files/U-DFN2018-6.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+DFN NoLead
+0
+11
+7
+Package_DFN_QFN
+DFN-6-1EP_2x2mm_P0.5mm_EP0.61x1.42mm
+DC6 Package; 6-Lead Plastic DFN (2mm x 2mm) (see Linear Technology DFN_6_05-08-1703.pdf)
+DFN 0.5
+0
+9
+7
+Package_DFN_QFN
+DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm
+6-Lead Plastic Dual Flat, No Lead Package (MA) - 2x2x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf)
+DFN 0.65
+0
+9
+7
+Package_DFN_QFN
+DFN-6-1EP_3x2mm_P0.5mm_EP1.65x1.35mm
+DFN, 6 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-dfn/(DCB6)%20DFN%2005-08-1715%20Rev%20A.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+DFN NoLead
+0
+11
+7
+Package_DFN_QFN
+DFN-6-1EP_3x3mm_P0.95mm_EP1.7x2.6mm
+DFN6 3*3 MM, 0.95 PITCH; CASE 506AH-01 (see ON Semiconductor 506AH.PDF)
+DFN 0.95
+0
+13
+7
+Package_DFN_QFN
+DFN-6-1EP_3x3mm_P1mm_EP1.5x2.4mm
+DFN, 6 Pin (https://www.silabs.com/documents/public/data-sheets/Si7020-A20.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+DFN NoLead
+0
+11
+7
+Package_DFN_QFN
+DFN-6_1.3x1.2mm_P0.4mm
+6-Lead Plastic DFN (1.3mm x 1.2mm) 
+DFN 0.4
+0
+6
+6
+Package_DFN_QFN
+DFN-8-1EP_2x2mm_P0.5mm_EP0.9x1.3mm
+DFN, 8 Pin (https://www.onsemi.com/pub/Collateral/NB3N551-D.PDF#page=7), generated with kicad-footprint-generator ipc_noLead_generator.py
+DFN NoLead
+0
+13
+9
+Package_DFN_QFN
+DFN-8-1EP_2x2mm_P0.5mm_EP0.9x1.5mm
+DFN, 8 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8127-AVR-8-bit-Microcontroller-ATtiny4-ATtiny5-ATtiny9-ATtiny10_Datasheet.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+DFN NoLead
+0
+13
+9
+Package_DFN_QFN
+DFN-8-1EP_2x2mm_P0.5mm_EP1.05x1.75mm
+DFN8 2x2, 0.5P; CASE 506CN (see ON Semiconductor 506CN.PDF)
+DFN 0.5
+0
+11
+9
+Package_DFN_QFN
+DFN-8-1EP_2x2mm_P0.45mm_EP0.64x1.38mm
+DC8 Package 8-Lead Plastic DFN (2mm x 2mm) (see Linear Technology DFN_8_05-08-1719.pdf)
+DFN 0.45
+0
+11
+9
+Package_DFN_QFN
+DFN-8-1EP_2x3mm_P0.5mm_EP0.61x2.2mm
+DDB Package; 8-Lead Plastic DFN (3mm x 2mm) (see Linear Technology DFN_8_05-08-1702.pdf)
+DFN 0.5
+0
+12
+9
+Package_DFN_QFN
+DFN-8-1EP_3x2mm_P0.5mm_EP1.3x1.5mm
+8-Lead Plastic Dual Flat, No Lead Package (8MA2) - 2x3x0.6 mm Body [UDFN] (see Atmel-8815-SEEPROM-AT24CS01-02-Datasheet.pdf)
+DFN 0.5
+0
+13
+9
+Package_DFN_QFN
+DFN-8-1EP_3x2mm_P0.5mm_EP1.36x1.46mm
+8-Lead Plastic Dual Flat, No Lead Package (8MA2) - 2x3x0.6 mm Body (http://ww1.microchip.com/downloads/en/DeviceDoc/20005010F.pdf)
+DFN 0.5
+0
+13
+9
+Package_DFN_QFN
+DFN-8-1EP_3x2mm_P0.5mm_EP1.75x1.45mm
+8-Lead Plastic Dual Flat, No Lead Package (MC) - 2x3x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf)
+DFN 0.5
+0
+13
+9
+Package_DFN_QFN
+DFN-8-1EP_3x2mm_P0.45mm_EP1.66x1.36mm
+DCB Package 8-Lead Plastic DFN (2mm x 3mm) (see Linear Technology DFN_8_05-08-1718.pdf)
+DFN 0.45
+0
+13
+9
+Package_DFN_QFN
+DFN-8-1EP_3x3mm_P0.5mm_EP1.66x2.38mm
+DD Package; 8-Lead Plastic DFN (3mm x 3mm) (see Linear Technology DFN_8_05-08-1698.pdf)
+DFN 0.5
+0
+13
+9
+Package_DFN_QFN
+DFN-8-1EP_3x3mm_P0.65mm_EP1.7x2.05mm
+DFN, 8 Pin (http://www.ixysic.com/home/pdfs.nsf/www/IX4426-27-28.pdf/$file/IX4426-27-28.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+DFN NoLead
+0
+13
+9
+Package_DFN_QFN
+DFN-8-1EP_3x3mm_P0.65mm_EP1.55x2.4mm
+8-Lead Plastic Dual Flat, No Lead Package (MF) - 3x3x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf)
+DFN 0.65
+0
+13
+9
+Package_DFN_QFN
+DFN-8-1EP_4x4mm_P0.8mm_EP2.3x3.24mm
+DFN, 8 Pin (https://www.st.com/resource/en/datasheet/ld1086.pdf#page=35), generated with kicad-footprint-generator ipc_noLead_generator.py
+DFN NoLead
+0
+13
+9
+Package_DFN_QFN
+DFN-8-1EP_4x4mm_P0.8mm_EP2.5x3.6mm
+8-Lead Plastic Dual Flat, No Lead Package (MD) - 4x4x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf)
+DFN 0.8
+0
+15
+9
+Package_DFN_QFN
+DFN-8-1EP_4x4mm_P0.8mm_EP2.39x2.21mm
+8-Lead Plastic Dual Flat, No Lead Package (MD) - 4x4x0.9 mm Body [DFN] (http://www.onsemi.com/pub/Collateral/NCP4308-D.PDF)
+DFN 0.8
+0
+13
+9
+Package_DFN_QFN
+DFN-8-1EP_6x5mm_P1.27mm_EP2x2mm
+DD Package; 8-Lead Plastic DFN (6mm x 5mm) (see http://www.everspin.com/file/236/download)
+dfn 
+0
+13
+9
+Package_DFN_QFN
+DFN-8-1EP_6x5mm_P1.27mm_EP4x4mm
+DD Package; 8-Lead Plastic DFN (6mm x 5mm) (see http://www.everspin.com/file/236/download)
+dfn 
+0
+25
+9
+Package_DFN_QFN
+DFN-8_2x2mm_P0.5mm
+DFN8 2x2, 0.5P; No exposed pad - Ref http://pdfserv.maximintegrated.com/land_patterns/90-0349.PDF
+DFN 0.5
+0
+8
+8
+Package_DFN_QFN
+DFN-10-1EP_2x3mm_P0.5mm_EP0.64x2.4mm
+DDB Package; 10-Lead Plastic DFN (3mm x 2mm) (see Linear Technology DFN_10_05-08-1722.pdf)
+DFN 0.5
+0
+13
+11
+Package_DFN_QFN
+DFN-10-1EP_3x3mm_P0.5mm_EP1.7x2.5mm
+DFN, 10 Pin (https://www.monolithicpower.com/pub/media/document/MPQ2483_r1.05.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+DFN NoLead
+0
+15
+11
+Package_DFN_QFN
+DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
+10-Lead Plastic Dual Flat, No Lead Package (MF) - 3x3x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf)
+DFN 0.5
+0
+15
+11
+Package_DFN_QFN
+DFN-10-1EP_3x3mm_P0.5mm_EP1.65x2.38mm
+DFN, 10 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3471fb.pdf#page=15), generated with kicad-footprint-generator ipc_noLead_generator.py
+DFN NoLead
+0
+15
+11
+Package_DFN_QFN
+DFN-10-1EP_3x3mm_P0.5mm_EP1.65x2.38mm_ThermalVias
+DFN, 10 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3471fb.pdf#page=15), generated with kicad-footprint-generator ipc_noLead_generator.py
+DFN NoLead
+0
+22
+11
+Package_DFN_QFN
+DFN-10-1EP_3x3mm_P0.5mm_EP1.75x2.7mm
+10-Lead Plastic Dual Flat No-Lead Package, 3x3mm Body (see Atmel Appnote 8826)
+DFN 0.5
+0
+15
+11
+Package_DFN_QFN
+DFN-10_2x2mm_P0.4mm
+10-Lead Plastic DFN (2mm x 2mm)  0.40mm pitch
+DFN 10 0.4mm
+0
+10
+10
+Package_DFN_QFN
+DFN-12-1EP_2x3mm_P0.45mm_EP0.64x2.4mm
+DDB Package; 12-Lead Plastic DFN (3mm x 2mm) (see Linear Technology DFN_12_05-08-1723.pdf)
+DFN 0.45
+0
+15
+13
+Package_DFN_QFN
+DFN-12-1EP_3x3mm_P0.5mm_EP2.05x2.86mm
+10-Lead Plastic Dual Flat, No Lead Package (MF) - 3x3x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf)
+DFN 0.5
+0
+17
+13
+Package_DFN_QFN
+DFN-12-1EP_3x3mm_P0.45mm_EP1.66x2.38mm
+DD Package; 12-Lead Plastic DFN (3mm x 3mm) (see Linear Technology DFN_12_05-08-1725.pdf)
+DFN 0.45
+0
+17
+13
+Package_DFN_QFN
+DFN-12-1EP_3x4mm_P0.5mm_EP1.7x3.3mm
+DE/UE Package; 12-Lead Plastic DFN (4mm x 3mm) (see Linear Technology DFN_12_05-08-1695.pdf)
+DFN 0.5
+0
+21
+13
+Package_DFN_QFN
+DFN-12-1EP_4x4mm_P0.5mm_EP2.66x3.38mm
+DF Package; 12-Lead Plastic DFN (4mm x 4mm) (see Linear Technology 05081733_A_DF12.pdf)
+DFN 0.5
+0
+21
+13
+Package_DFN_QFN
+DFN-12-1EP_4x4mm_P0.65mm_EP2.64x3.54mm
+DFN12, 4x4, 0.65P; CASE 506CE (see ON Semiconductor 506CE.PDF)
+DFN 0.65
+0
+21
+13
+Package_DFN_QFN
+DFN-14-1EP_3x3mm_P0.4mm_EP1.78x2.35mm
+DD Package; 14-Lead Plastic DFN (3mm x 3mm) (http://pdfserv.maximintegrated.com/land_patterns/90-0063.PDF)
+DFN 0.40
+0
+19
+15
+Package_DFN_QFN
+DFN-14-1EP_3x4.5mm_P0.65mm_EP1.65x4.25mm
+14-lead very thin plastic quad flat, 3.0x4.5mm size, 0.65mm pitch (http://ww1.microchip.com/downloads/en/DeviceDoc/14L_VDFN_4_5x3_0mm_JHA_C041198A.pdf)
+VDFN DFN 0.65mm
+0
+23
+15
+Package_DFN_QFN
+DFN-14-1EP_3x4.5mm_P0.65mm_EP1.65x4.25mm_ThermalVias
+14-lead very thin plastic quad flat, 3.0x4.5mm size, 0.65mm pitch (http://ww1.microchip.com/downloads/en/DeviceDoc/14L_VDFN_4_5x3_0mm_JHA_C041198A.pdf)
+VDFN DFN 0.65mm
+0
+33
+15
+Package_DFN_QFN
+DFN-14-1EP_3x4mm_P0.5mm_EP1.7x3.3mm
+DE Package; 14-Lead Plastic DFN (4mm x 3mm) (see Linear Technology DFN_14_05-08-1708.pdf)
+DFN 0.5
+0
+23
+15
+Package_DFN_QFN
+DFN-14-1EP_4x4mm_P0.5mm_EP2.86x3.6mm
+DFN14, 4x4, 0.5P; CASE 506CM (see ON Semiconductor 506CM.PDF)
+DFN 0.5
+0
+23
+15
+Package_DFN_QFN
+DFN-16-1EP_3x4mm_P0.45mm_EP1.7x3.3mm
+DE Package; 16-Lead Plastic DFN (4mm x 3mm) (see Linear Technology DFN_16_05-08-1732.pdf)
+DFN 0.45
+0
+25
+17
+Package_DFN_QFN
+DFN-16-1EP_3x5mm_P0.5mm_EP1.66x4.4mm
+DHC Package; 16-Lead Plastic DFN (5mm x 3mm) (see Linear Technology DFN_16_05-08-1706.pdf)
+DFN 0.5
+0
+27
+17
+Package_DFN_QFN
+DFN-16-1EP_4x5mm_P0.5mm_EP2.44x4.34mm
+DHD Package; 16-Lead Plastic DFN (5mm x 4mm) (see Linear Technology 05081707_A_DHD16.pdf)
+DFN 0.5
+0
+25
+17
+Package_DFN_QFN
+DFN-16-1EP_5x5mm_P0.5mm_EP3.46x4mm
+DH Package; 16-Lead Plastic DFN (5mm x 5mm) (see Linear Technology DFN_16_05-08-1709.pdf)
+DFN 0.5
+0
+26
+17
+Package_DFN_QFN
+DFN-18-1EP_3x5mm_P0.5mm_EP1.66x4.4mm
+DHC Package; 18-Lead Plastic DFN (5mm x 3mm) (see Linear Technology 05081955_0_DHC18.pdf)
+DFN 0.5
+0
+29
+19
+Package_DFN_QFN
+DFN-18-1EP_4x5mm_P0.5mm_EP2.44x4.34mm
+DHD Package; 18-Lead Plastic DFN (5mm x 4mm) (see Linear Technology DFN_18_05-08-1778.pdf)
+DFN 0.5
+0
+27
+19
+Package_DFN_QFN
+DFN-20-1EP_5x6mm_P0.5mm_EP3.24x4.24mm
+DFN20, 6x5, 0.5P; CASE 505AB (see ON Semiconductor 505AB.PDF)
+DFN 0.5
+0
+33
+21
+Package_DFN_QFN
+DFN-22-1EP_5x6mm_P0.5mm_EP3.14x4.3mm
+DFN22 6*5*0.9 MM, 0.5 P; CASE 506AF\xe2\x88\x9201 (see ON Semiconductor 506AF.PDF)
+DFN 0.5
+0
+35
+23
+Package_DFN_QFN
+DFN-24-1EP_4x7mm_P0.5mm_EP2.64x6.44mm
+DKD Package; 24-Lead Plastic DFN (7mm x 4mm) (see Linear Technology DFN_24_05-08-1864.pdf)
+DFN 0.5
+0
+35
+25
+Package_DFN_QFN
+DFN-32-1EP_4x7mm_P0.4mm_EP2.64x6.44mm
+DKD Package; 32-Lead Plastic DFN (7mm x 4mm) (see Linear Technology DFN_32_05-08-1734.pdf)
+DFN 0.4
+0
+43
+33
+Package_DFN_QFN
+DFN-44-1EP_5x8.9mm_P0.4mm_EP3.7x8.4mm
+DFN44 8.9x5, 0.4P; CASE 506BU-01 (see ON Semiconductor 506BU.PDF)
+DFN 0.4
+0
+63
+45
+Package_DFN_QFN
+DFN-S-8-1EP_6x5mm_P1.27mm
+8-Lead Plastic Dual Flat, No Lead Package (MF) - 6x5 mm Body [DFN-S] (see Microchip Packaging Specification 00000049BS.pdf)
+DFN 1.27
+0
+16
+9
+Package_DFN_QFN
+Diodes_DFN1006-3
+DFN package size 1006 3 pins
+DFN package size 1006 3 pins
+0
+3
+3
+Package_DFN_QFN
+Infineon_MLPQ-16-14-1EP_4x4mm_P0.5mm
+MLPQ 32 leads, 7x7mm, 0.127mm stencil (https://www.infineon.com/dgdl/Infineon-AN1170-AN-v05_00-EN.pdf?fileId=5546d462533600a40153559ac3e51134)
+mlpq 32 7x7mm
+0
+19
+15
+Package_DFN_QFN
+Infineon_MLPQ-40-32-1EP_7x7mm_P0.5mm
+MLPQ 32 leads, 7x7mm, 0.127mm stencil (https://www.infineon.com/dgdl/Infineon-AN1170-AN-v05_00-EN.pdf?fileId=5546d462533600a40153559ac3e51134)
+mlpq 32 7x7mm
+0
+76
+33
+Package_DFN_QFN
+Infineon_MLPQ-48-1EP_7x7mm_P0.5mm_EP5.55x5.55mm
+MLPQ 48 leads, 7x7mm (https://www.infineon.com/dgdl/irs2093mpbf.pdf?fileId=5546d462533600a401535675fb892793)
+mlpq 32 7x7mm
+0
+113
+49
+Package_DFN_QFN
+Infineon_MLPQ-48-1EP_7x7mm_P0.5mm_Pad5.15x5.15mm
+MLPQ 48 leads, 7x7mm (https://www.infineon.com/dgdl/irs2052mpbf.pdf?fileId=5546d462533600a401535675d3b32788)
+mlpq 32 7x7mm
+0
+117
+49
+Package_DFN_QFN
+Infineon_MLPQ-48-1EP_7x7mm_P0.5mm_Pad5.55x5.55mm
+MLPQ 48 leads, 7x7mm (https://www.infineon.com/dgdl/irs2093mpbf.pdf?fileId=5546d462533600a401535675fb892793)
+mlpq 32 7x7mm
+0
+117
+49
+Package_DFN_QFN
+Infineon_PQFN-22-15-4EP_6x5mm_P0.65mm
+PQFN 22 leads, 5x6mm, 0.127mm stencil (https://www.infineon.com/dgdl/ir4301.pdf?fileId=5546d462533600a4015355d5fc691819, https://www.infineon.com/dgdl/Infineon-AN1170-AN-v05_00-EN.pdf?fileId=5546d462533600a40153559ac3e51134)
+pqfn 22 5x6mm
+0
+56
+15
+Package_DFN_QFN
+Infineon_PQFN-44-31-5EP_7x7mm_P0.5mm
+PQFN 44 leads, 7x7mm, 0.127mm stencil (https://www.infineon.com/dgdl/ir4302.pdf?fileId=5546d462533600a4015355d602a9181d, https://www.infineon.com/dgdl/Infineon-AN1170-AN-v05_00-EN.pdf?fileId=5546d462533600a40153559ac3e51134)
+pqfn 44 7x7mm
+0
+125
+27
+Package_DFN_QFN
+Linear_DE14MA
+14-Lead Plastic DFN, 4mm x 3mm (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-dfn/05081731_C_DE14MA.pdf)
+DFN 0.5
+0
+14
+14
+Package_DFN_QFN
+Linear_UGK52_QFN-46-52
+Linear UKG52(46) package, QFN-52-1EP variant (see http://cds.linear.com/docs/en/datasheet/3886fe.pdf)
+QFN 0.5
+0
+62
+47
+Package_DFN_QFN
+MLF-6-1EP_1.6x1.6mm_P0.5mm_EP0.5x1.26mm
+MLF, 6 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/mic5353.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+MLF NoLead
+0
+9
+7
+Package_DFN_QFN
+MLF-8-1EP_3x3mm_P0.65mm_EP1.55x2.3mm
+8-Pin ePad 3mm x 3mm MLF - 3x3x0.85 mm Body (see Microchip datasheet http://ww1.microchip.com/downloads/en/DeviceDoc/mic5355_6.pdf)
+DFN MLF 0.65
+0
+12
+9
+Package_DFN_QFN
+MLF-8-1EP_3x3mm_P0.65mm_EP1.55x2.3mm_ThermalVias
+8-Pin ePad 3mm x 3mm MLF - 3x3x0.85 mm Body (see Microchip datasheet http://ww1.microchip.com/downloads/en/DeviceDoc/mic5355_6.pdf)
+DFN MLF 0.65
+0
+15
+9
+Package_DFN_QFN
+MLF-20-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
+MLF, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc8246.pdf#page=263), generated with kicad-footprint-generator ipc_noLead_generator.py
+MLF NoLead
+0
+25
+21
+Package_DFN_QFN
+MLF-20-1EP_4x4mm_P0.5mm_EP2.6x2.6mm_ThermalVias
+MLF, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc8246.pdf#page=263), generated with kicad-footprint-generator ipc_noLead_generator.py
+MLF NoLead
+0
+30
+21
+Package_DFN_QFN
+MLPQ-16-1EP_4x4mm_P0.65mm_EP2.8x2.8mm
+Micro Leadframe Package, 16 pin with exposed pad
+MLPQ- 0.65
+0
+21
+17
+Package_DFN_QFN
+Micrel_MLF-8-1EP_2x2mm_P0.5mm_EP0.8x1.3mm_ThermalVias
+http://ww1.microchip.com/downloads/en/DeviceDoc/mic2290.pdf
+mlf 8 2x2 mm
+0
+14
+9
+Package_DFN_QFN
+Microchip_8E-16
+16-Lead Quad Flat, No Lead Package (8E) - 4x4x0.9 mm Body [UQFN]; (see Microchip Packaging Specification 00000049BS.pdf)
+QFN Microchip 8E 16
+0
+20
+17
+Package_DFN_QFN
+Microchip_DRQFN-44-1EP_5x5mm_P0.7mm_EP2.65x2.65mm
+QFN, 44 Pin, dual row (http://ww1.microchip.com/downloads/en/DeviceDoc/44L_VQFN_5x5mm_Dual_Row_%5BS3B%5D_C04-21399a.pdf)
+QFN dual row
+0
+49
+45
+Package_DFN_QFN
+Microchip_DRQFN-44-1EP_5x5mm_P0.7mm_EP2.65x2.65mm_ThermalVias
+QFN, 44 Pin, dual row (http://ww1.microchip.com/downloads/en/DeviceDoc/44L_VQFN_5x5mm_Dual_Row_%5BS3B%5D_C04-21399a.pdf)
+QFN dual row
+0
+59
+45
+Package_DFN_QFN
+Microchip_DRQFN-64-1EP_7x7mm_P0.65mm_EP4.1x4.1mm
+QFN, 64 Pin, dual row (http://ww1.microchip.com/downloads/en/DeviceDoc/64L_VQFN_7x7_Dual_Row_%5BSVB%5D_C04-21420a.pdf)
+QFN dual row
+0
+74
+65
+Package_DFN_QFN
+Microchip_DRQFN-64-1EP_7x7mm_P0.65mm_EP4.1x4.1mm_ThermalVias
+QFN, 64 Pin, dual row (http://ww1.microchip.com/downloads/en/DeviceDoc/64L_VQFN_7x7_Dual_Row_%5BSVB%5D_C04-21420a.pdf)
+QFN dual row
+0
+91
+65
+Package_DFN_QFN
+Microsemi_QFN-40-32-2EP_6x8mm_P0.5mm
+40-Lead (32-Lead Populated) Plastic Quad Flat, No Lead Package - 6x8x0.9mm Body (https://www.microsemi.com/document-portal/doc_download/131677-pd70224-data-sheet)
+QFN 0.5
+0
+92
+34
+Package_DFN_QFN
+Mini-Circuits_DL805
+https://ww2.minicircuits.com/case_style/DL805.pdf
+RF Switch
+0
+11
+9
+Package_DFN_QFN
+Mini-Circuits_FG873-4_3x3mm
+Mini Circuits Case style FG (https://ww2.minicircuits.com/case_style/FG873.pdf)
+FG873
+0
+4
+4
+Package_DFN_QFN
+Nordic_AQFN-73-1EP_7x7mm_P0.5mm
+http://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.nrf52%2Fdita%2Fnrf52%2Fchips%2Fnrf52840.html
+AQFN 7mm 
+0
+78
+74
+Package_DFN_QFN
+OnSemi_DFN-8_2x2mm_P0.5mm
+DFN8 2x2, 0.5P (https://www.onsemi.com/pub/Collateral/511AT.PDF)
+DFN 0.5
+0
+8
+8
+Package_DFN_QFN
+OnSemi_UDFN-8_1.2x1.8mm_P0.4mm
+8-Lead Plastic Dual Flat, No Lead Package, 1.2x1.8x1.55 mm Body [UDFN] (See http://www.onsemi.com/pub/Collateral/NLSV2T244-D.PDF)
+dfn udfn dual flat
+0
+8
+8
+Package_DFN_QFN
+OnSemi_VCT-28_3.5x3.5mm_P0.4mm
+OnSemi  VCT, 28 Pin (http://www.onsemi.com/pub/Collateral/601AE.PDF), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+OnSemi VCT DFN_QFN
+0
+28
+28
+Package_DFN_QFN
+Panasonic_HQFN-16-1EP_4x4mm_P0.65mm_EP2.9x2.9mm
+Panasonic HQFN-16, 4x4x0.85mm (https://industrial.panasonic.com/content/data/SC/ds/ds7/c0/PKG_HQFN016-A-0404XZL_EN.pdf)
+panasonic hqfn
+0
+37
+17
+Package_DFN_QFN
+Panasonic_HSON-8_8x8mm_P2.00mm
+Panasonic HSON-8, 8x8x1.25mm (https://industrial.panasonic.com/content/data/SC/ds/ds7/c0/PKG_HSON008-A-0808XXI_EN.pdf)
+panasonic hson
+0
+27
+9
+Package_DFN_QFN
+QFN-12-1EP_3x3mm_P0.5mm_EP1.65x1.65mm
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+QFN, 68 Pin (https://cdn.microsemi.com/documents/1bf6886f-5919-4508-a50b-b1dbf3fdf0f4/download/#page=98), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+QFN DFN_QFN
+0
+85
+69
+Package_DFN_QFN
+QFN-68-1EP_8x8mm_P0.4mm_EP5.2x5.2mm_ThermalVias
+QFN, 68 Pin (https://cdn.microsemi.com/documents/1bf6886f-5919-4508-a50b-b1dbf3fdf0f4/download/#page=98), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+QFN DFN_QFN
+0
+111
+69
+Package_DFN_QFN
+QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm
+QFN, 72 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/00001682C.pdf#page=70), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+82
+73
+Package_DFN_QFN
+QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm_ThermalVias
+QFN, 72 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/00001682C.pdf#page=70), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+135
+73
+Package_DFN_QFN
+QFN-76-1EP_9x9mm_P0.4mm_EP3.8x3.8mm
+QFN, 76 Pin (https://www.marvell.com/documents/bqcwxsoiqfjkcjdjhkvc/#page=19), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+QFN DFN_QFN
+0
+86
+77
+Package_DFN_QFN
+QFN-76-1EP_9x9mm_P0.4mm_EP3.8x3.8mm_ThermalVias
+QFN, 76 Pin (https://www.marvell.com/documents/bqcwxsoiqfjkcjdjhkvc/#page=19), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+QFN DFN_QFN
+0
+103
+77
+Package_DFN_QFN
+Qorvo_DFN-8-1EP_2x2mm_P0.5mm
+DFN 8 2x2mm, 0.5mm http://www.qorvo.com/products/d/da000896
+DFN 0.5 Qorvo 2x2mm
+0
+9
+9
+Package_DFN_QFN
+ROHM_DFN0604-3
+DFN package size 0604 3 pins
+DFN package size 0604 3 pins
+0
+3
+3
+Package_DFN_QFN
+ST_UFQFPN-20_3x3mm_P0.5mm
+UFQFPN 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package (http://www.st.com/resource/en/datasheet/stm8s003f3.pdf)
+UFQFPN 0.5
+0
+20
+20
+Package_DFN_QFN
+ST_UQFN-6L_1.5x1.7mm_Pitch0.5mm
+ST UQFN 6 pin 0.5mm Pitch http://www.st.com/resource/en/datasheet/ecmf02-2amx6.pdf
+UQFN DFN 0.5 ST
+0
+6
+6
+Package_DFN_QFN
+SiliconLabs_QFN-20-1EP_3x3mm_P0.5mm
+20-Lead Plastic Quad Flat, No Lead Package - 3x3 mm Body [QFN] with corner pads; see figure 8.2 of https://www.silabs.com/documents/public/data-sheets/efm8bb1-datasheet.pdf
+QFN 0.5
+0
+25
+21
+Package_DFN_QFN
+SiliconLabs_QFN-20-1EP_3x3mm_P0.5mm_ThermalVias
+20-Lead Plastic Quad Flat, No Lead Package - 3x3 mm Body [QFN] with corner pads and thermal vias; see figure 8.2 of https://www.silabs.com/documents/public/data-sheets/efm8bb1-datasheet.pdf
+QFN 0.5
+0
+31
+21
+Package_DFN_QFN
+TDFN-6-1EP_2.5x2.5mm_P0.65mm_EP1.3x2mm
+TDFN, 6 Pin (http://www.nve.com/Downloads/ab3.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+TDFN NoLead
+0
+11
+7
+Package_DFN_QFN
+TDFN-6-1EP_2.5x2.5mm_P0.65mm_EP1.3x2mm_ThermalVias
+TDFN, 6 Pin (http://www.nve.com/Downloads/ab3.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+TDFN NoLead
+0
+18
+7
+Package_DFN_QFN
+TDFN-8-1EP_3x2mm_P0.5mm_EP1.80x1.65mm
+8-lead plastic dual flat, 2x3x0.75mm size, 0.5mm pitch (http://ww1.microchip.com/downloads/en/DeviceDoc/8L_TDFN_2x3_MN_C04-0129E-MN.pdf)
+TDFN DFN 0.5mm
+0
+12
+9
+Package_DFN_QFN
+TDFN-8-1EP_3x2mm_P0.5mm_EP1.80x1.65mm_ThermalVias
+8-lead plastic dual flat, 2x3x0.75mm size, 0.5mm pitch (http://ww1.microchip.com/downloads/en/DeviceDoc/8L_TDFN_2x3_MN_C04-0129E-MN.pdf)
+TDFN DFN 0.5mm
+0
+17
+9
+Package_DFN_QFN
+TDFN-12_2x3mm_P0.5mm
+TDFN, 12 Pads, No exposed, http://www.st.com/resource/en/datasheet/stm6600.pdf
+DFN
+0
+12
+12
+Package_DFN_QFN
+TQFN-16-1EP_3x3mm_P0.5mm_EP1.23x1.23mm
+TQFN, 16 Pin (https://pdfserv.maximintegrated.com/package_dwgs/21-0136.PDF (T1633-5), https://pdfserv.maximintegrated.com/land_patterns/90-0032.PDF), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+TQFN DFN_QFN
+0
+21
+17
+Package_DFN_QFN
+TQFN-16-1EP_5x5mm_P0.8mm_EP3.1x3.1mm
+TQFN, 16 Pin (https://pdfserv.maximintegrated.com/package_dwgs/21-0140.PDF), generated with kicad-footprint-generator ipc_noLead_generator.py
+TQFN NoLead
+0
+21
+17
+Package_DFN_QFN
+TQFN-20-1EP_5x5mm_P0.65mm_EP3.1x3.1mm
+TQFN, 20 Pin (https://pdfserv.maximintegrated.com/package_dwgs/21-0140.PDF), generated with kicad-footprint-generator ipc_noLead_generator.py
+TQFN NoLead
+0
+25
+21
+Package_DFN_QFN
+TQFN-20-1EP_5x5mm_P0.65mm_EP3.1x3.1mm_ThermalVias
+TQFN, 20 Pin (https://pdfserv.maximintegrated.com/package_dwgs/21-0140.PDF), generated with kicad-footprint-generator ipc_noLead_generator.py
+TQFN NoLead
+0
+35
+21
+Package_DFN_QFN
+TQFN-24-1EP_4x4mm_P0.5mm_EP2.8x2.8mm_PullBack
+TQFN, 24 Pin (https://ams.com/documents/20143/36005/AS1115_DS000206_1-00.pdf/3d3e6d35-b184-1329-adf9-2d769eb2404f), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+TQFN DFN_QFN
+0
+29
+25
+Package_DFN_QFN
+TQFN-24-1EP_4x4mm_P0.5mm_EP2.8x2.8mm_PullBack_ThermalVias
+TQFN, 24 Pin (https://ams.com/documents/20143/36005/AS1115_DS000206_1-00.pdf/3d3e6d35-b184-1329-adf9-2d769eb2404f), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+TQFN DFN_QFN
+0
+39
+25
+Package_DFN_QFN
+Texas_DRB0008A
+DFN-8, 3x3x1mm, http://www.ti.com/lit/ds/symlink/ucc24610.pdf
+DRB0008A
+0
+23
+9
+Package_DFN_QFN
+Texas_MOF0009A
+Texas Instruments, QFM MOF0009A, 6x8x2mm (http://www.ti.com/lit/ml/mpsi063a/mpsi063a.pdf)
+ti qfm mof0009a
+0
+24
+9
+Package_DFN_QFN
+Texas_R-PUQFN-N10
+http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=MPQF186&fileType=pdf
+Texas_R-PUQFN-N10
+0
+10
+10
+Package_DFN_QFN
+Texas_R-PWQFN-N28_EP2.1x3.1mm
+QFN, 28 Pin (http://www.ti.com/lit/ds/symlink/tps51363.pdf#page=29), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+33
+29
+Package_DFN_QFN
+Texas_R-PWQFN-N28_EP2.1x3.1mm_ThermalVias
+QFN, 28 Pin (http://www.ti.com/lit/ds/symlink/tps51363.pdf#page=29), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+43
+29
+Package_DFN_QFN
+Texas_RGE0024C_EP2.1x2.1mm
+Texas  QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/pca9548a.pdf#page=34), generated with kicad-footprint-generator ipc_noLead_generator.py
+Texas QFN NoLead
+0
+29
+25
+Package_DFN_QFN
+Texas_RGE0024C_EP2.1x2.1mm_ThermalVias
+Texas  QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/pca9548a.pdf#page=34), generated with kicad-footprint-generator ipc_noLead_generator.py
+Texas QFN NoLead
+0
+39
+25
+Package_DFN_QFN
+Texas_RGE0024H_EP2.7x2.7mm
+Texas  QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/tlc5971.pdf#page=43), generated with kicad-footprint-generator ipc_noLead_generator.py
+Texas QFN NoLead
+0
+29
+25
+Package_DFN_QFN
+Texas_RGE0024H_EP2.7x2.7mm_ThermalVias
+Texas  QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/tlc5971.pdf#page=43), generated with kicad-footprint-generator ipc_noLead_generator.py
+Texas QFN NoLead
+0
+39
+25
+Package_DFN_QFN
+Texas_RGV_S-PVQFN-N16_EP2.1x2.1mm
+QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/ina3221.pdf#page=44), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+21
+17
+Package_DFN_QFN
+Texas_RGV_S-PVQFN-N16_EP2.1x2.1mm_ThermalVias
+QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/ina3221.pdf#page=44), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+31
+17
+Package_DFN_QFN
+Texas_RGY_R-PVQFN-N24_EP2.05x3.1mm
+QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/bq24133.pdf#page=40)
+QFN NoLead
+0
+29
+25
+Package_DFN_QFN
+Texas_RGY_R-PVQFN-N24_EP2.05x3.1mm_ThermalVias
+QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/bq24133.pdf#page=40)
+QFN NoLead
+0
+36
+25
+Package_DFN_QFN
+Texas_RNN0018A
+Texas Instruments, VQFN-HR RNN0018A (http://www.ti.com/lit/ds/symlink/tps568215.pdf)
+ti vqfn-hr rnn0018a
+0
+26
+18
+Package_DFN_QFN
+Texas_RUM0016A_EP2.6x2.6mm
+QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/lmh0074.pdf#page=13), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+21
+17
+Package_DFN_QFN
+Texas_RUM0016A_EP2.6x2.6mm_ThermalVias
+QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/lmh0074.pdf#page=13), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+31
+17
+Package_DFN_QFN
+Texas_RWH0032A
+Texas Instruments, RWH0032A, 8x8x0.9mm (http://www.ti.com/lit/ds/snosd10c/snosd10c.pdf)
+ti rwh0032a
+0
+71
+33
+Package_DFN_QFN
+Texas_RWH0032A_ThermalVias
+Texas Instruments, RWH0032A, 8x8x0.9mm (http://www.ti.com/lit/ds/snosd10c/snosd10c.pdf)
+ti rwh0032a
+0
+94
+33
+Package_DFN_QFN
+Texas_R_PUQFN-N12
+Texas_R_PUQFN-N12 http://www.ti.com/lit/ds/symlink/txb0104.pdf
+Texas_R_PUQFN-N12
+0
+13
+12
+Package_DFN_QFN
+Texas_S-PDSO-N10_EP1.2x2mm
+DFN, 10 Pin (http://www.ti.com/lit/ds/symlink/tps7a91.pdf#page=30), generated with kicad-footprint-generator ipc_noLead_generator.py
+DFN NoLead
+0
+15
+11
+Package_DFN_QFN
+Texas_S-PDSO-N10_EP1.2x2mm_ThermalVias
+DFN, 10 Pin (http://www.ti.com/lit/ds/symlink/tps7a91.pdf#page=30), generated with kicad-footprint-generator ipc_noLead_generator.py
+DFN NoLead
+0
+22
+11
+Package_DFN_QFN
+Texas_S-PVQFN-N14
+Texas_S-PVQFN-N14  http://www.ti.com/lit/ds/symlink/txb0104.pdf
+Texas_S-PVQFN-N14_4.3x4.3_Pitch0.5mm_ThermalPad
+0
+19
+15
+Package_DFN_QFN
+Texas_S-PVQFN-N14_ThermalVias
+Texas_S-PVQFN-N14_ThermalVias  http://www.ti.com/lit/ds/symlink/txb0104.pdf
+Texas_S-PVQFN-N14_ThermalVias
+0
+24
+15
+Package_DFN_QFN
+Texas_S-PVQFN-N16_EP2.7x2.7mm
+QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/msp430g2001.pdf#page=43), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+26
+17
+Package_DFN_QFN
+Texas_S-PVQFN-N16_EP2.7x2.7mm_ThermalVias
+QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/msp430g2001.pdf#page=43), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+31
+17
+Package_DFN_QFN
+Texas_S-PVQFN-N20_EP2.4x2.4mm
+QFN, 20 Pin (http://www.ti.com/lit/ds/symlink/cc1101.pdf#page=101), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+25
+21
+Package_DFN_QFN
+Texas_S-PVQFN-N20_EP2.4x2.4mm_ThermalVias
+QFN, 20 Pin (http://www.ti.com/lit/ds/symlink/cc1101.pdf#page=101), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+35
+21
+Package_DFN_QFN
+Texas_S-PVQFN-N20_EP2.7x2.7mm
+QFN, 20 Pin (http://www.ti.com/lit/ds/symlink/drv8662.pdf#page=23), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+25
+21
+Package_DFN_QFN
+Texas_S-PVQFN-N20_EP2.7x2.7mm_ThermalVias
+QFN, 20 Pin (http://www.ti.com/lit/ds/symlink/drv8662.pdf#page=23), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+35
+21
+Package_DFN_QFN
+Texas_S-PVQFN-N20_EP3.15x3.15mm
+QFN, 20 Pin (www.ti.com/lit/ds/symlink/tps7a7200.pdf#page=36), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+25
+21
+Package_DFN_QFN
+Texas_S-PVQFN-N20_EP3.15x3.15mm_ThermalVias
+QFN, 20 Pin (www.ti.com/lit/ds/symlink/tps7a7200.pdf#page=36), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+47
+21
+Package_DFN_QFN
+Texas_S-PVQFN-N24_EP2.1x2.1mm
+QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/msp430fr5720.pdf#page=111), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+29
+25
+Package_DFN_QFN
+Texas_S-PVQFN-N24_EP2.1x2.1mm_ThermalVias
+QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/msp430fr5720.pdf#page=111), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+39
+25
+Package_DFN_QFN
+Texas_S-PVQFN-N32_EP3.45x3.45mm
+QFN, 32 Pin (http://www.ti.com/lit/ds/symlink/msp430f1122.pdf#page=46), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+42
+33
+Package_DFN_QFN
+Texas_S-PVQFN-N32_EP3.45x3.45mm_ThermalVias
+QFN, 32 Pin (http://www.ti.com/lit/ds/symlink/msp430f1122.pdf#page=46), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+59
+33
+Package_DFN_QFN
+Texas_S-PVQFN-N36_EP4.4x4.4mm
+QFN, 36 Pin (http://www.ti.com/lit/ds/slvsba5d/slvsba5d.pdf#page=31), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+46
+37
+Package_DFN_QFN
+Texas_S-PVQFN-N36_EP4.4x4.4mm_ThermalVias
+QFN, 36 Pin (http://www.ti.com/lit/ds/slvsba5d/slvsba5d.pdf#page=31), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+79
+37
+Package_DFN_QFN
+Texas_S-PVQFN-N40_EP2.9x2.9mm
+QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/msp430fr5731.pdf#page=114), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+45
+41
+Package_DFN_QFN
+Texas_S-PVQFN-N40_EP2.9x2.9mm_ThermalVias
+QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/msp430fr5731.pdf#page=114), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+55
+41
+Package_DFN_QFN
+Texas_S-PVQFN-N40_EP3.52x2.62mm
+QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/drv8308.pdf#page=56), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+47
+41
+Package_DFN_QFN
+Texas_S-PVQFN-N40_EP3.52x2.62mm_ThermalVias
+QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/drv8308.pdf#page=56), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+60
+41
+Package_DFN_QFN
+Texas_S-PVQFN-N40_EP4.6x4.6mm
+QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/dac7750.pdf#page=55), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+50
+41
+Package_DFN_QFN
+Texas_S-PVQFN-N40_EP4.6x4.6mm_ThermalVias
+QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/dac7750.pdf#page=55), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+83
+41
+Package_DFN_QFN
+Texas_S-PVQFN-N40_EP4.15x4.15mm
+QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/msp430g2755.pdf#page=70), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+50
+41
+Package_DFN_QFN
+Texas_S-PVQFN-N40_EP4.15x4.15mm_ThermalVias
+QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/msp430g2755.pdf#page=70), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+83
+41
+Package_DFN_QFN
+Texas_S-PVQFN-N48_EP5.15x5.15mm
+QFN, 48 Pin (http://www.ti.com/lit/ds/symlink/msp430f5232.pdf#page=112), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+65
+49
+Package_DFN_QFN
+Texas_S-PVQFN-N48_EP5.15x5.15mm_ThermalVias
+QFN, 48 Pin (http://www.ti.com/lit/ds/symlink/msp430f5232.pdf#page=112), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+111
+49
+Package_DFN_QFN
+Texas_S-PVQFN-N64_EP4.25x4.25mm
+QFN, 64 Pin (http://www.ti.com/lit/ds/symlink/msp430f5217.pdf#page=117), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+69
+65
+Package_DFN_QFN
+Texas_S-PVQFN-N64_EP4.25x4.25mm_ThermalVias
+QFN, 64 Pin (http://www.ti.com/lit/ds/symlink/msp430f5217.pdf#page=117), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+127
+65
+Package_DFN_QFN
+Texas_S-PWQFN-N16_EP2.1x2.1mm
+QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/drv8801.pdf#page=31), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+21
+17
+Package_DFN_QFN
+Texas_S-PWQFN-N16_EP2.1x2.1mm_ThermalVias
+QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/drv8801.pdf#page=31), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+31
+17
+Package_DFN_QFN
+Texas_S-PWQFN-N20
+20-Pin Plastic Quad Flatpack No-Lead Package, Body 3.0x3.0x0.8mm, Texas Instruments (http://www.ti.com/lit/ds/symlink/tps22993.pdf)
+QFN 0.4
+0
+24
+20
+Package_DFN_QFN
+Texas_S-PWQFN-N24_EP2.7x2.7mm
+QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/bq25601.pdf#page=54), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+29
+25
+Package_DFN_QFN
+Texas_S-PWQFN-N24_EP2.7x2.7mm_ThermalVias
+QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/bq25601.pdf#page=54), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+39
+25
+Package_DFN_QFN
+Texas_S-PWQFN-N32_EP2.8x2.8mm
+QFN, 32 Pin (https://www.ti.com/lit/ds/symlink/bq25703a.pdf#page=91), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+37
+33
+Package_DFN_QFN
+Texas_S-PWQFN-N32_EP2.8x2.8mm_ThermalVias
+QFN, 32 Pin (https://www.ti.com/lit/ds/symlink/bq25703a.pdf#page=91), generated with kicad-footprint-generator ipc_noLead_generator.py
+QFN NoLead
+0
+47
+33
+Package_DFN_QFN
+Texas_S-PWQFN-N100_EP5.5x5.5mm
+http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=szza059&fileType=pdf,http://www.ti.com/lit/ds/sllse76m/sllse76m.pdf
+MultiRow QFN
+0
+114
+105
+Package_DFN_QFN
+Texas_S-PWQFN-N100_EP5.5x5.5mm_ThermalVias
+http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=szza059&fileType=pdf,http://www.ti.com/lit/ds/sllse76m/sllse76m.pdf
+MultiRow QFN
+0
+131
+105
+Package_DFN_QFN
+Texas_S-PX2QFN-14
+Texas  QFN, 14 Pin (http://www.ti.com/lit/ds/symlink/tlv9004.pdf#page=64), generated with kicad-footprint-generator ipc_noLead_generator.py
+Texas QFN NoLead
+0
+14
+14
+Package_DFN_QFN
+Texas_VQFN-RHL-20
+http://www.ti.com/lit/ds/symlink/bq51050b.pdf
+RHL0020A
+0
+33
+21
+Package_DFN_QFN
+Texas_VQFN-RHL-20_ThermalVias
+http://www.ti.com/lit/ds/symlink/bq51050b.pdf
+RHL0020A
+0
+41
+21
+Package_DFN_QFN
+Texas_VSON-HR-8_1.5x2mm_P0.5mm
+Texas  VSON-HR, 8 Pin (http://www.ti.com/lit/ds/symlink/tps62823.pdf#page=29), generated with kicad-footprint-generator ipc_noLead_generator.py
+Texas VSON-HR NoLead
+0
+8
+8
+Package_DFN_QFN
+Texas_WQFN-MR-100_3x3-DapStencil
+http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=szza059&fileType=pdf,http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=mpqf258&fileType=pdf,http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=LPPD235&fileType=pdf
+MultiRow QFN
+0
+113
+105
+Package_DFN_QFN
+Texas_WQFN-MR-100_ThermalVias_3x3-DapStencil
+http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=szza059&fileType=pdf,http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=mpqf258&fileType=pdf,http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=LPPD235&fileType=pdf
+MultiRow QFN
+0
+126
+105
+Package_DFN_QFN
+Texas_X2QFN-12_1.6x1.6mm_P0.4mm
+Texas  X2QFN, 12 Pin (http://www.ti.com/lit/ml/mpqf391c/mpqf391c.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+Texas X2QFN DFN_QFN
+0
+12
+12
+Package_DFN_QFN
+UDFN-4-1EP_1x1mm_P0.65mm_EP0.48x0.48mm
+UDFN-4_1x1mm_P0.65mm, http://ww1.microchip.com/downloads/en/DeviceDoc/MIC550x-300mA-Single-Output-LDO-in-Small-Packages-DS20006006A.pdf
+UDFN-4_1x1mm_P0.65mm
+0
+5
+5
+Package_DFN_QFN
+UDFN-9_1.0x3.8mm_P0.5mm
+9-pin UDFN package, 1.0x3.8mm, (Ref: https://katalog.we-online.de/pbs/datasheet/824014881.pdf)
+UDFN SMD
+0
+9
+9
+Package_DFN_QFN
+UDFN-10_1.35x2.6mm_P0.5mm
+http://www.st.com/content/ccc/resource/technical/document/datasheet/f2/11/8a/ed/40/31/40/56/DM00088292.pdf/files/DM00088292.pdf/jcr:content/translations/en.DM00088292.pdf
+UDFN 0.5 uQFN
+0
+10
+10
+Package_DFN_QFN
+UQFN-10_1.3x1.8mm_P0.4mm
+UQFN, 10 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/00001725D.pdf (Page 9)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+UQFN DFN_QFN
+0
+10
+10
+Package_DFN_QFN
+UQFN-10_1.4x1.8mm_P0.4mm
+UQFN 10pin, https://www.onsemi.com/pub/Collateral/488AT.PDF
+UQFN-10_1.4x1.8mm_P0.4mm
+0
+10
+10
+Package_DFN_QFN
+UQFN-10_1.6x2.1mm_P0.5mm
+UQFN, 10 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/00001725D.pdf (Page 12)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+UQFN DFN_QFN
+0
+10
+10
+Package_DFN_QFN
+UQFN-16-1EP_3x3mm_P0.5mm_EP1.75x1.75mm
+16-Lead Ultra Thin Quad Flat, No Lead Package (UC) - 3x3x0.5 mm Body [UQFN]; (see Microchip Packaging Specification 00000049BS.pdf)
+QFN 0.5
+0
+21
+17
+Package_DFN_QFN
+UQFN-16-1EP_4x4mm_P0.65mm_EP2.6x2.6mm
+UQFN, 16 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/16L_UQFN_4x4x0_5mm_JQ_C04257A.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+UQFN DFN_QFN
+0
+21
+17
+Package_DFN_QFN
+UQFN-16-1EP_4x4mm_P0.65mm_EP2.6x2.6mm_ThermalVias
+UQFN, 16 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/16L_UQFN_4x4x0_5mm_JQ_C04257A.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+UQFN DFN_QFN
+0
+31
+17
+Package_DFN_QFN
+UQFN-16-1EP_4x4mm_P0.65mm_EP2.7x2.7mm
+16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN]; (see Microchip Packaging Specification 00000049BS.pdf)
+QFN 0.65
+0
+21
+17
+Package_DFN_QFN
+UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm
+UQFN, 20 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=332), generated with kicad-footprint-generator ipc_noLead_generator.py
+UQFN NoLead
+0
+25
+21
+Package_DFN_QFN
+UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm_ThermalVias
+UQFN, 20 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=332), generated with kicad-footprint-generator ipc_noLead_generator.py
+UQFN NoLead
+0
+30
+21
+Package_DFN_QFN
+UQFN-20-1EP_4x4mm_P0.5mm_EP2.8x2.8mm
+UQFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001839B.pdf#page=464), generated with kicad-footprint-generator ipc_noLead_generator.py
+UQFN NoLead
+0
+25
+21
+Package_DFN_QFN
+UQFN-20-1EP_4x4mm_P0.5mm_EP2.8x2.8mm_ThermalVias
+UQFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001839B.pdf#page=464), generated with kicad-footprint-generator ipc_noLead_generator.py
+UQFN NoLead
+0
+35
+21
+Package_DFN_QFN
+UQFN-28-1EP_4x4mm_P0.4mm_EP2.35x2.35mm
+UQFN, 28 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=338), generated with kicad-footprint-generator ipc_noLead_generator.py
+UQFN NoLead
+0
+33
+29
+Package_DFN_QFN
+UQFN-28-1EP_4x4mm_P0.4mm_EP2.35x2.35mm_ThermalVias
+UQFN, 28 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=338), generated with kicad-footprint-generator ipc_noLead_generator.py
+UQFN NoLead
+0
+43
+29
+Package_DFN_QFN
+UQFN-40-1EP_5x5mm_P0.4mm_EP3.8x3.8mm
+UQFN, 40 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=345), generated with kicad-footprint-generator ipc_noLead_generator.py
+UQFN NoLead
+0
+50
+41
+Package_DFN_QFN
+UQFN-40-1EP_5x5mm_P0.4mm_EP3.8x3.8mm_ThermalVias
+UQFN, 40 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=345), generated with kicad-footprint-generator ipc_noLead_generator.py
+UQFN NoLead
+0
+67
+41
+Package_DFN_QFN
+UQFN-48-1EP_6x6mm_P0.4mm_EP4.45x4.45mm
+UQFN, 48 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=347), generated with kicad-footprint-generator ipc_noLead_generator.py
+UQFN NoLead
+0
+58
+49
+Package_DFN_QFN
+UQFN-48-1EP_6x6mm_P0.4mm_EP4.45x4.45mm_ThermalVias
+UQFN, 48 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=347), generated with kicad-footprint-generator ipc_noLead_generator.py
+UQFN NoLead
+0
+75
+49
+Package_DFN_QFN
+UQFN-48-1EP_6x6mm_P0.4mm_EP4.62x4.62mm
+UQFN, 48 Pin (https://github.com/KiCad/kicad-symbols/pull/1189#issuecomment-449506354), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+UQFN DFN_QFN
+0
+53
+49
+Package_DFN_QFN
+UQFN-48-1EP_6x6mm_P0.4mm_EP4.62x4.62mm_ThermalVias
+UQFN, 48 Pin (https://github.com/KiCad/kicad-symbols/pull/1189#issuecomment-449506354), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+UQFN DFN_QFN
+0
+75
+49
+Package_DFN_QFN
+VDFN-8-1EP_2x2mm_P0.5mm_EP0.9x1.7mm
+8-Lead Very Thin Dual Flatpack No-Lead (LZ) - 2x3x0.9 mm Body [VDFN] (see Microchip Packaging Specification 00000049BS.pdf)
+DFN 0.5
+0
+11
+9
+Package_DFN_QFN
+VQFN-16-1EP_3x3mm_P0.5mm_EP1.6x1.6mm
+VQFN, 16 Pin (http://www.ti.com/lit/ds/symlink/cdclvp1102.pdf#page=28), generated with kicad-footprint-generator ipc_noLead_generator.py
+VQFN NoLead
+0
+21
+17
+Package_DFN_QFN
+VQFN-16-1EP_3x3mm_P0.5mm_EP1.6x1.6mm_ThermalVias
+VQFN, 16 Pin (http://www.ti.com/lit/ds/symlink/cdclvp1102.pdf#page=28), generated with kicad-footprint-generator ipc_noLead_generator.py
+VQFN NoLead
+0
+26
+17
+Package_DFN_QFN
+VQFN-16-1EP_3x3mm_P0.5mm_EP1.8x1.8mm
+VQFN, 16 Pin (https://www.st.com/resource/en/datasheet/stspin220.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+VQFN DFN_QFN
+0
+21
+17
+Package_DFN_QFN
+VQFN-16-1EP_3x3mm_P0.5mm_EP1.8x1.8mm_ThermalVias
+VQFN, 16 Pin (https://www.st.com/resource/en/datasheet/stspin220.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+VQFN DFN_QFN
+0
+26
+17
+Package_DFN_QFN
+VQFN-16-1EP_3x3mm_P0.5mm_EP1.45x1.45mm
+VQFN, 16 Pin (http://www.ti.com/lit/ds/sbos354a/sbos354a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+VQFN DFN_QFN
+0
+21
+17
+Package_DFN_QFN
+VQFN-16-1EP_3x3mm_P0.5mm_EP1.45x1.45mm_ThermalVias
+VQFN, 16 Pin (http://www.ti.com/lit/ds/sbos354a/sbos354a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+VQFN DFN_QFN
+0
+26
+17
+Package_DFN_QFN
+VQFN-16-1EP_3x3mm_P0.5mm_EP1.68x1.68mm
+VQFN, 16 Pin (http://www.ti.com/lit/ds/symlink/tlv62095.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+VQFN DFN_QFN
+0
+21
+17
+Package_DFN_QFN
+VQFN-16-1EP_3x3mm_P0.5mm_EP1.68x1.68mm_ThermalVias
+VQFN, 16 Pin (http://www.ti.com/lit/ds/symlink/tlv62095.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+VQFN DFN_QFN
+0
+26
+17
+Package_DFN_QFN
+VQFN-20-1EP_3x3mm_P0.4mm_EP1.7x1.7mm
+VQFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/20%20Lead%20VQFN%203x3x0_9mm_1_7EP%20U2B%20C04-21496a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+VQFN DFN_QFN
+0
+25
+21
+Package_DFN_QFN
+VQFN-20-1EP_3x3mm_P0.4mm_EP1.7x1.7mm_ThermalVias
+VQFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/20%20Lead%20VQFN%203x3x0_9mm_1_7EP%20U2B%20C04-21496a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+VQFN DFN_QFN
+0
+30
+21
+Package_DFN_QFN
+VQFN-20-1EP_3x3mm_P0.45mm_EP1.55x1.55mm
+VQFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc8246.pdf#page=264), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+VQFN DFN_QFN
+0
+25
+21
+Package_DFN_QFN
+VQFN-20-1EP_3x3mm_P0.45mm_EP1.55x1.55mm_ThermalVias
+VQFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc8246.pdf#page=264), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+VQFN DFN_QFN
+0
+30
+21
+Package_DFN_QFN
+VQFN-24-1EP_4x4mm_P0.5mm_EP2.45x2.45mm
+VQFN, 24 Pin (http://www.ti.com/lit/ds/symlink/msp430f1101a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+VQFN DFN_QFN
+0
+34
+25
+Package_DFN_QFN
+VQFN-24-1EP_4x4mm_P0.5mm_EP2.45x2.45mm_ThermalVias
+VQFN, 24 Pin (http://www.ti.com/lit/ds/symlink/msp430f1101a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+VQFN DFN_QFN
+0
+39
+25
+Package_DFN_QFN
+VQFN-28-1EP_4x4mm_P0.45mm_EP2.4x2.4mm
+VQFN, 28 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-9505-AT42-QTouch-BSW-AT42QT1060_Datasheet.pdf#page=28), generated with kicad-footprint-generator ipc_noLead_generator.py
+VQFN NoLead
+0
+33
+29
+Package_DFN_QFN
+VQFN-28-1EP_4x4mm_P0.45mm_EP2.4x2.4mm_ThermalVias
+VQFN, 28 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-9505-AT42-QTouch-BSW-AT42QT1060_Datasheet.pdf#page=28), generated with kicad-footprint-generator ipc_noLead_generator.py
+VQFN NoLead
+0
+43
+29
+Package_DFN_QFN
+VQFN-28-1EP_4x5mm_P0.5mm_EP2.55x3.55mm
+VQFN, 28 Pin (http://www.ti.com/lit/ds/symlink/lm5175.pdf#page=37), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+VQFN DFN_QFN
+0
+35
+29
+Package_DFN_QFN
+VQFN-28-1EP_4x5mm_P0.5mm_EP2.55x3.55mm_ThermalVias
+VQFN, 28 Pin (http://www.ti.com/lit/ds/symlink/lm5175.pdf#page=37), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py
+VQFN DFN_QFN
+0
+48
+29
+Package_DFN_QFN
+VQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm
+VQFN, 32 Pin (http://ww1.microchip.com/downloads/en/devicedoc/atmel-9520-at42-qtouch-bsw-at42qt1110_datasheet.pdf#page=42), generated with kicad-footprint-generator ipc_noLead_generator.py
+VQFN NoLead
+0
+37
+33
+Package_DFN_QFN
+VQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm_ThermalVias
+VQFN, 32 Pin (http://ww1.microchip.com/downloads/en/devicedoc/atmel-9520-at42-qtouch-bsw-at42qt1110_datasheet.pdf#page=42), generated with kicad-footprint-generator ipc_noLead_generator.py
+VQFN NoLead
+0
+47
+33
+Package_DFN_QFN
+VQFN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm
+VQFN, 32 Pin (https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT4222H.pdf#page=40), generated with kicad-footprint-generator ipc_noLead_generator.py
+VQFN NoLead
+0
+37
+33
+Package_DFN_QFN
+VQFN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm_ThermalVias
+VQFN, 32 Pin (https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT4222H.pdf#page=40), generated with kicad-footprint-generator ipc_noLead_generator.py
+VQFN NoLead
+0
+47
+33
+Package_DFN_QFN
+VQFN-46-1EP_5x6mm_P0.4mm_EP2.8x3.8mm
+VQFN, 46 Pin (http://www.ti.com/lit/ds/symlink/lp5036.pdf#page=59), generated with kicad-footprint-generator ipc_noLead_generator.py
+VQFN NoLead
+0
+53
+47
+Package_DFN_QFN
+VQFN-46-1EP_5x6mm_P0.4mm_EP2.8x3.8mm_ThermalVias
+VQFN, 46 Pin (http://www.ti.com/lit/ds/symlink/lp5036.pdf#page=59), generated with kicad-footprint-generator ipc_noLead_generator.py
+VQFN NoLead
+0
+66
+47
+Package_DFN_QFN
+VQFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
+VQFN, 48 Pin (http://www.ti.com/lit/ds/symlink/cc1312r.pdf#page=48), generated with kicad-footprint-generator ipc_noLead_generator.py
+VQFN NoLead
+0
+53
+49
+Package_DFN_QFN
+VQFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm_ThermalVias
+VQFN, 48 Pin (http://www.ti.com/lit/ds/symlink/cc1312r.pdf#page=48), generated with kicad-footprint-generator ipc_noLead_generator.py
+VQFN NoLead
+0
+79
+49
+Package_DFN_QFN
+WDFN-8-1EP_2x2.2mm_P0.5mm_EP0.80x0.54
+https://www.onsemi.com/pub/Collateral/511BN.PDF
+WDFN-8 1EP 2.2X2.0 0.5P
+0
+9
+9
+Package_DFN_QFN
+WDFN-8-1EP_3x2mm_P0.5mm_EP1.3x1.4mm
+WDFN, 8 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/8L_TDFN_2x3_MNY_C04-0129E-MNY.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+WDFN NoLead
+0
+13
+9
+Package_DFN_QFN
+WDFN-8_2x2mm_P0.5mm
+DFN8 2x2, 0.5P; No exposed pad (http://www.onsemi.com/pub/Collateral/NCP4308-D.PDF)
+DFN 0.5
+0
+8
+8
+Package_DFN_QFN
+WDFN-12-1EP_3x3mm_P0.45mm_EP1.7x2.5mm
+WDFN, 12 Pin (https://www.diodes.com/assets/Datasheets/PAM2306.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+WDFN NoLead
+0
+17
+13
+Package_DFN_QFN
+WQFN-14-1EP_2.5x2.5mm_P0.5mm_EP1.45x1.45mm
+WQFN, 14 Pin (https://www.onsemi.com/pub/Collateral/FUSB302B-D.PDF#page=32), generated with kicad-footprint-generator ipc_noLead_generator.py
+WQFN NoLead
+0
+19
+15
+Package_DFN_QFN
+WQFN-14-1EP_2.5x2.5mm_P0.5mm_EP1.45x1.45mm_ThermalVias
+WQFN, 14 Pin (https://www.onsemi.com/pub/Collateral/FUSB302B-D.PDF#page=32), generated with kicad-footprint-generator ipc_noLead_generator.py
+WQFN NoLead
+0
+24
+15
+Package_DFN_QFN
+WQFN-16-1EP_3x3mm_P0.5mm_EP1.75x1.75mm
+WQFN, 16 Pin (https://www.onsemi.com/pub/Collateral/FUSB307B-D.PDF#page=56), generated with kicad-footprint-generator ipc_noLead_generator.py
+WQFN NoLead
+0
+21
+17
+Package_DFN_QFN
+WQFN-16-1EP_3x3mm_P0.5mm_EP1.75x1.75mm_ThermalVias
+WQFN, 16 Pin (https://www.onsemi.com/pub/Collateral/FUSB307B-D.PDF#page=56), generated with kicad-footprint-generator ipc_noLead_generator.py
+WQFN NoLead
+0
+26
+17
+Package_DFN_QFN
+WQFN-16-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
+WQFN, 16 Pin (http://www.ti.com/lit/ds/symlink/ldc1312.pdf#page=59), generated with kicad-footprint-generator ipc_noLead_generator.py
+WQFN NoLead
+0
+21
+17
+Package_DFN_QFN
+WQFN-16-1EP_4x4mm_P0.5mm_EP2.6x2.6mm_ThermalVias
+WQFN, 16 Pin (http://www.ti.com/lit/ds/symlink/ldc1312.pdf#page=59), generated with kicad-footprint-generator ipc_noLead_generator.py
+WQFN NoLead
+0
+31
+17
+Package_DFN_QFN
+WQFN-20-1EP_2.5x4.5mm_P0.5mm_EP1x2.9mm
+http://www.onsemi.com/pub/Collateral/510CD.PDF
+WQFN-20 4.5mm 2.5mm 0.5mm
+0
+24
+21
+Package_DFN_QFN
+WQFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
+WQFN, 24 Pin (http://www.ti.com/lit/ds/symlink/lm26480.pdf#page=39), generated with kicad-footprint-generator ipc_noLead_generator.py
+WQFN NoLead
+0
+29
+25
+Package_DFN_QFN
+WQFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm_ThermalVias
+WQFN, 24 Pin (http://www.ti.com/lit/ds/symlink/lm26480.pdf#page=39), generated with kicad-footprint-generator ipc_noLead_generator.py
+WQFN NoLead
+0
+39
+25
+Package_DFN_QFN
+WQFN-24-1EP_4x4mm_P0.5mm_EP2.45x2.45mm
+WQFN, 24 Pin (http://www.ti.com/lit/ds/symlink/ts3a27518e.pdf#page=33), generated with kicad-footprint-generator ipc_noLead_generator.py
+WQFN NoLead
+0
+29
+25
+Package_DFN_QFN
+WQFN-24-1EP_4x4mm_P0.5mm_EP2.45x2.45mm_ThermalVias
+WQFN, 24 Pin (http://www.ti.com/lit/ds/symlink/ts3a27518e.pdf#page=33), generated with kicad-footprint-generator ipc_noLead_generator.py
+WQFN NoLead
+0
+39
+25
+Package_DFN_QFN
+WQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm
+QFN, 32-Leads, Body 5x5x0.8mm, Pitch 0.5mm, Thermal Pad 3.1x3.1mm; (see Texas Instruments LM25119 http://www.ti.com/lit/ds/symlink/lm25119.pdf)
+WQFN 0.5
+0
+37
+33
+Package_DIP
+DIP-4_W7.62mm
+4-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil
+0
+4
+4
+Package_DIP
+DIP-4_W7.62mm_LongPads
+4-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads
+0
+4
+4
+Package_DIP
+DIP-4_W7.62mm_SMDSocket_SmallPads
+4-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads
+0
+4
+4
+Package_DIP
+DIP-4_W7.62mm_Socket
+4-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket
+0
+4
+4
+Package_DIP
+DIP-4_W7.62mm_Socket_LongPads
+4-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads
+0
+4
+4
+Package_DIP
+DIP-4_W8.89mm_SMDSocket_LongPads
+4-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads
+0
+4
+4
+Package_DIP
+DIP-4_W10.16mm
+4-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils)
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil
+0
+4
+4
+Package_DIP
+DIP-4_W10.16mm_LongPads
+4-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads
+0
+4
+4
+Package_DIP
+DIP-5-6_W7.62mm
+5-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil
+0
+5
+5
+Package_DIP
+DIP-5-6_W7.62mm_LongPads
+5-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads
+0
+5
+5
+Package_DIP
+DIP-5-6_W7.62mm_SMDSocket_SmallPads
+5-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads
+0
+5
+5
+Package_DIP
+DIP-5-6_W7.62mm_Socket
+5-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket
+0
+5
+5
+Package_DIP
+DIP-5-6_W7.62mm_Socket_LongPads
+5-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads
+0
+5
+5
+Package_DIP
+DIP-5-6_W8.89mm_SMDSocket_LongPads
+5-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads
+0
+5
+5
+Package_DIP
+DIP-5-6_W10.16mm
+5-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils)
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil
+0
+5
+5
+Package_DIP
+DIP-5-6_W10.16mm_LongPads
+5-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads
+0
+5
+5
+Package_DIP
+DIP-6_W7.62mm
+6-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil
+0
+6
+6
+Package_DIP
+DIP-6_W7.62mm_LongPads
+6-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads
+0
+6
+6
+Package_DIP
+DIP-6_W7.62mm_SMDSocket_SmallPads
+6-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads
+0
+6
+6
+Package_DIP
+DIP-6_W7.62mm_Socket
+6-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket
+0
+6
+6
+Package_DIP
+DIP-6_W7.62mm_Socket_LongPads
+6-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads
+0
+6
+6
+Package_DIP
+DIP-6_W8.89mm_SMDSocket_LongPads
+6-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads
+0
+6
+6
+Package_DIP
+DIP-6_W10.16mm
+6-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils)
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil
+0
+6
+6
+Package_DIP
+DIP-6_W10.16mm_LongPads
+6-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads
+0
+6
+6
+Package_DIP
+DIP-8-16_W7.62mm
+16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil
+0
+8
+8
+Package_DIP
+DIP-8-16_W7.62mm_Socket
+16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket
+0
+8
+8
+Package_DIP
+DIP-8-16_W7.62mm_Socket_LongPads
+16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads
+0
+8
+8
+Package_DIP
+DIP-8-N6_W7.62mm
+8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), missing pin 6
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil
+0
+7
+7
+Package_DIP
+DIP-8-N7_W7.62mm
+8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), missing pin 7
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil
+0
+7
+7
+Package_DIP
+DIP-8_W7.62mm
+8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil
+0
+8
+8
+Package_DIP
+DIP-8_W7.62mm_LongPads
+8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads
+0
+8
+8
+Package_DIP
+DIP-8_W7.62mm_SMDSocket_SmallPads
+8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads
+0
+8
+8
+Package_DIP
+DIP-8_W7.62mm_Socket
+8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket
+0
+8
+8
+Package_DIP
+DIP-8_W7.62mm_Socket_LongPads
+8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads
+0
+8
+8
+Package_DIP
+DIP-8_W8.89mm_SMDSocket_LongPads
+8-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads
+0
+8
+8
+Package_DIP
+DIP-8_W10.16mm
+8-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils)
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil
+0
+8
+8
+Package_DIP
+DIP-8_W10.16mm_LongPads
+8-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads
+0
+8
+8
+Package_DIP
+DIP-10_W7.62mm
+10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil
+0
+10
+10
+Package_DIP
+DIP-10_W7.62mm_LongPads
+10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads
+0
+10
+10
+Package_DIP
+DIP-10_W7.62mm_SMDSocket_SmallPads
+10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads
+0
+10
+10
+Package_DIP
+DIP-10_W7.62mm_Socket
+10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket
+0
+10
+10
+Package_DIP
+DIP-10_W7.62mm_Socket_LongPads
+10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads
+0
+10
+10
+Package_DIP
+DIP-10_W8.89mm_SMDSocket_LongPads
+10-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads
+0
+10
+10
+Package_DIP
+DIP-10_W10.16mm
+10-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils)
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil
+0
+10
+10
+Package_DIP
+DIP-10_W10.16mm_LongPads
+10-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads
+0
+10
+10
+Package_DIP
+DIP-12_W7.62mm
+12-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil
+0
+12
+12
+Package_DIP
+DIP-12_W7.62mm_LongPads
+12-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads
+0
+12
+12
+Package_DIP
+DIP-12_W7.62mm_SMDSocket_SmallPads
+12-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads
+0
+12
+12
+Package_DIP
+DIP-12_W7.62mm_Socket
+12-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket
+0
+12
+12
+Package_DIP
+DIP-12_W7.62mm_Socket_LongPads
+12-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads
+0
+12
+12
+Package_DIP
+DIP-12_W8.89mm_SMDSocket_LongPads
+12-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads
+0
+12
+12
+Package_DIP
+DIP-12_W10.16mm
+12-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils)
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil
+0
+12
+12
+Package_DIP
+DIP-12_W10.16mm_LongPads
+12-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads
+0
+12
+12
+Package_DIP
+DIP-14_W7.62mm
+14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil
+0
+14
+14
+Package_DIP
+DIP-14_W7.62mm_LongPads
+14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads
+0
+14
+14
+Package_DIP
+DIP-14_W7.62mm_SMDSocket_SmallPads
+14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads
+0
+14
+14
+Package_DIP
+DIP-14_W7.62mm_Socket
+14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket
+0
+14
+14
+Package_DIP
+DIP-14_W7.62mm_Socket_LongPads
+14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads
+0
+14
+14
+Package_DIP
+DIP-14_W8.89mm_SMDSocket_LongPads
+14-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads
+0
+14
+14
+Package_DIP
+DIP-14_W10.16mm
+14-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils)
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil
+0
+14
+14
+Package_DIP
+DIP-14_W10.16mm_LongPads
+14-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads
+0
+14
+14
+Package_DIP
+DIP-16_W7.62mm
+16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil
+0
+16
+16
+Package_DIP
+DIP-16_W7.62mm_LongPads
+16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads
+0
+16
+16
+Package_DIP
+DIP-16_W7.62mm_SMDSocket_SmallPads
+16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads
+0
+16
+16
+Package_DIP
+DIP-16_W7.62mm_Socket
+16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket
+0
+16
+16
+Package_DIP
+DIP-16_W7.62mm_Socket_LongPads
+16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads
+0
+16
+16
+Package_DIP
+DIP-16_W8.89mm_SMDSocket_LongPads
+16-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads
+0
+16
+16
+Package_DIP
+DIP-16_W10.16mm
+16-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils)
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil
+0
+16
+16
+Package_DIP
+DIP-16_W10.16mm_LongPads
+16-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads
+0
+16
+16
+Package_DIP
+DIP-18_W7.62mm
+18-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil
+0
+18
+18
+Package_DIP
+DIP-18_W7.62mm_LongPads
+18-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads
+0
+18
+18
+Package_DIP
+DIP-18_W7.62mm_SMDSocket_SmallPads
+18-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads
+0
+18
+18
+Package_DIP
+DIP-18_W7.62mm_Socket
+18-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket
+0
+18
+18
+Package_DIP
+DIP-18_W7.62mm_Socket_LongPads
+18-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads
+0
+18
+18
+Package_DIP
+DIP-18_W8.89mm_SMDSocket_LongPads
+18-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads
+0
+18
+18
+Package_DIP
+DIP-20_W7.62mm
+20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil
+0
+20
+20
+Package_DIP
+DIP-20_W7.62mm_LongPads
+20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads
+0
+20
+20
+Package_DIP
+DIP-20_W7.62mm_SMDSocket_SmallPads
+20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads
+0
+20
+20
+Package_DIP
+DIP-20_W7.62mm_Socket
+20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket
+0
+20
+20
+Package_DIP
+DIP-20_W7.62mm_Socket_LongPads
+20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads
+0
+20
+20
+Package_DIP
+DIP-20_W8.89mm_SMDSocket_LongPads
+20-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads
+0
+20
+20
+Package_DIP
+DIP-22_W7.62mm
+22-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil
+0
+22
+22
+Package_DIP
+DIP-22_W7.62mm_LongPads
+22-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads
+0
+22
+22
+Package_DIP
+DIP-22_W7.62mm_SMDSocket_SmallPads
+22-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads
+0
+22
+22
+Package_DIP
+DIP-22_W7.62mm_Socket
+22-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket
+0
+22
+22
+Package_DIP
+DIP-22_W7.62mm_Socket_LongPads
+22-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads
+0
+22
+22
+Package_DIP
+DIP-22_W8.89mm_SMDSocket_LongPads
+22-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads
+0
+22
+22
+Package_DIP
+DIP-22_W10.16mm
+22-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils)
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil
+0
+22
+22
+Package_DIP
+DIP-22_W10.16mm_LongPads
+22-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads
+0
+22
+22
+Package_DIP
+DIP-22_W10.16mm_SMDSocket_SmallPads
+22-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil SMDSocket SmallPads
+0
+22
+22
+Package_DIP
+DIP-22_W10.16mm_Socket
+22-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), Socket
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil Socket
+0
+22
+22
+Package_DIP
+DIP-22_W10.16mm_Socket_LongPads
+22-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil Socket LongPads
+0
+22
+22
+Package_DIP
+DIP-22_W11.43mm_SMDSocket_LongPads
+22-lead though-hole mounted DIP package, row spacing 11.43 mm (450 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 11.43mm 450mil SMDSocket LongPads
+0
+22
+22
+Package_DIP
+DIP-24_W7.62mm
+24-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil
+0
+24
+24
+Package_DIP
+DIP-24_W7.62mm_LongPads
+24-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads
+0
+24
+24
+Package_DIP
+DIP-24_W7.62mm_SMDSocket_SmallPads
+24-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads
+0
+24
+24
+Package_DIP
+DIP-24_W7.62mm_Socket
+24-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket
+0
+24
+24
+Package_DIP
+DIP-24_W7.62mm_Socket_LongPads
+24-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads
+0
+24
+24
+Package_DIP
+DIP-24_W8.89mm_SMDSocket_LongPads
+24-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads
+0
+24
+24
+Package_DIP
+DIP-24_W10.16mm
+24-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils)
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil
+0
+24
+24
+Package_DIP
+DIP-24_W10.16mm_LongPads
+24-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads
+0
+24
+24
+Package_DIP
+DIP-24_W10.16mm_SMDSocket_SmallPads
+24-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil SMDSocket SmallPads
+0
+24
+24
+Package_DIP
+DIP-24_W10.16mm_Socket
+24-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), Socket
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil Socket
+0
+24
+24
+Package_DIP
+DIP-24_W10.16mm_Socket_LongPads
+24-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 10.16mm 400mil Socket LongPads
+0
+24
+24
+Package_DIP
+DIP-24_W11.43mm_SMDSocket_LongPads
+24-lead though-hole mounted DIP package, row spacing 11.43 mm (450 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 11.43mm 450mil SMDSocket LongPads
+0
+24
+24
+Package_DIP
+DIP-24_W15.24mm
+24-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils)
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil
+0
+24
+24
+Package_DIP
+DIP-24_W15.24mm_LongPads
+24-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads
+0
+24
+24
+Package_DIP
+DIP-24_W15.24mm_SMDSocket_SmallPads
+24-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads
+0
+24
+24
+Package_DIP
+DIP-24_W15.24mm_Socket
+24-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket
+0
+24
+24
+Package_DIP
+DIP-24_W15.24mm_Socket_LongPads
+24-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads
+0
+24
+24
+Package_DIP
+DIP-24_W16.51mm_SMDSocket_LongPads
+24-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads
+0
+24
+24
+Package_DIP
+DIP-28_W7.62mm
+28-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil
+0
+28
+28
+Package_DIP
+DIP-28_W7.62mm_LongPads
+28-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads
+0
+28
+28
+Package_DIP
+DIP-28_W7.62mm_SMDSocket_SmallPads
+28-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads
+0
+28
+28
+Package_DIP
+DIP-28_W7.62mm_Socket
+28-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket
+0
+28
+28
+Package_DIP
+DIP-28_W7.62mm_Socket_LongPads
+28-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads
+0
+28
+28
+Package_DIP
+DIP-28_W8.89mm_SMDSocket_LongPads
+28-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads
+0
+28
+28
+Package_DIP
+DIP-28_W15.24mm
+28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils)
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil
+0
+28
+28
+Package_DIP
+DIP-28_W15.24mm_LongPads
+28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads
+0
+28
+28
+Package_DIP
+DIP-28_W15.24mm_SMDSocket_SmallPads
+28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads
+0
+28
+28
+Package_DIP
+DIP-28_W15.24mm_Socket
+28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket
+0
+28
+28
+Package_DIP
+DIP-28_W15.24mm_Socket_LongPads
+28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads
+0
+28
+28
+Package_DIP
+DIP-28_W16.51mm_SMDSocket_LongPads
+28-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads
+0
+28
+28
+Package_DIP
+DIP-32_W7.62mm
+32-lead dip package, row spacing 7.62 mm (300 mils)
+DIL DIP PDIP 2.54mm 7.62mm 300mil
+0
+32
+32
+Package_DIP
+DIP-32_W15.24mm
+32-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils)
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil
+0
+32
+32
+Package_DIP
+DIP-32_W15.24mm_LongPads
+32-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads
+0
+32
+32
+Package_DIP
+DIP-32_W15.24mm_SMDSocket_SmallPads
+32-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads
+0
+32
+32
+Package_DIP
+DIP-32_W15.24mm_Socket
+32-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket
+0
+32
+32
+Package_DIP
+DIP-32_W15.24mm_Socket_LongPads
+32-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads
+0
+32
+32
+Package_DIP
+DIP-32_W16.51mm_SMDSocket_LongPads
+32-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads
+0
+32
+32
+Package_DIP
+DIP-40_W15.24mm
+40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils)
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil
+0
+40
+40
+Package_DIP
+DIP-40_W15.24mm_LongPads
+40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads
+0
+40
+40
+Package_DIP
+DIP-40_W15.24mm_SMDSocket_SmallPads
+40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads
+0
+40
+40
+Package_DIP
+DIP-40_W15.24mm_Socket
+40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket
+0
+40
+40
+Package_DIP
+DIP-40_W15.24mm_Socket_LongPads
+40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads
+0
+40
+40
+Package_DIP
+DIP-40_W16.51mm_SMDSocket_LongPads
+40-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads
+0
+40
+40
+Package_DIP
+DIP-40_W25.4mm
+40-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils)
+THT DIP DIL PDIP 2.54mm 25.4mm 1000mil
+0
+40
+40
+Package_DIP
+DIP-40_W25.4mm_LongPads
+40-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), LongPads
+THT DIP DIL PDIP 2.54mm 25.4mm 1000mil LongPads
+0
+40
+40
+Package_DIP
+DIP-40_W25.4mm_SMDSocket_SmallPads
+40-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 25.4mm 1000mil SMDSocket SmallPads
+0
+40
+40
+Package_DIP
+DIP-40_W25.4mm_Socket
+40-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), Socket
+THT DIP DIL PDIP 2.54mm 25.4mm 1000mil Socket
+0
+40
+40
+Package_DIP
+DIP-40_W25.4mm_Socket_LongPads
+40-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 25.4mm 1000mil Socket LongPads
+0
+40
+40
+Package_DIP
+DIP-40_W26.67mm_SMDSocket_LongPads
+40-lead though-hole mounted DIP package, row spacing 26.67 mm (1050 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 26.669999999999998mm 1050mil SMDSocket LongPads
+0
+40
+40
+Package_DIP
+DIP-42_W15.24mm
+42-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils)
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil
+0
+42
+42
+Package_DIP
+DIP-42_W15.24mm_LongPads
+42-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads
+0
+42
+42
+Package_DIP
+DIP-42_W15.24mm_SMDSocket_SmallPads
+42-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads
+0
+42
+42
+Package_DIP
+DIP-42_W15.24mm_Socket
+42-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket
+0
+42
+42
+Package_DIP
+DIP-42_W15.24mm_Socket_LongPads
+42-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads
+0
+42
+42
+Package_DIP
+DIP-42_W16.51mm_SMDSocket_LongPads
+42-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads
+0
+42
+42
+Package_DIP
+DIP-48_W15.24mm
+48-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils)
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil
+0
+48
+48
+Package_DIP
+DIP-48_W15.24mm_LongPads
+48-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads
+0
+48
+48
+Package_DIP
+DIP-48_W15.24mm_SMDSocket_SmallPads
+48-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads
+0
+48
+48
+Package_DIP
+DIP-48_W15.24mm_Socket
+48-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket
+0
+48
+48
+Package_DIP
+DIP-48_W15.24mm_Socket_LongPads
+48-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads
+0
+48
+48
+Package_DIP
+DIP-48_W16.51mm_SMDSocket_LongPads
+48-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads
+0
+48
+48
+Package_DIP
+DIP-64_W15.24mm
+64-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils)
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil
+0
+64
+64
+Package_DIP
+DIP-64_W15.24mm_LongPads
+64-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads
+0
+64
+64
+Package_DIP
+DIP-64_W15.24mm_SMDSocket_SmallPads
+64-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads
+0
+64
+64
+Package_DIP
+DIP-64_W15.24mm_Socket
+64-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket
+0
+64
+64
+Package_DIP
+DIP-64_W15.24mm_Socket_LongPads
+64-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads
+0
+64
+64
+Package_DIP
+DIP-64_W16.51mm_SMDSocket_LongPads
+64-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads
+0
+64
+64
+Package_DIP
+DIP-64_W22.86mm
+64-lead though-hole mounted DIP package, row spacing 22.86 mm (900 mils)
+THT DIP DIL PDIP 2.54mm 22.86mm 900mil
+0
+64
+64
+Package_DIP
+DIP-64_W22.86mm_LongPads
+64-lead though-hole mounted DIP package, row spacing 22.86 mm (900 mils), LongPads
+THT DIP DIL PDIP 2.54mm 22.86mm 900mil LongPads
+0
+64
+64
+Package_DIP
+DIP-64_W22.86mm_SMDSocket_SmallPads
+64-lead though-hole mounted DIP package, row spacing 22.86 mm (900 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 22.86mm 900mil SMDSocket SmallPads
+0
+64
+64
+Package_DIP
+DIP-64_W22.86mm_Socket
+64-lead though-hole mounted DIP package, row spacing 22.86 mm (900 mils), Socket
+THT DIP DIL PDIP 2.54mm 22.86mm 900mil Socket
+0
+64
+64
+Package_DIP
+DIP-64_W22.86mm_Socket_LongPads
+64-lead though-hole mounted DIP package, row spacing 22.86 mm (900 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 22.86mm 900mil Socket LongPads
+0
+64
+64
+Package_DIP
+DIP-64_W24.13mm_SMDSocket_LongPads
+64-lead though-hole mounted DIP package, row spacing 24.13 mm (950 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 24.13mm 950mil SMDSocket LongPads
+0
+64
+64
+Package_DIP
+DIP-64_W25.4mm
+64-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils)
+THT DIP DIL PDIP 2.54mm 25.4mm 1000mil
+0
+64
+64
+Package_DIP
+DIP-64_W25.4mm_LongPads
+64-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), LongPads
+THT DIP DIL PDIP 2.54mm 25.4mm 1000mil LongPads
+0
+64
+64
+Package_DIP
+DIP-64_W25.4mm_SMDSocket_SmallPads
+64-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), SMDSocket, SmallPads
+THT DIP DIL PDIP 2.54mm 25.4mm 1000mil SMDSocket SmallPads
+0
+64
+64
+Package_DIP
+DIP-64_W25.4mm_Socket
+64-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), Socket
+THT DIP DIL PDIP 2.54mm 25.4mm 1000mil Socket
+0
+64
+64
+Package_DIP
+DIP-64_W25.4mm_Socket_LongPads
+64-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), Socket, LongPads
+THT DIP DIL PDIP 2.54mm 25.4mm 1000mil Socket LongPads
+0
+64
+64
+Package_DIP
+DIP-64_W26.67mm_SMDSocket_LongPads
+64-lead though-hole mounted DIP package, row spacing 26.67 mm (1050 mils), SMDSocket, LongPads
+THT DIP DIL PDIP 2.54mm 26.669999999999998mm 1050mil SMDSocket LongPads
+0
+64
+64
+Package_DIP
+Fairchild_LSOP-8
+8-Lead, 300\" Wide, Surface Mount Package (https://www.fairchildsemi.com/package-drawings/ML/MLSOP08A.pdf)
+LSOP 2.54mm 300mil
+0
+8
+8
+Package_DIP
+PowerIntegrations_PDIP-8B
+Power Integrations variant of 8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads, see https://www.power.com/sites/default/files/product-docs/lnk520.pdf
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads
+0
+7
+7
+Package_DIP
+PowerIntegrations_PDIP-8C
+Power Integrations variant of 8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads, see https://ac-dc.power.com/sites/default/files/product-docs/tinyswitch-iii_family_datasheet.pdf
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads
+0
+7
+7
+Package_DIP
+PowerIntegrations_SDIP-10C
+PowerIntegrations variant of 10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads, see https://www.power.com/sites/default/files/product-docs/tophx_family_datasheet.pdf
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads
+0
+9
+9
+Package_DIP
+PowerIntegrations_SMD-8
+PowerIntegrations variant of 8-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils), see https://www.power.com/sites/default/files/product-docs/lnk520.pdf
+SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil
+0
+8
+8
+Package_DIP
+PowerIntegrations_SMD-8B
+PowerIntegrations variant of 8-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils), see https://www.power.com/sites/default/files/product-docs/lnk520.pdf
+SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil
+0
+7
+7
+Package_DIP
+PowerIntegrations_SMD-8C
+PowerIntegrations variant of 8-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils), see https://ac-dc.power.com/sites/default/files/product-docs/tinyswitch-iii_family_datasheet.pdf
+SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil
+0
+7
+7
+Package_DIP
+PowerIntegrations_eDIP-12B
+Power Integrations eDIP-12B, see https://www.power.com/sites/default/files/product-docs/linkswitch-pl_family_datasheet.pdf
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil
+0
+11
+11
+Package_DIP
+SMDIP-4_W7.62mm
+4-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil
+0
+4
+4
+Package_DIP
+SMDIP-4_W9.53mm
+4-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil
+0
+4
+4
+Package_DIP
+SMDIP-4_W9.53mm_Clearance8mm
+4-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm
+0
+4
+4
+Package_DIP
+SMDIP-4_W11.48mm
+4-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil
+0
+4
+4
+Package_DIP
+SMDIP-6_W7.62mm
+6-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil
+0
+6
+6
+Package_DIP
+SMDIP-6_W9.53mm
+6-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil
+0
+6
+6
+Package_DIP
+SMDIP-6_W9.53mm_Clearance8mm
+6-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm
+0
+6
+6
+Package_DIP
+SMDIP-6_W11.48mm
+6-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil
+0
+6
+6
+Package_DIP
+SMDIP-8_W7.62mm
+8-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil
+0
+8
+8
+Package_DIP
+SMDIP-8_W9.53mm
+8-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil
+0
+8
+8
+Package_DIP
+SMDIP-8_W9.53mm_Clearance8mm
+8-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm
+0
+8
+8
+Package_DIP
+SMDIP-8_W11.48mm
+8-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil
+0
+8
+8
+Package_DIP
+SMDIP-10_W7.62mm
+10-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil
+0
+10
+10
+Package_DIP
+SMDIP-10_W9.53mm
+10-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil
+0
+10
+10
+Package_DIP
+SMDIP-10_W9.53mm_Clearance8mm
+10-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm
+0
+10
+10
+Package_DIP
+SMDIP-10_W11.48mm
+10-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil
+0
+10
+10
+Package_DIP
+SMDIP-12_W7.62mm
+12-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil
+0
+12
+12
+Package_DIP
+SMDIP-12_W9.53mm
+12-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil
+0
+12
+12
+Package_DIP
+SMDIP-12_W9.53mm_Clearance8mm
+12-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm
+0
+12
+12
+Package_DIP
+SMDIP-12_W11.48mm
+12-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil
+0
+12
+12
+Package_DIP
+SMDIP-14_W7.62mm
+14-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil
+0
+14
+14
+Package_DIP
+SMDIP-14_W9.53mm
+14-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil
+0
+14
+14
+Package_DIP
+SMDIP-14_W9.53mm_Clearance8mm
+14-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm
+0
+14
+14
+Package_DIP
+SMDIP-14_W11.48mm
+14-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil
+0
+14
+14
+Package_DIP
+SMDIP-16_W7.62mm
+16-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil
+0
+16
+16
+Package_DIP
+SMDIP-16_W9.53mm
+16-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil
+0
+16
+16
+Package_DIP
+SMDIP-16_W9.53mm_Clearance8mm
+16-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm
+0
+16
+16
+Package_DIP
+SMDIP-16_W11.48mm
+16-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil
+0
+16
+16
+Package_DIP
+SMDIP-18_W7.62mm
+18-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil
+0
+18
+18
+Package_DIP
+SMDIP-18_W9.53mm
+18-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil
+0
+18
+18
+Package_DIP
+SMDIP-18_W9.53mm_Clearance8mm
+18-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm
+0
+18
+18
+Package_DIP
+SMDIP-18_W11.48mm
+18-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil
+0
+18
+18
+Package_DIP
+SMDIP-20_W7.62mm
+20-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil
+0
+20
+20
+Package_DIP
+SMDIP-20_W9.53mm
+20-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil
+0
+20
+20
+Package_DIP
+SMDIP-20_W9.53mm_Clearance8mm
+20-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm
+0
+20
+20
+Package_DIP
+SMDIP-20_W11.48mm
+20-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil
+0
+20
+20
+Package_DIP
+SMDIP-22_W7.62mm
+22-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil
+0
+22
+22
+Package_DIP
+SMDIP-22_W9.53mm
+22-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil
+0
+22
+22
+Package_DIP
+SMDIP-22_W9.53mm_Clearance8mm
+22-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm
+0
+22
+22
+Package_DIP
+SMDIP-22_W11.48mm
+22-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil
+0
+22
+22
+Package_DIP
+SMDIP-24_W7.62mm
+24-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil
+0
+24
+24
+Package_DIP
+SMDIP-24_W9.53mm
+24-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil
+0
+24
+24
+Package_DIP
+SMDIP-24_W11.48mm
+24-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil
+0
+24
+24
+Package_DIP
+SMDIP-24_W15.24mm
+24-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil
+0
+24
+24
+Package_DIP
+SMDIP-28_W15.24mm
+28-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil
+0
+28
+28
+Package_DIP
+SMDIP-32_W7.62mm
+32-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil
+0
+32
+32
+Package_DIP
+SMDIP-32_W9.53mm
+32-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil
+0
+32
+32
+Package_DIP
+SMDIP-32_W11.48mm
+32-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil
+0
+32
+32
+Package_DIP
+SMDIP-32_W15.24mm
+32-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil
+0
+32
+32
+Package_DIP
+SMDIP-40_W15.24mm
+40-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil
+0
+40
+40
+Package_DIP
+SMDIP-40_W25.24mm
+40-lead surface-mounted (SMD) DIP package, row spacing 25.24 mm (993 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 25.24mm 993mil
+0
+40
+40
+Package_DIP
+SMDIP-42_W15.24mm
+42-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil
+0
+42
+42
+Package_DIP
+SMDIP-48_W15.24mm
+48-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil
+0
+48
+48
+Package_DIP
+SMDIP-64_W15.24mm
+64-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils)
+SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil
+0
+64
+64
+Package_DIP
+Toshiba_11-7A9
+Toshiba 11-7A9 package, like 6-lead dip package with missing pin 5, row spacing 7.62 mm (300 mils), https://toshiba.semicon-storage.com/info/docget.jsp?did=1421&prodName=TLP3021(S)
+Toshiba 11-7A9 DIL DIP PDIP 2.54mm 7.62mm 300mil
+0
+5
+5
+Package_DIP
+Vishay_HVM-DIP-3_W7.62mm
+3-lead though-hole mounted high-volatge DIP package (based on standard DIP-4), row spacing 7.62 mm (300 mils), see https://www.vishay.com/docs/91361/hexdip.pdf
+THT DIP DIL PDIP 2.54mm 7.62mm 300mil Vishay HVMDIP HEXDIP
+0
+4
+3
+Package_DirectFET
+DirectFET_L4
+DirectFET L4 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=41
+DirectFET L4 MOSFET Infineon
+0
+11
+3
+Package_DirectFET
+DirectFET_L6
+DirectFET L6 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=42
+DirectFET L6 MOSFET Infineon
+0
+13
+3
+Package_DirectFET
+DirectFET_L8
+DirectFET L8 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=43
+DirectFET L8 MOSFET Infineon
+0
+15
+3
+Package_DirectFET
+DirectFET_LA
+DirectFET LA https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=44
+DirectFET LA MOSFET Infineon
+0
+15
+3
+Package_DirectFET
+DirectFET_M2
+DirectFET M2 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=33
+DirectFET M2 MOSFET Infineon
+0
+7
+3
+Package_DirectFET
+DirectFET_M4
+DirectFET M4 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=34
+DirectFET M4 MOSFET Infineon
+0
+9
+3
+Package_DirectFET
+DirectFET_MA
+DirectFET MA https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=35
+DirectFET MA MOSFET Infineon
+0
+8
+3
+Package_DirectFET
+DirectFET_MB
+DirectFET MB https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=36
+DirectFET MB MOSFET Infineon
+0
+8
+3
+Package_DirectFET
+DirectFET_MC
+DirectFET MC https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=37
+DirectFET MC MOSFET Infineon
+0
+10
+3
+Package_DirectFET
+DirectFET_MD
+DirectFET MD https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=38
+DirectFET MD MOSFET Infineon
+0
+8
+3
+Package_DirectFET
+DirectFET_ME
+DirectFET ME https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=39
+DirectFET ME MOSFET Infineon
+0
+10
+3
+Package_DirectFET
+DirectFET_MF
+DirectFET MF https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=40
+DirectFET MF MOSFET Infineon
+0
+8
+3
+Package_DirectFET
+DirectFET_MN
+DirectFET MN https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=30
+DirectFET MN MOSFET Infineon
+0
+7
+3
+Package_DirectFET
+DirectFET_MP
+DirectFET MP https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=28
+DirectFET MP MOSFET Infineon
+0
+7
+3
+Package_DirectFET
+DirectFET_MQ
+DirectFET MQ https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=29
+DirectFET MQ MOSFET Infineon
+0
+7
+3
+Package_DirectFET
+DirectFET_MT
+DirectFET MT https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=26
+DirectFET MT MOSFET Infineon
+0
+7
+3
+Package_DirectFET
+DirectFET_MU
+DirectFET MU https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=32
+DirectFET MU MOSFET Infineon
+0
+7
+3
+Package_DirectFET
+DirectFET_MX
+DirectFET MX https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=27
+DirectFET MX MOSFET Infineon
+0
+7
+3
+Package_DirectFET
+DirectFET_MZ
+DirectFET MZ https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=31
+DirectFET MZ MOSFET Infineon
+0
+7
+3
+Package_DirectFET
+DirectFET_S1
+DirectFET S1 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=20
+DirectFET S1 MOSFET Infineon
+0
+6
+3
+Package_DirectFET
+DirectFET_S2
+DirectFET S2 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=21
+DirectFET S2 MOSFET Infineon
+0
+7
+3
+Package_DirectFET
+DirectFET_S3C
+DirectFET S3C https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=25
+DirectFET S3C MOSFET Infineon
+0
+8
+3
+Package_DirectFET
+DirectFET_SA
+DirectFET SA https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=22
+DirectFET SA MOSFET Infineon
+0
+8
+3
+Package_DirectFET
+DirectFET_SB
+DirectFET SB https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=23
+DirectFET SB MOSFET Infineon
+0
+6
+3
+Package_DirectFET
+DirectFET_SC
+DirectFET SC https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=24
+DirectFET SC MOSFET Infineon
+0
+7
+3
+Package_DirectFET
+DirectFET_SH
+DirectFET SH https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=19
+DirectFET SH MOSFET Infineon
+0
+6
+3
+Package_DirectFET
+DirectFET_SJ
+DirectFET SJ https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=18
+DirectFET SJ MOSFET Infineon
+0
+7
+3
+Package_DirectFET
+DirectFET_SQ
+DirectFET SQ https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=17
+DirectFET SQ MOSFET Infineon
+0
+6
+3
+Package_DirectFET
+DirectFET_ST
+DirectFET ST https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=16
+DirectFET ST MOSFET Infineon
+0
+7
+3
+Package_LCC
+PLCC-20
+PLCC, 20 pins, surface mount
+plcc smt
+0
+20
+20
+Package_LCC
+PLCC-20_SMD-Socket
+PLCC, 20 pins, surface mount
+plcc smt
+0
+20
+20
+Package_LCC
+PLCC-20_THT-Socket
+PLCC, 20 pins, through hole
+plcc leaded
+0
+20
+20
+Package_LCC
+PLCC-28
+PLCC, 28 pins, surface mount
+plcc smt
+0
+28
+28
+Package_LCC
+PLCC-28_SMD-Socket
+PLCC, 28 pins, surface mount
+plcc smt
+0
+28
+28
+Package_LCC
+PLCC-28_THT-Socket
+PLCC, 28 pins, through hole
+plcc leaded
+0
+28
+28
+Package_LCC
+PLCC-32_11.4x14.0mm_P1.27mm
+PLCC, 32 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc0015.pdf), generated with kicad-footprint-generator ipc_plcc_jLead_generator.py
+PLCC LCC
+0
+32
+32
+Package_LCC
+PLCC-44
+PLCC, 44 pins, surface mount
+plcc smt
+0
+44
+44
+Package_LCC
+PLCC-44_16.6x16.6mm_P1.27mm
+PLCC, 44 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_plcc_jLead_generator.py
+PLCC LCC
+0
+44
+44
+Package_LCC
+PLCC-44_SMD-Socket
+PLCC, 44 pins, surface mount
+plcc smt
+0
+44
+44
+Package_LCC
+PLCC-44_THT-Socket
+PLCC, 44 pins, through hole
+plcc leaded
+0
+44
+44
+Package_LCC
+PLCC-52
+PLCC, 52 pins, surface mount
+plcc smt
+0
+52
+52
+Package_LCC
+PLCC-52_SMD-Socket
+PLCC, 52 pins, surface mount
+plcc smt
+0
+52
+52
+Package_LCC
+PLCC-52_THT-Socket
+PLCC, 52 pins, through hole
+plcc leaded
+0
+52
+52
+Package_LCC
+PLCC-68
+PLCC, 68 pins, surface mount
+plcc smt
+0
+68
+68
+Package_LCC
+PLCC-68_24.2x24.2mm_P1.27mm
+PLCC, 68 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_plcc_jLead_generator.py
+PLCC LCC
+0
+68
+68
+Package_LCC
+PLCC-68_SMD-Socket
+PLCC, 68 pins, surface mount
+plcc smt
+0
+68
+68
+Package_LCC
+PLCC-68_THT-Socket
+PLCC, 68 pins, through hole
+plcc leaded
+0
+68
+68
+Package_LCC
+PLCC-84
+PLCC, 84 pins, surface mount
+plcc smt
+0
+84
+84
+Package_LCC
+PLCC-84_29.3x29.3mm_P1.27mm
+PLCC, 84 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_plcc_jLead_generator.py
+PLCC LCC
+0
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+84
+Package_LCC
+PLCC-84_SMD-Socket
+PLCC, 84 pins, surface mount
+plcc smt
+0
+84
+84
+Package_LCC
+PLCC-84_THT-Socket
+PLCC, 84 pins, through hole
+plcc leaded
+0
+84
+84
+Package_LGA
+AMS_LGA-10-1EP_2.7x4mm_P0.6mm
+LGA-10, http://ams.com/eng/content/download/951091/2269479/471718
+lga land grid array
+0
+13
+11
+Package_LGA
+AMS_LGA-20_4.7x4.5mm_P0.65mm
+http://ams.com/eng/content/download/1008631/2361759/498838
+AMS LGA
+0
+20
+20
+Package_LGA
+Bosch_LGA-8_2.5x2.5mm_P0.65mm_ClockwisePinNumbering
+LGA-8
+lga land grid array
+0
+8
+8
+Package_LGA
+Bosch_LGA-8_2x2.5mm_P0.65mm_ClockwisePinNumbering
+LGA-8, https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMP280-DS001-18.pdf
+lga land grid array
+0
+8
+8
+Package_LGA
+Bosch_LGA-8_3x3mm_P0.8mm_ClockwisePinNumbering
+Bosch  LGA, 8 Pin (https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BME680-DS001-00.pdf#page=44), generated with kicad-footprint-generator ipc_noLead_generator.py
+Bosch LGA NoLead
+0
+8
+8
+Package_LGA
+Bosch_LGA-14_3x2.5mm_P0.5mm
+LGA-14 Bosch https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMI160-DS000-07.pdf
+lga land grid array
+0
+14
+14
+Package_LGA
+LGA-8_3x5mm_P1.25mm
+LGA-8
+lga land grid array
+0
+8
+8
+Package_LGA
+LGA-12_2x2mm_P0.5mm
+LGA12
+lga land grid array
+0
+12
+12
+Package_LGA
+LGA-14_2x2mm_P0.35mm_LayoutBorder3x4y
+LGA, 14 Pin (http://www.st.com/resource/en/datasheet/lis2dh.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LGA NoLead
+0
+14
+14
+Package_LGA
+LGA-14_3x2.5mm_P0.5mm_LayoutBorder3x4y
+LGA, 14 Pin (http://www.st.com/resource/en/datasheet/lsm6ds3.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LGA NoLead
+0
+14
+14
+Package_LGA
+LGA-14_3x5mm_P0.8mm_LayoutBorder1x6y
+LGA, 14 Pin (http://www.st.com/resource/en/datasheet/lsm303dlhc.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LGA NoLead
+0
+14
+14
+Package_LGA
+LGA-16_3x3mm_P0.5mm
+http://www.memsic.com/userfiles/files/DataSheets/Magnetic-Sensors-Datasheets/MMC5883MA-RevC.pdf
+lga land grid array
+0
+16
+16
+Package_LGA
+LGA-16_3x3mm_P0.5mm_LayoutBorder3x5y
+LGA, 16 Pin (http://www.st.com/resource/en/datasheet/lis331hh.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LGA NoLead
+0
+16
+16
+Package_LGA
+LGA-16_4x4mm_P0.65mm_LayoutBorder4x4y
+LGA, 16 Pin (http://www.st.com/resource/en/datasheet/l3gd20.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+LGA NoLead
+0
+16
+16
+Package_LGA
+LGA-24L_3x3.5mm_P0.43mm
+LGA 24L 3x3.5mm Pitch 0.43mm
+LGA 24L 3x3.5mm Pitch 0.43mm
+0
+24
+24
+Package_LGA
+LGA-28_5.2x3.8mm_P0.5mm
+LGA 28 5.2x3.8mm Pitch 0.5mm
+LGA 28 5.2x3.8mm Pitch 0.5mm
+0
+28
+28
+Package_LGA
+Linear_LGA-133_15.0x15.0_Layout12x12_P1.27mm
+Analog Devices (Linear Tech), 133-pin LGA uModule, 15.0x15.0x4.32mm, https://www.analog.com/media/en/technical-documentation/data-sheets/4637fc.pdf
+133 pin lga
+0
+133
+133
+Package_LGA
+NXP_LGA-8_3x5mm_P1.25mm_H1.1mm
+NXP  LGA, 8 Pin (https://www.nxp.com/docs/en/data-sheet/MPL3115A2.pdf#page=42), generated with kicad-footprint-generator ipc_noLead_generator.py
+NXP LGA NoLead
+0
+8
+8
+Package_LGA
+NXP_LGA-8_3x5mm_P1.25mm_H1.2mm
+NXP  LGA, 8 Pin (https://www.nxp.com/docs/en/data-sheet/MPL115A1.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+NXP LGA NoLead
+0
+8
+8
+Package_LGA
+ST_HLGA-10_2.5x2.5mm_P0.6mm_LayoutBorder3x2y
+ST  HLGA, 10 Pin (https://www.st.com/resource/en/datasheet/lps25hb.pdf#page=46), generated with kicad-footprint-generator ipc_noLead_generator.py
+ST HLGA NoLead
+0
+10
+10
+Package_LGA
+Texas_SIL0008D_MicroSiP-8-1EP_2.8x3mm_P0.65mm_EP1.1x1.9mm
+Texas SIL0008D MicroSiP, 8 Pin (http://www.ti.com/lit/ds/symlink/tps82130.pdf#page=19), generated with kicad-footprint-generator ipc_noLead_generator.py
+Texas MicroSiP NoLead
+0
+12
+9
+Package_LGA
+Texas_SIL0008D_MicroSiP-8-1EP_2.8x3mm_P0.65mm_EP1.1x1.9mm_ThermalVias
+Texas SIL0008D MicroSiP, 8 Pin (http://www.ti.com/lit/ds/symlink/tps82130.pdf#page=19), generated with kicad-footprint-generator ipc_noLead_generator.py
+Texas MicroSiP NoLead
+0
+16
+9
+Package_LGA
+Texas_SIL0010A_MicroSiP-10-1EP_3.8x3mm_P0.6mm_EP0.7x2.9mm_ThermalVias
+Texas SIL0010A MicroSiP, 10 Pin (http://www.ti.com/lit/ml/mpds579b/mpds579b.pdf), generated with kicad-footprint-generator ipc_lga_layoutBorder_generator.py
+Texas MicroSiP LGA
+0
+18
+11
+Package_QFP
+EQFP-144-1EP_20x20mm_P0.5mm_EP4x4mm
+EQFP, 144 Pin (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00482-02.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+EQFP QFP
+0
+154
+145
+Package_QFP
+EQFP-144-1EP_20x20mm_P0.5mm_EP4x4mm_ThermalVias
+EQFP, 144 Pin (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00482-02.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+EQFP QFP
+0
+171
+145
+Package_QFP
+EQFP-144-1EP_20x20mm_P0.5mm_EP5x5mm
+EQFP, 144 Pin (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00476-02.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+EQFP QFP
+0
+161
+145
+Package_QFP
+EQFP-144-1EP_20x20mm_P0.5mm_EP5x5mm_ThermalVias
+EQFP, 144 Pin (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00476-02.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+EQFP QFP
+0
+187
+145
+Package_QFP
+EQFP-144-1EP_20x20mm_P0.5mm_EP6.61x5.615mm
+EQFP, 144 Pin (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00485-02.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+EQFP QFP
+0
+165
+145
+Package_QFP
+EQFP-144-1EP_20x20mm_P0.5mm_EP6.61x5.615mm_ThermalVias
+EQFP, 144 Pin (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00485-02.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+EQFP QFP
+0
+196
+145
+Package_QFP
+EQFP-144-1EP_20x20mm_P0.5mm_EP7.2x6.35mm
+EQFP, 144 Pin (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00487-01.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+EQFP QFP
+0
+175
+145
+Package_QFP
+EQFP-144-1EP_20x20mm_P0.5mm_EP7.2x6.35mm_ThermalVias
+EQFP, 144 Pin (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00487-01.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+EQFP QFP
+0
+218
+145
+Package_QFP
+EQFP-144-1EP_20x20mm_P0.5mm_EP8.93x8.7mm
+EQFP, 144 Pin (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00479-02.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+EQFP QFP
+0
+194
+145
+Package_QFP
+EQFP-144-1EP_20x20mm_P0.5mm_EP8.93x8.7mm_ThermalVias
+EQFP, 144 Pin (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00479-02.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+EQFP QFP
+0
+259
+145
+Package_QFP
+HTQFP-64-1EP_10x10mm_P0.5mm_EP8x8mm
+64-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1 mm Body, 2.00 mm Footprint [HTQFP] thermal pad
+HTQFP-64 Pitch 0.5 
+0
+69
+65
+Package_QFP
+HTQFP-64-1EP_10x10mm_P0.5mm_EP8x8mm_Mask4.4x4.4mm_ThermalVias
+64-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1 mm Body, 2.00 mm Footprint [HTQFP] thermal pad
+HTQFP-64 Pitch 0.5 
+0
+135
+65
+Package_QFP
+LQFP-32_5x5mm_P0.5mm
+LQFP, 32 Pin (https://www.nxp.com/docs/en/package-information/SOT401-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+32
+32
+Package_QFP
+LQFP-32_7x7mm_P0.8mm
+LQFP, 32 Pin (https://www.nxp.com/docs/en/package-information/SOT358-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+32
+32
+Package_QFP
+LQFP-36_7x7mm_P0.65mm
+LQFP, 36 Pin (https://www.onsemi.com/pub/Collateral/561AV.PDF), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+36
+36
+Package_QFP
+LQFP-44_10x10mm_P0.8mm
+LQFP, 44 Pin (https://www.nxp.com/files-static/shared/doc/package_info/98ASS23225W.pdf?&fsrch=1), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+44
+44
+Package_QFP
+LQFP-48-1EP_7x7mm_P0.5mm_EP3.6x3.6mm
+LQFP, 48 Pin (http://www.analog.com/media/en/technical-documentation/data-sheets/LTC7810.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+58
+49
+Package_QFP
+LQFP-48-1EP_7x7mm_P0.5mm_EP3.6x3.6mm_ThermalVias
+LQFP, 48 Pin (http://www.analog.com/media/en/technical-documentation/data-sheets/LTC7810.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+75
+49
+Package_QFP
+LQFP-48_7x7mm_P0.5mm
+LQFP, 48 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ltc2358-16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+48
+48
+Package_QFP
+LQFP-52-1EP_10x10mm_P0.65mm_EP4.8x4.8mm
+LQFP, 52 Pin (https://www.onsemi.com/pub/Collateral/848H-01.PDF), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+62
+53
+Package_QFP
+LQFP-52-1EP_10x10mm_P0.65mm_EP4.8x4.8mm_ThermalVias
+LQFP, 52 Pin (https://www.onsemi.com/pub/Collateral/848H-01.PDF), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+95
+53
+Package_QFP
+LQFP-52_10x10mm_P0.65mm
+LQFP, 52 Pin (https://www.nxp.com/docs/en/package-information/98ARL10526D.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+52
+52
+Package_QFP
+LQFP-52_14x14mm_P1mm
+LQFP, 52 Pin (http://www.holtek.com/documents/10179/116711/HT1632Cv170.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+52
+52
+Package_QFP
+LQFP-64-1EP_10x10mm_P0.5mm_EP5x5mm
+LQFP, 64 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/adv7611.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+90
+65
+Package_QFP
+LQFP-64-1EP_10x10mm_P0.5mm_EP5x5mm_ThermalVias
+LQFP, 64 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/adv7611.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+107
+65
+Package_QFP
+LQFP-64-1EP_10x10mm_P0.5mm_EP6.5x6.5mm
+LQFP, 64 Pin (https://www.nxp.com/files-static/shared/doc/package_info/98ARH98426A.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+90
+65
+Package_QFP
+LQFP-64-1EP_10x10mm_P0.5mm_EP6.5x6.5mm_ThermalVias
+LQFP, 64 Pin (https://www.nxp.com/files-static/shared/doc/package_info/98ARH98426A.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+127
+65
+Package_QFP
+LQFP-64_7x7mm_P0.4mm
+LQFP, 64 Pin (https://www.nxp.com/docs/en/package-information/SOT414-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+64
+64
+Package_QFP
+LQFP-64_10x10mm_P0.5mm
+LQFP, 64 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606_7606-6_7606-4.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+64
+64
+Package_QFP
+LQFP-64_14x14mm_P0.8mm
+LQFP, 64 Pin (https://www.nxp.com/docs/en/package-information/SOT791-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+64
+64
+Package_QFP
+LQFP-80_10x10mm_P0.4mm
+LQFP, 80 Pin (https://www.renesas.com/eu/en/package-image/pdf/outdrawing/q80.10x10.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+80
+80
+Package_QFP
+LQFP-80_12x12mm_P0.5mm
+LQFP, 80 Pin (https://www.nxp.com/docs/en/package-information/SOT315-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+80
+80
+Package_QFP
+LQFP-80_14x14mm_P0.65mm
+LQFP, 80 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/AD9852.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+80
+80
+Package_QFP
+LQFP-100_14x14mm_P0.5mm
+LQFP, 100 Pin (https://www.nxp.com/docs/en/package-information/SOT407-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+100
+100
+Package_QFP
+LQFP-128_14x14mm_P0.4mm
+LQFP, 128 Pin (https://www.renesas.com/eu/en/package-image/pdf/outdrawing/q128.14x14.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+128
+128
+Package_QFP
+LQFP-128_14x20mm_P0.5mm
+LQFP, 128 Pin (https://www.nxp.com/docs/en/package-information/SOT425-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+128
+128
+Package_QFP
+LQFP-144_20x20mm_P0.5mm
+LQFP, 144 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=425), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+144
+144
+Package_QFP
+LQFP-160_24x24mm_P0.5mm
+LQFP, 160 Pin (https://www.nxp.com/docs/en/package-information/SOT435-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+160
+160
+Package_QFP
+LQFP-176_20x20mm_P0.4mm
+LQFP, 176 Pin (https://www.onsemi.com/pub/Collateral/566DB.PDF), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+176
+176
+Package_QFP
+LQFP-176_24x24mm_P0.5mm
+LQFP, 176 Pin (https://www.st.com/resource/en/datasheet/stm32f207vg.pdf#page=163), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+176
+176
+Package_QFP
+LQFP-208_28x28mm_P0.5mm
+LQFP, 208 Pin (https://www.nxp.com/docs/en/package-information/SOT459-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+208
+208
+Package_QFP
+LQFP-216_24x24mm_P0.4mm
+LQFP, 216 Pin (https://www.onsemi.com/pub/Collateral/561BE.PDF), generated with kicad-footprint-generator ipc_gullwing_generator.py
+LQFP QFP
+0
+216
+216
+Package_QFP
+MQFP-44_10x10mm_P0.8mm
+MQFP, 44 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ad7722.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MQFP QFP
+0
+44
+44
+Package_QFP
+PQFP-44_10x10mm_P0.8mm
+44-Lead Plastic Quad Flatpack - 10x10x2.5mm Body (http://www.onsemi.com/pub/Collateral/122BK.PDF)
+PQFP 0.8
+0
+44
+44
+Package_QFP
+PQFP-80_14x20mm_P0.8mm
+PQFP80 14x20 / QIP80E CASE 122BS (see ON Semiconductor 122BS.PDF)
+QFP 0.8
+0
+80
+80
+Package_QFP
+PQFP-100_14x20mm_P0.65mm
+PQFP, 100 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py
+PQFP QFP
+0
+100
+100
+Package_QFP
+PQFP-112_20x20mm_P0.65mm
+PQFP, 112 pins, 20mm sq body, 0.65mm pitch (http://cache.freescale.com/files/shared/doc/package_info/98ASS23330W.pdf, http://www.nxp.com/docs/en/application-note/AN4388.pdf)
+PQFP 112
+0
+112
+112
+Package_QFP
+PQFP-132_24x24mm_P0.635mm
+PQFP, 132 pins, 24mm sq body, 0.635mm pitch (https://www.intel.com/content/dam/www/public/us/en/documents/packaging-databooks/packaging-chapter-02-databook.pdf, http://www.nxp.com/docs/en/application-note/AN4388.pdf)
+PQFP 132
+0
+132
+132
+Package_QFP
+PQFP-132_24x24mm_P0.635mm_i386
+PQFP, 132 pins, 24mm sq body, 0.635mm pitch, Intel 386EX (https://www.intel.com/content/dam/www/public/us/en/documents/packaging-databooks/packaging-chapter-02-databook.pdf, http://www.nxp.com/docs/en/application-note/AN4388.pdf)
+PQFP 132 Intel 386EX
+0
+132
+132
+Package_QFP
+PQFP-144_28x28mm_P0.65mm
+PQFP, 144 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py
+PQFP QFP
+0
+144
+144
+Package_QFP
+PQFP-160_28x28mm_P0.65mm
+PQFP, 160 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py
+PQFP QFP
+0
+160
+160
+Package_QFP
+PQFP-208_28x28mm_P0.5mm
+PQFP, 208 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py
+PQFP QFP
+0
+208
+208
+Package_QFP
+PQFP-240_32.1x32.1mm_P0.5mm
+PQFP, 240 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py
+PQFP QFP
+0
+240
+240
+Package_QFP
+PQFP-256_28x28mm_P0.4mm
+PQFP256 28x28 / QFP256J CASE 122BX (see ON Semiconductor 122BX.PDF)
+QFP 0.4
+0
+256
+256
+Package_QFP
+TQFP-32_7x7mm_P0.8mm
+32-Lead Plastic Thin Quad Flatpack (PT) - 7x7x1.0 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049BS.pdf)
+QFP 0.8
+0
+32
+32
+Package_QFP
+TQFP-44-1EP_10x10mm_P0.8mm_EP4.5x4.5mm
+44-Lead Plastic Thin Quad Flatpack (MW) - 10x10x1.0 mm Body [TQFP] With 4.5x4.5 mm Exposed Pad (see Microchip Packaging Specification 00000049BS.pdf)
+QFP 0.8
+0
+54
+45
+Package_QFP
+TQFP-44_10x10mm_P0.8mm
+44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] (see Microchip Packaging Specification 00000049BS.pdf)
+QFP 0.8
+0
+44
+44
+Package_QFP
+TQFP-48-1EP_7x7mm_P0.5mm_EP3.5x3.5mm
+48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP] With Exposed Pad (see Microchip Packaging Specification 00000049BS.pdf)
+QFP 0.5
+0
+53
+49
+Package_QFP
+TQFP-48-1EP_7x7mm_P0.5mm_EP5x5mm
+TQFP, 48 Pin (https://www.trinamic.com/fileadmin/assets/Products/ICs_Documents/TMC2100_datasheet_Rev1.08.pdf (page 45)), generated with kicad-footprint-generator ipc_gullwing_generator.py
+TQFP QFP
+0
+65
+49
+Package_QFP
+TQFP-48-1EP_7x7mm_P0.5mm_EP5x5mm_ThermalVias
+TQFP, 48 Pin (https://www.trinamic.com/fileadmin/assets/Products/ICs_Documents/TMC2100_datasheet_Rev1.08.pdf (page 45)), generated with kicad-footprint-generator ipc_gullwing_generator.py
+TQFP QFP
+0
+91
+49
+Package_QFP
+TQFP-48_7x7mm_P0.5mm
+48 LEAD TQFP 7x7mm (see MICREL TQFP7x7-48LD-PL-1.pdf)
+QFP 0.5
+0
+48
+48
+Package_QFP
+TQFP-52-1EP_10x10mm_P0.65mm_EP6.5x6.5mm
+TQFP, 52 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/tqfp_edsv/sv_52_1.pdf), generated with kicad-footprint-generator ipc_qfp_generator.py
+TQFP QFP
+0
+78
+53
+Package_QFP
+TQFP-52-1EP_10x10mm_P0.65mm_EP6.5x6.5mm_ThermalVias
+TQFP, 52 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/tqfp_edsv/sv_52_1.pdf), generated with kicad-footprint-generator ipc_qfp_generator.py
+TQFP QFP
+0
+79
+53
+Package_QFP
+TQFP-64-1EP_10x10mm_P0.5mm_EP8x8mm
+64-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1 mm Body, 2.00 mm Footprint [TQFP] thermal pad
+QFP 0.5 
+0
+90
+65
+Package_QFP
+TQFP-64_7x7mm_P0.4mm
+TQFP64 7x7, 0.4P CASE 932BH (see ON Semiconductor 932BH.PDF)
+QFP 0.4
+0
+64
+64
+Package_QFP
+TQFP-64_10x10mm_P0.5mm
+TQFP, 64 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py
+TQFP QFP
+0
+64
+64
+Package_QFP
+TQFP-64_14x14mm_P0.8mm
+64-Lead Plastic Thin Quad Flatpack (PF) - 14x14x1 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049BS.pdf)
+QFP 0.8
+0
+64
+64
+Package_QFP
+TQFP-80-1EP_14x14mm_P0.65mm_EP9.5x9.5mm
+80-Lead Plastic Thin Quad Flatpack (PF) - 14x14mm body, 9.5mm sq thermal pad (http://www.analog.com/media/en/technical-documentation/data-sheets/AD9852.pdf)
+QFP 0.65
+0
+85
+81
+Package_QFP
+TQFP-80_12x12mm_P0.5mm
+80-Lead Plastic Thin Quad Flatpack (PT) - 12x12x1 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049BS.pdf)
+QFP 0.5
+0
+80
+80
+Package_QFP
+TQFP-80_14x14mm_P0.65mm
+80-Lead Plastic Thin Quad Flatpack (PF) - 14x14x1 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049BS.pdf)
+QFP 0.65
+0
+80
+80
+Package_QFP
+TQFP-100-1EP_14x14mm_P0.5mm_EP5x5mm
+TQFP, 100 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/tqfp_edsv/sv_100_4.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+TQFP QFP
+0
+117
+101
+Package_QFP
+TQFP-100-1EP_14x14mm_P0.5mm_EP5x5mm_ThermalVias
+TQFP, 100 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/tqfp_edsv/sv_100_4.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+TQFP QFP
+0
+143
+101
+Package_QFP
+TQFP-100_12x12mm_P0.4mm
+100-Lead Plastic Thin Quad Flatpack (PT) - 12x12x1 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049BS.pdf)
+QFP 0.4
+0
+100
+100
+Package_QFP
+TQFP-100_14x14mm_P0.5mm
+TQFP, 100 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py
+TQFP QFP
+0
+100
+100
+Package_QFP
+TQFP-120_14x14mm_P0.4mm
+TQFP120 14x14 / TQFP120 CASE 932AZ (see ON Semiconductor 932AZ.PDF)
+QFP 0.4
+0
+120
+120
+Package_QFP
+TQFP-128_14x14mm_P0.4mm
+TQFP128 14x14 / TQFP128 CASE 932BB (see ON Semiconductor 932BB.PDF)
+QFP 0.4
+0
+128
+128
+Package_QFP
+TQFP-144_16x16mm_P0.4mm
+144-Lead Plastic Thin Quad Flatpack (PH) - 16x16x1 mm Body, 2.00 mm Footprint [TQFP] (see Microchip Packaging Specification 00000049BS.pdf)
+QFP 0.4
+0
+144
+144
+Package_QFP
+TQFP-144_20x20mm_P0.5mm
+TQFP, 144 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py
+TQFP QFP
+0
+144
+144
+Package_QFP
+TQFP-176_24x24mm_P0.5mm
+TQFP, 176 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py
+TQFP QFP
+0
+176
+176
+Package_QFP
+VQFP-80_14x14mm_P0.65mm
+VQFP, 80 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py
+VQFP QFP
+0
+80
+80
+Package_QFP
+VQFP-100_14x14mm_P0.5mm
+VQFP, 100 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py
+VQFP QFP
+0
+100
+100
+Package_QFP
+VQFP-128_14x14mm_P0.4mm
+VQFP, 128 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py
+VQFP QFP
+0
+128
+128
+Package_QFP
+VQFP-176_20x20mm_P0.4mm
+VQFP, 176 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py
+VQFP QFP
+0
+176
+176
+Package_SIP
+PowerIntegrations_eSIP-7C
+eSIP-7C Vertical Flat Package with Heatsink Tab, https://ac-dc.power.com/sites/default/files/product-docs/topswitch-jx_family_datasheet.pdf
+Power Integrations E Package
+0
+6
+6
+Package_SIP
+PowerIntegrations_eSIP-7F
+eSIP-7F Flat Package with Heatsink Tab https://ac-dc.power.com/sites/default/files/product-docs/linkswitch-ph_family_datasheet.pdf
+Power Integrations L Package
+0
+6
+6
+Package_SIP
+SIP-8_19x3mm_P2.54mm
+SIP 8-pin (http://www.njr.com/semicon/PDF/package/SIP8_E.pdf)
+SIP8
+0
+8
+8
+Package_SIP
+SIP-9_21.54x3mm_P2.54mm
+SIP 9-pin ()
+SIP8
+0
+9
+9
+Package_SIP
+SIP3_11.6x8.5mm
+RECOM,R78EXX,https://www.recom-power.com/pdf/Innoline/R-78Exx-0.5.pdf
+SIP3 Regulator Module
+0
+3
+3
+Package_SIP
+SIP4_Sharp-SSR_P7.62mm_Angled
+SIP4 Footprint for SSR made by Sharp
+Solid State relais SSR Sharp
+0
+4
+4
+Package_SIP
+SIP4_Sharp-SSR_P7.62mm_Angled_NoHole
+SIP4 Footprint for SSR made by Sharp
+Solid State relais SSR Sharp
+0
+4
+4
+Package_SIP
+SIP4_Sharp-SSR_P7.62mm_Straight
+SIP4 Footprint for SSR made by Sharp
+Solid State relais SSR Sharp
+0
+4
+4
+Package_SIP
+SIP9_Housing
+SIP9
+SIP9
+0
+9
+9
+Package_SIP
+SIP9_Housing_BigPads
+SIP9, large pads
+SIP9
+0
+9
+9
+Package_SIP
+SLA704XM
+SIP SLA704XM (http://www.sumzi.com/upload/files/2007/07/2007073114282034189.PDF)
+SIP
+0
+18
+18
+Package_SIP
+STK672-040-E
+SIP-22 (http://www.onsemi.com/pub_link/Collateral/EN5227-D.PDF)
+SIP-22
+0
+22
+22
+Package_SIP
+STK672-080-E
+SIP-15 (http://www.onsemi.com/pub_link/Collateral/EN6507-D.PDF)
+SIP-15
+0
+15
+15
+Package_SIP
+Sanyo_STK4xx-15_59.2x8.0mm_P2.54mm
+Sanyo SIP-15, 59.2mm x 8.0mm bosy size, STK-433E STK-435E STK-436E (http://datasheet.octopart.com/STK430-Sanyo-datasheet-107060.pdf)
+Sanyo SIP-15
+0
+15
+15
+Package_SIP
+Sanyo_STK4xx-15_78.0x8.0mm_P2.54mm
+Sanyo SIP-15, 78.0mm x 8.0mm bosy size, STK-437E STK-439E STK-441E STK-443E (http://datasheet.octopart.com/STK430-Sanyo-datasheet-107060.pdf)
+Sanyo SIP-15
+0
+15
+15
+Package_SO
+Diodes_PSOP-8
+8-Lead Plastic PSOP, Exposed Die Pad (see https://www.diodes.com/assets/Datasheets/AP2204.pdf)
+SSOP 0.50 exposed pad
+0
+12
+9
+Package_SO
+Diodes_SO-8EP
+8-Lead Plastic SO, Exposed Die Pad (see https://www.diodes.com/assets/Package-Files/SO-8EP.pdf)
+SO exposed pad
+0
+9
+9
+Package_SO
+ETSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3x4.2mm
+20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body with Exposed Pad [eTSSOP] (see Microchip Packaging Specification 00000049BS.pdf)
+SSOP 0.65
+0
+27
+21
+Package_SO
+HSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.1mm
+HSOP, 8 Pin (https://www.st.com/resource/en/datasheet/l5973d.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+HSOP SO
+0
+13
+9
+Package_SO
+HSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.1mm_ThermalVias
+HSOP, 8 Pin (https://www.st.com/resource/en/datasheet/l5973d.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+HSOP SO
+0
+20
+9
+Package_SO
+HSOP-20-1EP_11.0x15.9mm_P1.27mm_SlugDown
+HSOP 11.0x15.9mm Pitch 1.27mm Slug Down (PowerSO-20) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/tda7266d.pdf, www.st.com/resource/en/application_note/cd00003801.pdf)
+HSOP 11.0 x 15.9mm Pitch 1.27mm
+0
+23
+21
+Package_SO
+HSOP-20-1EP_11.0x15.9mm_P1.27mm_SlugDown_ThermalVias
+HSOP 11.0x15.9mm Pitch 1.27mm Slug Down Thermal Vias (PowerSO-20) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/tda7266d.pdf, www.st.com/resource/en/application_note/cd00003801.pdf)
+HSOP 11.0 x 15.9mm Pitch 1.27mm
+0
+45
+21
+Package_SO
+HSOP-20-1EP_11.0x15.9mm_P1.27mm_SlugUp
+HSOP 11.0x15.9mm Pitch 1.27mm Slug Up (PowerSO-20) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/tda7266d.pdf, www.st.com/resource/en/application_note/cd00003801.pdf)
+HSOP 11.0 x 15.9mm Pitch 1.27mm
+0
+20
+20
+Package_SO
+HSOP-36-1EP_11.0x15.9mm_P0.65mm_SlugDown
+HSOP 11.0x15.9mm Pitch 0.65mm Slug Down (PowerSO-36) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/vn808cm-32-e.pdf, http://www.st.com/resource/en/application_note/cd00003801.pdf)
+HSOP 11.0 x 15.9mm Pitch 0.65mm
+0
+39
+37
+Package_SO
+HSOP-36-1EP_11.0x15.9mm_P0.65mm_SlugDown_ThermalVias
+HSOP 11.0x15.9mm Pitch 0.65mm Slug Down Thermal Vias (PowerSO-36) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/vn808cm-32-e.pdf, http://www.st.com/resource/en/application_note/cd00003801.pdf)
+HSOP 11.0 x 15.9mm Pitch 0.65mm
+0
+61
+37
+Package_SO
+HSOP-36-1EP_11.0x15.9mm_P0.65mm_SlugUp
+HSOP 11.0x15.9mm Pitch 0.65mm Slug Up (PowerSO-36) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/vn808cm-32-e.pdf, http://www.st.com/resource/en/application_note/cd00003801.pdf)
+HSOP 11.0 x 15.9mm Pitch 0.65mm
+0
+36
+36
+Package_SO
+HTSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.4x3.2mm
+HTSOP, 8 Pin (https://media.digikey.com/pdf/Data%20Sheets/Rohm%20PDFs/BD9G341EFJ.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+HTSOP SO
+0
+13
+9
+Package_SO
+HTSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.4x3.2mm_ThermalVias
+HTSOP, 8 Pin (https://media.digikey.com/pdf/Data%20Sheets/Rohm%20PDFs/BD9G341EFJ.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+HTSOP SO
+0
+20
+9
+Package_SO
+HTSSOP-16-1EP_4.4x5mm_P0.65mm_EP3.4x5mm
+16-Lead Plastic HTSSOP (4.4x5x1.2mm); Thermal pad; (http://www.ti.com/lit/ds/symlink/drv8833.pdf)
+SSOP 0.65
+0
+29
+17
+Package_SO
+HTSSOP-16-1EP_4.4x5mm_P0.65mm_EP3.4x5mm_Mask2.46x2.31mm_ThermalVias
+16-Lead Plastic HTSSOP (4.4x5x1.2mm); Thermal pad with vias; (http://www.ti.com/lit/ds/symlink/drv8833.pdf)
+SSOP 0.65
+0
+27
+17
+Package_SO
+HTSSOP-16-1EP_4.4x5mm_P0.65mm_EP3.4x5mm_Mask3x3mm_ThermalVias
+16-Lead Plastic HTSSOP (4.4x5x1.2mm); Thermal pad with vias; (http://www.ti.com/lit/ds/symlink/drv8800.pdf)
+SSOP 0.65
+0
+46
+17
+Package_SO
+HTSSOP-16-1EP_4.4x5mm_P0.65mm_EP3x3mm
+HTSSOP, 16 Pin (https://www.st.com/resource/en/datasheet/stp08cp05.pdf#page=20), generated with kicad-footprint-generator ipc_gullwing_generator.py
+HTSSOP SO
+0
+21
+17
+Package_SO
+HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm
+20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [HTSSOP], with thermal pad with vias
+HTSSOP 0.65
+0
+29
+21
+Package_SO
+HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm_Mask2.4x3.7mm
+HTSSOP, 20 Pin (http://www.ti.com/lit/ds/symlink/bq24006.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+HTSSOP SO
+0
+24
+21
+Package_SO
+HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm_Mask2.75x3.43mm
+HTSSOP, 20 Pin (http://www.ti.com/lit/ds/symlink/tlc5971.pdf#page=37&zoom=160,-90,3), generated with kicad-footprint-generator ipc_gullwing_generator.py
+HTSSOP SO
+0
+26
+21
+Package_SO
+HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm_Mask2.75x3.43mm_ThermalVias
+HTSSOP, 20 Pin (http://www.ti.com/lit/ds/symlink/tlc5971.pdf#page=37&zoom=160,-90,3), generated with kicad-footprint-generator ipc_gullwing_generator.py
+HTSSOP SO
+0
+42
+21
+Package_SO
+HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm_Mask2.75x3.43mm_ThermalVias_HandSolder
+HTSSOP, 20 Pin (http://www.ti.com/lit/ds/symlink/tlc5971.pdf#page=37&zoom=160,-90,3), generated with kicad-footprint-generator ipc_gullwing_generator.py
+HTSSOP SO
+0
+42
+21
+Package_SO
+HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm_ThermalVias
+20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [HTSSOP], with thermal pad with vias
+HTSSOP 0.65
+0
+45
+21
+Package_SO
+HTSSOP-24-1EP_4.4x7.8mm_P0.65mm_EP3.2x5mm
+HTSSOP, 24 Pin (https://www.st.com/resource/en/datasheet/stp16cp05.pdf#page=25), generated with kicad-footprint-generator ipc_gullwing_generator.py
+HTSSOP SO
+0
+31
+25
+Package_SO
+HTSSOP-24-1EP_4.4x7.8mm_P0.65mm_EP3.4x7.8mm_Mask2.4x4.68mm
+HTSSOP, 24 Pin (http://www.ti.com/lit/ds/symlink/tps703.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+HTSSOP SO
+0
+28
+25
+Package_SO
+HTSSOP-24-1EP_4.4x7.8mm_P0.65mm_EP3.4x7.8mm_Mask2.4x4.68mm_ThermalVias
+HTSSOP, 24 Pin (http://www.ti.com/lit/ds/symlink/tps703.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+HTSSOP SO
+0
+47
+25
+Package_SO
+HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x5.4mm
+HTSSOP, 28 Pin (https://pdfserv.maximintegrated.com/package_dwgs/21-0108.PDF), generated with kicad-footprint-generator ipc_gullwing_generator.py
+HTSSOP SO
+0
+30
+29
+Package_SO
+HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x5.4mm_ThermalVias
+HTSSOP, 28 Pin (https://pdfserv.maximintegrated.com/package_dwgs/21-0108.PDF), generated with kicad-footprint-generator ipc_gullwing_generator.py
+HTSSOP SO
+0
+41
+29
+Package_SO
+HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP3.4x9.5mm
+HTSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; thermal pad
+TSSOP HTSSOP 0.65 thermal pad
+0
+39
+29
+Package_SO
+HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP3.4x9.5mm_Mask2.4x6.17mm
+HTSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; thermal pad
+TSSOP HTSSOP 0.65 thermal pad
+0
+40
+29
+Package_SO
+HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP3.4x9.5mm_Mask2.4x6.17mm_ThermalVias
+HTSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; thermal pad
+TSSOP HTSSOP 0.65 thermal pad
+0
+55
+29
+Package_SO
+HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP3.4x9.5mm_ThermalVias
+HTSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; thermal pad
+TSSOP HTSSOP 0.65 thermal pad
+0
+58
+29
+Package_SO
+HTSSOP-32-1EP_6.1x11mm_P0.65mm_EP5.2x11mm_Mask4.11x4.36mm
+HTSSOP32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot487-1_po.pdf)
+SSOP 0.65 PowerPAD
+0
+43
+33
+Package_SO
+HTSSOP-32-1EP_6.1x11mm_P0.65mm_EP5.2x11mm_Mask4.11x4.36mm_ThermalVias
+HTSSOP32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot487-1_po.pdf)
+SSOP 0.65 PowerPAD
+0
+83
+33
+Package_SO
+HTSSOP-38-1EP_6.1x12.5mm_P0.65mm_EP5.2x12.5mm_Mask3.39x6.35mm
+HTSSOP, 38 Pin (http://www.ti.com/lit/ds/symlink/tlc5951.pdf#page=47&zoom=140,-67,15), generated with kicad-footprint-generator ipc_gullwing_generator.py
+HTSSOP SO
+0
+46
+39
+Package_SO
+HTSSOP-38-1EP_6.1x12.5mm_P0.65mm_EP5.2x12.5mm_Mask3.39x6.35mm_ThermalVias
+HTSSOP, 38 Pin (http://www.ti.com/lit/ds/symlink/tlc5951.pdf#page=47&zoom=140,-67,15), generated with kicad-footprint-generator ipc_gullwing_generator.py
+HTSSOP SO
+0
+87
+39
+Package_SO
+HTSSOP-56-1EP_6.1x14mm_P0.5mm_EP3.61x6.35mm
+HTSSOP56: plastic thin shrink small outline package http://www.ti.com/lit/ds/symlink/drv8301.pdf
+HTSSOP 0.5
+0
+72
+57
+Package_SO
+Infineon_PG-DSO-8-27_3.9x4.9mm_EP2.65x3mm
+Infineon  PG-DSO, 8 Pin (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-8-27), generated with kicad-footprint-generator ipc_gullwing_generator.py
+Infineon PG-DSO SO
+0
+13
+9
+Package_SO
+Infineon_PG-DSO-8-27_3.9x4.9mm_EP2.65x3mm_ThermalVias
+Infineon  PG-DSO, 8 Pin (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-8-27), generated with kicad-footprint-generator ipc_gullwing_generator.py
+Infineon PG-DSO SO
+0
+23
+9
+Package_SO
+Infineon_PG-DSO-8-43
+Infineon_PG-DSO-8-43
+DSO DSO-8 SOIC SOIC-8
+0
+12
+9
+Package_SO
+Infineon_PG-DSO-12-9
+Infineon PG-DSO 12 pin, exposed pad: 4.5x8.1mm, with thermal vias (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-9/)
+PG-DSO
+0
+23
+13
+Package_SO
+Infineon_PG-DSO-12-9_ThermalVias
+Infineon PG-DSO 12 pin, exposed pad: 4.5x8.1mm, with thermal vias (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-9/)
+PG-DSO
+0
+42
+13
+Package_SO
+Infineon_PG-DSO-12-11
+Infineon PG-DSO 12 pin, exposed pad: 4.5x8.1mm, with thermal vias (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-11/)
+PG-DSO
+0
+23
+13
+Package_SO
+Infineon_PG-DSO-12-11_ThermalVias
+Infineon PG-DSO 12 pin, exposed pad: 4.5x8.1mm, with thermal vias (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-11/)
+PG-DSO
+0
+42
+13
+Package_SO
+Infineon_PG-DSO-20-30
+Infineon SO package 20pin, exposed pad 4.5x7mm (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-20-71/)
+DSO-20
+0
+31
+21
+Package_SO
+Infineon_PG-DSO-20-30_ThermalVias
+Infineon SO package 20pin, exposed pad 4.5x7mm (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-20-71/)
+DSO-20
+0
+45
+21
+Package_SO
+Infineon_PG-DSO-20-32
+Infineon SO package 20pin without exposed pad (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-20-32/)
+DSO-20
+0
+20
+20
+Package_SO
+Infineon_PG-TSDSO-14-22
+Infineon_PG-TSDSO-14-22
+Infineon TSDSO 14-22 
+0
+17
+15
+Package_SO
+Linear_MSOP-12-16-1EP_3x4mm_P0.5mm
+12-Lead Plastic Micro Small Outline Package (MS) [MSOP], variant of MSOP-16 (see http://cds.linear.com/docs/en/datasheet/3630fd.pdf)
+SSOP 0.5
+0
+15
+13
+Package_SO
+Linear_MSOP-12-16_3x4mm_P0.5mm
+12-Lead Plastic Micro Small Outline Package (MS) [MSOP], variant of MSOP-16 (see https://www.analog.com/media/en/technical-documentation/data-sheets/3748fb.pdf)
+SSOP 0.5
+0
+12
+12
+Package_SO
+MFSOP6-4_4.4x3.6mm_P1.27mm
+https://toshiba.semicon-storage.com/ap-en/design-support/package/detail.4pin%20MFSOP6.html
+MFSOP 4 pin SMD
+0
+4
+4
+Package_SO
+MFSOP6-5_4.4x3.6mm_P1.27mm
+https://toshiba.semicon-storage.com/ap-en/design-support/package/detail.5pin%20MFSOP6.html
+MFSOP 4 pin SMD
+0
+5
+5
+Package_SO
+MSOP-8-1EP_3x3mm_P0.65mm_EP1.68x1.88mm
+MS8E Package; 8-Lead Plastic MSOP, Exposed Die Pad (see Linear Technology 05081662_K_MS8E.pdf)
+SSOP 0.65
+0
+13
+9
+Package_SO
+MSOP-8-1EP_3x3mm_P0.65mm_EP1.73x1.85mm
+MSOP, 8 Pin (http://www.ti.com/lit/ds/symlink/lm25085.pdf#page=32), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+13
+9
+Package_SO
+MSOP-8-1EP_3x3mm_P0.65mm_EP1.73x1.85mm_ThermalVias
+MSOP, 8 Pin (http://www.ti.com/lit/ds/symlink/lm25085.pdf#page=32), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+18
+9
+Package_SO
+MSOP-8-1EP_3x3mm_P0.65mm_EP1.95x2.15mm
+MSOP, 8 Pin (http://www.st.com/resource/en/datasheet/pm8834.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+13
+9
+Package_SO
+MSOP-8-1EP_3x3mm_P0.65mm_EP1.95x2.15mm_ThermalVias
+MSOP, 8 Pin (http://www.st.com/resource/en/datasheet/pm8834.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+18
+9
+Package_SO
+MSOP-8-1EP_3x3mm_P0.65mm_EP2.5x3mm_Mask1.73x2.36mm
+MSOP, 8 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/mic5355_6.pdf#page=15), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+14
+9
+Package_SO
+MSOP-8-1EP_3x3mm_P0.65mm_EP2.5x3mm_Mask1.73x2.36mm_ThermalVias
+MSOP, 8 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/mic5355_6.pdf#page=15), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+19
+9
+Package_SO
+MSOP-8_3x3mm_P0.65mm
+MSOP, 8 Pin (https://www.jedec.org/system/files/docs/mo-187F.pdf variant AA), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+8
+8
+Package_SO
+MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm
+MSOP, 10 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3805fg.pdf#page=18), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+15
+11
+Package_SO
+MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm_ThermalVias
+MSOP, 10 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3805fg.pdf#page=18), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+20
+11
+Package_SO
+MSOP-10-1EP_3x3mm_P0.5mm_EP1.73x1.98mm
+MSOP, 10 Pin (www.allegromicro.com/~/media/Files/Datasheets/A4952-3-Datasheet.ashx?la=en#page=10), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+15
+11
+Package_SO
+MSOP-10-1EP_3x3mm_P0.5mm_EP1.73x1.98mm_ThermalVias
+MSOP, 10 Pin (www.allegromicro.com/~/media/Files/Datasheets/A4952-3-Datasheet.ashx?la=en#page=10), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+20
+11
+Package_SO
+MSOP-10_3x3mm_P0.5mm
+10-Lead Plastic Micro Small Outline Package (MS) [MSOP] (see Microchip Packaging Specification 00000049BS.pdf)
+SSOP 0.5
+0
+10
+10
+Package_SO
+MSOP-12-1EP_3x4mm_P0.65mm_EP1.65x2.85mm
+MSOP, 12 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3652fe.pdf#page=24), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+17
+13
+Package_SO
+MSOP-12-1EP_3x4mm_P0.65mm_EP1.65x2.85mm_ThermalVias
+MSOP, 12 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3652fe.pdf#page=24), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+24
+13
+Package_SO
+MSOP-12-16-1EP_3x4mm_P0.5mm_EP1.65x2.85mm
+10-Lead Plastic Micro Small Outline Package (MS) [MSOP] (see Microchip Packaging Specification 00000049BS.pdf)
+SSOP 0.5
+0
+19
+13
+Package_SO
+MSOP-12-16-1EP_3x4mm_P0.5mm_EP1.65x2.85mm_ThermalVias
+10-Lead Plastic Micro Small Outline Package (MS) [MSOP] (see Microchip Packaging Specification 00000049BS.pdf)
+SSOP 0.5
+0
+25
+13
+Package_SO
+MSOP-12-16_3x4mm_P0.5mm
+10-Lead Plastic Micro Small Outline Package (MS) [MSOP] (see Microchip Packaging Specification 00000049BS.pdf)
+SSOP 0.5
+0
+12
+12
+Package_SO
+MSOP-12_3x4mm_P0.65mm
+MSOP, 12 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/6957fb.pdf#page=36), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+12
+12
+Package_SO
+MSOP-16-1EP_3x4.039mm_P0.5mm_EP1.651x2.845mm
+MSOP, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-msop/05081667_F_MSE16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+21
+17
+Package_SO
+MSOP-16-1EP_3x4.039mm_P0.5mm_EP1.651x2.845mm_ThermalVias
+MSOP, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-msop/05081667_F_MSE16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+28
+17
+Package_SO
+MSOP-16-1EP_3x4mm_P0.5mm_EP1.65x2.85mm
+MSOP, 16 Pin (http://cds.linear.com/docs/en/datasheet/37551fd.pdf#page=23), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+21
+17
+Package_SO
+MSOP-16-1EP_3x4mm_P0.5mm_EP1.65x2.85mm_ThermalVias
+MSOP, 16 Pin (http://cds.linear.com/docs/en/datasheet/37551fd.pdf#page=23), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+28
+17
+Package_SO
+MSOP-16_3x4.039mm_P0.5mm
+MSOP, 16 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-msop/05081669_A_MS16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+16
+16
+Package_SO
+MSOP-16_3x4mm_P0.5mm
+MSOP, 16 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/436412f.pdf#page=22), generated with kicad-footprint-generator ipc_gullwing_generator.py
+MSOP SO
+0
+16
+16
+Package_SO
+OnSemi_Micro8
+ON Semiconductor Micro8 (Case846A-02): https://www.onsemi.com/pub/Collateral/846A-02.PDF
+micro8
+0
+8
+8
+Package_SO
+PSOP-44_16.9x27.17mm_P1.27mm
+PSOP44: plastic thin shrink small outline package; 44 leads; body width 16.90 mm
+PSOP 1.27
+0
+44
+44
+Package_SO
+PowerIntegrations_SO-8
+Power-Integrations variant of 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC], see https://ac-dc.power.com/sites/default/files/product-docs/senzero_family_datasheet.pdf
+SOIC 1.27
+0
+8
+8
+Package_SO
+PowerIntegrations_SO-8B
+Power-Integrations variant of 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC], see https://www.mouser.com/ds/2/328/linkswitch-pl_family_datasheet-12517.pdf
+SOIC 1.27
+0
+7
+7
+Package_SO
+PowerIntegrations_SO-8C
+Power-Integrations variant of 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC], see https://www.mouser.com/ds/2/328/linkswitch-pl_family_datasheet-12517.pdf
+SOIC 1.27
+0
+7
+7
+Package_SO
+PowerIntegrations_eSOP-12B
+eSOP-12B SMT Flat Package with Heatsink Tab, see https://ac-dc.power.com/sites/default/files/product-docs/topswitch-jx_family_datasheet.pdf
+Power Integrations K Package
+0
+12
+12
+Package_SO
+PowerPAK_SO-8_Dual
+PowerPAK SO-8 Dual (https://www.vishay.com/docs/71655/powerpak.pdf, https://www.vishay.com/docs/72600/72600.pdf)
+PowerPAK SO-8 Dual
+0
+10
+6
+Package_SO
+PowerPAK_SO-8_Single
+PowerPAK SO-8 Single (https://www.vishay.com/docs/71655/powerpak.pdf, https://www.vishay.com/docs/72599/72599.pdf)
+PowerPAK SO-8 Single
+0
+9
+5
+Package_SO
+QSOP-16_3.9x4.9mm_P0.635mm
+16-Lead Plastic Shrink Small Outline Narrow Body (QR)-.150" Body [QSOP] (see Microchip Packaging Specification 00000049BS.pdf)
+SSOP 0.635
+0
+16
+16
+Package_SO
+QSOP-20_3.9x8.7mm_P0.635mm
+20-Lead Plastic Shrink Small Outline Narrow Body (http://www.analog.com/media/en/technical-documentation/data-sheets/ADuM7640_7641_7642_7643.pdf)
+QSOP 0.635
+0
+20
+20
+Package_SO
+QSOP-24_3.9x8.7mm_P0.635mm
+24-Lead Plastic Shrink Small Outline Narrow Body (QR)-.150" Body [QSOP] (see Microchip Packaging Specification 00000049CH.pdf)
+QSOP 0.635
+0
+24
+24
+Package_SO
+SC-74-6_1.5x2.9mm_P0.95mm
+SC-74, 6 Pin (https://www.nxp.com/docs/en/package-information/SOT457.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SC-74 SO
+0
+6
+6
+Package_SO
+SO-4_4.4x2.3mm_P1.27mm
+4-Lead Plastic Small Outline (SO), see http://datasheet.octopart.com/OPIA403BTRE-Optek-datasheet-5328560.pdf
+SO SOIC 1.27
+0
+4
+4
+Package_SO
+SO-4_4.4x3.6mm_P2.54mm
+4-Lead Plastic Small Outline (SO), see https://www.elpro.org/de/index.php?controller=attachment&id_attachment=339
+SO SOIC 2.54
+0
+4
+4
+Package_SO
+SO-4_4.4x3.9mm_P2.54mm
+SO, 4 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=10047&prodName=TLP3123), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SO SO
+0
+4
+4
+Package_SO
+SO-4_4.4x4.3mm_P2.54mm
+4-Lead Plastic Small Outline (SO), see https://docs.broadcom.com/docs/AV02-0173EN
+SO SOIC 2.54
+0
+4
+4
+Package_SO
+SO-4_7.6x3.6mm_P2.54mm
+4-Lead Plastic Small Outline (SO) (http://www.everlight.com/file/ProductFile/201407061745083848.pdf)
+SO SOIC 2.54
+0
+4
+4
+Package_SO
+SO-5_4.4x3.6mm_P1.27mm
+5-Lead Plastic Small Outline (SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true
+SO SOIC 1.27
+0
+5
+5
+Package_SO
+SO-6L_10x3.84mm_P1.27mm
+6-pin plasic small outline 7,5mm long https://toshiba.semicon-storage.com/info/docget.jsp?did=53548&prodName=TLP2770
+SO-6L
+0
+6
+6
+Package_SO
+SO-6_4.4x3.6mm_P1.27mm
+6-Lead Plastic Small Outline (SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true
+SO SOIC 1.27
+0
+6
+6
+Package_SO
+SO-8_3.9x4.9mm_P1.27mm
+SO, 8 Pin (https://www.nxp.com/docs/en/data-sheet/PCF8523.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SO SO
+0
+8
+8
+Package_SO
+SO-8_5.3x6.2mm_P1.27mm
+8-Lead Plastic Small Outline, 5.3x6.2mm Body (http://www.ti.com.cn/cn/lit/ds/symlink/tl7705a.pdf)
+SOIC 1.27
+0
+8
+8
+Package_SO
+SO-20_12.8x7.5mm_P1.27mm
+SO-20, 12.8x7.5mm, https://www.nxp.com/docs/en/data-sheet/SA605.pdf
+S0-20 
+0
+20
+20
+Package_SO
+SOIC-4_4.55x2.6mm_P1.27mm
+SOIC, 4 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=12884&prodName=TLP291), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+4
+4
+Package_SO
+SOIC-4_4.55x3.7mm_P2.54mm
+SOIC, 6 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=11791&prodName=TLP185), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+4
+4
+Package_SO
+SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
+SOIC, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ada4898-1_4898-2.pdf#page=29), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+13
+9
+Package_SO
+SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm_ThermalVias
+SOIC, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ada4898-1_4898-2.pdf#page=29), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+20
+9
+Package_SO
+SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm
+SOIC, 8 Pin (http://www.allegromicro.com/~/media/Files/Datasheets/A4950-Datasheet.ashx#page=8), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+13
+9
+Package_SO
+SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm_ThermalVias
+SOIC, 8 Pin (http://www.allegromicro.com/~/media/Files/Datasheets/A4950-Datasheet.ashx#page=8), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+20
+9
+Package_SO
+SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.81mm
+SOIC, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ada4898-1_4898-2.pdf#page=29), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+13
+9
+Package_SO
+SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.81mm_ThermalVias
+SOIC, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ada4898-1_4898-2.pdf#page=29), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+20
+9
+Package_SO
+SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.95x4.9mm_Mask2.71x3.4mm
+SOIC, 8 Pin (http://www.ti.com/lit/ds/symlink/lm5017.pdf#page=31), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+14
+9
+Package_SO
+SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.95x4.9mm_Mask2.71x3.4mm_ThermalVias
+SOIC, 8 Pin (http://www.ti.com/lit/ds/symlink/lm5017.pdf#page=31), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+23
+9
+Package_SO
+SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.514x3.2mm
+SOIC, 8 Pin (https://www.renesas.com/eu/en/www/doc/datasheet/hip2100.pdf#page=13), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+13
+9
+Package_SO
+SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.514x3.2mm_ThermalVias
+SOIC, 8 Pin (https://www.renesas.com/eu/en/www/doc/datasheet/hip2100.pdf#page=13), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+20
+9
+Package_SO
+SOIC-8-N7_3.9x4.9mm_P1.27mm
+8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC], pin 7 removed (Microchip Packaging Specification 00000049BS.pdf, http://www.onsemi.com/pub/Collateral/NCP1207B.PDF)
+SOIC 1.27
+0
+7
+7
+Package_SO
+SOIC-8_3.9x4.9mm_P1.27mm
+SOIC, 8 Pin (JEDEC MS-012AA, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_8.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+8
+8
+Package_SO
+SOIC-8_5.23x5.23mm_P1.27mm
+SOIC, 8 Pin (http://www.winbond.com/resource-files/w25q32jv%20revg%2003272018%20plus.pdf#page=68), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+8
+8
+Package_SO
+SOIC-8_5.275x5.275mm_P1.27mm
+SOIC, 8 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/20005045C.pdf#page=23), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+8
+8
+Package_SO
+SOIC-8_7.5x5.85mm_P1.27mm
+SOIC, 8 Pin (http://www.ti.com/lit/ml/mpds382b/mpds382b.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+8
+8
+Package_SO
+SOIC-14W_7.5x9mm_P1.27mm
+SOIC, 14 Pin (JEDEC MS-013AF, https://www.analog.com/media/en/package-pcb-resources/package/54614177245586rw_14.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+14
+14
+Package_SO
+SOIC-14_3.9x8.7mm_P1.27mm
+SOIC, 14 Pin (JEDEC MS-012AB, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_14.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+14
+14
+Package_SO
+SOIC-16W-12_7.5x10.3mm_P1.27mm
+SOIC-16 With 12 Pin Placed - Wide, 7.50 mm Body [SOIC] (https://docs.broadcom.com/docs/AV02-0169EN)
+SOIC 1.27 16 12 Wide
+0
+12
+12
+Package_SO
+SOIC-16W_5.3x10.2mm_P1.27mm
+16-Lead Plastic Small Outline (SO) - Wide, 5.3 mm Body (http://www.ti.com/lit/ml/msop002a/msop002a.pdf)
+SOIC 1.27
+0
+16
+16
+Package_SO
+SOIC-16W_7.5x10.3mm_P1.27mm
+SOIC, 16 Pin (JEDEC MS-013AA, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_wide-rw/rw_16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+16
+16
+Package_SO
+SOIC-16W_7.5x12.8mm_P1.27mm
+SOIC, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ri_soic_ic/ri_16_1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+16
+16
+Package_SO
+SOIC-16_3.9x9.9mm_P1.27mm
+SOIC, 16 Pin (JEDEC MS-012AC, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+16
+16
+Package_SO
+SOIC-16_4.55x10.3mm_P1.27mm
+SOIC, 16 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=12858&prodName=TLP291-4), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+16
+16
+Package_SO
+SOIC-18W_7.5x11.6mm_P1.27mm
+SOIC, 18 Pin (JEDEC MS-013AB, https://www.analog.com/media/en/package-pcb-resources/package/33254132129439rw_18.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+18
+18
+Package_SO
+SOIC-20W_7.5x12.8mm_P1.27mm
+SOIC, 20 Pin (JEDEC MS-013AC, https://www.analog.com/media/en/package-pcb-resources/package/233848rw_20.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+20
+20
+Package_SO
+SOIC-24W_7.5x15.4mm_P1.27mm
+SOIC, 24 Pin (JEDEC MS-013AD, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_wide-rw/RW_24.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+24
+24
+Package_SO
+SOIC-28W_7.5x17.9mm_P1.27mm
+SOIC, 28 Pin (JEDEC MS-013AE, https://www.analog.com/media/en/package-pcb-resources/package/35833120341221rw_28.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+28
+28
+Package_SO
+SOIC-28W_7.5x18.7mm_P1.27mm
+SOIC, 28 Pin (https://www.akm.com/akm/en/file/datasheet/AK5394AVS.pdf#page=23), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOIC SO
+0
+28
+28
+Package_SO
+SOIJ-8_5.3x5.3mm_P1.27mm
+8-Lead Plastic Small Outline (SM) - Medium, 5.28 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)
+SOIC 1.27
+0
+8
+8
+Package_SO
+SOJ-36_10.16x23.49mm_P1.27mm
+SOJ, 36 Pin (http://www.issi.com/WW/pdf/61-64C5128AL.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOJ SO
+0
+36
+36
+Package_SO
+SOP-4_3.8x4.1mm_P2.54mm
+SOP, 4 Pin (http://www.ixysic.com/home/pdfs.nsf/www/CPC1017N.pdf/$file/CPC1017N.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOP SO
+0
+4
+4
+Package_SO
+SOP-4_4.4x2.6mm_P1.27mm
+SOP, 4 Pin (http://www.vishay.com/docs/83510/tcmt1100.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOP SO
+0
+4
+4
+Package_SO
+SOP-8-1EP_4.57x4.57mm_P1.27mm_EP4.57x4.45mm
+SOP, 8 Pin (Mini-Circuits XX112 housing; https://ww2.minicircuits.com/case_style/XX112.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOP SO
+0
+13
+9
+Package_SO
+SOP-8-1EP_4.57x4.57mm_P1.27mm_EP4.57x4.45mm_ThermalVias
+SOP, 8 Pin (Mini-Circuits XX112 housing; https://ww2.minicircuits.com/case_style/XX112.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOP SO
+0
+20
+9
+Package_SO
+SOP-8_3.9x4.9mm_P1.27mm
+SOP, 8 Pin (http://www.macronix.com/Lists/Datasheet/Attachments/7534/MX25R3235F,%20Wide%20Range,%2032Mb,%20v1.6.pdf#page=79), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOP SO
+0
+8
+8
+Package_SO
+SOP-8_3.76x4.96mm_P1.27mm
+SOP, 8 Pin (https://ww2.minicircuits.com/case_style/XX211.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOP SO
+0
+8
+8
+Package_SO
+SOP-8_5.28x5.23mm_P1.27mm
+SOP, 8 Pin (http://www.macronix.com/Lists/Datasheet/Attachments/7534/MX25R3235F,%20Wide%20Range,%2032Mb,%20v1.6.pdf#page=80), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOP SO
+0
+8
+8
+Package_SO
+SOP-8_6.62x9.15mm_P2.54mm
+SOP, 8 Pin (http://www.ti.com/lit/ds/symlink/iso1050.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOP SO
+0
+8
+8
+Package_SO
+SOP-16_4.4x10.4mm_P1.27mm
+16-Lead Plastic Small Outline http://www.vishay.com/docs/49633/sg2098.pdf
+SOP 1.27
+0
+16
+16
+Package_SO
+SOP-16_4.55x10.3mm_P1.27mm
+SOP, 16 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=12855&prodName=TLP290-4), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOP SO
+0
+16
+16
+Package_SO
+SOP-18_7x12.5mm_P1.27mm
+SOP, 18 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=30523), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOP SO
+0
+18
+18
+Package_SO
+SOP-24_7.5x15.4mm_P1.27mm
+SOP, 24 Pin (http://www.issi.com/WW/pdf/31FL3218.pdf#page=14), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SOP SO
+0
+24
+24
+Package_SO
+SSO-4_6.7x5.1mm_P2.54mm_Clearance8mm
+4-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://www.vishay.com/docs/84299/vor1142b4.pdf
+SSO Stretched SO SOIC 2.54
+0
+4
+4
+Package_SO
+SSO-6_6.8x4.6mm_P1.27mm_Clearance7mm
+8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true
+SSO Stretched SO SOIC 1.27
+0
+6
+6
+Package_SO
+SSO-6_6.8x4.6mm_P1.27mm_Clearance8mm
+8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true
+SSO Stretched SO SOIC 1.27
+0
+6
+6
+Package_SO
+SSO-8_6.7x9.8mm_P2.54mm_Clearance8mm
+8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://www.vishay.com/docs/83831/lh1533ab.pdf
+SSO Stretched SO SOIC Pitch 2.54
+0
+8
+8
+Package_SO
+SSO-8_6.8x5.9mm_P1.27mm_Clearance7mm
+8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true
+SSO Stretched SO SOIC Pitch 1.27
+0
+8
+8
+Package_SO
+SSO-8_6.8x5.9mm_P1.27mm_Clearance8mm
+8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true
+SSO Stretched SO SOIC Pitch 1.27
+0
+8
+8
+Package_SO
+SSO-8_9.6x6.3mm_P1.27mm_Clearance10.5mm
+8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true
+SSO Stretched SO SOIC Pitch 1.27
+0
+8
+8
+Package_SO
+SSO-8_13.6x6.3mm_P1.27mm_Clearance14.2mm
+8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true
+SSO Stretched SO SOIC Pitch 1.27
+0
+8
+8
+Package_SO
+SSOP-8_2.95x2.8mm_P0.65mm
+SSOP-8 2.9 x2.8mm Pitch 0.65mm
+SSOP-8 2.95x2.8mm Pitch 0.65mm
+0
+8
+8
+Package_SO
+SSOP-8_3.9x5.05mm_P1.27mm
+SSOP, 8 Pin (http://www.fujitsu.com/downloads/MICRO/fsa/pdf/products/memory/fram/MB85RS16-DS501-00014-6v0-E.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SSOP SO
+0
+8
+8
+Package_SO
+SSOP-8_3.95x5.21x3.27mm_P1.27mm
+SSOP-8 3.95x5.21x3.27mm Pitch 1.27mm
+SSOP-8 3.95x5.21x3.27mm 1.27mm
+0
+8
+8
+Package_SO
+SSOP-8_5.25x5.24mm_P1.27mm
+SSOP, 8 Pin (http://www.fujitsu.com/ca/en/Images/MB85RS2MT-DS501-00023-1v0-E.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SSOP SO
+0
+8
+8
+Package_SO
+SSOP-10_3.9x4.9mm_P1.00mm
+10-Lead SSOP, 3.9 x 4.9mm body, 1.00mm pitch (http://www.st.com/resource/en/datasheet/viper01.pdf)
+SSOP 3.9 4.9 1.00
+0
+10
+10
+Package_SO
+SSOP-14_5.3x6.2mm_P0.65mm
+SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot337-1_po.pdf)
+SSOP 0.65
+0
+14
+14
+Package_SO
+SSOP-16_3.9x4.9mm_P0.635mm
+SSOP16: plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot519-1_po.pdf)
+SSOP 0.635
+0
+16
+16
+Package_SO
+SSOP-16_4.4x5.2mm_P0.65mm
+SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot369-1_po.pdf)
+SSOP 0.65
+0
+16
+16
+Package_SO
+SSOP-16_5.3x6.2mm_P0.65mm
+SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot338-1_po.pdf)
+SSOP 0.65
+0
+16
+16
+Package_SO
+SSOP-18_4.4x6.5mm_P0.65mm
+SSOP18: plastic shrink small outline package; 18 leads; body width 4.4 mm (http://toshiba.semicon-storage.com/info/docget.jsp?did=30523&prodName=TBD62783APG)
+SSOP 0.65
+0
+18
+18
+Package_SO
+SSOP-20_3.9x8.7mm_P0.635mm
+SSOP20: plastic shrink small outline package; 24 leads; body width 3.9 mm; lead pitch 0.635; (see http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT231X.pdf)
+SSOP 0.635
+0
+20
+20
+Package_SO
+SSOP-20_4.4x6.5mm_P0.65mm
+SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot266-1_po.pdf)
+SSOP 0.65
+0
+20
+20
+Package_SO
+SSOP-20_5.3x7.2mm_P0.65mm
+SSOP, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001800C.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SSOP SO
+0
+20
+20
+Package_SO
+SSOP-24_3.9x8.7mm_P0.635mm
+SSOP24: plastic shrink small outline package; 24 leads; body width 3.9 mm; lead pitch 0.635; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot556-1_po.pdf)
+SSOP 0.635
+0
+24
+24
+Package_SO
+SSOP-24_5.3x8.2mm_P0.65mm
+24-Lead Plastic Shrink Small Outline (SS)-5.30 mm Body [SSOP] (see Microchip Packaging Specification 00000049BS.pdf)
+SSOP 0.65
+0
+24
+24
+Package_SO
+SSOP-28_3.9x9.9mm_P0.635mm
+SSOP28: plastic shrink small outline package; 28 leads; body width 3.9 mm; lead pitch 0.635; (see http://cds.linear.com/docs/en/datasheet/38901fb.pdf)
+SSOP 0.635
+0
+28
+28
+Package_SO
+SSOP-28_5.3x10.2mm_P0.65mm
+28-Lead Plastic Shrink Small Outline (SS)-5.30 mm Body [SSOP] (see Microchip Packaging Specification 00000049BS.pdf)
+SSOP 0.65
+0
+28
+28
+Package_SO
+SSOP-32_11.305x20.495mm_P1.27mm
+SSOP, 32 Pin (http://www.issi.com/WW/pdf/61-64C5128AL.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+SSOP SO
+0
+32
+32
+Package_SO
+SSOP-44_5.3x12.8mm_P0.5mm
+44-Lead Plastic Shrink Small Outline (SS)-5.30 mm Body [SSOP] (http://cds.linear.com/docs/en/datasheet/680313fa.pdf)
+SSOP 0.5
+0
+44
+44
+Package_SO
+SSOP-48_7.5x15.9mm_P0.635mm
+SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot370-1_po.pdf)
+SSOP 0.635
+0
+48
+48
+Package_SO
+SSOP-56_7.5x18.5mm_P0.635mm
+SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot371-1_po.pdf)
+SSOP 0.635
+0
+56
+56
+Package_SO
+STC_SOP-16_3.9x9.9mm_P1.27mm
+STC  SOP, 16 Pin (https://www.stcmicro.com/datasheet/STC15F2K60S2-en.pdf#page=156), generated with kicad-footprint-generator ipc_gullwing_generator.py
+STC SOP SO
+0
+16
+16
+Package_SO
+ST_MultiPowerSO-30
+MultiPowerSO-30 3EP 16.0x17.2mm Pitch 1mm (http://www.st.com/resource/en/datasheet/vnh2sp30-e.pdf)
+MultiPowerSO-30 3EP 16.0x17.2mm Pitch 1mm
+0
+33
+33
+Package_SO
+ST_PowerSSO-24_SlugDown
+ST PowerSSO-24 1EP 7.5x10.3mm Pitch 0.8mm [JEDEC MO-271] (http://www.st.com/resource/en/datasheet/tda7266p.pdf, http://freedatasheets.com/downloads/Technical%20Note%20Powersso24%20TN0054.pdf)
+ST PowerSSO-24 1EP 7.5x10.3mm Pitch 0.8mm
+0
+25
+25
+Package_SO
+ST_PowerSSO-24_SlugDown_ThermalVias
+ST PowerSSO-24 1EP 7.5x10.3mm Pitch 0.8mm [JEDEC MO-271] (http://www.st.com/resource/en/datasheet/tda7266p.pdf, http://freedatasheets.com/downloads/Technical%20Note%20Powersso24%20TN0054.pdf)
+ST PowerSSO-24 1EP 7.5x10.3mm Pitch 0.8mm
+0
+38
+25
+Package_SO
+ST_PowerSSO-24_SlugUp
+ST PowerSSO-24 1EP 7.5x10.3mm Pitch 0.8mm [JEDEC MO-271] (http://www.st.com/resource/en/datasheet/tda7266p.pdf, http://freedatasheets.com/downloads/Technical%20Note%20Powersso24%20TN0054.pdf)
+ST PowerSSO-24 1EP 7.5x10.3mm Pitch 0.8mm
+0
+24
+24
+Package_SO
+ST_PowerSSO-36_SlugDown
+ST PowerSSO-36 1EP 7.5x10.3mm Pitch 0.8mm [JEDEC MO-271] (http://www.st.com/resource/en/datasheet/tda7492p.pdf, http://freedatasheets.com/downloads/Technical%20Note%20Powersso24%20TN0054.pdf)
+ST PowerSSO-36 1EP 7.5x10.3mm Pitch 0.8mm
+0
+37
+37
+Package_SO
+ST_PowerSSO-36_SlugDown_ThermalVias
+ST PowerSSO-36 1EP 7.5x10.3mm Pitch 0.8mm [JEDEC MO-271] (http://www.st.com/resource/en/datasheet/tda7492p.pdf, http://freedatasheets.com/downloads/Technical%20Note%20Powersso24%20TN0054.pdf)
+ST PowerSSO-36 1EP 7.5x10.3mm Pitch 0.8mm
+0
+50
+37
+Package_SO
+ST_PowerSSO-36_SlugUp
+ST PowerSSO-36 1EP 7.5x10.3mm Pitch 0.8mm [JEDEC MO-271] (http://www.st.com/resource/en/datasheet/tda7492p.pdf, http://freedatasheets.com/downloads/Technical%20Note%20Powersso24%20TN0054.pdf)
+ST PowerSSO-36 1EP 7.5x10.3mm Pitch 0.8mm
+0
+36
+36
+Package_SO
+TI_SO-PowerPAD-8
+8-Lead Plastic PSOP, Exposed Die Pad (TI DDA0008B, see http://www.ti.com/lit/ds/symlink/lm3404.pdf)
+SSOP 0.50 exposed pad
+0
+12
+9
+Package_SO
+TI_SO-PowerPAD-8_ThermalVias
+8-pin HTSOP package with 1.27mm pin pitch, compatible with SOIC-8, 3.9x4.9mm² body, exposed pad, thermal vias with large copper area, as proposed in http://www.ti.com/lit/ds/symlink/tps5430.pdf
+HTSOP 1.27
+0
+19
+9
+Package_SO
+TSOP-5_1.65x3.05mm_P0.95mm
+TSOP-5 package (comparable to TSOT-23), https://www.vishay.com/docs/71200/71200.pdf
+Jedec MO-193C TSOP-5L
+0
+5
+5
+Package_SO
+TSOP-6_1.65x3.05mm_P0.95mm
+TSOP-6 package (comparable to TSOT-23), https://www.vishay.com/docs/71200/71200.pdf
+Jedec MO-193C TSOP-6L
+0
+6
+6
+Package_SO
+TSOP-I-28_11.8x8mm_P0.55mm
+TSOP I, 28 pins, 18.8x8mm body, 0.55mm pitch, IPC-calculated pads (http://ww1.microchip.com/downloads/en/devicedoc/doc0807.pdf)
+TSOP I 28 pins
+0
+28
+28
+Package_SO
+TSOP-I-32_11.8x8mm_P0.5mm
+TSOP-I, 32 Pin (http://www.issi.com/WW/pdf/61-64C5128AL.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+TSOP-I SO
+0
+32
+32
+Package_SO
+TSOP-I-32_18.4x8mm_P0.5mm
+TSOP I, 32 pins, 18.4x8mm body (https://www.micron.com/~/media/documents/products/technical-note/nor-flash/tn1225_land_pad_design.pdf, http://www.fujitsu.com/downloads/MICRO/fma/pdfmcu/f32pm25.pdf)
+TSOP I 32
+0
+32
+32
+Package_SO
+TSOP-I-32_18.4x8mm_P0.5mm_Reverse
+TSOP I, 32 pins, 18.4x8mm body (http://www.futurlec.com/Datasheet/Memory/628128.pdf), reverse mount
+TSOP I 32 reverse
+0
+32
+32
+Package_SO
+TSOP-I-48_18.4x12mm_P0.5mm
+TSOP I, 32 pins, 18.4x8mm body (https://www.micron.com/~/media/documents/products/technical-note/nor-flash/tn1225_land_pad_design.pdf)
+TSOP I 32
+0
+48
+48
+Package_SO
+TSOP-I-56_18.4x14mm_P0.5mm
+TSOP I, 32 pins, 18.4x8mm body (https://www.micron.com/~/media/documents/products/technical-note/nor-flash/tn1225_land_pad_design.pdf)
+TSOP I 32
+0
+56
+56
+Package_SO
+TSOP-II-32_21.0x10.2mm_P1.27mm
+32-lead plastic TSOP; Type II
+TSOP-II 32
+0
+32
+32
+Package_SO
+TSOP-II-44_10.16x18.41mm_P0.8mm
+TSOP-II, 44 Pin (http://www.issi.com/WW/pdf/61-64C5128AL.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+TSOP-II SO
+0
+44
+44
+Package_SO
+TSOP-II-54_22.2x10.16mm_P0.8mm
+54-lead TSOP typ II package
+TSOPII TSOP2
+0
+54
+54
+Package_SO
+TSSOP-8_3x3mm_P0.65mm
+TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot505-1_po.pdf)
+SSOP 0.65
+0
+8
+8
+Package_SO
+TSSOP-8_4.4x3mm_P0.65mm
+8-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)
+SSOP 0.65
+0
+8
+8
+Package_SO
+TSSOP-10_3x3mm_P0.5mm
+TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot552-1_po.pdf)
+SSOP 0.5
+0
+10
+10
+Package_SO
+TSSOP-14-1EP_4.4x5mm_P0.65mm
+14-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] with exposed pad (http://cds.linear.com/docs/en/datasheet/34301fa.pdf)
+SSOP 0.65 exposed pad
+0
+18
+15
+Package_SO
+TSSOP-14_4.4x5mm_P0.65mm
+14-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)
+SSOP 0.65
+0
+14
+14
+Package_SO
+TSSOP-16-1EP_4.4x5mm_P0.65mm
+FE Package; 16-Lead Plastic TSSOP (4.4mm); Exposed Pad Variation BB; (see Linear Technology 1956f.pdf)
+SSOP 0.65
+0
+24
+17
+Package_SO
+TSSOP-16_4.4x5mm_P0.65mm
+16-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)
+SSOP 0.65
+0
+16
+16
+Package_SO
+TSSOP-20_4.4x6.5mm_P0.65mm
+20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)
+SSOP 0.65
+0
+20
+20
+Package_SO
+TSSOP-24_4.4x7.8mm_P0.65mm
+TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot355-1_po.pdf)
+SSOP 0.65
+0
+24
+24
+Package_SO
+TSSOP-28-1EP_4.4x9.7mm_P0.65mm
+TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; Exposed Pad Variation; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot361-1_po.pdf)
+SSOP 0.65
+0
+36
+29
+Package_SO
+TSSOP-28_4.4x9.7mm_P0.65mm
+TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot361-1_po.pdf)
+SSOP 0.65
+0
+28
+28
+Package_SO
+TSSOP-30_4.4x7.8mm_P0.5mm
+TSSOP30: plastic thin shrink small outline package; 30 leads; body width 4.4 mm (http://www.ti.com/lit/ds/symlink/bq78350.pdf)
+SSOP 0.5
+0
+30
+30
+Package_SO
+TSSOP-32_6.1x11mm_P0.65mm
+TSSOP32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot487-1_po.pdf)
+SSOP 0.65
+0
+32
+32
+Package_SO
+TSSOP-38_4.4x9.7mm_P0.5mm
+TSSOP38: plastic thin shrink small outline package; 38 leads; body width 4.4 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot510-1_po.pdf)
+SSOP 0.5
+0
+38
+38
+Package_SO
+TSSOP-38_6.1x12.5mm_P0.65mm
+TSSOP38: plastic thin shrink small outline package; 38 leads; body width 6.1 mm (http://www.ti.com/lit/ds/symlink/msp430g2744.pdf)
+SSOP 0.65
+0
+38
+38
+Package_SO
+TSSOP-44_4.4x11.2mm_P0.5mm
+TSSOP44: plastic thin shrink small outline package; 44 leads; body width 4.4 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot510-1_po.pdf)
+SSOP 0.5
+0
+44
+44
+Package_SO
+TSSOP-48_6.1x12.5mm_P0.5mm
+TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot362-1_po.pdf)
+SSOP 0.5
+0
+48
+48
+Package_SO
+TSSOP-56_6.1x14mm_P0.5mm
+TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot364-1_po.pdf)
+SSOP 0.5
+0
+56
+56
+Package_SO
+Texas_HSOP-8-1EP_3.9x4.9mm_P1.27mm
+Texas Instruments HSOP 9, 1.27mm pitch, 3.9x4.9mm body, exposed pad, DDA0008J (http://www.ti.com/lit/ds/symlink/tps5430.pdf)
+HSOP 1.27
+0
+11
+9
+Package_SO
+Texas_HSOP-8-1EP_3.9x4.9mm_P1.27mm_ThermalVias
+Texas Instruments HSOP 9, 1.27mm pitch, 3.9x4.9mm body, exposed pad, thermal vias, DDA0008J (http://www.ti.com/lit/ds/symlink/tps5430.pdf)
+HSOP 1.27
+0
+20
+9
+Package_SO
+Texas_HTSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.95x4.9mm_Mask2.4x3.1mm_ThermalVias
+8-pin HTSOP package with 1.27mm pin pitch, compatible with SOIC-8, 3.9x4.9mm body, exposed pad, thermal vias, http://www.ti.com/lit/ds/symlink/drv8870.pdf
+HTSOP 1.27
+0
+18
+9
+Package_SO
+Texas_PWP0020A
+20-Pin Thermally Enhanced Thin Shrink Small-Outline Package, Body 4.4x6.5x1.1mm, Pad 3.0x4.2mm, Texas Instruments (see http://www.ti.com/lit/ds/symlink/lm5118.pdf)
+PWP HTSSOP 0.65mm
+0
+25
+21
+Package_SO
+Texas_R-PDSO-G8_EP2.95x4.9mm_Mask2.4x3.1mm
+HSOIC, 8 Pin (http://www.ti.com/lit/ds/symlink/lmr14030.pdf#page=28, http://www.ti.com/lit/ml/msoi002j/msoi002j.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+HSOIC SO
+0
+16
+9
+Package_SO
+Texas_R-PDSO-G8_EP2.95x4.9mm_Mask2.4x3.1mm_ThermalVias
+HSOIC, 8 Pin (http://www.ti.com/lit/ds/symlink/lmr14030.pdf#page=28, http://www.ti.com/lit/ml/msoi002j/msoi002j.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+HSOIC SO
+0
+23
+9
+Package_SO
+Texas_R-PDSO-N5
+Plastic Small outline http://www.ti.com/lit/ml/mpds158c/mpds158c.pdf
+SOT23 R-PDSO-N5
+0
+5
+5
+Package_SO
+VSO-40_7.6x15.4mm_P0.762mm
+VSO40: plastic very small outline package; 40 leads (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot158-1_po.pdf)
+SSOP 0.762
+0
+40
+40
+Package_SO
+VSO-56_11.1x21.5mm_P0.75mm
+VSO56: plastic very small outline package; 56 leads (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot190-1_po.pdf)
+SSOP 0.75
+0
+56
+56
+Package_SO
+VSSOP-8_2.3x2mm_P0.5mm
+VSSOP-8 2.3x2mm Pitch 0.5mm
+VSSOP-8 2.3x2mm Pitch 0.5mm
+0
+8
+8
+Package_SO
+VSSOP-8_2.4x2.1mm_P0.5mm
+http://www.ti.com/lit/ml/mpds050d/mpds050d.pdf
+VSSOP DCU R-PDSO-G8 Pitch0.5mm
+0
+8
+8
+Package_SO
+VSSOP-8_3.0x3.0mm_P0.65mm
+VSSOP-8 3.0 x 3.0, http://www.ti.com/lit/ds/symlink/lm75b.pdf
+VSSOP-8 3.0 x 3.0
+0
+8
+8
+Package_SO
+VSSOP-10_3x3mm_P0.5mm
+VSSOP, 10 Pin (http://www.ti.com/lit/ds/symlink/ads1115.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py
+VSSOP SO
+0
+10
+10
+Package_SO
+Vishay_PowerPAK_1212-8_Dual
+PowerPAK 1212-8 Dual (https://www.vishay.com/docs/71656/ppak12128.pdf, https://www.vishay.com/docs/72598/72598.pdf)
+Vishay_PowerPAK_1212-8_Dual
+0
+6
+6
+Package_SO
+Vishay_PowerPAK_1212-8_Single
+PowerPAK 1212-8 Single (https://www.vishay.com/docs/71656/ppak12128.pdf, https://www.vishay.com/docs/72597/72597.pdf)
+Vishay PowerPAK 1212-8 Single
+0
+5
+5
+Package_SO
+Zetex_SM8
+Zetex,  SMD, 8 pin package (http://datasheet.octopart.com/ZDT6758TA-Zetex-datasheet-68057.pdf)
+Zetex SM8
+0
+8
+8
+Package_SON
+Diodes_PowerDI3333-8
+Diodes Incorporated PowerDI3333-8, Plastic Dual Flat No Lead Package, 3.3x3.3x0.8mm Body, https://www.diodes.com/assets/Package-Files/PowerDI3333-8.pdf
+PowerDI 0.65
+0
+13
+5
+Package_SON
+Fairchild_DualPower33-6_3x3mm
+Fairchild Power33 MOSFET package, 3x3mm (see https://www.fairchildsemi.com/datasheets/FD/FDMC8032L.pdf)
+mosfet
+0
+18
+6
+Package_SON
+Fairchild_MicroPak-6_1.0x1.45mm_P0.5mm
+Fairchild-specific MicroPak-6 1.0x1.45mm Pitch 0.5mm https://www.nxp.com/docs/en/application-note/AN10343.pdff
+Fairchild-specific MicroPak-6 1.0x1.45mm Pitch 0.5mm
+0
+6
+6
+Package_SON
+Fairchild_MicroPak2-6_1.0x1.0mm_P0.35mm
+Fairchild-specific MicroPak2-6 1.0x1.0mm Pitch 0.35mm https://www.nxp.com/docs/en/application-note/AN10343.pdff
+Fairchild-specific MicroPak2-6 1.0x1.0mm Pitch 0.35mm
+0
+6
+6
+Package_SON
+HUSON-3-1EP_2x2mm_P1.3mm_EP1.1x1.6mm
+HUSON, 3 Pin, SOT1061 (Ref: https://assets.nexperia.com/documents/data-sheet/PMEG2020CPA.pdf)
+huson nolead SOT1061
+0
+4
+3
+Package_SON
+HVSON-8-1EP_4x4mm_P0.8mm_EP2.2x3.1mm
+HVSON, 8 Pin (https://www.nxp.com/docs/en/data-sheet/PCF8523.pdf (page 57)), generated with kicad-footprint-generator ipc_noLead_generator.py
+HVSON NoLead
+0
+13
+9
+Package_SON
+Infineon_PG-TISON-8-2
+Infineon, PG-TISON-8-2, 5x6x1.15mm, 1.27mm Pitch, Exposed Paddle, https://www.infineon.com/cms/en/product/packages/PG-TISON/PG-TISON-8-2/
+tison
+0
+23
+7
+Package_SON
+Infineon_PG-TISON-8-3
+Infineon, PG-TISON-8-2, 5x6x1.15mm, 1.27mm Pitch, Exposed Paddle, https://www.infineon.com/cms/en/product/packages/PG-TISON/PG-TISON-8-2/
+tison
+0
+23
+7
+Package_SON
+Infineon_PG-TISON-8-4
+Infineon, PG-TISON-8-4, 5x6x1.15mm, 1.27mm Pitch, Exposed Paddle, https://www.infineon.com/cms/en/product/packages/PG-TISON/PG-TISON-8-4/
+tison
+0
+26
+8
+Package_SON
+Infineon_PG-TISON-8-5
+Infineon, PG-TISON-8-5, 8x8x1.1mm, 1mm Pitch, https://www.infineon.com/cms/en/product/packages/PG-TISON/PG-TISON-8-5/
+tison
+0
+34
+8
+Package_SON
+NXP_XSON-16
+http://www.nxp.com/documents/outline_drawing/SOT1341-1.pdf
+NXP XSON SOT-1341
+0
+16
+16
+Package_SON
+ROHM_VML0806
+VML0806, Rohm (http://rohmfs.rohm.com/en/techdata_basic/transistor/soldering_condition/VML0806_Soldering_Condition.pdf, http://rohmfs.rohm.com/en/products/databook/package/spec/discrete/vml0806_tr-e.pdf)
+ROHM VML0806
+0
+3
+3
+Package_SON
+RTC_SMD_MicroCrystal_C3_2.5x3.7mm
+MicroCrystal C3 2.5x3.7mm, https://www.microcrystal.com/fileadmin/Media/Products/RTC/Datasheet/RV-1805-C3.pdf
+RTC C3
+0
+10
+10
+Package_SON
+SON-8-1EP_3x2mm_P0.5mm_EP1.4x1.6mm
+SON, 8 Pin (http://www.fujitsu.com/downloads/MICRO/fsa/pdf/products/memory/fram/MB85RS16-DS501-00014-6v0-E.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+SON NoLead
+0
+13
+9
+Package_SON
+Texas_DQK
+Texas WSON-6 DQK, http://www.ti.com/lit/ds/symlink/csd16301q2.pdf
+Texas WSON6 2x2mm
+0
+10
+8
+Package_SON
+Texas_DRC0010J
+Texas DRC0010J, VSON10 3x3mm Body, 0.5mm Pitch,  http://www.ti.com/lit/ds/symlink/tps63000.pdf
+Texas VSON10 3x3mm
+0
+17
+11
+Package_SON
+Texas_DRC0010J_ThermalVias
+Texas DRC0010J, VSON10 3x3mm Body, 0.5mm Pitch,  http://www.ti.com/lit/ds/symlink/tps63000.pdf
+Texas VSON10 3x3mm
+0
+21
+11
+Package_SON
+Texas_DSC0010J
+3x3mm Body, 0.5mm Pitch, DSC0010J, WSON, http://www.ti.com/lit/ds/symlink/tps61201.pdf
+0.5 DSC0010J WSON
+0
+33
+11
+Package_SON
+Texas_DSC0010J_ThermalVias
+3x3mm Body, 0.5mm Pitch, DSC0010J, WSON, http://www.ti.com/lit/ds/symlink/tps61201.pdf
+0.5 DSC0010J WSON
+0
+39
+11
+Package_SON
+Texas_PWSON-N6
+Plastic Small Outline No-Lead http://www.ti.com/lit/ml/mpds176e/mpds176e.pdf
+Plastic Small Outline No-Lead
+0
+7
+7
+Package_SON
+Texas_R-PWSON-N12_EP0.4x2mm
+http://www.ti.com/lit/ds/symlink/tpd6f003.pdf
+WSON SMD
+0
+16
+13
+Package_SON
+Texas_S-PDSO-N12
+http://www.ti.com/lit/ds/symlink/bq27441-g1.pdf
+SON thermal pads
+0
+44
+13
+Package_SON
+Texas_S-PVSON-N8
+8-Lead Plastic VSON, 3x3mm Body, 0.65mm Pitch, S-PVSON-N8, http://www.ti.com/lit/ds/symlink/opa2333.pdf
+DFN 0.65 S-PVSON-N8
+0
+21
+9
+Package_SON
+Texas_S-PVSON-N8_ThermalVias
+8-Lead Plastic VSON, 3x3mm Body, 0.65mm Pitch, S-PVSON-N8, http://www.ti.com/lit/ds/symlink/opa2333.pdf
+DFN 0.65 S-PVSON-N8
+0
+27
+9
+Package_SON
+Texas_S-PVSON-N10
+3x3mm Body, 0.5mm Pitch, S-PVSON-N10, DRC, http://www.ti.com/lit/ds/symlink/tps61201.pdf
+0.5 S-PVSON-N10 DRC
+0
+33
+11
+Package_SON
+Texas_S-PVSON-N10_ThermalVias
+3x3mm Body, 0.5mm Pitch, S-PVSON-N10, DRC, http://www.ti.com/lit/ds/symlink/tps61201.pdf
+0.5 S-PVSON-N10 DRC
+0
+39
+11
+Package_SON
+Texas_S-PWSON-N8_EP1.2x2mm
+WSON, 8 Pin (http://www.ti.com/lit/ds/symlink/lp2951.pdf#page=27), generated with kicad-footprint-generator ipc_noLead_generator.py
+WSON NoLead
+0
+11
+9
+Package_SON
+Texas_S-PWSON-N8_EP1.2x2mm_ThermalVias
+WSON, 8 Pin (http://www.ti.com/lit/ds/symlink/lp2951.pdf#page=27), generated with kicad-footprint-generator ipc_noLead_generator.py
+WSON NoLead
+0
+18
+9
+Package_SON
+Texas_S-PWSON-N10
+3x3mm Body, 0.5mm Pitch, S-PWSON-N10, DSC, http://www.ti.com/lit/ds/symlink/tps63060.pdf
+0.5 S-PWSON-N10 DSC
+0
+41
+11
+Package_SON
+Texas_S-PWSON-N10_ThermalVias
+3x3mm Body, 0.5mm Pitch, S-PWSON-N10, DSC, http://www.ti.com/lit/ds/symlink/tps63060.pdf
+0.5 S-PWSON-N10 DSC
+0
+47
+11
+Package_SON
+Texas_X2SON-4_1x1mm_P0.65mm
+X2SON 5 pin 1x1mm package (Reference Datasheet: http://www.ti.com/lit/ds/sbvs193d/sbvs193d.pdf Reference part: TPS383x) [StepUp generated footprint]
+X2SON
+0
+13
+5
+Package_SON
+USON-10_2.5x1.0mm_P0.5mm
+USON-10 2.5x1.0mm_ Pitch 0.5mm http://www.ti.com/lit/ds/symlink/tpd4e02b04.pdf
+USON-10 2.5x1.0mm Pitch 0.5mm
+0
+10
+10
+Package_SON
+USON-20_2x4mm_P0.4mm
+USON-20 2x4mm Pitch 0.4mm http://www.ti.com/lit/ds/symlink/txb0108.pdf
+USON-20 2x4mm Pitch 0.4mm
+0
+20
+20
+Package_SON
+VSON-8_3.3x3.3mm_P0.65mm_NexFET
+8-Lead Plastic Dual Flat, No Lead Package (MF) - 3.3x3.3x1 mm Body [VSON] http://www.ti.com/lit/ds/symlink/csd87334q3d.pdf
+VSON 0.65
+0
+12
+5
+Package_SON
+VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm
+VSON, 10 Pin (http://rohmfs.rohm.com/en/products/databook/datasheet/ic/power/switching_regulator/bd8314nuv-e.pdf (Page 20)), generated with kicad-footprint-generator ipc_noLead_generator.py
+VSON NoLead
+0
+15
+11
+Package_SON
+VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm_ThermalVias
+VSON, 10 Pin (http://rohmfs.rohm.com/en/products/databook/datasheet/ic/power/switching_regulator/bd8314nuv-e.pdf (Page 20)), generated with kicad-footprint-generator ipc_noLead_generator.py
+VSON NoLead
+0
+18
+11
+Package_SON
+VSON-10-1EP_3x3mm_P0.5mm_EP1.65x2.4mm
+VSON 10 Thermal on 11 3x3mm Pitch 0.5mm http://chip.tomsk.ru/chip/chipdoc.nsf/Package/D8A64DD165C2AAD9472579400024FC41!OpenDocument
+VSON 10 Thermal on 11 3x3mm Pitch 0.5mm
+0
+21
+11
+Package_SON
+VSON-10-1EP_3x3mm_P0.5mm_EP1.65x2.4mm_ThermalVias
+VSON 10 Thermal on 11 3x3mm Pitch 0.5mm http://chip.tomsk.ru/chip/chipdoc.nsf/Package/D8A64DD165C2AAD9472579400024FC41!OpenDocument
+VSON 10 Thermal on 11 3x3mm Pitch 0.5mm
+0
+27
+11
+Package_SON
+VSONP-8-1EP_5x6_P1.27mm
+SON, 8-Leads, Body 5x6x1mm, Pitch 1.27mm; (see Texas Instruments CSD18531Q5A http://www.ti.com/lit/ds/symlink/csd18531q5a.pdf)
+VSONP 1.27
+0
+13
+3
+Package_SON
+WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm
+WSON, 6 Pin (http://www.ti.com/lit/ds/symlink/tps61040.pdf#page=35), generated with kicad-footprint-generator ipc_noLead_generator.py
+WSON NoLead
+0
+9
+7
+Package_SON
+WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm_ThermalVias
+WSON, 6 Pin (http://www.ti.com/lit/ds/symlink/tps61040.pdf#page=35), generated with kicad-footprint-generator ipc_noLead_generator.py
+WSON NoLead
+0
+12
+7
+Package_SON
+WSON-6-1EP_3x3mm_P0.95mm
+WSON6 3*3 MM, 0.95 PITCH; http://www.ti.com/lit/ds/symlink/lmr62421.pdf
+WSON6 0.95
+0
+10
+7
+Package_SON
+WSON-6_1.5x1.5mm_P0.5mm
+WSON6, http://www.ti.com/lit/ds/symlink/tlv702.pdf
+WSON6_1.5x1.5mm_P0.5mm
+0
+6
+6
+Package_SON
+WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm
+8-Lead Plastic WSON, 2x2mm Body, 0.5mm Pitch, WSON-8, http://www.ti.com/lit/ds/symlink/lm27761.pdf
+WSON 8 1EP
+0
+11
+9
+Package_SON
+WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm_ThermalVias
+8-Lead Plastic WSON, 2x2mm Body, 0.5mm Pitch, WSON-8, http://www.ti.com/lit/ds/symlink/lm27761.pdf
+WSON 8 1EP ThermalVias
+0
+14
+9
+Package_SON
+WSON-8-1EP_3x2.5mm_P0.5mm_EP1.2x1.5mm_PullBack
+WSON, 8 Pin (http://www.ti.com/lit/ml/mpds400/mpds400.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+WSON NoLead
+0
+13
+9
+Package_SON
+WSON-8-1EP_3x2.5mm_P0.5mm_EP1.2x1.5mm_PullBack_ThermalVias
+WSON, 8 Pin (http://www.ti.com/lit/ml/mpds400/mpds400.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+WSON NoLead
+0
+18
+9
+Package_SON
+WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm
+8-Lead Plastic WSON, 2x2mm Body, 0.5mm Pitch, WSON-8, http://www.ti.com/lit/ds/symlink/lm27761.pdf
+WSON 8 1EP
+0
+13
+9
+Package_SON
+WSON-8-1EP_6x5mm_P1.27mm_EP3.4x4.3mm
+WSON, 8 Pin (http://www.winbond.com/resource-files/w25q32jv%20revg%2003272018%20plus.pdf (page 68)), generated with kicad-footprint-generator ipc_noLead_generator.py
+WSON NoLead
+0
+13
+9
+Package_SON
+WSON-8-1EP_6x5mm_P1.27mm_EP3.4x4mm
+WSON, 8 Pin (http://ww1.microchip.com/downloads/en/AppNotes/S72030.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py
+WSON NoLead
+0
+13
+9
+Package_SON
+WSON-8_4x4mm_P0.8mm
+http://www.ti.com/lit/ml/mpds406/mpds406.pdf
+WSON8_4x4mm_P0.8mm
+0
+9
+9
+Package_SON
+WSON-10-1EP_2x3mm_P0.5mm_EP0.84x2.4mm
+WSON-10 package 2x3mm body, pitch 0.5mm, see http://www.ti.com/lit/ds/symlink/tps62177.pdf
+WSON 0.5 
+0
+14
+11
+Package_SON
+WSON-10-1EP_2x3mm_P0.5mm_EP0.84x2.4mm_ThermalVias
+WSON-10 package 2x3mm body, pitch 0.5mm, thermal vias and counter-pad, see http://www.ti.com/lit/ds/symlink/tps62177.pdf
+WSON 0.5 thermal vias
+0
+17
+11
+Package_SON
+WSON-10-1EP_4x3mm_P0.5mm_EP2.2x2mm
+10-Lead Plastic WSON, 4x3mm Body, 0.5mm Pitch (http://www.ti.com/lit/ds/symlink/lm4990.pdf)
+WSON 0.5
+0
+15
+11
+Package_SON
+WSON-12-1EP_3x2mm_P0.5mm_EP1x2.65
+WSON-12 http://www.ti.com/lit/ds/symlink/lm27762.pdf
+WSON-12
+0
+15
+13
+Package_SON
+WSON-12-1EP_3x2mm_P0.5mm_EP1x2.65_ThermalVias
+WSON-12 http://www.ti.com/lit/ds/symlink/lm27762.pdf
+WSON-12
+0
+19
+13
+Package_SON
+WSON-12-1EP_4x4mm_P0.5mm_EP2.6x3mm
+WSON, 12 Pin (http://www.ti.com/lit/ds/symlink/ldc1312.pdf#page=62), generated with kicad-footprint-generator ipc_noLead_generator.py
+WSON NoLead
+0
+17
+13
+Package_SON
+WSON-12-1EP_4x4mm_P0.5mm_EP2.6x3mm_ThermalVias
+WSON, 12 Pin (http://www.ti.com/lit/ds/symlink/ldc1312.pdf#page=62), generated with kicad-footprint-generator ipc_noLead_generator.py
+WSON NoLead
+0
+27
+13
+Package_SON
+WSON-14-1EP_4.0x4.0mm_P0.5mm_EP2.6x2.6mm
+14-Lead Plastic Dual Flat, No Lead Package - 4.0x4.0x0.8 mm Body [WSON], http://www.ti.com/lit/ml/mpds421/mpds421.pdf
+NHL014B
+0
+19
+15
+Package_SON
+WSON-16_3.3x1.35_P0.4mm
+WSON-16 3.3 x 1.35mm  Pitch 0.4mm http://www.chip.tomsk.ru/chip/chipdoc.nsf/Package/C67E729A4D6C883A4725793E004C8739!OpenDocument
+WSON-16 3.3 x 1.35mm  Pitch 0.4mm
+0
+20
+17
+Package_SON
+X2SON-8_1.4x1mm_P0.35mm
+X2SON-8 1.4x1mm Pitch0.35mm http://www.ti.com/lit/ds/symlink/pca9306.pdf
+X2SON-8 1.4x1mm Pitch0.35mm
+0
+8
+8
+Package_SO_J-Lead
+TSOC-6_3.76x3.94mm_P1.27mm
+Maxim Integrated TSOC-6 D6+1,https://datasheets.maximintegrated.com/en/ds/DS2401.pdf, https://pdfserv.maximintegrated.com/land_patterns/90-0321.PDF
+TSOC-6
+0
+6
+6
+Package_TO_SOT_SMD
+ATPAK-2
+ATPAK SMD package, http://www.onsemi.com/pub/Collateral/ENA2192-D.PDF
+ATPAK 
+0
+7
+3
+Package_TO_SOT_SMD
+Analog_KS-4
+Analog Devices KS-4, http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/sc70ks/ks_4.pdf
+Analog Devices KS-4 (like EIAJ SC-82)
+0
+4
+4
+Package_TO_SOT_SMD
+Diodes_SOT-553
+Diodes SOT-553, https://www.diodes.com/assets/Package-Files/SOT553.pdf
+SOT-553
+0
+5
+5
+Package_TO_SOT_SMD
+HVSOF5
+HVSOF5, http://rohmfs.rohm.com/en/techdata_basic/ic/package/hvsof5_1-e.pdf, http://rohmfs.rohm.com/en/products/databook/datasheet/ic/sensor/hall/bu52001gul-e.pdf
+HVSOF5
+0
+5
+5
+Package_TO_SOT_SMD
+HVSOF6
+HVSOF6, http://rohmfs.rohm.com/en/techdata_basic/ic/package/hvsof6_1-e.pdf, http://rohmfs.rohm.com/en/products/databook/datasheet/ic/audio_video/video_amplifier/bh76106hfv-e.pdf
+HVSOF6
+0
+7
+7
+Package_TO_SOT_SMD
+Infineon_PG-HDSOP-10-1
+Infineon PG-HDSOP-10-1 (DDPAK), 20.96x6.5x2.3mm, slug up (https://www.infineon.com/cms/en/product/packages/PG-HDSOP/PG-HDSOP-10-1/)
+hdsop 10 ddpak
+0
+10
+10
+Package_TO_SOT_SMD
+Infineon_PG-HSOF-8-1
+Infineon HSOF-8-1 power mosfet http://www.infineon.com/cms/en/product/packages/PG-HSOF/PG-HSOF-8-1/
+mosfet hsof
+0
+54
+3
+Package_TO_SOT_SMD
+Infineon_PG-HSOF-8-1_ThermalVias
+HSOF-8-1 power mosfet http://www.infineon.com/cms/en/product/packages/PG-HSOF/PG-HSOF-8-1/
+mosfet hsof thermal vias
+0
+57
+3
+Package_TO_SOT_SMD
+Infineon_PG-TO-220-7Lead_TabPin8
+Infineon PG-TO-220-7, Tab as Pin 8, see e.g. https://www.infineon.com/dgdl/Infineon-BTS50055-1TMC-DS-v01_00-EN.pdf?fileId=5546d4625a888733015aa9b0007235e9
+Infineon PG-TO-220-7
+0
+12
+8
+Package_TO_SOT_SMD
+LFPAK33
+LFPAK33 SOT-1210 https://assets.nexperia.com/documents/outline-drawing/SOT1210.pdf
+LFPAK33 SOT-1210
+0
+17
+5
+Package_TO_SOT_SMD
+LFPAK56
+LFPAK56 https://assets.nexperia.com/documents/outline-drawing/SOT669.pdf
+LFPAK56 SOT-669 Power-SO8
+0
+18
+5
+Package_TO_SOT_SMD
+OnSemi_ECH8
+On Semiconductor ECH8, https://www.onsemi.com/pub/Collateral/318BF.PDF
+ECH8 SOT28-FL SOT-28-FL
+0
+8
+8
+Package_TO_SOT_SMD
+PQFN_8x8
+Low Profile 8x8mm PQFN, Dual Cool 88, https://www.onsemi.com/pub/Collateral/FDMT80080DC-D.pdf
+pqfn vdfn mosfet
+0
+9
+3
+Package_TO_SOT_SMD
+PowerMacro_M234_NoHole
+TO-50-4 Power Macro Package Style M234
+TO-50-4 Power Macro Package Style M234
+0
+4
+4
+Package_TO_SOT_SMD
+PowerMacro_M234_WithHole
+TO-50-4 Power Macro Package Style M234
+TO-50-4 Power Macro Package Style M234
+0
+4
+4
+Package_TO_SOT_SMD
+Rohm_HRP7
+Rohm HRP7 SMD package, http://rohmfs.rohm.com/en/techdata_basic/ic/package/hrp7_1-e.pdf, http://rohmfs.rohm.com/en/products/databook/datasheet/ic/motor/dc/bd621x-e.pdf
+Rohm HRP7 SMD
+0
+69
+7
+Package_TO_SOT_SMD
+SC-59
+SC-59, https://lib.chipdip.ru/images/import_diod/original/SOT-23_SC-59.jpg
+SC-59
+0
+3
+3
+Package_TO_SOT_SMD
+SC-59_Handsoldering
+SC-59, hand-soldering varaint, https://lib.chipdip.ru/images/import_diod/original/SOT-23_SC-59.jpg
+SC-59 hand-soldering
+0
+3
+3
+Package_TO_SOT_SMD
+SC-70-8
+SC70-8
+SC70-8
+0
+8
+8
+Package_TO_SOT_SMD
+SC-70-8_Handsoldering
+SC70-8, Handsoldering
+SC70-8 Handsoldering
+0
+8
+8
+Package_TO_SOT_SMD
+SC-82AA
+SC-82AA
+SC-82AA
+0
+4
+4
+Package_TO_SOT_SMD
+SC-82AA_Handsoldering
+SC-82AA
+SC-82AA
+0
+4
+4
+Package_TO_SOT_SMD
+SC-82AB
+SC-82AB
+SC-82AB
+0
+4
+4
+Package_TO_SOT_SMD
+SC-82AB_Handsoldering
+SC-82AB
+SC-82AB
+0
+4
+4
+Package_TO_SOT_SMD
+SOT-23
+SOT-23, Standard
+SOT-23
+0
+3
+3
+Package_TO_SOT_SMD
+SOT-23-5
+5-pin SOT23 package
+SOT-23-5
+0
+5
+5
+Package_TO_SOT_SMD
+SOT-23-5_HandSoldering
+5-pin SOT23 package
+SOT-23-5 hand-soldering
+0
+5
+5
+Package_TO_SOT_SMD
+SOT-23-6
+6-pin SOT-23 package
+SOT-23-6
+0
+6
+6
+Package_TO_SOT_SMD
+SOT-23-6_Handsoldering
+6-pin SOT-23 package, Handsoldering
+SOT-23-6 Handsoldering
+0
+6
+6
+Package_TO_SOT_SMD
+SOT-23-8
+8-pin SOT-23 package, http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/sot-23rj/rj_8.pdf
+SOT-23-8
+0
+8
+8
+Package_TO_SOT_SMD
+SOT-23-8_Handsoldering
+8-pin SOT-23 package, Handsoldering, http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/sot-23rj/rj_8.pdf
+SOT-23-8 Handsoldering
+0
+8
+8
+Package_TO_SOT_SMD
+SOT-23W
+SOT-23W http://www.allegromicro.com/~/media/Files/Datasheets/A112x-Datasheet.ashx?la=en&hash=7BC461E058CC246E0BAB62433B2F1ECA104CA9D3
+SOT-23W
+0
+3
+3
+Package_TO_SOT_SMD
+SOT-23W_Handsoldering
+SOT-23W http://www.allegromicro.com/~/media/Files/Datasheets/A112x-Datasheet.ashx?la=en&hash=7BC461E058CC246E0BAB62433B2F1ECA104CA9D3
+SOT-23W for handsoldering
+0
+3
+3
+Package_TO_SOT_SMD
+SOT-23_Handsoldering
+SOT-23, Handsoldering
+SOT-23
+0
+3
+3
+Package_TO_SOT_SMD
+SOT-89-3
+SOT-89-3
+SOT-89-3
+0
+6
+3
+Package_TO_SOT_SMD
+SOT-89-3_Handsoldering
+SOT-89-3 Handsoldering
+SOT-89-3 Handsoldering
+0
+5
+3
+Package_TO_SOT_SMD
+SOT-89-5
+SOT-89-5, Housing,http://www.e-devices.ricoh.co.jp/en/products/product_power/pkg/sot-89-5.pdf
+SOT-89-5 Housing 
+0
+9
+5
+Package_TO_SOT_SMD
+SOT-89-5_Handsoldering
+SOT89-5, Housing,http://www.e-devices.ricoh.co.jp/en/products/product_power/pkg/sot-89-5.pdf
+SOT89-5 Housing 
+0
+9
+5
+Package_TO_SOT_SMD
+SOT-143
+SOT-143
+SOT-143
+0
+4
+4
+Package_TO_SOT_SMD
+SOT-143R_Reverse
+SOT-143R Reverse
+SOT-143R Reverse
+0
+4
+4
+Package_TO_SOT_SMD
+SOT-143R_Reverse_Handsoldering
+SOT-143R Reverse Handsoldering
+SOT-143 Reverse Handsoldering
+0
+4
+4
+Package_TO_SOT_SMD
+SOT-143_Handsoldering
+SOT-143 Handsoldering
+SOT-143 Handsoldering
+0
+4
+4
+Package_TO_SOT_SMD
+SOT-223
+module CMS SOT223 4 pins
+CMS SOT
+0
+4
+4
+Package_TO_SOT_SMD
+SOT-223-3_TabPin2
+module CMS SOT223 4 pins
+CMS SOT
+0
+4
+3
+Package_TO_SOT_SMD
+SOT-223-5
+module CMS SOT223 5 pins, http://ww1.microchip.com/downloads/en/DeviceDoc/51751a.pdf
+CMS SOT
+0
+5
+5
+Package_TO_SOT_SMD
+SOT-223-6
+module CMS SOT223 6 pins, http://www.ti.com/lit/ds/symlink/tps737.pdf
+CMS SOT
+0
+6
+6
+Package_TO_SOT_SMD
+SOT-223-6_TabPin3
+module CMS SOT223 6 pins, http://www.ti.com/lit/ds/symlink/tps737.pdf
+CMS SOT
+0
+6
+5
+Package_TO_SOT_SMD
+SOT-223-8
+module CMS SOT223 8 pins, https://www.diodes.com/assets/Datasheets/ZXSBMR16PT8.pdf
+CMS SOT
+0
+8
+8
+Package_TO_SOT_SMD
+SOT-323_SC-70
+SOT-323, SC-70
+SOT-323 SC-70
+0
+3
+3
+Package_TO_SOT_SMD
+SOT-323_SC-70_Handsoldering
+SOT-323, SC-70 Handsoldering
+SOT-323 SC-70 Handsoldering
+0
+3
+3
+Package_TO_SOT_SMD
+SOT-343_SC-70-4
+SOT-343, SC-70-4
+SOT-343 SC-70-4
+0
+4
+4
+Package_TO_SOT_SMD
+SOT-343_SC-70-4_Handsoldering
+SOT-343, SC-70-4, Handsoldering
+SOT-343 SC-70-4 Handsoldering
+0
+4
+4
+Package_TO_SOT_SMD
+SOT-353_SC-70-5
+SOT-353, SC-70-5
+SOT-353 SC-70-5
+0
+5
+5
+Package_TO_SOT_SMD
+SOT-353_SC-70-5_Handsoldering
+SOT-353, SC-70-5, Handsoldering
+SOT-353 SC-70-5 Handsoldering
+0
+5
+5
+Package_TO_SOT_SMD
+SOT-363_SC-70-6
+SOT-363, SC-70-6
+SOT-363 SC-70-6
+0
+6
+6
+Package_TO_SOT_SMD
+SOT-363_SC-70-6_Handsoldering
+SOT-363, SC-70-6, Handsoldering
+SOT-363 SC-70-6 Handsoldering
+0
+6
+6
+Package_TO_SOT_SMD
+SOT-383F
+8-pin SOT-383F, http://www.mouser.com/ds/2/80/CPDVR085V0C-HF-RevB-10783.pdf
+SOT-383F
+0
+9
+9
+Package_TO_SOT_SMD
+SOT-383FL
+8-pin SOT-383FL package, http://www.onsemi.com/pub_link/Collateral/ENA2267-D.PDF
+SOT-383FL
+0
+8
+8
+Package_TO_SOT_SMD
+SOT-416
+SOT-416, https://www.nxp.com/docs/en/package-information/SOT416.pdf
+SOT-416
+0
+3
+3
+Package_TO_SOT_SMD
+SOT-543
+SOT-543 4 lead surface package
+SOT-543 SC-107A EMD4
+0
+4
+4
+Package_TO_SOT_SMD
+SOT-553
+SOT553
+SOT-553
+0
+5
+5
+Package_TO_SOT_SMD
+SOT-563
+SOT563
+SOT-563
+0
+6
+6
+Package_TO_SOT_SMD
+SOT-665
+SOT665
+SOT-665
+0
+5
+5
+Package_TO_SOT_SMD
+SOT-666
+SOT666
+SOT-666
+0
+6
+6
+Package_TO_SOT_SMD
+SOT-723
+http://toshiba.semicon-storage.com/info/docget.jsp?did=5879&prodName=RN1104MFV
+sot 723
+0
+3
+3
+Package_TO_SOT_SMD
+SOT-883
+SOT-883, https://assets.nexperia.com/documents/outline-drawing/SOT883.pdf
+SOT-883
+0
+3
+3
+Package_TO_SOT_SMD
+SOT-886
+SOT-886
+SOT-886
+0
+6
+6
+Package_TO_SOT_SMD
+SOT-963
+SOT 963 6 pins package 1x0.8mm pitch 0.35mm
+SOT 963 6 pins package 1x0.8mm pitch 0.35mm
+0
+6
+6
+Package_TO_SOT_SMD
+SOT-1123
+SOT-1123 small outline transistor (see http://www.onsemi.com/pub/Collateral/NST3906F3-D.PDF)
+SOT-1123 transistor
+0
+3
+3
+Package_TO_SOT_SMD
+SOT-1333-1
+SOT-1333-1 
+SOT-1333-1 
+0
+9
+9
+Package_TO_SOT_SMD
+SOT-1334-1
+SOT-1334-1
+SOT-1334-1
+0
+14
+14
+Package_TO_SOT_SMD
+SuperSOT-3
+3-pin SuperSOT package https://www.fairchildsemi.com/package-drawings/MA/MA03B.pdf
+SuperSOT-3 SSOT-3
+0
+3
+3
+Package_TO_SOT_SMD
+SuperSOT-6
+6-pin SuperSOT package http://www.mouser.com/ds/2/149/FMB5551-889214.pdf
+SuperSOT-6 SSOT-6
+0
+6
+6
+Package_TO_SOT_SMD
+SuperSOT-8
+8-pin SuperSOT package, http://www.icbank.com/icbank_data/semi_package/ssot8_dim.pdf
+SuperSOT-8 SSOT-8
+0
+8
+8
+Package_TO_SOT_SMD
+TDSON-8-1
+Power MOSFET package, TDSON-8-1, 5.15x5.9mm (https://www.infineon.com/cms/en/product/packages/PG-TDSON/PG-TDSON-8-1/)
+tdson 
+0
+14
+5
+Package_TO_SOT_SMD
+TO-50-3_LongPad-NoHole_Housing
+TO-50-3 Macro T Package Style M236
+TO-50-3 Macro T Package Style M236
+0
+3
+3
+Package_TO_SOT_SMD
+TO-50-3_LongPad-WithHole_Housing
+TO-50-3 Macro T Package Style M236
+TO-50-3 Macro T Package Style M236
+0
+3
+3
+Package_TO_SOT_SMD
+TO-50-3_ShortPad-NoHole_Housing
+TO-50-3 Macro T Package Style M236
+TO-50-3 Macro T Package Style M236
+0
+3
+3
+Package_TO_SOT_SMD
+TO-50-3_ShortPad-WithHole_Housing
+TO-50-3 Macro T Package Style M236
+TO-50-3 Macro T Package Style M236
+0
+3
+3
+Package_TO_SOT_SMD
+TO-50-4_LongPad-NoHole_Housing
+TO-50-4 Macro X Package Style M238
+TO-50-4 Macro X Package Style M238
+0
+4
+4
+Package_TO_SOT_SMD
+TO-50-4_LongPad-WithHole_Housing
+TO-50-4 Macro X Package Style M238
+TO-50-4 Macro X Package Style M238
+0
+4
+4
+Package_TO_SOT_SMD
+TO-50-4_ShortPad-NoHole_Housing
+TO-50-4 Macro X Package Style M238
+TO-50-4 Macro X Package Style M238
+0
+4
+4
+Package_TO_SOT_SMD
+TO-50-4_ShortPad-WithHole_Housing
+TO-50-4 Macro X Package Style M238
+TO-50-4 Macro X Package Style M238
+0
+4
+4
+Package_TO_SOT_SMD
+TO-252-2
+TO-252 / DPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO252/PG-TO252-3-1/
+DPAK TO-252 DPAK-3 TO-252-3 SOT-428
+0
+7
+3
+Package_TO_SOT_SMD
+TO-252-2_TabPin1
+TO-252-2, tab to pin 1 https://www.wolfspeed.com/media/downloads/87/CSD01060.pdf
+TO-252-2 diode
+0
+7
+2
+Package_TO_SOT_SMD
+TO-252-3_TabPin2
+TO-252 / DPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO252/PG-TO252-3-1/
+DPAK TO-252 DPAK-3 TO-252-3 SOT-428
+0
+8
+3
+Package_TO_SOT_SMD
+TO-252-3_TabPin4
+TO-252 / DPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO252/PG-TO252-3-1/
+DPAK TO-252 DPAK-3 TO-252-3 SOT-428
+0
+8
+4
+Package_TO_SOT_SMD
+TO-252-4
+TO-252 / DPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO252/PG-TO252-5-11/
+DPAK TO-252 DPAK-5 TO-252-5
+0
+9
+5
+Package_TO_SOT_SMD
+TO-252-5_TabPin3
+TO-252 / DPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO252/PG-TO252-5-11/
+DPAK TO-252 DPAK-5 TO-252-5
+0
+10
+5
+Package_TO_SOT_SMD
+TO-252-5_TabPin6
+TO-252 / DPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO252/PG-TO252-5-11/
+DPAK TO-252 DPAK-5 TO-252-5
+0
+10
+6
+Package_TO_SOT_SMD
+TO-263-2
+TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-3-1/
+D2PAK DDPAK TO-263 D2PAK-3 TO-263-3 SOT-404
+0
+7
+3
+Package_TO_SOT_SMD
+TO-263-2_TabPin1
+TO-263 / D2PAK / DDPAK SMD package, tab to pin 1, https://www.wolfspeed.com/media/downloads/137/C3D06060G.pdf
+D2PAK DDPAK TO-263 D2PAK-3 TO-263-3 SOT-404 diode
+0
+7
+2
+Package_TO_SOT_SMD
+TO-263-3_TabPin2
+TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-3-1/
+D2PAK DDPAK TO-263 D2PAK-3 TO-263-3 SOT-404
+0
+8
+3
+Package_TO_SOT_SMD
+TO-263-3_TabPin4
+TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-3-1/
+D2PAK DDPAK TO-263 D2PAK-3 TO-263-3 SOT-404
+0
+8
+4
+Package_TO_SOT_SMD
+TO-263-4
+TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-5-1/
+D2PAK DDPAK TO-263 D2PAK-5 TO-263-5 SOT-426
+0
+9
+5
+Package_TO_SOT_SMD
+TO-263-5_TabPin3
+TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-5-1/
+D2PAK DDPAK TO-263 D2PAK-5 TO-263-5 SOT-426
+0
+10
+5
+Package_TO_SOT_SMD
+TO-263-5_TabPin6
+TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-5-1/
+D2PAK DDPAK TO-263 D2PAK-5 TO-263-5 SOT-426
+0
+10
+6
+Package_TO_SOT_SMD
+TO-263-6
+TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-7-1/
+D2PAK DDPAK TO-263 D2PAK-7 TO-263-7 SOT-427
+0
+11
+7
+Package_TO_SOT_SMD
+TO-263-7_TabPin4
+TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-7-1/
+D2PAK DDPAK TO-263 D2PAK-7 TO-263-7 SOT-427
+0
+12
+7
+Package_TO_SOT_SMD
+TO-263-7_TabPin8
+TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-7-1/
+D2PAK DDPAK TO-263 D2PAK-7 TO-263-7 SOT-427
+0
+12
+8
+Package_TO_SOT_SMD
+TO-263-9_TabPin5
+TO-263 / D2PAK / DDPAK SMD package, http://www.ti.com/lit/ds/symlink/lm4755.pdf
+D2PAK DDPAK TO-263 D2PAK-9 TO-263-9
+0
+14
+9
+Package_TO_SOT_SMD
+TO-263-9_TabPin10
+TO-263 / D2PAK / DDPAK SMD package, http://www.ti.com/lit/ds/symlink/lm4755.pdf
+D2PAK DDPAK TO-263 D2PAK-9 TO-263-9
+0
+14
+10
+Package_TO_SOT_SMD
+TO-268-2
+TO-268/D3PAK SMD package, http://www.icbank.com/icbank_data/semi_package/to268aa_dim.pdf
+D3PAK TO-268 D3PAK-3 TO-268-3
+0
+7
+3
+Package_TO_SOT_SMD
+TO-269AA
+SMD package TO-269AA (e.g. diode bridge), see http://www.vishay.com/docs/88854/padlayouts.pdf
+TO-269AA MBS diode bridge
+0
+4
+4
+Package_TO_SOT_SMD
+TO-277A
+Thermal enhanced ultra thin SMD package; 3 leads; body: 4.3x6.1x0.43mm, https://www.vishay.com/docs/95570/to-277asmpc.pdf
+TO-277A SMPC
+0
+12
+3
+Package_TO_SOT_SMD
+TO-277B
+TO-227B https://media.digikey.com/pdf/Data%20Sheets/Littelfuse%20PDFs/DST2050S.pdf
+TO-277B
+0
+9
+3
+Package_TO_SOT_SMD
+TSOT-23
+3-pin TSOT23 package, http://www.analog.com.tw/pdf/All_In_One.pdf
+TSOT-23
+0
+3
+3
+Package_TO_SOT_SMD
+TSOT-23-5
+5-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_5_05-08-1635.pdf
+TSOT-23-5
+0
+5
+5
+Package_TO_SOT_SMD
+TSOT-23-5_HandSoldering
+5-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_5_05-08-1635.pdf
+TSOT-23-5 Hand-soldering
+0
+5
+5
+Package_TO_SOT_SMD
+TSOT-23-6
+6-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_6_05-08-1636.pdf
+TSOT-23-6 MK06A TSOT-6
+0
+6
+6
+Package_TO_SOT_SMD
+TSOT-23-6_HandSoldering
+6-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_6_05-08-1636.pdf
+TSOT-23-6 MK06A TSOT-6 Hand-soldering
+0
+6
+6
+Package_TO_SOT_SMD
+TSOT-23-8
+8-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_8_05-08-1637.pdf
+TSOT-23-8
+0
+8
+8
+Package_TO_SOT_SMD
+TSOT-23-8_HandSoldering
+8-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_8_05-08-1637.pdf
+TSOT-23-8 Hand-soldering
+0
+8
+8
+Package_TO_SOT_SMD
+TSOT-23_HandSoldering
+5-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_5_05-08-1635.pdf
+TSOT-23 Hand-soldering
+0
+3
+3
+Package_TO_SOT_SMD
+Texas_DRT-3
+Texas Instrument DRT-3 1x0.8mm Pitch 0.7mm http://www.ti.com/lit/ds/symlink/tpd2eusb30.pdf
+DRT-3 1x0.8mm Pitch 0.7mm
+0
+3
+3
+Package_TO_SOT_SMD
+Texas_NDY0011A
+TO-PMOD-11 11-pin switching regulator package, http://www.ti.com/lit/ml/mmsf025/mmsf025.pdf
+Texas TO-PMOD NDY00011A
+0
+12
+12
+Package_TO_SOT_SMD
+Texas_R-PDSO-G6
+R-PDSO-G6, http://www.ti.com/lit/ds/slis144b/slis144b.pdf
+R-PDSO-G6 SC-70-6
+0
+6
+6
+Package_TO_SOT_SMD
+VSOF5
+VSOF5
+VSOF5
+0
+5
+5
+Package_TO_SOT_SMD
+Vishay_PowerPAK_SC70-6L_Dual
+Vishay PowerPAK SC70 dual transistor package http://www.vishay.com/docs/70487/70487.pdf
+powerpak sc70 sc-70 dual
+0
+8
+6
+Package_TO_SOT_SMD
+Vishay_PowerPAK_SC70-6L_Single
+Vishay PowerPAK SC70 single transistor package http://www.vishay.com/docs/70486/70486.pdf
+powerpak sc70 sc-70
+0
+6
+3
+Package_TO_SOT_THT
+Fairchild_TO-220F-6L
+Fairchild TO-220F-6L, http://www.mouser.com/ds/2/149/FSL136MRT-113334.pdf
+Fairchild TO-220F-6L
+0
+6
+6
+Package_TO_SOT_THT
+Heraeus_TO-92-2
+TO-92 2-pin variant by Heraeus, drill 0.75mm (http://www.produktinfo.conrad.com/datenblaetter/175000-199999/181293-da-01-de-TO92_Temperatursensor_PT1000_32209225.pdf)
+to-92 
+0
+2
+2
+Package_TO_SOT_THT
+NEC_Molded_7x4x9mm
+Molded Japan Transistor Package 7x4x9mm^3, http://rtellason.com/transdata/2sb734.pdf
+Japan transistor
+0
+3
+3
+Package_TO_SOT_THT
+PowerIntegrations_TO-220-7C
+Non Isolated Modified TO-220 7pin Package, see http://www.farnell.com/datasheets/5793.pdf
+Power Integration Y Package
+0
+6
+6
+Package_TO_SOT_THT
+SIPAK-1EP_Horizontal_TabDown
+SIPAK, Horizontal, RM 2.286mm
+SIPAK Horizontal RM 2.286mm
+0
+4
+4
+Package_TO_SOT_THT
+SIPAK_Vertical
+SIPAK, Vertical, RM 2.286mm
+SIPAK Vertical RM 2.286mm
+0
+3
+3
+Package_TO_SOT_THT
+SOD-70_P2.54mm
+Plastic near cylindrical package Sod-70 see: https://www.nxp.com/docs/en/data-sheet/KTY81_SER.pdf  [StepUp generated footprint]
+Sod-70
+0
+2
+2
+Package_TO_SOT_THT
+SOD-70_P5.08mm
+Plastic near cylindrical package Sod-70 see: https://www.nxp.com/docs/en/data-sheet/KTY81_SER.pdf  [StepUp generated footprint]
+Sod-70
+0
+2
+2
+Package_TO_SOT_THT
+SOT-227
+SOT-227 / SOT-227B / ISOTOP, M4 mounting screws (https://www.vishay.com/docs/95423/sot227g2.pdf, https://www.vishay.com/docs/95793/vs-fc420sa10.pdf)
+sot 227 isotop
+0
+8
+4
+Package_TO_SOT_THT
+TO-3
+Transistor TO-3
+TR TO-3 TO3 TO-204
+0
+4
+3
+Package_TO_SOT_THT
+TO-3P-3_Horizontal_TabDown
+TO-3P-3, Horizontal, RM 5.45mm, , see https://toshiba.semicon-storage.com/ap-en/design-support/package/detail.TO-3P(N).html
+TO-3P-3 Horizontal RM 5.45mm 
+0
+3
+3
+Package_TO_SOT_THT
+TO-3P-3_Horizontal_TabUp
+TO-3P-3, Horizontal, RM 5.45mm, , see https://toshiba.semicon-storage.com/ap-en/design-support/package/detail.TO-3P(N).html
+TO-3P-3 Horizontal RM 5.45mm 
+0
+3
+3
+Package_TO_SOT_THT
+TO-3P-3_Vertical
+TO-3P-3, Vertical, RM 5.45mm, , see https://toshiba.semicon-storage.com/ap-en/design-support/package/detail.TO-3P(N).html
+TO-3P-3 Vertical RM 5.45mm 
+0
+3
+3
+Package_TO_SOT_THT
+TO-3PB-3_Horizontal_TabDown
+TO-3PB-3, Horizontal, RM 5.45mm, , see http://www.onsemi.com/pub/Collateral/340AC.PDF
+TO-3PB-3 Horizontal RM 5.45mm 
+0
+3
+3
+Package_TO_SOT_THT
+TO-3PB-3_Horizontal_TabUp
+TO-3PB-3, Horizontal, RM 5.45mm, , see http://www.onsemi.com/pub/Collateral/340AC.PDF
+TO-3PB-3 Horizontal RM 5.45mm 
+0
+3
+3
+Package_TO_SOT_THT
+TO-3PB-3_Vertical
+TO-3PB-3, Vertical, RM 5.45mm, , see http://www.onsemi.com/pub/Collateral/340AC.PDF
+TO-3PB-3 Vertical RM 5.45mm 
+0
+3
+3
+Package_TO_SOT_THT
+TO-5-2
+TO-5-2
+TO-5-2
+0
+2
+2
+Package_TO_SOT_THT
+TO-5-2_Window
+TO-5-2_Window, Window
+TO-5-2_Window Window
+0
+2
+2
+Package_TO_SOT_THT
+TO-5-3
+TO-5-3
+TO-5-3
+0
+3
+3
+Package_TO_SOT_THT
+TO-5-3_Window
+TO-5-3_Window, Window
+TO-5-3_Window Window
+0
+3
+3
+Package_TO_SOT_THT
+TO-5-4
+TO-5-4
+TO-5-4
+0
+4
+4
+Package_TO_SOT_THT
+TO-5-4_Window
+TO-5-4_Window, Window
+TO-5-4_Window Window
+0
+4
+4
+Package_TO_SOT_THT
+TO-5-6
+TO-5-6
+TO-5-6
+0
+6
+6
+Package_TO_SOT_THT
+TO-5-6_Window
+TO-5-6_Window, Window
+TO-5-6_Window Window
+0
+6
+6
+Package_TO_SOT_THT
+TO-5-8
+TO-5-8
+TO-5-8
+0
+8
+8
+Package_TO_SOT_THT
+TO-5-8_PD5.08
+TO-5-8_PD5.08
+TO-5-8_PD5.08
+0
+8
+8
+Package_TO_SOT_THT
+TO-5-8_PD5.08_Window
+TO-5-8_PD5.08_Window, Window
+TO-5-8_PD5.08_Window Window
+0
+8
+8
+Package_TO_SOT_THT
+TO-5-8_Window
+TO-5-8_Window, Window
+TO-5-8_Window Window
+0
+8
+8
+Package_TO_SOT_THT
+TO-5-10
+TO-5-10
+TO-5-10
+0
+10
+10
+Package_TO_SOT_THT
+TO-5-10_Window
+TO-5-10_Window, Window
+TO-5-10_Window Window
+0
+10
+10
+Package_TO_SOT_THT
+TO-8-2
+TO-8-2
+TO-8-2
+0
+2
+2
+Package_TO_SOT_THT
+TO-8-2_Window
+TO-8-2_Window, Window
+TO-8-2_Window Window
+0
+2
+2
+Package_TO_SOT_THT
+TO-8-3
+TO-8-3
+TO-8-3
+0
+3
+3
+Package_TO_SOT_THT
+TO-8-3_Window
+TO-8-3_Window, Window
+TO-8-3_Window Window
+0
+3
+3
+Package_TO_SOT_THT
+TO-11-2
+TO-11-2
+TO-11-2
+0
+2
+2
+Package_TO_SOT_THT
+TO-11-2_Window
+TO-11-2_Window, Window
+TO-11-2_Window Window
+0
+2
+2
+Package_TO_SOT_THT
+TO-11-3
+TO-11-3
+TO-11-3
+0
+3
+3
+Package_TO_SOT_THT
+TO-11-3_Window
+TO-11-3_Window, Window
+TO-11-3_Window Window
+0
+3
+3
+Package_TO_SOT_THT
+TO-12-4
+TO-12-4
+TO-12-4
+0
+4
+4
+Package_TO_SOT_THT
+TO-12-4_Window
+TO-12-4_Window, Window
+TO-12-4_Window Window
+0
+4
+4
+Package_TO_SOT_THT
+TO-17-4
+TO-17-4
+TO-17-4
+0
+4
+4
+Package_TO_SOT_THT
+TO-17-4_Window
+TO-17-4_Window, Window
+TO-17-4_Window Window
+0
+4
+4
+Package_TO_SOT_THT
+TO-18-2
+TO-18-2
+TO-18-2
+0
+2
+2
+Package_TO_SOT_THT
+TO-18-2_Lens
+TO-18-2_Lens, Lens
+TO-18-2_Lens Lens
+0
+2
+2
+Package_TO_SOT_THT
+TO-18-2_Window
+TO-18-2_Window, Window
+TO-18-2_Window Window
+0
+2
+2
+Package_TO_SOT_THT
+TO-18-3
+TO-18-3
+TO-18-3
+0
+3
+3
+Package_TO_SOT_THT
+TO-18-3_Lens
+TO-18-3_Lens, Lens
+TO-18-3_Lens Lens
+0
+3
+3
+Package_TO_SOT_THT
+TO-18-3_Window
+TO-18-3_Window, Window
+TO-18-3_Window Window
+0
+3
+3
+Package_TO_SOT_THT
+TO-18-4
+TO-18-4
+TO-18-4
+0
+4
+4
+Package_TO_SOT_THT
+TO-18-4_Lens
+TO-18-4_Lens, Lens
+TO-18-4_Lens Lens
+0
+4
+4
+Package_TO_SOT_THT
+TO-18-4_Window
+TO-18-4_Window, Window
+TO-18-4_Window Window
+0
+4
+4
+Package_TO_SOT_THT
+TO-33-4
+TO-33-4
+TO-33-4
+0
+4
+4
+Package_TO_SOT_THT
+TO-33-4_Window
+TO-33-4_Window, Window
+TO-33-4_Window Window
+0
+4
+4
+Package_TO_SOT_THT
+TO-38-2
+TO-38-2
+TO-38-2
+0
+2
+2
+Package_TO_SOT_THT
+TO-38-2_Window
+TO-38-2_Window, Window
+TO-38-2_Window Window
+0
+2
+2
+Package_TO_SOT_THT
+TO-38-3
+TO-38-3
+TO-38-3
+0
+3
+3
+Package_TO_SOT_THT
+TO-38-3_Window
+TO-38-3_Window, Window
+TO-38-3_Window Window
+0
+3
+3
+Package_TO_SOT_THT
+TO-39-2
+TO-39-2
+TO-39-2
+0
+2
+2
+Package_TO_SOT_THT
+TO-39-2_Window
+TO-39-2_Window, Window
+TO-39-2_Window Window
+0
+2
+2
+Package_TO_SOT_THT
+TO-39-3
+TO-39-3
+TO-39-3
+0
+3
+3
+Package_TO_SOT_THT
+TO-39-3_Window
+TO-39-3_Window, Window
+TO-39-3_Window Window
+0
+3
+3
+Package_TO_SOT_THT
+TO-39-4
+TO-39-4
+TO-39-4
+0
+4
+4
+Package_TO_SOT_THT
+TO-39-4_Window
+TO-39-4_Window, Window
+TO-39-4_Window Window
+0
+4
+4
+Package_TO_SOT_THT
+TO-39-6
+TO-39-6
+TO-39-6
+0
+6
+6
+Package_TO_SOT_THT
+TO-39-6_Window
+TO-39-6_Window, Window
+TO-39-6_Window Window
+0
+6
+6
+Package_TO_SOT_THT
+TO-39-8
+TO-39-8
+TO-39-8
+0
+8
+8
+Package_TO_SOT_THT
+TO-39-8_Window
+TO-39-8_Window, Window
+TO-39-8_Window Window
+0
+8
+8
+Package_TO_SOT_THT
+TO-39-10
+TO-39-10
+TO-39-10
+0
+10
+10
+Package_TO_SOT_THT
+TO-39-10_Window
+TO-39-10_Window, Window
+TO-39-10_Window Window
+0
+10
+10
+Package_TO_SOT_THT
+TO-46-2
+TO-46-2
+TO-46-2
+0
+2
+2
+Package_TO_SOT_THT
+TO-46-2_Pin2Center
+TO-46-2, Pin2 at center of package, Thorlabs photodiodes
+TO-46-2 Thorlabs
+0
+2
+2
+Package_TO_SOT_THT
+TO-46-2_Pin2Center_Window
+TO-46-2, Pin2 at center of package, Thorlabs photodiodes
+TO-46-2 Thorlabs
+0
+2
+2
+Package_TO_SOT_THT
+TO-46-2_Window
+TO-46-2_Window, Window
+TO-46-2_Window Window
+0
+2
+2
+Package_TO_SOT_THT
+TO-46-3
+TO-46-3
+TO-46-3
+0
+3
+3
+Package_TO_SOT_THT
+TO-46-3_Pin2Center
+TO-46-3, Pin2 at center of package, Thorlabs photodiodes, https://www.thorlabs.de/drawings/374b6862eb3b5a04-9360B5F6-5056-2306-D912111C06C3F830/FDGA05-SpecSheet.pdf
+TO-46-3 Thorlabs
+0
+3
+3
+Package_TO_SOT_THT
+TO-46-3_Pin2Center_Window
+TO-46-3, Pin2 at center of package, Thorlabs photodiodes, https://www.thorlabs.de/drawings/374b6862eb3b5a04-9360B5F6-5056-2306-D912111C06C3F830/FDGA05-SpecSheet.pdf
+TO-46-3 Thorlabs
+0
+3
+3
+Package_TO_SOT_THT
+TO-46-3_Window
+TO-46-3_Window, Window
+TO-46-3_Window Window
+0
+3
+3
+Package_TO_SOT_THT
+TO-46-4
+TO-46-4
+TO-46-4
+0
+4
+4
+Package_TO_SOT_THT
+TO-46-4_Window
+TO-46-4_Window, Window
+TO-46-4_Window Window
+0
+4
+4
+Package_TO_SOT_THT
+TO-52-2
+TO-52-2
+TO-52-2
+0
+2
+2
+Package_TO_SOT_THT
+TO-52-2_Window
+TO-52-2_Window, Window
+TO-52-2_Window Window
+0
+2
+2
+Package_TO_SOT_THT
+TO-52-3
+TO-52-3
+TO-52-3
+0
+3
+3
+Package_TO_SOT_THT
+TO-52-3_Window
+TO-52-3_Window, Window
+TO-52-3_Window Window
+0
+3
+3
+Package_TO_SOT_THT
+TO-72-4
+TO-72-4
+TO-72-4
+0
+4
+4
+Package_TO_SOT_THT
+TO-72-4_Window
+TO-72-4_Window, Window
+TO-72-4_Window Window
+0
+4
+4
+Package_TO_SOT_THT
+TO-75-6
+TO-75-6
+TO-75-6
+0
+6
+6
+Package_TO_SOT_THT
+TO-75-6_Window
+TO-75-6_Window, Window
+TO-75-6_Window Window
+0
+6
+6
+Package_TO_SOT_THT
+TO-78-6
+TO-78-6
+TO-78-6
+0
+6
+6
+Package_TO_SOT_THT
+TO-78-6_Window
+TO-78-6_Window, Window
+TO-78-6_Window Window
+0
+6
+6
+Package_TO_SOT_THT
+TO-78-8
+TO-78-8
+TO-78-8
+0
+8
+8
+Package_TO_SOT_THT
+TO-78-8_Window
+TO-78-8_Window, Window
+TO-78-8_Window Window
+0
+8
+8
+Package_TO_SOT_THT
+TO-78-10
+TO-78-10
+TO-78-10
+0
+10
+10
+Package_TO_SOT_THT
+TO-78-10_Window
+TO-78-10_Window, Window
+TO-78-10_Window Window
+0
+10
+10
+Package_TO_SOT_THT
+TO-92
+TO-92 leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf)
+to-92 sc-43 sc-43a sot54 PA33 transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92-2
+TO-92 2-pin leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf)
+to-92 sc-43 sc-43a sot54 PA33 diode SOD70
+0
+2
+2
+Package_TO_SOT_THT
+TO-92-2_Horizontal1
+2-pin TO-92 horizontal, leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf)
+to-92 sc-43 sc-43a sot54 PA33 temperature sensor diode
+0
+2
+2
+Package_TO_SOT_THT
+TO-92-2_Horizontal2
+2-pin TO-92 horizontal, leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf)
+to-92 sc-43 sc-43a sot54 PA33 temperature sensor diode
+0
+2
+2
+Package_TO_SOT_THT
+TO-92-2_W4.0mm_Horizontal_FlatSideDown
+TO-92 horizontal, leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf)
+to-92 sc-43 sc-43a sot54 PA33 transistor
+0
+2
+2
+Package_TO_SOT_THT
+TO-92-2_W4.0mm_Horizontal_FlatSideUp
+TO-92 horizontal, leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf)
+to-92 sc-43 sc-43a sot54 PA33 transistor
+0
+2
+2
+Package_TO_SOT_THT
+TO-92-2_Wide
+TO-92 2-pin leads in-line, wide, drill 0.75mm
+to-92 sc-43 sc-43a sot54 PA33 diode SOD70
+0
+2
+2
+Package_TO_SOT_THT
+TO-92Flat
+TO-92Flat package, often used for hall sensors, drill 0.75mm (see e.g. http://www.ti.com/lit/ds/symlink/drv5023.pdf)
+to-92Flat hall sensor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92L
+TO-92L leads in-line (large body variant of TO-92), also known as TO-226, wide, drill 0.75mm (see https://www.diodes.com/assets/Package-Files/TO92L.pdf and http://www.ti.com/lit/an/snoa059/snoa059.pdf)
+TO-92L Molded Narrow transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92L_HandSolder
+TO-92L leads in-line (large body variant of TO-92), also known as TO-226, wide, drill 0.75mm, hand-soldering variant with enlarged pads (see https://www.diodes.com/assets/Package-Files/TO92L.pdf and http://www.ti.com/lit/an/snoa059/snoa059.pdf)
+to-92 sc-43 sc-43a sot54 PA33 transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92L_Inline
+TO-92L leads in-line (large body variant of TO-92), also known as TO-226, wide, drill 0.75mm (see https://www.diodes.com/assets/Package-Files/TO92L.pdf and http://www.ti.com/lit/an/snoa059/snoa059.pdf)
+TO-92L Inline Wide transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92L_Inline_Wide
+TO-92L leads in-line (large body variant of TO-92), also known as TO-226, wide, drill 0.75mm (see https://www.diodes.com/assets/Package-Files/TO92L.pdf and http://www.ti.com/lit/an/snoa059/snoa059.pdf)
+TO-92L Inline Wide transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92L_Wide
+TO-92L leads in-line (large body variant of TO-92), also known as TO-226, wide, drill 0.75mm (see https://www.diodes.com/assets/Package-Files/TO92L.pdf and http://www.ti.com/lit/an/snoa059/snoa059.pdf)
+TO-92L Molded Wide transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92Mini-2
+TO-92Mini package, drill 0.6mm (https://media.digikey.com/pdf/Data%20Sheets/Infineon%20PDFs/KT,KTY.pdf)
+to-92Mini transistor 
+0
+2
+2
+Package_TO_SOT_THT
+TO-92S
+TO-92S package, drill 0.75mm (https://www.diodes.com/assets/Package-Files/TO92S%20(Type%20B).pdf)
+to-92S transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92S-2
+TO-92S package, 2-pin, drill 0.75mm (https://www.diodes.com/assets/Package-Files/TO92S%20(Type%20B).pdf)
+to-92S transistor
+0
+2
+2
+Package_TO_SOT_THT
+TO-92S_Wide
+TO-92S_Wide package, drill 0.75mm (https://www.diodes.com/assets/Package-Files/TO92S%20(Type%20B).pdf)
+TO-92S_Wide transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92_HandSolder
+TO-92 leads molded, narrow, drill 0.75mm, handsoldering variant with enlarged pads (see NXP sot054_po.pdf)
+to-92 sc-43 sc-43a sot54 PA33 transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92_Horizontal1
+TO-92 horizontal, leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf)
+to-92 sc-43 sc-43a sot54 PA33 transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92_Horizontal2
+TO-92 horizontal, leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf)
+to-92 sc-43 sc-43a sot54 PA33 transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92_Inline
+TO-92 leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf)
+to-92 sc-43 sc-43a sot54 PA33 transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92_Inline_Horizontal1
+TO-92 horizontal, leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf)
+to-92 sc-43 sc-43a sot54 PA33 transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92_Inline_Horizontal2
+TO-92 horizontal, leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf)
+to-92 sc-43 sc-43a sot54 PA33 transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92_Inline_W4.0mm_Horizontal_FlatSideDown
+TO-92 horizontal, leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf)
+to-92 sc-43 sc-43a sot54 PA33 transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92_Inline_W4.0mm_Horizontal_FlatSideUp
+TO-92 horizontal, leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf)
+to-92 sc-43 sc-43a sot54 PA33 transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92_Inline_Wide
+TO-92 leads in-line, wide, drill 0.75mm (see NXP sot054_po.pdf)
+to-92 sc-43 sc-43a sot54 PA33 transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92_W4.0mm_StaggerEven_Horizontal_FlatSideDown
+TO-92 horizontal, leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf)
+to-92 sc-43 sc-43a sot54 PA33 transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92_W4.0mm_StaggerEven_Horizontal_FlatSideUp
+TO-92 horizontal, leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf)
+to-92 sc-43 sc-43a sot54 PA33 transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-92_Wide
+TO-92 leads molded, wide, drill 0.75mm (see NXP sot054_po.pdf)
+to-92 sc-43 sc-43a sot54 PA33 transistor
+0
+3
+3
+Package_TO_SOT_THT
+TO-99-6
+TO-99-6
+TO-99-6
+0
+6
+6
+Package_TO_SOT_THT
+TO-99-6_Window
+TO-99-6_Window, Window
+TO-99-6_Window Window
+0
+6
+6
+Package_TO_SOT_THT
+TO-99-8
+TO-99-8
+TO-99-8
+0
+8
+8
+Package_TO_SOT_THT
+TO-99-8_Window
+TO-99-8_Window, Window
+TO-99-8_Window Window
+0
+8
+8
+Package_TO_SOT_THT
+TO-100-10
+TO-100-10
+TO-100-10
+0
+10
+10
+Package_TO_SOT_THT
+TO-100-10_Window
+TO-100-10_Window, Window
+TO-100-10_Window Window
+0
+10
+10
+Package_TO_SOT_THT
+TO-126-2_Horizontal_TabDown
+TO-126-2, Horizontal, RM 5.08mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf
+TO-126-2 Horizontal RM 5.08mm
+0
+2
+2
+Package_TO_SOT_THT
+TO-126-2_Horizontal_TabUp
+TO-126-2, Horizontal, RM 5.08mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf
+TO-126-2 Horizontal RM 5.08mm
+0
+2
+2
+Package_TO_SOT_THT
+TO-126-2_Vertical
+TO-126-2, Vertical, RM 5.08mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf
+TO-126-2 Vertical RM 5.08mm
+0
+2
+2
+Package_TO_SOT_THT
+TO-126-3_Horizontal_TabDown
+TO-126-3, Horizontal, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf
+TO-126-3 Horizontal RM 2.54mm
+0
+3
+3
+Package_TO_SOT_THT
+TO-126-3_Horizontal_TabUp
+TO-126-3, Horizontal, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf
+TO-126-3 Horizontal RM 2.54mm
+0
+3
+3
+Package_TO_SOT_THT
+TO-126-3_Vertical
+TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf
+TO-126-3 Vertical RM 2.54mm
+0
+3
+3
+Package_TO_SOT_THT
+TO-218-2_Horizontal_TabDown
+TO-218-2, Horizontal, RM 10.95mm, SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf
+TO-218-2 Horizontal RM 10.95mm SOT-93
+0
+2
+2
+Package_TO_SOT_THT
+TO-218-2_Horizontal_TabUp
+TO-218-2, Horizontal, RM 10.95mm, SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf
+TO-218-2 Horizontal RM 10.95mm SOT-93
+0
+2
+2
+Package_TO_SOT_THT
+TO-218-2_Vertical
+TO-218-2, Vertical, RM 10.95mm, SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf
+TO-218-2 Vertical RM 10.95mm SOT-93
+0
+2
+2
+Package_TO_SOT_THT
+TO-218-3_Horizontal_TabDown
+TO-218-3, Horizontal, RM 5.475mm, SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf
+TO-218-3 Horizontal RM 5.475mm SOT-93
+0
+3
+3
+Package_TO_SOT_THT
+TO-218-3_Horizontal_TabUp
+TO-218-3, Horizontal, RM 5.475mm, SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf
+TO-218-3 Horizontal RM 5.475mm SOT-93
+0
+3
+3
+Package_TO_SOT_THT
+TO-218-3_Vertical
+TO-218-3, Vertical, RM 5.475mm, SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf
+TO-218-3 Vertical RM 5.475mm SOT-93
+0
+3
+3
+Package_TO_SOT_THT
+TO-220-2_Horizontal_TabDown
+TO-220-2, Horizontal, RM 5.08mm, see https://www.centralsemi.com/PDFS/CASE/TO-220-2PD.PDF
+TO-220-2 Horizontal RM 5.08mm
+0
+2
+2
+Package_TO_SOT_THT
+TO-220-2_Horizontal_TabUp
+TO-220-2, Horizontal, RM 5.08mm, see https://www.centralsemi.com/PDFS/CASE/TO-220-2PD.PDF
+TO-220-2 Horizontal RM 5.08mm
+0
+2
+2
+Package_TO_SOT_THT
+TO-220-2_Vertical
+TO-220-2, Vertical, RM 5.08mm, see https://www.centralsemi.com/PDFS/CASE/TO-220-2PD.PDF
+TO-220-2 Vertical RM 5.08mm
+0
+2
+2
+Package_TO_SOT_THT
+TO-220-3_Horizontal_TabDown
+TO-220-3, Horizontal, RM 2.54mm, see https://www.vishay.com/docs/66542/to-220-1.pdf
+TO-220-3 Horizontal RM 2.54mm
+0
+3
+3
+Package_TO_SOT_THT
+TO-220-3_Horizontal_TabUp
+TO-220-3, Horizontal, RM 2.54mm, see https://www.vishay.com/docs/66542/to-220-1.pdf
+TO-220-3 Horizontal RM 2.54mm
+0
+3
+3
+Package_TO_SOT_THT
+TO-220-3_Vertical
+TO-220-3, Vertical, RM 2.54mm, see https://www.vishay.com/docs/66542/to-220-1.pdf
+TO-220-3 Vertical RM 2.54mm
+0
+3
+3
+Package_TO_SOT_THT
+TO-220-4_Horizontal_TabDown
+TO-220-4, Horizontal, RM 2.54mm
+TO-220-4 Horizontal RM 2.54mm
+0
+4
+4
+Package_TO_SOT_THT
+TO-220-4_Horizontal_TabUp
+TO-220-4, Horizontal, RM 2.54mm
+TO-220-4 Horizontal RM 2.54mm
+0
+4
+4
+Package_TO_SOT_THT
+TO-220-4_P5.08x2.54mm_StaggerEven_Lead3.8mm_Vertical
+TO-220-4, Vertical, RM 2.54mm, staggered type-2
+TO-220-4 Vertical RM 2.54mm staggered type-2
+0
+4
+4
+Package_TO_SOT_THT
+TO-220-4_P5.08x2.54mm_StaggerEven_Lead5.84mm_TabDown
+TO-220-4, Horizontal, RM 2.54mm, staggered type-2
+TO-220-4 Horizontal RM 2.54mm staggered type-2
+0
+4
+4
+Package_TO_SOT_THT
+TO-220-4_P5.08x2.54mm_StaggerOdd_Lead3.8mm_Vertical
+TO-220-4, Vertical, RM 2.54mm, staggered type-1
+TO-220-4 Vertical RM 2.54mm staggered type-1
+0
+4
+4
+Package_TO_SOT_THT
+TO-220-4_P5.08x2.54mm_StaggerOdd_Lead5.84mm_TabDown
+TO-220-4, Horizontal, RM 2.54mm, staggered type-1
+TO-220-4 Horizontal RM 2.54mm staggered type-1
+0
+4
+4
+Package_TO_SOT_THT
+TO-220-4_Vertical
+TO-220-4, Vertical, RM 2.54mm
+TO-220-4 Vertical RM 2.54mm
+0
+4
+4
+Package_TO_SOT_THT
+TO-220-5_Horizontal_TabDown
+TO-220-5, Horizontal, RM 1.7mm, Pentawatt, Multiwatt-5, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421_straight_lead.pdf
+TO-220-5 Horizontal RM 1.7mm Pentawatt Multiwatt-5
+0
+5
+5
+Package_TO_SOT_THT
+TO-220-5_Horizontal_TabUp
+TO-220-5, Horizontal, RM 1.7mm, Pentawatt, Multiwatt-5, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421_straight_lead.pdf
+TO-220-5 Horizontal RM 1.7mm Pentawatt Multiwatt-5
+0
+5
+5
+Package_TO_SOT_THT
+TO-220-5_P3.4x3.7mm_StaggerEven_Lead3.8mm_Vertical
+TO-220-5, Vertical, RM 1.7mm, Pentawatt, Multiwatt-5, staggered type-2, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421.pdf?domain=www.linear.com, https://www.diodes.com/assets/Package-Files/TO220-5.pdf
+TO-220-5 Vertical RM 1.7mm Pentawatt Multiwatt-5 staggered type-2
+0
+5
+5
+Package_TO_SOT_THT
+TO-220-5_P3.4x3.7mm_StaggerOdd_Lead3.8mm_Vertical
+TO-220-5, Vertical, RM 1.7mm, Pentawatt, Multiwatt-5, staggered type-1, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421.pdf?domain=www.linear.com, https://www.diodes.com/assets/Package-Files/TO220-5.pdf
+TO-220-5 Vertical RM 1.7mm Pentawatt Multiwatt-5 staggered type-1
+0
+5
+5
+Package_TO_SOT_THT
+TO-220-5_P3.4x3.8mm_StaggerEven_Lead7.13mm_TabDown
+TO-220-5, Horizontal, RM 1.7mm, Pentawatt, Multiwatt-5, staggered type-2, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421.pdf?domain=www.linear.com, https://www.diodes.com/assets/Package-Files/TO220-5.pdf
+TO-220-5 Horizontal RM 1.7mm Pentawatt Multiwatt-5 staggered type-2
+0
+5
+5
+Package_TO_SOT_THT
+TO-220-5_P3.4x3.8mm_StaggerOdd_Lead7.13mm_TabDown
+TO-220-5, Horizontal, RM 1.7mm, Pentawatt, Multiwatt-5, staggered type-1, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421.pdf?domain=www.linear.com, https://www.diodes.com/assets/Package-Files/TO220-5.pdf
+TO-220-5 Horizontal RM 1.7mm Pentawatt Multiwatt-5 staggered type-1
+0
+5
+5
+Package_TO_SOT_THT
+TO-220-5_Vertical
+TO-220-5, Vertical, RM 1.7mm, Pentawatt, Multiwatt-5, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421_straight_lead.pdf
+TO-220-5 Vertical RM 1.7mm Pentawatt Multiwatt-5
+0
+5
+5
+Package_TO_SOT_THT
+TO-220-7_P2.54x3.7mm_StaggerEven_Lead3.8mm_Vertical
+TO-220-7, Vertical, RM 1.27mm, Multiwatt-7, staggered type-2
+TO-220-7 Vertical RM 1.27mm Multiwatt-7 staggered type-2
+0
+7
+7
+Package_TO_SOT_THT
+TO-220-7_P2.54x3.7mm_StaggerOdd_Lead3.8mm_Vertical
+TO-220-7, Vertical, RM 1.27mm, Multiwatt-7, staggered type-1
+TO-220-7 Vertical RM 1.27mm Multiwatt-7 staggered type-1
+0
+7
+7
+Package_TO_SOT_THT
+TO-220-7_P2.54x3.8mm_StaggerEven_Lead5.85mm_TabDown
+TO-220-7, Horizontal, RM 1.27mm, Multiwatt-7, staggered type-2
+TO-220-7 Horizontal RM 1.27mm Multiwatt-7 staggered type-2
+0
+7
+7
+Package_TO_SOT_THT
+TO-220-7_P2.54x3.8mm_StaggerOdd_Lead5.85mm_TabDown
+TO-220-7, Horizontal, RM 1.27mm, Multiwatt-7, staggered type-1
+TO-220-7 Horizontal RM 1.27mm Multiwatt-7 staggered type-1
+0
+7
+7
+Package_TO_SOT_THT
+TO-220-8_Vertical
+TO-220-8 (Multiwatt8), Vertical, 2.54mm Pitch (http://www.st.com/resource/en/datasheet/tda7264.pdf)
+TO-220-9 Vertical 2.54mm Pitch Multiwatt 8
+0
+8
+8
+Package_TO_SOT_THT
+TO-220-9_P1.94x3.7mm_StaggerEven_Lead3.8mm_Vertical
+TO-220-9, Vertical, RM 0.97mm, Multiwatt-9, staggered type-2
+TO-220-9 Vertical RM 0.97mm Multiwatt-9 staggered type-2
+0
+9
+9
+Package_TO_SOT_THT
+TO-220-9_P1.94x3.7mm_StaggerOdd_Lead3.8mm_Vertical
+TO-220-9, Vertical, RM 0.97mm, Multiwatt-9, staggered type-1
+TO-220-9 Vertical RM 0.97mm Multiwatt-9 staggered type-1
+0
+9
+9
+Package_TO_SOT_THT
+TO-220-9_P1.94x3.8mm_StaggerEven_Lead5.85mm_TabDown
+TO-220-9, Horizontal, RM 0.97mm, Multiwatt-9, staggered type-2
+TO-220-9 Horizontal RM 0.97mm Multiwatt-9 staggered type-2
+0
+9
+9
+Package_TO_SOT_THT
+TO-220-9_P1.94x3.8mm_StaggerOdd_Lead5.85mm_TabDown
+TO-220-9, Horizontal, RM 0.97mm, Multiwatt-9, staggered type-1
+TO-220-9 Horizontal RM 0.97mm Multiwatt-9 staggered type-1
+0
+9
+9
+Package_TO_SOT_THT
+TO-220-11_P3.4x2.54mm_StaggerEven_Lead5.84mm_TabDown
+TO-220-11, Horizontal, RM 1.7mm, staggered type-2, see http://www.st.com/resource/en/datasheet/tda7391lv.pdf
+TO-220-11 Horizontal RM 1.7mm staggered type-2
+0
+11
+11
+Package_TO_SOT_THT
+TO-220-11_P3.4x2.54mm_StaggerOdd_Lead5.84mm_TabDown
+TO-220-11, Horizontal, RM 1.7mm, staggered type-1, see http://www.st.com/resource/en/datasheet/tda7391lv.pdf
+TO-220-11 Horizontal RM 1.7mm staggered type-1
+0
+11
+11
+Package_TO_SOT_THT
+TO-220-11_P3.4x5.08mm_StaggerEven_Lead4.58mm_Vertical
+TO-220-11, Vertical, RM 1.7mm, staggered type-2, see http://www.st.com/resource/en/datasheet/tda7391lv.pdf
+TO-220-11 Vertical RM 1.7mm staggered type-2
+0
+11
+11
+Package_TO_SOT_THT
+TO-220-11_P3.4x5.08mm_StaggerOdd_Lead4.85mm_Vertical
+TO-220-11, Vertical, RM 1.7mm, staggered type-1, see http://www.st.com/resource/en/datasheet/tda7391lv.pdf
+TO-220-11 Vertical RM 1.7mm staggered type-1
+0
+11
+11
+Package_TO_SOT_THT
+TO-220-11_P3.4x5.08mm_StaggerOdd_Lead8.45mm_TabDown
+TO-220-11, Horizontal, RM 1.7mm, staggered type-1, see http://www.ti.com/lit/ds/symlink/lmd18200.pdf
+TO-220-11 Horizontal RM 1.7mm staggered type-1
+0
+11
+11
+Package_TO_SOT_THT
+TO-220-15_P2.54x2.54mm_StaggerEven_Lead4.58mm_Vertical
+TO-220-15, Vertical, RM 1.27mm, staggered type-2, see http://www.st.com/resource/en/datasheet/l298.pdf
+TO-220-15 Vertical RM 1.27mm staggered type-2
+0
+15
+15
+Package_TO_SOT_THT
+TO-220-15_P2.54x2.54mm_StaggerEven_Lead5.84mm_TabDown
+TO-220-15, Horizontal, RM 1.27mm, staggered type-2, see http://www.st.com/resource/en/datasheet/l298.pdf
+TO-220-15 Horizontal RM 1.27mm staggered type-2
+0
+15
+15
+Package_TO_SOT_THT
+TO-220-15_P2.54x2.54mm_StaggerOdd_Lead4.58mm_Vertical
+TO-220-15, Vertical, RM 1.27mm, staggered type-1, see http://www.st.com/resource/en/datasheet/l298.pdf
+TO-220-15 Vertical RM 1.27mm staggered type-1
+0
+15
+15
+Package_TO_SOT_THT
+TO-220-15_P2.54x2.54mm_StaggerOdd_Lead5.84mm_TabDown
+TO-220-15, Horizontal, RM 1.27mm, staggered type-1, see http://www.st.com/resource/en/datasheet/l298.pdf
+TO-220-15 Horizontal RM 1.27mm staggered type-1
+0
+15
+15
+Package_TO_SOT_THT
+TO-220F-2_Horizontal_TabDown
+TO-220F-2, Horizontal, RM 5.08mm, see http://www.onsemi.com/pub/Collateral/FFPF10F150S-D.pdf
+TO-220F-2 Horizontal RM 5.08mm
+0
+2
+2
+Package_TO_SOT_THT
+TO-220F-2_Horizontal_TabUp
+TO-220F-2, Horizontal, RM 5.08mm, see http://www.onsemi.com/pub/Collateral/FFPF10F150S-D.pdf
+TO-220F-2 Horizontal RM 5.08mm
+0
+2
+2
+Package_TO_SOT_THT
+TO-220F-2_Vertical
+TO-220F-2, Vertical, RM 5.08mm, see http://www.onsemi.com/pub/Collateral/FFPF10F150S-D.pdf
+TO-220F-2 Vertical RM 5.08mm
+0
+2
+2
+Package_TO_SOT_THT
+TO-220F-3_Horizontal_TabDown
+TO-220F-3, Horizontal, RM 2.54mm, see http://www.st.com/resource/en/datasheet/stp20nm60.pdf
+TO-220F-3 Horizontal RM 2.54mm
+0
+3
+3
+Package_TO_SOT_THT
+TO-220F-3_Horizontal_TabUp
+TO-220F-3, Horizontal, RM 2.54mm, see http://www.st.com/resource/en/datasheet/stp20nm60.pdf
+TO-220F-3 Horizontal RM 2.54mm
+0
+3
+3
+Package_TO_SOT_THT
+TO-220F-3_Vertical
+TO-220F-3, Vertical, RM 2.54mm, see http://www.st.com/resource/en/datasheet/stp20nm60.pdf
+TO-220F-3 Vertical RM 2.54mm
+0
+3
+3
+Package_TO_SOT_THT
+TO-220F-4_Horizontal_TabDown
+TO-220F-4, Horizontal, RM 2.54mm, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf
+TO-220F-4 Horizontal RM 2.54mm
+0
+4
+4
+Package_TO_SOT_THT
+TO-220F-4_Horizontal_TabUp
+TO-220F-4, Horizontal, RM 2.54mm, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf
+TO-220F-4 Horizontal RM 2.54mm
+0
+4
+4
+Package_TO_SOT_THT
+TO-220F-4_P5.08x2.05mm_StaggerEven_Lead1.85mm_Vertical
+TO-220F-4, Vertical, RM 2.54mm, staggered type-2, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf
+TO-220F-4 Vertical RM 2.54mm staggered type-2
+0
+4
+4
+Package_TO_SOT_THT
+TO-220F-4_P5.08x2.05mm_StaggerOdd_Lead1.85mm_Vertical
+TO-220F-4, Vertical, RM 2.54mm, staggered type-1, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf
+TO-220F-4 Vertical RM 2.54mm staggered type-1
+0
+4
+4
+Package_TO_SOT_THT
+TO-220F-4_P5.08x3.7mm_StaggerEven_Lead3.5mm_Vertical
+TO-220F-4, Vertical, RM 2.54mm, staggered type-2, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf
+TO-220F-4 Vertical RM 2.54mm staggered type-2
+0
+4
+4
+Package_TO_SOT_THT
+TO-220F-4_P5.08x3.7mm_StaggerOdd_Lead3.5mm_Vertical
+TO-220F-4, Vertical, RM 2.54mm, staggered type-1, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf
+TO-220F-4 Vertical RM 2.54mm staggered type-1
+0
+4
+4
+Package_TO_SOT_THT
+TO-220F-4_Vertical
+TO-220F-4, Vertical, RM 2.54mm, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf
+TO-220F-4 Vertical RM 2.54mm
+0
+4
+4
+Package_TO_SOT_THT
+TO-220F-5_Horizontal_TabDown
+TO-220F-5, Horizontal, RM 1.7mm, PentawattF-, MultiwattF-5
+TO-220F-5 Horizontal RM 1.7mm PentawattF- MultiwattF-5
+0
+5
+5
+Package_TO_SOT_THT
+TO-220F-5_Horizontal_TabUp
+TO-220F-5, Horizontal, RM 1.7mm, PentawattF-, MultiwattF-5
+TO-220F-5 Horizontal RM 1.7mm PentawattF- MultiwattF-5
+0
+5
+5
+Package_TO_SOT_THT
+TO-220F-5_P3.4x2.06mm_StaggerEven_Lead1.86mm_Vertical
+TO-220F-5, Vertical, RM 1.7mm, PentawattF-, MultiwattF-5, staggered type-2
+TO-220F-5 Vertical RM 1.7mm PentawattF- MultiwattF-5 staggered type-2
+0
+5
+5
+Package_TO_SOT_THT
+TO-220F-5_P3.4x2.06mm_StaggerOdd_Lead1.86mm_Vertical
+TO-220F-5, Vertical, RM 1.7mm, PentawattF-, MultiwattF-5, staggered type-1
+TO-220F-5 Vertical RM 1.7mm PentawattF- MultiwattF-5 staggered type-1
+0
+5
+5
+Package_TO_SOT_THT
+TO-220F-5_P3.4x3.7mm_StaggerEven_Lead3.5mm_Vertical
+TO-220F-5, Vertical, RM 1.7mm, PentawattF-, MultiwattF-5, staggered type-2
+TO-220F-5 Vertical RM 1.7mm PentawattF- MultiwattF-5 staggered type-2
+0
+5
+5
+Package_TO_SOT_THT
+TO-220F-5_P3.4x3.7mm_StaggerOdd_Lead3.5mm_Vertical
+TO-220F-5, Vertical, RM 1.7mm, PentawattF-, MultiwattF-5, staggered type-1
+TO-220F-5 Vertical RM 1.7mm PentawattF- MultiwattF-5 staggered type-1
+0
+5
+5
+Package_TO_SOT_THT
+TO-220F-5_Vertical
+TO-220F-5, Vertical, RM 1.7mm, PentawattF-, MultiwattF-5
+TO-220F-5 Vertical RM 1.7mm PentawattF- MultiwattF-5
+0
+5
+5
+Package_TO_SOT_THT
+TO-220F-7_P2.54x3.7mm_StaggerEven_Lead3.5mm_Vertical
+TO-220F-7, Vertical, RM 1.27mm, staggered type-2
+TO-220F-7 Vertical RM 1.27mm staggered type-2
+0
+7
+7
+Package_TO_SOT_THT
+TO-220F-7_P2.54x3.7mm_StaggerOdd_Lead3.5mm_Vertical
+TO-220F-7, Vertical, RM 1.27mm, staggered type-1
+TO-220F-7 Vertical RM 1.27mm staggered type-1
+0
+7
+7
+Package_TO_SOT_THT
+TO-220F-9_P1.8x3.7mm_StaggerEven_Lead3.5mm_Vertical
+TO-220F-9, Vertical, RM 0.9mm, staggered type-2
+TO-220F-9 Vertical RM 0.9mm staggered type-2
+0
+9
+9
+Package_TO_SOT_THT
+TO-220F-9_P1.8x3.7mm_StaggerOdd_Lead3.5mm_Vertical
+TO-220F-9, Vertical, RM 0.9mm, staggered type-1
+TO-220F-9 Vertical RM 0.9mm staggered type-1
+0
+9
+9
+Package_TO_SOT_THT
+TO-220F-11_P3.4x5.08mm_StaggerEven_Lead5.08mm_Vertical
+TO-220F-11, Vertical, RM 1.7mm, MultiwattF-11, staggered type-2, see http://www.ti.com/lit/ds/symlink/lm3886.pdf
+TO-220F-11 Vertical RM 1.7mm MultiwattF-11 staggered type-2
+0
+11
+11
+Package_TO_SOT_THT
+TO-220F-11_P3.4x5.08mm_StaggerOdd_Lead5.08mm_Vertical
+TO-220F-11, Vertical, RM 1.7mm, MultiwattF-11, staggered type-1, see http://www.ti.com/lit/ds/symlink/lm3886.pdf
+TO-220F-11 Vertical RM 1.7mm MultiwattF-11 staggered type-1
+0
+11
+11
+Package_TO_SOT_THT
+TO-220F-15_P2.54x5.08mm_StaggerEven_Lead5.08mm_Vertical
+TO-220F-15, Vertical, RM 1.27mm, MultiwattF-15, staggered type-2
+TO-220F-15 Vertical RM 1.27mm MultiwattF-15 staggered type-2
+0
+15
+15
+Package_TO_SOT_THT
+TO-220F-15_P2.54x5.08mm_StaggerOdd_Lead5.08mm_Vertical
+TO-220F-15, Vertical, RM 1.27mm, MultiwattF-15, staggered type-1
+TO-220F-15 Vertical RM 1.27mm MultiwattF-15 staggered type-1
+0
+15
+15
+Package_TO_SOT_THT
+TO-247-2_Horizontal_TabDown
+TO-247-2, Horizontal, RM 10.9mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html
+TO-247-2 Horizontal RM 10.9mm
+0
+2
+2
+Package_TO_SOT_THT
+TO-247-2_Horizontal_TabUp
+TO-247-2, Horizontal, RM 10.9mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html
+TO-247-2 Horizontal RM 10.9mm
+0
+2
+2
+Package_TO_SOT_THT
+TO-247-2_Vertical
+TO-247-2, Vertical, RM 10.9mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html
+TO-247-2 Vertical RM 10.9mm
+0
+2
+2
+Package_TO_SOT_THT
+TO-247-3_Horizontal_TabDown
+TO-247-3, Horizontal, RM 5.45mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html
+TO-247-3 Horizontal RM 5.45mm
+0
+3
+3
+Package_TO_SOT_THT
+TO-247-3_Horizontal_TabUp
+TO-247-3, Horizontal, RM 5.45mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html
+TO-247-3 Horizontal RM 5.45mm
+0
+3
+3
+Package_TO_SOT_THT
+TO-247-3_Vertical
+TO-247-3, Vertical, RM 5.45mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html
+TO-247-3 Vertical RM 5.45mm
+0
+3
+3
+Package_TO_SOT_THT
+TO-247-4_Horizontal_TabDown
+TO-247-4, Horizontal, RM 2.54mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html
+TO-247-4 Horizontal RM 2.54mm
+0
+4
+4
+Package_TO_SOT_THT
+TO-247-4_Horizontal_TabUp
+TO-247-4, Horizontal, RM 2.54mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html
+TO-247-4 Horizontal RM 2.54mm
+0
+4
+4
+Package_TO_SOT_THT
+TO-247-4_Vertical
+TO-247-4, Vertical, RM 2.54mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html
+TO-247-4 Vertical RM 2.54mm
+0
+4
+4
+Package_TO_SOT_THT
+TO-247-5_Horizontal_TabDown
+TO-247-5, Horizontal, RM 2.54mm, see http://ww1.microchip.com/downloads/en/DeviceDoc/20005685A.pdf
+TO-247-5 Horizontal RM 2.54mm
+0
+5
+5
+Package_TO_SOT_THT
+TO-247-5_Horizontal_TabUp
+TO-247-5, Horizontal, RM 2.54mm, see http://ww1.microchip.com/downloads/en/DeviceDoc/20005685A.pdf
+TO-247-5 Horizontal RM 2.54mm
+0
+5
+5
+Package_TO_SOT_THT
+TO-247-5_Vertical
+TO-247-5, Vertical, RM 2.54mm, see http://ww1.microchip.com/downloads/en/DeviceDoc/20005685A.pdf
+TO-247-5 Vertical RM 2.54mm
+0
+5
+5
+Package_TO_SOT_THT
+TO-251-2-1EP_Horizontal_TabDown
+TO-251-2, Horizontal, RM 4.58mm, IPAK, see https://www.diodes.com/assets/Package-Files/TO251.pdf
+TO-251-2 Horizontal RM 4.58mm IPAK
+0
+3
+3
+Package_TO_SOT_THT
+TO-251-2_Vertical
+TO-251-2, Vertical, RM 4.58mm, IPAK, see https://www.diodes.com/assets/Package-Files/TO251.pdf
+TO-251-2 Vertical RM 4.58mm IPAK
+0
+2
+2
+Package_TO_SOT_THT
+TO-251-3-1EP_Horizontal_TabDown
+TO-251-3, Horizontal, RM 2.29mm, IPAK, see https://www.diodes.com/assets/Package-Files/TO251.pdf
+TO-251-3 Horizontal RM 2.29mm IPAK
+0
+4
+4
+Package_TO_SOT_THT
+TO-251-3_Vertical
+TO-251-3, Vertical, RM 2.29mm, IPAK, see https://www.diodes.com/assets/Package-Files/TO251.pdf
+TO-251-3 Vertical RM 2.29mm IPAK
+0
+3
+3
+Package_TO_SOT_THT
+TO-262-3-1EP_Horizontal_TabDown
+TO-262-3, Horizontal, RM 2.54mm, IIPAK, I2PAK, see http://www.onsemi.com/pub/Collateral/EN8586-D.PDF
+TO-262-3 Horizontal RM 2.54mm IIPAK I2PAK
+0
+4
+4
+Package_TO_SOT_THT
+TO-262-3_Vertical
+TO-262-3, Vertical, RM 2.54mm, IIPAK, I2PAK, see http://www.onsemi.com/pub/Collateral/EN8586-D.PDF
+TO-262-3 Vertical RM 2.54mm IIPAK I2PAK
+0
+3
+3
+Package_TO_SOT_THT
+TO-262-5-1EP_Horizontal_TabDown
+TO-262-5, Horizontal, RM 1.7mm, IIPAK, I2PAK, see http://pdf.datasheetcatalog.com/datasheet/irf/iris4011.pdf
+TO-262-5 Horizontal RM 1.7mm IIPAK I2PAK
+0
+6
+6
+Package_TO_SOT_THT
+TO-262-5_Vertical
+TO-262-5, Vertical, RM 1.7mm, IIPAK, I2PAK, see http://pdf.datasheetcatalog.com/datasheet/irf/iris4011.pdf
+TO-262-5 Vertical RM 1.7mm IIPAK I2PAK
+0
+5
+5
+Package_TO_SOT_THT
+TO-264-2_Horizontal_TabDown
+TO-264-2, Horizontal, RM 10.9mm, see https://www.fairchildsemi.com/package-drawings/TO/TO264A03.pdf
+TO-264-2 Horizontal RM 10.9mm
+0
+2
+2
+Package_TO_SOT_THT
+TO-264-2_Horizontal_TabUp
+TO-264-2, Horizontal, RM 10.9mm, see https://www.fairchildsemi.com/package-drawings/TO/TO264A03.pdf
+TO-264-2 Horizontal RM 10.9mm
+0
+2
+2
+Package_TO_SOT_THT
+TO-264-2_Vertical
+TO-264-2, Vertical, RM 10.9mm, see https://www.fairchildsemi.com/package-drawings/TO/TO264A03.pdf
+TO-264-2 Vertical RM 10.9mm
+0
+2
+2
+Package_TO_SOT_THT
+TO-264-3_Horizontal_TabDown
+TO-264-3, Horizontal, RM 5.45mm, see https://www.fairchildsemi.com/package-drawings/TO/TO264A03.pdf
+TO-264-3 Horizontal RM 5.45mm
+0
+3
+3
+Package_TO_SOT_THT
+TO-264-3_Horizontal_TabUp
+TO-264-3, Horizontal, RM 5.45mm, see https://www.fairchildsemi.com/package-drawings/TO/TO264A03.pdf
+TO-264-3 Horizontal RM 5.45mm
+0
+3
+3
+Package_TO_SOT_THT
+TO-264-3_Vertical
+TO-264-3, Vertical, RM 5.45mm, see https://www.fairchildsemi.com/package-drawings/TO/TO264A03.pdf
+TO-264-3 Vertical RM 5.45mm
+0
+3
+3
+Package_TO_SOT_THT
+TO-264-5_Horizontal_TabDown
+TO-264-5, Horizontal, RM 3.81mm, see https://www.onsemi.com/pub/Collateral/NJL3281D-D.PDF
+TO-264-5 Horizontal RM 3.81mm
+0
+5
+5
+Package_TO_SOT_THT
+TO-264-5_Horizontal_TabUp
+TO-264-5, Horizontal, RM 3.81mm, see https://www.onsemi.com/pub/Collateral/NJL3281D-D.PDF
+TO-264-5 Horizontal RM 3.81mm
+0
+5
+5
+Package_TO_SOT_THT
+TO-264-5_Vertical
+TO-264-5, Vertical, RM 3.81mm, see https://www.onsemi.com/pub/Collateral/NJL3281D-D.PDF
+TO-264-5 Vertical RM 3.81mm
+0
+5
+5
+Potentiometer_SMD
+Potentiometer_ACP_CA6-VSMD_Vertical
+Potentiometer, vertical, ACP CA6-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/06/01-ACP-CA6.pdf
+Potentiometer vertical ACP CA6-VSMD
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_ACP_CA6-VSMD_Vertical_Hole
+Potentiometer, vertical, shaft hole, ACP CA6-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/06/01-ACP-CA6.pdf
+Potentiometer vertical hole ACP CA6-VSMD
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_ACP_CA9-VSMD_Vertical
+Potentiometer, vertical, ACP CA9-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf
+Potentiometer vertical ACP CA9-VSMD
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_ACP_CA9-VSMD_Vertical_Hole
+Potentiometer, vertical, shaft hole, ACP CA9-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf
+Potentiometer vertical hole ACP CA9-VSMD
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_ACP_CA14-VSMD_Vertical
+Potentiometer, vertical, ACP CA14-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf
+Potentiometer vertical ACP CA14-VSMD
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_ACP_CA14-VSMD_Vertical_Hole
+Potentiometer, vertical, shaft hole, ACP CA14-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf
+Potentiometer vertical hole ACP CA14-VSMD
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Bourns_3214G_Horizontal
+Potentiometer, horizontal, Bourns 3214G, https://www.bourns.com/docs/Product-Datasheets/3214.pdf
+Potentiometer horizontal Bourns 3214G
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Bourns_3214J_Horizontal
+Potentiometer, horizontal, Bourns 3214J, https://www.bourns.com/docs/Product-Datasheets/3214.pdf
+Potentiometer horizontal Bourns 3214J
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Bourns_3214W_Vertical
+Potentiometer, vertical, Bourns 3214W, https://www.bourns.com/docs/Product-Datasheets/3214.pdf
+Potentiometer vertical Bourns 3214W
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Bourns_3214X_Vertical
+Potentiometer, vertical, Bourns 3214X, https://www.bourns.com/docs/Product-Datasheets/3214.pdf
+Potentiometer vertical Bourns 3214X
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Bourns_3224G_Horizontal
+Potentiometer, horizontal, Bourns 3224G, https://www.bourns.com/docs/Product-Datasheets/3224.pdf
+Potentiometer horizontal Bourns 3224G
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Bourns_3224J_Horizontal
+Potentiometer, horizontal, Bourns 3224J, https://www.bourns.com/docs/Product-Datasheets/3224.pdf
+Potentiometer horizontal Bourns 3224J
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Bourns_3224W_Vertical
+Potentiometer, vertical, Bourns 3224W, https://www.bourns.com/docs/Product-Datasheets/3224.pdf
+Potentiometer vertical Bourns 3224W
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Bourns_3224X_Vertical
+Potentiometer, vertical, Bourns 3224X, https://www.bourns.com/docs/Product-Datasheets/3224.pdf
+Potentiometer vertical Bourns 3224X
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Bourns_3269P_Horizontal
+Potentiometer, horizontal, Bourns 3269P, https://www.bourns.com/docs/Product-Datasheets/3269.pdf
+Potentiometer horizontal Bourns 3269P
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Bourns_3269W_Vertical
+Potentiometer, vertical, Bourns 3269W, https://www.bourns.com/docs/Product-Datasheets/3269.pdf
+Potentiometer vertical Bourns 3269W
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Bourns_3269X_Horizontal
+Potentiometer, horizontal, Bourns 3269X, https://www.bourns.com/docs/Product-Datasheets/3269.pdf
+Potentiometer horizontal Bourns 3269X
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Bourns_3314G_Vertical
+Potentiometer, vertical, Bourns 3314G, http://www.bourns.com/docs/Product-Datasheets/3314.pdf
+Potentiometer vertical Bourns 3314G
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Bourns_3314J_Vertical
+Potentiometer, vertical, Bourns 3314J, http://www.bourns.com/docs/Product-Datasheets/3314.pdf
+Potentiometer vertical Bourns 3314J
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Bourns_3314R-1_Vertical_Hole
+Potentiometer, vertical, shaft hole, Bourns 3314R-1, http://www.bourns.com/docs/Product-Datasheets/3314.pdf
+Potentiometer vertical hole Bourns 3314R-1
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Bourns_3314R-GM5_Vertical
+Potentiometer, vertical, Bourns 3314R-GM5, http://www.bourns.com/docs/Product-Datasheets/3314.pdf
+Potentiometer vertical Bourns 3314R-GM5
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Bourns_3314S_Horizontal
+Potentiometer, horizontal, Bourns 3314S, http://www.bourns.com/docs/Product-Datasheets/3314.pdf
+Potentiometer horizontal Bourns 3314S
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Bourns_PRS11S_Vertical
+Potentiometer, vertical, Bourns PRS11S, http://www.bourns.com/docs/Product-Datasheets/PRS11S.pdf
+Potentiometer vertical Bourns PRS11S
+0
+5
+5
+Potentiometer_SMD
+Potentiometer_Bourns_TC33X_Vertical
+Potentiometer, Bourns, TC33X, Vertical, https://www.bourns.com/pdfs/TC33.pdf
+Potentiometer Bourns TC33X Vertical
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Vishay_TS53YJ_Vertical
+Potentiometer, vertical, Vishay TS53YJ, https://www.vishay.com/docs/51008/ts53.pdf
+Potentiometer vertical Vishay TS53YJ
+0
+3
+3
+Potentiometer_SMD
+Potentiometer_Vishay_TS53YL_Vertical
+Potentiometer, vertical, Vishay TS53YL, https://www.vishay.com/docs/51008/ts53.pdf
+Potentiometer vertical Vishay TS53YL
+0
+3
+3
+Potentiometer_THT
+Potentiometer_ACP_CA6-H2,5_Horizontal
+Potentiometer, horizontal, ACP CA6-H2,5, http://www.acptechnologies.com/wp-content/uploads/2017/06/01-ACP-CA6.pdf
+Potentiometer horizontal ACP CA6-H2,5
+0
+3
+3
+Potentiometer_THT
+Potentiometer_ACP_CA9-H2,5_Horizontal
+Potentiometer, horizontal, ACP CA9-H2,5, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf
+Potentiometer horizontal ACP CA9-H2,5
+0
+3
+3
+Potentiometer_THT
+Potentiometer_ACP_CA9-H3,8_Horizontal
+Potentiometer, horizontal, ACP CA9-H3,8, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf
+Potentiometer horizontal ACP CA9-H3,8
+0
+3
+3
+Potentiometer_THT
+Potentiometer_ACP_CA9-H5_Horizontal
+Potentiometer, horizontal, ACP CA9-H5, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf
+Potentiometer horizontal ACP CA9-H5
+0
+3
+3
+Potentiometer_THT
+Potentiometer_ACP_CA9-V10_Vertical
+Potentiometer, vertical, ACP CA9-V10, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf
+Potentiometer vertical ACP CA9-V10
+0
+3
+3
+Potentiometer_THT
+Potentiometer_ACP_CA9-V10_Vertical_Hole
+Potentiometer, vertical, shaft hole, ACP CA9-V10, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf
+Potentiometer vertical hole ACP CA9-V10
+0
+3
+3
+Potentiometer_THT
+Potentiometer_ACP_CA14-H2,5_Horizontal
+Potentiometer, horizontal, ACP CA14-H2,5, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf
+Potentiometer horizontal ACP CA14-H2,5
+0
+3
+3
+Potentiometer_THT
+Potentiometer_ACP_CA14-H4_Horizontal
+Potentiometer, horizontal, ACP CA14-H4, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf
+Potentiometer horizontal ACP CA14-H4
+0
+3
+3
+Potentiometer_THT
+Potentiometer_ACP_CA14-H5_Horizontal
+Potentiometer, horizontal, ACP CA14-H5, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf
+Potentiometer horizontal ACP CA14-H5
+0
+3
+3
+Potentiometer_THT
+Potentiometer_ACP_CA14V-15_Vertical
+Potentiometer, vertical, ACP CA14V-15, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf
+Potentiometer vertical ACP CA14V-15
+0
+3
+3
+Potentiometer_THT
+Potentiometer_ACP_CA14V-15_Vertical_Hole
+Potentiometer, vertical, shaft hole, ACP CA14V-15, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf
+Potentiometer vertical hole ACP CA14V-15
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Alpha_RD901F-40-00D_Single_Vertical
+Potentiometer, vertical, 9mm, single, http://www.taiwanalpha.com.tw/downloads?target=products&id=113
+potentiometer vertical 9mm single
+0
+5
+3
+Potentiometer_THT
+Potentiometer_Alpha_RD901F-40-00D_Single_Vertical_CircularHoles
+Potentiometer, vertical, 9mm, single, http://www.taiwanalpha.com.tw/downloads?target=products&id=113
+potentiometer vertical 9mm single
+0
+5
+3
+Potentiometer_THT
+Potentiometer_Alpha_RD902F-40-00D_Dual_Vertical
+Potentiometer, vertical, 9mm, dual, http://www.taiwanalpha.com.tw/downloads?target=products&id=113
+potentiometer vertical 9mm dual
+0
+8
+6
+Potentiometer_THT
+Potentiometer_Alpha_RD902F-40-00D_Dual_Vertical_CircularHoles
+Potentiometer, vertical, 9mm, dual, http://www.taiwanalpha.com.tw/downloads?target=products&id=113
+potentiometer vertical 9mm dual
+0
+8
+6
+Potentiometer_THT
+Potentiometer_Alps_RK09K_Single_Horizontal
+Potentiometer, horizontal, Alps RK09K Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09K/RK09K_list.html
+Potentiometer horizontal Alps RK09K Single
+0
+5
+3
+Potentiometer_THT
+Potentiometer_Alps_RK09K_Single_Vertical
+Potentiometer, vertical, Alps RK09K Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09K/RK09K_list.html
+Potentiometer vertical Alps RK09K Single
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Alps_RK09L_Double_Horizontal
+Potentiometer, horizontal, Alps RK09L Double, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09L/RK09L_list.html
+Potentiometer horizontal Alps RK09L Double
+0
+8
+6
+Potentiometer_THT
+Potentiometer_Alps_RK09L_Double_Vertical
+Potentiometer, vertical, Alps RK09L Double, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09L/RK09L_list.html
+Potentiometer vertical Alps RK09L Double
+0
+6
+6
+Potentiometer_THT
+Potentiometer_Alps_RK09L_Single_Horizontal
+Potentiometer, horizontal, Alps RK09L Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09L/RK09L_list.html
+Potentiometer horizontal Alps RK09L Single
+0
+5
+3
+Potentiometer_THT
+Potentiometer_Alps_RK09L_Single_Vertical
+Potentiometer, vertical, Alps RK09L Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09L/RK09L_list.html
+Potentiometer vertical Alps RK09L Single
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Alps_RK09Y11_Single_Horizontal
+Potentiometer, horizontal, Alps RK09Y11 Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09Y11/RK09Y11_list.html
+Potentiometer horizontal Alps RK09Y11 Single
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Alps_RK097_Dual_Horizontal
+Potentiometer, horizontal, Alps RK097 Dual, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK097/RK097_list.html
+Potentiometer horizontal Alps RK097 Dual
+0
+6
+6
+Potentiometer_THT
+Potentiometer_Alps_RK097_Single_Horizontal
+Potentiometer, horizontal, Alps RK097 Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK097/RK097_list.html
+Potentiometer horizontal Alps RK097 Single
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Alps_RK163_Dual_Horizontal
+Potentiometer, horizontal, Alps RK163 Dual, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK16/RK16_list.html
+Potentiometer horizontal Alps RK163 Dual
+0
+6
+6
+Potentiometer_THT
+Potentiometer_Alps_RK163_Single_Horizontal
+Potentiometer, horizontal, Alps RK163 Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK16/RK16_list.html
+Potentiometer horizontal Alps RK163 Single
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3005_Horizontal
+Potentiometer, horizontal, Bourns 3005, http://www.bourns.com/docs/Product-Datasheets/3005.pdf
+Potentiometer horizontal Bourns 3005
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3006P_Horizontal
+Potentiometer, horizontal, Bourns 3006P, https://www.bourns.com/docs/Product-Datasheets/3006.pdf
+Potentiometer horizontal Bourns 3006P
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3006W_Horizontal
+Potentiometer, horizontal, Bourns 3006W, https://www.bourns.com/docs/Product-Datasheets/3006.pdf
+Potentiometer horizontal Bourns 3006W
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3006Y_Horizontal
+Potentiometer, horizontal, Bourns 3006Y, https://www.bourns.com/docs/Product-Datasheets/3006.pdf
+Potentiometer horizontal Bourns 3006Y
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3009P_Horizontal
+Potentiometer, horizontal, Bourns 3009P, http://www.bourns.com/docs/Product-Datasheets/3009.pdf
+Potentiometer horizontal Bourns 3009P
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3009Y_Horizontal
+Potentiometer, horizontal, Bourns 3009Y, http://www.bourns.com/docs/Product-Datasheets/3009.pdf
+Potentiometer horizontal Bourns 3009Y
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3266P_Horizontal
+Potentiometer, horizontal, Bourns 3266P, https://www.bourns.com/docs/Product-Datasheets/3266.pdf
+Potentiometer horizontal Bourns 3266P
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3266W_Vertical
+Potentiometer, vertical, Bourns 3266W, https://www.bourns.com/docs/Product-Datasheets/3266.pdf
+Potentiometer vertical Bourns 3266W
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3266X_Horizontal
+Potentiometer, horizontal, Bourns 3266X, https://www.bourns.com/docs/Product-Datasheets/3266.pdf
+Potentiometer horizontal Bourns 3266X
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3266Y_Vertical
+Potentiometer, vertical, Bourns 3266Y, https://www.bourns.com/docs/Product-Datasheets/3266.pdf
+Potentiometer vertical Bourns 3266Y
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3266Z_Horizontal
+Potentiometer, horizontal, Bourns 3266Z, https://www.bourns.com/docs/Product-Datasheets/3266.pdf
+Potentiometer horizontal Bourns 3266Z
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3296P_Horizontal
+Potentiometer, horizontal, Bourns 3296P, https://www.bourns.com/pdfs/3296.pdf
+Potentiometer horizontal Bourns 3296P
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3296W_Vertical
+Potentiometer, vertical, Bourns 3296W, https://www.bourns.com/pdfs/3296.pdf
+Potentiometer vertical Bourns 3296W
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3296X_Horizontal
+Potentiometer, horizontal, Bourns 3296X, https://www.bourns.com/pdfs/3296.pdf
+Potentiometer horizontal Bourns 3296X
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3296Y_Vertical
+Potentiometer, vertical, Bourns 3296Y, https://www.bourns.com/pdfs/3296.pdf
+Potentiometer vertical Bourns 3296Y
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3296Z_Horizontal
+Potentiometer, horizontal, Bourns 3296Z, https://www.bourns.com/pdfs/3296.pdf
+Potentiometer horizontal Bourns 3296Z
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3299P_Horizontal
+Potentiometer, horizontal, Bourns 3299P, https://www.bourns.com/pdfs/3299.pdf
+Potentiometer horizontal Bourns 3299P
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3299W_Vertical
+Potentiometer, vertical, Bourns 3299W, https://www.bourns.com/pdfs/3299.pdf
+Potentiometer vertical Bourns 3299W
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3299X_Horizontal
+Potentiometer, horizontal, Bourns 3299X, https://www.bourns.com/pdfs/3299.pdf
+Potentiometer horizontal Bourns 3299X
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3299Y_Vertical
+Potentiometer, vertical, Bourns 3299Y, https://www.bourns.com/pdfs/3299.pdf
+Potentiometer vertical Bourns 3299Y
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3299Z_Horizontal
+Potentiometer, horizontal, Bourns 3299Z, https://www.bourns.com/pdfs/3299.pdf
+Potentiometer horizontal Bourns 3299Z
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3339H_Vertical
+Potentiometer, vertical, Bourns 3339H, http://www.bourns.com/docs/Product-Datasheets/3339.pdf
+Potentiometer vertical Bourns 3339H
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3339P_Vertical
+Potentiometer, vertical, Bourns 3339P, http://www.bourns.com/docs/Product-Datasheets/3339.pdf
+Potentiometer vertical Bourns 3339P
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3339P_Vertical_HandSoldering
+Potentiometer, vertical, Bourns 3339P, hand-soldering, http://www.bourns.com/docs/Product-Datasheets/3339.pdf
+Potentiometer vertical Bourns 3339P hand-soldering
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3339S_Horizontal
+Potentiometer, horizontal, Bourns 3339S, http://www.bourns.com/docs/Product-Datasheets/3339.pdf
+Potentiometer horizontal Bourns 3339S
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3339W_Horizontal
+Potentiometer, horizontal, Bourns 3339W, http://www.bourns.com/docs/Product-Datasheets/3339.pdf
+Potentiometer horizontal Bourns 3339W
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3386C_Horizontal
+Potentiometer, horizontal, Bourns 3386C, https://www.bourns.com/pdfs/3386.pdf
+Potentiometer horizontal Bourns 3386C
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3386F_Vertical
+Potentiometer, vertical, Bourns 3386F, https://www.bourns.com/pdfs/3386.pdf
+Potentiometer vertical Bourns 3386F
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3386P_Vertical
+Potentiometer, vertical, Bourns 3386P, https://www.bourns.com/pdfs/3386.pdf
+Potentiometer vertical Bourns 3386P
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_3386X_Horizontal
+Potentiometer, horizontal, Bourns 3386X, https://www.bourns.com/pdfs/3386.pdf
+Potentiometer horizontal Bourns 3386X
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_PTA1543_Single_Slide
+Bourns single-gang slide potentiometer, 15.0mm travel, https://www.bourns.com/docs/Product-Datasheets/pta.pdf
+Bourns single-gang slide potentiometer 15.0mm
+0
+7
+4
+Potentiometer_THT
+Potentiometer_Bourns_PTA2043_Single_Slide
+Bourns single-gang slide potentiometer, 20.0mm travel, https://www.bourns.com/docs/Product-Datasheets/pta.pdf
+Bourns single-gang slide potentiometer 20.0mm
+0
+7
+4
+Potentiometer_THT
+Potentiometer_Bourns_PTA3043_Single_Slide
+Bourns single-gang slide potentiometer, 30.0mm travel, https://www.bourns.com/docs/Product-Datasheets/pta.pdf
+Bourns single-gang slide potentiometer 30.0mm
+0
+7
+4
+Potentiometer_THT
+Potentiometer_Bourns_PTA4543_Single_Slide
+Bourns single-gang slide potentiometer, 45.0mm travel, https://www.bourns.com/docs/Product-Datasheets/pta.pdf
+Bourns single-gang slide potentiometer 45.0mm
+0
+7
+4
+Potentiometer_THT
+Potentiometer_Bourns_PTA6043_Single_Slide
+Bourns single-gang slide potentiometer, 60.0mm travel, https://www.bourns.com/docs/Product-Datasheets/pta.pdf
+Bourns single-gang slide potentiometer 60.0mm
+0
+7
+4
+Potentiometer_THT
+Potentiometer_Bourns_PTV09A-1_Single_Vertical
+Potentiometer, vertical, Bourns PTV09A-1 Single, http://www.bourns.com/docs/Product-Datasheets/ptv09.pdf
+Potentiometer vertical Bourns PTV09A-1 Single
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Bourns_PTV09A-2_Single_Horizontal
+Potentiometer, horizontal, Bourns PTV09A-2 Single, http://www.bourns.com/docs/Product-Datasheets/ptv09.pdf
+Potentiometer horizontal Bourns PTV09A-2 Single
+0
+5
+3
+Potentiometer_THT
+Potentiometer_Omeg_PC16BU_Horizontal
+Potentiometer, horizontal, Omeg PC16BU, http://www.omeg.co.uk/pc6bubrc.htm
+Potentiometer horizontal Omeg PC16BU
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Omeg_PC16BU_Vertical
+Potentiometer, vertical, Omeg PC16BU, http://www.omeg.co.uk/pc6bubrc.htm
+Potentiometer vertical Omeg PC16BU
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_PC-16_Dual_Horizontal
+Potentiometer, horizontal, Piher PC-16 Dual, http://www.piher-nacesa.com/pdf/20-PC16v03.pdf
+Potentiometer horizontal Piher PC-16 Dual
+0
+6
+6
+Potentiometer_THT
+Potentiometer_Piher_PC-16_Single_Horizontal
+Potentiometer, horizontal, Piher PC-16 Single, http://www.piher-nacesa.com/pdf/20-PC16v03.pdf
+Potentiometer horizontal Piher PC-16 Single
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_PC-16_Single_Vertical
+Potentiometer, vertical, Piher PC-16 Single, http://www.piher-nacesa.com/pdf/20-PC16v03.pdf
+Potentiometer vertical Piher PC-16 Single
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_PC-16_Triple_Horizontal
+Potentiometer, horizontal, Piher PC-16 Triple, http://www.piher-nacesa.com/pdf/20-PC16v03.pdf
+Potentiometer horizontal Piher PC-16 Triple
+0
+9
+9
+Potentiometer_THT
+Potentiometer_Piher_PT-6-H_Horizontal
+Potentiometer, horizontal, Piher PT-6-H, http://www.piher-nacesa.com/pdf/11-PT6v03.pdf
+Potentiometer horizontal Piher PT-6-H
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_PT-6-V_Vertical
+Potentiometer, vertical, Piher PT-6-V, http://www.piher-nacesa.com/pdf/11-PT6v03.pdf
+Potentiometer vertical Piher PT-6-V
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_PT-6-V_Vertical_Hole
+Potentiometer, vertical, shaft hole, Piher PT-6-V, http://www.piher-nacesa.com/pdf/11-PT6v03.pdf
+Potentiometer vertical hole Piher PT-6-V
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_PT-10-H01_Horizontal
+Potentiometer, horizontal, Piher PT-10-H01, http://www.piher-nacesa.com/pdf/12-PT10v03.pdf
+Potentiometer horizontal Piher PT-10-H01
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_PT-10-H05_Horizontal
+Potentiometer, horizontal, Piher PT-10-H05, http://www.piher-nacesa.com/pdf/12-PT10v03.pdf
+Potentiometer horizontal Piher PT-10-H05
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_PT-10-V05_Vertical
+Potentiometer, vertical, Piher PT-10-V05, http://www.piher-nacesa.com/pdf/12-PT10v03.pdf
+Potentiometer vertical Piher PT-10-V05
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_PT-10-V10_Vertical
+Potentiometer, vertical, Piher PT-10-V10, http://www.piher-nacesa.com/pdf/12-PT10v03.pdf
+Potentiometer vertical Piher PT-10-V10
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_PT-10-V10_Vertical_Hole
+Potentiometer, vertical, shaft hole, Piher PT-10-V10, http://www.piher-nacesa.com/pdf/12-PT10v03.pdf
+Potentiometer vertical hole Piher PT-10-V10
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_PT-15-H01_Horizontal
+Potentiometer, horizontal, Piher PT-15-H01, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf
+Potentiometer horizontal Piher PT-15-H01
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_PT-15-H05_Horizontal
+Potentiometer, horizontal, Piher PT-15-H05, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf
+Potentiometer horizontal Piher PT-15-H05
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_PT-15-H06_Horizontal
+Potentiometer, horizontal, Piher PT-15-H06, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf
+Potentiometer horizontal Piher PT-15-H06
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_PT-15-H25_Horizontal
+Potentiometer, horizontal, Piher PT-15-H25, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf
+Potentiometer horizontal Piher PT-15-H25
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_PT-15-V02_Vertical
+Potentiometer, vertical, Piher PT-15-V02, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf
+Potentiometer vertical Piher PT-15-V02
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_PT-15-V02_Vertical_Hole
+Potentiometer, vertical, shaft hole, Piher PT-15-V02, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf
+Potentiometer vertical hole Piher PT-15-V02
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_PT-15-V15_Vertical
+Potentiometer, vertical, Piher PT-15-V15, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf
+Potentiometer vertical Piher PT-15-V15
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_PT-15-V15_Vertical_Hole
+Potentiometer, vertical, shaft hole, Piher PT-15-V15, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf
+Potentiometer vertical hole Piher PT-15-V15
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_T-16H_Double_Horizontal
+Potentiometer, horizontal, Piher T-16H Double, http://www.piher-nacesa.com/pdf/22-T16v03.pdf
+Potentiometer horizontal Piher T-16H Double
+0
+6
+6
+Potentiometer_THT
+Potentiometer_Piher_T-16H_Single_Horizontal
+Potentiometer, horizontal, Piher T-16H Single, http://www.piher-nacesa.com/pdf/22-T16v03.pdf
+Potentiometer horizontal Piher T-16H Single
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Piher_T-16L_Single_Vertical_Hole
+Potentiometer, vertical, shaft hole, Piher T-16L Single, http://www.piher-nacesa.com/pdf/22-T16v03.pdf
+Potentiometer vertical hole Piher T-16L Single
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Runtron_RM-063_Horizontal
+Potentiometer, horizontal, Trimmer, RM-063 http://www.runtron.com/down/PDF%20Datasheet/Carbon%20Film%20Potentiometer/RM065%20RM063.pdf
+Potentiometer Trimmer RM-063
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Runtron_RM-065_Vertical
+Potentiometer, vertical, Trimmer, RM-065 http://www.runtron.com/down/PDF%20Datasheet/Carbon%20Film%20Potentiometer/RM065%20RM063.pdf
+Potentiometer Trimmer RM-065
+0
+3
+3
+Potentiometer_THT
+Potentiometer_TT_P0915N
+http://www.ttelectronics.com/sites/default/files/download-files/Datasheet_PanelPot_P09xSeries.pdf
+potentiometer vertical TT P0915N single
+0
+5
+3
+Potentiometer_THT
+Potentiometer_Vishay_43_Horizontal
+Potentiometer, horizontal, Vishay 43, http://www.vishay.com/docs/57026/43.pdf
+Potentiometer horizontal Vishay 43
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Vishay_148-149_Dual_Horizontal
+Potentiometer, horizontal, Vishay 148-149 Dual, http://www.vishay.com/docs/57040/148149.pdf
+Potentiometer horizontal Vishay 148-149 Dual
+0
+6
+6
+Potentiometer_THT
+Potentiometer_Vishay_148-149_Single_Horizontal
+Potentiometer, horizontal, Vishay 148-149 Single, http://www.vishay.com/docs/57040/148149.pdf
+Potentiometer horizontal Vishay 148-149 Single
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Vishay_148-149_Single_Vertical
+Potentiometer, vertical, Vishay 148-149 Single, http://www.vishay.com/docs/57040/148149.pdf
+Potentiometer vertical Vishay 148-149 Single
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Vishay_148E-149E_Dual_Horizontal
+Potentiometer, horizontal, Vishay 148E-149E Dual, http://www.vishay.com/docs/57040/148149.pdf
+Potentiometer horizontal Vishay 148E-149E Dual
+0
+10
+6
+Potentiometer_THT
+Potentiometer_Vishay_148E-149E_Single_Horizontal
+Potentiometer, horizontal, Vishay 148E-149E Single, http://www.vishay.com/docs/57040/148149.pdf
+Potentiometer horizontal Vishay 148E-149E Single
+0
+7
+3
+Potentiometer_THT
+Potentiometer_Vishay_248BH-249BH_Single_Horizontal
+Potentiometer, horizontal, Vishay 248BH-249BH Single, http://www.vishay.com/docs/57054/248249.pdf
+Potentiometer horizontal Vishay 248BH-249BH Single
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Vishay_248GJ-249GJ_Single_Horizontal
+Potentiometer, horizontal, Vishay 248GJ-249GJ Single, http://www.vishay.com/docs/57054/248249.pdf
+Potentiometer horizontal Vishay 248GJ-249GJ Single
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Vishay_248GJ-249GJ_Single_Vertical
+Potentiometer, vertical, Vishay 248GJ-249GJ Single, http://www.vishay.com/docs/57054/248249.pdf
+Potentiometer vertical Vishay 248GJ-249GJ Single
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Vishay_T7-YA_Single_Vertical
+Potentiometer, vertical, Vishay T7-YA Single, http://www.vishay.com/docs/51015/t7.pdf
+Potentiometer vertical Vishay T7-YA Single
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Vishay_T73XW_Horizontal
+Potentiometer, horizontal, Vishay T73XW, http://www.vishay.com/docs/51016/t73.pdf
+Potentiometer horizontal Vishay T73XW
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Vishay_T73XX_Horizontal
+Potentiometer, horizontal, Vishay T73XX, http://www.vishay.com/docs/51016/t73.pdf
+Potentiometer horizontal Vishay T73XX
+0
+3
+3
+Potentiometer_THT
+Potentiometer_Vishay_T73YP_Vertical
+Potentiometer, vertical, Vishay T73YP, http://www.vishay.com/docs/51016/t73.pdf
+Potentiometer vertical Vishay T73YP
+0
+3
+3
+RF
+Skyworks_SKY13575_639LF
+http://www.skyworksinc.com/uploads/documents/SKY13575_639LF_203270D.pdf
+Skyworks
+0
+19
+15
+RF
+Skyworks_SKY65404-31
+http://www.skyworksinc.com/uploads/documents/SKY65404_31_201512K.pdf
+Skyworks
+0
+7
+7
+RF_Antenna
+Coilcraft_MA5532-AE_RFID
+RFID Transponder Coil
+antenna rfid coilcraft
+0
+2
+2
+RF_Antenna
+Pulse_W3011
+Pulse RF Antenna, 4mm Clearance
+antenna rf
+0
+3
+2
+RF_Antenna
+Texas_SWRA117D_2.4GHz_Left
+http://www.ti.com/lit/an/swra117d/swra117d.pdf
+PCB antenna
+0
+2
+2
+RF_Antenna
+Texas_SWRA117D_2.4GHz_Right
+http://www.ti.com/lit/an/swra117d/swra117d.pdf
+PCB antenna
+0
+2
+2
+RF_Antenna
+Texas_SWRA416_868MHz_915MHz
+http://www.ti.com/lit/an/swra416/swra416.pdf
+PCB antenna
+0
+20
+1
+RF_Converter
+Anaren_0805_2012Metric-6
+https://cdn.anaren.com/product-documents/Xinger/DirectionalCouplers/DC4759J5020AHF/DC4759J5020AHF_DataSheet(Rev_E).pdf
+coupler rf
+0
+6
+6
+RF_Converter
+Balun_Johanson_1.6x0.8mm
+6-pin 1.6x0.8 mm balun footprint
+Johanson balun filter
+0
+6
+6
+RF_Converter
+Balun_Johanson_5400BL15B050E
+https://www.johansontechnology.com/datasheets/5400BL15B050/5400BL15B050.pdf
+balun RF
+0
+6
+6
+RF_Converter
+RF_Attenuator_Susumu_PAT1220
+http://www.susumu-usa.com/pdf/Foot_Print_38.pdf, https://www.susumu.co.jp/common/pdf/n_catalog_partition16_en.pdf
+2mm 1.2mm
+0
+3
+3
+RF_GPS
+Linx_RXM-GPS
+GPS Module, Linx
+gps linx
+0
+22
+22
+RF_GPS
+SIM28ML
+https://simcom.ee/documents/SIM28ML/SIM28ML_Hardware%20Design_V1.01.pdf
+SIM28ML GPS
+0
+18
+18
+RF_GPS
+Sierra_XA11X0
+QFN-24, Pitch 1.20 no EP, https://source.sierrawireless.com/resources/airprime/hardware_specs_user_guides/airprime_xm1100_product_technical_specification
+QFN-24 P1.20
+0
+24
+24
+RF_GPS
+Sierra_XM11X0
+QFN-20, Pitch 1.20 no EP, https://source.sierrawireless.com/resources/airprime/hardware_specs_user_guides/airprime_xm1100_product_technical_specification
+QFN-20 P1.20
+0
+20
+20
+RF_GPS
+ublox_LEA
+ublox LEA 6/7/8, (https://www.u-blox.com/sites/default/files/LEA-M8S-M8T-FW3_HardwareIntegrationManual_%28UBX-15030060%29.pdf)
+GPS ublox LEA 6/7/8
+0
+28
+28
+RF_GPS
+ublox_MAX
+ublox MAX 6/7/8, (https://www.u-blox.com/sites/default/files/MAX-8-M8-FW3_HardwareIntegrationManual_%28UBX-15030059%29.pdf)
+GPS ublox MAX 6/7/8
+0
+18
+18
+RF_GPS
+ublox_NEO
+ublox NEO 6/7/8, (https://www.u-blox.com/sites/default/files/NEO-8Q-NEO-M8-FW3_HardwareIntegrationManual_%28UBX-15029985%29_0.pdf)
+GPS ublox NEO 6/7/8
+0
+24
+24
+RF_GPS
+ublox_SAM-M8Q
+GPS Module, 15.5x15.5x6.3mm, https://www.u-blox.com/sites/default/files/SAM-M8Q_HardwareIntegrationManual_%28UBX-16018358%29.pdf
+ublox SAM-M8Q
+0
+100
+20
+RF_GPS
+ublox_SAM-M8Q_HandSolder
+GPS Module, 15.5x15.5x6.3mm, https://www.u-blox.com/sites/default/files/SAM-M8Q_HardwareIntegrationManual_%28UBX-16018358%29.pdf
+ublox SAM-M8Q
+0
+20
+20
+RF_GSM
+Quectel_BC66
+GSM NB-IoT module, 15.8x17.7x2mm, https://www.quectel.com/UploadImage/Downlad/Quectel_BC66_Hardware_Design_V1.1.pdf
+GSM NB-IoT Module BC66 M66
+0
+58
+58
+RF_GSM
+SIMCom_SIM800C
+Quad-Band GSM/GPRS module, 17.6x15.7x2.3mm, http://simcom.ee/documents/SIM800C/SIM800C_Hardware_Design_V1.05.pdf
+GSM Module SIM800C
+0
+42
+42
+RF_GSM
+SIMCom_SIM900
+Quad-Band GSM/GPRS module, 24x24x3mm, http://simcom.ee/documents/SIM900/SIM900_Hardware%20Design_V2.05.pdf
+GSM Module SIM900
+0
+68
+68
+RF_GSM
+Telit_xL865
+Telit xL865 familly footprint, http://www.telit.com/fileadmin/user_upload/products/Downloads/3G/Telit_UL865_Hardware_User_Guide_r8.pdf 
+xL865 gsm umts
+0
+52
+48
+RF_GSM
+ublox_SARA-G3_LGA-96
+ublox Sara GSM/HSPA modem, https://www.u-blox.com/sites/default/files/SARA-G3-U2_SysIntegrManual_%28UBX-13000995%29.pdf, pag.162
+ublox SARA-G3 SARA-U2 GSM HSPA
+0
+192
+96
+RF_Mini-Circuits
+Mini-Circuits_BK377
+Footprint for Mini-Circuits case BK377 (https://ww2.minicircuits.com/case_style/BK276.pdf)
+Mini-circuits BK377
+0
+14
+14
+RF_Mini-Circuits
+Mini-Circuits_BK377_LandPatternPL-005
+Footprint for Mini-Circuits case BK377 (https://ww2.minicircuits.com/case_style/BK276.pdf) according to land-pattern PL-005, including GND vias (https://ww2.minicircuits.com/pcb/98-pl005.pdf)
+Mini-circuits VCXO JTOS PL-005
+0
+50
+14
+RF_Mini-Circuits
+Mini-Circuits_CD541_H2.08mm
+https://ww2.minicircuits.com/case_style/CD541.pdf
+RF Transformer
+0
+6
+6
+RF_Mini-Circuits
+Mini-Circuits_CD542_H2.84mm
+https://ww2.minicircuits.com/case_style/CD542.pdf
+RF Transformer
+0
+6
+6
+RF_Mini-Circuits
+Mini-Circuits_CD542_LandPatternPL-052
+Footprint for Mini-Circuits case CD542 (https://ww2.minicircuits.com/case_style/CD542.pdf) using land-pattern PL-052, including GND-vias (https://ww2.minicircuits.com/pcb/98-pl052.pdf)
+MiniCircuits PL-052 CD542
+0
+17
+6
+RF_Mini-Circuits
+Mini-Circuits_CD542_LandPatternPL-094
+Footprint for mini circuit case CD542, Land pattern PL-094, pads 5 and 2 connected via insulated copper area below body, vias included (case drawing: https://ww2.minicircuits.com/case_style/CD542.pdf, land pattern drawing: https://ww2.minicircuits.com/pcb/98-pl094.pdf)
+mini-circuits CD542 pl-094
+0
+18
+6
+RF_Mini-Circuits
+Mini-Circuits_CD636_H4.11mm
+https://ww2.minicircuits.com/case_style/CD636.pdf
+RF Transformer
+0
+6
+6
+RF_Mini-Circuits
+Mini-Circuits_CD636_LandPatternPL-035
+Footprint for Mini-Circuits case CD636 (https://ww2.minicircuits.com/case_style/CD636.pdf) following land pattern PL-035, including GND-vias (https://ww2.minicircuits.com/pcb/98-pl035.pdf)
+mini-circuits pl-035 CD636
+0
+13
+6
+RF_Mini-Circuits
+Mini-Circuits_CD637_H5.23mm
+https://ww2.minicircuits.com/case_style/CD637.pdf
+RF Transformer
+0
+6
+6
+RF_Mini-Circuits
+Mini-Circuits_CK605
+Footprint for Mini-Circuits case CK605 (https://ww2.minicircuits.com/case_style/CK605.pdf)
+Mini-Circuits CK605
+0
+16
+16
+RF_Mini-Circuits
+Mini-Circuits_CK605_LandPatternPL-012
+Footprint for Mini-Circuits case CK605 (https://ww2.minicircuits.com/case_style/CK605.pdf) following land pattern PL-012, including GND vias (https://ww2.minicircuits.com/pcb/98-pl012.pdf)
+Mini-Circuits PL-012
+0
+53
+16
+RF_Mini-Circuits
+Mini-Circuits_DB1627
+Mini-Circuits top-hat case DB1627 (https://ww2.minicircuits.com/case_style/DB1627.pdf)
+Mini-Circuits DB1627
+0
+6
+6
+RF_Mini-Circuits
+Mini-Circuits_GP731
+Footprint for Mini-Circuits case GP731 (https://ww2.minicircuits.com/case_style/GP731.pdf)
+Mini-Circuits GP731
+0
+8
+8
+RF_Mini-Circuits
+Mini-Circuits_GP731_LandPatternPL-176
+Footprint for Mini-Circuits case GP731 (https://ww2.minicircuits.com/case_style/GP731.pdf) following land pattern PL-176, including GND vias (https://www.minicircuits.com/pcb/98-pl176.pdf)
+mini-circuits PL-176
+0
+21
+8
+RF_Mini-Circuits
+Mini-Circuits_GP1212
+Footprint for Mini-Circuits case GP1212 (https://ww2.minicircuits.com/case_style/GP731.pdf)
+mini-circuits GP1212
+0
+8
+8
+RF_Mini-Circuits
+Mini-Circuits_GP1212_LandPatternPL-176
+Footprint for Mini-Circuits case GP1212 (https://ww2.minicircuits.com/case_style/GP731.pdf) following land pattern PL-176, including GND vias (https://www.minicircuits.com/pcb/98-pl176.pdf)
+mini-circuits PL-176
+0
+21
+8
+RF_Mini-Circuits
+Mini-Circuits_HF1139
+Footprint for Mini-Circuits case HF1139 (https://ww2.minicircuits.com/case_style/HF1139.pdf)
+Mini-Circuits HF1139
+0
+8
+8
+RF_Mini-Circuits
+Mini-Circuits_HF1139_LandPatternPL-230
+Footprint for Mini-Circuits case HF1139 (https://ww2.minicircuits.com/case_style/HF1139.pdf) following land pattern PL-230, including GND vias (https://ww2.minicircuits.com/pcb/98-pl230.pdf)
+Mini-Circuits PL-230
+0
+37
+8
+RF_Mini-Circuits
+Mini-Circuits_HZ1198
+Footprint for Mini-Circuits case HZ1198 (https://ww2.minicircuits.com/case_style/HZ1198.pdf)
+Mini-Circuits HZ1198
+0
+6
+6
+RF_Mini-Circuits
+Mini-Circuits_HZ1198_LandPatternPL-247
+Footprint for Mini-Circuits cas HZ1198 (https://ww2.minicircuits.com/case_style/HZ1198.pdf) following land pattern PL-247, including GND-vias (https://www.minicircuits.com/pcb/98-pl247.pdf)
+Mini-Circuits PL-247 HZ1198
+0
+40
+6
+RF_Mini-Circuits
+Mini-Circuits_MMM168
+Footprint for Mini-Circuits case MMM168 (https://ww2.minicircuits.com/case_style/MMM168.pdf)
+Mini-Circuits MMM168
+0
+4
+4
+RF_Mini-Circuits
+Mini-Circuits_MMM168_LandPatternPL-225
+Footprint for Mini-Circuits case MMM168, Land pattern PL-225, vias included, (case drawing: https://ww2.minicircuits.com/case_style/MMM168.pdf, land pattern drawing: https://ww2.minicircuits.com/pcb/98-pl225.pdf)
+pl-225
+0
+10
+4
+RF_Mini-Circuits
+Mini-Circuits_QQQ130_ClockwisePinNumbering
+Footprint for Mini-Circuits case QQQ130 (https://ww2.minicircuits.com/case_style/QQQ130.pdf)
+Mini-Circuits QQQ130
+0
+6
+6
+RF_Mini-Circuits
+Mini-Circuits_QQQ130_LandPattern_PL-236_ClockwisePinNumbering
+Footprint for Mini-Circuits case QQQ130 (https://ww2.minicircuits.com/case_style/QQQ130.pdf) following land pattern PL-236, including GND vias (https://ww2.minicircuits.com/pcb/98-pl236.pdf)
+Mini-Circuits PL-236
+0
+14
+6
+RF_Mini-Circuits
+Mini-Circuits_TT1224_ClockwisePinNumbering
+Footprint for Mini-Circuits case TT1224 (https://ww2.minicircuits.com/case_style/TT1224.pdf) following land-pattern PL-258, including GND-vias (https://www.minicircuits.com/pcb/98-pl258.pdf)
+Mini-Circuits TT1224
+0
+6
+6
+RF_Mini-Circuits
+Mini-Circuits_TT1224_LandPatternPL-258_ClockwisePinNumbering
+Footprint for Mini-Circuits case TT1224 (https://ww2.minicircuits.com/case_style/TT1224.pdf) following land-pattern PL-258, including GND-vias (https://www.minicircuits.com/pcb/98-pl258.pdf)
+PL-258 Mini-Circuits
+0
+26
+6
+RF_Mini-Circuits
+Mini-Circuits_TTT167
+Footprint for Mini-Circuits case TTT167 (https://ww2.minicircuits.com/case_style/TTT167.pdf)
+Mini-Circuits TTT167
+0
+6
+6
+RF_Mini-Circuits
+Mini-Circuits_TTT167_LandPatternPL-079
+Footprint for Mini-Circuits case TTT167 (Mini-Circuits_TTT167_LandPatternPL-079) following land pattern PL-079, including GND vias (https://ww2.minicircuits.com/pcb/98-pl079.pdf)
+Mini-Circuits PL-079
+0
+36
+6
+RF_Mini-Circuits
+Mini-Circuits_YY161
+Footprint for Mini-Circuits case YY161 (https://ww2.minicircuits.com/case_style/YY161.pdf)
+Mini-Circuits YY161
+0
+8
+8
+RF_Mini-Circuits
+Mini-Circuits_YY161_LandPatternPL-049
+Footprint for Mini-Circuits case YY161 (https://ww2.minicircuits.com/case_style/YY161.pdf) using land-pattern PL-049, including GND-connections and vias (https://ww2.minicircuits.com/pcb/98-pl049.pdf)
+mini-circuits pl-049
+0
+36
+8
+RF_Module
+Ai-Thinker-Ra-01-LoRa
+Ai Thinker Ra-01 LoRa
+LoRa Ra-01
+0
+16
+16
+RF_Module
+Atmel_ATSAMR21G18-MR210UA_NoRFPads
+http://ww1.microchip.com/downloads/en/devicedoc/atmel-42475-atsamr21g18-mr210ua_datasheet.pdf
+module wireless zigbee 802.15.4 flash crypto ATSAMR21G18 AT45DB041E  TECC508A U.Fi
+0
+42
+42
+RF_Module
+BLE112-A
+Class 4 Bluetooth Module with on-board antenna
+Bluetooth Module
+0
+30
+30
+RF_Module
+CMWX1ZZABZ
+https://wireless.murata.com/RFM/data/type_abz.pdf
+iot lora sigfox
+0
+57
+57
+RF_Module
+CYBLE-21Pin-10x10mm
+Cypress EZ-BLE PRoC Module (Bluetooth Smart) 21 Pin Module
+Cypress BT Bluetooth
+0
+21
+21
+RF_Module
+DWM1000
+IEEE802.15.4-2011 UWB
+UWB Module
+0
+24
+24
+RF_Module
+DecaWave_DWM1001
+https://www.decawave.com/sites/default/files/dwm1001_datasheet.pdf
+UWB module
+0
+34
+34
+RF_Module
+Digi_XBee_SMT
+http://www.digi.com/resources/documentation/digidocs/pdfs/90002126.pdf http://ftp1.digi.com/support/documentation/90001020_F.pdf
+Digi XBee SMT RF
+0
+37
+37
+RF_Module
+E18-MS1-PCB
+http://www.cdebyte.com/en/downpdf.aspx?id=122
+Zigbee
+0
+24
+24
+RF_Module
+E73-2G4M04S
+http://www.cdebyte.com/en/downpdf.aspx?id=243
+BLE BLE5 nRF52832
+0
+44
+44
+RF_Module
+ESP-07
+Wi-Fi Module, http://wiki.ai-thinker.com/_media/esp8266/docs/a007ps01a2_esp-07_product_specification_v1.2.pdf
+Wi-Fi Module
+0
+16
+16
+RF_Module
+ESP-12E
+Wi-Fi Module, http://wiki.ai-thinker.com/_media/esp8266/docs/aithinker_esp_12f_datasheet_en.pdf
+Wi-Fi Module
+0
+22
+22
+RF_Module
+ESP-WROOM-02
+http://espressif.com/sites/default/files/documentation/0c-esp-wroom-02_datasheet_en.pdf
+ESP WROOM-02 espressif esp8266ex
+0
+19
+19
+RF_Module
+ESP32-WROOM-32
+Single 2.4 GHz Wi-Fi and Bluetooth combo chip https://www.espressif.com/sites/default/files/documentation/esp32-wroom-32_datasheet_en.pdf
+Single 2.4 GHz Wi-Fi and Bluetooth combo  chip
+0
+39
+39
+RF_Module
+ESP32-WROOM-32U
+Single 2.4 GHz Wi-Fi and Bluetooth combo chip with U.FL connector, https://www.espressif.com/sites/default/files/documentation/esp32-wroom-32d_esp32-wroom-32u_datasheet_en.pdf
+Single 2.4 GHz Wi-Fi and Bluetooth combo  chip
+0
+39
+39
+RF_Module
+Garmin_M8-35_9.8x14.0mm_Layout6x6_P1.5mm
+D52M ANT SoC Module https://www.thisisant.com/assets/resources/D00001687_D52_Module_Datasheet.v.2.3_(Garmin).pdf
+RF SoC Radio ANT Bluetooth BLE D52 nRF52 Garmin Canada Dynastream Nordic
+0
+35
+35
+RF_Module
+HOPERF_RFM9XW_SMD
+Low Power Long Range Transceiver Module SMD-16 (https://www.hoperf.com/data/upload/portal/20181127/5bfcbea20e9ef.pdf)
+LoRa Low Power Long Range Transceiver Module
+0
+16
+16
+RF_Module
+HOPERF_RFM9XW_THT
+Low Power Long Range Transceiver Module THT-16 (https://www.hoperf.com/data/upload/portal/20181127/5bfcbea20e9ef.pdf)
+Low Power Long Range Transceiver Module LoRa
+0
+16
+16
+RF_Module
+HOPERF_RFM69HW
+Radio, RF, Module, http://www.hoperf.com/upload/rf/RFM69HW-V1.3.pdf
+Radio RF Module
+0
+16
+16
+RF_Module
+IQRF_TRx2DA_KON-SIM-01
+8 pin SIM connector for IQRF TR-x2DA(T) modules, http://iqrf.org/weben/downloads.php?id=104
+IQRF_KON-SIM-01 IQRF_TRx2DA
+0
+10
+8
+RF_Module
+IQRF_TRx2D_KON-SIM-01
+8 pin SIM connector for IQRF TR-x2D(C)(T) modules, http://iqrf.org/weben/downloads.php?id=104
+IQRF_KON-SIM-01 IQRF_TRx2D IQRF_TRx2DC
+0
+10
+8
+RF_Module
+Laird_BL652
+Bluetooth v4.2 + NFC module
+Bluetooth BLE NFC
+0
+39
+39
+RF_Module
+MOD-nRF8001
+BLE module, https://www.olimex.com/Products/Modules/RF/MOD-nRF8001/
+BLE module
+0
+11
+11
+RF_Module
+Microchip_RN4871
+Microchip RN4871 footprint
+RN4871 BLE
+0
+16
+16
+RF_Module
+Modtronix_inAir9
+Modtronix Wireless SX1276 LoRa Module (http://modtronix.com/img/prod/imod/inair9/inair_dimensions.gif)
+Modtronix LoRa inAir inAir9 SX1276 RF 915MHz 868MHz Wireless
+0
+14
+14
+RF_Module
+MonoWireless_TWE-L-WX
+https://www.mono-wireless.com/jp/products/TWE-LITE/MW-PDS-TWELITE-JP.pdf
+TWE-L-WX
+0
+32
+32
+RF_Module
+Particle_P1
+https://docs.particle.io/datasheets/p1-datasheet/
+Particle P1
+0
+75
+75
+RF_Module
+RFDigital_RFD77101
+RFDigital RFD77101 Simblee
+RFDigital RFD77101 Simblee
+0
+48
+45
+RF_Module
+RN42
+Class 2 Bluetooth Module with on-board antenna
+Bluetooth Module
+0
+36
+33
+RF_Module
+RN42N
+Class 2 Bluetooth Module without antenna
+Bluetooth Module
+0
+39
+36
+RF_Module
+RN2483
+Low-Power Long Range LoRa Transceiver Module
+rf module lora lorawan
+0
+47
+47
+RF_Module
+ST_SPBTLE
+Bluetooth Low Energy Module
+ble module st bluetooth
+0
+11
+11
+RF_Module
+TD1205
+https://github.com/Telecom-Design/Documentation_TD_RF_Module/blob/master/TD1205%20Datasheet.pdf
+SIGFOX Module
+0
+9
+9
+RF_Module
+TD1208
+https://github.com/Telecom-Design/Documentation_TD_RF_Module/blob/master/TD1208%20Datasheet.pdf
+SIGFOX Module
+0
+25
+25
+RF_Module
+Taiyo-Yuden_EYSGJNZWY
+Taiyo Yuden NRF51822 Module Bluetooth https://www.yuden.co.jp/wireless_module/document/datareport2/en/TY_BLE_EYSGJNZ_DataReport_V1_9_20180530E.pdf
+Taiyo Yuden NRF51822 Module Bluetooth 
+0
+30
+28
+RF_Module
+ZETA-433-SO_SMD
+RF transceiver SMD style https://www.rfsolutions.co.uk/downloads/1456219226DS-ZETA.pdf
+RF transceiver SMD style
+0
+12
+12
+RF_Module
+ZETA-433-SO_THT
+RF transceiver THT style https://www.rfsolutions.co.uk/downloads/1456219226DS-ZETA.pdf
+RF transceiver SMD style
+0
+12
+12
+RF_Module
+nRF24L01_Breakout
+nRF24L01 breakout board
+nRF24L01 adapter breakout
+0
+8
+8
+RF_Shielding
+Laird_Technologies_97-2002_25.40x25.40mm
+Laird Technologies 97-2002 EZ PEEL Shielding Cabinet One Piece SMD 25.40x25.40mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+8
+1
+RF_Shielding
+Laird_Technologies_97-2003_12.70x13.37mm
+Laird Technologies 97-2003 EZ PEEL Shielding Cabinet One Piece SMD 12.70x13.37mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+8
+1
+RF_Shielding
+Laird_Technologies_BMI-S-101_13.66x12.70mm
+Laird Technologies BMI-S-101 Shielding Cabinet One Piece SMD 13.66x12.70mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+16
+1
+RF_Shielding
+Laird_Technologies_BMI-S-102_16.50x16.50mm
+Laird Technologies BMI-S-102 Shielding Cabinet One Piece SMD 16.50x16.50mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+16
+1
+RF_Shielding
+Laird_Technologies_BMI-S-103_26.21x26.21mm
+Laird Technologies BMI-S-103 Shielding Cabinet One Piece SMD 26.21x26.21mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+24
+1
+RF_Shielding
+Laird_Technologies_BMI-S-104_32.00x32.00mm
+Laird Technologies BMI-S-104 Shielding Cabinet One Piece SMD 32.00x32.00mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+28
+1
+RF_Shielding
+Laird_Technologies_BMI-S-105_38.10x25.40mm
+Laird Technologies BMI-S-105 Shielding Cabinet One Piece SMD 38.10x25.40mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+28
+1
+RF_Shielding
+Laird_Technologies_BMI-S-106_36.83x33.68mm
+Laird Technologies BMI-S-106 Shielding Cabinet One Piece SMD 36.83x33.68mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+28
+1
+RF_Shielding
+Laird_Technologies_BMI-S-107_44.37x44.37mm
+Laird Technologies BMI-S-107 Shielding Cabinet One Piece SMD 44.37x44.37mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+36
+1
+RF_Shielding
+Laird_Technologies_BMI-S-201-F_13.66x12.70mm
+Laird Technologies BMI-S-201-F Shielding Cabinet Two Piece SMD 13.66x12.70mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+16
+1
+RF_Shielding
+Laird_Technologies_BMI-S-202-F_16.50x16.50mm
+Laird Technologies BMI-S-202-F Shielding Cabinet Two Piece SMD 16.50x16.50mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+16
+1
+RF_Shielding
+Laird_Technologies_BMI-S-203-F_26.21x26.21mm
+Laird Technologies BMI-S-203-F Shielding Cabinet Two Piece SMD 26.21x26.21mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+24
+1
+RF_Shielding
+Laird_Technologies_BMI-S-204-F_32.00x32.00mm
+Laird Technologies BMI-S-204-F Shielding Cabinet Two Piece SMD 32.00x32.00mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+28
+1
+RF_Shielding
+Laird_Technologies_BMI-S-205-F_38.10x25.40mm
+Laird Technologies BMI-S-205-F Shielding Cabinet Two Piece SMD 38.10x25.40mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+28
+1
+RF_Shielding
+Laird_Technologies_BMI-S-206-F_36.83x33.68mm
+Laird Technologies BMI-S-206-F Shielding Cabinet Two Piece SMD 36.83x33.68mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+28
+1
+RF_Shielding
+Laird_Technologies_BMI-S-207-F_44.37x44.37mm
+Laird Technologies BMI-S-207-F Shielding Cabinet Two Piece SMD 44.37x44.37mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+36
+1
+RF_Shielding
+Laird_Technologies_BMI-S-208-F_39.60x39.60mm
+Laird Technologies BMI-S-208-F Shielding Cabinet Two Piece SMD 39.60x39.60mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+32
+1
+RF_Shielding
+Laird_Technologies_BMI-S-209-F_29.36x18.50mm
+Laird Technologies BMI-S-209-F Shielding Cabinet Two Piece SMD 29.36x18.50mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+20
+1
+RF_Shielding
+Laird_Technologies_BMI-S-210-F_44.00x30.50mm
+Laird Technologies BMI-S-210-F Shielding Cabinet Two Piece SMD 44.00x30.50mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf)
+Shielding Cabinet
+0
+32
+1
+RF_Shielding
+Laird_Technologies_BMI-S-230-F_50.8x38.1mm
+Laird Technologies BMI-S-230-F Shielding Cabinet Two Piece SMD 50.8x38.1mm
+Shielding Cabinet
+0
+36
+1
+RF_Shielding
+Wuerth_36103205_20x20mm
+WE-SHC Shielding Cabinet SMD 20x20mm
+Shielding Cabinet
+0
+20
+1
+RF_Shielding
+Wuerth_36103255_25x25mm
+WE-SHC Shielding Cabinet SMD 25x25mm
+Shielding Cabinet
+0
+24
+1
+RF_Shielding
+Wuerth_36103305_30x30mm
+WE-SHC Shielding Cabinet SMD 30x30mm
+Shielding Cabinet
+0
+28
+1
+RF_Shielding
+Wuerth_36103505_50x50mm
+WE-SHC Shielding Cabinet SMD 50x50mm
+Shielding Cabinet
+0
+44
+1
+RF_Shielding
+Wuerth_36103605_60x60mm
+WE-SHC Shielding Cabinet SMD 60x60mm
+Shielding Cabinet
+0
+52
+1
+RF_Shielding
+Wuerth_36503205_20x20mm
+WE-SHC Shielding Cabinet THT 21x21mm
+Shielding Cabinet
+0
+16
+1
+RF_Shielding
+Wuerth_36503255_25x25mm
+WE-SHC Shielding Cabinet THT 26x26mm
+Shielding Cabinet
+0
+20
+1
+RF_Shielding
+Wuerth_36503305_30x30mm
+WE-SHC Shielding Cabinet THT 31x31mm
+Shielding Cabinet
+0
+24
+1
+RF_Shielding
+Wuerth_36503505_50x50mm
+WE-SHC Shielding Cabinet THT 51x51mm
+Shielding Cabinet
+0
+40
+1
+RF_Shielding
+Wuerth_36503605_60x60mm
+WE-SHC Shielding Cabinet THT 61x61mm
+Shielding Cabinet
+0
+48
+1
+RF_WiFi
+USR-C322
+https://www.usriot.com/download/WIFI/USR-C322-Hardware-Manual_V1.2.01.pdf
+WiFi IEEE802.11 b/g/n
+0
+44
+44
+Relay_SMD
+Relay_DPDT_AXICOM_IMSeries_JLeg
+http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Specification+Or+Standard%7F108-98001%7FW5%7Fpdf%7FEnglish%7FENG_SS_108-98001_W5.pdf
+AXICOM IM-Series Relay J JLeg
+0
+8
+8
+Relay_SMD
+Relay_DPDT_FRT5_SMD
+IM Signal Relay DPDT FRT5 narrow footprint, SMD version of package
+Relay DPDT IM-relay FRT5
+0
+10
+10
+Relay_SMD
+Relay_DPDT_Omron_G6H-2F
+package for Omron G6H-2F relais, see http://cdn-reichelt.de/documents/datenblatt/C300/G6H%23OMR.pdf
+Omron G6H-2F relais
+0
+10
+10
+Relay_SMD
+Relay_DPDT_Omron_G6K-2F
+Omron G6K-2F relay package http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf
+Omron G6K-2F relay
+0
+8
+8
+Relay_SMD
+Relay_DPDT_Omron_G6K-2F-Y
+Omron G6K-2F-Y relay package http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf
+Omron G6K-2F-Y relay
+0
+8
+8
+Relay_SMD
+Relay_DPDT_Omron_G6K-2G
+Omron G6K-2G relay package http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf
+Omron G6K-2G relay
+0
+8
+8
+Relay_SMD
+Relay_DPDT_Omron_G6K-2G-Y
+Omron G6K-2G-Y relay package http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf
+Omron G6K-2G-Y relay
+0
+8
+8
+Relay_SMD
+Relay_DPDT_Omron_G6S-2F
+Relay Omron G6S-2F, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6s.pdf
+Relay Omron G6S-2F
+0
+8
+8
+Relay_SMD
+Relay_DPDT_Omron_G6S-2G
+Relay Omron G6S-2G, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6s.pdf
+Relay Omron G6S-2G
+0
+8
+8
+Relay_SMD
+Relay_DPDT_Omron_G6SK-2F
+Relay Omron G6SK-2F, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6s.pdf
+Relay Omron G6SK-2F
+0
+10
+10
+Relay_SMD
+Relay_DPDT_Omron_G6SK-2G
+Relay Omron G6SK-2G, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6s.pdf
+Relay Omron G6SK-2G
+0
+10
+10
+Relay_SMD
+Relay_SPDT_AXICOM_HF3Series_50ohms_Pitch1.27mm
+hiqsdr.com/images/3/3e/Axicom-HF3.pdf
+AXICOM HF3-Series Relay Pitch 1.27mm 50ohms
+0
+16
+16
+Relay_SMD
+Relay_SPDT_AXICOM_HF3Series_75ohms_Pitch1.27mm
+hiqsdr.com/images/3/3e/Axicom-HF3.pdf
+AXICOM HF3-Series Relay Pitch 1.27mm 75ohm
+0
+16
+16
+Relay_THT
+Relay_1-Form-A_Schrack-RYII_RM5mm
+Relay, 1-Form-A, Schrack-RYII, RM5mm, SPST-NO
+Relay 1-Form-A Schrack-RYII RM5mm SPST-NO
+0
+4
+4
+Relay_THT
+Relay_1-Form-B_Schrack-RYII_RM5mm
+Relay, 1-Form-B, Schrack-RYII, RM5mm, SPST-NC
+Relay 1-Form-B Schrack-RYII RM5mm SPST-NC
+0
+4
+4
+Relay_THT
+Relay_1-Form-C_Schrack-RYII_RM3.2mm
+Relay, 1-Form-C, Schrack-RYII, RM3.2mm, SPDT
+Relay 1-Form-C Schrack-RYII RM3.2mm SPDT
+0
+5
+5
+Relay_THT
+Relay_DPDT_AXICOM_IMSeries_Pitch3.2mm
+AXICOM IM-Series Relays, DPDR, Pitch 3.2mm, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Specification+Or+Standard%7F108-98001%7FV%7Fpdf%7FEnglish%7FENG_SS_108-98001_V_IM_0614_v1.pdf%7F4-1462039-1
+AXICOM IM-Series Relay DPDR Pitch 3.2mm
+0
+8
+8
+Relay_THT
+Relay_DPDT_AXICOM_IMSeries_Pitch5.08mm
+AXICOM IM-Series Relays, DPDR, Pitch 5.08
+AXICOM IM-Series Relay DPDR Pitch 5.08
+0
+8
+8
+Relay_THT
+Relay_DPDT_FRT5
+IM Signal Relay DPDT FRT5 narrow footprint
+Relay DPDT IM-relay FRT5
+0
+10
+10
+Relay_THT
+Relay_DPDT_Finder_30.22
+Finder 32.21-x000 Relay, DPDT, https://gfinder.findernet.com/public/attachments/30/EN/S30EN.pdf
+AXICOM IM-Series Relay SPDT
+0
+8
+8
+Relay_THT
+Relay_DPDT_Finder_40.52
+Relay DPDT Finder 40.52, Pitch 5mm/7.5mm, https://www.finder-relais.net/de/finder-relais-serie-40.pdf
+Relay DPDT Finder 40.52 Pitch 5mm
+0
+8
+8
+Relay_THT
+Relay_DPDT_Fujitsu_FTR-F1C
+https://www.fujitsu.com/downloads/MICRO/fcai/relays/ftr-f1.pdf
+relay dpdt fujitsu tht
+0
+8
+8
+Relay_THT
+Relay_DPDT_Omron_G5V-2
+http://omronfs.omron.com/en_US/ecb/products/pdf/en-g5v2.pdf
+Omron G5V-2 Relay DPDT
+0
+8
+8
+Relay_THT
+Relay_DPDT_Omron_G6H-2
+Omron relay G6H-2, see http://cdn-reichelt.de/documents/datenblatt/C300/G6H%23OMR.pdf
+Omron relay G6H-2
+0
+10
+10
+Relay_THT
+Relay_DPDT_Omron_G6K-2P
+Omron G6K-2P relay package http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf
+Omron G6K-2P relay
+0
+8
+8
+Relay_THT
+Relay_DPDT_Omron_G6K-2P-Y
+Omron G6K-2P-Y relay package http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf
+Omron G6K-2P-Y relay
+0
+8
+8
+Relay_THT
+Relay_DPDT_Omron_G6S-2
+Relay Omron G6S-2, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6s.pdf
+Relay Omron G6S-2
+0
+8
+8
+Relay_THT
+Relay_DPDT_Omron_G6SK-2
+Relay Omron G6SK-2, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6s.pdf
+Relay Omron G6SK-2
+0
+10
+10
+Relay_THT
+Relay_DPDT_Panasonic_JW2
+Panasonic Relay DPDT, http://www3.panasonic.biz/ac/e_download/control/relay/power/catalog/mech_eng_jw.pdf?via=ok
+Panasonic Relay DPDT
+0
+8
+8
+Relay_THT
+Relay_DPDT_Schrack-RT2-FormC-Dual-Coil_RM5mm
+Relay DPDT Schrack-RT2 RM5mm 16A 250V AC Form C http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Data+Sheet%7FRT2_bistable%7F1116%7Fpdf%7FEnglish%7FENG_DS_RT2_bistable_1116.pdf%7F1-1415537-8
+Relay DPDT Schrack-RT2 RM5mm 16A 250V AC Relay
+0
+9
+9
+Relay_THT
+Relay_DPDT_Schrack-RT2-FormC_RM5mm
+Relay DPDT Schrack-RT2 RM5mm 16A 250V AC Form C http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=RT2_reflow&DocType=DS&DocLang=EN
+Relay DPDT Schrack-RT2 RM5mm 16A 250V AC Relay
+0
+8
+8
+Relay_THT
+Relay_DPST_Fujitsu_FTR-F1A
+https://www.fujitsu.com/downloads/MICRO/fcai/relays/ftr-f1.pdf
+relay dpst fujitsu tht
+0
+6
+6
+Relay_THT
+Relay_DPST_Schrack-RT2-FormA_RM5mm
+Relay DPST Schrack-RT2 RM5mm 16A 250V AC Form A http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=RT2_reflow&DocType=DS&DocLang=EN
+Relay DPST Schrack-RT2 RM5mm 16A 250V AC Relay
+0
+6
+6
+Relay_THT
+Relay_SPDT_Finder_32.21-x000
+Finder 32.21-x000 Relay, SPDT, https://gfinder.findernet.com/assets/Series/355/S32EN.pdf
+AXICOM IM-Series Relay SPDT
+0
+5
+5
+Relay_THT
+Relay_SPDT_Finder_34.51_Horizontal
+Relay SPDT, Finder Type34.51, horizontal form, see https://gfinder.findernet.com/public/attachments/34/EN/S34USAEN.pdf
+Relay SPDT Finder
+0
+5
+5
+Relay_THT
+Relay_SPDT_Finder_34.51_Vertical
+Relay SPDT, Finder Type34.51, vertical/standing form, see https://gfinder.findernet.com/public/attachments/34/EN/S34USAEN.pdf
+Relay SPDT Finder
+0
+5
+5
+Relay_THT
+Relay_SPDT_Finder_36.11
+FINDER 36.11, SPDT relay, 10A, https://gfinder.findernet.com/public/attachments/36/EN/S36EN.pdf
+spdt relay
+0
+5
+5
+Relay_THT
+Relay_SPDT_Finder_40.11
+Relay SPDT Finder 40.11, https://www.finder-relais.net/de/finder-relais-serie-40.pdf
+Relay SPDT Finder 40.11 
+0
+5
+5
+Relay_THT
+Relay_SPDT_Finder_40.31
+Relay DPDT Finder 40.31, Pitch 3.5mm/7.5mm, https://www.finder-relais.net/de/finder-relais-serie-40.pdf
+Relay DPDT Finder 40.31 Pitch 3.5mm
+0
+5
+5
+Relay_THT
+Relay_SPDT_Finder_40.41
+Relay DPDT Finder 40.41, Pitch 3.5mm/7.5mm, https://www.finder-relais.net/de/finder-relais-serie-40.pdf
+Relay DPDT Finder 40.41 Pitch 3.5mm
+0
+5
+5
+Relay_THT
+Relay_SPDT_Finder_40.51
+Relay DPDT Finder 40.51, Pitch 5mm/7.5mm, https://www.finder-relais.net/de/finder-relais-serie-40.pdf
+Relay DPDT Finder 40.51 Pitch 5mm
+0
+5
+5
+Relay_THT
+Relay_SPDT_HJR-4102
+IM Signal Relay SPDT HJR-4102
+Relay SPDT IM-relay HJR-4102
+0
+6
+6
+Relay_THT
+Relay_SPDT_HsinDa_Y14
+http://www.hsinda.com.cn/en/ProductShow.asp?ID=208
+Relay Y14
+0
+6
+6
+Relay_THT
+Relay_SPDT_Omron-G5LE-1
+Omron Relay SPDT, http://www.omron.com/ecb/products/pdf/en-g5le.pdf
+Omron Relay SPDT
+0
+5
+5
+Relay_THT
+Relay_SPDT_Omron-G5Q-1
+Relay SPDT Omron Serie G5Q, http://omronfs.omron.com/en_US/ecb/products/pdf/en-g5q.pdf
+Relay SPDT Omron Serie G5Q
+0
+5
+5
+Relay_THT
+Relay_SPDT_Omron_G5V-1
+Relay Omron G5V-1, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g5v_1.pdf
+Relay Omron G5V-1
+0
+6
+6
+Relay_THT
+Relay_SPDT_Omron_G6E
+Relay SPDT Omron Serie G6E
+Relay SPDT Omron Serie G6E 1x um
+0
+5
+5
+Relay_THT
+Relay_SPDT_Omron_G6EK
+Relay SPDT Omron Serie G6EK, see http://www.logosfoundation.org/instrum_gwr/pi/Omron_G6E_134P.pdf
+Relay SPDT Omron Serie G6EK
+0
+6
+6
+Relay_THT
+Relay_SPDT_Panasonic_JW1_FormC
+Panasonic Relay SPDT, http://www3.panasonic.biz/ac/e_download/control/relay/power/catalog/mech_eng_jw.pdf?via=ok
+Panasonic Relay SPDT
+0
+5
+5
+Relay_THT
+Relay_SPDT_PotterBrumfield_T9AP5D52_12V30A
+Relay SPDT Potter&Brumfield T9AP5D52 12V 30A 1xUn Connector Fast ON Only Dummy for Space NO Pads
+Relay SPDT Potter&Brumfield T9AP5D52 12V 30A 1xUm Connector Fast ON Flachsteckeranschluss Only Dummy for Space NO Pads
+0
+0
+0
+Relay_THT
+Relay_SPDT_RAYEX-L90
+https://a3.sofastcdn.com/attachment/7jioKBjnRiiSrjrjknRiwS77gwbf3zmp/L90-SERIES.pdf
+Relay RAYEX L90 SPDT
+0
+6
+6
+Relay_THT
+Relay_SPDT_RAYEX-L90S
+https://a3.sofastcdn.com/attachment/7jioKBjnRiiSrjrjknRiwS77gwbf3zmp/L90-SERIES.pdf
+Relay RAYEX L90S SPDT
+0
+5
+5
+Relay_THT
+Relay_SPDT_SANYOU_SRD_Series_Form_C
+relay Sanyou SRD series Form C http://www.sanyourelay.ca/public/products/pdf/SRD.pdf
+relay Sanyu SRD form C
+0
+5
+5
+Relay_THT
+Relay_SPDT_Schrack-RP-II-1-16A-FormC_RM5mm
+Relay SPST Schrack-RP-II/1 RM5mm 16A 250V AC Form C http://image.schrack.com/datenblaetter/h_rp810012-b.pdf
+Relay SPST Schrack-RP-II/1 RM5mm 16A 250V AC Relay
+0
+8
+5
+Relay_THT
+Relay_SPDT_Schrack-RP-II-1-FormC_RM3.5mm
+Relay SPST Schrack-RP-II/1 RM3.5mm 8A 250V AC Form C http://image.schrack.com/datenblaetter/h_rp810012-b.pdf
+Relay SPST Schrack-RP-II/1 RM3.5mm 8A 250V AC Relay
+0
+5
+5
+Relay_THT
+Relay_SPDT_Schrack-RP-II-1-FormC_RM5mm
+Relay SPST Schrack-RP-II/1 RM5mm 8A 250V AC Form C http://image.schrack.com/datenblaetter/h_rp810012-b.pdf
+Relay SPST Schrack-RP-II/1 RM5mm 8A 250V AC Relay
+0
+5
+5
+Relay_THT
+Relay_SPDT_Schrack-RT1-16A-FormC_RM5mm
+Relay SPST Schrack-RT1 RM5mm 16A 250V AC Form C http://image.schrack.com/datenblaetter/h_rt114012--_de.pdf
+Relay SPST Schrack-RT1 RM5mm 16A 250V AC Relay
+0
+8
+5
+Relay_THT
+Relay_SPDT_Schrack-RT1-FormC_RM3.5mm
+Relay SPST Schrack-RT1 RM3.5mm 8A 250V AC Form C http://image.schrack.com/datenblaetter/h_rt114012--_de.pdf
+Relay SPST Schrack-RT1 RM3.5mm 8A 250V AC Relay
+0
+5
+5
+Relay_THT
+Relay_SPDT_Schrack-RT1-FormC_RM5mm
+Relay SPST Schrack-RT1 RM5mm 8A 250V AC Form C http://image.schrack.com/datenblaetter/h_rt114012--_de.pdf
+Relay SPST Schrack-RT1 RM5mm 8A 250V AC Relay
+0
+5
+5
+Relay_THT
+Relay_SPDT_StandexMeder_SIL_Form1C
+Standex-Meder SIL-relais, Form 1C, see https://standexelectronics.com/wp-content/uploads/datasheet_reed_relay_SIL.pdf
+Standex Meder SIL reed relais
+0
+5
+5
+Relay_THT
+Relay_SPST_Finder_32.21-x300
+Finder 32.21-x300 Relay, SPST, https://gfinder.findernet.com/assets/Series/355/S32EN.pdf
+Finder 32.21-x300 Relay SPST
+0
+4
+4
+Relay_THT
+Relay_SPST_Omron-G5Q-1A
+Relay SPST-NO Omron Serie G5Q, http://omronfs.omron.com/en_US/ecb/products/pdf/en-g5q.pdf
+Relay SPST-NO Omron Serie G5Q
+0
+4
+4
+Relay_THT
+Relay_SPST_Panasonic_JW1_FormA
+Panasonic Relay SPST, http://www3.panasonic.biz/ac/e_download/control/relay/power/catalog/mech_eng_jw.pdf?via=ok
+Panasonic Relay SPST
+0
+4
+4
+Relay_THT
+Relay_SPST_PotterBrumfield_T9AP1D52_12V30A
+Relay SPST Potter&Brumfield T9AP1D52 12V 30A 1xEin Connector Fast ON Only Dummy for Space NO Pads
+Relau SPST Potter&Brumfield T9AP1D52 12V 30A 1xEin Connector Fast ON Flachsteckeranschluss Only Dummy for Space NO Pads
+0
+0
+0
+Relay_THT
+Relay_SPST_RAYEX-L90A
+https://a3.sofastcdn.com/attachment/7jioKBjnRiiSrjrjknRiwS77gwbf3zmp/L90-SERIES.pdf
+Relay RAYEX L90A SPST NO
+0
+5
+5
+Relay_THT
+Relay_SPST_RAYEX-L90AS
+https://a3.sofastcdn.com/attachment/7jioKBjnRiiSrjrjknRiwS77gwbf3zmp/L90-SERIES.pdf
+Relay RAYEX L90AS SPST NO
+0
+4
+4
+Relay_THT
+Relay_SPST_RAYEX-L90B
+https://a3.sofastcdn.com/attachment/7jioKBjnRiiSrjrjknRiwS77gwbf3zmp/L90-SERIES.pdf
+Relay RAYEX L90B SPST NC
+0
+5
+5
+Relay_THT
+Relay_SPST_RAYEX-L90BS
+https://a3.sofastcdn.com/attachment/7jioKBjnRiiSrjrjknRiwS77gwbf3zmp/L90-SERIES.pdf
+Relay RAYEX L90BS SPST NC
+0
+4
+4
+Relay_THT
+Relay_SPST_SANYOU_SRD_Series_Form_A
+relay Sanyou SRD series Form A http://www.sanyourelay.ca/public/products/pdf/SRD.pdf
+relay Sanyu SRD form A
+0
+4
+4
+Relay_THT
+Relay_SPST_SANYOU_SRD_Series_Form_B
+relay Sanyou SRD series Form B opener http://www.sanyourelay.ca/public/products/pdf/SRD.pdf
+relay Sanyu SRD form B opener
+0
+4
+4
+Relay_THT
+Relay_SPST_Schrack-RP-II-1-16A-FormA_RM5mm
+Relay SPST Schrack-RP-II/1 RM5mm 16A 250V AC Form A http://image.schrack.com/datenblaetter/h_rp810012-b.pdf
+Relay SPST Schrack-RP-II/1 RM5mm 16A 250V AC Relay
+0
+6
+4
+Relay_THT
+Relay_SPST_Schrack-RP-II-1-FormA_RM3.5mm
+Relay SPST Schrack-RP-II/1 RM3.5mm 8A 250V AC Form A
+Relay SPST Schrack-RP-II/1 RM3.5mm 8A 250V AC Relay
+0
+4
+4
+Relay_THT
+Relay_SPST_Schrack-RP-II-1-FormA_RM5mm
+Relay SPST Schrack-RP-II/1 RM5mm 8A 250V AC Form A http://image.schrack.com/datenblaetter/h_rp810012-b.pdf
+Relay SPST Schrack-RP-II/1 RM5mm 8A 250V AC Relay
+0
+4
+4
+Relay_THT
+Relay_SPST_Schrack-RP3SL-1coil_RM5mm
+Relay SPST Schrack-RP3SL, 1-coil-version, RM5mm 16A 250V AC Form A http://www.alliedelec.com/m/d/543c6bed18bf23a83ae5238947033ee0.pdf
+Relay SPST Schrack-RP3SL RM5mm 16A 250V AC Relay
+0
+6
+4
+Relay_THT
+Relay_SPST_Schrack-RP3SL_RM5mm
+Relay SPST Schrack-RP3SL RM5mm 16A 250V AC Form A http://www.alliedelec.com/m/d/543c6bed18bf23a83ae5238947033ee0.pdf
+Relay SPST Schrack-RP3SL RM5mm 16A 250V AC Relay
+0
+7
+5
+Relay_THT
+Relay_SPST_Schrack-RT1-16A-FormA_RM5mm
+Relay SPST Schrack-RT2 RM5mm 16A 250V AC Form C http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=RT2_reflow&DocType=DS&DocLang=EN
+Relay SPST Schrack-RT2 RM5mm 16A 250V AC Relay
+0
+6
+4
+Relay_THT
+Relay_SPST_Schrack-RT1-FormA_RM3.5mm
+Relay SPST Schrack-RT1 RM3.5mm 8A 250V AC Form A
+Relay SPST Schrack-RT1 RM3.5mm 8A 250V AC Relay
+0
+4
+4
+Relay_THT
+Relay_SPST_Schrack-RT1-FormA_RM5mm
+Relay SPST Schrack-RT1 RM5mm 8A 250V AC Form C http://image.schrack.com/datenblaetter/h_rt114012--_de.pdf
+Relay SPST Schrack-RT1 RM5mm 8A 250V AC Relay
+0
+4
+4
+Relay_THT
+Relay_SPST_StandexMeder_MS_Form1AB
+Standex-Meder MS SIL-relais, Form 1A/1B, see https://standexelectronics.com/de/produkte/ms-reed-relais/
+Standex Meder MS SIL reed relais
+0
+4
+4
+Relay_THT
+Relay_SPST_StandexMeder_SIL_Form1A
+Standex-Meder SIL-relais, Form 1A, see https://standexelectronics.com/wp-content/uploads/datasheet_reed_relay_SIL.pdf
+Standex Meder SIL reed relais
+0
+4
+4
+Relay_THT
+Relay_SPST_StandexMeder_SIL_Form1B
+Standex-Meder SIL-relais, Form 1B, see https://standexelectronics.com/wp-content/uploads/datasheet_reed_relay_SIL.pdf
+Standex Meder SIL reed relais
+0
+4
+4
+Relay_THT
+Relay_SPST_TE_PCH-1xxx2M
+Miniature PCB Relay, PCH Series, 1 Form A (NO), SPST http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Data+Sheet%7FPCH_series_relay_data_sheet_E%7F1215%7Fpdf%7FEnglish%7FENG_DS_PCH_series_relay_data_sheet_E_1215.pdf
+Relay SPST NO
+0
+4
+4
+Relay_THT
+Relay_SPST_TE_PCN-1xxD3MHZ
+https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1461491%7FG2%7Fpdf%7FEnglish%7FENG_CD_1461491_G2.pdf%7F3-1461491-0
+SPST relay slim
+0
+4
+4
+Relay_THT
+Relay_Socket_DPDT_Finder_96.12
+https://gfinder.findernet.com/public/attachments/56/DE/S56DE.pdf
+Relay socket DPDT Finder 96.12 56.32
+0
+8
+8
+Relay_THT
+Relay_StandexMeder_DIP_HighProfile
+package for Standex Meder DIP reed relay series, see https://standexelectronics.com/wp-content/uploads/datasheet_reed_relay_DIP.pdf
+DIL DIP PDIP 2.54mm 7.62mm 300mil reed relay
+0
+8
+8
+Relay_THT
+Relay_StandexMeder_DIP_LowProfile
+package for Standex Meder DIP reed relay series, see https://standexelectronics.com/wp-content/uploads/datasheet_reed_relay_DIP.pdf
+DIL DIP PDIP 2.54mm 7.62mm 300mil reed relay
+0
+8
+8
+Relay_THT
+Relay_StandexMeder_UMS
+Standex-Meder SIL-relais, UMS, see http://cdn-reichelt.de/documents/datenblatt/C300/UMS05_1A80_75L_DB.pdf
+Standex Meder SIL reed relais
+0
+4
+4
+Resistor_SMD
+R_0201_0603Metric
+Resistor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator
+resistor
+0
+4
+2
+Resistor_SMD
+R_0402_1005Metric
+Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_0603_1608Metric
+Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_0603_1608Metric_Pad1.05x0.95mm_HandSolder
+Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_0612_1632Metric
+Resistor SMD 0612 (1632 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_0612_1632Metric_Pad1.18x3.40mm_HandSolder
+Resistor SMD 0612 (1632 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_0805_2012Metric
+Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_0805_2012Metric_Pad1.15x1.40mm_HandSolder
+Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_0815_2038Metric
+Resistor SMD 0815 (2038 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.yageo.com/documents/recent/PYu-PRPFPH_521_RoHS_L_0.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_0815_2038Metric_Pad1.53x4.00mm_HandSolder
+Resistor SMD 0815 (2038 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.yageo.com/documents/recent/PYu-PRPFPH_521_RoHS_L_0.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_01005_0402Metric
+Resistor SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator
+resistor
+0
+4
+2
+Resistor_SMD
+R_1020_2550Metric
+Resistor SMD 1020 (2550 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_1020_2550Metric_Pad1.33x5.20mm_HandSolder
+Resistor SMD 1020 (2550 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_1206_3216Metric
+Resistor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_1206_3216Metric_Pad1.42x1.75mm_HandSolder
+Resistor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_1210_3225Metric
+Resistor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_1210_3225Metric_Pad1.42x2.65mm_HandSolder
+Resistor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_1218_3246Metric
+Resistor SMD 1218 (3246 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20035/dcrcwe3.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_1218_3246Metric_Pad1.22x4.75mm_HandSolder
+Resistor SMD 1218 (3246 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.vishay.com/docs/20035/dcrcwe3.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_1806_4516Metric
+Resistor SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_1806_4516Metric_Pad1.57x1.80mm_HandSolder
+Resistor SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_1812_4532Metric
+Resistor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_1812_4532Metric_Pad1.30x3.40mm_HandSolder
+Resistor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_2010_5025Metric
+Resistor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_2010_5025Metric_Pad1.52x2.65mm_HandSolder
+Resistor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_2512_6332Metric
+Resistor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_2512_6332Metric_Pad1.52x3.35mm_HandSolder
+Resistor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_2816_7142Metric
+Resistor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_2816_7142Metric_Pad3.20x4.45mm_HandSolder
+Resistor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_4020_10251Metric
+Resistor SMD 4020 (10251 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://datasheet.octopart.com/HVC0603T5004FET-Ohmite-datasheet-26699797.pdf), generated with kicad-footprint-generator
+resistor
+0
+2
+2
+Resistor_SMD
+R_4020_10251Metric_Pad1.65x5.30mm_HandSolder
+Resistor SMD 4020 (10251 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://datasheet.octopart.com/HVC0603T5004FET-Ohmite-datasheet-26699797.pdf), generated with kicad-footprint-generator
+resistor handsolder
+0
+2
+2
+Resistor_SMD
+R_Array_Concave_2x0603
+Thick Film Chip Resistor Array, Wave soldering, Vishay CRA06P (see cra06p.pdf)
+resistor array
+0
+4
+4
+Resistor_SMD
+R_Array_Concave_4x0402
+Thick Film Chip Resistor Array, Wave soldering, Vishay CRA04P (see cra04p.pdf)
+resistor array
+0
+8
+8
+Resistor_SMD
+R_Array_Concave_4x0603
+Thick Film Chip Resistor Array, Wave soldering, Vishay CRA06P (see cra06p.pdf)
+resistor array
+0
+8
+8
+Resistor_SMD
+R_Array_Convex_2x0402
+Chip Resistor Network, ROHM MNR02 (see mnr_g.pdf)
+resistor array
+0
+4
+4
+Resistor_SMD
+R_Array_Convex_2x0603
+Chip Resistor Network, ROHM MNR12 (see mnr_g.pdf)
+resistor array
+0
+4
+4
+Resistor_SMD
+R_Array_Convex_2x0606
+Precision Thin Film Chip Resistor Array, VISHAY (see http://www.vishay.com/docs/28770/acasat.pdf)
+resistor array
+0
+4
+4
+Resistor_SMD
+R_Array_Convex_2x1206
+Chip Resistor Network, ROHM MNR32 (see mnr_g.pdf)
+resistor array
+0
+4
+4
+Resistor_SMD
+R_Array_Convex_4x0402
+Chip Resistor Network, ROHM MNR04 (see mnr_g.pdf)
+resistor array
+0
+8
+8
+Resistor_SMD
+R_Array_Convex_4x0603
+Chip Resistor Network, ROHM MNR14 (see mnr_g.pdf)
+resistor array
+0
+8
+8
+Resistor_SMD
+R_Array_Convex_4x0612
+Precision Thin Film Chip Resistor Array, VISHAY (see http://www.vishay.com/docs/28770/acasat.pdf)
+resistor array
+0
+8
+8
+Resistor_SMD
+R_Array_Convex_4x1206
+Chip Resistor Network, ROHM MNR34 (see mnr_g.pdf)
+resistor array
+0
+8
+8
+Resistor_SMD
+R_Array_Convex_5x0603
+Chip Resistor Network, ROHM MNR15 (see mnr_g.pdf)
+resistor array
+0
+10
+10
+Resistor_SMD
+R_Array_Convex_5x1206
+Chip Resistor Network, ROHM MNR35 (see mnr_g.pdf)
+resistor array
+0
+10
+10
+Resistor_SMD
+R_Array_Convex_8x0602
+Chip Resistor Network, ROHM MNR18 (see mnr_g.pdf)
+resistor array
+0
+16
+16
+Resistor_SMD
+R_Cat16-2
+SMT resistor net, Bourns CAT16 series, 2 way
+SMT resistor net Bourns CAT16 series 2 way
+0
+4
+4
+Resistor_SMD
+R_Cat16-4
+SMT resistor net, Bourns CAT16 series, 4 way
+SMT resistor net Bourns CAT16 series 4 way
+0
+8
+8
+Resistor_SMD
+R_Cat16-8
+SMT resistor net, Bourns CAT16 series, 8 way
+SMT resistor net Bourns CAT16 series 8 way
+0
+16
+16
+Resistor_SMD
+R_MELF_MMB-0207
+Resistor, MELF, MMB-0207, http://www.vishay.com/docs/28713/melfprof.pdf
+MELF Resistor
+0
+2
+2
+Resistor_SMD
+R_MicroMELF_MMU-0102
+Resistor, MicroMELF, MMU-0102, http://www.vishay.com/docs/28713/melfprof.pdf
+MicroMELF Resistor
+0
+2
+2
+Resistor_SMD
+R_MiniMELF_MMA-0204
+Resistor, MiniMELF, MMA-0204, http://www.vishay.com/docs/28713/melfprof.pdf
+MiniMELF Resistor
+0
+2
+2
+Resistor_SMD
+R_Shunt_Ohmite_LVK12
+4 contact shunt resistor
+shunt resistor 4 contacts
+0
+4
+4
+Resistor_SMD
+R_Shunt_Ohmite_LVK20
+4 contacts shunt resistor, https://www.ohmite.com/assets/docs/res_lvk.pdf
+4 contacts resistor smd
+0
+4
+4
+Resistor_SMD
+R_Shunt_Ohmite_LVK24
+4 contacts shunt resistor,https://www.ohmite.com/assets/docs/res_lvk.pdf
+4 contacts resistor smd
+0
+4
+4
+Resistor_SMD
+R_Shunt_Ohmite_LVK25
+4 contacts shunt resistor,https://www.ohmite.com/assets/docs/res_lvk.pdf
+4 contacts resistor smd
+0
+4
+4
+Resistor_SMD
+R_Shunt_Vishay_WSK2512_6332Metric_T1.19mm
+Shunt Resistor SMD 2512 (6332 Metric), 2.6mm thick, Vishay WKS2512, Terminal length (T) 1.19mm, 5 to 200 milli Ohm (http://http://www.vishay.com/docs/30108/wsk.pdf)
+resistor shunt WSK2512
+0
+4
+4
+Resistor_SMD
+R_Shunt_Vishay_WSK2512_6332Metric_T2.21mm
+Shunt Resistor SMD 2512 (6332 Metric), 2.6mm thick, Vishay WKS2512, Terminal length (T) 2.21mm, 1 to 4.9 milli Ohm (http://http://www.vishay.com/docs/30108/wsk.pdf)
+resistor shunt WSK2512
+0
+4
+4
+Resistor_SMD
+R_Shunt_Vishay_WSK2512_6332Metric_T2.66mm
+Shunt Resistor SMD 2512 (6332 Metric), 2.6mm thick, Vishay WKS2512, Terminal length (T) 2.66mm, 0.5 to 0.99 milli Ohm (http://http://www.vishay.com/docs/30108/wsk.pdf)
+resistor shunt WSK2512
+0
+4
+4
+Resistor_SMD
+R_Shunt_Vishay_WSKW0612
+https://www.vishay.com/docs/30332/wskw0612.pdf
+4-Terminal SMD Shunt
+0
+4
+4
+Resistor_SMD
+R_Shunt_Vishay_WSR2_WSR3
+Power Metal Strip Resistors 0.005 to 0.2, https://www.vishay.com/docs/30101/wsr.pdf
+SMD Shunt Resistor
+0
+2
+2
+Resistor_SMD
+R_Shunt_Vishay_WSR2_WSR3_KelvinConnection
+Power Metal Strip Resistors 0.005 to 0.2, https://www.vishay.com/docs/30101/wsr.pdf
+SMD Shunt Resistor
+0
+4
+2
+Resistor_THT
+R_Array_SIP4
+4-pin Resistor SIP pack
+R
+0
+4
+4
+Resistor_THT
+R_Array_SIP5
+5-pin Resistor SIP pack
+R
+0
+5
+5
+Resistor_THT
+R_Array_SIP6
+6-pin Resistor SIP pack
+R
+0
+6
+6
+Resistor_THT
+R_Array_SIP7
+7-pin Resistor SIP pack
+R
+0
+7
+7
+Resistor_THT
+R_Array_SIP8
+8-pin Resistor SIP pack
+R
+0
+8
+8
+Resistor_THT
+R_Array_SIP9
+9-pin Resistor SIP pack
+R
+0
+9
+9
+Resistor_THT
+R_Array_SIP10
+10-pin Resistor SIP pack
+R
+0
+10
+10
+Resistor_THT
+R_Array_SIP11
+11-pin Resistor SIP pack
+R
+0
+11
+11
+Resistor_THT
+R_Array_SIP12
+12-pin Resistor SIP pack
+R
+0
+12
+12
+Resistor_THT
+R_Array_SIP13
+13-pin Resistor SIP pack
+R
+0
+13
+13
+Resistor_THT
+R_Array_SIP14
+14-pin Resistor SIP pack
+R
+0
+14
+14
+Resistor_THT
+R_Axial_DIN0204_L3.6mm_D1.6mm_P1.90mm_Vertical
+Resistor, Axial_DIN0204 series, Axial, Vertical, pin pitch=1.9mm, 0.167W, length*diameter=3.6*1.6mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0204 series Axial Vertical pin pitch 1.9mm 0.167W length 3.6mm diameter 1.6mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0204_L3.6mm_D1.6mm_P2.54mm_Vertical
+Resistor, Axial_DIN0204 series, Axial, Vertical, pin pitch=2.54mm, 0.167W, length*diameter=3.6*1.6mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0204 series Axial Vertical pin pitch 2.54mm 0.167W length 3.6mm diameter 1.6mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0204_L3.6mm_D1.6mm_P5.08mm_Horizontal
+Resistor, Axial_DIN0204 series, Axial, Horizontal, pin pitch=5.08mm, 0.167W, length*diameter=3.6*1.6mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0204 series Axial Horizontal pin pitch 5.08mm 0.167W length 3.6mm diameter 1.6mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0204_L3.6mm_D1.6mm_P5.08mm_Vertical
+Resistor, Axial_DIN0204 series, Axial, Vertical, pin pitch=5.08mm, 0.167W, length*diameter=3.6*1.6mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0204 series Axial Vertical pin pitch 5.08mm 0.167W length 3.6mm diameter 1.6mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal
+Resistor, Axial_DIN0204 series, Axial, Horizontal, pin pitch=7.62mm, 0.167W, length*diameter=3.6*1.6mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0204 series Axial Horizontal pin pitch 7.62mm 0.167W length 3.6mm diameter 1.6mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0207_L6.3mm_D2.5mm_P2.54mm_Vertical
+Resistor, Axial_DIN0207 series, Axial, Vertical, pin pitch=2.54mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0207 series Axial Vertical pin pitch 2.54mm 0.25W = 1/4W length 6.3mm diameter 2.5mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0207_L6.3mm_D2.5mm_P5.08mm_Vertical
+Resistor, Axial_DIN0207 series, Axial, Vertical, pin pitch=5.08mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0207 series Axial Vertical pin pitch 5.08mm 0.25W = 1/4W length 6.3mm diameter 2.5mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal
+Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=7.62mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0207 series Axial Horizontal pin pitch 7.62mm 0.25W = 1/4W length 6.3mm diameter 2.5mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal
+Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0207_L6.3mm_D2.5mm_P15.24mm_Horizontal
+Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=15.24mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0207 series Axial Horizontal pin pitch 15.24mm 0.25W = 1/4W length 6.3mm diameter 2.5mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0309_L9.0mm_D3.2mm_P2.54mm_Vertical
+Resistor, Axial_DIN0309 series, Axial, Vertical, pin pitch=2.54mm, 0.5W = 1/2W, length*diameter=9*3.2mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0309 series Axial Vertical pin pitch 2.54mm 0.5W = 1/2W length 9mm diameter 3.2mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0309_L9.0mm_D3.2mm_P5.08mm_Vertical
+Resistor, Axial_DIN0309 series, Axial, Vertical, pin pitch=5.08mm, 0.5W = 1/2W, length*diameter=9*3.2mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0309 series Axial Vertical pin pitch 5.08mm 0.5W = 1/2W length 9mm diameter 3.2mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0309_L9.0mm_D3.2mm_P12.70mm_Horizontal
+Resistor, Axial_DIN0309 series, Axial, Horizontal, pin pitch=12.7mm, 0.5W = 1/2W, length*diameter=9*3.2mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0309 series Axial Horizontal pin pitch 12.7mm 0.5W = 1/2W length 9mm diameter 3.2mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0309_L9.0mm_D3.2mm_P15.24mm_Horizontal
+Resistor, Axial_DIN0309 series, Axial, Horizontal, pin pitch=15.24mm, 0.5W = 1/2W, length*diameter=9*3.2mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0309 series Axial Horizontal pin pitch 15.24mm 0.5W = 1/2W length 9mm diameter 3.2mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0309_L9.0mm_D3.2mm_P20.32mm_Horizontal
+Resistor, Axial_DIN0309 series, Axial, Horizontal, pin pitch=20.32mm, 0.5W = 1/2W, length*diameter=9*3.2mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0309 series Axial Horizontal pin pitch 20.32mm 0.5W = 1/2W length 9mm diameter 3.2mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0309_L9.0mm_D3.2mm_P25.40mm_Horizontal
+Resistor, Axial_DIN0309 series, Axial, Horizontal, pin pitch=25.4mm, 0.5W = 1/2W, length*diameter=9*3.2mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0309 series Axial Horizontal pin pitch 25.4mm 0.5W = 1/2W length 9mm diameter 3.2mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0411_L9.9mm_D3.6mm_P5.08mm_Vertical
+Resistor, Axial_DIN0411 series, Axial, Vertical, pin pitch=5.08mm, 1W, length*diameter=9.9*3.6mm^2
+Resistor Axial_DIN0411 series Axial Vertical pin pitch 5.08mm 1W length 9.9mm diameter 3.6mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0411_L9.9mm_D3.6mm_P7.62mm_Vertical
+Resistor, Axial_DIN0411 series, Axial, Vertical, pin pitch=7.62mm, 1W, length*diameter=9.9*3.6mm^2
+Resistor Axial_DIN0411 series Axial Vertical pin pitch 7.62mm 1W length 9.9mm diameter 3.6mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0411_L9.9mm_D3.6mm_P12.70mm_Horizontal
+Resistor, Axial_DIN0411 series, Axial, Horizontal, pin pitch=12.7mm, 1W, length*diameter=9.9*3.6mm^2
+Resistor Axial_DIN0411 series Axial Horizontal pin pitch 12.7mm 1W length 9.9mm diameter 3.6mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0411_L9.9mm_D3.6mm_P15.24mm_Horizontal
+Resistor, Axial_DIN0411 series, Axial, Horizontal, pin pitch=15.24mm, 1W, length*diameter=9.9*3.6mm^2
+Resistor Axial_DIN0411 series Axial Horizontal pin pitch 15.24mm 1W length 9.9mm diameter 3.6mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0411_L9.9mm_D3.6mm_P20.32mm_Horizontal
+Resistor, Axial_DIN0411 series, Axial, Horizontal, pin pitch=20.32mm, 1W, length*diameter=9.9*3.6mm^2
+Resistor Axial_DIN0411 series Axial Horizontal pin pitch 20.32mm 1W length 9.9mm diameter 3.6mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0411_L9.9mm_D3.6mm_P25.40mm_Horizontal
+Resistor, Axial_DIN0411 series, Axial, Horizontal, pin pitch=25.4mm, 1W, length*diameter=9.9*3.6mm^2
+Resistor Axial_DIN0411 series Axial Horizontal pin pitch 25.4mm 1W length 9.9mm diameter 3.6mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0414_L11.9mm_D4.5mm_P5.08mm_Vertical
+Resistor, Axial_DIN0414 series, Axial, Vertical, pin pitch=5.08mm, 2W, length*diameter=11.9*4.5mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf
+Resistor Axial_DIN0414 series Axial Vertical pin pitch 5.08mm 2W length 11.9mm diameter 4.5mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0414_L11.9mm_D4.5mm_P7.62mm_Vertical
+Resistor, Axial_DIN0414 series, Axial, Vertical, pin pitch=7.62mm, 2W, length*diameter=11.9*4.5mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf
+Resistor Axial_DIN0414 series Axial Vertical pin pitch 7.62mm 2W length 11.9mm diameter 4.5mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0414_L11.9mm_D4.5mm_P15.24mm_Horizontal
+Resistor, Axial_DIN0414 series, Axial, Horizontal, pin pitch=15.24mm, 2W, length*diameter=11.9*4.5mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf
+Resistor Axial_DIN0414 series Axial Horizontal pin pitch 15.24mm 2W length 11.9mm diameter 4.5mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0414_L11.9mm_D4.5mm_P20.32mm_Horizontal
+Resistor, Axial_DIN0414 series, Axial, Horizontal, pin pitch=20.32mm, 2W, length*diameter=11.9*4.5mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf
+Resistor Axial_DIN0414 series Axial Horizontal pin pitch 20.32mm 2W length 11.9mm diameter 4.5mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0414_L11.9mm_D4.5mm_P25.40mm_Horizontal
+Resistor, Axial_DIN0414 series, Axial, Horizontal, pin pitch=25.4mm, 2W, length*diameter=11.9*4.5mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf
+Resistor Axial_DIN0414 series Axial Horizontal pin pitch 25.4mm 2W length 11.9mm diameter 4.5mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0516_L15.5mm_D5.0mm_P5.08mm_Vertical
+Resistor, Axial_DIN0516 series, Axial, Vertical, pin pitch=5.08mm, 2W, length*diameter=15.5*5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0516 series Axial Vertical pin pitch 5.08mm 2W length 15.5mm diameter 5mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0516_L15.5mm_D5.0mm_P7.62mm_Vertical
+Resistor, Axial_DIN0516 series, Axial, Vertical, pin pitch=7.62mm, 2W, length*diameter=15.5*5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0516 series Axial Vertical pin pitch 7.62mm 2W length 15.5mm diameter 5mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0516_L15.5mm_D5.0mm_P20.32mm_Horizontal
+Resistor, Axial_DIN0516 series, Axial, Horizontal, pin pitch=20.32mm, 2W, length*diameter=15.5*5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0516 series Axial Horizontal pin pitch 20.32mm 2W length 15.5mm diameter 5mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0516_L15.5mm_D5.0mm_P25.40mm_Horizontal
+Resistor, Axial_DIN0516 series, Axial, Horizontal, pin pitch=25.4mm, 2W, length*diameter=15.5*5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0516 series Axial Horizontal pin pitch 25.4mm 2W length 15.5mm diameter 5mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0516_L15.5mm_D5.0mm_P30.48mm_Horizontal
+Resistor, Axial_DIN0516 series, Axial, Horizontal, pin pitch=30.48mm, 2W, length*diameter=15.5*5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf
+Resistor Axial_DIN0516 series Axial Horizontal pin pitch 30.48mm 2W length 15.5mm diameter 5mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0614_L14.3mm_D5.7mm_P5.08mm_Vertical
+Resistor, Axial_DIN0614 series, Axial, Vertical, pin pitch=5.08mm, 1.5W, length*diameter=14.3*5.7mm^2
+Resistor Axial_DIN0614 series Axial Vertical pin pitch 5.08mm 1.5W length 14.3mm diameter 5.7mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0614_L14.3mm_D5.7mm_P7.62mm_Vertical
+Resistor, Axial_DIN0614 series, Axial, Vertical, pin pitch=7.62mm, 1.5W, length*diameter=14.3*5.7mm^2
+Resistor Axial_DIN0614 series Axial Vertical pin pitch 7.62mm 1.5W length 14.3mm diameter 5.7mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0614_L14.3mm_D5.7mm_P15.24mm_Horizontal
+Resistor, Axial_DIN0614 series, Axial, Horizontal, pin pitch=15.24mm, 1.5W, length*diameter=14.3*5.7mm^2
+Resistor Axial_DIN0614 series Axial Horizontal pin pitch 15.24mm 1.5W length 14.3mm diameter 5.7mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0614_L14.3mm_D5.7mm_P20.32mm_Horizontal
+Resistor, Axial_DIN0614 series, Axial, Horizontal, pin pitch=20.32mm, 1.5W, length*diameter=14.3*5.7mm^2
+Resistor Axial_DIN0614 series Axial Horizontal pin pitch 20.32mm 1.5W length 14.3mm diameter 5.7mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0614_L14.3mm_D5.7mm_P25.40mm_Horizontal
+Resistor, Axial_DIN0614 series, Axial, Horizontal, pin pitch=25.4mm, 1.5W, length*diameter=14.3*5.7mm^2
+Resistor Axial_DIN0614 series Axial Horizontal pin pitch 25.4mm 1.5W length 14.3mm diameter 5.7mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0617_L17.0mm_D6.0mm_P5.08mm_Vertical
+Resistor, Axial_DIN0617 series, Axial, Vertical, pin pitch=5.08mm, 2W, length*diameter=17*6mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf
+Resistor Axial_DIN0617 series Axial Vertical pin pitch 5.08mm 2W length 17mm diameter 6mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0617_L17.0mm_D6.0mm_P7.62mm_Vertical
+Resistor, Axial_DIN0617 series, Axial, Vertical, pin pitch=7.62mm, 2W, length*diameter=17*6mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf
+Resistor Axial_DIN0617 series Axial Vertical pin pitch 7.62mm 2W length 17mm diameter 6mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0617_L17.0mm_D6.0mm_P20.32mm_Horizontal
+Resistor, Axial_DIN0617 series, Axial, Horizontal, pin pitch=20.32mm, 2W, length*diameter=17*6mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf
+Resistor Axial_DIN0617 series Axial Horizontal pin pitch 20.32mm 2W length 17mm diameter 6mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0617_L17.0mm_D6.0mm_P25.40mm_Horizontal
+Resistor, Axial_DIN0617 series, Axial, Horizontal, pin pitch=25.4mm, 2W, length*diameter=17*6mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf
+Resistor Axial_DIN0617 series Axial Horizontal pin pitch 25.4mm 2W length 17mm diameter 6mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0617_L17.0mm_D6.0mm_P30.48mm_Horizontal
+Resistor, Axial_DIN0617 series, Axial, Horizontal, pin pitch=30.48mm, 2W, length*diameter=17*6mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf
+Resistor Axial_DIN0617 series Axial Horizontal pin pitch 30.48mm 2W length 17mm diameter 6mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0918_L18.0mm_D9.0mm_P7.62mm_Vertical
+Resistor, Axial_DIN0918 series, Axial, Vertical, pin pitch=7.62mm, 4W, length*diameter=18*9mm^2
+Resistor Axial_DIN0918 series Axial Vertical pin pitch 7.62mm 4W length 18mm diameter 9mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0918_L18.0mm_D9.0mm_P22.86mm_Horizontal
+Resistor, Axial_DIN0918 series, Axial, Horizontal, pin pitch=22.86mm, 4W, length*diameter=18*9mm^2
+Resistor Axial_DIN0918 series Axial Horizontal pin pitch 22.86mm 4W length 18mm diameter 9mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0918_L18.0mm_D9.0mm_P25.40mm_Horizontal
+Resistor, Axial_DIN0918 series, Axial, Horizontal, pin pitch=25.4mm, 4W, length*diameter=18*9mm^2
+Resistor Axial_DIN0918 series Axial Horizontal pin pitch 25.4mm 4W length 18mm diameter 9mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0918_L18.0mm_D9.0mm_P30.48mm_Horizontal
+Resistor, Axial_DIN0918 series, Axial, Horizontal, pin pitch=30.48mm, 4W, length*diameter=18*9mm^2
+Resistor Axial_DIN0918 series Axial Horizontal pin pitch 30.48mm 4W length 18mm diameter 9mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0922_L20.0mm_D9.0mm_P7.62mm_Vertical
+Resistor, Axial_DIN0922 series, Axial, Vertical, pin pitch=7.62mm, 5W, length*diameter=20*9mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf
+Resistor Axial_DIN0922 series Axial Vertical pin pitch 7.62mm 5W length 20mm diameter 9mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0922_L20.0mm_D9.0mm_P25.40mm_Horizontal
+Resistor, Axial_DIN0922 series, Axial, Horizontal, pin pitch=25.4mm, 5W, length*diameter=20*9mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf
+Resistor Axial_DIN0922 series Axial Horizontal pin pitch 25.4mm 5W length 20mm diameter 9mm
+0
+2
+2
+Resistor_THT
+R_Axial_DIN0922_L20.0mm_D9.0mm_P30.48mm_Horizontal
+Resistor, Axial_DIN0922 series, Axial, Horizontal, pin pitch=30.48mm, 5W, length*diameter=20*9mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf
+Resistor Axial_DIN0922 series Axial Horizontal pin pitch 30.48mm 5W length 20mm diameter 9mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L20.0mm_W6.4mm_P5.08mm_Vertical
+Resistor, Axial_Power series, Axial, Vertical, pin pitch=5.08mm, 4W, length*width*height=20*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Axial Vertical pin pitch 5.08mm 4W length 20mm width 6.4mm height 6.4mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L20.0mm_W6.4mm_P7.62mm_Vertical
+Resistor, Axial_Power series, Axial, Vertical, pin pitch=7.62mm, 4W, length*width*height=20*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Axial Vertical pin pitch 7.62mm 4W length 20mm width 6.4mm height 6.4mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L20.0mm_W6.4mm_P22.40mm
+Resistor, Axial_Power series, Box, pin pitch=22.4mm, 4W, length*width*height=20*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 22.4mm 4W length 20mm width 6.4mm height 6.4mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L20.0mm_W6.4mm_P25.40mm
+Resistor, Axial_Power series, Box, pin pitch=25.4mm, 4W, length*width*height=20*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 25.4mm 4W length 20mm width 6.4mm height 6.4mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L20.0mm_W6.4mm_P30.48mm
+Resistor, Axial_Power series, Box, pin pitch=30.48mm, 4W, length*width*height=20*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 30.48mm 4W length 20mm width 6.4mm height 6.4mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L25.0mm_W6.4mm_P27.94mm
+Resistor, Axial_Power series, Box, pin pitch=27.94mm, 5W, length*width*height=25*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 27.94mm 5W length 25mm width 6.4mm height 6.4mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L25.0mm_W6.4mm_P30.48mm
+Resistor, Axial_Power series, Box, pin pitch=30.48mm, 5W, length*width*height=25*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 30.48mm 5W length 25mm width 6.4mm height 6.4mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L25.0mm_W9.0mm_P7.62mm_Vertical
+Resistor, Axial_Power series, Axial, Vertical, pin pitch=7.62mm, 7W, length*width*height=25*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Axial Vertical pin pitch 7.62mm 7W length 25mm width 9mm height 9mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L25.0mm_W9.0mm_P10.16mm_Vertical
+Resistor, Axial_Power series, Axial, Vertical, pin pitch=10.16mm, 7W, length*width*height=25*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Axial Vertical pin pitch 10.16mm 7W length 25mm width 9mm height 9mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L25.0mm_W9.0mm_P27.94mm
+Resistor, Axial_Power series, Box, pin pitch=27.94mm, 7W, length*width*height=25*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 27.94mm 7W length 25mm width 9mm height 9mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L25.0mm_W9.0mm_P30.48mm
+Resistor, Axial_Power series, Box, pin pitch=30.48mm, 7W, length*width*height=25*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 30.48mm 7W length 25mm width 9mm height 9mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L38.0mm_W6.4mm_P40.64mm
+Resistor, Axial_Power series, Box, pin pitch=40.64mm, 7W, length*width*height=38*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 40.64mm 7W length 38mm width 6.4mm height 6.4mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L38.0mm_W6.4mm_P45.72mm
+Resistor, Axial_Power series, Box, pin pitch=45.72mm, 7W, length*width*height=38*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 45.72mm 7W length 38mm width 6.4mm height 6.4mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L38.0mm_W9.0mm_P40.64mm
+Resistor, Axial_Power series, Box, pin pitch=40.64mm, 9W, length*width*height=38*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 40.64mm 9W length 38mm width 9mm height 9mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L38.0mm_W9.0mm_P45.72mm
+Resistor, Axial_Power series, Box, pin pitch=45.72mm, 9W, length*width*height=38*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 45.72mm 9W length 38mm width 9mm height 9mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L48.0mm_W12.5mm_P7.62mm_Vertical
+Resistor, Axial_Power series, Axial, Vertical, pin pitch=7.62mm, 15W, length*width*height=48*12.5*12.5mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Axial Vertical pin pitch 7.62mm 15W length 48mm width 12.5mm height 12.5mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L48.0mm_W12.5mm_P10.16mm_Vertical
+Resistor, Axial_Power series, Axial, Vertical, pin pitch=10.16mm, 15W, length*width*height=48*12.5*12.5mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Axial Vertical pin pitch 10.16mm 15W length 48mm width 12.5mm height 12.5mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L48.0mm_W12.5mm_P55.88mm
+Resistor, Axial_Power series, Box, pin pitch=55.88mm, 15W, length*width*height=48*12.5*12.5mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 55.88mm 15W length 48mm width 12.5mm height 12.5mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L48.0mm_W12.5mm_P60.96mm
+Resistor, Axial_Power series, Box, pin pitch=60.96mm, 15W, length*width*height=48*12.5*12.5mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 60.96mm 15W length 48mm width 12.5mm height 12.5mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L50.0mm_W9.0mm_P55.88mm
+Resistor, Axial_Power series, Box, pin pitch=55.88mm, 11W, length*width*height=50*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 55.88mm 11W length 50mm width 9mm height 9mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L50.0mm_W9.0mm_P60.96mm
+Resistor, Axial_Power series, Box, pin pitch=60.96mm, 11W, length*width*height=50*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 60.96mm 11W length 50mm width 9mm height 9mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L60.0mm_W14.0mm_P10.16mm_Vertical
+Resistor, Axial_Power series, Axial, Vertical, pin pitch=10.16mm, 25W, length*width*height=60*14*14mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Axial Vertical pin pitch 10.16mm 25W length 60mm width 14mm height 14mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L60.0mm_W14.0mm_P66.04mm
+Resistor, Axial_Power series, Box, pin pitch=66.04mm, 25W, length*width*height=60*14*14mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 66.04mm 25W length 60mm width 14mm height 14mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L60.0mm_W14.0mm_P71.12mm
+Resistor, Axial_Power series, Box, pin pitch=71.12mm, 25W, length*width*height=60*14*14mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 71.12mm 25W length 60mm width 14mm height 14mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L75.0mm_W9.0mm_P81.28mm
+Resistor, Axial_Power series, Box, pin pitch=81.28mm, 17W, length*width*height=75*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 81.28mm 17W length 75mm width 9mm height 9mm
+0
+2
+2
+Resistor_THT
+R_Axial_Power_L75.0mm_W9.0mm_P86.36mm
+Resistor, Axial_Power series, Box, pin pitch=86.36mm, 17W, length*width*height=75*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf
+Resistor Axial_Power series Box pin pitch 86.36mm 17W length 75mm width 9mm height 9mm
+0
+2
+2
+Resistor_THT
+R_Axial_Shunt_L22.2mm_W8.0mm_PS14.30mm_P25.40mm
+Resistor, Axial_Shunt series, Box, pin pitch=25.4mm, 3W, length*width*height=22.2*8*8mm^3, shunt pin pitch = 14.30mm, http://www.vishay.com/docs/30217/cpsl.pdf
+Resistor Axial_Shunt series Box pin pitch 25.4mm 3W length 22.2mm width 8mm height 8mm shunt pin pitch 14.30mm
+0
+4
+4
+Resistor_THT
+R_Axial_Shunt_L22.2mm_W9.5mm_PS14.30mm_P25.40mm
+Resistor, Axial_Shunt series, Box, pin pitch=25.4mm, 5W, length*width*height=22.2*9.5*9.5mm^3, shunt pin pitch = 14.30mm, http://www.vishay.com/docs/30217/cpsl.pdf
+Resistor Axial_Shunt series Box pin pitch 25.4mm 5W length 22.2mm width 9.5mm height 9.5mm shunt pin pitch 14.30mm
+0
+4
+4
+Resistor_THT
+R_Axial_Shunt_L35.3mm_W9.5mm_PS25.40mm_P38.10mm
+Resistor, Axial_Shunt series, Box, pin pitch=38.1mm, 7W, length*width*height=35.3*9.5*9.5mm^3, shunt pin pitch = 25.40mm, http://www.vishay.com/docs/30217/cpsl.pdf
+Resistor Axial_Shunt series Box pin pitch 38.1mm 7W length 35.3mm width 9.5mm height 9.5mm shunt pin pitch 25.40mm
+0
+4
+4
+Resistor_THT
+R_Axial_Shunt_L47.6mm_W9.5mm_PS34.93mm_P50.80mm
+Resistor, Axial_Shunt series, Box, pin pitch=50.8mm, 10W, length*width*height=47.6*9.5*9.5mm^3, shunt pin pitch = 34.93mm, http://www.vishay.com/docs/30217/cpsl.pdf
+Resistor Axial_Shunt series Box pin pitch 50.8mm 10W length 47.6mm width 9.5mm height 9.5mm shunt pin pitch 34.93mm
+0
+4
+4
+Resistor_THT
+R_Axial_Shunt_L47.6mm_W12.7mm_PS34.93mm_P50.80mm
+Resistor, Axial_Shunt series, Box, pin pitch=50.8mm, 15W, length*width*height=47.6*12.7*12.7mm^3, shunt pin pitch = 34.93mm, http://www.vishay.com/docs/30217/cpsl.pdf
+Resistor Axial_Shunt series Box pin pitch 50.8mm 15W length 47.6mm width 12.7mm height 12.7mm shunt pin pitch 34.93mm
+0
+4
+4
+Resistor_THT
+R_Bare_Metal_Element_L12.4mm_W4.8mm_P11.40mm
+Resistor, Bare_Metal_Element series, Bare Metal Strip/Wire, Horizontal, pin pitch=11.4mm, 1W, length*width=12.4*4.8mm^2, https://www.bourns.com/pdfs/PWR4412-2S.pdf
+Resistor Bare_Metal_Element series Bare Metal Strip Wire Horizontal pin pitch 11.4mm 1W length 12.4mm width 4.8mm 
+0
+2
+2
+Resistor_THT
+R_Bare_Metal_Element_L16.3mm_W4.8mm_P15.30mm
+Resistor, Bare_Metal_Element series, Bare Metal Strip/Wire, Horizontal, pin pitch=15.3mm, 3W, length*width=16.3*4.8mm^2, https://www.bourns.com/pdfs/PWR4412-2S.pdf
+Resistor Bare_Metal_Element series Bare Metal Strip Wire Horizontal pin pitch 15.3mm 3W length 16.3mm width 4.8mm 
+0
+2
+2
+Resistor_THT
+R_Bare_Metal_Element_L21.3mm_W4.8mm_P20.30mm
+Resistor, Bare_Metal_Element series, Bare Metal Strip/Wire, Horizontal, pin pitch=20.3mm, 5W, length*width=21.3*4.8mm^2, https://www.bourns.com/pdfs/PWR4412-2S.pdf
+Resistor Bare_Metal_Element series Bare Metal Strip Wire Horizontal pin pitch 20.3mm 5W length 21.3mm width 4.8mm 
+0
+2
+2
+Resistor_THT
+R_Box_L8.4mm_W2.5mm_P5.08mm
+Resistor, Box series, Radial, pin pitch=5.08mm, 0.5W = 1/2W, length*width=8.38*2.54mm^2, http://www.vishay.com/docs/60051/cns020.pdf
+Resistor Box series Radial pin pitch 5.08mm 0.5W = 1/2W length 8.38mm width 2.54mm
+0
+2
+2
+Resistor_THT
+R_Box_L13.0mm_W4.0mm_P9.00mm
+Resistor, Box series, Radial, pin pitch=9.00mm, 2W, length*width=13.0*4.0mm^2, http://www.produktinfo.conrad.com/datenblaetter/425000-449999/443860-da-01-de-METALLBAND_WIDERSTAND_0_1_OHM_5W_5Pr.pdf
+Resistor Box series Radial pin pitch 9.00mm 2W length 13.0mm width 4.0mm
+0
+2
+2
+Resistor_THT
+R_Box_L14.0mm_W5.0mm_P9.00mm
+Resistor, Box series, Radial, pin pitch=9.00mm, 5W, length*width=14.0*5.0mm^2, http://www.produktinfo.conrad.com/datenblaetter/425000-449999/443860-da-01-de-METALLBAND_WIDERSTAND_0_1_OHM_5W_5Pr.pdf
+Resistor Box series Radial pin pitch 9.00mm 5W length 14.0mm width 5.0mm
+0
+2
+2
+Resistor_THT
+R_Box_L26.0mm_W5.0mm_P20.00mm
+Resistor, Box series, Radial, pin pitch=20.00mm, 10W, length*width=26.0*5.0mm^2, http://www.produktinfo.conrad.com/datenblaetter/425000-449999/443860-da-01-de-METALLBAND_WIDERSTAND_0_1_OHM_5W_5Pr.pdf
+Resistor Box series Radial pin pitch 20.00mm 10W length 26.0mm width 5.0mm
+0
+2
+2
+Resistor_THT
+R_Radial_Power_L7.0mm_W8.0mm_Px2.40mm_Py2.30mm
+Resistor, Radial_Power series, Radial, pin pitch=2.40*2.30mm^2, 7W, length*width=7*8mm^2, http://www.vitrohm.com/content/files/vitrohm_series_kv_-_201601.pdf
+Resistor Radial_Power series Radial pin pitch 2.40*2.30mm^2 7W length 7mm width 8mm
+0
+2
+2
+Resistor_THT
+R_Radial_Power_L9.0mm_W10.0mm_Px2.70mm_Py2.30mm
+Resistor, Radial_Power series, Radial, pin pitch=2.70*2.30mm^2, 17W, length*width=9*10mm^2, http://www.vitrohm.com/content/files/vitrohm_series_kv_-_201601.pdf
+Resistor Radial_Power series Radial pin pitch 2.70*2.30mm^2 17W length 9mm width 10mm
+0
+2
+2
+Resistor_THT
+R_Radial_Power_L11.0mm_W7.0mm_P5.00mm
+Resistor, Radial_Power series, Radial, pin pitch=5.00mm, 2W, length*width=11.0*7.0mm^2, http://www.vishay.com/docs/30218/cpcx.pdf
+Resistor Radial_Power series Radial pin pitch 5.00mm 2W length 11.0mm width 7.0mm
+0
+2
+2
+Resistor_THT
+R_Radial_Power_L12.0mm_W8.0mm_P5.00mm
+Resistor, Radial_Power series, Radial, pin pitch=5.00mm, 3W, length*width=12.0*8.0mm^2, http://www.vishay.com/docs/30218/cpcx.pdf
+Resistor Radial_Power series Radial pin pitch 5.00mm 3W length 12.0mm width 8.0mm
+0
+2
+2
+Resistor_THT
+R_Radial_Power_L13.0mm_W9.0mm_P5.00mm
+Resistor, Radial_Power series, Radial, pin pitch=5.00mm, 7W, length*width=13.0*9.0mm^2, http://www.vishay.com/docs/30218/cpcx.pdf
+Resistor Radial_Power series Radial pin pitch 5.00mm 7W length 13.0mm width 9.0mm
+0
+2
+2
+Resistor_THT
+R_Radial_Power_L16.1mm_W9.0mm_P7.37mm
+Resistor, Radial_Power series, Radial, pin pitch=7.37mm, 10W, length*width=16.1*9mm^2, http://www.vishay.com/docs/30218/cpcx.pdf
+Resistor Radial_Power series Radial pin pitch 7.37mm 10W length 16.1mm width 9mm
+0
+2
+2
+Rotary_Encoder
+RotaryEncoder_Alps_EC11E-Switch_Vertical_H20mm
+Alps rotary encoder, EC12E... with switch, vertical shaft, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC11/EC11E15204A3.html
+rotary encoder
+0
+7
+6
+Rotary_Encoder
+RotaryEncoder_Alps_EC11E-Switch_Vertical_H20mm_CircularMountingHoles
+Alps rotary encoder, EC12E... with switch, vertical shaft, mounting holes with circular drills, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC11/EC11E15204A3.html
+rotary encoder
+0
+7
+6
+Rotary_Encoder
+RotaryEncoder_Alps_EC11E_Vertical_H20mm
+Alps rotary encoder, EC12E... without switch (pins are dummy), vertical shaft, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC11/EC11E15204A3.html
+rotary encoder
+0
+7
+4
+Rotary_Encoder
+RotaryEncoder_Alps_EC11E_Vertical_H20mm_CircularMountingHoles
+Alps rotary encoder, EC12E... without switch (pins are dummy), vertical shaft, mounting holes with circular drills, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC11/EC11E15204A3.html
+rotary encoder
+0
+7
+4
+Rotary_Encoder
+RotaryEncoder_Alps_EC12E-Switch_Vertical_H20mm
+Alps rotary encoder, EC12E... with switch, vertical shaft, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC12E/EC12E1240405.html & http://cdn-reichelt.de/documents/datenblatt/F100/402097STEC12E08.PDF
+rotary encoder
+0
+7
+6
+Rotary_Encoder
+RotaryEncoder_Alps_EC12E-Switch_Vertical_H20mm_CircularMountingHoles
+Alps rotary encoder, EC12E... with switch, vertical shaft, mounting holes with circular drills, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC12E/EC12E1240405.html & http://cdn-reichelt.de/documents/datenblatt/F100/402097STEC12E08.PDF
+rotary encoder
+0
+7
+6
+Rotary_Encoder
+RotaryEncoder_Alps_EC12E_Vertical_H20mm
+Alps rotary encoder, EC12E..., vertical shaft, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC12E/EC12E1240405.html
+rotary encoder
+0
+5
+4
+Rotary_Encoder
+RotaryEncoder_Alps_EC12E_Vertical_H20mm_CircularMountingHoles
+Alps rotary encoder, EC12E..., vertical shaft, mounting holes with circular drills, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC12E/EC12E1240405.html
+rotary encoder
+0
+5
+4
+SIT8008BI-13-33E-33
+OSC_SIT8008BI-13-33E-33.333330E
+
+
+0
+4
+4
+SN74LVC245APW
+SOP65P640X120-20N
+
+
+0
+20
+20
+Sensor
+Aosong_DHT11_5.5x12.0_P2.54mm
+Temperature and humidity module, http://akizukidenshi.com/download/ds/aosong/DHT11.pdf
+Temperature and humidity module
+0
+4
+4
+Sensor
+MQ-6
+Gas Sensor, 6 pin, https://www.winsen-sensor.com/d/files/semiconductor/mq-6.pdf
+gas sensor
+0
+6
+6
+Sensor
+SHT1x
+SHT1x
+SHT1x
+0
+8
+8
+Sensor_Audio
+Infineon_PG-LLGA-5-1
+Infineon_PG-LLGA-5-1 StepUp generated footprint, https://www.infineon.com/cms/en/product/packages/PG-LLGA/PG-LLGA-5-1/
+infineon mems microphone
+0
+15
+5
+Sensor_Audio
+ST_HLGA-6_3.76x4.72mm_P1.65mm
+http://www.st.com/content/ccc/resource/technical/document/datasheet/group3/27/62/48/98/44/54/4d/36/DM00303211/files/DM00303211.pdf/jcr:content/translations/en.DM00303211.pdf
+HLGA Sensor Audio
+0
+6
+6
+Sensor_Current
+AKM_CQ_7
+AKM Current Sensor, 7 pin, THT (http://www.akm.com/akm/en/file/datasheet/CQ-236B.pdf)
+akm current sensor tht
+0
+39
+7
+Sensor_Current
+AKM_CQ_7S
+AKM Current Sensor, 7 pin, SMD (http://www.akm.com/akm/en/file/datasheet/CQ-236B.pdf)
+akm current sensor smd
+0
+19
+7
+Sensor_Current
+AKM_CQ_VSOP-24_5.6x7.9mm_P0.65mm
+AKM VSOP-24 current sensor, 5.6x7.9mm body, 0.65mm pitch (http://www.akm.com/akm/en/file/datasheet/CQ-330J.pdf)
+akm vsop 24
+0
+10
+10
+Sensor_Current
+AKM_CZ_SSOP-10_6.5x8.1mm_P0.95mm
+AKM CZ-381x current sensor, 6.5x8.1mm body, 0.95mm pitch (http://www.akm.com/akm/en/product/detail/0009/)
+akm cz-381x 10
+0
+10
+10
+Sensor_Current
+Allegro_CB_PFF
+Allegro MicroSystems, CB-PFF Package (http://www.allegromicro.com/en/Products/Current-Sensor-ICs/Fifty-To-Two-Hundred-Amp-Integrated-Conductor-Sensor-ICs/ACS758.aspx) !PADS 4-5 DO NOT MATCH DATASHEET!
+Allegro CB-PFF
+0
+37
+5
+Sensor_Current
+Allegro_CB_PSF
+Allegro MicroSystems, CB-PSF Package (http://www.allegromicro.com/en/Products/Current-Sensor-ICs/Fifty-To-Two-Hundred-Amp-Integrated-Conductor-Sensor-ICs/ACS758.aspx)
+Allegro CB-PSF
+0
+5
+5
+Sensor_Current
+Allegro_CB_PSS
+Allegro MicroSystems, CB-PSS Package (http://www.allegromicro.com/en/Products/Current-Sensor-ICs/Fifty-To-Two-Hundred-Amp-Integrated-Conductor-Sensor-ICs/ACS758.aspx)
+Allegro CB-PSS
+0
+5
+5
+Sensor_Current
+Allegro_PSOF-7_4.8x6.4mm_P1.60mm
+Allegro Microsystems PSOF-7, 4.8x6.4mm Body, 1.60mm Pitch (http://www.allegromicro.com/~/media/Files/Datasheets/ACS780-Datasheet.ashx)
+Allegro PSOF-7
+0
+7
+7
+Sensor_Current
+Allegro_QFN-12-10-1EP_3x3mm_P0.5mm
+Allegro Microsystems 12-Lead (10-Lead Populated) Quad Flat Pack, 3x3mm Body, 0.5mm Pitch (http://www.allegromicro.com/~/media/Files/Datasheets/ACS711-Datasheet.ashx)
+Allegro QFN 0.5
+0
+14
+10
+Sensor_Current
+Allegro_QSOP-24_3.9x8.7mm_P0.635mm
+Allegro Microsystems 24-Lead Plastic Shrink Small Outline Narrow Body Body [QSOP] (http://www.allegromicro.com/~/media/Files/Datasheets/ACS726-Datasheet.ashx?la=en)
+Allegro QSOP 0.635
+0
+24
+24
+Sensor_Current
+Allegro_SIP-3
+Allegro Microsystems SIP-3, 1.27mm Pitch (http://www.allegromicro.com/~/media/Files/Datasheets/A1369-Datasheet.ashx)
+Allegro SIP-3
+0
+3
+3
+Sensor_Current
+Allegro_SIP-4
+Allegro Microsystems SIP-4, 1.27mm Pitch (http://www.allegromicro.com/~/media/Files/Datasheets/A1363-Datasheet.ashx)
+Allegro SIP-4
+0
+4
+4
+Sensor_Current
+Diodes_SIP-3_4.1x1.5mm_P1.27mm
+Diodes SIP-3 Bulk Pack, 1.27mm Pitch (https://www.diodes.com/assets/Package-Files/SIP-3-Bulk-Pack.pdf)
+Diodes SIP-3 Bulk Pack
+0
+3
+3
+Sensor_Current
+Diodes_SIP-3_4.1x1.5mm_P2.65mm
+Diodes SIP-3 Ammo Pack, 2.65mm Pitch (https://www.diodes.com/assets/Package-Files/SIP-3-Ammo-Pack.pdf)
+Diodes SIP-3 Ammo Pack
+0
+3
+3
+Sensor_Current
+Honeywell_CSLW
+https://sensing.honeywell.com/honeywell-sensing-cslw-series-product-sheet-005861-1-en.pdf
+Miniature Wired Open-Loop Current Sensor
+0
+5
+5
+Sensor_Current
+LEM_HO8-NP
+LEM HO 8/15/25-NP Current Transducer (https://www.lem.com/sites/default/files/products_datasheets/ho-np-0000_series.pdf)
+current transducer
+0
+13
+13
+Sensor_Current
+LEM_HO8-NSM
+LEM HO 8/15/25-NSM Current Transducer (https://www.lem.com/sites/default/files/products_datasheets/ho-nsm-0000_series.pdf)
+current transducer
+0
+13
+13
+Sensor_Current
+LEM_HO40-NP
+LEM HO 40/60/120/150-NP Current Transducer (https://www.lem.com/sites/default/files/products_datasheets/ho-np_0100__1100_series.pdf)
+current transducer
+0
+13
+13
+Sensor_Current
+LEM_HTFS
+LEM HTFS x00-P current transducer (https://www.lem.com/sites/default/files/products_datasheets/htfs_200_800-p.pdf)
+HTFS current transducer
+0
+4
+4
+Sensor_Current
+LEM_HX02-P
+LEM HX02-P hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%202_6-p_e%20v5.pdf)
+hall current
+0
+6
+6
+Sensor_Current
+LEM_HX03-P-SP2
+LEM HX03-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf)
+hall current
+0
+6
+6
+Sensor_Current
+LEM_HX04-P
+LEM HX04-P hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%202_6-p_e%20v5.pdf)
+hall current
+0
+6
+6
+Sensor_Current
+LEM_HX05-NP
+LEM HX05-NP hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%205_15-np_e%20v10.pdf)
+hall current
+0
+8
+8
+Sensor_Current
+LEM_HX05-P-SP2
+LEM HX05-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf)
+hall current
+0
+6
+6
+Sensor_Current
+LEM_HX06-P
+LEM HX06-P hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%202_6-p_e%20v5.pdf)
+hall current
+0
+6
+6
+Sensor_Current
+LEM_HX10-NP
+LEM HX10-NP hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%205_15-np_e%20v10.pdf)
+hall current
+0
+8
+8
+Sensor_Current
+LEM_HX10-P-SP2
+LEM HX10-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf)
+hall current
+0
+6
+6
+Sensor_Current
+LEM_HX15-NP
+LEM HX15-NP hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%205_15-np_e%20v10.pdf)
+hall current
+0
+8
+8
+Sensor_Current
+LEM_HX15-P-SP2
+LEM HX15-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf)
+hall current
+0
+6
+6
+Sensor_Current
+LEM_HX20-P-SP2
+LEM HX20-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf)
+hall current
+0
+6
+6
+Sensor_Current
+LEM_HX25-P-SP2
+LEM HX25-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf)
+hall current
+0
+6
+6
+Sensor_Current
+LEM_HX50-P-SP2
+LEM HX50-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf)
+hall current
+0
+6
+6
+Sensor_Current
+LEM_LA25-P
+LEM Current Transducer (https://www.lem.com/sites/default/files/products_datasheets/la_25-p.pdf)
+current transducer
+0
+3
+3
+Sensor_Current
+LEM_LTSR-NP
+LEM current transducer LEM_LTSR-NP 5V supply voltage series https://www.lem.com/sites/default/files/products_datasheets/ltsr_6-np.pdf
+Current transducer
+0
+10
+10
+Sensor_Motion
+InvenSense_QFN-24_3x3mm_P0.4mm
+24-Lead Plastic QFN (3mm x 3mm); Pitch 0.4mm; EP 1.7x1.54mm; for InvenSense motion sensors; keepout area marked (Package see: https://store.invensense.com/datasheets/invensense/MPU9250REV1.0.pdf; See also https://www.invensense.com/wp-content/uploads/2015/02/InvenSense-MEMS-Handling.pdf)
+QFN 0.4
+0
+24
+24
+Sensor_Motion
+InvenSense_QFN-24_3x3mm_P0.4mm_NoMask
+24-Lead Plastic QFN (3mm x 3mm); Pitch 0.4mm; EP 1.7x1.54mm; for InvenSense motion sensors; Mask removed below exposed pad; keepout area marked (Package see: https://store.invensense.com/datasheets/invensense/MPU9250REV1.0.pdf; See also https://www.invensense.com/wp-content/uploads/2015/02/InvenSense-MEMS-Handling.pdf)
+QFN 0.4
+0
+25
+24
+Sensor_Motion
+InvenSense_QFN-24_4x4mm_P0.5mm
+24-Lead Plastic QFN (4mm x 4mm); Pitch 0.5mm; EP 2.7x2.6mm; for InvenSense motion sensors; keepout area marked (Package see: https://store.invensense.com/datasheets/invensense/MPU-6050_DataSheet_V3%204.pdf; See also https://www.invensense.com/wp-content/uploads/2015/02/InvenSense-MEMS-Handling.pdf)
+QFN 0.5
+0
+24
+24
+Sensor_Motion
+InvenSense_QFN-24_4x4mm_P0.5mm_NoMask
+24-Lead Plastic QFN (4mm x 4mm); Pitch 0.5mm; EP 2.7x2.6mm; for InvenSense motion sensors; Mask removed below exposed pad; keepout area marked (Package see: https://store.invensense.com/datasheets/invensense/MPU-6050_DataSheet_V3%204.pdf; See also https://www.invensense.com/wp-content/uploads/2015/02/InvenSense-MEMS-Handling.pdf)
+QFN 0.5
+0
+25
+24
+Sensor_Pressure
+Freescale_98ARH99066A
+https://www.nxp.com/docs/en/data-sheet/MPXH6250A.pdf
+sensor pressure ssop 98ARH99066A
+0
+8
+8
+Sensor_Pressure
+Freescale_98ARH99089A
+https://www.nxp.com/docs/en/data-sheet/MPXH6250A.pdf
+sensor pressure ssop 98ARH99089A
+0
+8
+8
+Sensor_Pressure
+Honeywell_40PCxxxG1A
+https://www.honeywellscportal.com/index.php?ci_id=138832
+pressure sensor automotive honeywell
+0
+3
+3
+Sensor_Voltage
+LEM_LV25-P
+LEM LV25-P Voltage transducer, https://www.lem.com/sites/default/files/products_datasheets/lv_25-p.pdf
+LEM Hall Effect Voltage transducer
+0
+5
+5
+Socket
+3M_Textool_240-1288-00-0602J_2x20_P2.54mm
+3M 40-pin zero insertion force socket, though-hole, row spacing 25.4 mm (1000 mils)
+THT DIP DIL ZIF 25.4mm 1000mil Socket
+0
+40
+40
+Socket
+DIP_Socket-14_W4.3_W5.08_W7.62_W10.16_W10.9_3M_214-3339-00-0602J
+3M 14-pin zero insertion force socket, through-hole, row spacing 7.62 mm (300 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf
+THT DIP DIL ZIF 7.62mm 300mil Socket
+0
+14
+14
+Socket
+DIP_Socket-16_W4.3_W5.08_W7.62_W10.16_W10.9_3M_216-3340-00-0602J
+3M 16-pin zero insertion force socket, through-hole, row spacing 7.62 mm (300 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf
+THT DIP DIL ZIF 7.62mm 300mil Socket
+0
+16
+16
+Socket
+DIP_Socket-18_W4.3_W5.08_W7.62_W10.16_W10.9_3M_218-3341-00-0602J
+3M 18-pin zero insertion force socket, through-hole, row spacing 7.62 mm (300 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf
+THT DIP DIL ZIF 7.62mm 300mil Socket
+0
+18
+18
+Socket
+DIP_Socket-20_W4.3_W5.08_W7.62_W10.16_W10.9_3M_220-3342-00-0602J
+3M 20-pin zero insertion force socket, through-hole, row spacing 7.62 mm (300 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf
+THT DIP DIL ZIF 7.62mm 300mil Socket
+0
+20
+20
+Socket
+DIP_Socket-22_W6.9_W7.62_W10.16_W12.7_W13.5_3M_222-3343-00-0602J
+3M 22-pin zero insertion force socket, through-hole, row spacing 10.16 mm (400 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf
+THT DIP DIL ZIF 10.16mm 400mil Socket
+0
+22
+22
+Socket
+DIP_Socket-24_W4.3_W5.08_W7.62_W10.16_W10.9_3M_224-5248-00-0602J
+3M 24-pin zero insertion force socket, through-hole, row spacing 7.62 mm (300 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf
+THT DIP DIL ZIF 7.62mm 300mil Socket
+0
+24
+24
+Socket
+DIP_Socket-24_W11.9_W12.7_W15.24_W17.78_W18.5_3M_224-1275-00-0602J
+3M 24-pin zero insertion force socket, through-hole, row spacing 15.24 mm (600 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf
+THT DIP DIL ZIF 15.24mm 600mil Socket
+0
+24
+24
+Socket
+DIP_Socket-28_W6.9_W7.62_W10.16_W12.7_W13.5_3M_228-4817-00-0602J
+3M 28-pin zero insertion force socket, through-hole, row spacing 10.16 mm (400 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf
+THT DIP DIL ZIF 10.16mm 400mil Socket
+0
+28
+28
+Socket
+DIP_Socket-28_W11.9_W12.7_W15.24_W17.78_W18.5_3M_228-1277-00-0602J
+3M 28-pin zero insertion force socket, through-hole, row spacing 15.24 mm (600 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf
+THT DIP DIL ZIF 15.24mm 600mil Socket
+0
+28
+28
+Socket
+DIP_Socket-32_W11.9_W12.7_W15.24_W17.78_W18.5_3M_232-1285-00-0602J
+3M 32-pin zero insertion force socket, through-hole, row spacing 15.24 mm (600 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf
+THT DIP DIL ZIF 15.24mm 600mil Socket
+0
+32
+32
+Socket
+DIP_Socket-40_W11.9_W12.7_W15.24_W17.78_W18.5_3M_240-1280-00-0602J
+3M 40-pin zero insertion force socket, through-hole, row spacing 15.24 mm (600 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf
+THT DIP DIL ZIF 15.24mm 600mil Socket
+0
+40
+40
+Socket
+DIP_Socket-40_W22.1_W22.86_W25.4_W27.94_W28.7_3M_240-3639-00-0602J
+3M 40-pin zero insertion force socket, through-hole, row spacing 25.4 mm (1000 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf
+THT DIP DIL ZIF 25.4mm 1000mil Socket
+0
+40
+40
+Socket
+DIP_Socket-42_W11.9_W12.7_W15.24_W17.78_W18.5_3M_242-1281-00-0602J
+3M 42-pin zero insertion force socket, through-hole, row spacing 15.24 mm (600 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf
+THT DIP DIL ZIF 15.24mm 600mil Socket
+0
+42
+42
+Socket
+Wells_648-0482211SA01
+https://www.farnell.com/cad/316865.pdf?_ga=2.37208032.177107060.1530611323-249019997.1498114824
+48pin TSOP Socket
+0
+48
+48
+Symbol
+CE-Logo_8.5x6mm_SilkScreen
+CE marking
+Logo CE certification
+0
+0
+0
+Symbol
+CE-Logo_11.2x8mm_SilkScreen
+CE marking
+Logo CE certification
+0
+0
+0
+Symbol
+CE-Logo_16.8x12mm_SilkScreen
+CE marking
+Logo CE certification
+0
+0
+0
+Symbol
+CE-Logo_28x20mm_SilkScreen
+CE marking
+Logo CE certification
+0
+0
+0
+Symbol
+CE-Logo_42x30mm_SilkScreen
+CE marking
+Logo CE certification
+0
+0
+0
+Symbol
+CE-Logo_56.1x40mm_SilkScreen
+CE marking
+Logo CE certification
+0
+0
+0
+Symbol
+ESD-Logo_6.6x6mm_SilkScreen
+Electrostatic discharge Logo
+Logo ESD
+0
+0
+0
+Symbol
+ESD-Logo_8.9x8mm_SilkScreen
+Electrostatic discharge Logo
+Logo ESD
+0
+0
+0
+Symbol
+ESD-Logo_13.2x12mm_SilkScreen
+Electrostatic discharge Logo
+Logo ESD
+0
+0
+0
+Symbol
+ESD-Logo_22x20mm_SilkScreen
+Electrostatic discharge Logo
+Logo ESD
+0
+0
+0
+Symbol
+ESD-Logo_33x30mm_SilkScreen
+Electrostatic discharge Logo
+Logo ESD
+0
+0
+0
+Symbol
+ESD-Logo_44.1x40mm_SilkScreen
+Electrostatic discharge Logo
+Logo ESD
+0
+0
+0
+Symbol
+FCC-Logo_7.3x6mm_SilkScreen
+FCC marking
+Logo FCC certification
+0
+0
+0
+Symbol
+FCC-Logo_9.6x8mm_SilkScreen
+FCC marking
+Logo FCC certification
+0
+0
+0
+Symbol
+FCC-Logo_14.6x12mm_SilkScreen
+FCC marking
+Logo FCC certification
+0
+0
+0
+Symbol
+FCC-Logo_24.2x20mm_SilkScreen
+FCC marking
+Logo FCC certification
+0
+0
+0
+Symbol
+FCC-Logo_36.3x30mm_SilkScreen
+FCC marking
+Logo FCC certification
+0
+0
+0
+Symbol
+FCC-Logo_48.3x40mm_SilkScreen
+FCC marking
+Logo FCC certification
+0
+0
+0
+Symbol
+KiCad-Logo2_5mm_Copper
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo2_5mm_SilkScreen
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo2_6mm_Copper
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo2_6mm_SilkScreen
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo2_8mm_Copper
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo2_8mm_SilkScreen
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo2_12mm_Copper
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo2_12mm_SilkScreen
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo2_20mm_Copper
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo2_20mm_SilkScreen
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo2_30mm_Copper
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo2_30mm_SilkScreen
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo2_40mm_Copper
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo2_40mm_SilkScreen
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo_5mm_Copper
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo_5mm_SilkScreen
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo_6mm_Copper
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo_6mm_SilkScreen
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo_8mm_Copper
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo_8mm_SilkScreen
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo_12mm_Copper
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo_12mm_SilkScreen
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo_20mm_Copper
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo_20mm_SilkScreen
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo_30mm_Copper
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo_30mm_SilkScreen
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo_40mm_Copper
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+KiCad-Logo_40mm_SilkScreen
+KiCad Logo
+Logo KiCad
+0
+0
+0
+Symbol
+OSHW-Logo2_7.3x6mm_Copper
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Logo2_7.3x6mm_SilkScreen
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Logo2_9.8x8mm_Copper
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Logo2_9.8x8mm_SilkScreen
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Logo2_14.6x12mm_Copper
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Logo2_14.6x12mm_SilkScreen
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Logo2_24.3x20mm_Copper
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Logo2_24.3x20mm_SilkScreen
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Logo2_36.5x30mm_Copper
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Logo2_36.5x30mm_SilkScreen
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Logo2_48.7x40mm_Copper
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Logo2_48.7x40mm_SilkScreen
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Logo_5.7x6mm_Copper
+Open Source Hardware Logo
+Logo OSHW
+0
+0
+0
+Symbol
+OSHW-Logo_5.7x6mm_SilkScreen
+Open Source Hardware Logo
+Logo OSHW
+0
+0
+0
+Symbol
+OSHW-Logo_7.5x8mm_Copper
+Open Source Hardware Logo
+Logo OSHW
+0
+0
+0
+Symbol
+OSHW-Logo_7.5x8mm_SilkScreen
+Open Source Hardware Logo
+Logo OSHW
+0
+0
+0
+Symbol
+OSHW-Logo_11.4x12mm_Copper
+Open Source Hardware Logo
+Logo OSHW
+0
+0
+0
+Symbol
+OSHW-Logo_11.4x12mm_SilkScreen
+Open Source Hardware Logo
+Logo OSHW
+0
+0
+0
+Symbol
+OSHW-Logo_19x20mm_Copper
+Open Source Hardware Logo
+Logo OSHW
+0
+0
+0
+Symbol
+OSHW-Logo_19x20mm_SilkScreen
+Open Source Hardware Logo
+Logo OSHW
+0
+0
+0
+Symbol
+OSHW-Logo_28.5x30mm_Copper
+Open Source Hardware Logo
+Logo OSHW
+0
+0
+0
+Symbol
+OSHW-Logo_28.5x30mm_SilkScreen
+Open Source Hardware Logo
+Logo OSHW
+0
+0
+0
+Symbol
+OSHW-Logo_38.1x40mm_Copper
+Open Source Hardware Logo
+Logo OSHW
+0
+0
+0
+Symbol
+OSHW-Logo_38.1x40mm_SilkScreen
+Open Source Hardware Logo
+Logo OSHW
+0
+0
+0
+Symbol
+OSHW-Symbol_6.7x6mm_Copper
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Symbol_6.7x6mm_SilkScreen
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Symbol_8.9x8mm_Copper
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Symbol_8.9x8mm_SilkScreen
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Symbol_13.4x12mm_Copper
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Symbol_13.4x12mm_SilkScreen
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Symbol_22.3x20mm_Copper
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Symbol_22.3x20mm_SilkScreen
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Symbol_33.5x30mm_Copper
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Symbol_33.5x30mm_SilkScreen
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Symbol_44.5x40mm_Copper
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+OSHW-Symbol_44.5x40mm_SilkScreen
+Open Source Hardware Symbol
+Logo Symbol OSHW
+0
+0
+0
+Symbol
+Polarity_Center_Negative_6mm_SilkScreen
+Polarity Logo, Center Negative
+Logo Polarity Center Negative
+0
+0
+0
+Symbol
+Polarity_Center_Negative_8mm_SilkScreen
+Polarity Logo, Center Negative
+Logo Polarity Center Negative
+0
+0
+0
+Symbol
+Polarity_Center_Negative_12mm_SilkScreen
+Polarity Logo, Center Negative
+Logo Polarity Center Negative
+0
+0
+0
+Symbol
+Polarity_Center_Negative_20mm_SilkScreen
+Polarity Logo, Center Negative
+Logo Polarity Center Negative
+0
+0
+0
+Symbol
+Polarity_Center_Negative_30mm_SilkScreen
+Polarity Logo, Center Negative
+Logo Polarity Center Negative
+0
+0
+0
+Symbol
+Polarity_Center_Negative_40mm_SilkScreen
+Polarity Logo, Center Negative
+Logo Polarity Center Negative
+0
+0
+0
+Symbol
+Polarity_Center_Positive_6mm_SilkScreen
+Polarity Logo, Center Positive
+Logo Polarity Center Positive
+0
+0
+0
+Symbol
+Polarity_Center_Positive_8mm_SilkScreen
+Polarity Logo, Center Positive
+Logo Polarity Center Positive
+0
+0
+0
+Symbol
+Polarity_Center_Positive_12mm_SilkScreen
+Polarity Logo, Center Positive
+Logo Polarity Center Positive
+0
+0
+0
+Symbol
+Polarity_Center_Positive_20mm_SilkScreen
+Polarity Logo, Center Positive
+Logo Polarity Center Positive
+0
+0
+0
+Symbol
+Polarity_Center_Positive_30mm_SilkScreen
+Polarity Logo, Center Positive
+Logo Polarity Center Positive
+0
+0
+0
+Symbol
+Polarity_Center_Positive_40mm_SilkScreen
+Polarity Logo, Center Positive
+Logo Polarity Center Positive
+0
+0
+0
+Symbol
+RoHS-Logo_6mm_SilkScreen
+Restriction of Hazardous Substances Directive Logo
+Logo RoHS
+0
+0
+0
+Symbol
+RoHS-Logo_8mm_SilkScreen
+Restriction of Hazardous Substances Directive Logo
+Logo RoHS
+0
+0
+0
+Symbol
+RoHS-Logo_12mm_SilkScreen
+Restriction of Hazardous Substances Directive Logo
+Logo RoHS
+0
+0
+0
+Symbol
+RoHS-Logo_20mm_SilkScreen
+Restriction of Hazardous Substances Directive Logo
+Logo RoHS
+0
+0
+0
+Symbol
+RoHS-Logo_30mm_SilkScreen
+Restriction of Hazardous Substances Directive Logo
+Logo RoHS
+0
+0
+0
+Symbol
+RoHS-Logo_40mm_SilkScreen
+Restriction of Hazardous Substances Directive Logo
+Logo RoHS
+0
+0
+0
+Symbol
+Symbol_Attention_CopperTop_Big
+Symbol, Attention, Copper Top, Big,
+Symbol, Attention, Copper Top, Big,
+0
+0
+0
+Symbol
+Symbol_Attention_CopperTop_Small
+Symbol, Attention, Copper Top, Small,
+Symbol, Attention, Copper Top, Small,
+0
+0
+0
+Symbol
+Symbol_Barrel_Polarity
+Barrel connector polarity indicator
+barrel polarity
+0
+0
+0
+Symbol
+Symbol_CC-Attribution_CopperTop_Big
+Symbol, CC-Attribution, Copper Top, Big,
+Symbol, CC-Attribution, Copper Top, Big,
+0
+0
+0
+Symbol
+Symbol_CC-Attribution_CopperTop_Small
+Symbol, CC-Share Alike, Copper Top, Small,
+Symbol, CC-Share Alike, Copper Top, Small,
+0
+0
+0
+Symbol
+Symbol_CC-Noncommercial_CopperTop_Big
+Symbol, CC-Noncommercial, Copper Top, Big,
+Symbol, CC-Noncommercial, Copper Top, Big,
+0
+0
+0
+Symbol
+Symbol_CC-Noncommercial_CopperTop_Small
+Symbol, CC-Noncommercial Alike, Copper Top, Small,
+Symbol, CC-Noncommercial Alike, Copper Top, Small,
+0
+0
+0
+Symbol
+Symbol_CC-PublicDomain_CopperTop_Big
+Symbol, CC-PublicDomain, Copper Top, Big,
+Symbol, CC-PublicDomain, Copper Top, Big,
+0
+0
+0
+Symbol
+Symbol_CC-PublicDomain_CopperTop_Small
+Symbol, CC-Public Domain, Copper Top, Small,
+Symbol, CC-Public Domain, Copper Top, Small,
+0
+0
+0
+Symbol
+Symbol_CC-PublicDomain_SilkScreenTop_Big
+Symbol, CC-PublicDomain, SilkScreen Top, Big,
+Symbol, CC-PublicDomain, SilkScreen Top, Big,
+0
+0
+0
+Symbol
+Symbol_CC-ShareAlike_CopperTop_Big
+Symbol, CC-Share Alike, Copper Top, Big,
+Symbol, CC-Share Alike, Copper Top, Big,
+0
+0
+0
+Symbol
+Symbol_CC-ShareAlike_CopperTop_Small
+Symbol, CC-Share Alike, Copper Top, Small,
+Symbol, CC-Share Alike, Copper Top, Small,
+0
+0
+0
+Symbol
+Symbol_CreativeCommonsPublicDomain_CopperTop_Small
+Symbol, Creative Commons Public Domain, CopperTop, Small,
+Symbol, Creative Commons Public Domain, CopperTop, Small,
+0
+0
+0
+Symbol
+Symbol_CreativeCommonsPublicDomain_SilkScreenTop_Small
+Symbol, Creative Commons Public Domain, SilkScreenTop, Small,
+Symbol, Creative Commons Public Domain, SilkScreen Top, Small,
+0
+0
+0
+Symbol
+Symbol_CreativeCommons_CopperTop_Type1_Big
+Symbol, Creative Commons, CopperTop, Type 1, Big,
+Symbol, Creative Commons, CopperTop, Type 1, Big,
+0
+0
+0
+Symbol
+Symbol_CreativeCommons_CopperTop_Type2_Big
+Symbol, Creative Commons, CopperTop, Type 2, Big,
+Symbol, Creative Commons, CopperTop, Type 2, Big,
+0
+0
+0
+Symbol
+Symbol_CreativeCommons_CopperTop_Type2_Small
+Symbol, Creative Commons, CopperTop, Type 2, Small,
+Symbol, Creative Commons, CopperTop, Type 2, Small,
+0
+0
+0
+Symbol
+Symbol_CreativeCommons_SilkScreenTop_Type2_Big
+Symbol, Creative Commons, SilkScreen Top, Type 2, Big,
+Symbol, Creative Commons, SilkScreen Top, Type 2, Big,
+0
+0
+0
+Symbol
+Symbol_Danger_CopperTop_Big
+Symbol, Danger, CopperTop, Big,
+Symbol, Danger, CopperTop, Big,
+0
+0
+0
+Symbol
+Symbol_Danger_CopperTop_Small
+Symbol, Danger, Copper Top, Small,
+Symbol, Danger, Copper Top, Small,
+0
+0
+0
+Symbol
+Symbol_ESD-Logo-Text_CopperTop
+
+
+0
+0
+0
+Symbol
+Symbol_ESD-Logo_CopperTop
+ESD-Logo, similar JEDEC-14, without text, ohne Text, Copper Top,
+ESD-Logo, similar JEDEC-14, without text, ohne Text, Copper Top,
+0
+0
+0
+Symbol
+Symbol_GNU-GPL_CopperTop_Big
+Symbol, GNU-GPL, Copper Top, Big,
+Symbol, GNU-GPL, Copper Top, Big,
+0
+0
+0
+Symbol
+Symbol_GNU-GPL_CopperTop_Small
+Symbol, GNU-GPL, Copper Top, Small,
+Symbol, GNU-GPL, Copper Top, Small,
+0
+0
+0
+Symbol
+Symbol_GNU-Logo_CopperTop
+GNU-Logo, GNU-Head, GNU-Kopf, Copper Top,
+GNU-Logo, GNU-Head, GNU-Kopf, Copper Top,
+0
+0
+0
+Symbol
+Symbol_GNU-Logo_SilkscreenTop
+GNU-Logo, GNU-Head, GNU-Kopf, Silkscreen,
+GNU-Logo, GNU-Head, GNU-Kopf, Silkscreen,
+0
+0
+0
+Symbol
+Symbol_HighVoltage_Type1_CopperTop_Big
+Symbol, HighVoltage, Type1, Copper Top, Big,
+Symbol, HighVoltage, Type1, Copper Top, Big,
+0
+0
+0
+Symbol
+Symbol_HighVoltage_Type2_CopperTop_Big
+Symbol, HighVoltage, Type2, Copper Top, Big,
+Symbol, HighVoltage, Type2, Copper Top, Big,
+0
+0
+0
+Symbol
+Symbol_HighVoltage_Type2_CopperTop_VerySmall
+Symbol, High Voltage, Type 2, Copper Top, Very Small,
+Symbol, High Voltage, Type 2, Copper Top, Very Small,
+0
+0
+0
+Symbol
+Symbol_Highvoltage_Type1_CopperTop_Small
+Symbol, Highvoltage, Type 1, Copper Top, Small,
+Symbol, Highvoltage, Type 1, Copper Top, Small,
+0
+0
+0
+Symbol
+Symbol_Highvoltage_Type2_CopperTop_Small
+Symbol, Highvoltage, Type 2, Copper Top, Small,
+Symbol, Highvoltage, Type 2, Copper Top, Small,
+0
+0
+0
+Symbol
+WEEE-Logo_4.2x6mm_SilkScreen
+Waste Electrical and Electronic Equipment Directive
+Logo WEEE
+0
+0
+0
+Symbol
+WEEE-Logo_5.6x8mm_SilkScreen
+Waste Electrical and Electronic Equipment Directive
+Logo WEEE
+0
+0
+0
+Symbol
+WEEE-Logo_8.4x12mm_SilkScreen
+Waste Electrical and Electronic Equipment Directive
+Logo WEEE
+0
+0
+0
+Symbol
+WEEE-Logo_14x20mm_SilkScreen
+Waste Electrical and Electronic Equipment Directive
+Logo WEEE
+0
+0
+0
+Symbol
+WEEE-Logo_21x30mm_SilkScreen
+Waste Electrical and Electronic Equipment Directive
+Logo WEEE
+0
+0
+0
+Symbol
+WEEE-Logo_28.1x40mm_SilkScreen
+Waste Electrical and Electronic Equipment Directive
+Logo WEEE
+0
+0
+0
+TerminalBlock
+TerminalBlock_Altech_AK300-2_P5.00mm
+Altech AK300 terminal block, pitch 5.0mm, 45 degree angled, see http://www.mouser.com/ds/2/16/PCBMETRC-24178.pdf
+Altech AK300 terminal block pitch 5.0mm
+0
+2
+2
+TerminalBlock
+TerminalBlock_Altech_AK300-3_P5.00mm
+Altech AK300 terminal block, pitch 5.0mm, 45 degree angled, see http://www.mouser.com/ds/2/16/PCBMETRC-24178.pdf
+Altech AK300 terminal block pitch 5.0mm
+0
+3
+3
+TerminalBlock
+TerminalBlock_Altech_AK300-4_P5.00mm
+Altech AK300 terminal block, pitch 5.0mm, 45 degree angled, see http://www.mouser.com/ds/2/16/PCBMETRC-24178.pdf
+Altech AK300 terminal block pitch 5.0mm
+0
+4
+4
+TerminalBlock
+TerminalBlock_Wuerth_691311400102_P7.62mm
+https://katalog.we-online.de/em/datasheet/6913114001xx.pdf
+Wuerth WR-TBL Series 3114 terminal block pitch 7.62mm
+0
+2
+2
+TerminalBlock
+TerminalBlock_bornier-2_P5.08mm
+simple 2-pin terminal block, pitch 5.08mm, revamped version of bornier2
+terminal block bornier2
+0
+2
+2
+TerminalBlock
+TerminalBlock_bornier-3_P5.08mm
+simple 3-pin terminal block, pitch 5.08mm, revamped version of bornier3
+terminal block bornier3
+0
+3
+3
+TerminalBlock
+TerminalBlock_bornier-4_P5.08mm
+simple 4-pin terminal block, pitch 5.08mm, revamped version of bornier4
+terminal block bornier4
+0
+4
+4
+TerminalBlock
+TerminalBlock_bornier-5_P5.08mm
+simple 5-pin terminal block, pitch 5.08mm, revamped version of bornier5
+terminal block bornier5
+0
+5
+5
+TerminalBlock
+TerminalBlock_bornier-6_P5.08mm
+simple 6pin terminal block, pitch 5.08mm, revamped version of bornier6
+terminal block bornier6
+0
+6
+6
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x02_P3.50mm_Horizontal
+Terminal Block 4Ucon ItemNo. 19963, 2 pins, pitch 3.5mm, size 7.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/19963.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 19963 pitch 3.5mm size 7.7x7mm^2 drill 1.2mm pad 2.4mm
+0
+2
+2
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x02_P3.50mm_Vertical
+Terminal Block 4Ucon ItemNo. 10693, vertical (cable from top), 2 pins, pitch 3.5mm, size 8x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10693.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10693 vertical pitch 3.5mm size 8x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+2
+2
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x03_P3.50mm_Horizontal
+Terminal Block 4Ucon ItemNo. 20193, 3 pins, pitch 3.5mm, size 11.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/20193.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 20193 pitch 3.5mm size 11.2x7mm^2 drill 1.2mm pad 2.4mm
+0
+3
+3
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x03_P3.50mm_Vertical
+Terminal Block 4Ucon ItemNo. 10694, vertical (cable from top), 3 pins, pitch 3.5mm, size 11.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10694.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10694 vertical pitch 3.5mm size 11.5x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+3
+3
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x04_P3.50mm_Horizontal
+Terminal Block 4Ucon ItemNo. 20001, 4 pins, pitch 3.5mm, size 14.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/20001.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 20001 pitch 3.5mm size 14.7x7mm^2 drill 1.2mm pad 2.4mm
+0
+4
+4
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x04_P3.50mm_Vertical
+Terminal Block 4Ucon ItemNo. 10695, vertical (cable from top), 4 pins, pitch 3.5mm, size 15x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10695.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10695 vertical pitch 3.5mm size 15x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+4
+4
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x05_P3.50mm_Horizontal
+Terminal Block 4Ucon ItemNo. 20223, 5 pins, pitch 3.5mm, size 18.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/20223.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 20223 pitch 3.5mm size 18.2x7mm^2 drill 1.2mm pad 2.4mm
+0
+5
+5
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x05_P3.50mm_Vertical
+Terminal Block 4Ucon ItemNo. 10696, vertical (cable from top), 5 pins, pitch 3.5mm, size 18.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10696.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10696 vertical pitch 3.5mm size 18.5x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+5
+5
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x06_P3.50mm_Horizontal
+Terminal Block 4Ucon ItemNo. 19964, 6 pins, pitch 3.5mm, size 21.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/19964.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 19964 pitch 3.5mm size 21.7x7mm^2 drill 1.2mm pad 2.4mm
+0
+6
+6
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x06_P3.50mm_Vertical
+Terminal Block 4Ucon ItemNo. 10697, vertical (cable from top), 6 pins, pitch 3.5mm, size 22x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10697.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10697 vertical pitch 3.5mm size 22x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+6
+6
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x07_P3.50mm_Horizontal
+Terminal Block 4Ucon ItemNo. 10684, 7 pins, pitch 3.5mm, size 25.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10684.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10684 pitch 3.5mm size 25.2x7mm^2 drill 1.2mm pad 2.4mm
+0
+7
+7
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x07_P3.50mm_Vertical
+Terminal Block 4Ucon ItemNo. 10698, vertical (cable from top), 7 pins, pitch 3.5mm, size 25.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10698.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10698 vertical pitch 3.5mm size 25.5x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+7
+7
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x08_P3.50mm_Horizontal
+Terminal Block 4Ucon ItemNo. 19965, 8 pins, pitch 3.5mm, size 28.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/19965.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 19965 pitch 3.5mm size 28.7x7mm^2 drill 1.2mm pad 2.4mm
+0
+8
+8
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x08_P3.50mm_Vertical
+Terminal Block 4Ucon ItemNo. 10699, vertical (cable from top), 8 pins, pitch 3.5mm, size 29x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10699.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10699 vertical pitch 3.5mm size 29x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+8
+8
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x09_P3.50mm_Horizontal
+Terminal Block 4Ucon ItemNo. 10686, 9 pins, pitch 3.5mm, size 32.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10686.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10686 pitch 3.5mm size 32.2x7mm^2 drill 1.2mm pad 2.4mm
+0
+9
+9
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x09_P3.50mm_Vertical
+Terminal Block 4Ucon ItemNo. 10700, vertical (cable from top), 9 pins, pitch 3.5mm, size 32.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10700.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10700 vertical pitch 3.5mm size 32.5x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+9
+9
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x10_P3.50mm_Horizontal
+Terminal Block 4Ucon ItemNo. 10687, 10 pins, pitch 3.5mm, size 35.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10687.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10687 pitch 3.5mm size 35.7x7mm^2 drill 1.2mm pad 2.4mm
+0
+10
+10
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x10_P3.50mm_Vertical
+Terminal Block 4Ucon ItemNo. 10701, vertical (cable from top), 10 pins, pitch 3.5mm, size 36x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10701.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10701 vertical pitch 3.5mm size 36x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+10
+10
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x11_P3.50mm_Horizontal
+Terminal Block 4Ucon ItemNo. 10688, 11 pins, pitch 3.5mm, size 39.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10688.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10688 pitch 3.5mm size 39.2x7mm^2 drill 1.2mm pad 2.4mm
+0
+11
+11
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x11_P3.50mm_Vertical
+Terminal Block 4Ucon ItemNo. 10702, vertical (cable from top), 11 pins, pitch 3.5mm, size 39.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10702.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10702 vertical pitch 3.5mm size 39.5x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+11
+11
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x12_P3.50mm_Horizontal
+Terminal Block 4Ucon ItemNo. 10689, 12 pins, pitch 3.5mm, size 42.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10689.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10689 pitch 3.5mm size 42.7x7mm^2 drill 1.2mm pad 2.4mm
+0
+12
+12
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x12_P3.50mm_Vertical
+Terminal Block 4Ucon ItemNo. 10703, vertical (cable from top), 12 pins, pitch 3.5mm, size 43x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10703.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10703 vertical pitch 3.5mm size 43x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+12
+12
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x13_P3.50mm_Horizontal
+Terminal Block 4Ucon ItemNo. 10690, 13 pins, pitch 3.5mm, size 46.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10690.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10690 pitch 3.5mm size 46.2x7mm^2 drill 1.2mm pad 2.4mm
+0
+13
+13
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x13_P3.50mm_Vertical
+Terminal Block 4Ucon ItemNo. 10704, vertical (cable from top), 13 pins, pitch 3.5mm, size 46.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10704.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10704 vertical pitch 3.5mm size 46.5x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+13
+13
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x14_P3.50mm_Horizontal
+Terminal Block 4Ucon ItemNo. 10691, 14 pins, pitch 3.5mm, size 49.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10691.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10691 pitch 3.5mm size 49.7x7mm^2 drill 1.2mm pad 2.4mm
+0
+14
+14
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x14_P3.50mm_Vertical
+Terminal Block 4Ucon ItemNo. 10705, vertical (cable from top), 14 pins, pitch 3.5mm, size 50x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10705.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10705 vertical pitch 3.5mm size 50x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+14
+14
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x15_P3.50mm_Horizontal
+Terminal Block 4Ucon ItemNo. 10692, 15 pins, pitch 3.5mm, size 53.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10692.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10692 pitch 3.5mm size 53.2x7mm^2 drill 1.2mm pad 2.4mm
+0
+15
+15
+TerminalBlock_4Ucon
+TerminalBlock_4Ucon_1x15_P3.50mm_Vertical
+Terminal Block 4Ucon ItemNo. 10706, vertical (cable from top), 15 pins, pitch 3.5mm, size 53.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10706.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon
+THT Terminal Block 4Ucon ItemNo. 10706 vertical pitch 3.5mm size 53.5x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+15
+15
+TerminalBlock_Altech
+Altech_AK300_1x02_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+2
+2
+TerminalBlock_Altech
+Altech_AK300_1x03_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+3
+3
+TerminalBlock_Altech
+Altech_AK300_1x04_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+4
+4
+TerminalBlock_Altech
+Altech_AK300_1x05_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+5
+5
+TerminalBlock_Altech
+Altech_AK300_1x06_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+6
+6
+TerminalBlock_Altech
+Altech_AK300_1x07_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+7
+7
+TerminalBlock_Altech
+Altech_AK300_1x08_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+8
+8
+TerminalBlock_Altech
+Altech_AK300_1x09_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+9
+9
+TerminalBlock_Altech
+Altech_AK300_1x10_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+10
+10
+TerminalBlock_Altech
+Altech_AK300_1x11_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+11
+11
+TerminalBlock_Altech
+Altech_AK300_1x12_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+12
+12
+TerminalBlock_Altech
+Altech_AK300_1x13_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+13
+13
+TerminalBlock_Altech
+Altech_AK300_1x14_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+14
+14
+TerminalBlock_Altech
+Altech_AK300_1x15_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+15
+15
+TerminalBlock_Altech
+Altech_AK300_1x16_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+16
+16
+TerminalBlock_Altech
+Altech_AK300_1x17_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+17
+17
+TerminalBlock_Altech
+Altech_AK300_1x18_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+18
+18
+TerminalBlock_Altech
+Altech_AK300_1x19_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+19
+19
+TerminalBlock_Altech
+Altech_AK300_1x20_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+20
+20
+TerminalBlock_Altech
+Altech_AK300_1x21_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+21
+21
+TerminalBlock_Altech
+Altech_AK300_1x22_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+22
+22
+TerminalBlock_Altech
+Altech_AK300_1x23_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+23
+23
+TerminalBlock_Altech
+Altech_AK300_1x24_P5.00mm_45-Degree
+Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF)
+Altech AK300 serie connector
+0
+24
+24
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-02_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+2
+2
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-03_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+3
+3
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-04_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+4
+4
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-05_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+5
+5
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-06_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+6
+6
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-07_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+7
+7
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-08_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+8
+8
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-09_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+9
+9
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-10_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+10
+10
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-11_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+11
+11
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-12_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+12
+12
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-13_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+13
+13
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-14_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+14
+14
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-15_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+15
+15
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-16_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+16
+16
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-17_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+17
+17
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-18_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+18
+18
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-19_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+19
+19
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-20_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+20
+20
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-21_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+21
+21
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-22_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+22
+22
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-23_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+23
+23
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-24_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+24
+24
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-25_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+25
+25
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-26_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+26
+26
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-27_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+27
+27
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-28_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+28
+28
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-29_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+29
+29
+TerminalBlock_Dinkle
+TerminalBlock_Dinkle_DT-55-B01X-30_P10.00mm
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX
+Dinkle DT-55-B01X Terminal Block  pitch 10.00mm
+0
+30
+30
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_360271_1x01_Horizontal_ScrewM3.0_Boxed
+single screw terminal block Metz Connect 360271, block size 9x7.3mm^2, drill diamater 1.5mm, 1 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 134, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT single screw terminal block Metz Connect 360271 size 9x7.3mm^2 drill 1.5mm pad 3mm
+0
+1
+1
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_360272_1x01_Horizontal_ScrewM2.6
+single screw terminal block Metz Connect 360272, block size 4x4mm^2, drill diamater 1.5mm, 2 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 131, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT single screw terminal block Metz Connect 360272 size 4x4mm^2 drill 1.5mm pad 3mm
+0
+2
+1
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_360273_1x01_Horizontal_ScrewM2.6_WireProtection
+single screw terminal block Metz Connect 360273, block size 5x4mm^2, drill diamater 1.5mm, 2 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 131, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT single screw terminal block Metz Connect 360273 size 5x4mm^2 drill 1.5mm pad 3mm
+0
+2
+1
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_360291_1x01_Horizontal_ScrewM3.0_Boxed
+single screw terminal block Metz Connect 360291, block size 9x7.3mm^2, drill diamater 1.5mm, 2 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 133, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT single screw terminal block Metz Connect 360291 size 9x7.3mm^2 drill 1.5mm pad 3mm
+0
+2
+1
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_360322_1x01_Horizontal_ScrewM3.0_WireProtection
+single screw terminal block Metz Connect 360322, block size 6x4mm^2, drill diamater 1.5mm, 2 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 133, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT single screw terminal block Metz Connect 360322 size 6x4mm^2 drill 1.5mm pad 3mm
+0
+2
+1
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_360381_1x01_Horizontal_ScrewM3.0
+single screw terminal block Metz Connect 360381, block size 5x5mm^2, drill diamater 1.5mm, 2 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 133, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT single screw terminal block Metz Connect 360381 size 5x5mm^2 drill 1.5mm pad 3mm
+0
+2
+1
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_360410_1x01_Horizontal_ScrewM3.0
+single screw terminal block Metz Connect 360410, block size 5x5mm^2, drill diamater 1.5mm, 2 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 132, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT single screw terminal block Metz Connect 360410 size 5x5mm^2 drill 1.5mm pad 3mm
+0
+2
+1
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_360425_1x01_Horizontal_ScrewM4.0_Boxed
+single screw terminal block Metz Connect 360425, block size 9x9mm^2, drill diamater 1.6mm, 4 pads, pad diameter 3.2mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 134, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT single screw terminal block Metz Connect 360425 size 9x9mm^2 drill 1.6mm pad 3.2mm
+0
+4
+1
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type011_RT05502HBWC_1x02_P5.00mm_Horizontal
+terminal block Metz Connect Type011_RT05502HBWC, 2 pins, pitch 5mm, size 10x10.5mm^2, drill diamater 1.4mm, pad diameter 2.8mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310111_RT055xxHBLC_OFF-022717S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type011_RT05502HBWC pitch 5mm size 10x10.5mm^2 drill 1.4mm pad 2.8mm
+0
+2
+2
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type011_RT05503HBWC_1x03_P5.00mm_Horizontal
+terminal block Metz Connect Type011_RT05503HBWC, 3 pins, pitch 5mm, size 15x10.5mm^2, drill diamater 1.4mm, pad diameter 2.8mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310111_RT055xxHBLC_OFF-022717S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type011_RT05503HBWC pitch 5mm size 15x10.5mm^2 drill 1.4mm pad 2.8mm
+0
+3
+3
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type011_RT05504HBWC_1x04_P5.00mm_Horizontal
+terminal block Metz Connect Type011_RT05504HBWC, 4 pins, pitch 5mm, size 20x10.5mm^2, drill diamater 1.4mm, pad diameter 2.8mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310111_RT055xxHBLC_OFF-022717S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type011_RT05504HBWC pitch 5mm size 20x10.5mm^2 drill 1.4mm pad 2.8mm
+0
+4
+4
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type011_RT05505HBWC_1x05_P5.00mm_Horizontal
+terminal block Metz Connect Type011_RT05505HBWC, 5 pins, pitch 5mm, size 25x10.5mm^2, drill diamater 1.4mm, pad diameter 2.8mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310111_RT055xxHBLC_OFF-022717S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type011_RT05505HBWC pitch 5mm size 25x10.5mm^2 drill 1.4mm pad 2.8mm
+0
+5
+5
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type011_RT05506HBWC_1x06_P5.00mm_Horizontal
+terminal block Metz Connect Type011_RT05506HBWC, 6 pins, pitch 5mm, size 30x10.5mm^2, drill diamater 1.4mm, pad diameter 2.8mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310111_RT055xxHBLC_OFF-022717S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type011_RT05506HBWC pitch 5mm size 30x10.5mm^2 drill 1.4mm pad 2.8mm
+0
+6
+6
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type055_RT01502HDWU_1x02_P5.00mm_Horizontal
+terminal block Metz Connect Type055_RT01502HDWU, 2 pins, pitch 5mm, size 10x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310551_RT015xxHDWU_OFF-022723S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type055_RT01502HDWU pitch 5mm size 10x8mm^2 drill 1.3mm pad 2.5mm
+0
+2
+2
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type055_RT01503HDWU_1x03_P5.00mm_Horizontal
+terminal block Metz Connect Type055_RT01503HDWU, 3 pins, pitch 5mm, size 15x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310551_RT015xxHDWU_OFF-022723S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type055_RT01503HDWU pitch 5mm size 15x8mm^2 drill 1.3mm pad 2.5mm
+0
+3
+3
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type055_RT01504HDWU_1x04_P5.00mm_Horizontal
+terminal block Metz Connect Type055_RT01504HDWU, 4 pins, pitch 5mm, size 20x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310551_RT015xxHDWU_OFF-022723S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type055_RT01504HDWU pitch 5mm size 20x8mm^2 drill 1.3mm pad 2.5mm
+0
+4
+4
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type059_RT06302HBWC_1x02_P3.50mm_Horizontal
+terminal block Metz Connect Type059_RT06302HBWC, 2 pins, pitch 3.5mm, size 7x6.5mm^2, drill diamater 1.2mm, pad diameter 2.3mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310591_RT063xxHBWC_OFF-022684T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type059_RT06302HBWC pitch 3.5mm size 7x6.5mm^2 drill 1.2mm pad 2.3mm
+0
+2
+2
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type059_RT06303HBWC_1x03_P3.50mm_Horizontal
+terminal block Metz Connect Type059_RT06303HBWC, 3 pins, pitch 3.5mm, size 10.5x6.5mm^2, drill diamater 1.2mm, pad diameter 2.3mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310591_RT063xxHBWC_OFF-022684T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type059_RT06303HBWC pitch 3.5mm size 10.5x6.5mm^2 drill 1.2mm pad 2.3mm
+0
+3
+3
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type059_RT06304HBWC_1x04_P3.50mm_Horizontal
+terminal block Metz Connect Type059_RT06304HBWC, 4 pins, pitch 3.5mm, size 14x6.5mm^2, drill diamater 1.2mm, pad diameter 2.3mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310591_RT063xxHBWC_OFF-022684T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type059_RT06304HBWC pitch 3.5mm size 14x6.5mm^2 drill 1.2mm pad 2.3mm
+0
+4
+4
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type059_RT06305HBWC_1x05_P3.50mm_Horizontal
+terminal block Metz Connect Type059_RT06305HBWC, 5 pins, pitch 3.5mm, size 17.5x6.5mm^2, drill diamater 1.2mm, pad diameter 2.3mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310591_RT063xxHBWC_OFF-022684T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type059_RT06305HBWC pitch 3.5mm size 17.5x6.5mm^2 drill 1.2mm pad 2.3mm
+0
+5
+5
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type059_RT06306HBWC_1x06_P3.50mm_Horizontal
+terminal block Metz Connect Type059_RT06306HBWC, 6 pins, pitch 3.5mm, size 21x6.5mm^2, drill diamater 1.2mm, pad diameter 2.3mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310591_RT063xxHBWC_OFF-022684T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type059_RT06306HBWC pitch 3.5mm size 21x6.5mm^2 drill 1.2mm pad 2.3mm
+0
+6
+6
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type067_RT01902HDWC_1x02_P10.00mm_Horizontal
+terminal block Metz Connect Type067_RT01902HDWC, 2 pins, pitch 10mm, size 15.8x8.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310671_RT019xxHDWC_OFF-023605N.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type067_RT01902HDWC pitch 10mm size 15.8x8.2mm^2 drill 1.3mm pad 2.6mm
+0
+2
+2
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type067_RT01903HDWC_1x03_P10.00mm_Horizontal
+terminal block Metz Connect Type067_RT01903HDWC, 3 pins, pitch 10mm, size 25.8x8.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310671_RT019xxHDWC_OFF-023605N.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type067_RT01903HDWC pitch 10mm size 25.8x8.2mm^2 drill 1.3mm pad 2.6mm
+0
+3
+3
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type067_RT01904HDWC_1x04_P10.00mm_Horizontal
+terminal block Metz Connect Type067_RT01904HDWC, 4 pins, pitch 10mm, size 35.8x8.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310671_RT019xxHDWC_OFF-023605N.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type067_RT01904HDWC pitch 10mm size 35.8x8.2mm^2 drill 1.3mm pad 2.6mm
+0
+4
+4
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type067_RT01905HDWC_1x05_P10.00mm_Horizontal
+terminal block Metz Connect Type067_RT01905HDWC, 5 pins, pitch 10mm, size 45.8x8.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310671_RT019xxHDWC_OFF-023605N.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type067_RT01905HDWC pitch 10mm size 45.8x8.2mm^2 drill 1.3mm pad 2.6mm
+0
+5
+5
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type073_RT02602HBLU_1x02_P5.08mm_Horizontal
+terminal block Metz Connect Type073_RT02602HBLU, 2 pins, pitch 5.08mm, size 10.2x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310731_RT026xxHBLU_OFF-022792U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type073_RT02602HBLU pitch 5.08mm size 10.2x11mm^2 drill 1.4mm pad 2.6mm
+0
+2
+2
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type073_RT02603HBLU_1x03_P5.08mm_Horizontal
+terminal block Metz Connect Type073_RT02603HBLU, 3 pins, pitch 5.08mm, size 15.2x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310731_RT026xxHBLU_OFF-022792U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type073_RT02603HBLU pitch 5.08mm size 15.2x11mm^2 drill 1.4mm pad 2.6mm
+0
+3
+3
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type086_RT03402HBLC_1x02_P3.81mm_Horizontal
+terminal block Metz Connect Type086_RT03402HBLC, 2 pins, pitch 3.81mm, size 7.51x7.3mm^2, drill diamater 0.7mm, pad diameter 1.4mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310861_RT034xxHBLC_OFF-026114K.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type086_RT03402HBLC pitch 3.81mm size 7.51x7.3mm^2 drill 0.7mm pad 1.4mm
+0
+2
+2
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type086_RT03403HBLC_1x03_P3.81mm_Horizontal
+terminal block Metz Connect Type086_RT03403HBLC, 3 pins, pitch 3.81mm, size 11.3x7.3mm^2, drill diamater 0.7mm, pad diameter 1.4mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310861_RT034xxHBLC_OFF-026114K.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type086_RT03403HBLC pitch 3.81mm size 11.3x7.3mm^2 drill 0.7mm pad 1.4mm
+0
+3
+3
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type086_RT03404HBLC_1x04_P3.81mm_Horizontal
+terminal block Metz Connect Type086_RT03404HBLC, 4 pins, pitch 3.81mm, size 15.1x7.3mm^2, drill diamater 0.7mm, pad diameter 1.4mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310861_RT034xxHBLC_OFF-026114K.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type086_RT03404HBLC pitch 3.81mm size 15.1x7.3mm^2 drill 0.7mm pad 1.4mm
+0
+4
+4
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type086_RT03405HBLC_1x05_P3.81mm_Horizontal
+terminal block Metz Connect Type086_RT03405HBLC, 5 pins, pitch 3.81mm, size 18.9x7.3mm^2, drill diamater 0.7mm, pad diameter 1.4mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310861_RT034xxHBLC_OFF-026114K.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type086_RT03405HBLC pitch 3.81mm size 18.9x7.3mm^2 drill 0.7mm pad 1.4mm
+0
+5
+5
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type086_RT03406HBLC_1x06_P3.81mm_Horizontal
+terminal block Metz Connect Type086_RT03406HBLC, 6 pins, pitch 3.81mm, size 22.8x7.3mm^2, drill diamater 0.7mm, pad diameter 1.4mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310861_RT034xxHBLC_OFF-026114K.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type086_RT03406HBLC pitch 3.81mm size 22.8x7.3mm^2 drill 0.7mm pad 1.4mm
+0
+6
+6
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type094_RT03502HBLU_1x02_P5.00mm_Horizontal
+terminal block Metz Connect Type094_RT03502HBLU, 2 pins, pitch 5mm, size 10x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/ru/system/files/productfiles/Data_sheet_310941_RT035xxHBLU_OFF-022742T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type094_RT03502HBLU pitch 5mm size 10x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+2
+2
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type094_RT03503HBLU_1x03_P5.00mm_Horizontal
+terminal block Metz Connect Type094_RT03503HBLU, 3 pins, pitch 5mm, size 15x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/ru/system/files/productfiles/Data_sheet_310941_RT035xxHBLU_OFF-022742T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type094_RT03503HBLU pitch 5mm size 15x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+3
+3
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type094_RT03504HBLU_1x04_P5.00mm_Horizontal
+terminal block Metz Connect Type094_RT03504HBLU, 4 pins, pitch 5mm, size 20x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/ru/system/files/productfiles/Data_sheet_310941_RT035xxHBLU_OFF-022742T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type094_RT03504HBLU pitch 5mm size 20x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+4
+4
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type094_RT03505HBLU_1x05_P5.00mm_Horizontal
+terminal block Metz Connect Type094_RT03505HBLU, 5 pins, pitch 5mm, size 25x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/ru/system/files/productfiles/Data_sheet_310941_RT035xxHBLU_OFF-022742T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type094_RT03505HBLU pitch 5mm size 25x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+5
+5
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type094_RT03506HBLU_1x06_P5.00mm_Horizontal
+terminal block Metz Connect Type094_RT03506HBLU, 6 pins, pitch 5mm, size 30x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/ru/system/files/productfiles/Data_sheet_310941_RT035xxHBLU_OFF-022742T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type094_RT03506HBLU pitch 5mm size 30x8.3mm^2 drill 1.3mm pad 2.6mm
+0
+6
+6
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type101_RT01602HBWC_1x02_P5.08mm_Horizontal
+terminal block Metz Connect Type101_RT01602HBWC, 2 pins, pitch 5.08mm, size 10.2x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311011_RT016xxHBWC_OFF-022771S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type101_RT01602HBWC pitch 5.08mm size 10.2x8mm^2 drill 1.3mm pad 2.5mm
+0
+2
+2
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type101_RT01603HBWC_1x03_P5.08mm_Horizontal
+terminal block Metz Connect Type101_RT01603HBWC, 3 pins, pitch 5.08mm, size 15.2x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311011_RT016xxHBWC_OFF-022771S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type101_RT01603HBWC pitch 5.08mm size 15.2x8mm^2 drill 1.3mm pad 2.5mm
+0
+3
+3
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type101_RT01604HBWC_1x04_P5.08mm_Horizontal
+terminal block Metz Connect Type101_RT01604HBWC, 4 pins, pitch 5.08mm, size 20.3x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311011_RT016xxHBWC_OFF-022771S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type101_RT01604HBWC pitch 5.08mm size 20.3x8mm^2 drill 1.3mm pad 2.5mm
+0
+4
+4
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type101_RT01605HBWC_1x05_P5.08mm_Horizontal
+terminal block Metz Connect Type101_RT01605HBWC, 5 pins, pitch 5.08mm, size 25.4x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311011_RT016xxHBWC_OFF-022771S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type101_RT01605HBWC pitch 5.08mm size 25.4x8mm^2 drill 1.3mm pad 2.5mm
+0
+5
+5
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type101_RT01606HBWC_1x06_P5.08mm_Horizontal
+terminal block Metz Connect Type101_RT01606HBWC, 6 pins, pitch 5.08mm, size 30.5x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311011_RT016xxHBWC_OFF-022771S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type101_RT01606HBWC pitch 5.08mm size 30.5x8mm^2 drill 1.3mm pad 2.5mm
+0
+6
+6
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type171_RT13702HBWC_1x02_P7.50mm_Horizontal
+terminal block Metz Connect Type171_RT13702HBWC, 2 pins, pitch 7.5mm, size 15x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311711_RT137xxHBWC_OFF-022811Q.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type171_RT13702HBWC pitch 7.5mm size 15x9mm^2 drill 1.3mm pad 2.5mm
+0
+2
+2
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type171_RT13703HBWC_1x03_P7.50mm_Horizontal
+terminal block Metz Connect Type171_RT13703HBWC, 3 pins, pitch 7.5mm, size 22.5x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311711_RT137xxHBWC_OFF-022811Q.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type171_RT13703HBWC pitch 7.5mm size 22.5x9mm^2 drill 1.3mm pad 2.5mm
+0
+3
+3
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type171_RT13704HBWC_1x04_P7.50mm_Horizontal
+terminal block Metz Connect Type171_RT13704HBWC, 4 pins, pitch 7.5mm, size 30x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311711_RT137xxHBWC_OFF-022811Q.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type171_RT13704HBWC pitch 7.5mm size 30x9mm^2 drill 1.3mm pad 2.5mm
+0
+4
+4
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type171_RT13705HBWC_1x05_P7.50mm_Horizontal
+terminal block Metz Connect Type171_RT13705HBWC, 5 pins, pitch 7.5mm, size 37.5x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311711_RT137xxHBWC_OFF-022811Q.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type171_RT13705HBWC pitch 7.5mm size 37.5x9mm^2 drill 1.3mm pad 2.5mm
+0
+5
+5
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type171_RT13706HBWC_1x06_P7.50mm_Horizontal
+terminal block Metz Connect Type171_RT13706HBWC, 6 pins, pitch 7.5mm, size 45x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311711_RT137xxHBWC_OFF-022811Q.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type171_RT13706HBWC pitch 7.5mm size 45x9mm^2 drill 1.3mm pad 2.5mm
+0
+6
+6
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type175_RT02702HBLC_1x02_P7.50mm_Horizontal
+terminal block Metz Connect Type175_RT02702HBLC, 2 pins, pitch 7.5mm, size 15x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311751_RT027xxHBLC_OFF-022814U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type175_RT02702HBLC pitch 7.5mm size 15x11mm^2 drill 1.4mm pad 2.6mm
+0
+2
+2
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type175_RT02703HBLC_1x03_P7.50mm_Horizontal
+terminal block Metz Connect Type175_RT02703HBLC, 3 pins, pitch 7.5mm, size 22.5x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311751_RT027xxHBLC_OFF-022814U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type175_RT02703HBLC pitch 7.5mm size 22.5x11mm^2 drill 1.4mm pad 2.6mm
+0
+3
+3
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type175_RT02704HBLC_1x04_P7.50mm_Horizontal
+terminal block Metz Connect Type175_RT02704HBLC, 4 pins, pitch 7.5mm, size 30x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311751_RT027xxHBLC_OFF-022814U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type175_RT02704HBLC pitch 7.5mm size 30x11mm^2 drill 1.4mm pad 2.6mm
+0
+4
+4
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type175_RT02705HBLC_1x05_P7.50mm_Horizontal
+terminal block Metz Connect Type175_RT02705HBLC, 5 pins, pitch 7.5mm, size 37.5x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311751_RT027xxHBLC_OFF-022814U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type175_RT02705HBLC pitch 7.5mm size 37.5x11mm^2 drill 1.4mm pad 2.6mm
+0
+5
+5
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type175_RT02706HBLC_1x06_P7.50mm_Horizontal
+terminal block Metz Connect Type175_RT02706HBLC, 6 pins, pitch 7.5mm, size 45x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311751_RT027xxHBLC_OFF-022814U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type175_RT02706HBLC pitch 7.5mm size 45x11mm^2 drill 1.4mm pad 2.6mm
+0
+6
+6
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type205_RT04502UBLC_1x02_P5.00mm_45Degree
+terminal block Metz Connect Type205_RT04502UBLC, 45Degree (cable under 45degree), 2 pins, pitch 5mm, size 10x12.5mm^2, drill diamater 1.4mm, pad diameter 2.7mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_312051_RT045xxUBLC_OFF-022759T.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type205_RT04502UBLC 45Degree pitch 5mm size 10x12.5mm^2 drill 1.4mm pad 2.7mm
+0
+2
+2
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type205_RT04503UBLC_1x03_P5.00mm_45Degree
+terminal block Metz Connect Type205_RT04503UBLC, 45Degree (cable under 45degree), 3 pins, pitch 5mm, size 15x12.5mm^2, drill diamater 1.4mm, pad diameter 2.7mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_312051_RT045xxUBLC_OFF-022759T.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type205_RT04503UBLC 45Degree pitch 5mm size 15x12.5mm^2 drill 1.4mm pad 2.7mm
+0
+3
+3
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type205_RT04504UBLC_1x04_P5.00mm_45Degree
+terminal block Metz Connect Type205_RT04504UBLC, 45Degree (cable under 45degree), 4 pins, pitch 5mm, size 20x12.5mm^2, drill diamater 1.4mm, pad diameter 2.7mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_312051_RT045xxUBLC_OFF-022759T.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type205_RT04504UBLC 45Degree pitch 5mm size 20x12.5mm^2 drill 1.4mm pad 2.7mm
+0
+4
+4
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type205_RT04505UBLC_1x05_P5.00mm_45Degree
+terminal block Metz Connect Type205_RT04505UBLC, 45Degree (cable under 45degree), 5 pins, pitch 5mm, size 25x12.5mm^2, drill diamater 1.4mm, pad diameter 2.7mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_312051_RT045xxUBLC_OFF-022759T.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type205_RT04505UBLC 45Degree pitch 5mm size 25x12.5mm^2 drill 1.4mm pad 2.7mm
+0
+5
+5
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type205_RT04506UBLC_1x06_P5.00mm_45Degree
+terminal block Metz Connect Type205_RT04506UBLC, 45Degree (cable under 45degree), 6 pins, pitch 5mm, size 30x12.5mm^2, drill diamater 1.4mm, pad diameter 2.7mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_312051_RT045xxUBLC_OFF-022759T.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type205_RT04506UBLC 45Degree pitch 5mm size 30x12.5mm^2 drill 1.4mm pad 2.7mm
+0
+6
+6
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type701_RT11L02HGLU_1x02_P6.35mm_Horizontal
+terminal block Metz Connect Type701_RT11L02HGLU, 2 pins, pitch 6.35mm, size 12.7x12.5mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_317011_RT11LxxHGLU_OFF-022798U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type701_RT11L02HGLU pitch 6.35mm size 12.7x12.5mm^2 drill 1.3mm pad 2.5mm
+0
+2
+2
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type701_RT11L03HGLU_1x03_P6.35mm_Horizontal
+terminal block Metz Connect Type701_RT11L03HGLU, 3 pins, pitch 6.35mm, size 19x12.5mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_317011_RT11LxxHGLU_OFF-022798U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type701_RT11L03HGLU pitch 6.35mm size 19x12.5mm^2 drill 1.3mm pad 2.5mm
+0
+3
+3
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type703_RT10N02HGLU_1x02_P9.52mm_Horizontal
+terminal block Metz Connect Type703_RT10N02HGLU, 2 pins, pitch 9.52mm, size 19x12.5mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_317031_RT10NxxHGLU_OFF-022897S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type703_RT10N02HGLU pitch 9.52mm size 19x12.5mm^2 drill 1.3mm pad 2.6mm
+0
+2
+2
+TerminalBlock_MetzConnect
+TerminalBlock_MetzConnect_Type703_RT10N03HGLU_1x03_P9.52mm_Horizontal
+terminal block Metz Connect Type703_RT10N03HGLU, 3 pins, pitch 9.52mm, size 28.6x12.5mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_317031_RT10NxxHGLU_OFF-022897S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect
+THT terminal block Metz Connect Type703_RT10N03HGLU pitch 9.52mm size 28.6x12.5mm^2 drill 1.3mm pad 2.6mm
+0
+3
+3
+TerminalBlock_Philmore
+TerminalBlock_Philmore_TB132_1x02_P5.00mm_Horizontal
+Terminal Block Philmore , 2 pins, pitch 5mm, size 10x10.2mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.philmore-datak.com/mc/Page%20197.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Philmore
+THT Terminal Block Philmore  pitch 5mm size 10x10.2mm^2 drill 1.2mm pad 2.4mm
+0
+2
+2
+TerminalBlock_Philmore
+TerminalBlock_Philmore_TB133_1x03_P5.00mm_Horizontal
+Terminal Block Philmore , 3 pins, pitch 5mm, size 15x10.2mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.philmore-datak.com/mc/Page%20197.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Philmore
+THT Terminal Block Philmore  pitch 5mm size 15x10.2mm^2 drill 1.2mm pad 2.4mm
+0
+3
+3
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-2-5.08_1x02_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-2-5.08, 2 pins, pitch 5.08mm, size 10.2x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-2-5.08 pitch 5.08mm size 10.2x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+2
+2
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-2_1x02_P5.00mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-2, 2 pins, pitch 5mm, size 10x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-2 pitch 5mm size 10x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+2
+2
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-3-5.08_1x03_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-3-5.08, 3 pins, pitch 5.08mm, size 15.2x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-3-5.08 pitch 5.08mm size 15.2x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+3
+3
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-3_1x03_P5.00mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-3, 3 pins, pitch 5mm, size 15x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-3 pitch 5mm size 15x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+3
+3
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-4-5.08_1x04_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-4-5.08, 4 pins, pitch 5.08mm, size 20.3x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-4-5.08 pitch 5.08mm size 20.3x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+4
+4
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-4_1x04_P5.00mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-4, 4 pins, pitch 5mm, size 20x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-4 pitch 5mm size 20x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+4
+4
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-5-5.08_1x05_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-5-5.08, 5 pins, pitch 5.08mm, size 25.4x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-5-5.08 pitch 5.08mm size 25.4x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+5
+5
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-5_1x05_P5.00mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-5, 5 pins, pitch 5mm, size 25x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-5 pitch 5mm size 25x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+5
+5
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-6-5.08_1x06_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-6-5.08, 6 pins, pitch 5.08mm, size 30.5x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-6-5.08 pitch 5.08mm size 30.5x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+6
+6
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-6_1x06_P5.00mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-6, 6 pins, pitch 5mm, size 30x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-6 pitch 5mm size 30x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+6
+6
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-7-5.08_1x07_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-7-5.08, 7 pins, pitch 5.08mm, size 35.6x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-7-5.08 pitch 5.08mm size 35.6x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+7
+7
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-7_1x07_P5.00mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-7, 7 pins, pitch 5mm, size 35x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-7 pitch 5mm size 35x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+7
+7
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-8-5.08_1x08_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-8-5.08, 8 pins, pitch 5.08mm, size 40.6x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-8-5.08 pitch 5.08mm size 40.6x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+8
+8
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-8_1x08_P5.00mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-8, 8 pins, pitch 5mm, size 40x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-8 pitch 5mm size 40x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+8
+8
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-9-5.08_1x09_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-9-5.08, 9 pins, pitch 5.08mm, size 45.7x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-9-5.08 pitch 5.08mm size 45.7x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+9
+9
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-9_1x09_P5.00mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-9, 9 pins, pitch 5mm, size 45x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-9 pitch 5mm size 45x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+9
+9
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-10-5.08_1x10_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-10-5.08, 10 pins, pitch 5.08mm, size 50.8x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-10-5.08 pitch 5.08mm size 50.8x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+10
+10
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-10_1x10_P5.00mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-10, 10 pins, pitch 5mm, size 50x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-10 pitch 5mm size 50x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+10
+10
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-11-5.08_1x11_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-11-5.08, 11 pins, pitch 5.08mm, size 55.9x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-11-5.08 pitch 5.08mm size 55.9x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+11
+11
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-11_1x11_P5.00mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-11, 11 pins, pitch 5mm, size 55x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-11 pitch 5mm size 55x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+11
+11
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-12-5.08_1x12_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-12-5.08, 12 pins, pitch 5.08mm, size 61x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-12-5.08 pitch 5.08mm size 61x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+12
+12
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-12_1x12_P5.00mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-12, 12 pins, pitch 5mm, size 60x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-12 pitch 5mm size 60x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+12
+12
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-13-5.08_1x13_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-13-5.08, 13 pins, pitch 5.08mm, size 66x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-13-5.08 pitch 5.08mm size 66x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+13
+13
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-13_1x13_P5.00mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-13, 13 pins, pitch 5mm, size 65x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-13 pitch 5mm size 65x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+13
+13
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-14-5.08_1x14_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-14-5.08, 14 pins, pitch 5.08mm, size 71.1x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-14-5.08 pitch 5.08mm size 71.1x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+14
+14
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-14_1x14_P5.00mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-14, 14 pins, pitch 5mm, size 70x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-14 pitch 5mm size 70x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+14
+14
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-15-5.08_1x15_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-15-5.08, 15 pins, pitch 5.08mm, size 76.2x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-15-5.08 pitch 5.08mm size 76.2x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+15
+15
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-15_1x15_P5.00mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-15, 15 pins, pitch 5mm, size 75x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-15 pitch 5mm size 75x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+15
+15
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-16-5.08_1x16_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-16-5.08, 16 pins, pitch 5.08mm, size 81.3x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-16-5.08 pitch 5.08mm size 81.3x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+16
+16
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-1,5-16_1x16_P5.00mm_Horizontal
+Terminal Block Phoenix MKDS-1,5-16, 16 pins, pitch 5mm, size 80x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-1,5-16 pitch 5mm size 80x9.8mm^2 drill 1.3mm pad 2.6mm
+0
+16
+16
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-3-2-5.08_1x02_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-3-2-5.08, 2 pins, pitch 5.08mm, size 10.2x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-3-2-5.08 pitch 5.08mm size 10.2x11.2mm^2 drill 1.3mm pad 2.6mm
+0
+2
+2
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-3-3-5.08_1x03_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-3-3-5.08, 3 pins, pitch 5.08mm, size 15.2x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-3-3-5.08 pitch 5.08mm size 15.2x11.2mm^2 drill 1.3mm pad 2.6mm
+0
+3
+3
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-3-4-5.08_1x04_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-3-4-5.08, 4 pins, pitch 5.08mm, size 20.3x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-3-4-5.08 pitch 5.08mm size 20.3x11.2mm^2 drill 1.3mm pad 2.6mm
+0
+4
+4
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-3-5-5.08_1x05_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-3-5-5.08, 5 pins, pitch 5.08mm, size 25.4x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-3-5-5.08 pitch 5.08mm size 25.4x11.2mm^2 drill 1.3mm pad 2.6mm
+0
+5
+5
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-3-6-5.08_1x06_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-3-6-5.08, 6 pins, pitch 5.08mm, size 30.5x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-3-6-5.08 pitch 5.08mm size 30.5x11.2mm^2 drill 1.3mm pad 2.6mm
+0
+6
+6
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-3-7-5.08_1x07_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-3-7-5.08, 7 pins, pitch 5.08mm, size 35.6x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-3-7-5.08 pitch 5.08mm size 35.6x11.2mm^2 drill 1.3mm pad 2.6mm
+0
+7
+7
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-3-8-5.08_1x08_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-3-8-5.08, 8 pins, pitch 5.08mm, size 40.6x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-3-8-5.08 pitch 5.08mm size 40.6x11.2mm^2 drill 1.3mm pad 2.6mm
+0
+8
+8
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-3-9-5.08_1x09_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-3-9-5.08, 9 pins, pitch 5.08mm, size 45.7x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-3-9-5.08 pitch 5.08mm size 45.7x11.2mm^2 drill 1.3mm pad 2.6mm
+0
+9
+9
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-3-10-5.08_1x10_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-3-10-5.08, 10 pins, pitch 5.08mm, size 50.8x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-3-10-5.08 pitch 5.08mm size 50.8x11.2mm^2 drill 1.3mm pad 2.6mm
+0
+10
+10
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-3-11-5.08_1x11_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-3-11-5.08, 11 pins, pitch 5.08mm, size 55.9x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-3-11-5.08 pitch 5.08mm size 55.9x11.2mm^2 drill 1.3mm pad 2.6mm
+0
+11
+11
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-3-12-5.08_1x12_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-3-12-5.08, 12 pins, pitch 5.08mm, size 61x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-3-12-5.08 pitch 5.08mm size 61x11.2mm^2 drill 1.3mm pad 2.6mm
+0
+12
+12
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-3-13-5.08_1x13_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-3-13-5.08, 13 pins, pitch 5.08mm, size 66x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-3-13-5.08 pitch 5.08mm size 66x11.2mm^2 drill 1.3mm pad 2.6mm
+0
+13
+13
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-3-14-5.08_1x14_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-3-14-5.08, 14 pins, pitch 5.08mm, size 71.1x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-3-14-5.08 pitch 5.08mm size 71.1x11.2mm^2 drill 1.3mm pad 2.6mm
+0
+14
+14
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-3-15-5.08_1x15_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-3-15-5.08, 15 pins, pitch 5.08mm, size 76.2x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-3-15-5.08 pitch 5.08mm size 76.2x11.2mm^2 drill 1.3mm pad 2.6mm
+0
+15
+15
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MKDS-3-16-5.08_1x16_P5.08mm_Horizontal
+Terminal Block Phoenix MKDS-3-16-5.08, 16 pins, pitch 5.08mm, size 81.3x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MKDS-3-16-5.08 pitch 5.08mm size 81.3x11.2mm^2 drill 1.3mm pad 2.6mm
+0
+16
+16
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MPT-0,5-2-2.54_1x02_P2.54mm_Horizontal
+Terminal Block Phoenix MPT-0,5-2-2.54, 2 pins, pitch 2.54mm, size 5.54x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725656-920552.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MPT-0,5-2-2.54 pitch 2.54mm size 5.54x6.2mm^2 drill 1.1mm pad 2.2mm
+0
+2
+2
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MPT-0,5-3-2.54_1x03_P2.54mm_Horizontal
+Terminal Block Phoenix MPT-0,5-3-2.54, 3 pins, pitch 2.54mm, size 8.08x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725656-920552.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MPT-0,5-3-2.54 pitch 2.54mm size 8.08x6.2mm^2 drill 1.1mm pad 2.2mm
+0
+3
+3
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MPT-0,5-4-2.54_1x04_P2.54mm_Horizontal
+Terminal Block Phoenix MPT-0,5-4-2.54, 4 pins, pitch 2.54mm, size 10.6x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MPT-0,5-4-2.54 pitch 2.54mm size 10.6x6.2mm^2 drill 1.1mm pad 2.2mm
+0
+4
+4
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MPT-0,5-5-2.54_1x05_P2.54mm_Horizontal
+Terminal Block Phoenix MPT-0,5-5-2.54, 5 pins, pitch 2.54mm, size 13.2x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MPT-0,5-5-2.54 pitch 2.54mm size 13.2x6.2mm^2 drill 1.1mm pad 2.2mm
+0
+5
+5
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MPT-0,5-6-2.54_1x06_P2.54mm_Horizontal
+Terminal Block Phoenix MPT-0,5-6-2.54, 6 pins, pitch 2.54mm, size 15.7x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MPT-0,5-6-2.54 pitch 2.54mm size 15.7x6.2mm^2 drill 1.1mm pad 2.2mm
+0
+6
+6
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MPT-0,5-7-2.54_1x07_P2.54mm_Horizontal
+Terminal Block Phoenix MPT-0,5-7-2.54, 7 pins, pitch 2.54mm, size 18.2x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MPT-0,5-7-2.54 pitch 2.54mm size 18.2x6.2mm^2 drill 1.1mm pad 2.2mm
+0
+7
+7
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MPT-0,5-8-2.54_1x08_P2.54mm_Horizontal
+Terminal Block Phoenix MPT-0,5-8-2.54, 8 pins, pitch 2.54mm, size 20.8x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MPT-0,5-8-2.54 pitch 2.54mm size 20.8x6.2mm^2 drill 1.1mm pad 2.2mm
+0
+8
+8
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MPT-0,5-9-2.54_1x09_P2.54mm_Horizontal
+Terminal Block Phoenix MPT-0,5-9-2.54, 9 pins, pitch 2.54mm, size 23.3x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MPT-0,5-9-2.54 pitch 2.54mm size 23.3x6.2mm^2 drill 1.1mm pad 2.2mm
+0
+9
+9
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MPT-0,5-10-2.54_1x10_P2.54mm_Horizontal
+Terminal Block Phoenix MPT-0,5-10-2.54, 10 pins, pitch 2.54mm, size 25.9x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MPT-0,5-10-2.54 pitch 2.54mm size 25.9x6.2mm^2 drill 1.1mm pad 2.2mm
+0
+10
+10
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MPT-0,5-11-2.54_1x11_P2.54mm_Horizontal
+Terminal Block Phoenix MPT-0,5-11-2.54, 11 pins, pitch 2.54mm, size 28.4x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MPT-0,5-11-2.54 pitch 2.54mm size 28.4x6.2mm^2 drill 1.1mm pad 2.2mm
+0
+11
+11
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_MPT-0,5-12-2.54_1x12_P2.54mm_Horizontal
+Terminal Block Phoenix MPT-0,5-12-2.54, 12 pins, pitch 2.54mm, size 30.9x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix MPT-0,5-12-2.54 pitch 2.54mm size 30.9x6.2mm^2 drill 1.1mm pad 2.2mm
+0
+12
+12
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-2-3.5-H_1x02_P3.50mm_Horizontal
+Terminal Block Phoenix PT-1,5-2-3.5-H, 2 pins, pitch 3.5mm, size 7x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-2-3.5-H pitch 3.5mm size 7x7.6mm^2 drill 1.2mm pad 2.4mm
+0
+2
+2
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-2-5.0-H_1x02_P5.00mm_Horizontal
+Terminal Block Phoenix PT-1,5-2-5.0-H, 2 pins, pitch 5mm, size 10x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-2-5.0-H pitch 5mm size 10x9mm^2 drill 1.3mm pad 2.6mm
+0
+2
+2
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-3-3.5-H_1x03_P3.50mm_Horizontal
+Terminal Block Phoenix PT-1,5-3-3.5-H, 3 pins, pitch 3.5mm, size 10.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-3-3.5-H pitch 3.5mm size 10.5x7.6mm^2 drill 1.2mm pad 2.4mm
+0
+3
+3
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-3-5.0-H_1x03_P5.00mm_Horizontal
+Terminal Block Phoenix PT-1,5-3-5.0-H, 3 pins, pitch 5mm, size 15x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-3-5.0-H pitch 5mm size 15x9mm^2 drill 1.3mm pad 2.6mm
+0
+3
+3
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-4-3.5-H_1x04_P3.50mm_Horizontal
+Terminal Block Phoenix PT-1,5-4-3.5-H, 4 pins, pitch 3.5mm, size 14x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-4-3.5-H pitch 3.5mm size 14x7.6mm^2 drill 1.2mm pad 2.4mm
+0
+4
+4
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-4-5.0-H_1x04_P5.00mm_Horizontal
+Terminal Block Phoenix PT-1,5-4-5.0-H, 4 pins, pitch 5mm, size 20x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-4-5.0-H pitch 5mm size 20x9mm^2 drill 1.3mm pad 2.6mm
+0
+4
+4
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-5-3.5-H_1x05_P3.50mm_Horizontal
+Terminal Block Phoenix PT-1,5-5-3.5-H, 5 pins, pitch 3.5mm, size 17.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-5-3.5-H pitch 3.5mm size 17.5x7.6mm^2 drill 1.2mm pad 2.4mm
+0
+5
+5
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-5-5.0-H_1x05_P5.00mm_Horizontal
+Terminal Block Phoenix PT-1,5-5-5.0-H, 5 pins, pitch 5mm, size 25x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-5-5.0-H pitch 5mm size 25x9mm^2 drill 1.3mm pad 2.6mm
+0
+5
+5
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-6-3.5-H_1x06_P3.50mm_Horizontal
+Terminal Block Phoenix PT-1,5-6-3.5-H, 6 pins, pitch 3.5mm, size 21x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-6-3.5-H pitch 3.5mm size 21x7.6mm^2 drill 1.2mm pad 2.4mm
+0
+6
+6
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-6-5.0-H_1x06_P5.00mm_Horizontal
+Terminal Block Phoenix PT-1,5-6-5.0-H, 6 pins, pitch 5mm, size 30x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-6-5.0-H pitch 5mm size 30x9mm^2 drill 1.3mm pad 2.6mm
+0
+6
+6
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-7-3.5-H_1x07_P3.50mm_Horizontal
+Terminal Block Phoenix PT-1,5-7-3.5-H, 7 pins, pitch 3.5mm, size 24.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-7-3.5-H pitch 3.5mm size 24.5x7.6mm^2 drill 1.2mm pad 2.4mm
+0
+7
+7
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-7-5.0-H_1x07_P5.00mm_Horizontal
+Terminal Block Phoenix PT-1,5-7-5.0-H, 7 pins, pitch 5mm, size 35x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-7-5.0-H pitch 5mm size 35x9mm^2 drill 1.3mm pad 2.6mm
+0
+7
+7
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-8-3.5-H_1x08_P3.50mm_Horizontal
+Terminal Block Phoenix PT-1,5-8-3.5-H, 8 pins, pitch 3.5mm, size 28x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-8-3.5-H pitch 3.5mm size 28x7.6mm^2 drill 1.2mm pad 2.4mm
+0
+8
+8
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-8-5.0-H_1x08_P5.00mm_Horizontal
+Terminal Block Phoenix PT-1,5-8-5.0-H, 8 pins, pitch 5mm, size 40x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-8-5.0-H pitch 5mm size 40x9mm^2 drill 1.3mm pad 2.6mm
+0
+8
+8
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-9-3.5-H_1x09_P3.50mm_Horizontal
+Terminal Block Phoenix PT-1,5-9-3.5-H, 9 pins, pitch 3.5mm, size 31.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-9-3.5-H pitch 3.5mm size 31.5x7.6mm^2 drill 1.2mm pad 2.4mm
+0
+9
+9
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-9-5.0-H_1x09_P5.00mm_Horizontal
+Terminal Block Phoenix PT-1,5-9-5.0-H, 9 pins, pitch 5mm, size 45x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-9-5.0-H pitch 5mm size 45x9mm^2 drill 1.3mm pad 2.6mm
+0
+9
+9
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-10-3.5-H_1x10_P3.50mm_Horizontal
+Terminal Block Phoenix PT-1,5-10-3.5-H, 10 pins, pitch 3.5mm, size 35x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-10-3.5-H pitch 3.5mm size 35x7.6mm^2 drill 1.2mm pad 2.4mm
+0
+10
+10
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-10-5.0-H_1x10_P5.00mm_Horizontal
+Terminal Block Phoenix PT-1,5-10-5.0-H, 10 pins, pitch 5mm, size 50x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-10-5.0-H pitch 5mm size 50x9mm^2 drill 1.3mm pad 2.6mm
+0
+10
+10
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-11-3.5-H_1x11_P3.50mm_Horizontal
+Terminal Block Phoenix PT-1,5-11-3.5-H, 11 pins, pitch 3.5mm, size 38.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-11-3.5-H pitch 3.5mm size 38.5x7.6mm^2 drill 1.2mm pad 2.4mm
+0
+11
+11
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-11-5.0-H_1x11_P5.00mm_Horizontal
+Terminal Block Phoenix PT-1,5-11-5.0-H, 11 pins, pitch 5mm, size 55x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-11-5.0-H pitch 5mm size 55x9mm^2 drill 1.3mm pad 2.6mm
+0
+11
+11
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-12-3.5-H_1x12_P3.50mm_Horizontal
+Terminal Block Phoenix PT-1,5-12-3.5-H, 12 pins, pitch 3.5mm, size 42x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-12-3.5-H pitch 3.5mm size 42x7.6mm^2 drill 1.2mm pad 2.4mm
+0
+12
+12
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-12-5.0-H_1x12_P5.00mm_Horizontal
+Terminal Block Phoenix PT-1,5-12-5.0-H, 12 pins, pitch 5mm, size 60x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-12-5.0-H pitch 5mm size 60x9mm^2 drill 1.3mm pad 2.6mm
+0
+12
+12
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-13-3.5-H_1x13_P3.50mm_Horizontal
+Terminal Block Phoenix PT-1,5-13-3.5-H, 13 pins, pitch 3.5mm, size 45.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-13-3.5-H pitch 3.5mm size 45.5x7.6mm^2 drill 1.2mm pad 2.4mm
+0
+13
+13
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-13-5.0-H_1x13_P5.00mm_Horizontal
+Terminal Block Phoenix PT-1,5-13-5.0-H, 13 pins, pitch 5mm, size 65x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-13-5.0-H pitch 5mm size 65x9mm^2 drill 1.3mm pad 2.6mm
+0
+13
+13
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-14-3.5-H_1x14_P3.50mm_Horizontal
+Terminal Block Phoenix PT-1,5-14-3.5-H, 14 pins, pitch 3.5mm, size 49x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-14-3.5-H pitch 3.5mm size 49x7.6mm^2 drill 1.2mm pad 2.4mm
+0
+14
+14
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-14-5.0-H_1x14_P5.00mm_Horizontal
+Terminal Block Phoenix PT-1,5-14-5.0-H, 14 pins, pitch 5mm, size 70x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-14-5.0-H pitch 5mm size 70x9mm^2 drill 1.3mm pad 2.6mm
+0
+14
+14
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-15-3.5-H_1x15_P3.50mm_Horizontal
+Terminal Block Phoenix PT-1,5-15-3.5-H, 15 pins, pitch 3.5mm, size 52.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-15-3.5-H pitch 3.5mm size 52.5x7.6mm^2 drill 1.2mm pad 2.4mm
+0
+15
+15
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-15-5.0-H_1x15_P5.00mm_Horizontal
+Terminal Block Phoenix PT-1,5-15-5.0-H, 15 pins, pitch 5mm, size 75x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-15-5.0-H pitch 5mm size 75x9mm^2 drill 1.3mm pad 2.6mm
+0
+15
+15
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-16-3.5-H_1x16_P3.50mm_Horizontal
+Terminal Block Phoenix PT-1,5-16-3.5-H, 16 pins, pitch 3.5mm, size 56x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-16-3.5-H pitch 3.5mm size 56x7.6mm^2 drill 1.2mm pad 2.4mm
+0
+16
+16
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PT-1,5-16-5.0-H_1x16_P5.00mm_Horizontal
+Terminal Block Phoenix PT-1,5-16-5.0-H, 16 pins, pitch 5mm, size 80x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PT-1,5-16-5.0-H pitch 5mm size 80x9mm^2 drill 1.3mm pad 2.6mm
+0
+16
+16
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-2-2,5-V-SMD_1x02-1MP_P2.50mm_Vertical
+PhoenixContact PTSM0,5 2 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814702/pdf
+PhoenixContact PTSM0.5 2 2.5mm vertical SMD spring clamp terminal block connector 
+0
+4
+3
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-2-2.5-H-THR_1x02_P2.50mm_Horizontal
+Terminal Block Phoenix PTSM-0,5-2-2.5-H-THR, 2 pins, pitch 2.5mm, size 7.2x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PTSM-0,5-2-2.5-H-THR pitch 2.5mm size 7.2x10mm^2 drill 1.2mm pad 3mm
+0
+4
+2
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-2-2.5-V-THR_1x02_P2.50mm_Vertical
+Terminal Block Phoenix PTSM-0,5-2-2.5-V-THR, vertical (cable from top), 2 pins, pitch 2.5mm, size 5.5x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PTSM-0,5-2-2.5-V-THR vertical pitch 2.5mm size 5.5x5mm^2 drill 1.2mm pad 2mm
+0
+4
+2
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-2-HV-2.5-SMD_1x02-1MP_P2.50mm_Vertical
+PhoenixContact PTSM0,5 2 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778696/pdf
+2.5mm vertical SMD spring clamp terminal block connector 
+0
+4
+3
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-3-2,5-V-SMD_1x03-1MP_P2.50mm_Vertical
+PhoenixContact PTSM0,5 3 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814715/pdf
+PhoenixContact PTSM0.5 3 2.5mm vertical SMD spring clamp terminal block connector 
+0
+5
+4
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-3-2.5-H-THR_1x03_P2.50mm_Horizontal
+Terminal Block Phoenix PTSM-0,5-3-2.5-H-THR, 3 pins, pitch 2.5mm, size 9.7x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PTSM-0,5-3-2.5-H-THR pitch 2.5mm size 9.7x10mm^2 drill 1.2mm pad 3mm
+0
+6
+3
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-3-2.5-V-THR_1x03_P2.50mm_Vertical
+Terminal Block Phoenix PTSM-0,5-3-2.5-V-THR, vertical (cable from top), 3 pins, pitch 2.5mm, size 8x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PTSM-0,5-3-2.5-V-THR vertical pitch 2.5mm size 8x5mm^2 drill 1.2mm pad 2mm
+0
+6
+3
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-3-HV-2.5-SMD_1x03-1MP_P2.50mm_Vertical
+PhoenixContact PTSM0,5 3 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778706/pdf
+2.5mm vertical SMD spring clamp terminal block connector 
+0
+5
+4
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-4-2,5-V-SMD_1x04-1MP_P2.50mm_Vertical
+PhoenixContact PTSM0,5 4 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814728/pdf
+PhoenixContact PTSM0.5 4 2.5mm vertical SMD spring clamp terminal block connector 
+0
+6
+5
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-4-2.5-H-THR_1x04_P2.50mm_Horizontal
+Terminal Block Phoenix PTSM-0,5-4-2.5-H-THR, 4 pins, pitch 2.5mm, size 12.2x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PTSM-0,5-4-2.5-H-THR pitch 2.5mm size 12.2x10mm^2 drill 1.2mm pad 3mm
+0
+8
+4
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-4-2.5-V-THR_1x04_P2.50mm_Vertical
+Terminal Block Phoenix PTSM-0,5-4-2.5-V-THR, vertical (cable from top), 4 pins, pitch 2.5mm, size 10.5x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PTSM-0,5-4-2.5-V-THR vertical pitch 2.5mm size 10.5x5mm^2 drill 1.2mm pad 2mm
+0
+8
+4
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-4-HV-2.5-SMD_1x04-1MP_P2.50mm_Vertical
+PhoenixContact PTSM0,5 4 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778719/pdf
+2.5mm vertical SMD spring clamp terminal block connector 
+0
+4
+3
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-5-2,5-V-SMD_1x05-1MP_P2.50mm_Vertical
+PhoenixContact PTSM0,5 5 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814731/pdf
+PhoenixContact PTSM0.5 5 2.5mm vertical SMD spring clamp terminal block connector 
+0
+7
+6
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-5-2.5-H-THR_1x05_P2.50mm_Horizontal
+Terminal Block Phoenix PTSM-0,5-5-2.5-H-THR, 5 pins, pitch 2.5mm, size 14.7x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PTSM-0,5-5-2.5-H-THR pitch 2.5mm size 14.7x10mm^2 drill 1.2mm pad 3mm
+0
+10
+5
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-5-2.5-V-THR_1x05_P2.50mm_Vertical
+Terminal Block Phoenix PTSM-0,5-5-2.5-V-THR, vertical (cable from top), 5 pins, pitch 2.5mm, size 13x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PTSM-0,5-5-2.5-V-THR vertical pitch 2.5mm size 13x5mm^2 drill 1.2mm pad 2mm
+0
+10
+5
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-5-HV-2.5-SMD_1x05-1MP_P2.50mm_Vertical
+PhoenixContact PTSM0,5 5 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778722/pdf
+2.5mm vertical SMD spring clamp terminal block connector 
+0
+7
+6
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-6-2,5-V-SMD_1x06-1MP_P2.50mm_Vertical
+PhoenixContact PTSM0,5 6 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814744/pdf
+PhoenixContact PTSM0.5 6 2.5mm vertical SMD spring clamp terminal block connector 
+0
+8
+7
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-6-2.5-H-THR_1x06_P2.50mm_Horizontal
+Terminal Block Phoenix PTSM-0,5-6-2.5-H-THR, 6 pins, pitch 2.5mm, size 17.2x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PTSM-0,5-6-2.5-H-THR pitch 2.5mm size 17.2x10mm^2 drill 1.2mm pad 3mm
+0
+12
+6
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-6-2.5-V-THR_1x06_P2.50mm_Vertical
+Terminal Block Phoenix PTSM-0,5-6-2.5-V-THR, vertical (cable from top), 6 pins, pitch 2.5mm, size 15.5x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PTSM-0,5-6-2.5-V-THR vertical pitch 2.5mm size 15.5x5mm^2 drill 1.2mm pad 2mm
+0
+12
+6
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-6-HV-2.5-SMD_1x06-1MP_P2.50mm_Vertical
+PhoenixContact PTSM0,5 6 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778735/pdf
+2.5mm vertical SMD spring clamp terminal block connector 
+0
+8
+7
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-7-2,5-V-SMD_1x07-1MP_P2.50mm_Vertical
+PhoenixContact PTSM0,5 7 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814757/pdf
+PhoenixContact PTSM0.5 7 2.5mm vertical SMD spring clamp terminal block connector 
+0
+9
+8
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-7-2.5-H-THR_1x07_P2.50mm_Horizontal
+Terminal Block Phoenix PTSM-0,5-7-2.5-H-THR, 7 pins, pitch 2.5mm, size 19.7x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PTSM-0,5-7-2.5-H-THR pitch 2.5mm size 19.7x10mm^2 drill 1.2mm pad 3mm
+0
+14
+7
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-7-2.5-V-THR_1x07_P2.50mm_Vertical
+Terminal Block Phoenix PTSM-0,5-7-2.5-V-THR, vertical (cable from top), 7 pins, pitch 2.5mm, size 18x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PTSM-0,5-7-2.5-V-THR vertical pitch 2.5mm size 18x5mm^2 drill 1.2mm pad 2mm
+0
+14
+7
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-7-HV-2.5-SMD_1x07-1MP_P2.50mm_Vertical
+PhoenixContact PTSM0,5 7 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778748/pdf
+2.5mm vertical SMD spring clamp terminal block connector 
+0
+9
+8
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-8-2,5-V-SMD_1x08-1MP_P2.50mm_Vertical
+PhoenixContact PTSM0,5 8 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814760/pdf
+PhoenixContact PTSM0.5 8 2.5mm vertical SMD spring clamp terminal block connector 
+0
+10
+9
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-8-2.5-H-THR_1x08_P2.50mm_Horizontal
+Terminal Block Phoenix PTSM-0,5-8-2.5-H-THR, 8 pins, pitch 2.5mm, size 22.2x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PTSM-0,5-8-2.5-H-THR pitch 2.5mm size 22.2x10mm^2 drill 1.2mm pad 3mm
+0
+16
+8
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-8-2.5-V-THR_1x08_P2.50mm_Vertical
+Terminal Block Phoenix PTSM-0,5-8-2.5-V-THR, vertical (cable from top), 8 pins, pitch 2.5mm, size 20.5x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix
+THT Terminal Block Phoenix PTSM-0,5-8-2.5-V-THR vertical pitch 2.5mm size 20.5x5mm^2 drill 1.2mm pad 2mm
+0
+16
+8
+TerminalBlock_Phoenix
+TerminalBlock_Phoenix_PTSM-0,5-8-HV-2.5-SMD_1x08-1MP_P2.50mm_Vertical
+PhoenixContact PTSM0,5 8 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778751/pdf
+2.5mm vertical SMD spring clamp terminal block connector 
+0
+10
+9
+TerminalBlock_RND
+TerminalBlock_RND_205-00001_1x02_P5.00mm_Horizontal
+terminal block RND 205-00001, 2 pins, pitch 5mm, size 10x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00001 pitch 5mm size 10x9mm^2 drill 1.3mm pad 2.5mm
+0
+2
+2
+TerminalBlock_RND
+TerminalBlock_RND_205-00002_1x03_P5.00mm_Horizontal
+terminal block RND 205-00002, 3 pins, pitch 5mm, size 15x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00002 pitch 5mm size 15x9mm^2 drill 1.3mm pad 2.5mm
+0
+3
+3
+TerminalBlock_RND
+TerminalBlock_RND_205-00003_1x04_P5.00mm_Horizontal
+terminal block RND 205-00003, 4 pins, pitch 5mm, size 20x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00003 pitch 5mm size 20x9mm^2 drill 1.3mm pad 2.5mm
+0
+4
+4
+TerminalBlock_RND
+TerminalBlock_RND_205-00004_1x05_P5.00mm_Horizontal
+terminal block RND 205-00004, 5 pins, pitch 5mm, size 25x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00004 pitch 5mm size 25x9mm^2 drill 1.3mm pad 2.5mm
+0
+5
+5
+TerminalBlock_RND
+TerminalBlock_RND_205-00005_1x06_P5.00mm_Horizontal
+terminal block RND 205-00005, 6 pins, pitch 5mm, size 30x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00005 pitch 5mm size 30x9mm^2 drill 1.3mm pad 2.5mm
+0
+6
+6
+TerminalBlock_RND
+TerminalBlock_RND_205-00006_1x07_P5.00mm_Horizontal
+terminal block RND 205-00006, 7 pins, pitch 5mm, size 35x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00006 pitch 5mm size 35x9mm^2 drill 1.3mm pad 2.5mm
+0
+7
+7
+TerminalBlock_RND
+TerminalBlock_RND_205-00007_1x08_P5.00mm_Horizontal
+terminal block RND 205-00007, 8 pins, pitch 5mm, size 40x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00007 pitch 5mm size 40x9mm^2 drill 1.3mm pad 2.5mm
+0
+8
+8
+TerminalBlock_RND
+TerminalBlock_RND_205-00008_1x09_P5.00mm_Horizontal
+terminal block RND 205-00008, 9 pins, pitch 5mm, size 45x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00008 pitch 5mm size 45x9mm^2 drill 1.3mm pad 2.5mm
+0
+9
+9
+TerminalBlock_RND
+TerminalBlock_RND_205-00009_1x10_P5.00mm_Horizontal
+terminal block RND 205-00009, 10 pins, pitch 5mm, size 50x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00009 pitch 5mm size 50x9mm^2 drill 1.3mm pad 2.5mm
+0
+10
+10
+TerminalBlock_RND
+TerminalBlock_RND_205-00010_1x11_P5.00mm_Horizontal
+terminal block RND 205-00010, 11 pins, pitch 5mm, size 55x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00010 pitch 5mm size 55x9mm^2 drill 1.3mm pad 2.5mm
+0
+11
+11
+TerminalBlock_RND
+TerminalBlock_RND_205-00011_1x12_P5.00mm_Horizontal
+terminal block RND 205-00011, 12 pins, pitch 5mm, size 60x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00011 pitch 5mm size 60x9mm^2 drill 1.3mm pad 2.5mm
+0
+12
+12
+TerminalBlock_RND
+TerminalBlock_RND_205-00012_1x02_P5.00mm_Horizontal
+terminal block RND 205-00012, 2 pins, pitch 5mm, size 10x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00012 pitch 5mm size 10x7.6mm^2 drill 1.3mm pad 2.5mm
+0
+2
+2
+TerminalBlock_RND
+TerminalBlock_RND_205-00013_1x03_P5.00mm_Horizontal
+terminal block RND 205-00013, 3 pins, pitch 5mm, size 15x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00013 pitch 5mm size 15x7.6mm^2 drill 1.3mm pad 2.5mm
+0
+3
+3
+TerminalBlock_RND
+TerminalBlock_RND_205-00014_1x04_P5.00mm_Horizontal
+terminal block RND 205-00014, 4 pins, pitch 5mm, size 20x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00014 pitch 5mm size 20x7.6mm^2 drill 1.3mm pad 2.5mm
+0
+4
+4
+TerminalBlock_RND
+TerminalBlock_RND_205-00015_1x05_P5.00mm_Horizontal
+terminal block RND 205-00015, 5 pins, pitch 5mm, size 25x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00015 pitch 5mm size 25x7.6mm^2 drill 1.3mm pad 2.5mm
+0
+5
+5
+TerminalBlock_RND
+TerminalBlock_RND_205-00016_1x06_P5.00mm_Horizontal
+terminal block RND 205-00016, 6 pins, pitch 5mm, size 30x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00016 pitch 5mm size 30x7.6mm^2 drill 1.3mm pad 2.5mm
+0
+6
+6
+TerminalBlock_RND
+TerminalBlock_RND_205-00017_1x07_P5.00mm_Horizontal
+terminal block RND 205-00017, 7 pins, pitch 5mm, size 35x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00017 pitch 5mm size 35x7.6mm^2 drill 1.3mm pad 2.5mm
+0
+7
+7
+TerminalBlock_RND
+TerminalBlock_RND_205-00018_1x08_P5.00mm_Horizontal
+terminal block RND 205-00018, 8 pins, pitch 5mm, size 40x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00018 pitch 5mm size 40x7.6mm^2 drill 1.3mm pad 2.5mm
+0
+8
+8
+TerminalBlock_RND
+TerminalBlock_RND_205-00019_1x09_P5.00mm_Horizontal
+terminal block RND 205-00019, 9 pins, pitch 5mm, size 45x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00019 pitch 5mm size 45x7.6mm^2 drill 1.3mm pad 2.5mm
+0
+9
+9
+TerminalBlock_RND
+TerminalBlock_RND_205-00020_1x10_P5.00mm_Horizontal
+terminal block RND 205-00020, 10 pins, pitch 5mm, size 50x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00020 pitch 5mm size 50x7.6mm^2 drill 1.3mm pad 2.5mm
+0
+10
+10
+TerminalBlock_RND
+TerminalBlock_RND_205-00021_1x11_P5.00mm_Horizontal
+terminal block RND 205-00021, 11 pins, pitch 5mm, size 55x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00021 pitch 5mm size 55x7.6mm^2 drill 1.3mm pad 2.5mm
+0
+11
+11
+TerminalBlock_RND
+TerminalBlock_RND_205-00022_1x12_P5.00mm_Horizontal
+terminal block RND 205-00022, 12 pins, pitch 5mm, size 60x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00022 pitch 5mm size 60x7.6mm^2 drill 1.3mm pad 2.5mm
+0
+12
+12
+TerminalBlock_RND
+TerminalBlock_RND_205-00023_1x02_P10.00mm_Horizontal
+terminal block RND 205-00023, 2 pins, pitch 10mm, size 15x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00023 pitch 10mm size 15x9mm^2 drill 1.3mm pad 2.5mm
+0
+2
+2
+TerminalBlock_RND
+TerminalBlock_RND_205-00024_1x03_P10.00mm_Horizontal
+terminal block RND 205-00024, 3 pins, pitch 10mm, size 25x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00024 pitch 10mm size 25x9mm^2 drill 1.3mm pad 2.5mm
+0
+3
+3
+TerminalBlock_RND
+TerminalBlock_RND_205-00025_1x04_P10.00mm_Horizontal
+terminal block RND 205-00025, 4 pins, pitch 10mm, size 35x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00025 pitch 10mm size 35x9mm^2 drill 1.3mm pad 2.5mm
+0
+4
+4
+TerminalBlock_RND
+TerminalBlock_RND_205-00026_1x05_P10.00mm_Horizontal
+terminal block RND 205-00026, 5 pins, pitch 10mm, size 45x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00026 pitch 10mm size 45x9mm^2 drill 1.3mm pad 2.5mm
+0
+5
+5
+TerminalBlock_RND
+TerminalBlock_RND_205-00027_1x06_P10.00mm_Horizontal
+terminal block RND 205-00027, 6 pins, pitch 10mm, size 55x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00027 pitch 10mm size 55x9mm^2 drill 1.3mm pad 2.5mm
+0
+6
+6
+TerminalBlock_RND
+TerminalBlock_RND_205-00028_1x07_P10.00mm_Horizontal
+terminal block RND 205-00028, 7 pins, pitch 10mm, size 65x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00028 pitch 10mm size 65x9mm^2 drill 1.3mm pad 2.5mm
+0
+7
+7
+TerminalBlock_RND
+TerminalBlock_RND_205-00029_1x08_P10.00mm_Horizontal
+terminal block RND 205-00029, 8 pins, pitch 10mm, size 75x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00029 pitch 10mm size 75x9mm^2 drill 1.3mm pad 2.5mm
+0
+8
+8
+TerminalBlock_RND
+TerminalBlock_RND_205-00030_1x09_P10.00mm_Horizontal
+terminal block RND 205-00030, 9 pins, pitch 10mm, size 85x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00030 pitch 10mm size 85x9mm^2 drill 1.3mm pad 2.5mm
+0
+9
+9
+TerminalBlock_RND
+TerminalBlock_RND_205-00031_1x10_P10.00mm_Horizontal
+terminal block RND 205-00031, 10 pins, pitch 10mm, size 95x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00031 pitch 10mm size 95x9mm^2 drill 1.3mm pad 2.5mm
+0
+10
+10
+TerminalBlock_RND
+TerminalBlock_RND_205-00032_1x11_P10.00mm_Horizontal
+terminal block RND 205-00032, 11 pins, pitch 10mm, size 105x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00032 pitch 10mm size 105x9mm^2 drill 1.3mm pad 2.5mm
+0
+11
+11
+TerminalBlock_RND
+TerminalBlock_RND_205-00033_1x12_P10.00mm_Horizontal
+terminal block RND 205-00033, 12 pins, pitch 10mm, size 115x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00033 pitch 10mm size 115x9mm^2 drill 1.3mm pad 2.5mm
+0
+12
+12
+TerminalBlock_RND
+TerminalBlock_RND_205-00045_1x02_P5.00mm_Horizontal
+terminal block RND 205-00045, 2 pins, pitch 5mm, size 10x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00045 pitch 5mm size 10x8.1mm^2 drill 1.1mm pad 2.1mm
+0
+2
+2
+TerminalBlock_RND
+TerminalBlock_RND_205-00046_1x03_P5.00mm_Horizontal
+terminal block RND 205-00046, 3 pins, pitch 5mm, size 15x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00046 pitch 5mm size 15x8.1mm^2 drill 1.1mm pad 2.1mm
+0
+3
+3
+TerminalBlock_RND
+TerminalBlock_RND_205-00047_1x04_P5.00mm_Horizontal
+terminal block RND 205-00047, 4 pins, pitch 5mm, size 20x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00047 pitch 5mm size 20x8.1mm^2 drill 1.1mm pad 2.1mm
+0
+4
+4
+TerminalBlock_RND
+TerminalBlock_RND_205-00048_1x05_P5.00mm_Horizontal
+terminal block RND 205-00048, 5 pins, pitch 5mm, size 25x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00048 pitch 5mm size 25x8.1mm^2 drill 1.1mm pad 2.1mm
+0
+5
+5
+TerminalBlock_RND
+TerminalBlock_RND_205-00049_1x06_P5.00mm_Horizontal
+terminal block RND 205-00049, 6 pins, pitch 5mm, size 30x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00049 pitch 5mm size 30x8.1mm^2 drill 1.1mm pad 2.1mm
+0
+6
+6
+TerminalBlock_RND
+TerminalBlock_RND_205-00050_1x07_P5.00mm_Horizontal
+terminal block RND 205-00050, 7 pins, pitch 5mm, size 35x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00050 pitch 5mm size 35x8.1mm^2 drill 1.1mm pad 2.1mm
+0
+7
+7
+TerminalBlock_RND
+TerminalBlock_RND_205-00051_1x08_P5.00mm_Horizontal
+terminal block RND 205-00051, 8 pins, pitch 5mm, size 40x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00051 pitch 5mm size 40x8.1mm^2 drill 1.1mm pad 2.1mm
+0
+8
+8
+TerminalBlock_RND
+TerminalBlock_RND_205-00052_1x09_P5.00mm_Horizontal
+terminal block RND 205-00052, 9 pins, pitch 5mm, size 45x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00052 pitch 5mm size 45x8.1mm^2 drill 1.1mm pad 2.1mm
+0
+9
+9
+TerminalBlock_RND
+TerminalBlock_RND_205-00053_1x10_P5.00mm_Horizontal
+terminal block RND 205-00053, 10 pins, pitch 5mm, size 50x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00053 pitch 5mm size 50x8.1mm^2 drill 1.1mm pad 2.1mm
+0
+10
+10
+TerminalBlock_RND
+TerminalBlock_RND_205-00054_1x11_P5.00mm_Horizontal
+terminal block RND 205-00054, 11 pins, pitch 5mm, size 55x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00054 pitch 5mm size 55x8.1mm^2 drill 1.1mm pad 2.1mm
+0
+11
+11
+TerminalBlock_RND
+TerminalBlock_RND_205-00055_1x12_P5.00mm_Horizontal
+terminal block RND 205-00055, 12 pins, pitch 5mm, size 60x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00055 pitch 5mm size 60x8.1mm^2 drill 1.1mm pad 2.1mm
+0
+12
+12
+TerminalBlock_RND
+TerminalBlock_RND_205-00056_1x02_P5.00mm_45Degree
+terminal block RND 205-00056, 45Degree (cable under 45degree), 2 pins, pitch 5mm, size 10x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00056 45Degree pitch 5mm size 10x12.6mm^2 drill 1.3mm pad 2.5mm
+0
+2
+2
+TerminalBlock_RND
+TerminalBlock_RND_205-00057_1x03_P5.00mm_45Degree
+terminal block RND 205-00057, 45Degree (cable under 45degree), 3 pins, pitch 5mm, size 15x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00057 45Degree pitch 5mm size 15x12.6mm^2 drill 1.3mm pad 2.5mm
+0
+3
+3
+TerminalBlock_RND
+TerminalBlock_RND_205-00058_1x04_P5.00mm_45Degree
+terminal block RND 205-00058, 45Degree (cable under 45degree), 4 pins, pitch 5mm, size 20x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00058 45Degree pitch 5mm size 20x12.6mm^2 drill 1.3mm pad 2.5mm
+0
+4
+4
+TerminalBlock_RND
+TerminalBlock_RND_205-00059_1x05_P5.00mm_45Degree
+terminal block RND 205-00059, 45Degree (cable under 45degree), 5 pins, pitch 5mm, size 25x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00059 45Degree pitch 5mm size 25x12.6mm^2 drill 1.3mm pad 2.5mm
+0
+5
+5
+TerminalBlock_RND
+TerminalBlock_RND_205-00060_1x06_P5.00mm_45Degree
+terminal block RND 205-00060, 45Degree (cable under 45degree), 6 pins, pitch 5mm, size 30x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00060 45Degree pitch 5mm size 30x12.6mm^2 drill 1.3mm pad 2.5mm
+0
+6
+6
+TerminalBlock_RND
+TerminalBlock_RND_205-00061_1x07_P5.00mm_45Degree
+terminal block RND 205-00061, 45Degree (cable under 45degree), 7 pins, pitch 5mm, size 35x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00061 45Degree pitch 5mm size 35x12.6mm^2 drill 1.3mm pad 2.5mm
+0
+7
+7
+TerminalBlock_RND
+TerminalBlock_RND_205-00062_1x08_P5.00mm_45Degree
+terminal block RND 205-00062, 45Degree (cable under 45degree), 8 pins, pitch 5mm, size 40x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00062 45Degree pitch 5mm size 40x12.6mm^2 drill 1.3mm pad 2.5mm
+0
+8
+8
+TerminalBlock_RND
+TerminalBlock_RND_205-00063_1x09_P5.00mm_45Degree
+terminal block RND 205-00063, 45Degree (cable under 45degree), 9 pins, pitch 5mm, size 45x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00063 45Degree pitch 5mm size 45x12.6mm^2 drill 1.3mm pad 2.5mm
+0
+9
+9
+TerminalBlock_RND
+TerminalBlock_RND_205-00064_1x10_P5.00mm_45Degree
+terminal block RND 205-00064, 45Degree (cable under 45degree), 10 pins, pitch 5mm, size 50x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00064 45Degree pitch 5mm size 50x12.6mm^2 drill 1.3mm pad 2.5mm
+0
+10
+10
+TerminalBlock_RND
+TerminalBlock_RND_205-00065_1x11_P5.00mm_45Degree
+terminal block RND 205-00065, 45Degree (cable under 45degree), 11 pins, pitch 5mm, size 55x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00065 45Degree pitch 5mm size 55x12.6mm^2 drill 1.3mm pad 2.5mm
+0
+11
+11
+TerminalBlock_RND
+TerminalBlock_RND_205-00066_1x12_P5.00mm_45Degree
+terminal block RND 205-00066, 45Degree (cable under 45degree), 12 pins, pitch 5mm, size 60x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00066 45Degree pitch 5mm size 60x12.6mm^2 drill 1.3mm pad 2.5mm
+0
+12
+12
+TerminalBlock_RND
+TerminalBlock_RND_205-00067_1x02_P7.50mm_Horizontal
+terminal block RND 205-00067, 2 pins, pitch 7.5mm, size 15x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00067 pitch 7.5mm size 15x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+2
+2
+TerminalBlock_RND
+TerminalBlock_RND_205-00068_1x03_P7.50mm_Horizontal
+terminal block RND 205-00068, 3 pins, pitch 7.5mm, size 22.5x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00068 pitch 7.5mm size 22.5x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+3
+3
+TerminalBlock_RND
+TerminalBlock_RND_205-00069_1x04_P7.50mm_Horizontal
+terminal block RND 205-00069, 4 pins, pitch 7.5mm, size 30x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00069 pitch 7.5mm size 30x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+4
+4
+TerminalBlock_RND
+TerminalBlock_RND_205-00070_1x05_P7.50mm_Horizontal
+terminal block RND 205-00070, 5 pins, pitch 7.5mm, size 37.5x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00070 pitch 7.5mm size 37.5x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+5
+5
+TerminalBlock_RND
+TerminalBlock_RND_205-00071_1x06_P7.50mm_Horizontal
+terminal block RND 205-00071, 6 pins, pitch 7.5mm, size 45x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00071 pitch 7.5mm size 45x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+6
+6
+TerminalBlock_RND
+TerminalBlock_RND_205-00072_1x07_P7.50mm_Horizontal
+terminal block RND 205-00072, 7 pins, pitch 7.5mm, size 52.5x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00072 pitch 7.5mm size 52.5x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+7
+7
+TerminalBlock_RND
+TerminalBlock_RND_205-00073_1x08_P7.50mm_Horizontal
+terminal block RND 205-00073, 8 pins, pitch 7.5mm, size 60x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00073 pitch 7.5mm size 60x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+8
+8
+TerminalBlock_RND
+TerminalBlock_RND_205-00074_1x09_P7.50mm_Horizontal
+terminal block RND 205-00074, 9 pins, pitch 7.5mm, size 67.5x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00074 pitch 7.5mm size 67.5x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+9
+9
+TerminalBlock_RND
+TerminalBlock_RND_205-00075_1x10_P7.50mm_Horizontal
+terminal block RND 205-00075, 10 pins, pitch 7.5mm, size 75x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00075 pitch 7.5mm size 75x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+10
+10
+TerminalBlock_RND
+TerminalBlock_RND_205-00076_1x11_P7.50mm_Horizontal
+terminal block RND 205-00076, 11 pins, pitch 7.5mm, size 82.5x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00076 pitch 7.5mm size 82.5x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+11
+11
+TerminalBlock_RND
+TerminalBlock_RND_205-00077_1x12_P7.50mm_Horizontal
+terminal block RND 205-00077, 12 pins, pitch 7.5mm, size 90x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00077 pitch 7.5mm size 90x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+12
+12
+TerminalBlock_RND
+TerminalBlock_RND_205-00078_1x02_P10.00mm_Horizontal
+terminal block RND 205-00078, 2 pins, pitch 10mm, size 15x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00078 pitch 10mm size 15x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+2
+2
+TerminalBlock_RND
+TerminalBlock_RND_205-00079_1x03_P10.00mm_Horizontal
+terminal block RND 205-00079, 3 pins, pitch 10mm, size 25x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00079 pitch 10mm size 25x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+3
+3
+TerminalBlock_RND
+TerminalBlock_RND_205-00080_1x04_P10.00mm_Horizontal
+terminal block RND 205-00080, 4 pins, pitch 10mm, size 35x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00080 pitch 10mm size 35x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+4
+4
+TerminalBlock_RND
+TerminalBlock_RND_205-00081_1x05_P10.00mm_Horizontal
+terminal block RND 205-00081, 5 pins, pitch 10mm, size 45x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00081 pitch 10mm size 45x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+5
+5
+TerminalBlock_RND
+TerminalBlock_RND_205-00082_1x06_P10.00mm_Horizontal
+terminal block RND 205-00082, 6 pins, pitch 10mm, size 55x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00082 pitch 10mm size 55x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+6
+6
+TerminalBlock_RND
+TerminalBlock_RND_205-00083_1x07_P10.00mm_Horizontal
+terminal block RND 205-00083, 7 pins, pitch 10mm, size 65x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00083 pitch 10mm size 65x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+7
+7
+TerminalBlock_RND
+TerminalBlock_RND_205-00084_1x08_P10.00mm_Horizontal
+terminal block RND 205-00084, 8 pins, pitch 10mm, size 75x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00084 pitch 10mm size 75x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+8
+8
+TerminalBlock_RND
+TerminalBlock_RND_205-00085_1x09_P10.00mm_Horizontal
+terminal block RND 205-00085, 9 pins, pitch 10mm, size 85x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00085 pitch 10mm size 85x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+9
+9
+TerminalBlock_RND
+TerminalBlock_RND_205-00086_1x10_P10.00mm_Horizontal
+terminal block RND 205-00086, 10 pins, pitch 10mm, size 95x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00086 pitch 10mm size 95x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+10
+10
+TerminalBlock_RND
+TerminalBlock_RND_205-00087_1x11_P10.00mm_Horizontal
+terminal block RND 205-00087, 11 pins, pitch 10mm, size 105x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00087 pitch 10mm size 105x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+11
+11
+TerminalBlock_RND
+TerminalBlock_RND_205-00088_1x12_P10.00mm_Horizontal
+terminal block RND 205-00088, 12 pins, pitch 10mm, size 115x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00088 pitch 10mm size 115x10.3mm^2 drill 1.3mm pad 2.5mm
+0
+12
+12
+TerminalBlock_RND
+TerminalBlock_RND_205-00232_1x02_P5.08mm_Horizontal
+terminal block RND 205-00232, 2 pins, pitch 5.08mm, size 10.2x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00232 pitch 5.08mm size 10.2x8.45mm^2 drill 1.1mm pad 2.1mm
+0
+2
+2
+TerminalBlock_RND
+TerminalBlock_RND_205-00233_1x03_P5.08mm_Horizontal
+terminal block RND 205-00233, 3 pins, pitch 5.08mm, size 15.2x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00233 pitch 5.08mm size 15.2x8.45mm^2 drill 1.1mm pad 2.1mm
+0
+3
+3
+TerminalBlock_RND
+TerminalBlock_RND_205-00234_1x04_P5.08mm_Horizontal
+terminal block RND 205-00234, 4 pins, pitch 5.08mm, size 20.3x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00234 pitch 5.08mm size 20.3x8.45mm^2 drill 1.1mm pad 2.1mm
+0
+4
+4
+TerminalBlock_RND
+TerminalBlock_RND_205-00235_1x05_P5.08mm_Horizontal
+terminal block RND 205-00235, 5 pins, pitch 5.08mm, size 25.4x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00235 pitch 5.08mm size 25.4x8.45mm^2 drill 1.1mm pad 2.1mm
+0
+5
+5
+TerminalBlock_RND
+TerminalBlock_RND_205-00236_1x06_P5.08mm_Horizontal
+terminal block RND 205-00236, 6 pins, pitch 5.08mm, size 30.5x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00236 pitch 5.08mm size 30.5x8.45mm^2 drill 1.1mm pad 2.1mm
+0
+6
+6
+TerminalBlock_RND
+TerminalBlock_RND_205-00237_1x07_P5.08mm_Horizontal
+terminal block RND 205-00237, 7 pins, pitch 5.08mm, size 35.6x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00237 pitch 5.08mm size 35.6x8.45mm^2 drill 1.1mm pad 2.1mm
+0
+7
+7
+TerminalBlock_RND
+TerminalBlock_RND_205-00238_1x08_P5.08mm_Horizontal
+terminal block RND 205-00238, 8 pins, pitch 5.08mm, size 40.6x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00238 pitch 5.08mm size 40.6x8.45mm^2 drill 1.1mm pad 2.1mm
+0
+8
+8
+TerminalBlock_RND
+TerminalBlock_RND_205-00239_1x09_P5.08mm_Horizontal
+terminal block RND 205-00239, 9 pins, pitch 5.08mm, size 45.7x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00239 pitch 5.08mm size 45.7x8.45mm^2 drill 1.1mm pad 2.1mm
+0
+9
+9
+TerminalBlock_RND
+TerminalBlock_RND_205-00240_1x10_P5.08mm_Horizontal
+terminal block RND 205-00240, 10 pins, pitch 5.08mm, size 50.8x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00240 pitch 5.08mm size 50.8x8.45mm^2 drill 1.1mm pad 2.1mm
+0
+10
+10
+TerminalBlock_RND
+TerminalBlock_RND_205-00241_1x02_P10.16mm_Horizontal
+terminal block RND 205-00241, 2 pins, pitch 10.2mm, size 15.2x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00241 pitch 10.2mm size 15.2x8.3mm^2 drill 1.3mm pad 2.5mm
+0
+2
+2
+TerminalBlock_RND
+TerminalBlock_RND_205-00242_1x03_P10.16mm_Horizontal
+terminal block RND 205-00242, 3 pins, pitch 10.2mm, size 25.4x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00242 pitch 10.2mm size 25.4x8.3mm^2 drill 1.3mm pad 2.5mm
+0
+3
+3
+TerminalBlock_RND
+TerminalBlock_RND_205-00243_1x04_P10.16mm_Horizontal
+terminal block RND 205-00243, 4 pins, pitch 10.2mm, size 35.6x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00243 pitch 10.2mm size 35.6x8.3mm^2 drill 1.3mm pad 2.5mm
+0
+4
+4
+TerminalBlock_RND
+TerminalBlock_RND_205-00244_1x05_P10.16mm_Horizontal
+terminal block RND 205-00244, 5 pins, pitch 10.2mm, size 45.7x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00244 pitch 10.2mm size 45.7x8.3mm^2 drill 1.3mm pad 2.5mm
+0
+5
+5
+TerminalBlock_RND
+TerminalBlock_RND_205-00245_1x06_P10.16mm_Horizontal
+terminal block RND 205-00245, 6 pins, pitch 10.2mm, size 55.9x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00245 pitch 10.2mm size 55.9x8.3mm^2 drill 1.3mm pad 2.5mm
+0
+6
+6
+TerminalBlock_RND
+TerminalBlock_RND_205-00246_1x07_P10.16mm_Horizontal
+terminal block RND 205-00246, 7 pins, pitch 10.2mm, size 66x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00246 pitch 10.2mm size 66x8.3mm^2 drill 1.3mm pad 2.5mm
+0
+7
+7
+TerminalBlock_RND
+TerminalBlock_RND_205-00247_1x08_P10.16mm_Horizontal
+terminal block RND 205-00247, 8 pins, pitch 10.2mm, size 76.2x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00247 pitch 10.2mm size 76.2x8.3mm^2 drill 1.3mm pad 2.5mm
+0
+8
+8
+TerminalBlock_RND
+TerminalBlock_RND_205-00248_1x09_P10.16mm_Horizontal
+terminal block RND 205-00248, 9 pins, pitch 10.2mm, size 86.4x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00248 pitch 10.2mm size 86.4x8.3mm^2 drill 1.3mm pad 2.5mm
+0
+9
+9
+TerminalBlock_RND
+TerminalBlock_RND_205-00249_1x10_P10.16mm_Horizontal
+terminal block RND 205-00249, 10 pins, pitch 10.2mm, size 96.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00249 pitch 10.2mm size 96.5x8.3mm^2 drill 1.3mm pad 2.5mm
+0
+10
+10
+TerminalBlock_RND
+TerminalBlock_RND_205-00250_1x11_P10.16mm_Horizontal
+terminal block RND 205-00250, 11 pins, pitch 10.2mm, size 107x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00250 pitch 10.2mm size 107x8.3mm^2 drill 1.3mm pad 2.5mm
+0
+11
+11
+TerminalBlock_RND
+TerminalBlock_RND_205-00251_1x12_P10.16mm_Horizontal
+terminal block RND 205-00251, 12 pins, pitch 10.2mm, size 117x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00251 pitch 10.2mm size 117x8.3mm^2 drill 1.3mm pad 2.5mm
+0
+12
+12
+TerminalBlock_RND
+TerminalBlock_RND_205-00276_1x02_P5.00mm_Vertical
+terminal block RND 205-00078, vertical (cable from top), 2 pins, pitch 5mm, size 10x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00078 vertical pitch 5mm size 10x10mm^2 drill 1.3mm pad 2.5mm
+0
+2
+2
+TerminalBlock_RND
+TerminalBlock_RND_205-00277_1x03_P5.00mm_Vertical
+terminal block RND 205-00079, vertical (cable from top), 3 pins, pitch 5mm, size 15x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00079 vertical pitch 5mm size 15x10mm^2 drill 1.3mm pad 2.5mm
+0
+3
+3
+TerminalBlock_RND
+TerminalBlock_RND_205-00278_1x04_P5.00mm_Vertical
+terminal block RND 205-00080, vertical (cable from top), 4 pins, pitch 5mm, size 20x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00080 vertical pitch 5mm size 20x10mm^2 drill 1.3mm pad 2.5mm
+0
+4
+4
+TerminalBlock_RND
+TerminalBlock_RND_205-00279_1x05_P5.00mm_Vertical
+terminal block RND 205-00081, vertical (cable from top), 5 pins, pitch 5mm, size 25x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00081 vertical pitch 5mm size 25x10mm^2 drill 1.3mm pad 2.5mm
+0
+5
+5
+TerminalBlock_RND
+TerminalBlock_RND_205-00280_1x06_P5.00mm_Vertical
+terminal block RND 205-00082, vertical (cable from top), 6 pins, pitch 5mm, size 30x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00082 vertical pitch 5mm size 30x10mm^2 drill 1.3mm pad 2.5mm
+0
+6
+6
+TerminalBlock_RND
+TerminalBlock_RND_205-00281_1x07_P5.00mm_Vertical
+terminal block RND 205-00083, vertical (cable from top), 7 pins, pitch 5mm, size 35x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00083 vertical pitch 5mm size 35x10mm^2 drill 1.3mm pad 2.5mm
+0
+7
+7
+TerminalBlock_RND
+TerminalBlock_RND_205-00282_1x08_P5.00mm_Vertical
+terminal block RND 205-00084, vertical (cable from top), 8 pins, pitch 5mm, size 40x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00084 vertical pitch 5mm size 40x10mm^2 drill 1.3mm pad 2.5mm
+0
+8
+8
+TerminalBlock_RND
+TerminalBlock_RND_205-00283_1x09_P5.00mm_Vertical
+terminal block RND 205-00085, vertical (cable from top), 9 pins, pitch 5mm, size 45x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00085 vertical pitch 5mm size 45x10mm^2 drill 1.3mm pad 2.5mm
+0
+9
+9
+TerminalBlock_RND
+TerminalBlock_RND_205-00284_1x10_P5.00mm_Vertical
+terminal block RND 205-00086, vertical (cable from top), 10 pins, pitch 5mm, size 50x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00086 vertical pitch 5mm size 50x10mm^2 drill 1.3mm pad 2.5mm
+0
+10
+10
+TerminalBlock_RND
+TerminalBlock_RND_205-00285_1x11_P5.00mm_Vertical
+terminal block RND 205-00087, vertical (cable from top), 11 pins, pitch 5mm, size 55x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00087 vertical pitch 5mm size 55x10mm^2 drill 1.3mm pad 2.5mm
+0
+11
+11
+TerminalBlock_RND
+TerminalBlock_RND_205-00286_1x12_P5.00mm_Vertical
+terminal block RND 205-00088, vertical (cable from top), 12 pins, pitch 5mm, size 60x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00088 vertical pitch 5mm size 60x10mm^2 drill 1.3mm pad 2.5mm
+0
+12
+12
+TerminalBlock_RND
+TerminalBlock_RND_205-00287_1x02_P5.08mm_Horizontal
+terminal block RND 205-00287, 2 pins, pitch 5.08mm, size 10.2x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00287 pitch 5.08mm size 10.2x10.6mm^2 drill 1.3mm pad 2.5mm
+0
+2
+2
+TerminalBlock_RND
+TerminalBlock_RND_205-00288_1x03_P5.08mm_Horizontal
+terminal block RND 205-00288, 3 pins, pitch 5.08mm, size 15.2x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00288 pitch 5.08mm size 15.2x10.6mm^2 drill 1.3mm pad 2.5mm
+0
+3
+3
+TerminalBlock_RND
+TerminalBlock_RND_205-00289_1x04_P5.08mm_Horizontal
+terminal block RND 205-00289, 4 pins, pitch 5.08mm, size 20.3x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00289 pitch 5.08mm size 20.3x10.6mm^2 drill 1.3mm pad 2.5mm
+0
+4
+4
+TerminalBlock_RND
+TerminalBlock_RND_205-00290_1x05_P5.08mm_Horizontal
+terminal block RND 205-00290, 5 pins, pitch 5.08mm, size 25.4x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00290 pitch 5.08mm size 25.4x10.6mm^2 drill 1.3mm pad 2.5mm
+0
+5
+5
+TerminalBlock_RND
+TerminalBlock_RND_205-00291_1x06_P5.08mm_Horizontal
+terminal block RND 205-00291, 6 pins, pitch 5.08mm, size 30.5x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00291 pitch 5.08mm size 30.5x10.6mm^2 drill 1.3mm pad 2.5mm
+0
+6
+6
+TerminalBlock_RND
+TerminalBlock_RND_205-00292_1x07_P5.08mm_Horizontal
+terminal block RND 205-00292, 7 pins, pitch 5.08mm, size 35.6x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00292 pitch 5.08mm size 35.6x10.6mm^2 drill 1.3mm pad 2.5mm
+0
+7
+7
+TerminalBlock_RND
+TerminalBlock_RND_205-00293_1x08_P5.08mm_Horizontal
+terminal block RND 205-00293, 8 pins, pitch 5.08mm, size 40.6x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00293 pitch 5.08mm size 40.6x10.6mm^2 drill 1.3mm pad 2.5mm
+0
+8
+8
+TerminalBlock_RND
+TerminalBlock_RND_205-00294_1x09_P5.08mm_Horizontal
+terminal block RND 205-00294, 9 pins, pitch 5.08mm, size 45.7x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00294 pitch 5.08mm size 45.7x10.6mm^2 drill 1.3mm pad 2.5mm
+0
+9
+9
+TerminalBlock_RND
+TerminalBlock_RND_205-00295_1x10_P5.08mm_Horizontal
+terminal block RND 205-00295, 10 pins, pitch 5.08mm, size 50.8x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00295 pitch 5.08mm size 50.8x10.6mm^2 drill 1.3mm pad 2.5mm
+0
+10
+10
+TerminalBlock_RND
+TerminalBlock_RND_205-00296_1x11_P5.08mm_Horizontal
+terminal block RND 205-00296, 11 pins, pitch 5.08mm, size 55.9x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00296 pitch 5.08mm size 55.9x10.6mm^2 drill 1.3mm pad 2.5mm
+0
+11
+11
+TerminalBlock_RND
+TerminalBlock_RND_205-00297_1x12_P5.08mm_Horizontal
+terminal block RND 205-00297, 12 pins, pitch 5.08mm, size 61x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00297 pitch 5.08mm size 61x10.6mm^2 drill 1.3mm pad 2.5mm
+0
+12
+12
+TerminalBlock_RND
+TerminalBlock_RND_205-00298_1x02_P10.00mm_Horizontal
+terminal block RND 205-00298, 2 pins, pitch 10mm, size 15x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00298 pitch 10mm size 15x8.1mm^2 drill 1.3mm pad 2.5mm
+0
+2
+2
+TerminalBlock_RND
+TerminalBlock_RND_205-00299_1x03_P10.00mm_Horizontal
+terminal block RND 205-00299, 3 pins, pitch 10mm, size 25x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00299 pitch 10mm size 25x8.1mm^2 drill 1.3mm pad 2.5mm
+0
+3
+3
+TerminalBlock_RND
+TerminalBlock_RND_205-00300_1x04_P10.00mm_Horizontal
+terminal block RND 205-00300, 4 pins, pitch 10mm, size 35x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00300 pitch 10mm size 35x8.1mm^2 drill 1.3mm pad 2.5mm
+0
+4
+4
+TerminalBlock_RND
+TerminalBlock_RND_205-00301_1x05_P10.00mm_Horizontal
+terminal block RND 205-00301, 5 pins, pitch 10mm, size 45x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00301 pitch 10mm size 45x8.1mm^2 drill 1.3mm pad 2.5mm
+0
+5
+5
+TerminalBlock_RND
+TerminalBlock_RND_205-00302_1x06_P10.00mm_Horizontal
+terminal block RND 205-00302, 6 pins, pitch 10mm, size 55x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00302 pitch 10mm size 55x8.1mm^2 drill 1.3mm pad 2.5mm
+0
+6
+6
+TerminalBlock_RND
+TerminalBlock_RND_205-00303_1x07_P10.00mm_Horizontal
+terminal block RND 205-00303, 7 pins, pitch 10mm, size 65x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00303 pitch 10mm size 65x8.1mm^2 drill 1.3mm pad 2.5mm
+0
+7
+7
+TerminalBlock_RND
+TerminalBlock_RND_205-00304_1x08_P10.00mm_Horizontal
+terminal block RND 205-00304, 8 pins, pitch 10mm, size 75x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00304 pitch 10mm size 75x8.1mm^2 drill 1.3mm pad 2.5mm
+0
+8
+8
+TerminalBlock_RND
+TerminalBlock_RND_205-00305_1x09_P10.00mm_Horizontal
+terminal block RND 205-00305, 9 pins, pitch 10mm, size 85x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00305 pitch 10mm size 85x8.1mm^2 drill 1.3mm pad 2.5mm
+0
+9
+9
+TerminalBlock_RND
+TerminalBlock_RND_205-00306_1x10_P10.00mm_Horizontal
+terminal block RND 205-00306, 10 pins, pitch 10mm, size 95x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00306 pitch 10mm size 95x8.1mm^2 drill 1.3mm pad 2.5mm
+0
+10
+10
+TerminalBlock_RND
+TerminalBlock_RND_205-00307_1x11_P10.00mm_Horizontal
+terminal block RND 205-00307, 11 pins, pitch 10mm, size 105x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00307 pitch 10mm size 105x8.1mm^2 drill 1.3mm pad 2.5mm
+0
+11
+11
+TerminalBlock_RND
+TerminalBlock_RND_205-00308_1x12_P10.00mm_Horizontal
+terminal block RND 205-00308, 12 pins, pitch 10mm, size 115x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND
+THT terminal block RND 205-00308 pitch 10mm size 115x8.1mm^2 drill 1.3mm pad 2.5mm
+0
+12
+12
+TerminalBlock_TE-Connectivity
+TerminalBlock_TE_1-282834-0_1x10_P2.54mm_Horizontal
+Terminal Block TE 1-282834-0, 10 pins, pitch 2.54mm, size 25.86x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity
+THT Terminal Block TE 1-282834-0 pitch 2.54mm size 25.86x6.5mm^2 drill 1.1mm pad 2.1mm
+0
+10
+10
+TerminalBlock_TE-Connectivity
+TerminalBlock_TE_1-282834-1_1x11_P2.54mm_Horizontal
+Terminal Block TE 1-282834-1, 11 pins, pitch 2.54mm, size 28.4x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity
+THT Terminal Block TE 1-282834-1 pitch 2.54mm size 28.4x6.5mm^2 drill 1.1mm pad 2.1mm
+0
+11
+11
+TerminalBlock_TE-Connectivity
+TerminalBlock_TE_1-282834-2_1x12_P2.54mm_Horizontal
+Terminal Block TE 1-282834-2, 12 pins, pitch 2.54mm, size 30.94x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity
+THT Terminal Block TE 1-282834-2 pitch 2.54mm size 30.94x6.5mm^2 drill 1.1mm pad 2.1mm
+0
+12
+12
+TerminalBlock_TE-Connectivity
+TerminalBlock_TE_282834-2_1x02_P2.54mm_Horizontal
+Terminal Block TE 282834-2, 2 pins, pitch 2.54mm, size 5.54x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity
+THT Terminal Block TE 282834-2 pitch 2.54mm size 5.54x6.5mm^2 drill 1.1mm pad 2.1mm
+0
+2
+2
+TerminalBlock_TE-Connectivity
+TerminalBlock_TE_282834-3_1x03_P2.54mm_Horizontal
+Terminal Block TE 282834-3, 3 pins, pitch 2.54mm, size 8.08x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity
+THT Terminal Block TE 282834-3 pitch 2.54mm size 8.08x6.5mm^2 drill 1.1mm pad 2.1mm
+0
+3
+3
+TerminalBlock_TE-Connectivity
+TerminalBlock_TE_282834-4_1x04_P2.54mm_Horizontal
+Terminal Block TE 282834-4, 4 pins, pitch 2.54mm, size 10.620000000000001x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity
+THT Terminal Block TE 282834-4 pitch 2.54mm size 10.620000000000001x6.5mm^2 drill 1.1mm pad 2.1mm
+0
+4
+4
+TerminalBlock_TE-Connectivity
+TerminalBlock_TE_282834-5_1x05_P2.54mm_Horizontal
+Terminal Block TE 282834-5, 5 pins, pitch 2.54mm, size 13.16x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity
+THT Terminal Block TE 282834-5 pitch 2.54mm size 13.16x6.5mm^2 drill 1.1mm pad 2.1mm
+0
+5
+5
+TerminalBlock_TE-Connectivity
+TerminalBlock_TE_282834-6_1x06_P2.54mm_Horizontal
+Terminal Block TE 282834-6, 6 pins, pitch 2.54mm, size 15.7x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity
+THT Terminal Block TE 282834-6 pitch 2.54mm size 15.7x6.5mm^2 drill 1.1mm pad 2.1mm
+0
+6
+6
+TerminalBlock_TE-Connectivity
+TerminalBlock_TE_282834-7_1x07_P2.54mm_Horizontal
+Terminal Block TE 282834-7, 7 pins, pitch 2.54mm, size 18.240000000000002x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity
+THT Terminal Block TE 282834-7 pitch 2.54mm size 18.240000000000002x6.5mm^2 drill 1.1mm pad 2.1mm
+0
+7
+7
+TerminalBlock_TE-Connectivity
+TerminalBlock_TE_282834-8_1x08_P2.54mm_Horizontal
+Terminal Block TE 282834-8, 8 pins, pitch 2.54mm, size 20.78x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity
+THT Terminal Block TE 282834-8 pitch 2.54mm size 20.78x6.5mm^2 drill 1.1mm pad 2.1mm
+0
+8
+8
+TerminalBlock_TE-Connectivity
+TerminalBlock_TE_282834-9_1x09_P2.54mm_Horizontal
+Terminal Block TE 282834-9, 9 pins, pitch 2.54mm, size 23.32x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity
+THT Terminal Block TE 282834-9 pitch 2.54mm size 23.32x6.5mm^2 drill 1.1mm pad 2.1mm
+0
+9
+9
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-101_1x01_P5.00mm_45Degree
+Terminal Block WAGO 236-101, 45Degree (cable under 45degree), 1 pins, pitch 5mm, size 7.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-101 45Degree pitch 5mm size 7.3x14mm^2 drill 1.15mm pad 3mm
+0
+1
+1
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-102_1x02_P5.00mm_45Degree
+Terminal Block WAGO 236-102, 45Degree (cable under 45degree), 2 pins, pitch 5mm, size 12.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-102 45Degree pitch 5mm size 12.3x14mm^2 drill 1.15mm pad 3mm
+0
+2
+2
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-103_1x03_P5.00mm_45Degree
+Terminal Block WAGO 236-103, 45Degree (cable under 45degree), 3 pins, pitch 5mm, size 17.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-103 45Degree pitch 5mm size 17.3x14mm^2 drill 1.15mm pad 3mm
+0
+3
+3
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-104_1x04_P5.00mm_45Degree
+Terminal Block WAGO 236-104, 45Degree (cable under 45degree), 4 pins, pitch 5mm, size 22.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-104 45Degree pitch 5mm size 22.3x14mm^2 drill 1.15mm pad 3mm
+0
+4
+4
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-106_1x06_P5.00mm_45Degree
+Terminal Block WAGO 236-106, 45Degree (cable under 45degree), 6 pins, pitch 5mm, size 32.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-106 45Degree pitch 5mm size 32.3x14mm^2 drill 1.15mm pad 3mm
+0
+6
+6
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-108_1x08_P5.00mm_45Degree
+Terminal Block WAGO 236-108, 45Degree (cable under 45degree), 8 pins, pitch 5mm, size 42.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-108 45Degree pitch 5mm size 42.3x14mm^2 drill 1.15mm pad 3mm
+0
+8
+8
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-112_1x12_P5.00mm_45Degree
+Terminal Block WAGO 236-112, 45Degree (cable under 45degree), 12 pins, pitch 5mm, size 62.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-112 45Degree pitch 5mm size 62.3x14mm^2 drill 1.15mm pad 3mm
+0
+12
+12
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-116_1x16_P5.00mm_45Degree
+Terminal Block WAGO 236-116, 45Degree (cable under 45degree), 16 pins, pitch 5mm, size 82.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-116 45Degree pitch 5mm size 82.3x14mm^2 drill 1.15mm pad 3mm
+0
+16
+16
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-124_1x24_P5.00mm_45Degree
+Terminal Block WAGO 236-124, 45Degree (cable under 45degree), 24 pins, pitch 5mm, size 122x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-124 45Degree pitch 5mm size 122x14mm^2 drill 1.15mm pad 3mm
+0
+24
+24
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-136_1x36_P5.00mm_45Degree
+Terminal Block WAGO 236-136, 45Degree (cable under 45degree), 36 pins, pitch 5mm, size 182x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-136 45Degree pitch 5mm size 182x14mm^2 drill 1.15mm pad 3mm
+0
+36
+36
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-148_1x48_P5.00mm_45Degree
+Terminal Block WAGO 236-148, 45Degree (cable under 45degree), 48 pins, pitch 5mm, size 242x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-148 45Degree pitch 5mm size 242x14mm^2 drill 1.15mm pad 3mm
+0
+48
+48
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-201_1x01_P7.50mm_45Degree
+Terminal Block WAGO 236-201, 45Degree (cable under 45degree), 1 pins, pitch 7.5mm, size 9.8x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-201 45Degree pitch 7.5mm size 9.8x14mm^2 drill 1.15mm pad 3mm
+0
+1
+1
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-202_1x02_P7.50mm_45Degree
+Terminal Block WAGO 236-202, 45Degree (cable under 45degree), 2 pins, pitch 7.5mm, size 17.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-202 45Degree pitch 7.5mm size 17.3x14mm^2 drill 1.15mm pad 3mm
+0
+2
+2
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-203_1x03_P7.50mm_45Degree
+Terminal Block WAGO 236-203, 45Degree (cable under 45degree), 3 pins, pitch 7.5mm, size 24.8x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-203 45Degree pitch 7.5mm size 24.8x14mm^2 drill 1.15mm pad 3mm
+0
+3
+3
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-204_1x04_P7.50mm_45Degree
+Terminal Block WAGO 236-204, 45Degree (cable under 45degree), 4 pins, pitch 7.5mm, size 32.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-204 45Degree pitch 7.5mm size 32.3x14mm^2 drill 1.15mm pad 3mm
+0
+4
+4
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-206_1x06_P7.50mm_45Degree
+Terminal Block WAGO 236-206, 45Degree (cable under 45degree), 6 pins, pitch 7.5mm, size 47.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-206 45Degree pitch 7.5mm size 47.3x14mm^2 drill 1.15mm pad 3mm
+0
+6
+6
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-208_1x08_P7.50mm_45Degree
+Terminal Block WAGO 236-208, 45Degree (cable under 45degree), 8 pins, pitch 7.5mm, size 62.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-208 45Degree pitch 7.5mm size 62.3x14mm^2 drill 1.15mm pad 3mm
+0
+8
+8
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-212_1x12_P7.50mm_45Degree
+Terminal Block WAGO 236-212, 45Degree (cable under 45degree), 12 pins, pitch 7.5mm, size 92.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-212 45Degree pitch 7.5mm size 92.3x14mm^2 drill 1.15mm pad 3mm
+0
+12
+12
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-216_1x16_P7.50mm_45Degree
+Terminal Block WAGO 236-216, 45Degree (cable under 45degree), 16 pins, pitch 7.5mm, size 122x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-216 45Degree pitch 7.5mm size 122x14mm^2 drill 1.15mm pad 3mm
+0
+16
+16
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-224_1x24_P7.50mm_45Degree
+Terminal Block WAGO 236-224, 45Degree (cable under 45degree), 24 pins, pitch 7.5mm, size 182x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-224 45Degree pitch 7.5mm size 182x14mm^2 drill 1.15mm pad 3mm
+0
+24
+24
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-301_1x01_P10.00mm_45Degree
+Terminal Block WAGO 236-301, 45Degree (cable under 45degree), 1 pins, pitch 10mm, size 12.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-301 45Degree pitch 10mm size 12.3x14mm^2 drill 1.15mm pad 3mm
+0
+1
+1
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-302_1x02_P10.00mm_45Degree
+Terminal Block WAGO 236-302, 45Degree (cable under 45degree), 2 pins, pitch 10mm, size 22.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-302 45Degree pitch 10mm size 22.3x14mm^2 drill 1.15mm pad 3mm
+0
+2
+2
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-303_1x03_P10.00mm_45Degree
+Terminal Block WAGO 236-303, 45Degree (cable under 45degree), 3 pins, pitch 10mm, size 32.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-303 45Degree pitch 10mm size 32.3x14mm^2 drill 1.15mm pad 3mm
+0
+3
+3
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-304_1x04_P10.00mm_45Degree
+Terminal Block WAGO 236-304, 45Degree (cable under 45degree), 4 pins, pitch 10mm, size 42.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-304 45Degree pitch 10mm size 42.3x14mm^2 drill 1.15mm pad 3mm
+0
+4
+4
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-306_1x06_P10.00mm_45Degree
+Terminal Block WAGO 236-306, 45Degree (cable under 45degree), 6 pins, pitch 10mm, size 62.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-306 45Degree pitch 10mm size 62.3x14mm^2 drill 1.15mm pad 3mm
+0
+6
+6
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-308_1x08_P10.00mm_45Degree
+Terminal Block WAGO 236-308, 45Degree (cable under 45degree), 8 pins, pitch 10mm, size 82.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-308 45Degree pitch 10mm size 82.3x14mm^2 drill 1.15mm pad 3mm
+0
+8
+8
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-312_1x12_P10.00mm_45Degree
+Terminal Block WAGO 236-312, 45Degree (cable under 45degree), 12 pins, pitch 10mm, size 122x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-312 45Degree pitch 10mm size 122x14mm^2 drill 1.15mm pad 3mm
+0
+12
+12
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-316_1x16_P10.00mm_45Degree
+Terminal Block WAGO 236-316, 45Degree (cable under 45degree), 16 pins, pitch 10mm, size 162x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-316 45Degree pitch 10mm size 162x14mm^2 drill 1.15mm pad 3mm
+0
+16
+16
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-324_1x24_P10.00mm_45Degree
+Terminal Block WAGO 236-324, 45Degree (cable under 45degree), 24 pins, pitch 10mm, size 242x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-324 45Degree pitch 10mm size 242x14mm^2 drill 1.15mm pad 3mm
+0
+24
+24
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-401_1x01_P5.00mm_45Degree
+Terminal Block WAGO 236-401, 45Degree (cable under 45degree), 1 pins, pitch 5mm, size 7.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-401 45Degree pitch 5mm size 7.3x14mm^2 drill 1.15mm pad 3mm
+0
+2
+1
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-402_1x02_P5.00mm_45Degree
+Terminal Block WAGO 236-402, 45Degree (cable under 45degree), 2 pins, pitch 5mm, size 12.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-402 45Degree pitch 5mm size 12.3x14mm^2 drill 1.15mm pad 3mm
+0
+4
+2
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-403_1x03_P5.00mm_45Degree
+Terminal Block WAGO 236-403, 45Degree (cable under 45degree), 3 pins, pitch 5mm, size 17.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-403 45Degree pitch 5mm size 17.3x14mm^2 drill 1.15mm pad 3mm
+0
+6
+3
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-404_1x04_P5.00mm_45Degree
+Terminal Block WAGO 236-404, 45Degree (cable under 45degree), 4 pins, pitch 5mm, size 22.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-404 45Degree pitch 5mm size 22.3x14mm^2 drill 1.15mm pad 3mm
+0
+8
+4
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-406_1x06_P5.00mm_45Degree
+Terminal Block WAGO 236-406, 45Degree (cable under 45degree), 6 pins, pitch 5mm, size 32.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-406 45Degree pitch 5mm size 32.3x14mm^2 drill 1.15mm pad 3mm
+0
+12
+6
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-408_1x08_P5.00mm_45Degree
+Terminal Block WAGO 236-408, 45Degree (cable under 45degree), 8 pins, pitch 5mm, size 42.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-408 45Degree pitch 5mm size 42.3x14mm^2 drill 1.15mm pad 3mm
+0
+16
+8
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-412_1x12_P5.00mm_45Degree
+Terminal Block WAGO 236-412, 45Degree (cable under 45degree), 12 pins, pitch 5mm, size 62.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-412 45Degree pitch 5mm size 62.3x14mm^2 drill 1.15mm pad 3mm
+0
+24
+12
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-416_1x16_P5.00mm_45Degree
+Terminal Block WAGO 236-416, 45Degree (cable under 45degree), 16 pins, pitch 5mm, size 82.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-416 45Degree pitch 5mm size 82.3x14mm^2 drill 1.15mm pad 3mm
+0
+32
+16
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-424_1x24_P5.00mm_45Degree
+Terminal Block WAGO 236-424, 45Degree (cable under 45degree), 24 pins, pitch 5mm, size 122x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-424 45Degree pitch 5mm size 122x14mm^2 drill 1.15mm pad 3mm
+0
+48
+24
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-436_1x36_P5.00mm_45Degree
+Terminal Block WAGO 236-436, 45Degree (cable under 45degree), 36 pins, pitch 5mm, size 182x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-436 45Degree pitch 5mm size 182x14mm^2 drill 1.15mm pad 3mm
+0
+72
+36
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-448_1x48_P5.00mm_45Degree
+Terminal Block WAGO 236-448, 45Degree (cable under 45degree), 48 pins, pitch 5mm, size 242x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-448 45Degree pitch 5mm size 242x14mm^2 drill 1.15mm pad 3mm
+0
+96
+48
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-501_1x01_P7.50mm_45Degree
+Terminal Block WAGO 236-501, 45Degree (cable under 45degree), 1 pins, pitch 7.5mm, size 9.8x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-501 45Degree pitch 7.5mm size 9.8x14mm^2 drill 1.15mm pad 3mm
+0
+2
+1
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-502_1x02_P7.50mm_45Degree
+Terminal Block WAGO 236-502, 45Degree (cable under 45degree), 2 pins, pitch 7.5mm, size 17.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-502 45Degree pitch 7.5mm size 17.3x14mm^2 drill 1.15mm pad 3mm
+0
+4
+2
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-503_1x03_P7.50mm_45Degree
+Terminal Block WAGO 236-503, 45Degree (cable under 45degree), 3 pins, pitch 7.5mm, size 24.8x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-503 45Degree pitch 7.5mm size 24.8x14mm^2 drill 1.15mm pad 3mm
+0
+6
+3
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-504_1x04_P7.50mm_45Degree
+Terminal Block WAGO 236-504, 45Degree (cable under 45degree), 4 pins, pitch 7.5mm, size 32.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-504 45Degree pitch 7.5mm size 32.3x14mm^2 drill 1.15mm pad 3mm
+0
+8
+4
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-506_1x06_P7.50mm_45Degree
+Terminal Block WAGO 236-506, 45Degree (cable under 45degree), 6 pins, pitch 7.5mm, size 47.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-506 45Degree pitch 7.5mm size 47.3x14mm^2 drill 1.15mm pad 3mm
+0
+12
+6
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-508_1x08_P7.50mm_45Degree
+Terminal Block WAGO 236-508, 45Degree (cable under 45degree), 8 pins, pitch 7.5mm, size 62.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-508 45Degree pitch 7.5mm size 62.3x14mm^2 drill 1.15mm pad 3mm
+0
+16
+8
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-512_1x12_P7.50mm_45Degree
+Terminal Block WAGO 236-512, 45Degree (cable under 45degree), 12 pins, pitch 7.5mm, size 92.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-512 45Degree pitch 7.5mm size 92.3x14mm^2 drill 1.15mm pad 3mm
+0
+24
+12
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-516_1x16_P7.50mm_45Degree
+Terminal Block WAGO 236-516, 45Degree (cable under 45degree), 16 pins, pitch 7.5mm, size 122x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-516 45Degree pitch 7.5mm size 122x14mm^2 drill 1.15mm pad 3mm
+0
+32
+16
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-524_1x24_P7.50mm_45Degree
+Terminal Block WAGO 236-524, 45Degree (cable under 45degree), 24 pins, pitch 7.5mm, size 182x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-524 45Degree pitch 7.5mm size 182x14mm^2 drill 1.15mm pad 3mm
+0
+48
+24
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-601_1x01_P10.00mm_45Degree
+Terminal Block WAGO 236-601, 45Degree (cable under 45degree), 1 pins, pitch 10mm, size 12.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-601 45Degree pitch 10mm size 12.3x14mm^2 drill 1.15mm pad 3mm
+0
+2
+1
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-602_1x02_P10.00mm_45Degree
+Terminal Block WAGO 236-602, 45Degree (cable under 45degree), 2 pins, pitch 10mm, size 22.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-602 45Degree pitch 10mm size 22.3x14mm^2 drill 1.15mm pad 3mm
+0
+4
+2
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-603_1x03_P10.00mm_45Degree
+Terminal Block WAGO 236-603, 45Degree (cable under 45degree), 3 pins, pitch 10mm, size 32.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-603 45Degree pitch 10mm size 32.3x14mm^2 drill 1.15mm pad 3mm
+0
+6
+3
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-604_1x04_P10.00mm_45Degree
+Terminal Block WAGO 236-604, 45Degree (cable under 45degree), 4 pins, pitch 10mm, size 42.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-604 45Degree pitch 10mm size 42.3x14mm^2 drill 1.15mm pad 3mm
+0
+8
+4
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-606_1x06_P10.00mm_45Degree
+Terminal Block WAGO 236-606, 45Degree (cable under 45degree), 6 pins, pitch 10mm, size 62.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-606 45Degree pitch 10mm size 62.3x14mm^2 drill 1.15mm pad 3mm
+0
+12
+6
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-608_1x08_P10.00mm_45Degree
+Terminal Block WAGO 236-608, 45Degree (cable under 45degree), 8 pins, pitch 10mm, size 82.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-608 45Degree pitch 10mm size 82.3x14mm^2 drill 1.15mm pad 3mm
+0
+16
+8
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-612_1x12_P10.00mm_45Degree
+Terminal Block WAGO 236-612, 45Degree (cable under 45degree), 12 pins, pitch 10mm, size 122x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-612 45Degree pitch 10mm size 122x14mm^2 drill 1.15mm pad 3mm
+0
+24
+12
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-616_1x16_P10.00mm_45Degree
+Terminal Block WAGO 236-616, 45Degree (cable under 45degree), 16 pins, pitch 10mm, size 162x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-616 45Degree pitch 10mm size 162x14mm^2 drill 1.15mm pad 3mm
+0
+32
+16
+TerminalBlock_WAGO
+TerminalBlock_WAGO_236-624_1x24_P10.00mm_45Degree
+Terminal Block WAGO 236-624, 45Degree (cable under 45degree), 24 pins, pitch 10mm, size 242x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 236-624 45Degree pitch 10mm size 242x14mm^2 drill 1.15mm pad 3mm
+0
+48
+24
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-101_1x01_P5.00mm_45Degree
+Terminal Block WAGO 804-101, 45Degree (cable under 45degree), 1 pins, pitch 5mm, size 6.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-101 45Degree pitch 5mm size 6.5x15mm^2 drill 1.2mm pad 3mm
+0
+2
+1
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-102_1x02_P5.00mm_45Degree
+Terminal Block WAGO 804-102, 45Degree (cable under 45degree), 2 pins, pitch 5mm, size 11.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-102 45Degree pitch 5mm size 11.5x15mm^2 drill 1.2mm pad 3mm
+0
+4
+2
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-103_1x03_P5.00mm_45Degree
+Terminal Block WAGO 804-103, 45Degree (cable under 45degree), 3 pins, pitch 5mm, size 16.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-103 45Degree pitch 5mm size 16.5x15mm^2 drill 1.2mm pad 3mm
+0
+6
+3
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-104_1x04_P5.00mm_45Degree
+Terminal Block WAGO 804-104, 45Degree (cable under 45degree), 4 pins, pitch 5mm, size 21.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-104 45Degree pitch 5mm size 21.5x15mm^2 drill 1.2mm pad 3mm
+0
+8
+4
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-105_1x05_P5.00mm_45Degree
+Terminal Block WAGO 804-105, 45Degree (cable under 45degree), 5 pins, pitch 5mm, size 26.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-105 45Degree pitch 5mm size 26.5x15mm^2 drill 1.2mm pad 3mm
+0
+10
+5
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-106_1x06_P5.00mm_45Degree
+Terminal Block WAGO 804-106, 45Degree (cable under 45degree), 6 pins, pitch 5mm, size 31.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-106 45Degree pitch 5mm size 31.5x15mm^2 drill 1.2mm pad 3mm
+0
+12
+6
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-107_1x07_P5.00mm_45Degree
+Terminal Block WAGO 804-107, 45Degree (cable under 45degree), 7 pins, pitch 5mm, size 36.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-107 45Degree pitch 5mm size 36.5x15mm^2 drill 1.2mm pad 3mm
+0
+14
+7
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-108_1x08_P5.00mm_45Degree
+Terminal Block WAGO 804-108, 45Degree (cable under 45degree), 8 pins, pitch 5mm, size 41.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-108 45Degree pitch 5mm size 41.5x15mm^2 drill 1.2mm pad 3mm
+0
+16
+8
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-109_1x09_P5.00mm_45Degree
+Terminal Block WAGO 804-109, 45Degree (cable under 45degree), 9 pins, pitch 5mm, size 46.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-109 45Degree pitch 5mm size 46.5x15mm^2 drill 1.2mm pad 3mm
+0
+18
+9
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-110_1x10_P5.00mm_45Degree
+Terminal Block WAGO 804-110, 45Degree (cable under 45degree), 10 pins, pitch 5mm, size 51.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-110 45Degree pitch 5mm size 51.5x15mm^2 drill 1.2mm pad 3mm
+0
+20
+10
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-112_1x12_P5.00mm_45Degree
+Terminal Block WAGO 804-112, 45Degree (cable under 45degree), 12 pins, pitch 5mm, size 61.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-112 45Degree pitch 5mm size 61.5x15mm^2 drill 1.2mm pad 3mm
+0
+24
+12
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-116_1x16_P5.00mm_45Degree
+Terminal Block WAGO 804-116, 45Degree (cable under 45degree), 16 pins, pitch 5mm, size 81.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-116 45Degree pitch 5mm size 81.5x15mm^2 drill 1.2mm pad 3mm
+0
+32
+16
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-124_1x24_P5.00mm_45Degree
+Terminal Block WAGO 804-124, 45Degree (cable under 45degree), 24 pins, pitch 5mm, size 122x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-124 45Degree pitch 5mm size 122x15mm^2 drill 1.2mm pad 3mm
+0
+48
+24
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-301_1x01_P7.50mm_45Degree
+Terminal Block WAGO 804-301, 45Degree (cable under 45degree), 1 pins, pitch 7.5mm, size 6.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-301 45Degree pitch 7.5mm size 6.5x15mm^2 drill 1.2mm pad 3mm
+0
+2
+1
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-302_1x02_P7.50mm_45Degree
+Terminal Block WAGO 804-302, 45Degree (cable under 45degree), 2 pins, pitch 7.5mm, size 14x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-302 45Degree pitch 7.5mm size 14x15mm^2 drill 1.2mm pad 3mm
+0
+4
+2
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-303_1x03_P7.50mm_45Degree
+Terminal Block WAGO 804-303, 45Degree (cable under 45degree), 3 pins, pitch 7.5mm, size 21.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-303 45Degree pitch 7.5mm size 21.5x15mm^2 drill 1.2mm pad 3mm
+0
+6
+3
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-304_1x04_P7.50mm_45Degree
+Terminal Block WAGO 804-304, 45Degree (cable under 45degree), 4 pins, pitch 7.5mm, size 29x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-304 45Degree pitch 7.5mm size 29x15mm^2 drill 1.2mm pad 3mm
+0
+8
+4
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-305_1x05_P7.50mm_45Degree
+Terminal Block WAGO 804-305, 45Degree (cable under 45degree), 5 pins, pitch 7.5mm, size 36.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-305 45Degree pitch 7.5mm size 36.5x15mm^2 drill 1.2mm pad 3mm
+0
+10
+5
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-306_1x06_P7.50mm_45Degree
+Terminal Block WAGO 804-306, 45Degree (cable under 45degree), 6 pins, pitch 7.5mm, size 44x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-306 45Degree pitch 7.5mm size 44x15mm^2 drill 1.2mm pad 3mm
+0
+12
+6
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-307_1x07_P7.50mm_45Degree
+Terminal Block WAGO 804-307, 45Degree (cable under 45degree), 7 pins, pitch 7.5mm, size 51.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-307 45Degree pitch 7.5mm size 51.5x15mm^2 drill 1.2mm pad 3mm
+0
+14
+7
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-308_1x08_P7.50mm_45Degree
+Terminal Block WAGO 804-308, 45Degree (cable under 45degree), 8 pins, pitch 7.5mm, size 59x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-308 45Degree pitch 7.5mm size 59x15mm^2 drill 1.2mm pad 3mm
+0
+16
+8
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-309_1x09_P7.50mm_45Degree
+Terminal Block WAGO 804-309, 45Degree (cable under 45degree), 9 pins, pitch 7.5mm, size 66.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-309 45Degree pitch 7.5mm size 66.5x15mm^2 drill 1.2mm pad 3mm
+0
+18
+9
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-310_1x10_P7.50mm_45Degree
+Terminal Block WAGO 804-310, 45Degree (cable under 45degree), 10 pins, pitch 7.5mm, size 74x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-310 45Degree pitch 7.5mm size 74x15mm^2 drill 1.2mm pad 3mm
+0
+20
+10
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-312_1x12_P7.50mm_45Degree
+Terminal Block WAGO 804-312, 45Degree (cable under 45degree), 12 pins, pitch 7.5mm, size 89x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-312 45Degree pitch 7.5mm size 89x15mm^2 drill 1.2mm pad 3mm
+0
+24
+12
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-316_1x16_P7.50mm_45Degree
+Terminal Block WAGO 804-316, 45Degree (cable under 45degree), 16 pins, pitch 7.5mm, size 119x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-316 45Degree pitch 7.5mm size 119x15mm^2 drill 1.2mm pad 3mm
+0
+32
+16
+TerminalBlock_WAGO
+TerminalBlock_WAGO_804-324_1x24_P7.50mm_45Degree
+Terminal Block WAGO 804-324, 45Degree (cable under 45degree), 24 pins, pitch 7.5mm, size 179x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO
+THT Terminal Block WAGO 804-324 45Degree pitch 7.5mm size 179x15mm^2 drill 1.2mm pad 3mm
+0
+48
+24
+TestPoint
+TestPoint_2Pads_Pitch2.54mm_Drill0.8mm
+Test point with 2 pins, pitch 2.54mm, drill diameter 0.8mm
+CONN DEV
+0
+2
+2
+TestPoint
+TestPoint_2Pads_Pitch5.08mm_Drill1.3mm
+Test point with 2 pads, pitch 5.08mm, hole diameter 1.3mm, wire diameter 1.0mm
+CONN DEV
+0
+2
+2
+TestPoint
+TestPoint_Bridge_Pitch2.0mm_Drill0.7mm
+wire loop as test point, pitch 2.0mm, hole diameter 0.7mm, wire diameter 0.5mm
+test point wire loop
+0
+2
+1
+TestPoint
+TestPoint_Bridge_Pitch2.54mm_Drill0.7mm
+wire loop as test point, pitch 2.0mm, hole diameter 0.7mm, wire diameter 0.5mm
+test point wire loop
+0
+2
+1
+TestPoint
+TestPoint_Bridge_Pitch2.54mm_Drill1.0mm
+wire loop as test point, pitch 2.54mm, hole diameter 1.0mm, wire diameter 0.8mm
+test point wire loop
+0
+2
+1
+TestPoint
+TestPoint_Bridge_Pitch2.54mm_Drill1.3mm
+wire loop as test point, pitch 2.54mm, hole diameter 1.3mm, wire diameter 1.0mm
+test point wire loop
+0
+2
+1
+TestPoint
+TestPoint_Bridge_Pitch3.81mm_Drill1.3mm
+wire loop as test point, pitch 3.81mm, hole diameter 1.3mm, wire diameter 1.0mm
+test point wire loop
+0
+2
+1
+TestPoint
+TestPoint_Bridge_Pitch5.08mm_Drill0.7mm
+wire loop as test point, pitch 5.08mm, hole diameter 0.7mm, wire diameter 1.0mm
+test point wire loop
+0
+2
+1
+TestPoint
+TestPoint_Bridge_Pitch5.08mm_Drill1.3mm
+wire loop as test point, pitch 5.08mm, hole diameter 1.3mm, wire diameter 1.0mm
+test point wire loop
+0
+2
+1
+TestPoint
+TestPoint_Bridge_Pitch6.35mm_Drill1.3mm
+wire loop as test point, pitch 6.35mm, hole diameter 1.3mm, wire diameter 1.0mm
+test point wire loop
+0
+2
+1
+TestPoint
+TestPoint_Bridge_Pitch7.62mm_Drill1.3mm
+wire loop as test point, pitch 7.62mm, hole diameter 1.3mm, wire diameter 1.0mm
+test point wire loop
+0
+2
+1
+TestPoint
+TestPoint_Keystone_5000-5004_Miniature
+Keystone Miniature THM Test Point 5000-5004, http://www.keyelco.com/product-pdf.cfm?p=1309
+Through Hole Mount Test Points
+0
+1
+1
+TestPoint
+TestPoint_Keystone_5005-5009_Compact
+Keystone Miniature THM Test Point 5005-5009, http://www.keyelco.com/product-pdf.cfm?p=1314
+Through Hole Mount Test Points
+0
+1
+1
+TestPoint
+TestPoint_Keystone_5010-5014_Multipurpose
+Keystone Miniature THM Test Point 5010-5014, http://www.keyelco.com/product-pdf.cfm?p=1319
+Through Hole Mount Test Points
+0
+1
+1
+TestPoint
+TestPoint_Keystone_5015_Micro-Minature
+SMT Test Point- Micro Miniature 5015, http://www.keyelco.com/product-pdf.cfm?p=1353
+Test Point
+0
+1
+1
+TestPoint
+TestPoint_Keystone_5019_Minature
+SMT Test Point- Micro Miniature 5019, http://www.keyelco.com/product-pdf.cfm?p=1357
+Test Point
+0
+1
+1
+TestPoint
+TestPoint_Loop_D1.80mm_Drill1.0mm_Beaded
+wire loop with bead as test point, loop diameter 1.8mm, hole diameter 1.0mm
+test point wire loop bead
+0
+1
+1
+TestPoint
+TestPoint_Loop_D2.50mm_Drill1.0mm
+wire loop as test point, loop diameter 2.5mm, hole diameter 1.0mm
+test point wire loop bead
+0
+1
+1
+TestPoint
+TestPoint_Loop_D2.50mm_Drill1.0mm_LowProfile
+low profile wire loop as test point, loop diameter 2.5mm, hole diameter 1.0mm
+test point wire loop bead
+0
+1
+1
+TestPoint
+TestPoint_Loop_D2.50mm_Drill1.85mm
+wire loop as test point, loop diameter 2.5mm, hole diameter 1.85mm
+test point wire loop bead
+0
+1
+1
+TestPoint
+TestPoint_Loop_D2.54mm_Drill1.5mm_Beaded
+wire loop with bead as test point, loop diameter2.548mm, hole diameter 1.5mm
+test point wire loop bead
+0
+1
+1
+TestPoint
+TestPoint_Loop_D2.60mm_Drill0.9mm_Beaded
+wire loop with bead as test point, loop diameter2.6mm, hole diameter 0.9mm
+test point wire loop bead
+0
+1
+1
+TestPoint
+TestPoint_Loop_D2.60mm_Drill1.4mm_Beaded
+wire loop with bead as test point, loop diameter2.6mm, hole diameter 1.4mm
+test point wire loop bead
+0
+1
+1
+TestPoint
+TestPoint_Loop_D2.60mm_Drill1.6mm_Beaded
+wire loop with bead as test point, loop diameter2.6mm, hole diameter 1.6mm
+test point wire loop bead
+0
+1
+1
+TestPoint
+TestPoint_Loop_D3.50mm_Drill0.9mm_Beaded
+wire loop with bead as test point, loop diameter2.6mm, hole diameter 0.9mm
+test point wire loop bead
+0
+1
+1
+TestPoint
+TestPoint_Loop_D3.50mm_Drill1.4mm_Beaded
+wire loop with bead as test point, loop diameter 3.5mm, hole diameter 1.4mm
+test point wire loop bead
+0
+1
+1
+TestPoint
+TestPoint_Loop_D3.80mm_Drill2.0mm
+wire loop as test point, loop diameter 3.8mm, hole diameter 2.0mm
+test point wire loop bead
+0
+1
+1
+TestPoint
+TestPoint_Loop_D3.80mm_Drill2.5mm
+wire loop as test point, loop diameter 3.8mm, hole diameter 2.5mm
+test point wire loop bead
+0
+1
+1
+TestPoint
+TestPoint_Loop_D3.80mm_Drill2.8mm
+wire loop as test point, loop diameter 3.8mm, hole diameter 2.8mm
+test point wire loop bead
+0
+1
+1
+TestPoint
+TestPoint_Pad_1.0x1.0mm
+SMD rectangular pad as test Point, square 1.0mm side length
+test point SMD pad rectangle square
+0
+1
+1
+TestPoint
+TestPoint_Pad_1.5x1.5mm
+SMD rectangular pad as test Point, square 1.5mm side length
+test point SMD pad rectangle square
+0
+1
+1
+TestPoint
+TestPoint_Pad_2.0x2.0mm
+SMD rectangular pad as test Point, square 2.0mm side length
+test point SMD pad rectangle square
+0
+1
+1
+TestPoint
+TestPoint_Pad_2.5x2.5mm
+SMD rectangular pad as test Point, square 2.5mm side length
+test point SMD pad rectangle square
+0
+1
+1
+TestPoint
+TestPoint_Pad_3.0x3.0mm
+SMD rectangular pad as test Point, square 3.0mm side length
+test point SMD pad rectangle square
+0
+1
+1
+TestPoint
+TestPoint_Pad_4.0x4.0mm
+SMD rectangular pad as test Point, square 4.0mm side length
+test point SMD pad rectangle square
+0
+1
+1
+TestPoint
+TestPoint_Pad_D1.0mm
+SMD pad as test Point, diameter 1.0mm
+test point SMD pad
+0
+1
+1
+TestPoint
+TestPoint_Pad_D1.5mm
+SMD pad as test Point, diameter 1.5mm
+test point SMD pad
+0
+1
+1
+TestPoint
+TestPoint_Pad_D2.0mm
+SMD pad as test Point, diameter 2.0mm
+test point SMD pad
+0
+1
+1
+TestPoint
+TestPoint_Pad_D2.5mm
+SMD pad as test Point, diameter 2.5mm
+test point SMD pad
+0
+1
+1
+TestPoint
+TestPoint_Pad_D3.0mm
+SMD pad as test Point, diameter 3.0mm
+test point SMD pad
+0
+1
+1
+TestPoint
+TestPoint_Pad_D4.0mm
+SMD pad as test Point, diameter 4.0mm
+test point SMD pad
+0
+1
+1
+TestPoint
+TestPoint_Plated_Hole_D2.0mm
+Plated Hole as test Point, diameter 2.0mm
+test point plated hole
+0
+1
+1
+TestPoint
+TestPoint_Plated_Hole_D3.0mm
+Plated Hole as test Point, diameter 3.0mm
+test point plated hole
+0
+1
+1
+TestPoint
+TestPoint_Plated_Hole_D4.0mm
+Plated Hole as test Point, diameter 4.0mm
+test point plated hole
+0
+1
+1
+TestPoint
+TestPoint_Plated_Hole_D5.0mm
+Plated Hole as test Point, diameter 5.0mm
+test point plated hole
+0
+1
+1
+TestPoint
+TestPoint_THTPad_1.0x1.0mm_Drill0.5mm
+THT rectangular pad as test Point, square 1.0mm side length, hole diameter 0.5mm
+test point THT pad rectangle square
+0
+1
+1
+TestPoint
+TestPoint_THTPad_1.5x1.5mm_Drill0.7mm
+THT rectangular pad as test Point, square 1.5mm side length, hole diameter 0.7mm
+test point THT pad rectangle square
+0
+1
+1
+TestPoint
+TestPoint_THTPad_2.0x2.0mm_Drill1.0mm
+THT rectangular pad as test Point, square 2.0mm_Drill1.0mm  side length, hole diameter 1.0mm
+test point THT pad rectangle square
+0
+1
+1
+TestPoint
+TestPoint_THTPad_2.5x2.5mm_Drill1.2mm
+THT rectangular pad as test Point, square 2.5mm side length, hole diameter 1.2mm
+test point THT pad rectangle square
+0
+1
+1
+TestPoint
+TestPoint_THTPad_3.0x3.0mm_Drill1.5mm
+THT rectangular pad as test Point, square 3.0mm side length, hole diameter 1.5mm
+test point THT pad rectangle square
+0
+1
+1
+TestPoint
+TestPoint_THTPad_4.0x4.0mm_Drill2.0mm
+THT rectangular pad as test Point, square 4.0mm  side length, hole diameter 2.0mm
+test point THT pad rectangle square
+0
+1
+1
+TestPoint
+TestPoint_THTPad_D1.0mm_Drill0.5mm
+THT pad as test Point, diameter 1.0mm, hole diameter 0.5mm
+test point THT pad
+0
+1
+1
+TestPoint
+TestPoint_THTPad_D1.5mm_Drill0.7mm
+THT pad as test Point, diameter 1.5mm, hole diameter 0.7mm
+test point THT pad
+0
+1
+1
+TestPoint
+TestPoint_THTPad_D2.0mm_Drill1.0mm
+THT pad as test Point, diameter 2.0mm, hole diameter 1.0mm
+test point THT pad
+0
+1
+1
+TestPoint
+TestPoint_THTPad_D2.5mm_Drill1.2mm
+THT pad as test Point, diameter 2.5mm, hole diameter 1.2mm 
+test point THT pad
+0
+1
+1
+TestPoint
+TestPoint_THTPad_D3.0mm_Drill1.5mm
+THT pad as test Point, diameter 3.0mm, hole diameter 1.5mm
+test point THT pad
+0
+1
+1
+TestPoint
+TestPoint_THTPad_D4.0mm_Drill2.0mm
+THT pad as test Point, diameter 4.0mm, hole diameter 2.0mm
+test point THT pad
+0
+1
+1
+Transformer_SMD
+Pulse_P0926NL
+SMT Gate Drive Transformer, 1:1:1, 8.0x6.3x5.3mm (https://productfinder.pulseeng.com/products/datasheets/SPM2007_61.pdf)
+pulse pa0926nl
+0
+6
+6
+Transformer_SMD
+Pulse_PA1323NL
+SMT Gate Drive Transformer, 1:1, 9.5x7.1x5.3mm (https://productfinder.pulseeng.com/products/datasheets/SPM2007_61.pdf)
+pulse pa1323nl
+0
+6
+6
+Transformer_SMD
+Pulse_PA2001NL
+SMT Gate Drive Transformer, 1:1, 8.6x6.7x2.5mm (https://productfinder.pulseeng.com/products/datasheets/P663.pdf)
+pulse pa2001nl pe-68386nl
+0
+4
+4
+Transformer_SMD
+Pulse_PA2002NL-PA2008NL-PA2009NL
+SMT Gate Drive Transformer, 1:1:1 or 2:1:1 or 2.5:1:1 or 1:1, 9.0x8.6x7.6mm (https://productfinder.pulseeng.com/products/datasheets/P663.pdf)
+pulse pa2002nl pa2008nl pa2009nl p0544nl pa0184nl pa0297nl pa0510nl
+0
+6
+6
+Transformer_SMD
+Pulse_PA2004NL
+SMT Gate Drive Transformer, 1:1:1, 8.6x6.7x3.6mm (https://productfinder.pulseeng.com/products/datasheets/P663.pdf)
+pulse pa2004nl pa0264nl
+0
+6
+6
+Transformer_SMD
+Pulse_PA2005NL
+SMT Gate Drive Transformer, 1:1:1, 11.8x8.8x4.0mm (https://productfinder.pulseeng.com/products/datasheets/P663.pdf)
+pulse pa2005nl pa0173nl
+0
+6
+6
+Transformer_SMD
+Pulse_PA2006NL
+SMT Gate Drive Transformer, 1:1, 11.8x8.8x4.0mm (https://productfinder.pulseeng.com/products/datasheets/P663.pdf)
+pulse pa2006nl pa0186nl
+0
+4
+4
+Transformer_SMD
+Pulse_PA2007NL
+SMT Gate Drive Transformer, 1:1, 9.0x8.6x7.6mm (https://productfinder.pulseeng.com/products/datasheets/P663.pdf)
+pulse pa2007nl
+0
+4
+4
+Transformer_SMD
+Pulse_PA2777NL
+SMT Gate Drive Transformer, 1:1, 7.1x6.1x5.5mm (https://productfinder.pulseeng.com/products/datasheets/SPM2007_61.pdf)
+pulse pa2777nl
+0
+8
+8
+Transformer_SMD
+Pulse_PA3493NL
+SMT Gate Drive Transformer, 1.25:1, 10.9x9.7x2.7mm (https://productfinder.pulseeng.com/products/datasheets/SPM2007_61.pdf)
+pulse pa3493nl
+0
+4
+4
+Transformer_SMD
+Transformer_Coilcraft_CST1
+Current sense transformer, SMD, 8.0x8.13x5.3mm (https://www.coilcraft.com/pdfs/cst.pdf)
+Transformer current sense SMD
+0
+8
+8
+Transformer_SMD
+Transformer_Coilcraft_CST2
+Current sense transformer, SMD, 8.0x8.13x5.3mm (https://www.coilcraft.com/pdfs/cst.pdf)
+Transformer current sense SMD
+0
+8
+8
+Transformer_SMD
+Transformer_Coilcraft_CST2010
+Current sense transformer, SMD, 14.55x19.91x10.50mm (https://www.coilcraft.com/pdfs/cst2010.pdf)
+Transformer current sense SMD
+0
+12
+12
+Transformer_SMD
+Transformer_CurrentSense_8.4x7.2mm
+Transformer current sense SMD 8.4x7.2mm
+Transformer current sense SMD
+0
+8
+8
+Transformer_SMD
+Transformer_Ethernet_Bel_S558-5999-T7-F
+Ethernet Transformer, Bel S558-5999-T7-F, https://www.belfuse.com/resources/ICMs/lan-/S558-5999-T7-F.pdf
+Ethernet Transformer
+0
+16
+16
+Transformer_SMD
+Transformer_Ethernet_Bourns_PT61017PEL
+https://www.bourns.com/docs/Product-Datasheets/PT61017PEL.pdf
+Transformer Ethernet Single Center-Tap
+0
+16
+16
+Transformer_SMD
+Transformer_Ethernet_HALO_TG111-MSC13
+Transformer Ethernet SMD, https://www.haloelectronics.com/pdf/discrete-genesus.pdf
+Transformer Ethernet SMD
+0
+24
+24
+Transformer_SMD
+Transformer_MACOM_SM-22
+https://cdn.macom.com/datasheets/ETC1-1-13.pdf
+RF Transformer
+0
+5
+5
+Transformer_SMD
+Transformer_NF_ETAL_P2781
+NF-Transformer, ETAL, P2781, SMD,
+NF-Transformer ETAL P2781 SMD 
+0
+8
+7
+Transformer_SMD
+Transformer_NF_ETAL_P2781_HandSoldering
+NF-Transformer, ETAL, P2781, SMD, Handsoldering
+NF-Transformer ETAL P2781 SMD Handsoldering 
+0
+8
+7
+Transformer_SMD
+Transformer_NF_ETAL_P3000
+NF-Reansformer, ETAL, P3000, SMD,
+NF-Reansformer ETAL P3000 SMD 
+0
+15
+13
+Transformer_SMD
+Transformer_NF_ETAL_P3000_HandSoldering
+NF-Reansformer, ETAL, P3000, SMD, Handsoldering,
+NF-Reansformer ETAL P3000 SMD Handsoldering 
+0
+15
+13
+Transformer_SMD
+Transformer_NF_ETAL_P3181
+NF-Transformer, ETAL, P3181, SMD,
+NF-Transformer ETAL P3181 SMD 
+0
+7
+6
+Transformer_SMD
+Transformer_NF_ETAL_P3181_HandSoldering
+NF-Transformer, ETAL, P3181, SMD, Hand Soldering,
+NF-Transformer ETAL P3181 SMD Hand Soldering 
+0
+7
+6
+Transformer_SMD
+Transformer_NF_ETAL_P3188
+NF-Transformer, ETAL, P3188, SMD,
+NF-Transformer ETAL P3188 SMD 
+0
+8
+6
+Transformer_SMD
+Transformer_NF_ETAL_P3188_HandSoldering
+NF-Transformer, ETAL, P3188, SMD, Handsoldering,
+NF-Transformer ETAL P3188 SMD Handsoldering 
+0
+8
+6
+Transformer_SMD
+Transformer_NF_ETAL_P3191
+NF-Transformer, ETAL, P3191, SMD,
+NF-Transformer ETAL P3191 SMD 
+0
+8
+6
+Transformer_SMD
+Transformer_NF_ETAL_P3191_HandSoldering
+NF-Transformer, ETAL, P3191, SMD, Handsoldering,
+NF-Transformer ETAL P3191 SMD Handsoldering 
+0
+8
+6
+Transformer_SMD
+Transformer_Pulse_H1100NL
+For H1100NL, H1101NL, H1102NL, H1121NL, H1183NL, H1199NL, HX1188NL, HX1198NL and H1302NL. https://productfinder.pulseeng.com/doc_type/WEB301/doc_num/H1102NL/doc_part/H1102NL.pdf
+H1100NL H1101NL H1102NL H1121NL H1183NL H1199NL HX1188NL HX1198NL H1302N
+0
+16
+16
+Transformer_THT
+Autotransformer_Toroid_1Tap_Horizontal_D9.0mm_Amidon-T30
+Autotransformer, Toroid, horizontal, laying, 1 Tap, Diameter 9mm, Amidon T30,
+Autotransformer Toroid horizontal laying 1 Tap Diameter 9mm Amidon T30 
+0
+3
+3
+Transformer_THT
+Autotransformer_Toroid_1Tap_Horizontal_D10.5mm_Amidon-T37
+Autotransformer, Toroid, horizontal, laying, 1 Tap, Diameter 10,5mm, Amidon T37,
+Autotransformer Toroid horizontal laying 1 Tap Diameter 10 5mm Amidon T37 
+0
+3
+3
+Transformer_THT
+Autotransformer_Toroid_1Tap_Horizontal_D12.5mm_Amidon-T44
+Autotransformer, Toroid, horizontal, laying, 1 Tap, Diameter 12,5mm, Amidon T44,
+Autotransformer Toroid horizontal laying 1 Tap Diameter 12 5mm Amidon T44 
+0
+3
+3
+Transformer_THT
+Autotransformer_Toroid_1Tap_Horizontal_D14.0mm_Amidon-T50
+Choke, Inductance, Autotransformer, Toroid, horizontal, laying, 1 Tap, Diameter 14mm, Amidon T50,
+Choke Inductance Autotransformer Toroid horizontal laying 1 Tap Diameter 14mm Amidon T50 
+0
+3
+3
+Transformer_THT
+Autotransformer_ZS1052-AC
+Ignition coil for xenon flash, http://www.excelitas.com/downloads/ZS1052ACH.pdf
+ignition coil autotransformer
+0
+3
+3
+Transformer_THT
+Transformer_37x44
+transformer 37x44mm²
+transformer 37x44mm²
+0
+12
+4
+Transformer_THT
+Transformer_Breve_TEZ-22x24
+http://www.breve.pl/pdf/ANG/TEZ_ang.pdf
+TEZ PCB Transformer
+0
+7
+7
+Transformer_THT
+Transformer_Breve_TEZ-28x33
+http://www.breve.pl/pdf/ANG/TEZ_ang.pdf
+TEZ PCB Transformer
+0
+9
+9
+Transformer_THT
+Transformer_Breve_TEZ-35x42
+http://www.breve.pl/pdf/ANG/TEZ_ang.pdf
+TEZ PCB Transformer
+0
+9
+9
+Transformer_THT
+Transformer_Breve_TEZ-38x45
+http://www.breve.pl/pdf/ANG/TEZ_ang.pdf
+TEZ PCB Transformer
+0
+9
+9
+Transformer_THT
+Transformer_Breve_TEZ-44x52
+http://www.breve.pl/pdf/ANG/TEZ_ang.pdf
+TEZ PCB Transformer
+0
+10
+10
+Transformer_THT
+Transformer_Breve_TEZ-47x57
+http://www.breve.pl/pdf/ANG/TEZ_ang.pdf
+TEZ PCB Transformer
+0
+13
+13
+Transformer_THT
+Transformer_CHK_EI30-2VA_1xSec
+Trafo, Printtrafo, CHK, EI30, 2VA, 1x Sec,http://www.eratransformers.com/downloads/030-7585.0.pdf
+Trafo Printtrafo CHK EI30 2VA 1x Sec 
+0
+10
+10
+Transformer_THT
+Transformer_CHK_EI30-2VA_2xSec
+Trafo, Printtrafo, CHK, EI30, 2VA, 2x Sec,
+Trafo Printtrafo CHK EI30 2VA 2x Sec 
+0
+10
+10
+Transformer_THT
+Transformer_CHK_EI30-2VA_Neutral
+Trafo, Printtrafo, CHK, EI30, 2VA, neutral,
+Trafo Printtrafo CHK EI30 2VA neutral 
+0
+10
+10
+Transformer_THT
+Transformer_CHK_EI38-3VA_1xSec
+Trafo, Printtrafo, CHK, EI38, 3VA, 1x Sec, http://www.eratransformers.com/product-detail/20
+Trafo Printtrafo CHK EI38 3VA 1x Sec 
+0
+10
+10
+Transformer_THT
+Transformer_CHK_EI38-3VA_2xSec
+Trafo, Printtrafo, CHK, EI38, 3VA, 2x Sec, http://www.eratransformers.com/product-detail/20
+Trafo Printtrafo CHK EI38 3VA 2x Sec 
+0
+10
+10
+Transformer_THT
+Transformer_CHK_EI38-3VA_Neutral
+Trafo, Printtrafo, CHK, EI38, 3VA, neutral, http://www.eratransformers.com/product-detail/20
+Trafo Printtrafo CHK EI42 3VA neutral 
+0
+10
+10
+Transformer_THT
+Transformer_CHK_EI42-5VA_1xSec
+Trafo, Printtrafo, CHK, EI42, 5VA, 1x Sec,
+Trafo Printtrafo CHK EI42 5VA 1x Sec 
+0
+10
+10
+Transformer_THT
+Transformer_CHK_EI42-5VA_2xSec
+Trafo, Printtrafo, CHK, EI42, 5VA, 2x Sec,
+Trafo Printtrafo CHK EI42 5VA 2x Sec 
+0
+10
+10
+Transformer_THT
+Transformer_CHK_EI42-5VA_Neutral
+Trafo, Printtrafo, CHK, EI42, 5VA, neutral,
+Trafo Printtrafo CHK EI42 5VA neutral 
+0
+10
+10
+Transformer_THT
+Transformer_CHK_EI48-8VA_1xSec
+Trafo, Printtrafo, CHK, EI48, 8VA, 1x Sec, http://www.eratransformers.com/product-detail/18
+Trafo Printtrafo CHK EI48 8VA 1x Sec 
+0
+12
+12
+Transformer_THT
+Transformer_CHK_EI48-8VA_2xSec
+Trafo, Printtrafo, CHK, EI48, 8VA, 2x Sec, http://www.eratransformers.com/product-detail/18
+Trafo Printtrafo CHK EI48 8VA 2x Sec 
+0
+12
+12
+Transformer_THT
+Transformer_CHK_EI48-8VA_Neutral
+Trafo, Printtrafo, CHK, EI48, 8VA, neutral, http://www.eratransformers.com/product-detail/18
+Trafo Printtrafo CHK EI48 8VA neutral 
+0
+12
+12
+Transformer_THT
+Transformer_CHK_EI48-10VA_1xSec
+Trafo, Printtrafo, CHK, EI48, 10VA, 1x Sec,
+Trafo Printtrafo CHK EI48 10VA 1x Sec 
+0
+12
+12
+Transformer_THT
+Transformer_CHK_EI48-10VA_2xSec
+Trafo, Printtrafo, CHK, EI48, 10VA, 2x Sec, http://www.eratransformers.com/product-detail/18
+Trafo Printtrafo CHK EI48 10VA 2x Sec 
+0
+12
+12
+Transformer_THT
+Transformer_CHK_EI48-10VA_Neutral
+Trafo, Printtrafo, CHK, EI48, 10VA, neutral, http://www.eratransformers.com/product-detail/18
+Trafo Printtrafo CHK EI48 10VA neutral 
+0
+12
+12
+Transformer_THT
+Transformer_CHK_EI54-12VA_1xSec
+Trafo, Printtrafo, CHK, EI54, 12VA, 1x Sec,http://www.eratransformers.com/product-detail/19
+Trafo Printtrafo CHK EI54 12VA 1x Sec 
+0
+14
+14
+Transformer_THT
+Transformer_CHK_EI54-12VA_2xSec
+Trafo, Printtrafo, CHK, EI54, 12VA, 2x Sec,http://www.eratransformers.com/product-detail/19
+Trafo Printtrafo CHK EI54 12VA 2x Sec 
+0
+14
+14
+Transformer_THT
+Transformer_CHK_EI54-12VA_Neutral
+Trafo, Printtrafo, CHK, EI54, 12VA, neutral,http://www.eratransformers.com/product-detail/19
+Trafo Printtrafo CHK EI54 12VA neutral 
+0
+14
+14
+Transformer_THT
+Transformer_CHK_EI54-16VA_1xSec
+Trafo, Printtrafo, CHK, EI54, 16VA, 1x Sec,http://www.eratransformers.com/product-detail/19
+Trafo Printtrafo CHK EI54 16VA 1x Sec 
+0
+14
+14
+Transformer_THT
+Transformer_CHK_EI54-16VA_2xSec
+Trafo, Printtrafo, CHK, EI54, 16VA, 2x Sec,http://www.eratransformers.com/product-detail/19
+Trafo Printtrafo CHK EI54 16VA 2x Sec 
+0
+14
+14
+Transformer_THT
+Transformer_CHK_EI54-16VA_Neutral
+Trafo, Printtrafo, CHK, EI54, 16VA, neutral,http://www.eratransformers.com/product-detail/19
+Trafo Printtrafo CHK EI54 16VA neutral 
+0
+14
+14
+Transformer_THT
+Transformer_CHK_UI30-4VA_Flat
+Trafo, Flattrafo, CHK, UI30, 4VA,
+Trafo Flattrafo CHK UI30 4VA 
+0
+16
+16
+Transformer_THT
+Transformer_CHK_UI39-10VA_Flat
+Trafo, Flattrafo, CHK, UI39, 10VA,
+Trafo Flattrafo CHK UI39 10VA 
+0
+20
+20
+Transformer_THT
+Transformer_Coilcraft_Q4434-B_Rhombus-T1311
+Transformator, Transformer, Flyback, Coilcraft Q4434-B, Rgombus T1311,
+Transformator Transformer Flyback Coilcraft Q4434-B Rgombus T1311 
+0
+8
+8
+Transformer_THT
+Transformer_EPCOS_B66359A1013T_Horizontal
+Transformer, Transformator, ETD29, 13 Pin, Horizontal, EPCOS-B66359A1013T,
+Transformer Transformator ETD29 13 Pin Horizontal EPCOS-B66359A1013T 
+0
+13
+13
+Transformer_THT
+Transformer_EPCOS_B66359J1014T_Vertical
+Transformer, Transformator, ETD29, 14 Pin, Vertical, EPCOS-B66359J1014T,
+Transformer Transformator ETD29 14 Pin Vertical EPCOS-B66359J1014T 
+0
+14
+14
+Transformer_THT
+Transformer_Microphone_Lundahl_LL1538
+AUDIO TRAFO LUNDAHL, https://www.lundahltransformers.com/wp-content/uploads/datasheets/1538_8xl.pdf
+AUDIO TRAFO LUNDAHL
+0
+7
+7
+Transformer_THT
+Transformer_Microphone_Lundahl_LL1587
+AUDIO TRAFO LUNDAHL, https://www.lundahltransformers.com/wp-content/uploads/datasheets/1587.pdf
+AUDIO TRAFO LUNDAHL
+0
+7
+7
+Transformer_THT
+Transformer_Myrra_74040_Horizontal
+Transformer, Transformator, ETD29, 13 Pin, Horizontal, Myrra-74040,
+Transformer Transformator ETD29 13 Pin Horizontal Myrra-74040 
+0
+13
+13
+Transformer_THT
+Transformer_Myrra_EF20_7408x
+EF20 flyback transformer,http://myrra.com/wp-content/uploads/2017/09/Datasheet-74087-74088-74089-rev-A.pdf
+transformer flyback SMPS
+0
+9
+9
+Transformer_THT
+Transformer_NF_ETAL_1-1_P1200
+NF-Transformer, 1:1, ETAL P1200,http://www.etalgroup.com/sites/default/files/products/P1200_April_2005.pdf
+NF-Transformer 1to1 ETAL P1200 
+0
+4
+4
+Transformer_THT
+Transformer_NF_ETAL_P1165
+NF-Transformer,  ETAL, P1165,http://www.etalgroup.com/sites/default/files/products/P1165_February_2006.pdf
+NF-Transformer ETAL P1165 
+0
+4
+4
+Transformer_THT
+Transformer_NF_ETAL_P3324
+NF-Transformer, ETAL P3324,http://www.etalgroup.com/sites/default/files/products/P3324_April_2005.pdf
+NF-Transformer ETAL P3324 
+0
+4
+4
+Transformer_THT
+Transformer_NF_ETAL_P3356
+NF-Transformer, ETAL P3356, http://www.etalgroup.com/sites/default/files/products/P3356_December_2005.pdf
+NF-Transformer ETAL P3356 
+0
+4
+4
+Transformer_THT
+Transformer_Toroid_Horizontal_D9.0mm_Amidon-T30
+Transformer, Toroid, horizontal, laying, Diameter 9mm, Amidon, T30,
+Transformer Toroid horizontal laying Diameter 9mm Amidon T30 
+0
+4
+4
+Transformer_THT
+Transformer_Toroid_Horizontal_D10.5mm_Amidon-T37
+Transformer, Toroid, horizontal, laying, Diameter 10,5mm, Amidon T37,
+Transformer Toroid horizontal laying Diameter 10 5mm Amidon T37 
+0
+4
+4
+Transformer_THT
+Transformer_Toroid_Horizontal_D12.5mm_Amidon-T44
+Transformer, Toroid, horizontal, laying, Diameter 12,5mm, Amidon T44,
+Transformer Toroid horizontal laying Diameter 12 5mm Amidon T44 
+0
+4
+4
+Transformer_THT
+Transformer_Toroid_Horizontal_D14.0mm_Amidon-T50
+Transformer, Toroid, horizontal, laying, Diameter 14mm, Amidon T50,
+Transformer Toroid horizontal laying Diameter 14mm Amidon T50 
+0
+4
+4
+Transformer_THT
+Transformer_Toroid_Horizontal_D18.0mm
+Transformer, Toroid, tapped, horizontal, laying, Diameter 18mm, 
+Transformer Toroid tapped horizontal laying Diameter 18mm 
+0
+5
+4
+Transformer_THT
+Transformer_Toroid_Tapped_Horizontal_D9.0mm_Amidon-T30
+Transformer, Toroid, tapped, horizontal, laying, Diameter 9mm, Amidon, T30,
+Transformer Toroid tapped horizontal laying Diameter 9mm Amidon T30 
+0
+6
+6
+Transformer_THT
+Transformer_Toroid_Tapped_Horizontal_D10.5mm_Amidon-T37
+Transformer, Toroid, tapped, horizontal, laying, Diameter 10,5mm, Amidon, T37,
+Transformer Toroid tapped horizontal laying Diameter 10 5mm Amidon T37 
+0
+6
+6
+Transformer_THT
+Transformer_Toroid_Tapped_Horizontal_D12.5mm_Amidon-T44
+Transformer, Toroid, tapped, horizontal, laying, Diameter 12,5mm, Amidon, T44,
+Transformer Toroid tapped horizontal laying Diameter 12 5mm Amidon T44 
+0
+6
+6
+Transformer_THT
+Transformer_Toroid_Tapped_Horizontal_D14.0mm_Amidon-T50
+Transformer, Toroid, tapped, horizontal, laying, Diameter 14mm, Amidon T50,
+Transformer Toroid tapped horizontal laying Diameter 14mm Amidon T50 
+0
+6
+6
+Transformer_THT
+Transformer_Wuerth_750343373
+Transformer, horizontal core with bobbin, 10 pin, 3.81mm pitch, 15.24mm row spacing, 22x23x17.53mm (https://katalog.we-online.com/ctm/datasheet/750343373.pdf)
+transformer flyback
+0
+10
+10
+Valve
+Valve_ECC-83-1
+Valve ECC-83-1 round pins
+Valve ECC-83-1 round pins
+0
+9
+9
+Valve
+Valve_ECC-83-2
+Valve ECC-83-2 flat pins
+Valve ECC-83-2 flat pins
+0
+10
+9
+Valve
+Valve_EURO
+Valve Euro
+Valve Euro
+0
+7
+5
+Valve
+Valve_Glimm
+Valve Glimm
+Valve Glimm
+0
+2
+2
+Valve
+Valve_Mini_G
+Valve mini G
+Valve mini G
+0
+9
+7
+Valve
+Valve_Mini_P
+Valve mini P
+Valve mini P
+0
+7
+7
+Valve
+Valve_Mini_Pentode_Linear
+Mini-Pentode, 5-pin, e.g. JAN6418
+Valve Mini-Pentode 5-pin JAN6418
+0
+5
+5
+Valve
+Valve_Noval_G
+Valve NOVAL G
+Valve NOVAL G
+0
+11
+9
+Valve
+Valve_Noval_P
+Valve NOVAL P
+Valve NOVAL P
+0
+9
+9
+Valve
+Valve_Octal
+8-pin round valve
+valve
+0
+9
+8
+Varistor
+RV_Disc_D7mm_W3.4mm_P5mm
+Varistor, diameter 7mm, width 3.4mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D7mm_W3.5mm_P5mm
+Varistor, diameter 7mm, width 3.5mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D7mm_W3.6mm_P5mm
+Varistor, diameter 7mm, width 3.6mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D7mm_W3.7mm_P5mm
+Varistor, diameter 7mm, width 3.7mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D7mm_W3.8mm_P5mm
+Varistor, diameter 7mm, width 3.8mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D7mm_W3.9mm_P5mm
+Varistor, diameter 7mm, width 3.9mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D7mm_W4.2mm_P5mm
+Varistor, diameter 7mm, width 4.2mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D7mm_W4.3mm_P5mm
+Varistor, diameter 7mm, width 4.3mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D7mm_W4.5mm_P5mm
+Varistor, diameter 7mm, width 4.5mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D7mm_W4.8mm_P5mm
+Varistor, diameter 7mm, width 4.8mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D7mm_W4.9mm_P5mm
+Varistor, diameter 7mm, width 4.9mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D7mm_W4mm_P5mm
+Varistor, diameter 7mm, width 4mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D7mm_W5.1mm_P5mm
+Varistor, diameter 7mm, width 5.1mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D7mm_W5.4mm_P5mm
+Varistor, diameter 7mm, width 5.4mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D7mm_W5.5mm_P5mm
+Varistor, diameter 7mm, width 5.5mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D7mm_W5.7mm_P5mm
+Varistor, diameter 7mm, width 5.7mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D9mm_W3.3mm_P5mm
+Varistor, diameter 9mm, width 3.3mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D9mm_W3.4mm_P5mm
+Varistor, diameter 9mm, width 3.4mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D9mm_W3.5mm_P5mm
+Varistor, diameter 9mm, width 3.5mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D9mm_W3.6mm_P5mm
+Varistor, diameter 9mm, width 3.6mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D9mm_W3.7mm_P5mm
+Varistor, diameter 9mm, width 3.7mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D9mm_W3.8mm_P5mm
+Varistor, diameter 9mm, width 3.8mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D9mm_W3.9mm_P5mm
+Varistor, diameter 9mm, width 3.9mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D9mm_W4.1mm_P5mm
+Varistor, diameter 9mm, width 4.1mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D9mm_W4.2mm_P5mm
+Varistor, diameter 9mm, width 4.2mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D9mm_W4.4mm_P5mm
+Varistor, diameter 9mm, width 4.4mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D9mm_W4.5mm_P5mm
+Varistor, diameter 9mm, width 4.5mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D9mm_W4.8mm_P5mm
+Varistor, diameter 9mm, width 4.8mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D9mm_W4mm_P5mm
+Varistor, diameter 9mm, width 4mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D9mm_W5.2mm_P5mm
+Varistor, diameter 9mm, width 5.2mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D9mm_W5.4mm_P5mm
+Varistor, diameter 9mm, width 5.4mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D9mm_W5.5mm_P5mm
+Varistor, diameter 9mm, width 5.5mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D9mm_W5.7mm_P5mm
+Varistor, diameter 9mm, width 5.7mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D9mm_W6.1mm_P5mm
+Varistor, diameter 9mm, width 6.1mm, pitch 5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W3.9mm_P7.5mm
+Varistor, diameter 12mm, width 3.9mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W4.2mm_P7.5mm
+Varistor, diameter 12mm, width 4.2mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W4.3mm_P7.5mm
+Varistor, diameter 12mm, width 4.3mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W4.4mm_P7.5mm
+Varistor, diameter 12mm, width 4.4mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W4.5mm_P7.5mm
+Varistor, diameter 12mm, width 4.5mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W4.6mm_P7.5mm
+Varistor, diameter 12mm, width 4.6mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W4.7mm_P7.5mm
+Varistor, diameter 12mm, width 4.7mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W4.8mm_P7.5mm
+Varistor, diameter 12mm, width 4.8mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W4mm_P7.5mm
+Varistor, diameter 12mm, width 4mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W5.1mm_P7.5mm
+Varistor, diameter 12mm, width 5.1mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W5.4mm_P7.5mm
+Varistor, diameter 12mm, width 5.4mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W5.8mm_P7.5mm
+Varistor, diameter 12mm, width 5.8mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W5mm_P7.5mm
+Varistor, diameter 12mm, width 5mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W6.1mm_P7.5mm
+Varistor, diameter 12mm, width 6.1mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W6.2mm_P7.5mm
+Varistor, diameter 12mm, width 6.2mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W6.3mm_P7.5mm
+Varistor, diameter 12mm, width 6.3mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W6.7mm_P7.5mm
+Varistor, diameter 12mm, width 6.7mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W7.1mm_P7.5mm
+Varistor, diameter 12mm, width 7.1mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W7.5mm_P7.5mm
+Varistor, diameter 12mm, width 7.5mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D12mm_W7.9mm_P7.5mm
+Varistor, diameter 12mm, width 7.9mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W3.9mm_P7.5mm
+Varistor, diameter 15.5mm, width 3.9mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W4.2mm_P7.5mm
+Varistor, diameter 15.5mm, width 4.2mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W4.3mm_P7.5mm
+Varistor, diameter 15.5mm, width 4.3mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W4.4mm_P7.5mm
+Varistor, diameter 15.5mm, width 4.4mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W4.5mm_P7.5mm
+Varistor, diameter 15.5mm, width 4.5mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W4.6mm_P7.5mm
+Varistor, diameter 15.5mm, width 4.6mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W4.7mm_P7.5mm
+Varistor, diameter 15.5mm, width 4.7mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W4.8mm_P7.5mm
+Varistor, diameter 15.5mm, width 4.8mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W4.9mm_P7.5mm
+Varistor, diameter 15.5mm, width 4.9mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W4mm_P7.5mm
+Varistor, diameter 15.5mm, width 4mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W5.2mm_P7.5mm
+Varistor, diameter 15.5mm, width 5.2mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W5.4mm_P7.5mm
+Varistor, diameter 15.5mm, width 5.4mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W5.9mm_P7.5mm
+Varistor, diameter 15.5mm, width 5.9mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W5mm_P7.5mm
+Varistor, diameter 15.5mm, width 5mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W6.1mm_P7.5mm
+Varistor, diameter 15.5mm, width 6.1mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W6.3mm_P7.5mm
+Varistor, diameter 15.5mm, width 6.3mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W6.4mm_P7.5mm
+Varistor, diameter 15.5mm, width 6.4mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W6.8mm_P7.5mm
+Varistor, diameter 15.5mm, width 6.8mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W7.2mm_P7.5mm
+Varistor, diameter 15.5mm, width 7.2mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W7.5mm_P7.5mm
+Varistor, diameter 15.5mm, width 7.5mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W8mm_P7.5mm
+Varistor, diameter 15.5mm, width 8mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D15.5mm_W11mm_P7.5mm
+Varistor, diameter 15.5mm, width 11mm, pitch 7.5mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D16.5mm_W6.7mm_P7.5mm
+Varistor, diameter 16.5mm, width 6.7mm, pitch 5mm, https://katalog.we-online.de/pbs/datasheet/820542711.pdf
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W4.3mm_P10mm
+Varistor, diameter 21.5mm, width 4.3mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W4.4mm_P10mm
+Varistor, diameter 21.5mm, width 4.4mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W4.5mm_P10mm
+Varistor, diameter 21.5mm, width 4.5mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W4.6mm_P10mm
+Varistor, diameter 21.5mm, width 4.6mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W4.7mm_P10mm
+Varistor, diameter 21.5mm, width 4.7mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W4.8mm_P10mm
+Varistor, diameter 21.5mm, width 4.8mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W4.9mm_P10mm
+Varistor, diameter 21.5mm, width 4.9mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W5.1mm_P10mm
+Varistor, diameter 21.5mm, width 5.1mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W5.3mm_P10mm
+Varistor, diameter 21.5mm, width 5.3mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W5.4mm_P10mm
+Varistor, diameter 21.5mm, width 5.4mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W5.6mm_P10mm
+Varistor, diameter 21.5mm, width 5.6mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W5.8mm_P10mm
+Varistor, diameter 21.5mm, width 5.8mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W5mm_P10mm
+Varistor, diameter 21.5mm, width 5mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W6.1mm_P7.5mm
+varistor
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W6.3mm_P10mm
+Varistor, diameter 21.5mm, width 6.3mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W6.5mm_P10mm
+Varistor, diameter 21.5mm, width 6.5mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W6.7mm_P10mm
+Varistor, diameter 21.5mm, width 6.7mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W6.8mm_P10mm
+Varistor, diameter 21.5mm, width 6.8mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W7.1mm_P10mm
+Varistor, diameter 21.5mm, width 7.1mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W7.5mm_P10mm
+Varistor, diameter 21.5mm, width 7.5mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W7.9mm_P10mm
+Varistor, diameter 21.5mm, width 7.9mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W8.4mm_P10mm
+Varistor, diameter 21.5mm, width 8.4mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+Varistor
+RV_Disc_D21.5mm_W11.4mm_P10mm
+Varistor, diameter 21.5mm, width 11.4mm, pitch 10mm
+varistor SIOV
+0
+2
+2
+XC6SLX9-2TQG144C
+TQ144
+<b>TQ144 TQG144</b>
+
+0
+144
+144
diff --git a/MCL86jr/PCBA/fp-lib-table b/MCL86jr/PCBA/fp-lib-table
new file mode 100644
index 0000000..41d1716
--- /dev/null
+++ b/MCL86jr/PCBA/fp-lib-table
@@ -0,0 +1,6 @@
+(fp_lib_table
+  (lib (name XC6SLX9-2TQG144C)(type KiCad)(uri Z:/Ted/projs/KiCAD_Library/XC6SLX9-2TQG144C)(options "")(descr ""))
+  (lib (name SIT8008BI-13-33E-33)(type KiCad)(uri Z:/Ted/projs/KiCAD_Library/SIT8008BI-13-33E-33.333330E)(options "")(descr ""))
+  (lib (name Xilinx_6_Series)(type KiCad)(uri Z:/Ted/projs/KiCAD_Library/Xilinx_6_Series)(options "")(descr ""))
+  (lib (name CY62148GN-45ZSXI)(type KiCad)(uri Z:/Ted/projs/KiCAD_Library/CY62148GN-45ZSXI)(options "")(descr ""))
+)
diff --git a/MCL86jr/PCBA/sym-lib-table b/MCL86jr/PCBA/sym-lib-table
new file mode 100644
index 0000000..201cece
--- /dev/null
+++ b/MCL86jr/PCBA/sym-lib-table
@@ -0,0 +1,5 @@
+(sym_lib_table
+  (lib (name FPGA_Xilinx_Spartan6)(type Legacy)(uri Z:/Ted/projs/KiCAD_Library/Xilinx_6_Series/FPGA_Xilinx_Spartan6.lib)(options "")(descr ""))
+  (lib (name SN74LVC245APW)(type Legacy)(uri Z:/Ted/projs/KiCAD_Library/SN74LVC245APW/SN74LVC245APW.lib)(options "")(descr ""))
+  (lib (name MIC5504-1.2YM5-TR)(type Legacy)(uri Z:/Ted/projs/KiCAD_Library/MIC5504-1.2YM5-TR/MIC5504-1.2YM5-TR.lib)(options "")(descr ""))
+)
diff --git a/README.md b/README.md
index ba5ebc8..2bb6d71 100644
--- a/README.md
+++ b/README.md
@@ -5,6 +5,10 @@ My blog which has some details on these projects: www.MicroCoreLabs.Wordpress.co
 My YouTube Channel with some videos of the stuff in action: www.youtube.com/channel/UC9B3TaEUon-araO2j7tp9jg/videos
 
 
+Boards:
+
+	MCL86jr -  IBMPCjr Accelerator which performs 4X faster than an IBM PC 
+	
 Emulated Processors:
 
 	MCL68 - Motorola 68000 Emulator written in C