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MicroCoreLabs
2020-02-17 20:31:28 -08:00
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92
MCL86/Core/Lattice_XO2_Small_Example/TEST.ASM Normal file
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org 0000 ; Force A86 to locate code at address 0x0000
SETUP: mov si, HELLO_MSG ; Load pointer to the Hello Message
mov SP,00600 ; Locate the stack pointer
mov ax,cs ; Locate the Data Segment to CS
mov ds,ax
; Print the Hello Message
PRINT_MSG: lodsb ; Load a character into AL
cmp al,024 ; Look for the $ which ends the string
je MENU_POLL
mov bl,al
call PRINT_CHAR
jmp PRINT_MSG
MENU_POLL: in al,001 ; Load the UART Status register
and al,001 ; Isolate the RX_BYTE_AVAILABLE bit
jz MENU_POLL
in al,000 ; Retrieve the byte from the UART_RX Buffer
mov bl,al
call PRINT_CHAR ; echo the keypress back to the host
cmp bl,031 ; Check for an ASCII 1
je LEDS_ON
cmp bl,032 ; Check for an ASCII 2
je LEDS_OFF
cmp bl,033 ; Check for an ASCII 3
je PRT_ASCII
cmp bl,034 ; Check for an ASCII 4
je SETUP
jmp MENU_POLL ; Otherwise loop back to beginning
LEDS_ON: mov al,000
out 003, al ; LEDS are located at UART register 0x3
jmp MENU_POLL
LEDS_OFF: mov al,0FF
out 003, al ; LEDS are located at UART register 0x3
jmp MENU_POLL
; Print the ASCII Table
PRT_ASCII: mov bl,021
mov cx,05C
L1: call PRINT_CHAR
inc bl
loop L1
mov bl,13
call PRINT_CHAR
mov bl,10
call PRINT_CHAR
jmp MENU_POLL
; Print Character
PRINT_CHAR: in al,001 ; Load the UART Status register
and al,002 ; Isolate the TX_BUSY bit
jnz PRINT_CHAR
mov al,bl
out 002,al
ret
HELLO_MSG: db 27, "[2J", 27, "[H", 13, 10
db " __ __ _____ _ ___ __ " , 13, 10
db "| \/ |/ ____| | / _ \ / / " , 13, 10
db "| \ / | | | | | (_) |/ /_ " , 13, 10
db "| |\/| | | | | > _ <| '_ \ " , 13, 10
db "| | | | |____| |___| (_) | (_) |" , 13, 10
db "|_| |_|\_____|______\___/ \___/ " , 13, 10, 13, 10,13,10
db "Hello from MicroCore Labs !!!" , 13, 10
db "-----------------------------" , 13, 10, " ", 13, 10
db "This is the MCL86 core running on the Lattice XO2 Breakout Board.", 13, 10
db " ", 13, 10
db " ", 13, 10
db " Press:", 13, 10
db " 1) Turn on LEDs", 13, 10
db " 2) Turn off LEDs", 13, 10
db " 3) Print ASCII characters", 13, 10
db " 4) Refresh screen", 13, 10
db " All other keys will be echoed back", 13, 10
db " ", 13, 10
db "$"

463
MCL86/Core/Lattice_XO2_Small_Example/biu.v Normal file
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//
//
// File Name : biu.v
// Used on :
// Author : Ted Fried, MicroCore Labs
// Creation : 3/2/16
// Code Type : Synthesizable
//
// Description:
// ============
//
// Bus Interface Unit of the MCL86 processor
// ported to the Lattice XO2 Breakout Board.
//
// - All segments fixed to CS to save space.
// - UART fixed to 9600 baud
// - UART jumpers must me installed on the XO2 Breakout Board!
//
//------------------------------------------------------------------------
//
// Modification History:
// =====================
//
// Revision 1.0 3/2/16
// Initial revision
//
//
//------------------------------------------------------------------------
//
// Copyright (c) 2020 Ted Fried
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
//------------------------------------------------------------------------
module biu
(
input CORE_CLK_INT, // Core Signals
input RESET_n,
input UART_RX, // UART
output UART_TX,
output [7:0] LEDS,
input [15:0] EU_BIU_COMMAND, // EU to BIU Signals
input [15:0] EU_BIU_DATAOUT,
input [15:0] EU_REGISTER_R3,
output BIU_DONE, // BIU to EU Signals
output [1:0] BIU_SEGMENT,
output [7:0] PFQ_TOP_BYTE,
output PFQ_EMPTY,
output[15:0] PFQ_ADDR_OUT,
output [15:0] BIU_REGISTER_ES,
output [15:0] BIU_REGISTER_SS,
output [15:0] BIU_REGISTER_CS,
output [15:0] BIU_REGISTER_DS,
output [15:0] BIU_REGISTER_RM,
output [15:0] BIU_REGISTER_REG,
output [15:0] BIU_RETURN_DATA
);
//------------------------------------------------------------------------
// Internal Signals
reg biu_done_int;
reg eu_biu_req_caught;
reg eu_biu_req_d1;
reg uart_cs_n;
reg uart_wr_n;
reg word_cycle;
reg biu_ram_wr;
wire eu_biu_req;
wire eu_prefix_seg;
reg pfq_empty;
reg [15:0] biu_register_cs;
reg [15:0] biu_register_rm;
reg [15:0] biu_register_reg;
reg [15:0] biu_return_data_int;
reg [15:0] eu_register_r3_d;
reg [1:0] io_address;
reg [15:0] pfq_addr_out;
reg [3:0] biu_state;
reg [15:0] pfq_addr_out_d1;
wire [1:0] eu_biu_strobe;
wire [1:0] eu_biu_segment;
wire [4:0] eu_biu_req_code;
wire [1:0] eu_qs_out;
wire [1:0] eu_segment_override_value;
wire [19:0] code_rom_addr;
reg [19:0] memory_address;
wire [7:0] biu_ram_data;
wire [7:0] uart_dataout;
reg [7:0] memory_data;
//------------------------------------------------------------------------
//
// BIU Code/Data RAM. Lattice XO2 2Kx8 DPRAM
//
// Port-A is for EU x86 user code fetching
// Port-B is for BIU data accesses
//
//------------------------------------------------------------------------
assign code_rom_addr = { biu_register_cs[15:0] , 4'h0 } + pfq_addr_out[15:0] ;
biu_ram BIU_2Kx8
(
.ResetA (1'b0),
.ClockEnA (1'b1),
.ClockA (CORE_CLK_INT),
.AddressA (code_rom_addr[10:0]),
.DataInA (8'h0),
.QA (PFQ_TOP_BYTE),
.WrA (1'b0),
.ResetB (1'b0),
.ClockEnB (1'b1),
.ClockB (CORE_CLK_INT),
.AddressB (memory_address[10:0]),
.DataInB (memory_data[7:0]),
.QB (biu_ram_data[7:0]),
.WrB (biu_ram_wr)
);
//------------------------------------------------------------------------
//
// UART - Fixed 9600 baud at 26.6Mhz
//
//------------------------------------------------------------------------
uart BIU_UART (
.CLK (CORE_CLK_INT),
.RESET_n (RESET_n),
.UART_RX (UART_RX),
.UART_TX (UART_TX),
.LEDS (LEDS),
.ADDRESS (io_address[1:0]),
.DATA_IN (EU_BIU_DATAOUT[7:0]),
.DATA_OUT (uart_dataout[7:0]),
.CS_n (uart_cs_n),
.WR_n (uart_wr_n)
);
//------------------------------------------------------------------------
//
// BIU Combinationals
//
//------------------------------------------------------------------------
// Outputs to the EU
//
assign BIU_DONE = biu_done_int;
assign PFQ_EMPTY = pfq_empty;
assign PFQ_ADDR_OUT = pfq_addr_out_d1;
assign BIU_SEGMENT = 'h0;
assign BIU_REGISTER_ES = biu_register_cs;
assign BIU_REGISTER_SS = biu_register_cs;
assign BIU_REGISTER_CS = biu_register_cs;
assign BIU_REGISTER_DS = biu_register_cs;
assign BIU_REGISTER_RM = biu_register_rm;
assign BIU_REGISTER_REG = biu_register_reg;
assign BIU_RETURN_DATA = biu_return_data_int;
// Input signals from the EU requesting BIU processing.
// eu_biu_strobe[1:0] are available for only one clock cycle and cause BIU to take immediate action.
// eu_biu_req stays asserted until the BIU is available to service the request.
//
assign eu_prefix_seg = EU_BIU_COMMAND[14];
assign eu_biu_strobe[1:0] = EU_BIU_COMMAND[13:12]; // 01=opcode fetch 10=clock load 11=load segment register(eu_biu_req_code has the regiter#)
assign eu_biu_segment[1:0] = EU_BIU_COMMAND[11:10];
assign eu_biu_req = EU_BIU_COMMAND[9];
assign eu_biu_req_code = EU_BIU_COMMAND[8:4];
assign eu_qs_out[1:0] = EU_BIU_COMMAND[3:2]; // Updated for every opcode fetch using biu_strobe and Jump request using eu_biu_rq
assign eu_segment_override_value[1:0] = EU_BIU_COMMAND[1:0];
//------------------------------------------------------------------------
//
// BIU Controller
//
//------------------------------------------------------------------------
//
always @(posedge CORE_CLK_INT)
begin : BIU_CONTROLLER
if (RESET_n==1'b0)
begin
eu_register_r3_d <= 'h0;
eu_biu_req_caught <= 'h0;
biu_register_cs <= 16'hFFFF;
biu_register_rm <= 'h0;
biu_register_reg <= 'h0;
pfq_addr_out <= 'h0;
biu_done_int <= 'h0;
eu_biu_req_d1 <= 'h0;
uart_cs_n <= 1'b1;
uart_wr_n <= 1'b1;
biu_return_data_int <= 'h0;
pfq_empty <= 1'b1;
memory_address <= 'h0;
word_cycle <= 'b0;
io_address <= 'h0;
biu_state <= 'h0;
biu_ram_wr <= 1'b0;
end
else
begin
// These signals may be pipelined from zero to one clock.
// They are currently pipelined by one clock.
pfq_addr_out_d1 <= pfq_addr_out;
// Register pipelining in and out of the BIU.
eu_register_r3_d <= EU_REGISTER_R3;
// Capture a bus request from the EU
eu_biu_req_d1 <= eu_biu_req;
if (eu_biu_req_d1==1'b0 && eu_biu_req==1'b1)
begin
eu_biu_req_caught <= 1'b1;
end
else if (biu_done_int==1'b1)
begin
eu_biu_req_caught <= 1'b0;
end
// Strobe from EU to update the segment and addressing registers
// To save logic, all segments will echo the CS.
if (eu_biu_strobe==2'b11)
begin
case (eu_biu_req_code[2:0]) // synthesis parallel_case
3'h2 : biu_register_cs <= EU_BIU_DATAOUT[15:0];
3'h4 : biu_register_rm <= EU_BIU_DATAOUT[15:0];
3'h5 : biu_register_reg <= EU_BIU_DATAOUT[15:0];
default : ;
endcase
end
// Prefetch Queue
// --------------
// Not actually a queue for this implementation.
// Increment the output address of the queue upon EU fetch request strobe.
// Reset the address when the EU asserts the Jump request.
// Data is ready when pfq_empty is a zero to adjust for RAM pipelining.
//---------------------------------------------------------------------------------
if (eu_biu_req_caught==1'b1 && eu_biu_req_code==5'h19)
begin
pfq_addr_out <= eu_register_r3_d; // Update the prefetch queue to the new address.
pfq_empty <= 1'b1;
end
else if (eu_biu_strobe==2'b01)
begin
pfq_addr_out <= pfq_addr_out + 1; // Increment the current IP - Instruction Pointer.
pfq_empty <= 1'b1;
end
else
begin
pfq_empty <= 1'b0; // Give ROM time to respond.
end
// BIU State Machine
biu_state <= biu_state + 1'b1;
case (biu_state) // synthesis parallel_case
8'h00 : begin
io_address[1:0] <= eu_register_r3_d[1:0];
memory_address <= { biu_register_cs[15:0] , 4'h0 } + eu_register_r3_d[15:0];
memory_data <= EU_BIU_DATAOUT[7:0];
if (eu_biu_req_caught==1'b1)
begin
case (eu_biu_req_code) // synthesis parallel_case
// IO Byte Read
8'h08 : begin
uart_cs_n <= 1'b0;
biu_state <= 4'h1;
end
// IO Byte Write
8'h0A : begin
uart_cs_n <= 1'b0;
uart_wr_n <= 1'b0;
biu_state <= 4'h4;
end
// Memory Byte Read
8'h0C : begin
biu_state <= 4'h1;
end
// Memory Word Read
8'h10 : begin
word_cycle <= 1'b1;
biu_state <= 4'h1;
end
// Memory Word Read from Stack Segment
8'h11 : begin
word_cycle <= 1'b1;
biu_state <= 4'h1;
end
// Memory Word Write to Stack Segment
8'h14 : begin
biu_ram_wr <= 1'b1;
word_cycle <= 1'b1;
biu_state <= 4'h4;
end
// Memory Byte Write
8'h0E : begin
biu_ram_wr <= 1'b1;
biu_state <= 4'h4;
end
// Memory Word Write
8'h13 : begin
biu_ram_wr <= 1'b1;
word_cycle <= 1'b1;
biu_state <= 4'h4;
end
// Jump Request
8'h19 : begin
biu_done_int <= 1'b1;
biu_state <= 4'h5;
end
default : ;
endcase
end
else
begin
biu_state <= 4'h0;
end
end
// 8-bit processing
8'h04 :
begin
uart_cs_n <= 1'b1;
uart_wr_n <= 1'b1;
if (uart_cs_n==1'b0)
begin
biu_return_data_int <= { 8'h00 , uart_dataout[7:0] };
end
else
begin
biu_return_data_int <= { 8'h00 , biu_ram_data[7:0] };
end
if (word_cycle==1'b1)
begin
memory_address <= memory_address + 1;
memory_data <= EU_BIU_DATAOUT[15:8];
biu_state <= 4'h7;
end
else
begin
biu_ram_wr <= 1'b0;
biu_done_int <= 1'b1;
end
end
// Complete the cycle
8'h05 :
begin
biu_done_int <= 1'b0;
biu_state <= 4'h0;
end
// 16-bit processing
8'h08 :
begin
biu_return_data_int[15:8] <= biu_ram_data[7:0];
biu_ram_wr <= 1'b0;
biu_done_int <= 1'b1;
word_cycle <= 1'b0;
biu_state <= 4'h5;
end
default : ;
endcase
end
end
endmodule // biu.v

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MCL86/Core/Lattice_XO2_Small_Example/biu_ram.v Normal file
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/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4 */
/* Module Version: 7.5 */
/* C:\lscc\diamond\3.6_x64\ispfpga\bin\nt64\scuba.exe -w -n biu_ram -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type bram -wp 11 -rp 1010 -data_width 8 -rdata_width 8 -num_rows 2048 -cascade -1 -memfile c:/mcl/mcl86/lattice_test_board/user_code.mem -memformat hex -writemodeA NORMAL -writemodeB NORMAL */
/* Fri Mar 04 15:22:02 2016 */
`timescale 1 ns / 1 ps
module biu_ram (DataInA, DataInB, AddressA, AddressB, ClockA, ClockB,
ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB, QA, QB)/* synthesis NGD_DRC_MASK=1 */;
input wire [7:0] DataInA;
input wire [7:0] DataInB;
input wire [10:0] AddressA;
input wire [10:0] AddressB;
input wire ClockA;
input wire ClockB;
input wire ClockEnA;
input wire ClockEnB;
input wire WrA;
input wire WrB;
input wire ResetA;
input wire ResetB;
output wire [7:0] QA;
output wire [7:0] QB;
wire scuba_vhi;
wire scuba_vlo;
VHI scuba_vhi_inst (.Z(scuba_vhi));
defparam biu_ram_0_0_1.INIT_DATA = "STATIC" ;
defparam biu_ram_0_0_1.ASYNC_RESET_RELEASE = "SYNC" ;
defparam biu_ram_0_0_1.INITVAL_1F = "0x0000000000000000000A000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_0_1.INITVAL_0A = "0x000000000000000000000000000000000000000000000000000000000000000000000415A000000A" ;
defparam biu_ram_0_0_1.INITVAL_09 = "0x1B631040451F03500A20198970069516025108F019810000000000A1BC5504630106520CA2012800" ;
defparam biu_ram_0_0_1.INITVAL_08 = "0x00000000AD06454062211060912631008E9040090600000000014D308AC00CCF01C4540122000000" ;
defparam biu_ram_0_0_1.INITVAL_07 = "0x0000A1A645180EF01C2508091000000000015AA306A20014D00000015A000000A1BC4203E2008AFB" ;
defparam biu_ram_0_0_1.INITVAL_06 = "0x02A22004F800A390881C00A8401CF00FC9E1CA200A4F300C8C07A051080312039108AD0000A1BADD" ;
defparam biu_ram_0_0_1.INITVAL_05 = "0x1BADD1BADD1BADD1BADD1BADD1BADD1BAAD022100641C00A2F07E2313A0D1E4601F8C5114DA1B4D0" ;
defparam biu_ram_0_0_1.INITVAL_04 = "0x1FEFF180FF1FECF1FEFF1F8FF1FEFC19EC0018FC15AC013E801809F100CF1FEC019EFF1F80C01800" ;
defparam biu_ram_0_0_1.INITVAL_03 = "0x180CA1A0C01EE0C180F01C0000180C00000180C019ECC018AD000FF01EC013E8018000180C00000C" ;
defparam biu_ram_0_0_1.INITVAL_02 = "0x0180F000C0194D001E0F000C01E0F00000C018FF1FE0F1800F1800C15A001FE00000FF1E0000000F" ;
defparam biu_ram_0_0_1.INITVAL_01 = "0x01EFF1FE001FE001FE0A1B0BB144BB064631545208249160281460711A39046E00100C122311666F" ;
defparam biu_ram_0_0_1.INITVAL_00 = "0x00EB30C00D172441603407602084B00281B000A811404148140284B0128814E441988E118601808E" ;
defparam biu_ram_0_0_1.CSDECODE_B = "0b000" ;
defparam biu_ram_0_0_1.CSDECODE_A = "0b000" ;
defparam biu_ram_0_0_1.WRITEMODE_B = "NORMAL" ;
defparam biu_ram_0_0_1.WRITEMODE_A = "NORMAL" ;
defparam biu_ram_0_0_1.GSR = "ENABLED" ;
defparam biu_ram_0_0_1.RESETMODE = "ASYNC" ;
defparam biu_ram_0_0_1.REGMODE_B = "NOREG" ;
defparam biu_ram_0_0_1.REGMODE_A = "NOREG" ;
defparam biu_ram_0_0_1.DATA_WIDTH_B = 4 ;
defparam biu_ram_0_0_1.DATA_WIDTH_A = 4 ;
DP8KC biu_ram_0_0_1 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(DataInA[3]), .DIA2(DataInA[2]),
.DIA1(DataInA[1]), .DIA0(DataInA[0]), .ADA12(AddressA[10]), .ADA11(AddressA[9]),
.ADA10(AddressA[8]), .ADA9(AddressA[7]), .ADA8(AddressA[6]), .ADA7(AddressA[5]),
.ADA6(AddressA[4]), .ADA5(AddressA[3]), .ADA4(AddressA[2]), .ADA3(AddressA[1]),
.ADA2(AddressA[0]), .ADA1(scuba_vlo), .ADA0(scuba_vlo), .CEA(ClockEnA),
.OCEA(ClockEnA), .CLKA(ClockA), .WEA(WrA), .CSA2(scuba_vlo), .CSA1(scuba_vlo),
.CSA0(scuba_vlo), .RSTA(ResetA), .DIB8(scuba_vlo), .DIB7(scuba_vlo),
.DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo), .DIB3(DataInB[3]),
.DIB2(DataInB[2]), .DIB1(DataInB[1]), .DIB0(DataInB[0]), .ADB12(AddressB[10]),
.ADB11(AddressB[9]), .ADB10(AddressB[8]), .ADB9(AddressB[7]), .ADB8(AddressB[6]),
.ADB7(AddressB[5]), .ADB6(AddressB[4]), .ADB5(AddressB[3]), .ADB4(AddressB[2]),
.ADB3(AddressB[1]), .ADB2(AddressB[0]), .ADB1(scuba_vlo), .ADB0(scuba_vlo),
.CEB(ClockEnB), .OCEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB2(scuba_vlo),
.CSB1(scuba_vlo), .CSB0(scuba_vlo), .RSTB(ResetB), .DOA8(), .DOA7(),
.DOA6(), .DOA5(), .DOA4(), .DOA3(QA[3]), .DOA2(QA[2]), .DOA1(QA[1]),
.DOA0(QA[0]), .DOB8(), .DOB7(), .DOB6(), .DOB5(), .DOB4(), .DOB3(QB[3]),
.DOB2(QB[2]), .DOB1(QB[1]), .DOB0(QB[0]))
/* synthesis MEM_LPC_FILE="biu_ram.lpc" */
/* synthesis MEM_INIT_FILE="user_code.mem" */;
VLO scuba_vlo_inst (.Z(scuba_vlo));
defparam biu_ram_0_1_0.INIT_DATA = "STATIC" ;
defparam biu_ram_0_1_0.ASYNC_RESET_RELEASE = "SYNC" ;
defparam biu_ram_0_1_0.INITVAL_1F = "0x00000000000000F0000E000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biu_ram_0_1_0.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000020002204420" ;
defparam biu_ram_0_1_0.INITVAL_09 = "0x00C660C4660CC6604C620CC6704E760C4760CE620CC42044220442000C660EC720CE670CC5204622" ;
defparam biu_ram_0_1_0.INITVAL_08 = "0x04422044000EE670CC760CC240885404E660EA22064220442204007088420CC620CE750443204422" ;
defparam biu_ram_0_1_0.INITVAL_07 = "0x0442000E440846604C770A4230442204422000370EC7504002044220002204420004670CC420EE66" ;
defparam biu_ram_0_1_0.INITVAL_06 = "0x0CC740464504C660EE6404C6704C620CC660CE720CE6604634088260CE270C4760CA000442000422" ;
defparam biu_ram_0_1_0.INITVAL_05 = "0x04422044220442204422044220442204400044220EC6404C7608C760C8260CE620CC660800000002" ;
defparam biu_ram_0_1_0.INITVAL_04 = "0x04A550A4250AA550AA550AE550AA550EA7204E570007204A220E425044750AA720EA550AE2704E22" ;
defparam biu_ram_0_1_0.INITVAL_03 = "0x0E470004520A427064520642204E27044220E4720E45704E00044520447204A220E4220E47204427" ;
defparam biu_ram_0_1_0.INITVAL_02 = "0x04E22044520E00204422044520A4220442704E550AA220E4220A427000220AA22044550A42204425" ;
defparam biu_ram_0_1_0.INITVAL_01 = "0x04A550AA220AA220AA200085108651180EC11E70040EB1C00E016001C0BF1D8F003C05164BD1C0EF" ;
defparam biu_ram_0_1_0.INITVAL_00 = "0x17AE01C0BD1D8731F01707E810E6F802E3F1003E1B00E1EE0201CFE008ED10072074D8190001606B" ;
defparam biu_ram_0_1_0.CSDECODE_B = "0b000" ;
defparam biu_ram_0_1_0.CSDECODE_A = "0b000" ;
defparam biu_ram_0_1_0.WRITEMODE_B = "NORMAL" ;
defparam biu_ram_0_1_0.WRITEMODE_A = "NORMAL" ;
defparam biu_ram_0_1_0.GSR = "ENABLED" ;
defparam biu_ram_0_1_0.RESETMODE = "ASYNC" ;
defparam biu_ram_0_1_0.REGMODE_B = "NOREG" ;
defparam biu_ram_0_1_0.REGMODE_A = "NOREG" ;
defparam biu_ram_0_1_0.DATA_WIDTH_B = 4 ;
defparam biu_ram_0_1_0.DATA_WIDTH_A = 4 ;
DP8KC biu_ram_0_1_0 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(DataInA[7]), .DIA2(DataInA[6]),
.DIA1(DataInA[5]), .DIA0(DataInA[4]), .ADA12(AddressA[10]), .ADA11(AddressA[9]),
.ADA10(AddressA[8]), .ADA9(AddressA[7]), .ADA8(AddressA[6]), .ADA7(AddressA[5]),
.ADA6(AddressA[4]), .ADA5(AddressA[3]), .ADA4(AddressA[2]), .ADA3(AddressA[1]),
.ADA2(AddressA[0]), .ADA1(scuba_vlo), .ADA0(scuba_vlo), .CEA(ClockEnA),
.OCEA(ClockEnA), .CLKA(ClockA), .WEA(WrA), .CSA2(scuba_vlo), .CSA1(scuba_vlo),
.CSA0(scuba_vlo), .RSTA(ResetA), .DIB8(scuba_vlo), .DIB7(scuba_vlo),
.DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo), .DIB3(DataInB[7]),
.DIB2(DataInB[6]), .DIB1(DataInB[5]), .DIB0(DataInB[4]), .ADB12(AddressB[10]),
.ADB11(AddressB[9]), .ADB10(AddressB[8]), .ADB9(AddressB[7]), .ADB8(AddressB[6]),
.ADB7(AddressB[5]), .ADB6(AddressB[4]), .ADB5(AddressB[3]), .ADB4(AddressB[2]),
.ADB3(AddressB[1]), .ADB2(AddressB[0]), .ADB1(scuba_vlo), .ADB0(scuba_vlo),
.CEB(ClockEnB), .OCEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB2(scuba_vlo),
.CSB1(scuba_vlo), .CSB0(scuba_vlo), .RSTB(ResetB), .DOA8(), .DOA7(),
.DOA6(), .DOA5(), .DOA4(), .DOA3(QA[7]), .DOA2(QA[6]), .DOA1(QA[5]),
.DOA0(QA[4]), .DOB8(), .DOB7(), .DOB6(), .DOB5(), .DOB4(), .DOB3(QB[7]),
.DOB2(QB[6]), .DOB1(QB[5]), .DOB0(QB[4]))
/* synthesis MEM_LPC_FILE="biu_ram.lpc" */
/* synthesis MEM_INIT_FILE="user_code.mem" */;
// exemplar begin
// exemplar attribute biu_ram_0_0_1 MEM_LPC_FILE biu_ram.lpc
// exemplar attribute biu_ram_0_0_1 MEM_INIT_FILE user_code.mem
// exemplar attribute biu_ram_0_1_0 MEM_LPC_FILE biu_ram.lpc
// exemplar attribute biu_ram_0_1_0 MEM_INIT_FILE user_code.mem
// exemplar end
endmodule

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@@ -0,0 +1,41 @@
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D8 E8 49 00 EB F4 E4 01 24 01 74 FA E4 00 8A D8
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74 13 80 FB 34 74 C9 EB DD B0 00 E6 03 EB D7 B0
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73 20 74 68 65 20 4D 43 4C 38 36 20 63 6F 72 65
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20 20 0D 0A 20 20 20 20 20 0D 0A 20 50 72 65 73
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20 20 34 29 20 52 65 66 72 65 73 68 20 73 63 72
65 65 6E 0D 0A 20 20 20 20 20 20 20 20 41 6C 6C
20 6F 74 68 65 72 20 6B 65 79 73 20 77 69 6C 6C
20 62 65 20 65 63 68 6F 65 64 20 62 61 63 6B 0D
0A 20 20 20 20 20 0D 0A 24

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//
//
// File Name : uart.v
// Used on :
// Author : Ted Fried, MicroCore Labs
// Creation : 3/1/16
// Code Type : Synthesizable
//
// Description:
// ============
//
// Fixed 9600 baud rate UART
//
//
//------------------------------------------------------------------------
//
// Copyright (c) 2020 Ted Fried
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
//------------------------------------------------------------------------
module uart
(
input CLK,
input RESET_n,
input UART_RX,
output UART_TX,
output reg [7:0] LEDS,
input [1:0] ADDRESS,
input [7:0] DATA_IN,
output [7:0] DATA_OUT,
input CS_n,
input WR_n
);
//------------------------------------------------------------------------
// Internal Signals
reg RX_STATE;
reg uart_rx_d;
reg uart_rx_d1;
reg uart_rx_d2;
reg bit_clk;
reg bit_clk_d;
reg rx_havebyte;
reg host_tx_go;
reg host_tx_go_d;
reg rx_byte_available;
reg [7:0] tx_byte;
reg [10:0] tx_count;
reg [10:0] tx_shift_out;
reg [8:0] rx_byte;
reg [11:0] rx_count;
reg [4:0] rx_bits;
reg [11:0] prescaler;
wire [1:0] uart_status;
//------------------------------------------------------------------------
//
// Combinationals
//
//------------------------------------------------------------------------
assign UART_TX = tx_shift_out[0];
assign DATA_OUT = (ADDRESS==2'h0) ? rx_byte[7:0] :
(ADDRESS==2'h1) ? uart_status :
8'hEE;
assign uart_status[1] = (tx_count[9:0]==10'b0000000000) ? 1'b0 : 1'b1; // 1=TX_BUSY
assign uart_status[0] = rx_byte_available;
//------------------------------------------------------------------------
//
// UART Controller
//
//------------------------------------------------------------------------
always @(posedge CLK)
begin : STATE_MACHINE
if (RESET_n==1'b0)
begin
RX_STATE <= 'h0;
uart_rx_d <= 'h0;
uart_rx_d1 <= 'h0;
uart_rx_d2 <= 'h0;
bit_clk <= 'h0;
bit_clk_d <= 'h0;
prescaler <= 'h0;
rx_havebyte <= 'h0;
rx_count <= 'h0;
rx_byte <= 9'b1111_1111_1;
tx_shift_out <= 10'b1111111111;
tx_count <= 'h0;
host_tx_go <= 'h0;
host_tx_go_d <= 'h0;
tx_byte <= 8'hFF;
rx_byte_available <= 'h0;
rx_bits <= 'h0;
end
else
begin
//------------------------------------------------------------------------
//
// Host interface and prescaler
//
//------------------------------------------------------------------------
// Host
// Address: 0x0 - RO - RX_BYTE - reading clears the RX_HAS_BYTE bit
// 0x1 - RO - UART status [1]=TX_BUSY [0]=RX_HAS_BYTE
// 0x2 - WO - TX Byte - Automatically initiates the TX
if (CS_n==1'b0 && WR_n==1'b0 && ADDRESS==2'h2)
begin
host_tx_go <= 1'b1;
tx_byte <= DATA_IN;
end
else
begin
host_tx_go <= 1'b0;
end
if (rx_havebyte==1'b1)
begin
rx_byte_available <= 1'b1;
end
else if (CS_n==1'b0 && ADDRESS==2'h0)
begin
rx_byte_available <= 1'b0;
end
if (CS_n==1'b0 && WR_n==1'b0 && ADDRESS==2'h3)
begin
LEDS <= DATA_IN;
end
if (prescaler[11:0]==12'hAD2)
begin
bit_clk <= ~ bit_clk;
prescaler <= 'h0;
end
else
begin
prescaler <= prescaler + 1;
end
bit_clk_d <= bit_clk;
//------------------------------------------------------------------------
//
// RX Controller
//
//------------------------------------------------------------------------
uart_rx_d <= UART_RX;
uart_rx_d1 <= uart_rx_d;
uart_rx_d2 <= uart_rx_d1;
case (RX_STATE) // synthesis parallel_case
1'h0 : begin
// Debounce signals
rx_havebyte <= 1'b0;
rx_bits <= 'h0;
// Look for start bit
if (uart_rx_d2==1'b0)
begin
rx_count <= rx_count +1;
end
// Count half-way into the start bit
if (rx_count==12'h569)
begin
rx_count <= 'h0;
rx_byte <= 9'b1_11111111;
RX_STATE <= 1'h1;
end
end
1'h1 : begin
rx_count <= rx_count + 1;
// Count complete bit-times
if (rx_count==12'hAD2)
begin
rx_byte[8:0] <= { uart_rx_d2 , rx_byte[8:1] };
rx_bits <= rx_bits + 1'b1;
rx_count <= 'h0;
end
// Complete byte has been shifted in
if (rx_bits==4'h9)
begin
rx_havebyte <= 1'b1;
RX_STATE <= 1'h0;
end
end
default : ;
endcase
//------------------------------------------------------------------------
//
// TX Controller
//
//------------------------------------------------------------------------
// Load transmit shifter on rising edge of host request
host_tx_go_d <= host_tx_go;
if (host_tx_go_d==1'b0 && host_tx_go==1'b1)
begin
tx_shift_out <= { 1'b1 , tx_byte , 1'b0 , 1'b1 };
tx_count <= 11'b11111111111;
end
// Otherwise shift out bits at each bit clock.
// When tx_count is all zeros tye byte has been sent.
else
begin
if (bit_clk_d != bit_clk)
begin
tx_shift_out[10:0] <= { 1'b1 , tx_shift_out[10:1] };
tx_count[10:0] <= { 1'b0 , tx_count[10:1] };
end
end
end
end
endmodule

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//
//
// File Name : XO2x86.v
// Used on :
// Author : Ted Fried, MicroCore Labs
// Creation : 2/29/2016
// Code Type : Synthesizable
//
// Description:
// ============
//
// MCL86 ported to the Lattice XO2-7000 Breakout Board - Top Level
//
//------------------------------------------------------------------------
//
// Modification History:
// =====================
//
// Revision 1.0 3/3/15
// Initial revision
//
//
//------------------------------------------------------------------------
//
// Copyright (c) 2020 Ted Fried
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
//------------------------------------------------------------------------
`timescale 1ns/100ps
module xo2x86
(
input RESET_n ,
input UART_RX,
output UART_TX,
output [7:0] LEDS
);
//------------------------------------------------------------------------
// Internal Signals
wire clk_int;
wire t_eu_prefix_lock;
wire t_eu_flag_i;
wire t_pfq_empty;
wire t_biu_done;
wire [15:0] t_eu_biu_command;
wire [15:0] t_eu_biu_dataout;
wire [15:0] t_eu_register_r3;
wire [7:0] t_pfq_top_byte;
wire [15:0] t_pfq_addr_out;
wire [15:0] t_biu_register_es;
wire [15:0] t_biu_register_ss;
wire [15:0] t_biu_register_cs;
wire [15:0] t_biu_register_ds;
wire [15:0] t_biu_register_rm;
wire [15:0] t_biu_register_reg;
wire [15:0] t_biu_return_data;
wire [1:0] t_biu_segment;
//------------------------------------------------------------------------
// GSR - Global Set/Reset for Lattice XO2
// POR - Power On reset for Lattice XO2
// OSCH - Internal clock oscillator for Lattice XO2
//------------------------------------------------------------------------
GSR GSR_INST (
.GSR (RESET_n) );
PUR PUR_INST (
.PUR (RESET_n) );
defparam OSCILLATOR_INST.NOM_FREQ = "26.60";
OSCH OSCILLATOR_INST
(
.STDBY (1'b0),
.OSC (clk_int),
.SEDSTDBY ()
);
//------------------------------------------------------------------------
// BIU Core
//------------------------------------------------------------------------
biu BIU_CORE
(
.CORE_CLK_INT (clk_int),
.RESET_n (RESET_n),
.UART_RX (UART_RX),
.UART_TX (UART_TX),
.LEDS (LEDS),
.EU_BIU_COMMAND (t_eu_biu_command),
.EU_BIU_DATAOUT (t_eu_biu_dataout),
.EU_REGISTER_R3 (t_eu_register_r3),
.BIU_DONE (t_biu_done),
.BIU_SEGMENT (t_biu_segment),
.PFQ_TOP_BYTE (t_pfq_top_byte),
.PFQ_EMPTY (t_pfq_empty),
.PFQ_ADDR_OUT (t_pfq_addr_out),
.BIU_REGISTER_ES (t_biu_register_es),
.BIU_REGISTER_SS (t_biu_register_ss),
.BIU_REGISTER_CS (t_biu_register_cs),
.BIU_REGISTER_DS (t_biu_register_ds),
.BIU_REGISTER_RM (t_biu_register_rm),
.BIU_REGISTER_REG (t_biu_register_reg),
.BIU_RETURN_DATA (t_biu_return_data)
);
//------------------------------------------------------------------------
// EU Core
//------------------------------------------------------------------------
mcl86_eu_core EU_CORE
(
.CORE_CLK_INT (clk_int),
.RESET_n (RESET_n),
.TEST_N_INT (1'b1),
.EU_BIU_COMMAND (t_eu_biu_command),
.EU_BIU_DATAOUT (t_eu_biu_dataout),
.EU_REGISTER_R3 (t_eu_register_r3),
.EU_PREFIX_LOCK (t_eu_prefix_lock),
.EU_FLAG_I (t_eu_flag_i),
.BIU_DONE (t_biu_done),
.BIU_CLK_COUNTER_ZERO (1'b1),
.BIU_NMI_CAUGHT (1'b0),
.BIU_NMI_DEBOUNCE (),
.BIU_INTR (1'b0),
.PFQ_TOP_BYTE (t_pfq_top_byte),
.PFQ_EMPTY (t_pfq_empty),
.PFQ_ADDR_OUT (t_pfq_addr_out),
.BIU_REGISTER_ES (t_biu_register_es),
.BIU_REGISTER_SS (t_biu_register_ss),
.BIU_REGISTER_CS (t_biu_register_cs),
.BIU_REGISTER_DS (t_biu_register_ds),
.BIU_REGISTER_RM (t_biu_register_rm),
.BIU_REGISTER_REG (t_biu_register_reg),
.BIU_RETURN_DATA (t_biu_return_data)
);
endmodule
//------------------------------------------------------------------------