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MicroCoreLabs
2020-01-25 11:42:25 -08:00
parent 50099361f5
commit e4bde7a1f9
17 changed files with 3354 additions and 2405 deletions
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118
MCL51/Core/MCL51_top.v
View File

@@ -21,20 +21,42 @@
//
//
//------------------------------------------------------------------------
//
// Copyright (c) 2020 Ted Fried
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
//------------------------------------------------------------------------
module MCL51_top
(
input CLK,
input RESET_n,
input CLK,
input RESET_n,
input UART_RX,
output UART_TX,
output SPEAKER
input UART_RX,
output UART_TX,
output SPEAKER
);
//------------------------------------------------------------------------
// Internal Signals
@@ -58,57 +80,57 @@ wire [7:0] t_biu_return_data;
assign clk_int = CLK;
assign t_rst_n_int = (t_biu_reset_out==1'b0 && RESET_n==1'b1) ? 1'b1 : 1'b0;
//------------------------------------------------------------------------
// EU Core
//------------------------------------------------------------------------
eu EU_CORE
eu EU_CORE
(
.CORE_CLK (clk_int),
.RST_n (t_rst_n_int),
.EU_BIU_STROBE (t_eu_biu_strobe),
.EU_BIU_DATAOUT (t_eu_biu_dataout),
.EU_REGISTER_R3 (t_eu_register_r3),
.EU_REGISTER_IP (t_eu_register_ip),
.BIU_SFR_ACC (t_biu_sfr_acc),
.BIU_SFR_DPTR (t_biu_sfr_dptr),
.BIU_SFR_SP (t_biu_sfr_sp),
.BIU_SFR_PSW (t_biu_sfr_psw),
.BIU_RETURN_DATA (t_biu_return_data),
.BIU_INTERRUPT (t_biu_interrupt)
.CORE_CLK (clk_int),
.RST_n (t_rst_n_int),
.EU_BIU_STROBE (t_eu_biu_strobe),
.EU_BIU_DATAOUT (t_eu_biu_dataout),
.EU_REGISTER_R3 (t_eu_register_r3),
.EU_REGISTER_IP (t_eu_register_ip),
.BIU_SFR_ACC (t_biu_sfr_acc),
.BIU_SFR_DPTR (t_biu_sfr_dptr),
.BIU_SFR_SP (t_biu_sfr_sp),
.BIU_SFR_PSW (t_biu_sfr_psw),
.BIU_RETURN_DATA (t_biu_return_data),
.BIU_INTERRUPT (t_biu_interrupt)
);
);
//------------------------------------------------------------------------
// BIU Core
//------------------------------------------------------------------------
biu BIU_CORE
biu BIU_CORE
(
.CORE_CLK (clk_int),
.RST_n (t_rst_n_int),
.UART_RX (UART_RX),
.UART_TX (UART_TX),
.SPEAKER (SPEAKER),
.EU_BIU_STROBE (t_eu_biu_strobe),
.EU_BIU_DATAOUT (t_eu_biu_dataout),
.EU_REGISTER_R3 (t_eu_register_r3),
.EU_REGISTER_IP (t_eu_register_ip),
.BIU_SFR_ACC (t_biu_sfr_acc),
.BIU_SFR_DPTR (t_biu_sfr_dptr),
.BIU_SFR_SP (t_biu_sfr_sp),
.BIU_SFR_PSW (t_biu_sfr_psw),
.BIU_RETURN_DATA (t_biu_return_data),
.BIU_INTERRUPT (t_biu_interrupt),
.RESET_OUT (t_biu_reset_out)
);
.CORE_CLK (clk_int),
.RST_n (t_rst_n_int),
.UART_RX (UART_RX),
.UART_TX (UART_TX),
.SPEAKER (SPEAKER),
.EU_BIU_STROBE (t_eu_biu_strobe),
.EU_BIU_DATAOUT (t_eu_biu_dataout),
.EU_REGISTER_R3 (t_eu_register_r3),
.EU_REGISTER_IP (t_eu_register_ip),
.BIU_SFR_ACC (t_biu_sfr_acc),
.BIU_SFR_DPTR (t_biu_sfr_dptr),
.BIU_SFR_SP (t_biu_sfr_sp),
.BIU_SFR_PSW (t_biu_sfr_psw),
.BIU_RETURN_DATA (t_biu_return_data),
.BIU_INTERRUPT (t_biu_interrupt),
.RESET_OUT (t_biu_reset_out)
);

249
MCL51/Core/mdio.vec → MCL51/Core/Microcode_MCL51.txt
View File

@@ -1,111 +1,144 @@
#
# Microcode for the MCL51
#
# ------------------------------------------------------------------------
#
# Copyright (C) 2019 by Ted Fried info@MicroCoreLabs.com
#
# Permission to use, copy, modify, and distribute this software and its
# documentation for any purpose and without fee is hereby granted, provided
# that the above copyright notice appear in all copies and that both that
# copyright notice and this permission notice appear in supporting documentation.
# This software is provided "as is" without express or implied warranty.
#
# ------------------------------------------------------------------------
#
#
#
# [15:8]=Internal Flags and system signals [7:0]=Actual PSW register from the BIU
# ** Flags must be written to the PSW through the BIU - User could access PSW by address at any time
#
# assign eu_flags_r[15] = eu_add_carry
# assign eu_flags_r[14] = eu_add_aux_carry
# assign eu_flags_r[13] = eu_add_carry16
# assign eu_flags_r[12] =
# assign eu_flags_r[11] =
# assign eu_flags_r[10] = eu_add_overflow
# assign eu_flags_r[9] =
# assign eu_flags_r[8] = BIU_INTERRUPT
#
# assign eu_flags_r[7] = BIU_SFR_PSW[7] // C
# assign eu_flags_r[6] = BIU_SFR_PSW[6] // AC
# assign eu_flags_r[5] = BIU_SFR_PSW[5] // F0
# assign eu_flags_r[4] = BIU_SFR_PSW[4] // RS1
# assign eu_flags_r[3] = BIU_SFR_PSW[3] // RS0
# assign eu_flags_r[2] = BIU_SFR_PSW[2] // Overflow
# assign eu_flags_r[1] = BIU_INTR // Interrupt from the BIU
# assign eu_flags_r[0] = BIU_SFR_PSW[0] // Parity
#
#
#
# BIU Strobes
# -------------
# // Signals from the EU to request BIU processing
# // Only asserted for one clock cycle and cause BIU to take immediate action.
# //
#
# eu_biu_address_code = eu_biu_strobe[6:4];
# 0=Program code space
# 1=Direct Data space
# 2=Indirect Data space
# 3=SFR or Bit address?
#
# eu_biu_strobe = eu_biu_strobe[2:0];
# 0=idle
# 1=write BIU_DATAOUT to address in r3
# 2=read address in r3 into BIU_RETURN_DATA
# 3=Global Interrupt Disable
# 4=Global Interrupt Enable
#
#
# EU Registers
# --------------
#
# Destination Operand0 Operand1
# -----------------------------------------------------------------------------------------------
# 0 r0 0 r0 0 r0
# 1 r1 1 r1 1 r1
# 2 r2 2 r2 2 r2
# 3 r3 3 r3 3 r3
# 4 BIU_Dataout 4 00,BIU_Return_Data 4 00,SP
# 5 Dummy 5 {eu_flags_r} 5
# 6 BIU_Strobe 6 00,ACC 6 DPTR
# 7 IP 7 IP 7 Opcode Immediate[15:0]
# 8+ 16'h0000
#
#
# EU Opcodes
# -----------
# 0x1 - JUMP
# ----------------
# Bits[31:28] : 0x1
# Bits[27:24] : CALL 1=Push next IP address to call stack
# Bits[22:20] : Jump Source:
# 0x0=Immediate[12:0]
# 0x1={4'h0 & code_byte} -- For initial Jump
# 0x2={immediate[xx:0] & code_byte[3:0]} -- Addressing modes
# 0x3=Return to CALL stored IP address -- CALL Return
# 0x4={ 7'h00 , BIU_RETURN_DATA[2:0] } -- Bit Mask decoding table
#
#
# Bits[19:16] : Jump Condition:
# 0x0=Unconditional
# 0x1=Last_ALU_Result!=0
# 0x2=Last_ALU_Result==0
# Bits[12:0] : Immediate[12:0]
#
#
# 0x2 - ADD
# 0x3 - XOR
# 0x4 - OR
# 0x5 - AND
# 0x6 - Byte swap eu_operand0
# 0x7 - Shift Right based on type: { immediate[0] , eu_operand0[7:0] }
# Immedaite = 0 = Eight bit - shift in op0[0],
# 1 = Eight bit - shift in PSW_carry
# 2 = Sixteen bit - shift in eu_add_carry16
#
//
//
// File Name : Microcode_MCL51.txt
// Used on : MCL51
// Author : Ted Fried, MicroCore Labs
// Creation : 1/25/2020
// Code Type : Microcode
//
// Description:
// ============
//
// Microcode for the MCL51
//
//------------------------------------------------------------------------
//
// Modification History:
// =====================
//
// Revision 1.0 1/25/2020
// Initial revision
//
//
//------------------------------------------------------------------------
//
// Copyright (c) 2020 Ted Fried
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
//------------------------------------------------------------------------
// Microcode and microsequencer notes:
//
[15:8]=Internal Flags and system signals [7:0]=Actual PSW register from the BIU
** Flags must be written to the PSW through the BIU - User could access PSW by address at any time
assign eu_flags_r[15] = eu_add_carry
assign eu_flags_r[14] = eu_add_aux_carry
assign eu_flags_r[13] = eu_add_carry16
assign eu_flags_r[12] =
assign eu_flags_r[11] =
assign eu_flags_r[10] = eu_add_overflow
assign eu_flags_r[9] =
assign eu_flags_r[8] = BIU_INTERRUPT
assign eu_flags_r[7] = BIU_SFR_PSW[7] // C
assign eu_flags_r[6] = BIU_SFR_PSW[6] // AC
assign eu_flags_r[5] = BIU_SFR_PSW[5] // F0
assign eu_flags_r[4] = BIU_SFR_PSW[4] // RS1
assign eu_flags_r[3] = BIU_SFR_PSW[3] // RS0
assign eu_flags_r[2] = BIU_SFR_PSW[2] // Overflow
assign eu_flags_r[1] = BIU_INTR // Interrupt from the BIU
assign eu_flags_r[0] = BIU_SFR_PSW[0] // Parity
BIU Strobes
-------------
// Signals from the EU to request BIU processing
// Only asserted for one clock cycle and cause BIU to take immediate action.
//
eu_biu_address_code = eu_biu_strobe[6:4];
0=Program code space
1=Direct Data space
2=Indirect Data space
3=SFR or Bit address?
eu_biu_strobe = eu_biu_strobe[2:0];
0=idle
1=write BIU_DATAOUT to address in r3
2=read address in r3 into BIU_RETURN_DATA
3=Global Interrupt Disable
4=Global Interrupt Enable
EU Registers
--------------
Destination Operand0 Operand1
-----------------------------------------------------------------------------------------------
0 r0 0 r0 0 r0
1 r1 1 r1 1 r1
2 r2 2 r2 2 r2
3 r3 3 r3 3 r3
4 BIU_Dataout 4 00,BIU_Return_Data 4 00,SP
5 Dummy 5 {eu_flags_r} 5
6 BIU_Strobe 6 00,ACC 6 DPTR
7 IP 7 IP 7 Opcode Immediate[15:0]
8+ 16'h0000
EU Opcodes
-----------
0x1 - JUMP
----------------
Bits[31:28] : 0x1
Bits[27:24] : CALL 1=Push next IP address to call stack
Bits[22:20] : Jump Source:
0x0=Immediate[12:0]
0x1={4'h0 & code_byte} -- For initial Jump
0x2={immediate[xx:0] & code_byte[3:0]} -- Addressing modes
0x3=Return to CALL stored IP address -- CALL Return
0x4={ 7'h00 , BIU_RETURN_DATA[2:0] } -- Bit Mask decoding table
Bits[19:16] : Jump Condition:
0x0=Unconditional
0x1=Last_ALU_Result!=0
0x2=Last_ALU_Result==0
Bits[12:0] : Immediate[12:0]
0x2 - ADD
0x3 - XOR
0x4 - OR
0x5 - AND
0x6 - Byte swap eu_operand0
0x7 - Shift Right based on type: { immediate[0] , eu_operand0[7:0] }
Immedaite = 0 = Eight bit - shift in op0[0],
1 = Eight bit - shift in PSW_carry
2 = Sixteen bit - shift in eu_add_carry16
# Reset the CPU
p 00 00000 00001 0001
p 01 00000 00001 0000

417
MCL51/Core/biu.v
View File

@@ -2,7 +2,7 @@
//
// File Name : biu.v
// Used on :
// Author : MicroCore Labs
// Author : Ted Fried, MicroCore Labs
// Creation : 3/13/16
// Code Type : Synthesizable
//
@@ -22,38 +22,59 @@
//
//
//------------------------------------------------------------------------
//
// Copyright (c) 2020 Ted Fried
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
//------------------------------------------------------------------------
module biu
(
input CORE_CLK, // Core Signals
input RST_n,
input CORE_CLK, // Core Signals
input RST_n,
input UART_RX, // Peripheral IOs
output UART_TX,
output SPEAKER,
input UART_RX, // Peripheral IOs
output UART_TX,
output SPEAKER,
input [7:0] EU_BIU_STROBE, // EU to BIU Signals
input [7:0] EU_BIU_DATAOUT,
input [15:0] EU_REGISTER_R3,
input [15:0] EU_REGISTER_IP,
output [7:0] BIU_SFR_ACC, // BIU to EU Signals
output [15:0] BIU_SFR_DPTR,
output [7:0] BIU_SFR_SP,
output [7:0] BIU_SFR_PSW,
output [7:0] BIU_RETURN_DATA,
output BIU_INTERRUPT,
input [7:0] EU_BIU_STROBE, // EU to BIU Signals
input [7:0] EU_BIU_DATAOUT,
input [15:0] EU_REGISTER_R3,
input [15:0] EU_REGISTER_IP,
output [7:0] BIU_SFR_ACC, // BIU to EU Signals
output [15:0] BIU_SFR_DPTR,
output [7:0] BIU_SFR_SP,
output [7:0] BIU_SFR_PSW,
output [7:0] BIU_RETURN_DATA,
output BIU_INTERRUPT,
output RESET_OUT
output RESET_OUT
);
//------------------------------------------------------------------------
// Internal Signals
@@ -64,7 +85,7 @@ wire biu_int2;
wire biu_int3;
wire biu_sfr_select;
wire acc_parity;
wire biu_timer_wr_strobe;
wire biu_timer_wr_strobe;
wire biu_uart_rd_strobe;
wire biu_uart_wr_strobe;
wire loader_wr;
@@ -85,8 +106,8 @@ wire [7:0] biu_program_data;
wire [2:0] eu_biu_strobe_mode;
wire [2:0] eu_biu_strobe_int;
wire [7:0] biu_ram_dataout;
wire [7:0] biu_timer_dataout;
wire [7:0] biu_uart_dataout;
wire [7:0] biu_timer_dataout;
wire [7:0] biu_uart_dataout;
wire [15:0] loader_addr_int;
wire [7:0] loader_data_int;
@@ -96,56 +117,56 @@ wire [7:0] loader_data_int;
//
// User Program ROM. 4Kx8
//
//------------------------------------------------------------------------
//------------------------------------------------------------------------
/* Program ROM without interface to the UART Loader
biu_rom BIU_4Kx8
biu_rom BIU_4Kx8
(
.Reset (1'b0),
.OutClockEn (1'b1),
.OutClock (CORE_CLK),
.Address (EU_REGISTER_IP[11:0]),
.Q (biu_program_data)
.Reset (1'b0),
.OutClockEn (1'b1),
.OutClock (CORE_CLK),
.Address (EU_REGISTER_IP[11:0]),
.Q (biu_program_data)
);
*/
// For Lattice XO2 Series FPGAs
biu_rom_dp BIU_4Kx8
biu_rom_dp BIU_4Kx8
(
.ResetA (1'b0),
.ClockEnA (1'b1),
.ClockA (CORE_CLK),
.WrA (1'b0),
.AddressA (EU_REGISTER_IP[11:0]),
.DataInA (8'h00),
.QA (biu_program_data),
.ResetA (1'b0),
.ClockEnA (1'b1),
.ClockA (CORE_CLK),
.WrA (1'b0),
.AddressA (EU_REGISTER_IP[11:0]),
.DataInA (8'h00),
.QA (biu_program_data),
.ResetB (1'b0),
.ClockEnB (1'b1),
.ClockB (CORE_CLK),
.WrB (loader_wr),
.AddressB (loader_addr_int[11:0]),
.DataInB (loader_data_int),
.QB ( )
.ResetB (1'b0),
.ClockEnB (1'b1),
.ClockB (CORE_CLK),
.WrB (loader_wr),
.AddressB (loader_addr_int[11:0]),
.DataInB (loader_data_int),
.QB ( )
);
//------------------------------------------------------------------------
//
// User Data RAM. 512x8
//
//------------------------------------------------------------------------
//------------------------------------------------------------------------
// For Lattice XO2 Series FPGAs
biu_ram BIU_512x8
biu_ram BIU_512x8
(
.Reset (1'b0),
.ClockEn (1'b1),
.Clock (CORE_CLK),
.Address (eu_register_r3_d1[8:0]),
.Data (EU_BIU_DATAOUT),
.Q (biu_ram_dataout),
.WE (biu_ram_wr)
.Reset (1'b0),
.ClockEn (1'b1),
.Clock (CORE_CLK),
.Address (eu_register_r3_d1[8:0]),
.Data (EU_BIU_DATAOUT),
.Q (biu_ram_dataout),
.WE (biu_ram_wr)
);
//------------------------------------------------------------------------
@@ -160,12 +181,12 @@ biu_ram BIU_512x8
assign BIU_SFR_ACC = biu_sfr_acc_int;
assign BIU_SFR_DPTR = { biu_sfr_dph_int , biu_sfr_dpl_int };
assign BIU_SFR_SP = biu_sfr_sp_int;
assign BIU_SFR_PSW = { biu_sfr_psw_int[7:1] , acc_parity };
assign BIU_SFR_PSW = { biu_sfr_psw_int[7:1] , acc_parity };
assign BIU_RETURN_DATA = (eu_biu_strobe_mode==2'h0) ? biu_program_data :
(biu_sfr_select==1'b1) ? biu_sfr_dataout :
biu_ram_dataout ;
assign BIU_RETURN_DATA = (eu_biu_strobe_mode==2'h0) ? biu_program_data :
(biu_sfr_select==1'b1) ? biu_sfr_dataout :
biu_ram_dataout ;
// Parity for the Accumulator
@@ -174,8 +195,8 @@ assign acc_parity = (biu_sfr_acc_int[0]^biu_sfr_acc_int[1]^biu_sfr_acc_int[2]^bi
// EU strobes to request BIU processing.
assign eu_biu_strobe_mode[2:0] = EU_BIU_STROBE[6:4];
assign eu_biu_strobe_int[2:0] = EU_BIU_STROBE[2:0];
@@ -183,7 +204,7 @@ assign eu_biu_strobe_int[2:0] = EU_BIU_STROBE[2:0];
// Select the SFR range if the address is 0x0080 to 0x00FF and addressing mode is Direct
assign biu_sfr_select = ( eu_register_r3_d1[15:7]==9'b0000_0000_1 && eu_biu_strobe_mode[1:0]==3'h1) ? 1'b1 : 1'b0;
assign biu_sfr_select = ( eu_register_r3_d1[15:7]==9'b0000_0000_1 && eu_biu_strobe_mode[1:0]==3'h1) ? 1'b1 : 1'b0;
// Decode the write enable to the RAM block
@@ -191,41 +212,41 @@ assign biu_ram_wr = (biu_sfr_select==1'b0 && eu_biu_strobe_int==3'h1) ? 1'b1 : 1
// Mux the SFR data outputs
assign biu_sfr_dataout = (eu_register_r3_d1[7:0]==8'h81) ? biu_sfr_sp_int :
(eu_register_r3_d1[7:0]==8'h82) ? biu_sfr_dpl_int :
(eu_register_r3_d1[7:0]==8'h83) ? biu_sfr_dph_int :
(eu_register_r3_d1[7:0]==8'hA8) ? biu_sfr_ie_int :
(eu_register_r3_d1[7:0]==8'hA9) ? biu_sfr_is_int :
assign biu_sfr_dataout = (eu_register_r3_d1[7:0]==8'h81) ? biu_sfr_sp_int :
(eu_register_r3_d1[7:0]==8'h82) ? biu_sfr_dpl_int :
(eu_register_r3_d1[7:0]==8'h83) ? biu_sfr_dph_int :
(eu_register_r3_d1[7:0]==8'hA8) ? biu_sfr_ie_int :
(eu_register_r3_d1[7:0]==8'hA9) ? biu_sfr_is_int :
(eu_register_r3_d1[7:0]==8'hC0) ? biu_sfr_pxy_din :
(eu_register_r3_d1[7:0]==8'hD0) ? biu_sfr_psw_int :
(eu_register_r3_d1[7:0]==8'hD0) ? biu_sfr_psw_int :
(eu_register_r3_d1[7:0]==8'hE0) ? biu_sfr_acc_int :
(eu_register_r3_d1[7:0]==8'hF0) ? biu_sfr_b_int :
8'hEE ;
8'hEE ;
// Simple fixed priority interrupt controller
// biu_sfr_ie_int[7] is the global_intr_enable
// biu_sfr_is_int[3:0] contains the interrupt source
// Interrupt 2 = Timer Interrupt Vector at address 0x4
// 3 = UART-RX Interrupt Vector at address 0x6
// Interrupt 2 = Timer Interrupt Vector at address 0x4
// 3 = UART-RX Interrupt Vector at address 0x6
//
assign BIU_INTERRUPT = (core_interrupt_disable==1'b0 && biu_sfr_ie_int[7]==1'b1 && biu_int2==1'b1) ? 1'b1 :
(core_interrupt_disable==1'b0 && biu_sfr_ie_int[7]==1'b1 && biu_int3==1'b1) ? 1'b1 : 1'b0;
// (core_interrupt_disable==1'b0 && biu_sfr_ie_int[7]==1'b1 && biu_int4==1'b1) ? 1'b1 :
// 1'b0 ;
// 1'b0 ;
assign biu_sfr_is_int[7:4] = 4'h0;
assign biu_sfr_is_int[3:0] = (biu_int2==1'b1) ? 4'h2 :
(biu_int3==1'b1) ? 4'h3 : 4'hF;
// 4'h4 ;
// 4'h4 ;
//------------------------------------------------------------------------
//
// BIU Controller
@@ -238,89 +259,89 @@ begin : BIU_CONTROLLER
if (RST_n==1'b0)
begin
biu_sfr_dpl_int <= 'h0;
biu_sfr_dph_int <= 'h0;
biu_sfr_ie_int <= 'h0;
biu_sfr_psw_int <= 'h0;
biu_sfr_acc_int <= 'h0;
biu_sfr_b_int <= 8'h00;
biu_sfr_sp_int <= 'h07;
eu_register_r3_d1 <= 'h0;
biu_pxy_rd <= 'h0;
biu_pxy_wr <= 'h0;
biu_sfr_pxy_addr <= 'h0;
biu_sfr_pxy_dout <= 'h0;
core_interrupt_disable <= 'h0;
biu_sfr_dpl_int <= 'h0;
biu_sfr_dph_int <= 'h0;
biu_sfr_ie_int <= 'h0;
biu_sfr_psw_int <= 'h0;
biu_sfr_acc_int <= 'h0;
biu_sfr_b_int <= 8'h00;
biu_sfr_sp_int <= 'h07;
eu_register_r3_d1 <= 'h0;
biu_pxy_rd <= 'h0;
biu_pxy_wr <= 'h0;
biu_sfr_pxy_addr <= 'h0;
biu_sfr_pxy_dout <= 'h0;
core_interrupt_disable <= 'h0;
end
else
begin
eu_register_r3_d1 <= EU_REGISTER_R3;
if (eu_biu_strobe_int==3'h3)
begin
core_interrupt_disable <= 1'b1;
end
if (eu_biu_strobe_int==3'h4)
begin
core_interrupt_disable <= 1'b0;
end
// Writes to SFR's
if (biu_sfr_select==1'b1 && eu_biu_strobe_int==3'h1)
begin
case (eu_register_r3_d1[7:0]) // synthesis parallel_case
8'h81 : biu_sfr_sp_int <= EU_BIU_DATAOUT[7:0];
8'h82 : biu_sfr_dpl_int <= EU_BIU_DATAOUT[7:0];
8'h83 : biu_sfr_dph_int <= EU_BIU_DATAOUT[7:0];
8'hA8 : biu_sfr_ie_int <= EU_BIU_DATAOUT[7:0];
8'hD0 : biu_sfr_psw_int <= EU_BIU_DATAOUT[7:0];
8'hE0 : biu_sfr_acc_int <= EU_BIU_DATAOUT[7:0];
8'hF0 : biu_sfr_b_int <= EU_BIU_DATAOUT[7:0];
// Proxy Addressing Registers
8'hC1 : biu_sfr_pxy_dout <= EU_BIU_DATAOUT[7:0];
8'hC2 : biu_sfr_pxy_addr <= EU_BIU_DATAOUT[7:0];
default : ;
endcase
end
// Assert the write strobe to the proxy addressed peripherals
if (biu_sfr_select==1'b1 && eu_biu_strobe_int==3'h1 && eu_register_r3_d1[7:0]==8'hC1)
begin
biu_pxy_wr <= 1'b1;
end
else
begin
biu_pxy_wr <= 1'b0;
end
// Assert the read strobe to the proxy addressed peripherals
if (biu_sfr_select==1'b1 && eu_biu_strobe_int==3'h1 && eu_register_r3_d1[7:0]==8'hC2)
begin
biu_pxy_rd <= 1'b1;
end
else
begin
biu_pxy_rd <= 1'b0;
end
end
if (eu_biu_strobe_int==3'h3)
begin
core_interrupt_disable <= 1'b1;
end
if (eu_biu_strobe_int==3'h4)
begin
core_interrupt_disable <= 1'b0;
end
// Writes to SFR's
if (biu_sfr_select==1'b1 && eu_biu_strobe_int==3'h1)
begin
case (eu_register_r3_d1[7:0]) // synthesis parallel_case
8'h81 : biu_sfr_sp_int <= EU_BIU_DATAOUT[7:0];
8'h82 : biu_sfr_dpl_int <= EU_BIU_DATAOUT[7:0];
8'h83 : biu_sfr_dph_int <= EU_BIU_DATAOUT[7:0];
8'hA8 : biu_sfr_ie_int <= EU_BIU_DATAOUT[7:0];
8'hD0 : biu_sfr_psw_int <= EU_BIU_DATAOUT[7:0];
8'hE0 : biu_sfr_acc_int <= EU_BIU_DATAOUT[7:0];
8'hF0 : biu_sfr_b_int <= EU_BIU_DATAOUT[7:0];
// Proxy Addressing Registers
8'hC1 : biu_sfr_pxy_dout <= EU_BIU_DATAOUT[7:0];
8'hC2 : biu_sfr_pxy_addr <= EU_BIU_DATAOUT[7:0];
default : ;
endcase
end
// Assert the write strobe to the proxy addressed peripherals
if (biu_sfr_select==1'b1 && eu_biu_strobe_int==3'h1 && eu_register_r3_d1[7:0]==8'hC1)
begin
biu_pxy_wr <= 1'b1;
end
else
begin
biu_pxy_wr <= 1'b0;
end
// Assert the read strobe to the proxy addressed peripherals
if (biu_sfr_select==1'b1 && eu_biu_strobe_int==3'h1 && eu_register_r3_d1[7:0]==8'hC2)
begin
biu_pxy_rd <= 1'b1;
end
else
begin
biu_pxy_rd <= 1'b0;
end
end
end
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//------------------------------------------------------------------------
@@ -338,14 +359,14 @@ end
//
// Steer the peripheral read data
assign biu_sfr_pxy_din = (biu_sfr_pxy_addr[7:4]==4'h0) ? biu_timer_dataout :
(biu_sfr_pxy_addr[7:4]==4'h1) ? biu_uart_dataout :
8'hEE ;
assign biu_sfr_pxy_din = (biu_sfr_pxy_addr[7:4]==4'h0) ? biu_timer_dataout :
(biu_sfr_pxy_addr[7:4]==4'h1) ? biu_uart_dataout :
8'hEE ;
// Gate the peripheral read and write strobes
assign biu_timer_wr_strobe = (biu_sfr_pxy_addr[7:4]==4'h0) ? biu_pxy_wr : 1'b0;
assign biu_uart_wr_strobe = (biu_sfr_pxy_addr[7:4]==4'h1) ? biu_pxy_wr : 1'b0;
assign biu_uart_rd_strobe = (biu_sfr_pxy_addr[7:4]==4'h1) ? biu_pxy_rd : 1'b0;
assign biu_timer_wr_strobe = (biu_sfr_pxy_addr[7:4]==4'h0) ? biu_pxy_wr : 1'b0;
assign biu_uart_wr_strobe = (biu_sfr_pxy_addr[7:4]==4'h1) ? biu_pxy_wr : 1'b0;
assign biu_uart_rd_strobe = (biu_sfr_pxy_addr[7:4]==4'h1) ? biu_pxy_rd : 1'b0;
@@ -357,49 +378,49 @@ assign biu_uart_rd_strobe = (biu_sfr_pxy_addr[7:4]==4'h1) ? biu_pxy_rd : 1'b0;
// Timer-0 = Frequency generator
// Timer-1 = Pulse generator
//
//------------------------------------------------------------------------
timer BIU_TIMER
//------------------------------------------------------------------------
timer BIU_TIMER
(
.CORE_CLK (CORE_CLK),
.RST_n (RST_n),
.ADDRESS (biu_sfr_pxy_addr[3:0]),
.DATA_IN (biu_sfr_pxy_dout),
.DATA_OUT (biu_timer_dataout),
.STROBE_WR (biu_timer_wr_strobe),
.TIMER0_OUT (SPEAKER),
.TIMER1_OUT (biu_int2)
.CORE_CLK (CORE_CLK),
.RST_n (RST_n),
.ADDRESS (biu_sfr_pxy_addr[3:0]),
.DATA_IN (biu_sfr_pxy_dout),
.DATA_OUT (biu_timer_dataout),
.STROBE_WR (biu_timer_wr_strobe),
.TIMER0_OUT (SPEAKER),
.TIMER1_OUT (biu_int2)
);
//------------------------------------------------------------------------
//
// UART - Fixed 9600 baud
//
//------------------------------------------------------------------------
//------------------------------------------------------------------------
uart_and_loader BIU_UART
uart_and_loader BIU_UART
(
.CLK (CORE_CLK),
.RST_n (RST_n),
.ADDRESS (biu_sfr_pxy_addr[1:0]),
.DATA_IN (biu_sfr_pxy_dout),
.DATA_OUT (biu_uart_dataout),
.STROBE_RD (biu_uart_rd_strobe),
.STROBE_WR (biu_uart_wr_strobe),
.UART_RX (UART_RX),
.UART_TX (UART_TX),
.UART_INT (biu_int3),
.CLK (CORE_CLK),
.RST_n (RST_n),
.ADDRESS (biu_sfr_pxy_addr[1:0]),
.DATA_IN (biu_sfr_pxy_dout),
.DATA_OUT (biu_uart_dataout),
.STROBE_RD (biu_uart_rd_strobe),
.STROBE_WR (biu_uart_wr_strobe),
.UART_RX (UART_RX),
.UART_TX (UART_TX),
.UART_INT (biu_int3),
.LOADER_ADDR (loader_addr_int ),
.LOADER_DATA (loader_data_int ),
.LOADER_WR (loader_wr ),
.RESET_OUT (RESET_OUT )
.LOADER_ADDR (loader_addr_int ),
.LOADER_DATA (loader_data_int ),
.LOADER_WR (loader_wr ),
.RESET_OUT (RESET_OUT )
);
endmodule // biu.v

296
MCL51/Core/eu.v
View File

@@ -2,7 +2,7 @@
//
// File Name : eu.v
// Used on : MCL51
// Author : MicroCore Labs
// Author : Ted Fried, MicroCore Labs
// Creation : 3/13/2016
// Code Type : Synthesizable
//
@@ -21,31 +21,53 @@
//
//
//------------------------------------------------------------------------
//
// Copyright (c) 2020 Ted Fried
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
//------------------------------------------------------------------------
module eu
(
input CORE_CLK, // Core Clock
input RST_n,
output [7:0] EU_BIU_STROBE, // EU to BIU Signals
output [7:0] EU_BIU_DATAOUT,
output [15:0] EU_REGISTER_R3,
output [15:0] EU_REGISTER_IP,
input [7:0] BIU_SFR_ACC, // BIU to EU Signals
input [15:0] BIU_SFR_DPTR,
input [7:0] BIU_SFR_SP,
input [7:0] BIU_SFR_PSW,
input [7:0] BIU_RETURN_DATA,
input BIU_INTERRUPT
input CORE_CLK, // Core Clock
input RST_n,
output [7:0] EU_BIU_STROBE, // EU to BIU Signals
output [7:0] EU_BIU_DATAOUT,
output [15:0] EU_REGISTER_R3,
output [15:0] EU_REGISTER_IP,
input [7:0] BIU_SFR_ACC, // BIU to EU Signals
input [15:0] BIU_SFR_DPTR,
input [7:0] BIU_SFR_SP,
input [7:0] BIU_SFR_PSW,
input [7:0] BIU_RETURN_DATA,
input BIU_INTERRUPT
);
//------------------------------------------------------------------------
// Internal Signals
@@ -94,29 +116,29 @@ wire [15:0] eu_flags_r;
//
// EU Microcode ROM. 1Kx32
//
//------------------------------------------------------------------------
//------------------------------------------------------------------------
/*
// For Lattice XO2 FPGAs
eu_rom EU_1Kx32
eu_rom EU_1Kx32
(
.Reset (1'b0),
.OutClockEn (1'b1),
.OutClock (CORE_CLK),
.Address (eu_rom_address[9:0]),
.Q (eu_rom_data)
.Reset (1'b0),
.OutClockEn (1'b1),
.OutClock (CORE_CLK),
.Address (eu_rom_address[9:0]),
.Q (eu_rom_data)
);
*/
// For Xilinx Artix FPGAs
eu_rom EU_1Kx32
eu_rom EU_1Kx32
(
.clka (CORE_CLK),
.addra (eu_rom_address[9:0]),
.douta (eu_rom_data)
.clka (CORE_CLK),
.addra (eu_rom_address[9:0]),
.douta (eu_rom_data)
);
@@ -127,72 +149,72 @@ eu_rom EU_1Kx32
//
//------------------------------------------------------------------------
assign EU_BIU_STROBE = eu_biu_strobe;
assign EU_BIU_DATAOUT = eu_biu_dataout;
assign EU_REGISTER_R3 = eu_register_r3;
assign EU_REGISTER_IP = eu_register_ip;
assign EU_BIU_STROBE = eu_biu_strobe;
assign EU_BIU_DATAOUT = eu_biu_dataout;
assign EU_REGISTER_R3 = eu_register_r3;
assign EU_REGISTER_IP = eu_register_ip;
// EU ROM opcode decoder
assign eu_opcode_type = eu_rom_data[30:28];
assign eu_opcode_dst_sel = eu_rom_data[26:24];
assign eu_opcode_op0_sel = eu_rom_data[23:20];
assign eu_opcode_op1_sel = eu_rom_data[18:16];
assign eu_opcode_type = eu_rom_data[30:28];
assign eu_opcode_dst_sel = eu_rom_data[26:24];
assign eu_opcode_op0_sel = eu_rom_data[23:20];
assign eu_opcode_op1_sel = eu_rom_data[18:16];
assign eu_opcode_immediate = eu_rom_data[15:0];
assign eu_opcode_jump_call = eu_rom_data[24];
assign eu_opcode_jump_src = eu_rom_data[22:20];
assign eu_opcode_jump_cond = eu_rom_data[18:16];
assign eu_opcode_jump_call = eu_rom_data[24];
assign eu_opcode_jump_src = eu_rom_data[22:20];
assign eu_opcode_jump_cond = eu_rom_data[18:16];
assign eu_operand0 = (eu_opcode_op0_sel==4'h0) ? eu_register_r0 :
(eu_opcode_op0_sel==4'h1) ? eu_register_r1 :
(eu_opcode_op0_sel==4'h2) ? eu_register_r2 :
(eu_opcode_op0_sel==4'h3) ? eu_register_r3 :
assign eu_operand0 = (eu_opcode_op0_sel==4'h0) ? eu_register_r0 :
(eu_opcode_op0_sel==4'h1) ? eu_register_r1 :
(eu_opcode_op0_sel==4'h2) ? eu_register_r2 :
(eu_opcode_op0_sel==4'h3) ? eu_register_r3 :
(eu_opcode_op0_sel==4'h4) ? { 8'h00 , BIU_RETURN_DATA } :
(eu_opcode_op0_sel==4'h5) ? { eu_flags_r[15:0] } :
(eu_opcode_op0_sel==4'h5) ? { eu_flags_r[15:0] } :
(eu_opcode_op0_sel==4'h6) ? { 8'h00 , BIU_SFR_ACC } :
(eu_opcode_op0_sel==4'h7) ? eu_register_ip :
16'h0000 ;
(eu_opcode_op0_sel==4'h7) ? eu_register_ip :
16'h0000 ;
assign eu_operand1 = (eu_opcode_op1_sel==3'h0) ? eu_register_r0 :
(eu_opcode_op1_sel==3'h1) ? eu_register_r1 :
(eu_opcode_op1_sel==3'h2) ? eu_register_r2 :
(eu_opcode_op1_sel==3'h3) ? eu_register_r3 :
(eu_opcode_op1_sel==3'h4) ? { 8'h00 , BIU_SFR_SP } :
//(eu_opcode_op1_sel==3'h5) ? eu_alu_last_result :
(eu_opcode_op1_sel==3'h6) ? BIU_SFR_DPTR :
eu_opcode_immediate ;
assign eu_operand1 = (eu_opcode_op1_sel==3'h0) ? eu_register_r0 :
(eu_opcode_op1_sel==3'h1) ? eu_register_r1 :
(eu_opcode_op1_sel==3'h2) ? eu_register_r2 :
(eu_opcode_op1_sel==3'h3) ? eu_register_r3 :
(eu_opcode_op1_sel==3'h4) ? { 8'h00 , BIU_SFR_SP } :
//(eu_opcode_op1_sel==3'h5) ? eu_alu_last_result :
(eu_opcode_op1_sel==3'h6) ? BIU_SFR_DPTR :
eu_opcode_immediate ;
// JUMP condition codes
assign eu_jump_gate = (eu_opcode_jump_cond==4'h0) ? 1'b1 : // unconditional jump
(eu_opcode_jump_cond==4'h1 && eu_alu_last_result!=16'h0) ? 1'b1 :
(eu_opcode_jump_cond==4'h2 && eu_alu_last_result==16'h0) ? 1'b1 :
1'b0 ;
1'b0 ;
// ** Flags must be written to the PSW through the BIU
assign eu_flags_r[15] = eu_add_carry;
assign eu_flags_r[14] = eu_add_aux_carry;
assign eu_flags_r[15] = eu_add_carry;
assign eu_flags_r[14] = eu_add_aux_carry;
assign eu_flags_r[13] = eu_add_carry16;
//assign eu_flags_r[12] =
//assign eu_flags_r[11] =
assign eu_flags_r[10] = eu_add_overflow;
//assign eu_flags_r[9] =
assign eu_flags_r[8] = BIU_INTERRUPT;
//assign eu_flags_r[12] =
//assign eu_flags_r[11] =
assign eu_flags_r[10] = eu_add_overflow;
//assign eu_flags_r[9] =
assign eu_flags_r[8] = BIU_INTERRUPT;
assign eu_flags_r[7] = BIU_SFR_PSW[7]; // C
assign eu_flags_r[6] = BIU_SFR_PSW[6]; // AC
assign eu_flags_r[5] = BIU_SFR_PSW[5]; // F0
assign eu_flags_r[4] = BIU_SFR_PSW[4]; // RS1
assign eu_flags_r[3] = BIU_SFR_PSW[3]; // RS0
assign eu_flags_r[2] = BIU_SFR_PSW[2]; // Overflow
assign eu_flags_r[1] = BIU_SFR_PSW[1]; // User Defined Flag
assign eu_flags_r[0] = BIU_SFR_PSW[0]; // ACC Parity generated in the BIU
assign eu_flags_r[7] = BIU_SFR_PSW[7]; // C
assign eu_flags_r[6] = BIU_SFR_PSW[6]; // AC
assign eu_flags_r[5] = BIU_SFR_PSW[5]; // F0
assign eu_flags_r[4] = BIU_SFR_PSW[4]; // RS1
assign eu_flags_r[3] = BIU_SFR_PSW[3]; // RS0
assign eu_flags_r[2] = BIU_SFR_PSW[2]; // Overflow
assign eu_flags_r[1] = BIU_SFR_PSW[1]; // User Defined Flag
assign eu_flags_r[0] = BIU_SFR_PSW[0]; // ACC Parity generated in the BIU
@@ -201,13 +223,13 @@ assign eu_flags_r[0] = BIU_SFR_PSW[0]; // ACC Parity generated in the BIU
// ------------------------------------------
// eu_alu0 = NOP
// eu_alu1 = JUMP
assign eu_alu2 = adder_out; // ADD
assign eu_alu3 = eu_operand0 ^ eu_operand1; // XOR
assign eu_alu4 = eu_operand0 | eu_operand1; // OR
assign eu_alu5 = eu_operand0 & eu_operand1; // AND
assign eu_alu6 = { eu_operand0[7:0] , eu_operand0[15:8] }; // BYTESWAP
assign eu_alu7 = (eu_opcode_immediate[1:0]==2'h0) ? { 8'h00 , eu_operand0[0] , eu_operand0[7:1] } : // Rotate in bit[0]
(eu_opcode_immediate[1:0]==2'h1) ? { 8'h00 , BIU_SFR_PSW[7] , eu_operand0[7:1] } : // Rotate in Carry bit
assign eu_alu2 = adder_out; // ADD
assign eu_alu3 = eu_operand0 ^ eu_operand1; // XOR
assign eu_alu4 = eu_operand0 | eu_operand1; // OR
assign eu_alu5 = eu_operand0 & eu_operand1; // AND
assign eu_alu6 = { eu_operand0[7:0] , eu_operand0[15:8] }; // BYTESWAP
assign eu_alu7 = (eu_opcode_immediate[1:0]==2'h0) ? { 8'h00 , eu_operand0[0] , eu_operand0[7:1] } : // Rotate in bit[0]
(eu_opcode_immediate[1:0]==2'h1) ? { 8'h00 , BIU_SFR_PSW[7] , eu_operand0[7:1] } : // Rotate in Carry bit
{ eu_add_carry16 , eu_operand0[15:1] } ; // 16-bit shift-right
@@ -220,7 +242,7 @@ assign eu_alu_out = (eu_opcode_type==3'h2) ? eu_alu2 :
(eu_opcode_type==3'h7) ? eu_alu7 :
16'hEEEE;
// Generate 16-bit full adder for the EU
assign carry[0] = 1'b0;
@@ -228,17 +250,17 @@ genvar i;
generate
for (i=0; i < 16; i=i+1)
begin : GEN_ADDER
assign adder_out[i] = eu_operand0[i] ^ eu_operand1[i] ^ carry[i];
assign carry[i+1] = (eu_operand0[i] & eu_operand1[i]) | (eu_operand0[i] & carry[i]) | (eu_operand1[i] & carry[i]);
assign adder_out[i] = eu_operand0[i] ^ eu_operand1[i] ^ carry[i];
assign carry[i+1] = (eu_operand0[i] & eu_operand1[i]) | (eu_operand0[i] & carry[i]) | (eu_operand1[i] & carry[i]);
end
endgenerate
assign new_instruction = (eu_rom_address[9:8]==2'b00) ? 1'b1 : 1'b0;
assign new_instruction = (eu_rom_address[9:8]==2'b00) ? 1'b1 : 1'b0;
//------------------------------------------------------------------------------------------
//
// EU Microsequencer
@@ -259,7 +281,7 @@ begin : EU_MICROSEQUENCER
eu_register_r1 <= 'h0;
eu_register_r2 <= 'h0;
eu_register_r3 <= 'h0;
eu_register_ip <= 16'hFFFF; // User Program code starts at 0x0000 after reset. Main loop does initial increment.
eu_register_ip <= 16'hFFFF; // User Program code starts at 0x0000 after reset. Main loop does initial increment.
eu_biu_strobe <= 'h0;
eu_biu_dataout <= 'h0;
eu_stall_pipeline <= 'h0;
@@ -270,64 +292,64 @@ begin : EU_MICROSEQUENCER
else
begin
// Generate and store flags for addition
if (eu_stall_pipeline==1'b0 && eu_opcode_type==3'h2)
begin
eu_add_carry16 <= carry[16];
eu_add_carry <= carry[8];
eu_add_aux_carry <= carry[4];
eu_add_overflow <= carry[8] ^ carry[7];
// Generate and store flags for addition
if (eu_stall_pipeline==1'b0 && eu_opcode_type==3'h2)
begin
eu_add_carry16 <= carry[16];
eu_add_carry <= carry[8];
eu_add_aux_carry <= carry[4];
eu_add_overflow <= carry[8] ^ carry[7];
end
// Register writeback
// Register writeback
if (eu_stall_pipeline==1'b0 && eu_opcode_type!=3'h0 && eu_opcode_type!=3'h1)
begin
eu_alu_last_result <= eu_alu_out[15:0];
case (eu_opcode_dst_sel) // synthesis parallel_case
3'h0 : eu_register_r0 <= eu_alu_out[15:0];
3'h1 : eu_register_r1 <= eu_alu_out[15:0];
3'h2 : eu_register_r2 <= eu_alu_out[15:0];
3'h3 : eu_register_r3 <= eu_alu_out[15:0];
3'h4 : eu_biu_dataout <= eu_alu_out[7:0];
//3'h5 :
3'h6 : eu_biu_strobe <= eu_alu_out[7:0];
3'h7 : eu_register_ip <= eu_alu_out[15:0];
default : ;
endcase
begin
eu_alu_last_result <= eu_alu_out[15:0];
case (eu_opcode_dst_sel) // synthesis parallel_case
3'h0 : eu_register_r0 <= eu_alu_out[15:0];
3'h1 : eu_register_r1 <= eu_alu_out[15:0];
3'h2 : eu_register_r2 <= eu_alu_out[15:0];
3'h3 : eu_register_r3 <= eu_alu_out[15:0];
3'h4 : eu_biu_dataout <= eu_alu_out[7:0];
//3'h5 :
3'h6 : eu_biu_strobe <= eu_alu_out[7:0];
3'h7 : eu_register_ip <= eu_alu_out[15:0];
default : ;
endcase
end
// JUMP Opcode
if (eu_stall_pipeline==1'b0 && eu_opcode_type==3'h1 && eu_jump_gate==1'b1)
begin
eu_stall_pipeline <= 1'b1;
// For subroutine CALLs, store next opcode address
if (eu_opcode_jump_call==1'b1)
begin
eu_calling_address[19:0] <= {eu_calling_address[9:0] , eu_rom_address[9:0] }; // Two deep calling addresses
end
// JUMP Opcode
if (eu_stall_pipeline==1'b0 && eu_opcode_type==3'h1 && eu_jump_gate==1'b1)
begin
eu_stall_pipeline <= 1'b1;
// For subroutine CALLs, store next opcode address
if (eu_opcode_jump_call==1'b1)
begin
eu_calling_address[19:0] <= {eu_calling_address[9:0] , eu_rom_address[9:0] }; // Two deep calling addresses
end
case (eu_opcode_jump_src) // synthesis parallel_case
3'h0 : eu_rom_address <= eu_opcode_immediate[9:0];
3'h1 : eu_rom_address <= { 2'h0 , BIU_RETURN_DATA }; // Initial opcode jump decoding
3'h2 : eu_rom_address <= { eu_opcode_immediate[9:4] , eu_register_r0[11:8] }; // EA decoding
3'h3 : begin // CALL Return
eu_rom_address <= eu_calling_address[9:0];
eu_calling_address[9:0] <= eu_calling_address[19:10];
end
3'h4 : eu_rom_address <= { eu_opcode_immediate[5:0] , BIU_RETURN_DATA[2:0] , 1'b0 }; // Bit Mask decoding table
default : ;
endcase
end
case (eu_opcode_jump_src) // synthesis parallel_case
3'h0 : eu_rom_address <= eu_opcode_immediate[9:0];
3'h1 : eu_rom_address <= { 2'h0 , BIU_RETURN_DATA }; // Initial opcode jump decoding
3'h2 : eu_rom_address <= { eu_opcode_immediate[9:4] , eu_register_r0[11:8] }; // EA decoding
3'h3 : begin // CALL Return
eu_rom_address <= eu_calling_address[9:0];
eu_calling_address[9:0] <= eu_calling_address[19:10];
end
3'h4 : eu_rom_address <= { eu_opcode_immediate[5:0] , BIU_RETURN_DATA[2:0] , 1'b0 }; // Bit Mask decoding table
default : ;
endcase
end
else
begin
eu_stall_pipeline <= 1'b0; // Debounce the pipeline stall
eu_rom_address <= eu_rom_address + 1'b1;
eu_stall_pipeline <= 1'b0; // Debounce the pipeline stall
eu_rom_address <= eu_rom_address + 1'b1;
end
end