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MicroCoreLabs
2020-01-25 11:42:25 -08:00
parent 50099361f5
commit e4bde7a1f9
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368
MCLR5/Core/MCLR5.v
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@@ -14,16 +14,28 @@
//
//------------------------------------------------------------------------
//
// Copyright (C) 2018 by Ted Fried info@MicroCoreLabs.com
// Copyright (c) 2020 Ted Fried
//
// Permission to use, copy, modify, and distribute this software and its
// documentation for any purpose and without fee is hereby granted, provided
// that the above copyright notice appear in all copies and that both that
// copyright notice and this permission notice appear in supporting documentation.
// This software is provided "as is" without express or implied warranty.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
//------------------------------------------------------------------------
//
// Modification History:
// =====================
//
@@ -36,14 +48,14 @@
module MCLR5
(
input CORE_CLK,
input RST_n,
input CORE_CLK,
input RST_n,
output [31:0] LOAD_STORE_ADDRESS,
output [31:0] STORE_DATA,
input [31:0] LOAD_DATA,
output LOAD_REQ,
output STORE_REQ
output [31:0] LOAD_STORE_ADDRESS,
output [31:0] STORE_DATA,
input [31:0] LOAD_DATA,
output LOAD_REQ,
output STORE_REQ
);
@@ -119,31 +131,31 @@ wire [4:0] alu3_opcode_rd;
/*
// For Xilinx FPGAs
DPROM_8Kx128 code_rom
DPROM_8Kx128 code_rom
(
.clka (CORE_CLK),
.addra (new_pc[14:2]),
.douta (program_rom_data[127:0]),
.clka (CORE_CLK),
.addra (new_pc[14:2]),
.douta (program_rom_data[127:0]),
.clkb (CORE_CLK),
.addrb (new_pc_plus1[14:2]),
.doutb (program_rom_data[255:128])
.clkb (CORE_CLK),
.addrb (new_pc_plus1[14:2]),
.doutb (program_rom_data[255:128])
);
*/
DPROM_8Kx128 code_rom (
.address_a (new_pc[14:2]), // input, width = 13, ram_input.address_a
.address_b (new_pc_plus1[14:2]), // input, width = 13, .address_b
.clock (CORE_CLK), // input, width = 1, .clock
.q_a (program_rom_data[127:0]), // output, width = 128, ram_output.q_a
.q_b (program_rom_data[255:128]) // output, width = 128, .q_b
);
DPROM_8Kx128 code_rom (
.address_a (new_pc[14:2]), // input, width = 13, ram_input.address_a
.address_b (new_pc_plus1[14:2]), // input, width = 13, .address_b
.clock (CORE_CLK), // input, width = 1, .clock
.q_a (program_rom_data[127:0]), // output, width = 128, ram_output.q_a
.q_b (program_rom_data[255:128]) // output, width = 128, .q_b
);
assign new_pc_plus1 = new_pc + 3'h4;
@@ -158,25 +170,25 @@ assign alu3_pc = new_pc + 3;
assign alu0_opcode = (new_pc[1:0]==2'h0) ? program_rom_data[31:0] :
(new_pc[1:0]==2'h1) ? program_rom_data[63:32] :
(new_pc[1:0]==2'h2) ? program_rom_data[95:64] :
program_rom_data[127:96] ;
program_rom_data[127:96] ;
assign alu1_opcode = (new_pc[1:0]==2'h0) ? program_rom_data[63:32] :
(new_pc[1:0]==2'h1) ? program_rom_data[95:64] :
(new_pc[1:0]==2'h2) ? program_rom_data[127:96] :
(new_pc[1:0]==2'h2) ? program_rom_data[127:96] :
program_rom_data[159:128] ;
assign alu2_opcode = (new_pc[1:0]==2'h0) ? program_rom_data[95:64] :
(new_pc[1:0]==2'h1) ? program_rom_data[127:96] :
(new_pc[1:0]==2'h1) ? program_rom_data[127:96] :
(new_pc[1:0]==2'h2) ? program_rom_data[159:128] :
program_rom_data[191:160] ;
program_rom_data[191:160] ;
assign alu3_opcode = (new_pc[1:0]==2'h0) ? program_rom_data[127:96] :
(new_pc[1:0]==2'h1) ? program_rom_data[159:128] :
(new_pc[1:0]==2'h2) ? program_rom_data[191:160] :
program_rom_data[223:192] ;
(new_pc[1:0]==2'h2) ? program_rom_data[191:160] :
program_rom_data[223:192] ;
// Register decodes from the opcode
//
@@ -214,7 +226,7 @@ assign alu0_rs1 = (alu0_opcode_rs1 == 5'h00) ? 32'h0 :
(alu0_opcode_rs1 == 5'h01) ? register_1 :
(alu0_opcode_rs1 == 5'h02) ? register_2 :
(alu0_opcode_rs1 == 5'h03) ? register_3 :
register_4 ;
register_4 ;
@@ -222,53 +234,53 @@ assign alu0_rs2 = (alu0_opcode_rs2 == 5'h00) ? 32'h0 :
(alu0_opcode_rs2 == 5'h01) ? register_1 :
(alu0_opcode_rs2 == 5'h02) ? register_2 :
(alu0_opcode_rs2 == 5'h03) ? register_3 :
register_4 ;
register_4 ;
//------------------------------------------------------------------------
assign alu1_rs1 = ( alu0_rd[32]==1'b1 && (alu1_opcode_rs1==alu0_opcode_rd) ) ? alu0_rd[31:0] :
(alu1_opcode_rs1 == 5'h00) ? 32'h0 :
(alu1_opcode_rs1 == 5'h01) ? register_1 :
(alu1_opcode_rs1 == 5'h02) ? register_2 :
(alu1_opcode_rs1 == 5'h03) ? register_3 :
register_4 ;
register_4 ;
assign alu1_rs2 = ( alu0_rd[32]==1'b1 && (alu1_opcode_rs2==alu0_opcode_rd) ) ? alu0_rd[31:0] :
(alu1_opcode_rs2 == 5'h00) ? 32'h0 :
(alu1_opcode_rs2 == 5'h01) ? register_1 :
(alu1_opcode_rs2 == 5'h02) ? register_2 :
(alu1_opcode_rs2 == 5'h03) ? register_3 :
register_4 ;
register_4 ;
//------------------------------------------------------------------------
assign alu2_rs1 = ( alu1_rd[32]==1'b1 && (alu2_opcode_rs1==alu1_opcode_rd) ) ? alu1_rd[31:0] :
( alu0_rd[32]==1'b1 && (alu2_opcode_rs1==alu0_opcode_rd) ) ? alu0_rd[31:0] :
(alu2_opcode_rs1 == 5'h00) ? 32'h0 :
(alu2_opcode_rs1 == 5'h01) ? register_1 :
(alu2_opcode_rs1 == 5'h02) ? register_2 :
(alu2_opcode_rs1 == 5'h03) ? register_3 :
register_4 ;
register_4 ;
assign alu2_rs2 = ( alu1_rd[32]==1'b1 && (alu2_opcode_rs2==alu1_opcode_rd) ) ? alu1_rd[31:0] :
( alu0_rd[32]==1'b1 && (alu2_opcode_rs2==alu0_opcode_rd) ) ? alu0_rd[31:0] :
(alu2_opcode_rs2 == 5'h00) ? 32'h0 :
(alu2_opcode_rs2 == 5'h01) ? register_1 :
(alu2_opcode_rs2 == 5'h02) ? register_2 :
(alu2_opcode_rs2 == 5'h03) ? register_3 :
register_4 ;
register_4 ;
//------------------------------------------------------------------------
assign alu3_rs1 = ( alu2_rd[32]==1'b1 && (alu3_opcode_rs1==alu2_opcode_rd) ) ? alu2_rd[31:0] :
( alu1_rd[32]==1'b1 && (alu3_opcode_rs1==alu1_opcode_rd) ) ? alu1_rd[31:0] :
( alu0_rd[32]==1'b1 && (alu3_opcode_rs1==alu0_opcode_rd) ) ? alu0_rd[31:0] :
@@ -276,11 +288,11 @@ assign alu3_rs1 = ( alu2_rd[32]==1'b1 && (alu3_opcode_rs1==alu2_opcode_rd) ) ? a
(alu3_opcode_rs1 == 5'h01) ? register_1 :
(alu3_opcode_rs1 == 5'h02) ? register_2 :
(alu3_opcode_rs1 == 5'h03) ? register_3 :
register_4 ;
register_4 ;
assign alu3_rs2 = ( alu2_rd[32]==1'b1 && (alu3_opcode_rs2==alu2_opcode_rd) ) ? alu2_rd[31:0] :
( alu1_rd[32]==1'b1 && (alu3_opcode_rs2==alu1_opcode_rd) ) ? alu1_rd[31:0] :
( alu0_rd[32]==1'b1 && (alu3_opcode_rs2==alu0_opcode_rd) ) ? alu0_rd[31:0] :
@@ -288,11 +300,11 @@ assign alu3_rs2 = ( alu2_rd[32]==1'b1 && (alu3_opcode_rs2==alu2_opcode_rd) ) ? a
(alu3_opcode_rs2 == 5'h01) ? register_1 :
(alu3_opcode_rs2 == 5'h02) ? register_2 :
(alu3_opcode_rs2 == 5'h03) ? register_3 :
register_4 ;
register_4 ;
//------------------------------------------------------------------------------------------
//
// Register writebacks
@@ -305,73 +317,73 @@ begin : REGISTER_WRITEBACKS
if (RST_n==1'b0)
begin
alu0_load_req_d <= 'h0;
new_pc <= 32'hFFFF_FFFC;
new_pc <= 32'hFFFF_FFFC;
end
else
begin
if ( (loadstore_stall == 4'b0000 && (alu0_load_req==1'b1 || alu0_store_req==1'b1) ) ||
(loadstore_stall == 4'b0000 && (alu1_load_req==1'b1 || alu1_store_req==1'b1) ) ||
(loadstore_stall == 4'b0000 && (alu2_load_req==1'b1 || alu2_store_req==1'b1) ) ||
(loadstore_stall == 4'b0000 && (alu3_load_req==1'b1 || alu3_store_req==1'b1) ) )
begin
loadstore_stall <= 4'b1111; // new_pc_stall for three cycles
(loadstore_stall == 4'b0000 && (alu3_load_req==1'b1 || alu3_store_req==1'b1) ) )
begin
loadstore_stall <= 4'b1111; // new_pc_stall for three cycles
end
else
begin
loadstore_stall <= { 1'b0 , loadstore_stall[3:1] };
else
begin
loadstore_stall <= { 1'b0 , loadstore_stall[3:1] };
end
// Writeback register file
// Only write back registers that have been updated.
// Block register updates if a previous alu is taking a branch
//
if (new_pc_stall==1'b0 && ((loadstore_stall==4'b0001 || alu0_newpc[32]==1'b0) && alu1_newpc[32]==1'b0 && alu2_newpc[32]==1'b0) && alu3_rd[32]==1'b1)
begin
case (alu3_opcode_rd)
5'h01 : register_1 <= alu3_rd[31:0];
5'h02 : register_2 <= alu3_rd[31:0];
5'h03 : register_3 <= alu3_rd[31:0];
5'h04 : register_4 <= alu3_rd[31:0];
default: ;
case (alu3_opcode_rd)
5'h01 : register_1 <= alu3_rd[31:0];
5'h02 : register_2 <= alu3_rd[31:0];
5'h03 : register_3 <= alu3_rd[31:0];
5'h04 : register_4 <= alu3_rd[31:0];
default: ;
endcase
end
end
else if (new_pc_stall==1'b0 && ((loadstore_stall==4'b0001 || alu0_newpc[32]==1'b0) && alu1_newpc[32]==1'b0) && alu2_rd[32]==1'b1)
begin
case (alu2_opcode_rd)
5'h01 : register_1 <= alu2_rd[31:0];
5'h02 : register_2 <= alu2_rd[31:0];
5'h03 : register_3 <= alu2_rd[31:0];
5'h04 : register_4 <= alu2_rd[31:0];
default: ;
case (alu2_opcode_rd)
5'h01 : register_1 <= alu2_rd[31:0];
5'h02 : register_2 <= alu2_rd[31:0];
5'h03 : register_3 <= alu2_rd[31:0];
5'h04 : register_4 <= alu2_rd[31:0];
default: ;
endcase
end
end
else if (new_pc_stall==1'b0 && (loadstore_stall==4'b0001 || alu0_newpc[32]==1'b0) && alu1_rd[32]==1'b1)
begin
case (alu1_opcode_rd)
5'h01 : register_1 <= alu1_rd[31:0];
5'h02 : register_2 <= alu1_rd[31:0];
5'h03 : register_3 <= alu1_rd[31:0];
5'h04 : register_4 <= alu1_rd[31:0];
default: ;
case (alu1_opcode_rd)
5'h01 : register_1 <= alu1_rd[31:0];
5'h02 : register_2 <= alu1_rd[31:0];
5'h03 : register_3 <= alu1_rd[31:0];
5'h04 : register_4 <= alu1_rd[31:0];
default: ;
endcase
end
end
else if (new_pc_stall==1'b0 && alu0_rd[32]==1'b1)
begin
case (alu0_opcode_rd)
5'h01 : register_1 <= alu0_rd[31:0];
5'h02 : register_2 <= alu0_rd[31:0];
5'h03 : register_3 <= alu0_rd[31:0];
5'h04 : register_4 <= alu0_rd[31:0];
default: ;
case (alu0_opcode_rd)
5'h01 : register_1 <= alu0_rd[31:0];
5'h02 : register_2 <= alu0_rd[31:0];
5'h03 : register_3 <= alu0_rd[31:0];
5'h04 : register_4 <= alu0_rd[31:0];
default: ;
endcase
end
end
//------------------------------------------------------------------------
@@ -383,33 +395,33 @@ else
if ((new_pc_stall==1'b0 && alu0_newpc[32]==1'b1) && loadstore_stall!=4'b0001)
begin
new_pc_stall <= 1'b1;
new_pc <= alu0_newpc[31:0];
end
new_pc_stall <= 1'b1;
new_pc <= alu0_newpc[31:0];
end
else if (new_pc_stall==1'b0 && alu1_newpc[32]==1'b1)
begin
new_pc_stall <= 1'b1;
new_pc <= alu1_newpc[31:0];
end
new_pc_stall <= 1'b1;
new_pc <= alu1_newpc[31:0];
end
else if (new_pc_stall==1'b0 && alu2_newpc[32]==1'b1)
begin
new_pc_stall <= 1'b1;
new_pc <= alu2_newpc[31:0];
end
new_pc_stall <= 1'b1;
new_pc <= alu2_newpc[31:0];
end
else if (new_pc_stall==1'b0 && alu3_newpc[32]==1'b1)
begin
new_pc_stall <= 1'b1;
new_pc <= alu3_newpc[31:0];
end
new_pc_stall <= 1'b1;
new_pc <= alu3_newpc[31:0];
end
else
begin
new_pc <= new_pc + 32'h0000_0004;
new_pc_stall <= 1'b0;
end
begin
new_pc <= new_pc + 32'h0000_0004;
new_pc_stall <= 1'b0;
end
end
end // Register writebacks
@@ -422,68 +434,68 @@ end // Register writebacks
//
//------------------------------------------------------------------------
MCLR5_alu mclr5_alu0
MCLR5_alu mclr5_alu0
(
.OPCODE (alu0_opcode),
.PC (alu0_pc),
.RS1 (alu0_rs1),
.RS2 (alu0_rs2),
.RD (alu0_rd),
.NEWPC (alu0_newpc),
.LOAD_DATA (alu0_load_data),
.STORE_DATA (alu0_store_data),
.LOAD_REQ (alu0_load_req),
.STORE_REQ (alu0_store_req),
.LOAD_STORE_ADDRESS (alu0_load_store_address)
.OPCODE (alu0_opcode),
.PC (alu0_pc),
.RS1 (alu0_rs1),
.RS2 (alu0_rs2),
.RD (alu0_rd),
.NEWPC (alu0_newpc),
.LOAD_DATA (alu0_load_data),
.STORE_DATA (alu0_store_data),
.LOAD_REQ (alu0_load_req),
.STORE_REQ (alu0_store_req),
.LOAD_STORE_ADDRESS (alu0_load_store_address)
);
MCLR5_alu mclr5_alu1
MCLR5_alu mclr5_alu1
(
.OPCODE (alu1_opcode),
.PC (alu1_pc),
.RS1 (alu1_rs1),
.RS2 (alu1_rs2),
.RD (alu1_rd),
.NEWPC (alu1_newpc),
.LOAD_DATA (),
.STORE_DATA (),
.LOAD_REQ (alu1_load_req),
.STORE_REQ (alu1_store_req),
.LOAD_STORE_ADDRESS ()
.OPCODE (alu1_opcode),
.PC (alu1_pc),
.RS1 (alu1_rs1),
.RS2 (alu1_rs2),
.RD (alu1_rd),
.NEWPC (alu1_newpc),
.LOAD_DATA (),
.STORE_DATA (),
.LOAD_REQ (alu1_load_req),
.STORE_REQ (alu1_store_req),
.LOAD_STORE_ADDRESS ()
);
MCLR5_alu mclr5_alu2
MCLR5_alu mclr5_alu2
(
.OPCODE (alu2_opcode),
.PC (alu2_pc),
.RS1 (alu2_rs1),
.RS2 (alu2_rs2),
.RD (alu2_rd),
.NEWPC (alu2_newpc),
.LOAD_DATA (),
.STORE_DATA (),
.LOAD_REQ (alu2_load_req),
.STORE_REQ (alu2_store_req),
.LOAD_STORE_ADDRESS ()
.OPCODE (alu2_opcode),
.PC (alu2_pc),
.RS1 (alu2_rs1),
.RS2 (alu2_rs2),
.RD (alu2_rd),
.NEWPC (alu2_newpc),
.LOAD_DATA (),
.STORE_DATA (),
.LOAD_REQ (alu2_load_req),
.STORE_REQ (alu2_store_req),
.LOAD_STORE_ADDRESS ()
);
MCLR5_alu mclr5_alu3
MCLR5_alu mclr5_alu3
(
.OPCODE (alu3_opcode),
.PC (alu3_pc),
.RS1 (alu3_rs1),
.RS2 (alu3_rs2),
.RD (alu3_rd),
.NEWPC (alu3_newpc),
.LOAD_DATA (),
.STORE_DATA (),
.LOAD_REQ (alu3_load_req),
.STORE_REQ (alu3_store_req),
.LOAD_STORE_ADDRESS ()
.OPCODE (alu3_opcode),
.PC (alu3_pc),
.RS1 (alu3_rs1),
.RS2 (alu3_rs2),
.RD (alu3_rd),
.NEWPC (alu3_newpc),
.LOAD_DATA (),
.STORE_DATA (),
.LOAD_REQ (alu3_load_req),
.STORE_REQ (alu3_store_req),
.LOAD_STORE_ADDRESS ()
);

98
MCLR5/Core/MCLR5_alu.v
View File

@@ -14,16 +14,28 @@
//
//------------------------------------------------------------------------
//
// Copyright (C) 2018 by Ted Fried info@MicroCoreLabs.com
// Copyright (c) 2020 Ted Fried
//
// Permission to use, copy, modify, and distribute this software and its
// documentation for any purpose and without fee is hereby granted, provided
// that the above copyright notice appear in all copies and that both that
// copyright notice and this permission notice appear in supporting documentation.
// This software is provided "as is" without express or implied warranty.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
//------------------------------------------------------------------------
//
// Modification History:
// =====================
//
@@ -115,9 +127,9 @@ assign bge_taken = ($signed(RS1) >= $signed(RS2)) ? 1'b1 : 1'b0;
assign bltu_taken = (RS1 < RS2) ? 1'b1 : 1'b0;
assign bgeu_taken = (RS1 >= RS2) ? 1'b1 : 1'b0;
assign pc_adjusted = PC - 4'h4; // Subtracts pipelined PC to the true PC
assign STORE_DATA = RS2;
@@ -126,48 +138,48 @@ always @* begin
32'b???????_?????_?????_???_?????_01101?? : RD = { 1'b1 , {u_immediate[31:12] , 12'b0 } } ; // LUI
32'b???????_?????_?????_???_?????_00101?? : RD = { 1'b1 , PC + {u_immediate[31:12] , 12'b0 } } ; // AUIPC
32'b???????_?????_?????_???_?????_11011?? : RD = { 1'b1 , PC + 3'h4 } ; // JAL
32'b???????_?????_?????_???_?????_11001?? : RD = { 1'b1 , PC + 3'h4 } ; // JALR
32'b???????_?????_?????_000_?????_00100?? : RD = { 1'b1 , RS1 + i_immediate } ; // ADDI
32'b???????_?????_?????_010_?????_00100?? : RD = { 1'b1 , slti_true } ; // SLTI
32'b???????_?????_?????_011_?????_00100?? : RD = { 1'b1 , sltiu_true } ; // SLTIU
32'b???????_?????_?????_100_?????_00100?? : RD = { 1'b1 , RS1 ^ i_immediate } ; // XORI
32'b???????_?????_?????_110_?????_00100?? : RD = { 1'b1 , RS1 | i_immediate } ; // ORI
32'b???????_?????_?????_111_?????_00100?? : RD = { 1'b1 , RS1 & i_immediate } ; // ANDI
32'b???????_?????_?????_001_?????_00100?? : RD = { 1'b1 , slli_result } ; // SLLI
32'b?0?????_?????_?????_101_?????_00100?? : RD = { 1'b1 , srli_result } ; // SRLI
32'b?1?????_?????_?????_101_?????_00100?? : RD = { 1'b1 , srai_result } ; // SRAI
32'b?0?????_?????_?????_000_?????_01100?? : RD = { 1'b1 , RS1 + RS2 } ; // ADD
32'b?1?????_?????_?????_000_?????_01100?? : RD = { 1'b1 , RS1 - RS2 } ; // SUB
32'b???????_?????_?????_001_?????_01100?? : RD = { 1'b1 , sll_result } ; // SLL
32'b???????_?????_?????_010_?????_01100?? : RD = { 1'b1 , slt_true } ; // SLT
32'b???????_?????_?????_011_?????_01100?? : RD = { 1'b1 , sltu_true } ; // SLTU
32'b???????_?????_?????_100_?????_01100?? : RD = { 1'b1 , RS1 ^ RS2 } ; // XOR
32'b?0?????_?????_?????_101_?????_01100?? : RD = { 1'b1 , srl_result } ; // SRL
32'b?1?????_?????_?????_101_?????_01100?? : RD = { 1'b1 , sra_result } ; // SRA
32'b???????_?????_?????_110_?????_01100?? : RD = { 1'b1 , RS1 | RS2 } ; // OR
32'b???????_?????_?????_111_?????_01100?? : RD = { 1'b1 , RS1 & RS2 } ; // AND
32'b???????_?????_?????_010_?????_00000?? : RD = { 1'b1 , LOAD_DATA } ; // LW
default : RD = { 1'b0 , 32'h0000_0000 } ;
32'b???????_?????_?????_???_?????_11011?? : RD = { 1'b1 , PC + 3'h4 } ; // JAL
32'b???????_?????_?????_???_?????_11001?? : RD = { 1'b1 , PC + 3'h4 } ; // JALR
32'b???????_?????_?????_000_?????_00100?? : RD = { 1'b1 , RS1 + i_immediate } ; // ADDI
32'b???????_?????_?????_010_?????_00100?? : RD = { 1'b1 , slti_true } ; // SLTI
32'b???????_?????_?????_011_?????_00100?? : RD = { 1'b1 , sltiu_true } ; // SLTIU
32'b???????_?????_?????_100_?????_00100?? : RD = { 1'b1 , RS1 ^ i_immediate } ; // XORI
32'b???????_?????_?????_110_?????_00100?? : RD = { 1'b1 , RS1 | i_immediate } ; // ORI
32'b???????_?????_?????_111_?????_00100?? : RD = { 1'b1 , RS1 & i_immediate } ; // ANDI
32'b???????_?????_?????_001_?????_00100?? : RD = { 1'b1 , slli_result } ; // SLLI
32'b?0?????_?????_?????_101_?????_00100?? : RD = { 1'b1 , srli_result } ; // SRLI
32'b?1?????_?????_?????_101_?????_00100?? : RD = { 1'b1 , srai_result } ; // SRAI
32'b?0?????_?????_?????_000_?????_01100?? : RD = { 1'b1 , RS1 + RS2 } ; // ADD
32'b?1?????_?????_?????_000_?????_01100?? : RD = { 1'b1 , RS1 - RS2 } ; // SUB
32'b???????_?????_?????_001_?????_01100?? : RD = { 1'b1 , sll_result } ; // SLL
32'b???????_?????_?????_010_?????_01100?? : RD = { 1'b1 , slt_true } ; // SLT
32'b???????_?????_?????_011_?????_01100?? : RD = { 1'b1 , sltu_true } ; // SLTU
32'b???????_?????_?????_100_?????_01100?? : RD = { 1'b1 , RS1 ^ RS2 } ; // XOR
32'b?0?????_?????_?????_101_?????_01100?? : RD = { 1'b1 , srl_result } ; // SRL
32'b?1?????_?????_?????_101_?????_01100?? : RD = { 1'b1 , sra_result } ; // SRA
32'b???????_?????_?????_110_?????_01100?? : RD = { 1'b1 , RS1 | RS2 } ; // OR
32'b???????_?????_?????_111_?????_01100?? : RD = { 1'b1 , RS1 & RS2 } ; // AND
32'b???????_?????_?????_010_?????_00000?? : RD = { 1'b1 , LOAD_DATA } ; // LW
default : RD = { 1'b0 , 32'h0000_0000 } ;
endcase
casex (OPCODE)
32'b???????_?????_?????_010_?????_00000?? : LOAD_STORE_ADDRESS = RS1 + i_immediate ; // Loads
32'b???????_?????_?????_010_?????_01000?? : LOAD_STORE_ADDRESS = RS1 + s_immediate ; // Stores
default : ;
32'b???????_?????_?????_010_?????_00000?? : LOAD_STORE_ADDRESS = RS1 + i_immediate ; // Loads
32'b???????_?????_?????_010_?????_01000?? : LOAD_STORE_ADDRESS = RS1 + s_immediate ; // Stores
default : ;
endcase
casex (OPCODE)
32'b???????_?????_?????_010_?????_00000?? : LOAD_REQ = 1'b1 ;
32'b???????_?????_?????_010_?????_01000?? : STORE_REQ = 1'b1 ;
32'b???????_?????_?????_010_?????_01000?? : STORE_REQ = 1'b1 ;
default : begin LOAD_REQ = 1'b0 ; STORE_REQ = 1'b0; end
endcase
@@ -188,9 +200,9 @@ always @* begin
32'b???????_?????_?????_110_?????_11000?? : if (bltu_taken == 1'b1) NEWPC = { 1'b1 , pc_adjusted + b_immediate } ; // BLTU
32'b???????_?????_?????_111_?????_11000?? : if (bgeu_taken == 1'b1) NEWPC = { 1'b1 , pc_adjusted + b_immediate } ; // BGEU
default : NEWPC = { 1'b0 , 32'h0000_0000 } ; // No Branch Taken
default : NEWPC = { 1'b0 , 32'h0000_0000 } ; // No Branch Taken
endcase
@@ -199,7 +211,7 @@ always @* begin
end