17 lines
751 B
Plaintext
17 lines
751 B
Plaintext
Release 14.7 Drc P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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Wed Nov 11 19:11:46 2020
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drc -z MCL86jr.ncd MCL86jr.pcf
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INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance
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with the CLKFX and CLKFX180 outputs of the DCM comp SPARTAN6PLL/dcm_sp_inst,
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consult the device Data Sheet.
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WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
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(RAMB8BWER). 9K Block RAM initialization data, both user defined and
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default, may be incorrect and should not be used. For more information,
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please reference Xilinx Answer Record 39999.
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DRC detected 0 errors and 1 warnings. Please see the previously displayed
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individual error or warning messages for more details.
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