68 lines
2.8 KiB
Plaintext
68 lines
2.8 KiB
Plaintext
Release 14.7 - ngc2edif P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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Reading design EU4Kx32.ngc ...
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WARNING:NetListWriters:298 - No output is written to EU4Kx32.xncf, ignored.
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Processing design ...
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Preping design's networks ...
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Preping design's macros ...
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finished :Prep
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Writing EDIF netlist file EU4Kx32.edif ...
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ngc2edif: Total memory usage is 79384 kilobytes
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Release 14.7 - ngc2edif P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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Reading design MCL86jr.ngc ...
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WARNING:NetListWriters:298 - No output is written to MCL86jr.xncf, ignored.
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Processing design ...
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Preping design's networks ...
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Preping design's macros ...
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WARNING:NetListWriters:306 - Signal bus EU_CORE/carry<16 : 3> on block MCL86jr
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is not reconstructed, because there are some missing bus signals.
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WARNING:NetListWriters:306 - Signal bus
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EU_CORE/eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT<12 : 0> on
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block MCL86jr is not reconstructed, because there are some missing bus
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signals.
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WARNING:NetListWriters:306 - Signal bus EU_CORE/eu_operand0<15 : 5> on block
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MCL86jr is not reconstructed, because there are some missing bus signals.
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finished :Prep
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Writing EDIF netlist file MCL86jr.edif ...
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ngc2edif: Total memory usage is 82712 kilobytes
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Release 14.7 - ngc2edif P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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Reading design EU4Kx32.ngc ...
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WARNING:NetListWriters:298 - No output is written to EU4Kx32.xncf, ignored.
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Processing design ...
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Preping design's networks ...
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Preping design's macros ...
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finished :Prep
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Writing EDIF netlist file EU4Kx32.edif ...
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ngc2edif: Total memory usage is 78744 kilobytes
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Release 14.7 - ngc2edif P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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Reading design MCL86jr.ngc ...
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WARNING:NetListWriters:298 - No output is written to MCL86jr.xncf, ignored.
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Processing design ...
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Preping design's networks ...
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Preping design's macros ...
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WARNING:NetListWriters:306 - Signal bus EU_CORE/carry<16 : 3> on block MCL86jr
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is not reconstructed, because there are some missing bus signals.
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WARNING:NetListWriters:306 - Signal bus EU_CORE/eu_operand0<15 : 5> on block
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MCL86jr is not reconstructed, because there are some missing bus signals.
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finished :Prep
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Writing EDIF netlist file MCL86jr.edif ...
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ngc2edif: Total memory usage is 82840 kilobytes
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Release 14.7 - ngc2edif P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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Reading design EU4Kx32.ngc ...
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WARNING:NetListWriters:298 - No output is written to EU4Kx32.xncf, ignored.
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Processing design ...
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Preping design's networks ...
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Preping design's macros ...
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finished :Prep
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Writing EDIF netlist file EU4Kx32.edif ...
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ngc2edif: Total memory usage is 78744 kilobytes
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