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MicroCoreLabs.Projects/MCL86jr/FPGA/MCL86jr/planAhead.ngc2edif.log
2020-11-11 20:09:27 -08:00

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Release 14.7 - ngc2edif P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading design EU4Kx32.ngc ...
WARNING:NetListWriters:298 - No output is written to EU4Kx32.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file EU4Kx32.edif ...
ngc2edif: Total memory usage is 79384 kilobytes
Release 14.7 - ngc2edif P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading design MCL86jr.ngc ...
WARNING:NetListWriters:298 - No output is written to MCL86jr.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
WARNING:NetListWriters:306 - Signal bus EU_CORE/carry<16 : 3> on block MCL86jr
is not reconstructed, because there are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus
EU_CORE/eu_opcode_jump_src[2]_eu_rom_address[12]_wide_mux_146_OUT<12 : 0> on
block MCL86jr is not reconstructed, because there are some missing bus
signals.
WARNING:NetListWriters:306 - Signal bus EU_CORE/eu_operand0<15 : 5> on block
MCL86jr is not reconstructed, because there are some missing bus signals.
finished :Prep
Writing EDIF netlist file MCL86jr.edif ...
ngc2edif: Total memory usage is 82712 kilobytes
Release 14.7 - ngc2edif P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading design EU4Kx32.ngc ...
WARNING:NetListWriters:298 - No output is written to EU4Kx32.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file EU4Kx32.edif ...
ngc2edif: Total memory usage is 78744 kilobytes
Release 14.7 - ngc2edif P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading design MCL86jr.ngc ...
WARNING:NetListWriters:298 - No output is written to MCL86jr.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
WARNING:NetListWriters:306 - Signal bus EU_CORE/carry<16 : 3> on block MCL86jr
is not reconstructed, because there are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus EU_CORE/eu_operand0<15 : 5> on block
MCL86jr is not reconstructed, because there are some missing bus signals.
finished :Prep
Writing EDIF netlist file MCL86jr.edif ...
ngc2edif: Total memory usage is 82840 kilobytes
Release 14.7 - ngc2edif P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading design EU4Kx32.ngc ...
WARNING:NetListWriters:298 - No output is written to EU4Kx32.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file EU4Kx32.edif ...
ngc2edif: Total memory usage is 78744 kilobytes