diff --git a/Makefile b/Makefile index 99651111..89aa41ac 100644 --- a/Makefile +++ b/Makefile @@ -10,10 +10,10 @@ SRC = system syseng sysen1 sysen2 sysen3 sysnet kshack dragon channa \ spcwar rwg libmax rat z emaxim rz maxtul aljabr cffk das ell ellen \ jim jm jpg macrak maxdoc maxsrc mrg munfas paulw reh rlb rlb% share \ tensor transl wgd zz graphs lmlib pratt quux scheme gsb ejs mudsys \ - draw wl taa tj6 budd sharem + draw wl taa tj6 budd sharem ucode DOC = info _info_ sysdoc sysnet syshst kshack _teco_ emacs emacs1 c kcc \ chprog sail draw wl pc tj6 share _glpr_ _xgpr_ inquir mudman system \ - xfont maxout + xfont maxout ucode moon BIN = sys2 emacs _teco_ lisp liblsp alan inquir sail comlap c decsys moon \ graphs draw datdrw fonts fonts1 fonts2 games macsym maxer1 diff --git a/build/misc.tcl b/build/misc.tcl index 5e4861f5..5785cd9b 100644 --- a/build/misc.tcl +++ b/build/misc.tcl @@ -819,6 +819,14 @@ respond "*" ":link sys1;ts acnvrt,sysbin;cnvrt bin\r" respond "*" ":midas kshack;ts micro_micro\r" expect ":KILL" +# KL10 microcode. +respond "*" ":micro ucode;u1=ucode;its,define,macro,basic,skpjmp,shift,arith,fp,byte,io,eis,blt\r" +expect ":KILL" +respond "*" ":ucnvrt ucode; u1\r" +expect ":KILL" +# Write the RAM file to the front end filesystem: +# :klfedr write ucode;u1 ram + # XXFILE respond "*" ":midas sysbin;xxfile bin_sysen1;xxfile\r" expect ":KILL" diff --git a/doc/moon/klproc.11 b/doc/moon/klproc.11 new file mode 100644 index 00000000..a1902f6e --- /dev/null +++ b/doc/moon/klproc.11 @@ -0,0 +1,144 @@ +.device xgp +.font 1 "lspman;30vr1" +.font 2 "fonts;36vbee" +.font 3 "lspman;30vri1" +.select 1 +.!xgpcommands_";topmar 0;botmar 0;ffcut 1" +.paper size 50000,8500; +.page!height_2000; page!width_70; +.evenleftborder_1400; oddleftborder_1400 +.page frame page!height high page!width wide; +.area text lines 4 to page!height +.place text +. << 1-1/2" margins all around >> << well... >> +.turn on "" for "%", "", "{", "" for "\", "" +. <<  font,  move over,  tab,  flush right,  fill chr >> +{date} +.break skip 2 +.once center select 2 +I.T.S. CRASH PROCEDURE +.skip 500 mills +Find the CRASH LOG book and record the particulars, including +the date, the time, your name, the message that was printed +on the system console, and anything else that seems relevant. + +If the message on the system console is anything other than "KL10 HALTED..." +don't do anything; get a system hacker. If you don't understand the +rest of these directions, don't do anything. Get a system hacker +or leave it down. + +If the message was "KL10 HALTED...", +type DDT . The console should type out +a greater than, period, carriage return. You are now in exec DDT. +Type to get the symbol table. Type the PC number that was +in the KL10 HALTED message and an underscore to get the symbolic location +of the crash. Determine the cause of the crash. If you don't know +how to do this, then don't worry about it. + +If you think the crashed system needs to be saved so a system hacker +can look at it, type Y and wait for a space to echo. +Then type CRASH 3name1 , where 3name1 is a suitable +name based on where it halted. You can use CTRL/F to list the directory +and find what names have already been used. + +Now execute the 3Warm Boot1 procedure. If it fails, try a 3Cold Boot1. +.break skip 1500 mills + +.once center select 2 +PROCEDURE FOR BRINGING DOWN I.T.S. +.skip 500 mills +Find a console and type control-Z. ITS responds with its greeting. +Type :LOGIN DEC (if you are from DEC); otherwise login with your normal +user name. Note that this command begins with a colon. +Alternatively, borrow the console of a user who is already +logged in. + +Type :LOCK . Type 5DOWN. No carriage return is necessary. +Answer the questions. (The "5" is the number of minutes before shutdown.) + +ITS will now type a "going down" message on all consoles. If +all users, including you, log out (by typing control-Z and :LOGOUT) the system will go down right away. + +After it types "ITS NOT IN OPERATION" the lights on the memories will +blink for a while, then the system console will type a carriage return. +You are now in exec DDT. Hitting break then control-C will get you to KLDCP. + +.break skip 1500 mills +.once center select 2 +COLD BOOT PROCEDURE +.skip 500 mills +This procedure is to be used to restart ITS after running +diagnostics or the DEC system, after a power failure, +or after the warm boot procedure has been tried and found wanting. + +Make plenty damn sure the right disks are mounted. Currently +"ITS PK0 #0 + KLDCP" should be on unit 0, not write-protected, +"ITS PK1 #1" should be on unit 1, not write-protected, and +"ITS SECONDARY PACK #13" should be on unit 2, not write-protected. + +If there was a power failure, some circuit breakers may need to be reset. +Push stop on disk unit 0, wait until it stops spinning, then +open the back and turn "CB1" (lower right corner) off and on. +Then push start. If there are no lights lit on the disk DF10C +(second box from the left on the right-hand side), open its rear door +and reset the white circuit breaker near the bottom of the inside +of the door. Check the +3fault1 light on the KL10. If it is on, open the rear door +of the right-hand KL10 cabinet and check the fault lights on +the power control. (Column of LED's near the bottom of the cabinet.) + +Push the DISK button on the KL10, to reload KLDCP. +If it doesn't work, check the top of the ENABLE switch is pushed in. +If this fails, try doing the preceding paragraph. +If it wins, "DECSYSTEM10 DIAGNOSTIC CONSOLE" will be typed out on +the system console. + +Type RP0 . + +Type J KLINIT . +Wait for a prompt. (Several lines will be typed +out first.) If a "2-way interleave" note is on the console, use KLINI2 +instead of KLINIT. + +If, while running KLINIT you get a message such as ?10 ERR ADR=nn COR=nn ACT=nn +there is probably a failing memory. Get help. + +Type J NTSDDT . If this responds with +I NTSDDT , then +you are winning and exec ddt is now running. Otherwise, get a system +hacker. + +Reload the I/O pdp11 by typing L BOOT11 , wait for +blank line, type G, wait for blank line. If you get file not +found (FNF), try L BOOT11 . + +Continue with the warm boot procedure. + +.break skip 1500 mills +.once center select 2 +WARM BOOT PROCEDURE +.break skip 500 mills +Type L 3sys1 , where 3sys1 is the name +of the current system, which will be found on a punch card on the LA36. +Type G. It should reply "SALVAGER.nnn", then +after a half minute it should say "ITS IN OPERATION". +If it says "*** ERROR SYSTEM MAY NOT BE BROUGHT UP ***", +or any other ominous error message, do not attempt +to do anything further. Get a system hacker. + +If it types "ITS IN OPERATION" but then doesn't seem to do anything +further, you may need to reload the I/O pdp11. See the Cold Boot procedure. + +Usually it types out "IT IS NOW ..." and the date and time. If the +.<> +machine has been powered off, it will ask you to enter the date and time. +If this happens, or the date or time it prints is way off (shouldn't happen), +you can set the time by going to the Data Point and hitting control Z. +When you get the greeting, type :LOGIN PDSET . +Type the date in the form "3yymmdd1D". Type the time in the form +"3hhmmss1T". Type . Type Q . +Note that the system console will type out the date, time, and day of +the week. Be sure to check this to verify that you got it right. +.break skip 300 mills +.comment +  \ No newline at end of file diff --git a/doc/sysdoc/kl.hung b/doc/sysdoc/kl.hung new file mode 100755 index 00000000..17f5f293 --- /dev/null +++ b/doc/sysdoc/kl.hung @@ -0,0 +1,30 @@ +Copyright (c) 1999 Massachusetts Institute of Technology +See the COPYING file at the top-level directory of this project. +------------------------------ +Date: Sat, 14 Jul 84 02:43 EDT +From: David A. Moon +To: alan at MIT-MC.ARPA +cc: bug-its at MIT-MC.ARPA +Re: ITS seemed to be looping + +Things to try: + + Raise switch 0 (the switch 0 on the left). If this goes to DDT, it's + taking clock interrupts. + + Hit Break and type PC . If I remember correctly, you can read + the PC this way without halting the machine. There are some other status-type + commands; PCF is the PC flags, PI is the interrupt status. + + Hit Break and type SP . This stops the machine cleanly (between + instructions). If this works, the microcode isn't looping. Now you can + get the PC then type DDT (or ST 774000) to get into DDT and decode that PC. + + If the microcode is looping the SM command will restart it. This also does + nasty things like resetting the I/O bus. I think it preserves the PC though. + + There is a command file, J KLHUNG, which prints out everything in sight. 90% + of what it prints is worthless, but it includes micro and macro PCs. + +I believe there is a piece of paper taped to the machine that tells you to +do J KLHUNG. Of course there are a lot of pieces of paper taped to the machine! diff --git a/doc/sysdoc/kl10.flklor b/doc/sysdoc/kl10.flklor new file mode 100755 index 00000000..9ec72a16 --- /dev/null +++ b/doc/sysdoc/kl10.flklor @@ -0,0 +1,55 @@ +Copyright (c) 1999 Massachusetts Institute of Technology +See the COPYING file at the top-level directory of this project. +------------------------------ + KL10 Folklore + +Sometimes an MF10 memory gets hung. Often the INC RQ light will be +on. Sometimes raising the RESET switch inside the memory's front door +will help; sometimes a module in the port control is fried. (Any of +several modules.) + +TU41 blower belt has to correct belt, has to not be worn out, and has +to have pulleys aligned. Otherwise it drops off or breaks and tape +rotates backwards. + +RP04 oscillating seeks & Maytag mode when loading => tachometer output +needs to be adjusted. + +When powering machine back on, circuit breaker in disk DF10 may trip. + +When powering machine back on, sometimes disk #0 needs to be stopped, +powered off and on, and started again, to reset the two-massbus +switch. + +If DECtape motor doesn't win, may be G848 seating problem. + +If kicking the LA36 causes power fail, "power warn" lead to top left +edge of CPU backplane needs to be disconnected. (Apparently the other +end is unconnected.) [Missing ECO in 863.] + +Bad door-open switches (?) in MF10. Memories have to be operated with +over-ride turned on. + +Apparently power supplies in CPU and IO box can drift voltages. + +Apparently air-flow sensors can fail sporadically. I am told that +disconnecting one => indication of good airflow. + +RP04 attention/error conditions are super-random. + +Often mysterious marginality is caused by bad seating of modules. + +CONO'ing a PI channel off doesn't necessarily prevent it from +interrupting. It works to have each interrupt routine do CONSO to make +sure the channel is enabled, and dismiss if not. + +Before running a memory diagnostic, do PE0, because the memory +diagnostics don't know how to handle parity faults. + +MF10's always fail solidly. + +Obscure cases in the microcode tend to have bugs. E.g. you could +interrupt out of a PI cycle, hence BLKI/BLKO as interrupt instructions +tended to be flakey. + + \ No newline at end of file diff --git a/doc/sysdoc/kl10.info b/doc/sysdoc/kl10.info new file mode 100755 index 00000000..d201bbca --- /dev/null +++ b/doc/sysdoc/kl10.info @@ -0,0 +1,15 @@ +Copyright (c) 1999 Massachusetts Institute of Technology +See the COPYING file at the top-level directory of this project. +------------------------------ +MOON@MIT-MC 11/17/75 17:30:16 Re: HANDY THINGS TO KNOW ABOUT KL10 +To: [.INFO.;KL10 INFO] at MIT-MC, MOON at MIT-MC +[1] WHEN RUNNING MEMORY DIAGNOSTICS, USE 'PE' COMMAND +TO TURN OFF PARITY CHECKING. +[2] WHEN RUNNING ANY DIAGNOSTIC, EVEN THE 'DG' SERIES, +YOU HAVE TO 'P U.RAM'. +[3] WHEN RUNNING DDDFA THE CHANNEL HAS TO BE IN KA + MODE. THIS IS A BUG IN THE PROGRAM. +[4] WHEN POWERING THE SYSTEM ON, THE LAST THING TO BE +TURNED ON HAS TO BE RP04 #0. OTHERWISE THE PDP11 CAN'T +ACCESS THAT DISK FOR SOME REASON. + diff --git a/doc/ucode/1proc.plan b/doc/ucode/1proc.plan new file mode 100755 index 00000000..fd94608a Binary files /dev/null and b/doc/ucode/1proc.plan differ diff --git a/doc/ucode/u126.doc b/doc/ucode/u126.doc new file mode 100755 index 00000000..9fbfc496 --- /dev/null +++ b/doc/ucode/u126.doc @@ -0,0 +1,104 @@ + U.DOC -- Third release, edit 126 +January 16, 1976 + Copyright 1976, Digital Equipment Corp., Maynard, Mass. + 1.0 SUMMARY + 1.1 Edit version 126 is the third release of U, the KL10 + microcode. + 1.2 U is not dependent on any monitor, but because of + hardware differences between the various -10 + processors, a monitor must be built specifically for + the KL10. It has been tested with the 6.02 monitor + and the TOPS-20 version 1 monitor. U has no DATE75 + dependencies. + The following are known deficiencies in U 126: + U 126 will not work correctly with processor + revision levels less than 6. This will not + ordinarily be a problem, because this release is part + of rev 7a and rev 8, and should therefore be applied + to machines already at rev 6; if there is any doubt + whether a machine has been kept up to ECO level, + however, customers should check before installing U + 126. The symptom of this failure is that the PC + doesn't get loaded if a page failure occurs on an + instruction fetch, and therefore the instruction + which preceeded the page failure gets performed again + on return from the page fault handler. + If rev 8 is installed U 126 is necessary. + KLpaging does not work with the cache on, because + there is too much time from "REQ SV.VMA" till + "RETURN0". the fix (as yet untested or installed): + =0 + PGRST2: BR/AR,AR_ARX, + ARX_SV.ARX,J/PGRST3 + BR/AR,AR_ARX,SC_-SC-1, + ARX_SV.ARX + PGRST3: REQ SV.VMA + SET ACCOUNT EN,RETURN0 + This bug does not matter for 2040 machines (they have + no cache) and thus there is no need to fix it in this + release. It will be fixed in the next release. + The code which performs START and CONTINUE + functions on leaving the HALT loop is incorrectly + coded, in that it sets the interrupt inhibit flag for + one instruction. This results in a processor hang at + WGRANT if there is an interrupt request up when the + processor is continued, and the first instruction + after the continue is an i/o instruction. This + should be fixed in DEFINE.MIC by setting SPEC + INSTR/CONT=0. This fix has received only minimal + testing. It will be fixed in the next release. + U.DOC -- Third release, edit 126 Page 2 + The following problems have been fixed: + Race if page fail occurs while writing FM. + microcode patch eliminates most probable cause, which + is page fail at nicond time while writing ac other + than 0. it does not take care of the possibility + that cond/fm write will glitch at instr 1777 time. + Fixes in several places to set and clear account + enable so as to get repeatable accounting measures of + useful work done. the enable is now cleared for + meter update cycles and KL page refill cycles. the + hardware already takes care of PI cycles. + Spec change to exit from halt loop, so that + AR0-8=0 with AR9-35 non-zero loads AR into PC to + start processor. this is different from executing + JRST because PC flags are cleared. + Fix EIS to tolerate page fail on read of fill byte + in MOVSRJ or binary to decimal conversion. + Integrate opcode counting/timing code under + conditionals. + Fix parity error code to writeback AR on read + pause write error. + Rewrite of DDIV, so that the no-divide test is on + the most significant half of the magnitude of the + dividend, rather than the magnitude of the most + significant half. in the process, save time and + space. Also put in conditional assembly variable + "WRTST" to inhibit write test cycle for instructions + which appear not to need it, and thus to speed them + up. + Fix the S-bus diag instruction. (It was page + faulting on the register function.) + Recode string compare to save space and time. + change defaults for KLpaging to include EIS, exclude + tracks feature. change KLpaging (new spec) to keep + "logically writable" in software bit. recode + KLpaging to eliminate problem of writing hardware + page table before checking for age trap, and + therefore leaving the page accessible after the trap. + The recoding also improves the algorithm in that the + hardware entry includes the W bit set if the core + tables allowed write and the CST indicates written, + even if the current reference was not a write. + Also fix code which writes page table directory, + to get write reference bit from VMA HELD into bit 5 + of saved page fail word. + 1.3 U is implicitly documented in the System Reference + Manual, in that it is an implimentation of a PDP10. + The only other documentation is in the listing and + prints of the KL10 processor. + 1.4 Function of U + U is the microprogram which directs the operation of + the KL10 hardware to emulate the behaviour of a + U.DOC -- Third release, edit 126 Page 3 + PDP10. diff --git a/doc/ucode/ucode.bugs b/doc/ucode/ucode.bugs new file mode 100755 index 00000000..b2866368 --- /dev/null +++ b/doc/ucode/ucode.bugs @@ -0,0 +1,336 @@ +ED@MIT-MC 10/24/79 00:42:03 +To: (BUG ITS) at MIT-MC, (FILE [UCODE;UCODE BUGS]) at MIT-MC +On MC, single-instruction proceed still loses if the +instruction page faults on fetch. Doing +100/ jrst 2000 +2000/ jrst 4000 +... +30000/ jrst 0 +1000G +100>> JRST 2000  results in: +0>> 0 note that 0, being swapped IN, doesn't execute. + +MOON@MIT-MC 05/23/78 22:05:31 +In case you were wondering, the very sporadic lossage where +XCT @(P) executes a random illegal instruction still happens. +Probably XCT FDTB(CH) still loses also. Sigh. + +MOON@MIT-MC 05/08/78 14:56:33 +REVISION 10 FCO SUMMARY + +M8530-3 MAKE 'PHYS REF' ENABLE LOADING OF VMA<13-17> (HOORAY!) + +M8524-4 MAKE 'COND/INSTR ABORT' IOR 'TRAP CYC N' INTO 'TRAP REQ N' (HOORAY!) + +M8513-7 FIX CACHE PARITY ERRORS IN TOPS20 RELEASE 2 (HO HUM) + +M8560-2 SBUS TERMINATION PROBLEMS (ZZZ) + +M8558-3 DITTO (ZZZ) + + +MOON5@MIT-MC 03/10/77 20:26:58 Re: REVISION 9A CONTINUED +ALSO, THE M8563 DMC BOARD IS MODIFIED. DMC5 LOC D5 +CHANGES LOGIC FOR 1 BUS MODE READ-PAUSE-WRITE (I THINK). + +MOON5@MIT-MC 03/10/77 13:51:34 Re: REVISION 9A +(1) ON M8517 MB BOARD, BUFFER CCL CCW BUF WR (BIG DEAL) +(2) ON M8552 DTE20 DPS5 LOC B5 PUT DPS5 TO10 I BIT + DIRECTLY INTO 7432 INSTEAD OF THROUGH FLIP FLOP. +(3) ON M8553 DTE20 CNT CHANGE AROUND TO11 BYTE COUNT + LOGIC IN OBSCURE WAYS, ALSO DELETING SOME UNIBUS + PARITY CRAP. +(4) ON M8554 DTE20 INT2 LOC B4, CLEAR CLK RUN ON TIMEOUT. + ALSO REPLACES THIS 74H74 WITH ANOTHER ONE. + INT1 TOP CENTER AND RIGHT GENERATE MST CLR FROM + PWR FAIL FROM UBUS AC LO. + ALSO CHANGE SIGN OF INPUT TO 9601 AT B3 ON INT2. +NO MICROCODE IMPLICATIONS. DOES THIS MAKE BYTE +TRANSFER MODE WORK OR SOMETHING? + +MOON5@MIT-MC 02/24/77 01:51:11 +REVISION 9 (PUT IN TODAY) FIXES WRITING OF BAD PARITY INTO +FAST MEMORY BY GLITCH AT PAGE FAIL (CLK SBR CALL). + +MOON5@MIT-MC (Sent by ___002@MIT-MC) 02/24/77 01:15:22 +INSTR AT PIBYTE+2 SHOULD HAVE MQ*4 NOT MQ*2 +DOESN'T APPLY TO ONE-DTE20 MACHINE PROBABLY + +MOON 1/28/77 +tried the jpc code again. jumpn tt,(f) caused a page fault +with code of 0 when it shouldn't have (page jumped to was +set up rd only in map in core). theory is that this +is caused by more than 6 ticks between jump fetch and nicond. +can't see right now how to bum jpc code to be faster. + +MOON 9/28/76 +[1] One/proceed page-fault problem will be fixed in Revision 10, +by changing the SCD board to IOR the trap cyc flags back into the +trap req flags instead of jamming them. This is a kludge, but it looks +like it will work. +[2] Tonight teco has been bombing out in various ways. +Once it looked like P was clobbered to 0, another time to a PC +that had problem been POPJed back to. + -- SEE NEXT, MAY BE FIXED + +RMS@MIT-MC 09/17/76 22:16:12 Re: MC hardware lossage. +To: MOON at MIT-MC +An XCT FDTB(CH) with CH/ 123 executed something equivalent to +64240,,507665 instead of what was located at FDTB+123/ JRST FSET. +There were about 60 words in the job that would address-compute to +that value. FDTB 123= 27751. None of those words containing +the suitable garbage were at addresses = 751 mod 1000, but +104751 was off by only 10 . + -- THIS WAS AN I.T.S. BUG, FIXED. (PFA6++) + MOON@MIT-MC 08/19/76 04:51:44 Re: One proceed lossage on KL +To: KLH at MIT-MC +CC: [UCODE;UCODE BUGS] at MIT-MC, GLS at MIT-MC +I've tracked this down. It happens whenever you one-proceed an instruction +that jumps into (or drops into) a page that's not swapped in. There is this +horrible design error in the machine where in this case the PC gets advanced +to point to the instruction that lost, but the flags in LH(PC) [including +one proceed] don't get advanced. So then the flags are one instruction +behind, and you get "two proceed". You can probably get N-proceed by making +a chain of jumps into successive swapped-out pages. + +I don't see any easy (or even moderately hard) way to fix this in the +microcode without breaking something else. (A few months ago I put in +a change which it turns out was only fixing one symptom of this problem.) +We have some hardware changes due to be put in in a week or two that +supposedly fix all outstanding problems; I'm going to try and find out +if they fix this one or if not what can be done about it. + -- SEE ABOVE, TO BE FIXED REV. 10. + +MOON@MIT-MC 07/07/76 16:06:48 Re: HANGING AT PG4++ GETTING EBUS +SET PI CYCLE SETS CON INT DISABLE. CON CLR PI CYCLE, WHICH +IS HOW PI CYCLES THAT DO BLKO AND PNTR DOSN'T OVERFLOW GET +CLEARED, FAILS TO CLEAR CON INT DISABLE. NORMALLY THE NICOND +ON THE FETCH OF THE INTERRUPTED INSTRUCTION CLEARS IT, BUT +IF THERE IS A PAGE FAIL ON THAT INSTRUCTION, IT DOESN'T GET +CLOCKED. HOWEVER, PAGE FAILS MUSTN'T CLEAR CON INT DISABLE, +ONLY PAGE FAULTS. IDEALLY, IT SHOULD BE CLEARED AT PFT, +BUT # ISN'T AVAILABLE. I'LL ADD AN ADDITIONAL INSTRUCTION +AT PFT. + -- FIXED UCODE + +7/1/76 UPDATED TO DEC VERSION 126 (RELEASE 3, REV 8) +TRIED HACKING JPC TO AVOID FM PARITY ERRORS, +BUT I CAN'T WIN. LOSES ON AN AOBJP THAT JUMPS AND +PAGE FAILS. SIGH. JUST GOTTA GET THE HARDWARE FIXED. + +6/9/76 +JRST 12, CHOOSES WHETHER TO SET THE USER OR THE EXEC +JPC BY THE RESTORED USER-MODE FLAG RATHER THAN BY THE +ONE AT THE BEGINNING OF THE INSTRUCTION. SEE BRJMP. +[FIXED 6/9/76] +^_ +MOON@MIT-MC 06/09/76 03:48:51 +TRIED FIXING THE ABORT INSTR LOSSAGE BY MAKING +JRST 12, DO ARX_MEM BEFORE THE NICOND SO AS TO HAVE +CONTROL OVER WHERE THE INSTR HAS TO GET ABORTED FROM. +BUT SINCE THE FLAGS HAVE BEEN SET ALREADY WE BETTER +SET THE PC TOO, BUT THAT BRINGS US RIGHT BACK TO +THE SAME OLD LOSSAGE WITH ABORT INSTR. GRUMBLE! +NEED SOME HACK HERE TO TOUCH THE FROB BEFORE SETTING +THE FLAGS OR SOMETHING... + +[WILL TRY DOING IT WITH THE SR INSTEAD. 6/9/76] +[COMPLETE WINNER, 6/10/76] + + +Date: 8 JUN 1976 0310-PDT +From: Jeff Rubin (JBR @ SU-AI) +Subject: FM Parity Mod +To: moon @ MIT-MC + +In our machine there is an OR gate on the CON5 page producing CON FM WRITE PAR L. +The input to this gate is on pin 9 and comes from E62(14) (CON FM WRITE 18-35 H). +This is changed so that pin 9 comes from -CLK SBR CALL L on pin FN1, pin 10 comes +from E62(15) (CON FM WRITE 18-35 L) and pin 11 comes from -CON CLK B L. The output +is changed to E57(7). The gate is now drawn as an active low AND. In order to +free up connector pin FN1, CON MBOX WAIT H is deleted from FN1 (was not used). +The terminator that was on E57(9) remains there and terminates -CLK SBR CALL L. +The terminator on the CTL1 page on -CLK SBR CALL L is deleted. Finally, a twisted +pair is added from CTL1 4A36F1 (-CLK SBR CALL L) to CON5 4F35N1. + +I don't exactly see why they bothered to gate the signal with the clock since +in our machine at least, it is already gated with the clock on the APR page +at the input to the RAM. The real fix, I think, is that when the CLK page causes +a CLK INSTR 1777, it causes the CRAM to thrash while the clock is low (i.e. CON +FM WRITE PAR is enabled) and a glitch on the write parity signal gets through to +the RAM. + +------- + + +Date: 5 JUN 1976 2236-PDT +From: Jeff Rubin (JBR @ SU-AI) +Subject: FM parity errors +To: moon @ MIT-MC + +I installed a mod that Eggers told me over the phone and it seems to +have cleared up our FM parity error problem. We have only run for about +1 1/2 hours since installing the mod but no parity error in that time. +If you want I can send you a description of the mod, although I'm not +sure what differences there are between our machines in the same area. + +------- + +Date: 1 JUN 1976 2330-PDT +From: Jeff Rubin (JBR @ SU-AI) +Subject: KL10 ARX parity errors +To: moon @ MIT-MC + +I noticed that your microcode ignores ARX parity errors. I recently discovered +one cause of them and was wondering if you had discovered the same thing. Ours +was caused by executing an instruction in the last location of a page when the +mapping information for the next page is not yet in the page table ram and the +A field of the D ram for the instruction is I-PF. It starts the prefetch and +gets a page fault due to no PT DIR match. But the EBOX continues to execute +microcode and doesn't do an MB WAIT right away. When the MBOX gets the page fault +it sets CLK MBOX RESP which loads the ARX with a bad parity zero and also sets +CON ARX LOADED. There is a term called CLK INSTR 1777 which attempts to hold +off CON ARX LOADED, but it isn't set until the EBOX does an MB WAIT which causes +CLK PAGE FAIL which eventually sets CLK INSTR 1777. I called Eggers and he +said he hadn't heard of this bug before. + +Yes, indeed, we have made quite a bit of progress running the system on the +KL. We are currently being hacked by some (prbably software) bug having to do +with turning on cacheing for a job and by FM parity errors. Eggers told me +of one way that he heard FM parity errors can be caused, but I haven't checked +it out yet. + +------- +KLH@MIT-AI (___022) 06/04/76 03:00:16 +PUSHJ P,FOO AND ^N PROCEEDED FOR TWO INSTRUICTIONS!! + +MOON5@MIT-MC 06/04/76 00:01:29 +ONE PROCEED DOES INFINITE +PROCEED IF PAGE FAULT ON THE INSTRUCTION. + +THIS IS A HARDWARE BUG - PGF4+20 OR SO DOES "ABORT INSTR", +WHICH RESETS THE TRAP FLAGS IN THE PC FROM THE TRAP CYCLE +FLAGS. HOWEVER, IF THE PAGE FAULT WAS ON THE INSTRUCTION +BEING FETCHED, THE DISP/NICOND FAILED TO CLOCK THE TRAP +CYCLE FLAGS FROM THE PC FLAGS. THE TRAP REQUEST BITS IN +THE PC FLAGS WERE STILL SET, BUT THE ABORT INSTR CLEARED +THEM. ABORT INSTR SHOULD NOT BE DONE IF THE PAGE FAULT +CAME FROM NICOND. I'M NOT SURE HOW ONE DETECTS THAT. + +ONE DETECTS THAT BY LOOKING AT THE "FETCH" BIT IN VMA. +SKIPPING THE ABORT INSTR IS HARD TO DO BECAUSE PFT MIGHT +DECIDE TO TAKE AN INTERRUPT INSTEAD. I TRIED TO UNABORT +THE INSTR BY DOING A DISP/NICOND WITH 1111 IN LOW J, +BUT THAT CLOBBERED THE PC TO THE ADDRESS OF THE PTW. +THIS MAY REQUIRE A HARDWARE MOD TO FIX. +[FIXED 6/9/76] + +MOON@MIT-MC 05/30/76 16:10:30 Re: HANGING WAITING FOR EBUS +THIS APPEARS TO BE DUE TO ATTEMPTING TO GRAB THE EBUS +TO TURN OFF THE PI TO TAKE A PAGE FAULT WHILE CON INT DISABLE +IS SET, BUT CON PI CYCLE IS NOT SET. THE PI BOARD THINKS IT'S +OK TO INTERRUPT, BUT THE CON BOARD THINKS IT ISN'T, SO THE +PI BOARD GRABS THE EBUS TO GIVE AN INTERRUPT, BUT THE CON +BOARD WON'T ADMIT TO THE MICROCODE THAT THERE IS AN INTERRUPT, +SO UCODE HANGS WAITING FOR THE EBUS TO BECOME AVAILABLE. + +AN EXTRA INSTRUCTION "CLR INTRPT INH" AT "PIFET" IN "IO" +HAS BEEN PUT IN AND WILL PROBABLY FIX THIS. (I THINK IF +YOU TAKE A DTE OR METER INTERRUPT, GO TO PIFET, PAGE +FAULT ON THE FETCH OF THE INSTRUCTION INTERRUPTED OUT OF, +AND TAKE ANOTHER INTERRUPT JUST THEN, WAS WHEN IT LOST.) +[FIXED 5/30/76] + +MOON@MIT-MC 05/30/76 16:06:56 Re: POP AC,AC LOSES +FIXED 5/30/76. + +MOON@MIT-MC 05/16/76 00:03:50 Re: MOVN CAUSES BAD PAGE FAILS +FIXED BY KLUDGING MOVN, MOVNI TO BE DIFFERENT FROM MOVNM +AND MOVNS AND SAVE A CYCLE (SIMILARLY FOR MOVM, MOVMI) + +moon@MIT-MC 02/17/76 17:04:24 +To: [UCODE;UCODE BUGS] at MIT-MC +CC: MOON at MIT-MC +When get no valid match on page fail, try clearing 8P instead +of 4P so as to get both valid bits set. Jud thinks this may +neutralize the paging bug. +[Done, 5/9/76] + +MOON5@MIT-MC 02/13/76 23:19:33 +OCCASIONAL LOSS OF TRAPS +[One proceed not setting %PSINH, lose if page fault, fixed 5/9/76] + +MOON@MC 02/12/76 02:22:43 +THE JPC FEATURE CAUSES FM PAR TO BE WRITTEN WRONG AT "AOJJPC:". +PUTTING IN A TIME/3T MAKES IT HAPPEN GROSSLY OFTEN. +I SUSPECT THE LOSS INVOLVES A PAGE FAIL ON THE ALREADY-STARTED +FETCH OF THE NEXT INSTRUCTION. SEE (CON4) CON AR 36, WHICH +SHOULD BE ZERO DURING WRITING INTO FAST MEMORY. WE'LL SEE WHAT +HAPPENS IN REV 7. +[Still loses, I think, 5/7/76] + +MOON@MC 02/11/76 18:30:35 +To: [UCODE;UCODE BUGS] at MC +CC: BUG-ITS at MC +CURRENTLY INSTALLED UCODE IS MISSING JPC FEATURE FOR SOME REASON. + +ALSO, CAN'T ONE-PROCEED THROUGH A UUO THAT SYSTEM RETURNS TO USER. +HOWEVER, ONE PROCEEDING THROUGH AN LUUO WORKS. [Fixed] + +MOON@MC 02/03/76 17:02:25 Re: PAGE LOSSAGE +1000-3000 LOSES +1000-3000-5000-7000 WINS +1000-3000-15000-17000 LOSES + +THE PROBLEM IS THAT PAGE FAIL HOLD COMES ON AND GENERATES +PT DIR CLR, WHICH ENABLES BOTH VALID BIT RAMS (PAG3). +ABOUT 10-20 NANOSEC LATER, - PT MATCH COMES UP AND PF CODE +01 IN H COMES ON. THIS GETS STROBED INTO THE EBUS REGISTER +BY LOAD EBUS REG (CSH3), WHICH LASTS 40 NANOSEC STARTING +ABOUT 10 NANOSECONDS AFTER PF CODE 01 IN H COMES UP. +THIS DERIVES FROM PAGE FAIL T2, WHICH IS TOO LATE. +AS FAR AS I CAN SEE, THE ONLY WAY TO FIX THIS IS THE ORIGINALLY- +PROPOSED MOD TO THE PAG BOARD TO "AND" PAGE FAIL HOLD WITH +CON KI10 PAGING MODE IN THE GENERATION OF PT DIR CLR. REV.7 +DOESN'T CHANGE THE TIMING SUFFICIENTLY. + +DEC HAS BEEN INFORMED. + +KNOWN BUGS/MISSING FEATURES IN ITS KL10 MICROCODE + +FAST MEMORY PARITY LOSSAGE IN JPC MICROCODE. +I PUT A TIME/3T AT AOJJPC WHICH APPEARS TO HAVE FIXED IT +(WILL HAVE TO WAIT AND SEE IF ANY MORE FM PAR LOSSAGE +HAPPENS.) IF SO, A TIME/3T MAY HELP WITH THE NXT INSTR +LOSSAGE, TOO. + +SEE MOON;CACHE LOSSAG. -- FIXED + +PAGE LOSSAGE - 1000/ JRST 2000 2000/JRST 1000 DOES PAGE + REFILL EVERY 5 MICROSEC. CAN'T HAVE EVEN/ODD + PAIR IN PT AT SAME TIME. - PT MATCH IS COMING UP. + AS FAR AS I CAN TELL ALL THE RIGHT THINGS ARE GOING + INTO THE PT DIR; UNFORTUNATELY NOT EVERYTHING + COMES OUT TO THE BACKPLANE. FAILS ON BOTH + OF OUR COPIES OF M8520. + +M.A.R. DOESN'T WORK + REV.7 SHOULD FIX THIS BY MAKING 'PF EBOX HANDLE' WORK. + +ONE PROCEED + WORKS BUT STILL UNSOLVED IS THE PROBLEM OF LOSING + PDL OR ARITH OVERFLOW TRAP WHEN ONE-PROCEEDING. + +J.P.C. -- WHEN TURNED ON, SYS WON'T RUN + APPARENTLY IT SCREWS UP WHEN IN USER MODE? + 6 FEB 76 - SINGLE-JPC MODE WORKS! RING MODE + HAS NOT BEEN TESTED. + +VECTOR INTERRUPTS OF THE BLKO VARIETY PICK +UP THE JSR FROM 40+2*N INSTEAD OF LOC+1. +THIS HAS TO BE FIXED TO MAKE THE IMPTERFACE WORK. + --> THIS HAS BEEN FIXED BUT NOT TESTED. + +TURN ON UCODE STATE 01 AND UCODE STATE 03 DURING PAGE FAIL + +TROUBLE WITH IMULI ? HAS THIS BEEN FIXED? diff --git a/doc/ucode/ucode.info b/doc/ucode/ucode.info new file mode 100755 index 00000000..58da9072 Binary files /dev/null and b/doc/ucode/ucode.info differ diff --git a/src/ucode/arith.6 b/src/ucode/arith.6 new file mode 100755 index 00000000..9a1d981f --- /dev/null +++ b/src/ucode/arith.6 @@ -0,0 +1,367 @@ +.TOC "ADD, SUB" + + .DCODE +270: R-PF, AC, J/ADD + I-PF`Y2D + RPW, M, J/ADD + RPW, B, J/ADD + .UCODE + +=00**** +ADD: AR_ARPaYAD/A+B,AD ǧlI += + + + .DCODE +274: R-PF, AC, J/SUB + I-PF, AC,2ӫB + RPW, M, J/SUB + RPW, B, J/SUB + .UCODE + +=00**** +SUB: AR_AC !R_AR += AR_AR-BR,AD FLAGS,EXIT + .TOC "MUL, IMUL" + + .DCODE +220: R, ACe/MUL + I, AC, J/3j̓ + RW, M, J/IMUL + RW, B, J/IMUL + .UCODE + +.IFNOT/IMUWOT +=00*01* +IMULI: +.IF/IMULI.* =00*000 +IMULI: SKP AR18,GEN AC0,SIGNS DISP, ;OPTIMIZE SPECIAL CASE + TIME/3T,SC_#,#/17. +=010 MQ_AR,AR_AC0, ;HERE FOR IMULI OF + BY + + CLR ARX,FE_#,#/-9., ; 9 STEPS WILL DO + CALL,J/M)Յ +.ENDIF/IMULI.OPT +IMUL: MQ_AK ҿAC0, ;M'IER T&Y M'CAND TO AR + CLR ARX,oY#/-18., + CALL,J/MULSUB ;CALL MULTIPLY SUBROUTINE +.IF/IMULI.OPT +=110 AR_SHIFT,SKP AR NE,INH CRY18, ;HERE FROM IMULI + I FETCH,J/MUL1 ; AFTER SHORT MULTIPLY +.ENDIF/IMULI.OPT + SC_#,#/35.,SKP AR SIG ;CHECK OVERFLOW AND STORE += +=1****0 +IMUL2: AR_SHIFT,B WRITE,J/ST6 ;STORE LOW WORD OF PRODUCT + SET AROV,AR_SIGN,J/IMUL2 ;NOTE OVERFLOW... + + + .DCODE +224: R, DBL AC, J/MUL + I, DBL AC, J/MUL + RW, M, J/MUL + RW, DBL B, J/MUL + .UCODE + +=00*000 +MUL: MQ_AR,CLR ARX, ;MULTIPLIER TO MQ + AR_AC0,FE_#,#/-18., ;SETUP MULTIPLICAND AND STEP CNT + CALL,J/MULSUB ;AND GO TO SUBROUTINE +=100 GEN AR*BR,AD/AND,SKP AD0 ;M'IER NEG, CHECK M'CAND & PROD TOO +=110 +MUL1: SC_#,#/35.,EXIT ;STORE DOUBLE RESULT + SET AROV,J/MUL1 ;MUST HAVE SQUARED 400000,,0 += + .TOC "MULTIPLY SUBROUTINE" +; ENTER WITH MULTIPLIER IN MQ, +; MULTIPLICAND IN AR!ARX, MINUS STEP COUNT IN FE +; RETURNS PRODUCT IN AR!ARX!MQ. +; RETURN 4, 6 TELLS SIGN OF MULTIPLIER +; 4 AND 6 ARE USED SO CALLER CAN IGNORE +; DIFFERENCE BY ALIGNMENT OF CALL LOC'N +;[TIME=4+2(-FE)+(# OF ARITH STEPS)] ... IF FE=-18, 40-58. + +MUL "FE_FE+1,DISP/MUL,MQ/MQ*.25" + +MULSUB: BR_AR LONG,AR_0S,ARX_0S, ;M'CAND TO BR LONG, CLEAR PROD + MUL,J/MULP ;START THE MULTIPLICATION +=000 ;GRAB AN 8-WORD BLOCK +MULP: +=011 (AR+ARX+MQ)*2,FE_SC,RETURN6 ;DISCARD REDUNDANT SIGN BIT + +=100 AR_AR*.25 LONG,MUL,J/MULP ;M'IER BITS 00 AFTER POS STEP + AR_(AR+BR)*.25,ARX/ADX*.25, ;01 AFTER + + MUL,J/MULP + AR_(AR-2BR)*.25,ARX/ADX*.25, ;10 AFTER + + MUL,J/MULM + AR_(AR-BR)*.25,ARX/ADX*.25, + MUL,J/MULM ;11 AFTER + + +=000 ;ANOTHER 8-WORD BLOCK FOR +MULM: ; AFTER SUBTRACTION STEPS +=011 (AR+ARX+MQ)*2,FE_SC,RETURN4 ;M'IER WAS NEGATIVE + +=100 AR_(AR+BR)*.25,ARX/ADX*.25, ;M'IER BITS 00 AFTER NEG STEP + MUL,J/MULP + AR_(AR+2BR)*.25,ARX/ADX*.25, ;01 AFTER - + MUL,J/MULP + AR_(AR-BR)*.25,ARX/ADX*.25, ;10 AFTER - + MUL,J/MULM + AR_AR*.25 LONG,MUL,J/MULM ;11 AFTER - + +;HERE TO CONTINUE A LONG MULTIPLICATION +; WITH PARTIAL PRODUCT IN AR LONG + +MULREE: AD/0S,MUL,J/MULP ;DIVE IN WITHOUT CLOBBERING AR + .TOC "DIV, IDIV" + + .DCODE +230: R, DBL AC, J/IDIV + I, DBL AC, J/IDIV + RW, M, J/IDIV + RW, DBL B, J/IDIV + +234: R, DBL AC, J/DIV + I, DBL AC, J/DIV + RW, M, J/DIV + RW, DBL B, J/DIV + .UCODE + +=00*000 +DIV: BR/AR,ARX+MQ_0.M, ;DIVISOR TO BR + AR_AC1*2,ARL/AD*2, ;LOW DIVIDEND TO AR + CALL.M,J/DIV1 ;GET HIGH DIVIDEND +=10 +IDIV: BR/AR,ARX+MQ_0.M,SC_1, ;DIVISOR TO BR + AR_AC0,ARL/AD,CALL.M, ;DIVIDEND TO AR + SKP AR0,J/DIV2 ;TEST DIVISOR SIGN +=011 +NODIVD: SET NO DIVIDE,J/NOP ;HERE IF DIVIDE IMPOSSIBLE + +=110 ARX_AR,AR_-BRX, ;REMAIN TO ARX, GET CORRECT QUOTIENT + SC_#,#/36.,EXIT + ARX_AR,AR_BRX, ;HERE FOR POS QUOTIENT + SC_#,#/36.,EXIT += +;HERE ON D5ċ TO SET UP DIVIDEND + +DIV1: BRX/ARX,ARX_AR,AR_AC0, ;CLR BRX, DIVIDEND IN AR LONG + FE_#,#/33.,TIME/3T, ;SETUP ITERATION COUNT + SIGNS DItJ_DIVS1 ;ENTER SUBR + +;HERE ON IDIV TO SET UP DIVIDEND. SKIP IF DIVISOR NEG +; ALSO CALLED BY ADJBP +=1****0 +DIV2: BRX/ARX,ARX_SHIFT,AR_SIGLR BRX, DIVIDEND TO AR LONG + FE_#,#/33., ;SETUP LOOP COUNT + SKP AR0,J/DIVS1 ;ENTER SUBR ACCORDING TO SIGNS + BRX/ARX,ARX_SHIFT,AR_SIGN, ;CLR BRX, DIVIDEND TO AR LONG + FE_#,#/33., ;SETUP LOOP COUNT + SKP AR0,J/DIVS2 ;ENTER SUBR ACCORDING TO SIGNS + .TOC "INTEGER DIVIDE SUBROUTINE" +; ENTER WITH SIGNS DISPATCH OF DIVISOR AND DIVIDEND, +; DIVISOR IN BR, BRX CLR; DIVIDEND IN AR!ARX +; STEP COUNT IN FE (# OF QUOTIENT BITS -2) +; IF NO DIVIDE, RETURN 3 WITH IFETCH STARTED +; OTHERWISE, RETURN WITH SIGNED REMAINDER IN AR, +; POSITIVE QUOTIENT IN BRX AND MQ. +; RETURN 6 IF QUOTIENT SHOULD BE NEGATIVE, +; RETURN 7 IF QUOTIENT SHOULD BE POSITIVE. +;[TIME=14+3(FE)+3(D'END NEG)+3(RESTORE REQ'D)+1(REMAINDER NEG)] +; ... IF FE=33, 113-120 + +DIVIDE "FE_FE-1,DISP/DIV,MQ/MQ*2" + +=1**100 +DIVS1: DIVIDE,AR_2(AR-BR), + ARX/ADX*2,J/DIVS3 ;BOTH D'END AND D'SOR POS + AR_-AR LONG,J/DIVS1 ;MAKE POh"IIDEND, THEN CHK +DIVS2: DIVIDE,AR_2(AR+BR), + ARX/ADX*2,J/DIVS4 ;D'END POS, D'SNG + AR_-AR LONG,J/DIVS2 + +=1*010 +DIVS3BbI1"W(R+BR),ARX/ADX*2, + ARL/AD*2,CALL.M,J/DIVLP ;START DIVIDING + I FETCH,RETURN3 ;RETURN TO CALLER WITH NO DIVIDE + + AR_-BR,BRX/ARX,RETURN6 ;D'END NEG, SO NEGATE QUO & REM + BRX/ARX,RETURN7 ;EVERYTHING POSITIVE + + +=1**010 +DIVS4: DIVIDE,AR_2(AR-BR),ARX/ADX*2, + ARL/AD*2,CALL.M,J/DIVLP ;BEGIN DIVISION FOR REAL BITS + I FETCH,RETURN3 ;ABORT FOR IMPOSSIBLE DIVISION + + BRX/ARX,RETURN6 ;NEGATE QUO + AR_-BR,BRX/ARX,RETURN7 ;NEGATE REM + .TOC "BASIC DIVIDE LOOP" +; THE LOOP ITSELF IS AN INNER SUBROUTINE, TO MAKE IT SUITABLE +; FOR USE IN DOUBLE-LENGTH DIVISION. +; THE DOUBLE LENGTH REMAINDER IS RETURNED IN BR!BRX (RESTORED) +; THE SINGLE LENGTH QUOTIENT (LOW PART IF DBL-LEN DIVISION) IN ARX +; RETURN 6 IF QUOTIENT (REALLY AC0.XOR.BR) NEGATIVE, OR 7 IF POSITIVE +;[TIME=12+3(FE)+3(RESTORE REQ'D)] ... IF FE=33, 111-114. + +=1*000 +kLBbIIDE,AR_2(AR+BR),ARX/ADX*2ēVLP + DIVIDE,ARA)YARX/A2YKILP +DIV-: DIVIDE,AR_2(AR-BR),ARX/ADX*2,J/DIVLP +DIV+: DIVIDE,AR_2(AR+BR),ARX/ADX*2,J/DIVLP + DIVIDE,AR_AR+BR,ARX/ADX,J/DIVX +1$֓VA_AR-BR,ARX/ADX,J/DIVX + DIVIDE,AR_AR-BR,ARX/ADX,J/DIVX ;NO SHIFT ON FINAL STEP + DIVIDE,AR_AR+BR,ARX/ADX,J/DIVX + +;HERE AFTER FINAL DIVIDE STEP +; MQ HAS POSITIVE FORM QUOTIENT +; AR!4 AS REMAINDER, EXCEPT THATj UST BE RESTORED IF I$ ; NEGATIVE (IT'S NEGATIVE IF THERE WAS NO CARRY ON FINAL STEP) +; THEIINAL DIVIDEND IS STILL INaY SO WE CHECK ITS SIGN +; TO DETERMINE WHETHER TO NEGATE THE (RESTORED) REMAINDER. + +=1**100 +DIVX: AR_AR+BR LONG ;RESTORE REMAIN WITH POS D'SOR + BR_AR LONG,ARX/MQ,FE_SC, ;LONG REMAIN TO BR, QUO TO ARX + SKP AC0+,RETURN6 ;RETURN TESTING D'END SIGN + AR_AR-BR LONG ;RESTORE REMAIN WITH NEG D'SOR + BR_AR LONG,ARX/MQ,FE_SC, + SKP AC0-,RETURN6 + + +;SUBROUTINE FOR FIRST PART OF LONG DIVISIONS +; ENTER AT DDVSUB WITH SKP BR0 +; RETURN3 IF SHOULD RESUME WITH ADD STEP +; RETURN5 IF SHOULD RESUME WITH SUBTRACT + +=000 +DDVLP: AR_2(AR+BR),ARX/ADX*2,DIVIDE,J/DDVLP + AR_2(AR-BR),ARX/ADX*2,DIVIDE,J/DDVLP +DDVSUB: AR_2(AR-BR),ARX/ADX*2,DIVIDE,J/DDVLP + AR_2(AR+BR),ARX/ADX*2,DIVIDE,J/DDVLP + AR_MQ,MQ_AR,FE_#,#/32.,RETURN3 + AR_MQ,MQ_AR,FE_#,#/32.,RETURN5 + AR_MQ,MQ_AR,FE_#,#/32.,RETURN5 + AR_MQ,MQ_AR,FE_#,#/32.,RETURN3 + .TOC "DOUBLE INcť ARITHMETIC -- DADD, DSUB"MD5  + .DCODE +.IFNOT/DBL.INT +114: I, J/UUO + I, J/UUO + I, J/UUO + I, J/UUO +.IF/DBL.INT +114: R, B/0, J/DASMD ;DADD + R, B/2, J/DASMD ;DSUB + R, B/4, J/DASMD ;DMUL + R, J/DDIV + .UCODE + +;HERE FOR DOUBLE WORD ADD, SUBTRACT, MULTIPLY, OR DIVIDE +;ENTER WITH (E) IN AR, E IN VMA + +=00**00 +DDIV: ARX_AC3,CLR MQ,J/DDIV0 ;GET LOWEST PART OF D'END + +DASMD: BR/AR,AR_AC1*2,ARL/AD*2, ;HIGH MEM WORD TO BR + VMA_VMA+1,LOAD ARX, ;ASK FOR LOW WORD + MQ_0.S,CALL.S,J/XFERW ;AND WAIT FOR IT +=11 ARX_ARX*2 ;SHIFT LOW MEM WORD LEFT += BRX/ARX,ARX_AR,AR_AC0, ;ALL DATA IN PLACE + SC_#,#/35.,B DISP ;DO THE OPERATION + +;HERE WITH (E) IN BR, (E+1)*2 IN BRX +; (AC) IN AR, (AC+1)*2 IN ARX + +=00* AR_AR+BR LONG,AD FLAGS,EXIT DBL ;DADD + + AR_AR-BR LONG,1FAGS,Ej BL ;DSUB + + MQ_SHIFT,AR_0S,ARX_0S, ;DMUL, USE AC1 AS INITIAL M'IER + FE_#,#/-18.,J/DMULT ;SETUP STEP COUNT += + ;HEREADOUBLE WORD MULTIPLY + +=1*00* +DMULT: AD/0S,MUL,CALL.M,J/MULP ;BEGIN MULTIPLY +=10* AR_AR+BR LONG ;CANCEL EFFECTS OF LOW BIT 0 + MQ_AR,AR_MQ ;EXCH HI AND LOW PRODUCT WORDS + +;HERE AFTER 1ST CALL ON MPY SUBR. SAVE LOW WORD OF PROD, GET HIGH M'IER + + AC3_AR ;LOW WORD OF PRODUCT + AR_AC0 ;GET HIGH M'IER WORD +=1**000 MQ_AR,AR_MQ,CALL, ;DIVE IN AGAIN + FE_#,#/-18.,J/MULREE ;CONTINUE THE MULTIPLY +=100 GEN AR*BR,AD/AND,SKP AD0 ;SKP IF M'IER, M'CAND, & PROD NEG +=110 +DMUL1: AC0_AR,AR_SIGN, + SC_#,#/35.,J/DMUL2 ;STORE HIGH WORD OF PRODUCT + SET AROV,J/DMUL1 + +;MULTIPLY NOW COMPLETE, STORE RESULTS WITH PROPER SIGN IN BIT 0 + +DMUL2: BR/AR,AR_SHIFT ;GET 2ND WITH SIGN, SAVE SIGN + AC1_AR,AR_ARX,ARX/MQ ;READY TO BUILD 3RD WORD + ARX_SHIFT,AR_BR,MQ_MQ*2 ;SIGNIFICANT B5)O ARX, SIGN TO AR + AR_SHIFT,ARX_AC3, ;3RD WORD IN AR, GET LOW + MQ_MQ*.25 ;EXTRA PROD BIT TO MQ 35 + AC2_AR,AR_MQ ;,I FETCH WHEN TIMING FIXED +=0* ARX_SHIFT,AR_BR,I FETCH, ;LOW WORD AND SIGN READY + CALL,J/SHIFT ; GET LOW WORD TO AR +STRAC3: AC3_AR,FINISH ;GANZ GETAN + r"ҋ FOR DOUBL$ΩEGER DIVISION +pi 4(), ARX HAS (AC3+AD MQ IS CLEAR + +DDIV0: T0_AR,AR_ARX,ARX_ARX*8,SC_1 ;SAVE (E) IN T0 + BRX/ARX,ARX_SHIFT, ;AC3 3-35 TO BRX, 1-2 TO ARX + AR_AC2,SC_#,#/2 ;j C2 READY + AR_SHIFT,BR/ARDwAC2 BITS 2-35 WITH AC3 1-2 + ARX_AC1,VMA_VMA+1 ;READY TO GET (E+1) + BR/AR,AR_ARX,ARX_BR*2, ;LOW DOUBLE WORD NOW IN BR LONG + SC_1,FE_1 + ARX_SHIFT,AR_AC0,SKP AD0 ;HIGH DOUBLEWORD IN AR LONG +=0 +DDIV1: BR_AR LONG,AR_BRX,ARX_BR, ;HI POS D'END TO BR + LOAD AR,J/DDIV2 ;GET LOW D'SOR READY + BR_AR LONG,AR_-BR LONG, ;NEGATE LOW D'END + FE_-1,SKP CRY0 ;TEST FOR CARRY PROPAGATION +=0 BR_AR LONG,AR_BR COMP LONG,J/DDIV1 + BR_AR LONG,AR_-BR LONG,J/DDIV1 ;FINISH NEGATION OF D'END +=0* +DDIV2: T1_AR,MQ_ARX,ARX_0S, ;LOWEST D'END TO T1, NEXT TO MQ + CALL,J/XFERW ; WAIT FOR (E+1) + ARX_SHIFT,AR_T0,SKP FE0 ;DIVISOR NOW IN AR LONG +=0 AR_BR LONG,BR_AR LONG, ;PUT OPERANDS IN PLACE FOR DIV + SIGNS DISP,J/DDIV3 ;TEST D'SOR SIGN + AR_BR LONG,BR_AR LONG,SET SR2, ;NOTE D'END NEGATIVE + SIGNS DISP,J/DDIV3 + +;HERE WITH THE DIVISOR IN BR LONG, +; THE HIGH PART OF THE MAGNITUDE OF THE DIVIDEND IN AR LONG, +; AND THE LOW PART OF THE MAGNITUDE OF THE DIVIDEND IN MQ AND T1 +; SKIP IF DIVISOR NEGATIVE, & CHECK FOR NO-DIVIDE. +=011 +DDIV3: AR_2(AR-BR),ARX/ADX*2,MQ_MQ*2, ;SEE IF FIRST DIVIDE STEP + SKP CRY0,J/DDIV4 ; GENERATES A 1 + AR_2(AR+BR),ARX/ADX*2,MQ_MQ*2,SKP CRY0 +=000 +DDIV4: FE_#,#/33.,SKP BR0,CALL,J/DDVLP ;GO DO FIRST HALF OF DIVIDE + I FETCH,J/NODIVD ;TOO MANY QUOTIENT BITS +=011 AC1_AR,CLR SC,J/DDIV6 ;SAVE HI QUOTIENT IN AC1 +=101 AC1_AR,SC_1S ;SET FLAG FOR RESUMPTION += +DDIV6: AR_T1 ;GET LOWEST DIVIDEND BITS +=100 MQ_AR,AR_MQ,CALL, ;FINISH DIVISION, GENERATING + SKP SC0,J/DIVLP ; 35 MORE QUOTIENT BITS +=110 AR_AC1,SR DISP,SET SR3,J/DDVX1 ;QUOTIENT NEGATIVE. NOTE + AR_AC1,SR DISP ;HERE'S HIGH PART OF QUOTIENT +=1101 +DDVX1: BR_AR LONG,AR_BR LONG,J/DDVX2 ;POS REMAINDER. GO STORE + BR_AR LONG,AR_-BR LONG,J/DDVX2 ;NEGATE REMAINDER +DDVX2: AC2_AR,AR_SIGN,SC_#,#/35. + AR_SHIFT,SR DISP ;GET LOW WORD OF REM. TEST QUO SIGN +=1110 AC3_AR,AR_BR,ARX/ADX*2, ;GET QUOTIENT, SQUEEZE OUT HOLE + EXIT DBL + AC3_AR,AR_-BR,ARX/ADX*2,AD LONG,;GET NEGATIVE QUOTIENT + EXIT DBL +.ENDIF/DBL.INT diff --git a/src/ucode/basic.23 b/src/ucode/basic.23 new file mode 100755 index 00000000..da09f79b --- /dev/null +++ b/src/ucode/basic.23 @@ -0,0 +1,690 @@ +.TOC "THE INSTRUCTION LOOP" + +;INSTRUCTION DECODE, EA COMPUTATION, AND OPERAND FETCH +; IN GENERAL, AN INSTRUCTION IS STARTED AT XCTGO. +; AT THIS TIME THE INSTRUCTION IS IN ARX AND IR, AND PC HAS ITS ADDRESS. +; THE DRAM OUTPUTS AND "AC" BITS WILL SETTLE DURING THIS +; MICROINSTRUCTION, AND WILL BE LATCHED BY THE CLOCK WHICH ENDS +; THE CYCLE. XCTGO DISPATCHES ON THE STATE OF THE +; INDIRECT AND INDEX BITS OF THE ARX (EA MOD DISP) TO COMPEA OR +; ONE OF THE THREE LOCATIONS FOLLOWING IT. +; IF INDIRECT IS SPECIFIED, THE INDIRECT POINTER IS FETCHED (AT +; COMPEA+2 OR +3 DEPENDING ON WHETHER INDEXING IS ALSO SPECIFIED). +; WE WAIT FOR IT AT INDRCT, AND THEN LOOP BACK TO COMPEA. WHEN NO +; INDIRECT IS CALLED FOR, WE COMPUTE THE INSTRUCTION'S EFFECTIVE ADDRESS +; (EA) AT COMPEA OR COMPEA+1 (DEPENDING ON WHETHER INDEXING IS CALLED +; FOR), AND PERFORM THE FUNCTION "A READ", WHOSE OPERATION DEPENDS +; ON THE DRAM A FIELD, AS FOLLOWS: +; +; MACRO A-FLD MEM FUNCTION VMA DISPATCH +; I 0 NONE AD(=EA) DRAM J +; I-PF 1 FETCH PC+1 DRAM J +; 2 NONE AD 42 +; W 3 WR TST AD 43 +; R 4 READ AD 44 +; R-PF 5 READ AD 45 +; RW 6 READ/WR TST AD 46 +; RPW 7 RD-PSE/WR TST AD 47 +; +; A FIELD VALUES 0 AND 1 ARE USED FOR INSTRUCTIONS WHICH NEITHER +; READ NOR WRITE THE CONTENTS OF EA (IMMEDIATE-MODE INSTRUCTIONS, +; JUMPS, ETC). THESE DISPATCH FROM "A READ" DIRECTLY TO THE MICROCODE +; WHICH HANDLES THE INSTRUCTION. IF THE A FIELD CONTAINS 1, "A READ" +; CAUSES A PREFETCH (FROM PC+1), SO THAT THE MBOX CAN WORK ON GETTING +; THE NEXT INSTRUCTION INTO ARX WHILE THE EBOX PERFORMS THIS ONE. +; IF THE A FIELD CONTAINS 3, THE MBOX PERFORMS A PAGING CHECK ON +; EA, AND CAUSES A PAGE FAIL IF THAT LOCATION IS NOT WRITABLE. +; THE MICROCODE GOES TO 43 TO WAIT FOR COMPLETION OF THE PAGE CHECK, +; AND AT THAT LOCATION LOADS AC INTO AR. THE WRITABILITY OF EA IS +; VERIFIED AT THIS TIME TO PREVENT INCORRECTLY SETTING FLAGS OR +; THE PROCESSOR STATE IF THE INSTRUCTION WILL BE ABORTED BY PAGE +; FAILURE. LOCATION 43 THEN DISPATCHES TO THE HANDLER FOR THE +; CURRENT INSTRUCTION. +; A FIELD VALUES 4 TO 7 PERFORM READS FROM EA. 6 AND 7 ALSO TEST +; THE WRITABILITY OF THE LOCATION, AND 7 PERFORMS THE FIRST HALF OF +; A READ-PAUSE-WRITE CYCLE IF EA IS AN UN-CACHED ADDRESS. THE DISPATCH +; IS TO 40+A, WHERE WE WAIT FOR MEMORY DATA TO ARRIVE IN AR. IF THE A +; FIELD WAS 5, WE PREFETCH FROM PC+1 AS SOON AS THE DATA ARRIVES. +; IN ANY CASE, WE DISPATCH ACCORDING TO THE DRAM J FIELD TO THE +; HANDLER FOR THE INSTRUCTION. +; IF A PAGE FAIL OCCURS AT ANY TIME (EITHER IN THIS CODE OR DURING +; INSTRUCTION EXECUTION) THE MICROPROCESSOR TRAPS TO CRAM LOCATION +; 1777, WHERE IT CAUSES A PAGE FAIL TRAP. + ; MOST INSTRUCTIONS (THE MOVE, HALFWORD, AND BOOLEAN GROUPS, +; PLUS ADD AND SUB) ARE PERFORMED BY HANDLERS CONSISTING OF ONE OR +; TWO MICROINSTRUCTIONS WHICH LEAVE THE RESULT IN AR, AND COMPLETE +; BY INVOKING THE "EXIT" MACRO. EXIT USES THE MEM/B WRITE FUNCTION +; TO BEGIN A STORE TO MEMORY FOR THOSE MODES IN WHICH THE RESULT +; GOES TO MEMORY, AND DISP/DRAM B TO GET TO ONE OF THE MICROINSTRUCTIONS +; FOLLOWING ST0. THIS CODE DEPENDS ON A CERTAIN AMOUNT OF CORRELATION +; BETWEEN THE DRAM A AND B FIELDS. IN PARTICULAR, STAC (STORE AC) +; ASSUMES THAT A PREFETCH HAS OCCURRED, WHILE THE OTHERS ASSUME THAT +; NO PREFETCH HAS OCCURED. THUS NORMAL AND IMMEDIATE MODES, WHOSE +; RESULTS GO ONLY TO AC, MUST PREFETCH IN THE DRAM A FIELD, WHILE +; MEM, BOTH, AND SELF MODES, WHOSE RESULTS GO TO MEMORY, MUST NOT. +; (THIS RESTRICTION IS AVOIDED FOR THOSE INSTRUCTIONS WHICH NEVER +; PREFETCH -- IN MUL, DIV, AND IDIV BY USE OF THE EXIT TO ST2AC, +; AND IN IMUL AND THE SINGLE PRECISION FLOATING POINT +; INSTRUCTIONS BY A RESTRICTED EXIT TO ST6.) +; ANOTHER LARGE SET OF INSTRUCTIONS (SKIP, AOS, SOS, JUMP, AOJ, +; SOJ, AOBJ, CAI, CAM, AND THE TEST GROUP) KNOWS WHERE TO PUT THE +; RESULTS WITHOUT MODE INFORMATION, AND THEY USE THE DRAM B FIELD TO +; DETERMINE WHETHER TO SKIP OR JUMP, AS A FUNCTION OF THEIR OPERANDS. +; SKIP, AOS, AND SOS ARE CONSIDERED SELF-MODE INSTRUCTIONS, +; AND AFTER MAKING THE FETCH DECISION (AND RE-WRITING MEMORY, IN +; THE CASE OF AOS OR SOS), JUMP TO STSELF TO DECIDE WHETHER OR NOT +; TO PUT THE RESULT ALSO IN AC. THE OTHER INSTRUCTIONS OF THIS SET +; JUMP TO STORAC OR NOP AFTER MAKING THE FETCH DECISION, DEPENDING +; ON WHETHER OR NOT THE OPCODE DEFINITION REQUIRES MODIFICATION OF AC. +; (NOTE THE DIFFERENCE BETWEEN STAC AND FINI ON THE ONE HAND, +; AND STORAC AND NOP ON THE OTHER -- STORAC AND NOP MUST BE USED WHEN +; THE NEXT INSTRUCTION FETCH OCCURS ON THE PRECEDING EBOX CYCLE, BECAUSE +; NICOND MUST NOT IMMEDIATELY FOLLOW A FETCH (ONE CYCLE REQUIRED FOR +; VMA AC REF TO MAKE IT THROUGH THE NICOND LOGIC), STAC AND FINI ARE +; USED WHEN THERE HAS BEEN AN INTERVENING CYCLE.) + .TOC "NEXT INSTRUCTION DISPATCH" + +;START BY PUTTING PC WORD IN AR, JUMP HERE +0: +START: SET FLAGS_AR,BR/AR,J/BRJMP ;LOAD UP FLAGS +CONT: VMA/PC,FETCH,J/XCTW ;HERE TO CONTINUE FROM PC + +; DISP/NICOND (THE "NXT INSTR" MACRO) BRINGS US TO ONE OF THE +; LOCATIONS FOLLOWING "NEXT". PC HAS BEEN UPDATED TO ADDRESS THE NEXT +; INSTRUCTION IN THE NORMAL FLOW, AND IF IT IS FROM MEMORY +; (AS OPPOSED TO AC'S), THE INSTRUCTION IS IN ARX AND IR. +; THE NICOND DISPATCH IS PRIORITY ENCODED, AS FOLLOWS: +; [FOR FULL DETAILS, SEE PRINT CON2] +;(1) IF PI CYCLE IS TRUE, GO TO NEXT FOR SECOND HALF +; OF STANDARD OR VECTOR INTERRUPT. +;(2) IF THE RUN FLOP (CON RUN) IS OFF, GO TO NEXT+2, FROM WHICH THE +; MICROCODE WILL ENTER THE HALT LOOP TO WAIT FOR THE CONSOLE TO RESTART +; INSTRUCTION PROCESSING. +;(3) IF THE METER HAS A REQUEST, GO TO NEXT+4 (MTRINT) TO SERVE IT. +;(4) IF THE PI SYSTEM HAS A REQUEST READY, GO TO NEXT+6 (INTRPT) +; TO START A PI CYCLE. +;(5) IF CON UCODE STATE 05 (TRACK EN) IS SET, GO TO NEXT+10 OR 11. +; THIS FLOP IS ENTIRELY UNDER CONTROL OF THE MICROCODE, AND IS ONLY +; USED FOR THE SPECIAL STATISTICS-GATHERING MICROCODE. +;(6) IF THE LAST INSTRUCTION SET A TRAP FLAG, GO TO NEXT+13 OR +17, +; IT DOESN'T MATTER WHICH. +;(7) IF VMA CONTAINS AN AC ADDRESS, IMPLYING THAT THE NEXT +; INSTRUCTION IS TO COME OUT OF FAST MEMORY, GO TO NEXT+16 TO GET IT. +;(10) --NORMAL CASE-- THE INSTRUCTION IS IN ARX, READY TO GO, GO +; TO NEXT+12 (XCTGO). + +=11*0000 ;USE LOC'NS INACCESSIBLE TO DRAM +NEXT: SET PI CYCLE,GEN FE, ;2ND PART OF INTERRUPT + BYTE DISP,J/PICYC2 ;SKIP IF VECTOR INT +=0010 AR_0S,SET HALTED,J/HALT1 ;HERE IF RUN FLOP OFF +=0100 +MTRINT: CLR ACCOUNT EN,J/MTRREQ ;HERE IF METER REQUEST UP + AR_EBUS,SC_#,#/2,J/PICYC1 ;HERE IF TAKE INTRPT DOESNT FIND +=0110 ; A METER REQUEST +INTRPT: AR_EBUS,SC_#,#/2,J/PICYC1 ;HERE IF INTERRUPT PENDING +.IF/TRACKS +=1000 AR_TRX+1,GEN CRY18,SKP CRY0,J/TRK1 ;HERE TO STORE PC BEFORE + AR_TRX+1,GEN CRY18,SKP CRY0,J/TRK1 ; EXECUTING NEXT INSTR +.ENDIF/TRACKS +.IF/OP.CNT +=1000 SC_#,#/9.,SKP USER,J/OPCT1 ;COUNT THIS INSTR + SC_#,#/9.,SKP USER,J/OPCT1 +.ENDIF/OP.CNT +.IF/OP.TIME +=1000 AR_2,CLR TRK+PA EN,J/OPTM1 ;TIME OUT THIS INSTR + AR_2,CLR TRK+PA EN,J/OPTM1 +.ENDIF/OP.TIME +;-- THE NICOND DISPATCH BLOCK CONTINUES ON THE NEXT PAGE -- + ;-- NICOND DISPATCH CONTINUED -- + +=1010 +XCTGO: BRX/ARX,SET ACCOUNT EN, ;SAVE INSTR, ENABLE ACCOUNTING, + EA MOD DISP,J/COMPEA,AR_1S ;GO CALCULATE EA, -1 FOR SOJ HACK +.IFNOT/ONE PROCEED +TRAP: VMA_420+TRAP,J/TRAPX ;HERE IF TRAP BITS SET +.IF/ONE PROCEED +TRAP: GET ECL EBUS,SC_1,J/TR3CHK ;TRAP, CHECK FOR ONE PROCEED +.ENDIF/ONE PROCEED +=1110 ARX_FM(VMA),TIME/3T,LOAD IR,J/XCTGO ;HERE IF INSTR IS IN FM +.IFNOT/ONE PROCEED + VMA_420+TRAP,J/TRAPX ;HERE IF TRAP BITS SET +.IF/ONE PROCEED + ARX_FM(VMA),TIME/3T,LOAD IR, ;HERE IF TRAP AND VMA->ACS + J/TRAP ;FETCH THE INSTR THEN TRAP +.ENDIF/ONE PROCEED + +.IF/ONE PROCEED +;HERE ON TRAPS, WITH INSTRUCTION IN ARX AND IR, 1 IN SC, +;AND ECL EBUS GRABBED. UNFORTUNATELY THE HARDWARE CAREFULLY +;CLEARS THE TRAP BITS IN THE PC WORD ON A NICOND, BUT +;WE CAN USE A DIAGNOSTIC FUNCTION TO READ THE TRAP CYC BITS (SCD4). +;THE "ADDRESS BREAK INHIBIT" HAIR (SCD5) IS USED TO +;DETECT WHEN AN INSTRUCTION IS COMPLETED. +;IF THIS IS A TRAP 3, AND SCD ADDR BRK CYC IS TRUE, WE ARE +;IN THE MIDDLE OF A ONE-PROCEED, SO SUPPRESS THE TRAP. +;SCD ADDR BRK CYC IS ON WHEN NICOND IS DONE WITH +;ADR BRK INH SET IN THE PC FLAGS (I.E. JUST STARTING +;OR RE-STARTING THE INSTRUCTION BEING ONE-PROCEEDED.) + +TR3CHK: AR03-04_SCD TRAP CYC + VMA_420+TRAP,SH DISP,J/TR3DSP ;VMA -> TRAP INST, CHECK TRAP NUMBER +=11100 +TR3DSP: +=01 + REL ECL EBUS,J/TRAPX ;TRAP 1 - TAKE TRAP + REL ECL EBUS,J/TRAPX ;TRAP 2 - TAKE TRAP + AR05_SCD ADDR BRK CYC ;TRAP 3 - CHECK FOR ONE PROCEED + GEN P AND SC,SKP SCAD NE ;SKIP IF ONE-PROCEEDING +=1***0 + REL ECL EBUS,J/TRAPX ;NO, TAKE THE TRAP + REL ECL EBUS ;YES, DO THE INSTR THEN + TRAP3,J/XCTGO ;ARRANGE FOR ANOTHER TRAP + ;WHEN THE INSTRUCTION COMPLETES +.ENDIF/ONE PROCEED + +;HERE ON TRAPS, VMA SETUP WITH 420+TRAP CODE + +TRAPX: LOAD ARX,PT REF ;GET AND XCT TRAP INSTR + SET PC+1 INH ;DON'T INCREMENT PC FOR THIS INSTR + +;HERE AFTER FETCHING INSTR TO BE EXECUTED + +XCTW: ARX_MEM,LOAD IR,J/XCTGO ;GET INSTR TO XCT + .TOC "EFFECTIVE ADDRESS COMPUTATION AND OPERAND FETCH" + +;COME HERE WITH -1 IN AR IF YOU EXPECT SOJ TO WORK! +=11***00 ;HERE WITH XR CALC IN PROG +COMPEA: AR_ARX (AD),A READ, ;NO MOD, GET OPERAND IF ANY + MQ_AR ;SOJ SERIES EXPECTS -1 IN MQ + AR_ARX+XR,A READ, ;INDEXED, NO @ + MQ_AR ;SOJ SERIES EXPECTS -1 IN MQ + GEN ARX,A INDRCT, ;DO INDIRECT, NO INDEX + SKP INTRPT,J/INDRCT + GEN ARX+XR,A INDRCT, ;BOTH @ AND XR + SKP INTRPT,J/INDRCT +=11****0 +INDRCT: ARX_MEM,J/INDLP ;GET INDIRECT POINTER, EVAL +TAKINT: ARX_MEM,TAKE INTRPT ;INTERRUPT DURING INDIRECT + +;APPARENTLY A INDRCT AT COMPEA+2/+3 CAN +; CAUSE AR AS WELL AS ARX TO BE CLOBBERED BY ARX_MEM. +;HENCE WE MUST RESTORE THE -1 THAT THE SOJ SERIES DEPENDS ON. + +INDLP: EA MOD DISP,AR_1S,J/COMPEA ;EVALUATE POINTER + .TOC "WAIT FOR (E)" + +;THE EXECUTE CODE FOR EACH INSTRUCTION IS ENTERED WITH +; THE OPCODE AND AC # IN BRX AND IR, THE LAST INDIRECT WORD +; IN ARX, AND AR AND VMA SETUP AS A FUNCTION OF THE A +; FIELD OF THE DISPATCH RAM. A PREFETCH IS IN PROGRESS IF THE +; DRAM A FIELD WAS 1 OR 5 (OR IF IR CONTAINS "JRST 0,"). + +;ON "A READ", THE HARDWARE DISPATCHES TO THE EXECUTE CODE FOR +; THE INSTRUCTION IF THE DRAM A FIELD IS 0 OR 1. IF THE A FIELD +; CONTAINS 2-7, THE HARDWARE DISPATCHES TO 40+A, BELOW: + +;COME HERE ON "A READ" FUNCTION IF DRAM A FIELD IS 3 +; A "WRITE TST" IS IN PROGRESS + +43: BR/AR,AR_AC0,MB WAIT, ;WAIT FOR PERMISSION TO WRITE + TIME/3T,IR DISP,J/0 ;AND GO TO EXECUTE CODE + +;HERE ON "A READ" FUNCTION IF DRAM A FIELD IS 4 +; A "LOAD AR" IS IN PROGRESS + +44: BR/AR,AR_MEM,TIME/3T, ;GET OPERAND + IR DISP,J/0 ; START EXECUTE + +;HERE ON "A READ" IF A FIELD IS 5 +; A "LOAD AR" IS IN PROGRESS, AND WE MUST PREFETCH WHEN IT COMPLETES + +45: BR/AR,FIN XFER,I FETCH, ;GET OPERAND, PREFETCH, + TIME/3T,IR DISP,J/0 ; & START EXECUTE + +;HERE ON "A READ" IF A FIELD IS 6 +; A "LOAD AR" IS IN PROGRESS, BUT PAGING IS TESTING WRITABILITY + +46: BR/AR,AR_MEM,TIME/3T, ;GET OPERAND + IR DISP,J/0 ; START EXECUTE + +;HERE ON "A READ" IF A FIELD IS 7 +; A "READ-PAUSE-WRITE" IS IN PROGRESS + +47: BR/AR,AR_MEM,TIME/3T, ;GET OPERAND + IR DISP,J/0 ; START EXECUTE + .TOC "TERMINATION" + +;DISPATCH HERE WITH THE "EXIT" MACRO, +; OR JUMP DIRECTLY TO ONE OF THESE LOCATIONS. + +=11*000 +ST0: ;BASE FOR B DISP IN EXIT MACRO +=001 +ST2AC: AC0_AR,AR_SIGN,I FETCH,J/STD1 ;HERE TO STORE AC0 & AC1 + FIN STORE,EXIT DBL ;MULB, DIVB, ETC ... + FIN STORE,I FETCH, ;SELF MODE + SKP AC#0,J/STSELF ; RESULT TO AC TOO? +=101 +STAC: AC0_AR,NXT INSTR ;NORMAL AND IMMEDIATE MODES +ST6: +IFNOP: +STMEM: FIN STORE,I FETCH,J/NOP ;MEM MODE +IFSTAC: +STBOTH: FIN STORE,I FETCH,J/STORAC ;BOTH MODE += +;HERE TO FINISH, AFTER FETCHING NEXT INSTRUCTION. +; WE MUST GUARANTEE AT LEAST ONE EBOX CYCLE BETWEEN FETCH AND NICOND, +; TO ALLOW VMA AC REF TO MAKE IT THROUGH THE NICOND LOGIC. +=11***0 +STSELF: ;SKIP, AOS, SOS COME HERE +STORAC: SR_0,J/STAC ;STORE AC, TOO +NOP: J/FINI ;DELAY THEN NXT INSTR + +.IF/JPC SUPPORT +=11*110 +NJPCP: AR_PC,SKP USER,J/JPCEX ;FOR JPC HACK - SKIP IF NOT JUMPING +.ENDIF/JPC SUPPORT +FINI: SR_0,NXT INSTR ;GET NEXT INSTR IN ARX & IR, + ; LOAD PC, TEST PI CYCLE, RUN, + ; PI READY, TRAPS + +;HERE TO STORE ARITHMETIC DOUBLE RESULTS + +DSTAC: AC0_AR,AR_SIGN ;HERE WITH FETCH STARTED +STD1: AR_SHIFT,SR_0 ;BRING IN LOW PART +STAC1: AC1_AR,NXT INSTR AFTER AC1 ;STORE AC1 + + +;HERE TO GET MICRO-CODE VERSION #. FIXED LOC'N SO SOFTWARE CAN FIND IT +137: +UVERS: BR/AR,AR0-8_#,#/VERS,J/GTAR08 ;COPY VERSION TO AR + .TOC "MOVE GROUP, EXCH, BLT" + + .DCODE +200: R-PF, AC, J/MOVE ;BASIC MOVE + I-PF, AC, J/MOVE +.IF/WRTST + W, M, J/MOVE +.IFNOT/WRTST + I, B/1, J/MOVEM +.ENDIF/WRTST + RPW, S, J/MOVE + +204: R-PF, AC, J/MOVS + I-PF, AC, J/MOVS + W, M, J/MOVS + RPW, S, J/MOVS + +210: R-PF, AC, J/MOVN + I-PF, AC, J/MOVN + W, M, J/MOVN + RPW, S, J/MOVN + +214: R-PF, AC, J/MOVM + I-PF, AC, J/MOVM + W, M, J/MOVM + RPW, S, J/MOVM + .UCODE + +; ENTER WITH 0,E, (E), OR (AC) IN AR + +=00**** +MOVS: AR_AR SWAP,EXIT ;ALSO USED BY HALFWORD GROUP += +=00**** +MOVM: BR/AR,SKP AR0,J/MOVE ;FORCE POSITIVE += +=00**** +MOVN: BR/AR,J/MOVNEG ;GET NEGATIVE += +=00*000 +MOVE: EXIT ;STORE AS IS FROM AR +MOVNEG: AR_-BR,AD FLAGS,FETCH WAIT,J/MOVE + +;EXCH, BLT + + .DCODE +250: RPW, B/0, J/EXCH + I, J/BLT + .UCODE + +=00***0 +MOVEM: ;LIKE EXCH, EXCEPT NO STORE AC +EXCH: ARX_AR,AR_AC0,STORE,J/STMAC ;PUT AC AT E, THEN STORE AC + +BLT: MQ_AR,ARX_AR, ;END ADDR TO MQ & ARX + ARR_AC0,ARL_ARL,J/BLT1 ;FIRST DEST ADDR TO AR + .TOC "HALFWORD GROUP" +; DESTINATION LEFT HALF + + .DCODE +500: R-PF, AC, J/HLL + I-PF, AC, J/HLL + RPW, M, J/HRR ;HLLM = HRR EXCEPT FOR STORE + RPW, S, J/MOVE ;HLLS = MOVES + + R-PF, AC, J/HRL + I-PF, AC, J/HRL + RPW, M, J/HRLM + RPW, S, J/HRLS + +510: R-PF, AC, J/HLLZ + I-PF, AC, J/HLLZ + W, M, J/HLLZ + RPW, S, J/HLLZ + + R-PF, AC, J/HRLZ + I-PF, AC, J/HRLZ + W, M, J/HRLZ + RPW, S, J/HRLZ + +520: R-PF, AC, J/HLLO + I-PF, AC, J/HLLO + W, M, J/HLLO + RPW, S, J/HLLO + + R-PF, AC, J/HRLO + I-PF, AC, J/HRLO + W, M, J/HRLO + RPW, S, J/HRLO + +530: R-PF, AC, J/HLLE + I-PF, AC, J/HLLE + W, M, J/HLLE + RPW, S, J/HLLE + + R-PF, AC, J/HRLE + I-PF, AC, J/HRLE + W, M, J/HRLE + RPW, S, J/HRLE + ; DESTINATION RIGHT HALF + +540: R-PF, AC, J/HRR + I-PF, AC, J/HRR + RPW, M, J/HLL ;HRRM = HLL EXCEPT FOR STORE + RPW, S, J/MOVE ;HRRS = MOVES + + R-PF, AC, J/HLR + I-PF, AC, J/HLR + RPW, M, J/HLRM + RPW, S, J/HLRS + +550: R-PF, AC, J/HRRZ + I-PF, AC, J/HRRZ + W, M, J/HRRZ + RPW, S, J/HRRZ + + R-PF, AC, J/HLRZ + I-PF, AC, J/HLRZ + W, M, J/HLRZ + RPW, S, J/HLRZ + +560: R-PF, AC, J/HRRO + I-PF, AC, J/HRRO + W, M, J/HRRO + RPW, S, J/HRRO + + R-PF, AC, J/HLRO + I-PF, AC, J/HLRO + W, M, J/HLRO + RPW, S, J/HLRO + +570: R-PF, AC, J/HRRE + I-PF, AC, J/HRRE + W, M, J/HRRE + RPW, S, J/HRRE + + R-PF, AC, J/HLRE + I-PF, AC, J/HLRE + W, M, J/HLRE + RPW, S, J/HLRE + + .UCODE + ;FIRST, THE 16 OPS WHICH DO NOT AFFECT THE "OTHER" HALF. +;THESE MUST BE TREATED SEPARATELY, BECAUSE THEY COMBINE MEMORY DATA +;IN AR WITH DATA FROM THE FM. ENTER WITH 0,E OR (E) IN AR. + +=00***0 +HRR: ARL_AC0,ARR_ARR,EXIT ;HRR, HRRI, HLLM +=00**** +HLL: ARR_AC0,ARL_ARL,EXIT ;HLL, HLLI, HRRM += ;HRRS, HLLS ARE BOTH EQUIVALENT TO MOVES +=00**** +HRL: ARL_ARR,ARR_AC0,EXIT ;HRL, HRLI += +=00**** +HLR: ARR_ARL,ARL_AC0,EXIT ;HLR, HLRI += +=00***0 +HRLM: ARL_ARR,ARR_AC0,J/MOVS ;HRLM +HRLS: ARL_ARR,ARR_ARR,EXIT ;HRLS += +=00***0 +HLRM: ARR_ARL,ARL_AC0,J/MOVS ;HLRM +HLRS: ARR_ARL,ARL_ARL,EXIT ;HLRS += +;NOW THE HALFWORD OPS WHICH CONTROL THE "OTHER" HALF +; ENTER WITH 0,E, (E), OR (AC) IN AR + +=00**** +HRRE: SKP AR18 ;SELECT HRRZ OR HRRO ON SIGN += +=00***0 +HRRZ: ARL_0S,ARR_ARR,EXIT +HRRO: ARL_1S,ARR_ARR,EXIT += +=00**** +HRLE: SKP AR18 += +=00***0 +HRLZ: ARL_ARR,ARR_0S,EXIT +HRLO: ARL_ARR,ARR_1S,EXIT += +=00**** +HLRE: SKP AR0 += +=00***0 +HLRZ: ARR_ARL,ARL_0S,EXIT +HLRO: ARR_ARL,ARL_1S,EXIT += +=00**** +HLLE: SKP AR0 += +=00***0 +HLLZ: ARR_0S,ARL_ARL,EXIT +HLLO: ARR_1S,ARL_ARL,EXIT += + .TOC "DMOVE, DMOVN, DMOVEM, DMOVNM" +;DOUBLE-WORD MOVES + + .DCODE +120: R, B/0, J/DMOVE + R, B/1, J/DMOVN + .UCODE + +; ENTER WITH (E) IN AR +=00**** +DMOVN: +DMOVE: VMA_VMA+1,LOAD ARX,B DISP ;PICK UP (E+1) += +=1**00 + ARX_MEM,J/STDAC ;GO STORE DOUBLE AC + ARX_MEM,MQ_0.S,CALL.S,J/GTDBR ;LOAD BR WITH DOUBLE OPERAND +=11 AR_-BR LONG,AD FLAGS, ;NEGATE DOUBLE OPERAND + SC_#,#/35. ;& STORE RESULT +DBLST: AC0_AR,AR_0S,I FETCH,J/STD1 ;STORE HIGH WORD, READY LOW + + +;DOUBLE MOVES TO MEMORY + + .DCODE +124: W, J/DMOVEM + W, J/DMOVNM + .UCODE + +;ENTER WITH (AC) IN AR +=00**00 +DMOVEM: ARX_AC1,STORE,SC_#,#/36.,J/DMVM1 +DMOVNM: ARX_AC1,MQ_0.S,CALL.S,J/GTDBR ;HIGH WORD IS ALREADY IN AR +=11 AR_-BR LONG,AD FLAGS, ;NEGATE + STORE,SC_#,#/35. ; & STORE += +DMVM1: MEM_AR,VMA_VMA+1,AR_0S + AR_SHIFT,STORE,J/STMEM + +GTDBR: ARX_ARX*2 ;SHIFT OUT LOW SIGN +LDBRL: BR_AR LONG,RETURN3 ;COPY TO BR LONG + .TOC "BOOLEAN GROUP" + + .DCODE +400: I-PF, AC, J/SETZ + I-PF, AC, J/SETZ + IW, M, J/SETZ + IW, B, J/SETZ + .UCODE + +=00**** +SETZ: AR_0S,EXIT += + .DCODE +404: R-PF, AC, J/AND + I-PF, AC, J/AND + RPW, M, J/AND + RPW, B, J/AND + .UCODE + +=00**** +AND: AR_AR*AC0,AD/AND,EXIT += + .DCODE +410: R-PF, AC, J/ANDCA + I-PF, AC, J/ANDCA + RPW, M, J/ANDCA + RPW, B, J/ANDCA + .UCODE + +=00**** +ANDCA: AR_AR*AC0,AD/ANDCB,EXIT += + .DCODE +414: R-PF, AC, J/MOVE ;SETM = MOVE + I-PF, AC, J/MOVE + RPW, M, J/MOVE ;SETMM = NOP THAT WRITES MEMORY + RPW, B, J/MOVE ;SETMB = MOVE THAT WRITES MEMORY + +420: R-PF, AC, J/ANDCM + I-PF, AC, J/ANDCM + RPW, M, J/ANDCM + RPW, B, J/ANDCM + .UCODE + +=00**** +ANDCM: AR_AR*AC0,AD/ANDCA,EXIT += + .DCODE +424: R-PF, J/TDN + I-PF, J/TDN + W, M, J/MOVE ;SETAM = MOVEM + W, M, J/MOVE ;SETAB, TOO + .UCODE + .DCODE +430: R-PF, AC, J/XOR + I-PF, AC, J/XOR + RPW, M, J/XOR + RPW, B, J/XOR + .UCODE + +=00**** +XOR: AR_AR*AC0,AD/XOR,EXIT += + .DCODE +434: R-PF, AC, J/IOR + I-PF, AC, J/IOR + RPW, M, J/IOR + RPW, B, J/IOR + .UCODE + +=00**** +IOR: AR_AR*AC0,AD/OR,EXIT += + .DCODE +440: R-PF, AC, J/ANDCB + I-PF, AC, J/ANDCB + RPW, M, J/ANDCB + RPW, B, J/ANDCB + .UCODE + +=00**** +ANDCB: AR_AR*AC0,AD/ANDC,EXIT += + .DCODE +444: R-PF, AC, J/EQV + I-PF, AC, J/EQV + RPW, M, J/EQV + RPW, B, J/EQV + .UCODE + +=00**** +EQV: AR_AR*AC0,AD/EQV,EXIT += + .DCODE +450: I-PF, AC, J/SETCA + I-PF, AC, J/SETCA + IW, M, J/SETCA + IW, B, J/SETCA + .UCODE + +=00**** +SETCA: AR_AR*AC0,AD/SETCB,EXIT += + .DCODE +454: R-PF, AC, J/ORCA + I-PF, AC, J/ORCA + RPW, M, J/ORCA + RPW, B, J/ORCA + .UCODE + +=00**** +ORCA: AR_AR*AC0,AD/ORCB,EXIT += + .DCODE +460: R-PF, AC, J/SETCM + I-PF, AC, J/SETCM + RPW, M, J/SETCM + RPW, B, J/SETCM + .UCODE + +=00**** +SETCM: ADA/AR,AD/SETCA,AR/AD,EXIT += + .DCODE +464: R-PF, AC, J/ORCM + I-PF, AC, J/ORCM + RPW, M, J/ORCM + RPW, B, J/ORCM + .UCODE + +=00**** +ORCM: AR_AR*AC0,AD/ORCA,EXIT += + .DCODE +470: R-PF, AC, J/ORCB + I-PF, AC, J/ORCB + RPW, M, J/ORCB + RPW, B, J/ORCB + .UCODE + +=00**** +ORCB: AR_AR*AC0,AD/ORC,EXIT += + .DCODE +474: I-PF, AC, J/SETO + I-PF, AC, J/SETO + IW, M, J/SETO + IW, B, J/SETO + .UCODE + +=00**** +SETO: AR_1S,EXIT += + \ No newline at end of file diff --git a/src/ucode/bcirc.3 b/src/ucode/bcirc.3 new file mode 100755 index 00000000..92d47f50 --- /dev/null +++ b/src/ucode/bcirc.3 @@ -0,0 +1,4 @@ + +.SET/CIRC.BIG.OPT=1 +.SET/CIRC=1 + \ No newline at end of file diff --git a/src/ucode/blt.9 b/src/ucode/blt.9 new file mode 100755 index 00000000..edc492a9 --- /dev/null +++ b/src/ucode/blt.9 @@ -0,0 +1,157 @@ +.TOC "BLT" +; ENTER WITH 0,E IN AR + +;IN THE LOOP, ARX CONTAINS THE CURRENT DESTINATION ADDRESS, +; BRX CONTAINS THE TERMINAL ADDRESS, AND BR CONTAINS THE DIFFERENCE +; BETWEEN THE SOURCE AND DESTINATION ADDRESSES. + +;UNLIKE EARLIER -10 PROCESSORS, THIS CODE CHECKS FOR THE CASE IN WHICH +; THE DESTINATION ADDRESS IN RH(AC) IS GREATER THAN E, AND RATHER THAN +; STOPPING AFTER ONE WORD, COPIES DOWNWARD (EFFECTIVELY DECREMENTING +; AC BY 1,,1 ON EACH STEP, RATHER THAN INCREMENTING). + +;THIS CODE ALSO PROVIDES A GUARANTEED RESULT IN AC ON COMPLETION OF +; THE TRANSFER (EXCEPT IN THE CASE AC IS PART OF BUT NOT THE LAST WORD +; OF THE DESTINATION BLOCK). WHEN AC IS NOT PART OF THE DESTINATION +; BLOCK, IT IS LEFT CONTAINING THE ADDRESSES OF THE FIRST WORD FOLLOWING +; THE SOURCE BLOCK (IN THE LH), AND THE FIRST WORD FOLLOWING THE DEST- +; INATION BLOCK (IN THE RH). IF AC IS THE LAST WORD OF THE DESTINATION +; BLOCK, IT WILL BE A COPY OF THE LAST WORD OF THE SOURCE BLOCK. + +;IN ADDITION, A SPECIAL-CASE CHECK IS MADE FOR THE CASE IN WHICH EACH +; WORD STORED IS USED AS THE SOURCE OF THE NEXT TRANSFER. IN THIS CASE, +; ONLY ONE READ NEED BE PERFORMED, AND THAT DATA MAY BE STORED FOR EACH +; TRANSFER. THUS THE COMMON USE OF BLT TO CLEAR CORE IS SPEEDED UP. + +;BLT: ARX_AR,MQ_AR,ARR_AC0,ARL_ARL ;END TO ARX & MQ, DEST TO AR +BLT1: BR/AR,ARX_AR,BRX/ARX, ;DST TO BR & ARX, END TO BRX + AR_AC0 ;SRC TO ARL + ARR_ARL,ARL_0.M ;SRC TO ARR + AR_AR-BR ;SRC-DST TO ARR +.IF/BACK.BLT + BR/AR,SKP ARX LE BRX ;SRC-DST TO BR. UP OR DOWN? +=00 AR_MQ-1,CALL,J/BLTAC ;DOWN, READY WITH E-1 + AR_MQ+1,CALL,J/BLTAC ;UP, PUT E+1 IN AR FOR AC +DOWN: VMA_ARX+BR,LOAD AR,J/DN1 ;DOWN, START THE LOOP +.IFNOT/BACK.BLT +=0* BR/AR,AR_MQ+1,CALL,J/BLTAC ;SRC-DST TO BR, E+1 IN AR +.ENDIF/BACK.BLT + SKP BR EQ -1,J/UP ;IS THIS CORE CLEARING CASE? + + +;HERE TO SETUP FINAL AC + +BLTAC: ARL_ARR,AR_AR+BR ;FINAL DEST TO LH, SRC TO RH + AR_AR SWAP,SR_BLT(SRC) ;REARRANGE + AC0_AR,RETURN2 + ;HERE FOR UPWARD BLT (AC RH .LE. E) +=0 +UP: VMA_ARX+BR,LOAD AR,J/UP1 ;NOT CLEAR CORE + SKP P!S XCT,VMA_ARX+BR,LOAD AR ;DO NOT OPTIMIZE UNDER EXT ADDR + +;USE EVEN LOC'NS OF THIS BLOCK OF 4 IN SPECIAL "CLEAR CORE" CASE + +=00 AR_MEM,CALL,SR_BLT(DST),J/UP2 ;GET THE WORD TO STORE IN ALL +UP1: AR_MEM,CALL,SR_BLT(DST),J/UP2 ;GET SOURCE WORD + CALL,SR_BLT(DST),J/UP2 ;HERE TO STORE SAME SRC AGAIN + VMA_ARX+BR,LOAD AR,J/UP1 ;HERE TO GET NEXT SRC + +UP2: VMA_ARX,STORE,SKP INTRPT ;OK, GET DST ADDRESS +=0 +UP3: SKP ARX LT BRX,J/UP4 ;CHECK FOR LAST TRANSFER + MEM_AR,J/BLTPF ;FINISH THIS, GO SERVE INTRPT +=0 +UP4: FIN STORE,I FETCH,J/NOP ;THAT'S ALL, FOLKS + MEM_AR,ARX_ARX+1, ;STORE DST, + SR_BLT(SRC),RETURN2 ; CONTINUE + +;BLT CONTINUED - HERE FOR DOWNWARD BLT (AC RH .GT. E) +.IF/BACK.BLT + +DN1: AR_MEM,SR_BLT(DST) ;WAIT FOR SOURCE DATA + VMA_ARX,STORE,SKP INTRPT ;OK, START DST REF +=0 SKP ARX LE BRX,J/DN3 ;CHECK FOR END CONDITION + MEM_AR,J/BLTPF ;FINISH STORE, TAKE INTRPT +=0 +DN3: MEM_AR,ARX_ARX-1, ;NOT END, LOOP + SR_BLT(SRC),J/DOWN + FIN STORE,I FETCH,J/NOP ;END +.ENDIF/BACK.BLT + .TOC "STORING OF JPC" + +.IF/JPC SUPPORT + +AOBJPC: ;HERE TO STORE JPC FOR AOBJN/AOBJP +SOJJPC: ;HERE FOR SOJ SERIES +AOJJPC: ;HERE FOR AOJ SERIES + AC0_AR,B DISP +=*1*000 ;HERE FOR JUMP SERIES +JMPJPC: GEN AR-1,SKP AR0,SIGNS DISP,J/JPCP ;LE + SKP AR NE,J/NJPCP ;E + SKP AR0,J/JPCP ;L + J/FINI ;- + GEN AR-1,SKP AR0,SIGNS DISP,J/NJPCP ;G + SKP AR NE,J/JPCP ;N + SKP AR0,J/NJPCP ;GE + AR_PC,SC_#,#/32.,SKP USER,J/JPCEX ;A + +=*1*110 +JPCP: NXT INSTR ;NOT JUMPING +JPCIFY: AR_PC,SC_#,#/32.,SKP USER,J/JPCEX ;JUMPING + +;THIS IS LIKE STORAC, EXCEPT IT STORES THE JPC ALSO. +;CALLED WITH SKP USER, BECAUSE WRITING IN FM USES THE COND +;FIELD, WHICH MEANS JPCSTO CAN'T DO THE SKP USER ITSELF. + +=0 +JPCSTO: AC0_AR,AR_PC,SC_#,#/32.,J/JPCEX + AC0_AR,AR_PC,SC_#,#/32.,J/JPCUSR + +.IFNOT/JPC.RING +=*1***0 +JPCEX: XJPC_AR,NXT INSTR AFTER JPC +JPCUSR: JPC_AR,NXT INSTR AFTER JPC +.IF/JPC.RING +;COME HERE WITH: SKP USER,SC_#,#/32. +=*1***0 +JPCEX: AR_XJPC+1,J/JPCEX1 +JPCUSR: AR_JPC+1 + JPC_AR,SH DISP,AR_PC +=*10000 + JPC0_AR,NXT INSTR AFTER JPC + JPC1_AR,NXT INSTR AFTER JPC + JPC2_AR,NXT INSTR AFTER JPC + JPC3_AR,NXT INSTR AFTER JPC + JPC4_AR,NXT INSTR AFTER JPC + JPC5_AR,NXT INSTR AFTER JPC + JPC6_AR,NXT INSTR AFTER JPC + JPC7_AR,NXT INSTR AFTER JPC + JPC10_AR,NXT INSTR AFTER JPC + JPC11_AR,NXT INSTR AFTER JPC + JPC12_AR,NXT INSTR AFTER JPC + JPC13_AR,NXT INSTR AFTER JPC + JPC14_AR,NXT INSTR AFTER JPC + JPC15_AR,NXT INSTR AFTER JPC + JPC16_AR,NXT INSTR AFTER JPC + JPC17_AR,NXT INSTR AFTER JPC + +JPCEX1: XJPC_AR,SH DISP,AR_PC +=*10000 + XJPC0_AR,NXT INSTR AFTER JPC + XJPC1_AR,NXT INSTR AFTER JPC + XJPC2_AR,NXT INSTR AFTER JPC + XJPC3_AR,NXT INSTR AFTER JPC + XJPC4_AR,NXT INSTR AFTER JPC + XJPC5_AR,NXT INSTR AFTER JPC + XJPC6_AR,NXT INSTR AFTER JPC + XJPC7_AR,NXT INSTR AFTER JPC + XJPC10_AR,NXT INSTR AFTER JPC + XJPC11_AR,NXT INSTR AFTER JPC + XJPC12_AR,NXT INSTR AFTER JPC + XJPC13_AR,NXT INSTR AFTER JPC + XJPC14_AR,NXT INSTR AFTER JPC + XJPC15_AR,NXT INSTR AFTER JPC + XJPC16_AR,NXT INSTR AFTER JPC + XJPC17_AR,NXT INSTR AFTER JPC +.ENDIF/JPC.RING +.ENDIF/JPC SUPPORT diff --git a/src/ucode/byte.7 b/src/ucode/byte.7 new file mode 100755 index 00000000..391e2cd0 --- /dev/null +++ b/src/ucode/byte.7 @@ -0,0 +1,226 @@ +.TOC "BYTE GROUP -- IBP, ILDB, LDB, IDPB, DPB" + + .DCODE +;133: R, J/IBP ;OR ADJBP +134: RW, J/ILDB ;CAN'T USE RPW BECAUSE OF FPD + R, J/LDB + RW, J/IDPB + R, J/DPB + .UCODE + +;ALL FIVE INSTRUCTIONS OF THIS GROUP ARE CALLED WITH THE BYTE POINTER +;IN THE AR. ALL INSTRUCTIONS SHARE COMMON SUBROUTINES, SO THAT +;THE 10/11 INTERFACE AND STRING MAY ALSO USE THESE SUBROUTINES + +;IBP OR ADJBP +;IBP IF AC#0, ADJBP OTHERWISE +; HERE WITH THE BASE POINTER IN AR + +;IBP: SKP AC#0 ;IS THIS IBP OR ADJBP? +.IF/ADJBP +=1**000 +IBP1: T0_AR,BR/AR, ;SAVE POINTER FOR ADJBP + SC_S,AR_0S,CALL,J/GETSC ; GET BYTE SIZE +.ENDIF/ADJBP +=001 +IBP2: BR/AR,P_P-S,CALL.M, ;NEW P UNLESS OVERFLOW + SKP SCAD0,J/IBPS +.IF/ADJBP + BR/AR,AR_BR,J/ADJBP ;HOLD S IN BR AND MQ +.ENDIF/ADJBP +=101 FIN STORE,I FETCH,J/NOP ;IBP DONE += + +=00*000 +ILDB: BR/AR,P_P-S,BYTE DISP, ;START IBP + CALL.M,J/IBPS ;AND CALL SUBR +=100 +LDB: ARX_AR,SC_P,CALL,J/BYTEA ;BEGIN EA COMPUTATION + SC_FE+SC,CALL,J/LDB1 ;SC_P+S WHILE LOADING AR +=111 AC0_AR,CLR FPD,I FETCH,J/NOP ;DONE += + +=00*000 +IDPB: BR/AR,P_P-S,BYTE DISP, ;START IBP + CALL.M,J/IBPS +=100 +DPB: ARX_AR,SC_P,CALL,J/BYTEA ;COMPUTE EFFECTIVE BYTE ADDR + AR_AC0,TIME/3T,SC_#-SC,#/36., ;COMPUTE 36-P + CALL,SKP SCAD0,J/DPB1 ;CALL DEPOSITOR +=111 +BFIN: FIN STORE,I FETCH ;DONE += +=*1***0 +CLRFPD: CLR FPD,J/FINI ;CAN'T DO THIS UNTIL STORE COMPLETE + J/FINI ;HERE FROM BLKO/BLKI PI += + .TOC "INCREMENT BYTE POINTER SUBROUTINE" + +;THIS SUBROUTINE IS CALLED BY THE INSTRUCTIONS ILDB, IDPB AS +;WELL AS THE MICROCODED 10/11 INTERFACE HANDLER. +;CALL WITH BYTE DISP TESTING FPD AND SIGN OF P-S +;[TIME=2+2(BP OVFLO)] + +=1**010 ;BR12 IRELEVANT +IBPS: STORE,RETURN4 ;SIMPLE, NO OVERFLOW + FE_#,#/36.,GEN AR+1,TIME/2T, ;HERE IF OVRFLO OF WORD + ARX_AR,J/NXTWRD + AR_BR,RETURN4 ;FPD WAS SET, RESTORE AR + AR_BR,RETURN4 ; AND CONVERT TO LDB OR DPB += ;TEST BR12 ONLY +NXTWRD: AR_AR+1,P_FE-S,STORE, + TIME/2T,RETURN4 + + +.TOC "BYTE EFFECTIVE ADDRESS EVALUATOR" + +;ENTER WITH POINTER IN AR, ARX, AND BR +;RETURN1 WITH (EA) LOADING INTO AR AND ARX, +;FPD SET, P IN SC, AND S IN FE +;[TIME=4+1(INDEXED)+?(INDIRECT)] + +BYTEA: MEM_AR,FE_S,SET FPD, ;PUT AWAY UPDATED POINTER + EA MOD DISP ;EVAL BP ADDR +=11**00 +BFETCH: VMA_ARX,BYTE READ,RETURN1 ;START DATA FETCH + VMA_ARX+XR,BYTE READ,RETURN1 ;ADDRESS IS INDEXED + GEN ARX,BYTE INDRCT,J/BYTEI ;DO INDIRECT + GEN ARX+XR,BYTE INDRCT,J/BYTEI ;INDIRECT INDEXED!!! + +BYTEI: ARX_MEM,SKP INTRPT ;WAIT FOR INDIRECT WORD +=0 EA MOD DISP,J/BFETCH ;PROCEED IN ADDR EVAL + SR DISP,J/CLEAN ;INTERRUPTED, CLEAN UP AS REQ'D + .TOC "LOAD BYTE SUBROUTINE" +;ENTER WITH S IN FE, P+S IN SC, AND AR LOAD IN PROGRESS +;SKP INTERRUPT AT ENTRY IS OPTIONAL +;RETURN2 WITH BYTE RIGHT JUSTIFIED IN AR +;[TIME=7] +=1****0 +LDB1: AR_MEM,SC_#-SC,#/36.,SKP SCAD0, ;36-(P+S) + TIME/3T,J/LDB2 + AR_MEM,SR DISP,J/CLEAN ;HERE IF INTERRUPT PENDING += +=*1***0 +LDB2: ARX_SHIFT,AR_0S,SC_FE,J/SHIFT ;BYTE IN ARX HI, READY TO SHIFT + ARX_AR,AR_0S, ;P+S > 36, PUT BYTE IN ARX HI + SC_FE+SC,SKP SCAD0 ;ADJUST S AND SHIFT BYTE + +;PUT BYTE INTO AR RIGHT-JUSTIFIED +; THIS INSTRUCTION ALSO CALLED ALONE AS A SUBROUTINE + +=1****0 +SHIFT: AR_SHIFT,RETURN2 ;RETURN WITH BYTE IN AR + RETURN2 ;BYTE WAS OFF THE END, RETURN AR=0 + + +.TOC "DEPOSIT BYTE SUBROUTINE" +;ENTER WITH BYTE RIGHT JUSTIFIED IN AR, POINTER IN BR, +; S IN FE, 36-P IN SC, AND LOAD AR-ARX STARTED +; SKP IF P>36 +;RETURN3 WITH FINAL STORE IN PROGRESS +;[TIME=11] + +=1****0 +DPB1: MQ_AR,AR_MEM,ARX_MEM, ;GET WORD TO ROTATE 36-P + GEN FE-SC,TIME/3T, ;COMPUTE S-(36-P) + SKP SCAD0,J/DPB2 ;CHECK THAT P+S<36 + MB WAIT,RETURN3 ;P>36, STORE NOTHING + +=*1***0 +DPB2: FE_SC ;P+S>36, S_36-P + ARX_SHIFT,AR_MQ,SC_FE, ;ARX HAS P,X,S + FE_#-SC,#/72. ;SC_S, FE_72-(36-P)=36+P + SC_#-SC,#/36. ;SC_36-S (KNOWN .LE. P) + AR_SHIFT,ARX_SHIFT, ;S,P,X + SC_FE-SC ;SC_(36+P)-(36-S)=P+S + AR_SHIFT,STORE,RETURN3 ;DONE, STORE IT BACK + .TOC "ADJBP" +;HERE FOR ADJUST BYTE POINTER (IBP WITH NON-ZERO AC) +; BYTE SIZE (S) IS RIGHT ADJUSTED IN BR AND MQ +; FULL POINTER IS IN AR, AND SAVED IN T0 + +.IF/ADJBP + +ADJBP: SC_P,AR+ARX+MQ_0.M, ;GET P + SKP BR EQ ;CHECK SIZE IS NON-ZERO + +=1***00 + BRX/ARX,P_SC,CALL.M,J/SIXDIV ;DIVIDE P BY S + AR_T0,J/IFSTAC ;OOPS, S=0, RETURN UNALTERED POINTER + T1_AR,AR_0S,ARX_0S, ;SAVE P/S + SC_FE-SC ;36-P IN SC += +=*1**0* + P_SC,MQ_0.M,CALL.M,J/SIXDIV ;36-P IN AR0-5 + AR_AR+T1,SKP AD NE ;(P/S)+(36-P/S)=BYTES/WORD +=*1***0 + I FETCH,J/NODIVD ;ABORT, BYTES/WORD=0 + T1_AR,BR/AR,AR_ARX ;SAVE BYTES/WORD, READY TO + ; DIVIDE BY IT + T2_AR,AR_MQ ;SAVE REMAIN(36-P/S), GET (36-P)/S + AR_AR*AC0,AD/A+B,ARL/AD, ;ADJUSTMENT IN AR + ARX+MQ_0.M + +;COMPUTE QUOTIENT Q AND REMAINDER R OF ADJUSTMENT/(BYTES/WORD) +; SUCH THAT ADJUSTMENT=Q*(BYTES/WORD)+R, 1 .LE. R .LE. (BYTES/WORD) +; SINCE ADJUSTMENT IS CALCULATED RELATIVE TO LEFT-MOST BYTE OF +; A WORD, THIS GIVES Q AS THE NUMBER OF WORDS BY WHICH TO INDEX THE +; BYTE POINTER, AND R AS THE NUMBER OF BYTES FROM THE LEFT OF THE +; WORD. MULTIPLYING R BY THE BYTE SIZE WILL GIVE THE NUMBER OF BITS +; FROM THE LEFTMOST BYTE, AND ADDING REMAIN(36-P/S) WILL GIVE NUMBER +; OF BITS FROM BIT 0. FINALLY, WE MUST SUBTRACT THIS FROM 36 TO GET +; THE CORRECT P FIELD, WHICH IS ALWAYS RELATIVE TO THE RIGHT EDGE OF +; THE WORD. + +=*1*100 + AC0_AR,SC_1,CALL,J/DIV2 ;DO THE BASIC DIVIDE +=110 ARX_-BRX,FE_#,#/-4,J/ADJD1 ;NEG QUO ==> NEG REMAIN + ARX/MQ,SKP AR NE,FE_#,#/-4 ;POS QUO. IS REMAIN .GT. 0? +=1****0 +ADJD1: AR_AR+T1,J/ADJD2 ;INCREASE REMAIN TO MEET CONSTRAINT + BR/AR,AR_ARX (ADX), ;REMAIN IN RANGE, + ARL+ARX_0.M,J/ADJD3 ; QUOTIENT TO ARR + +ADJD2: BR/AR,AR_ARX-1, ;HOLD UPDATED REMAINDER, + ARL+ARX_0.M ; GET CORRESPONDING QUOTIENT +ADJD3: AR_AR+T0,INH CRY18, ;ADD Q TO Y OF POINTER, + BRX/ARX ;CLR BRX + +=1**00* + AC0_AR,AR_0S,SC_S,CALL,J/GETSC ;SAVE UPDATED Y, GET SIZE + MQ_AR,AR_T2,CLR ARX, ;M'IER IS S, GET REMAIN(36-P/S) + CALL,J/MULREE ;COMPUTE (R*S)+REMAIN(36-P/S) +=11* AR_ARX*2,I FETCH ;PUT THAT IN AR0-5 + SC_P-#,#/36.,AR_AC0 + P_-SC,J/STAC ;THAT'S NEW P, DONE + +.ENDIF/ADJBP + ;SUBROUTINE TO GET CONTENTS OF SC RIGHT ALIGNED IN AR +;[TIME=6] + +GETSC: AR0-8_SC ;PUT SC INTO AR +GETEXP: ARX_AR,SC_#,#/9.,J/SHIFT ;HERE WITH DATA IN AR0-8 + + +;SUBROUTINE FOR SHORT DIVISION, BR KNOWN POSITIVE +; CALL WITH MQ CLEAR, DIVISOR RIGHT-ALIGNED IN BR, AND DIVIDEND +; IN AR0-5 (OR LEFT-ALIGNED IN ARX IF ENTERING AT SDIV) +; RETURN QUOTIENT IN AR AND MQ, REMAIN IN ARX +;[TIME=22+3(RESTORE REQ'D)] + +;TO IMPROVE ADJBP PERFORMANCE, INSERT THE INSTRUCTION SHOWN BELOW +; (SIXDZ), AND CHANGE THE CALLS TO SIXDIV TO "SKP SCAD NE,J/SIXDZ" +;=0 +;SIXDZ: AR_0S,ARX_0S,FE_#,#/36.,RETURN2 ;HERE IF DIVIDEND IS ZERO + +SIXDIV: ARX_AR,AR_0S,FE_#,#/4,J/SDIV- +=*1*0*0 +SDIV: DIVIDE,AR_2(AR+BR),ARX/ADX*2,J/SDIV +SDIV-: DIVIDE,AR_2(AR-BR),ARX/ADX*2,J/SDIV + DIVIDE,AR_AR+BR,J/SDIVR ;NO SHIFT ON FINAL STEP + DIVIDE,AR_AR-BR +=1**1*0 +SDIVR: AR_AR+BR ;NO CRY0 MEANS RESTORE REQ'D + ARX_AR,AR_MQ, ;RETURN QUO IN AR, REMAIN IN ARX + FE_#,#/36.,RETURN2 + \ No newline at end of file diff --git a/src/ucode/define.32 b/src/ucode/define.32 new file mode 100755 index 00000000..e04855b0 --- /dev/null +++ b/src/ucode/define.32 @@ -0,0 +1,1463 @@ +.TITLE "KL10 ITS MICROCODE" + ;FROM "KL10 MICROCODE V126, DEC 17, 75" + +; THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT +; NOTICE AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL +; EQUIPMENT CORPORATION. DIGITAL EQUIPMENT CORPORATION ASSUMES NO +; RESPONSIBILITY FOR ANY ERRORS THAT MAY APPEAR IN THIS DOCUMENT. +; THE SOFTWARE DESCRIBED IN THIS DOCUMENT IS FURNISHED TO THE +; PURCHASER UNDER A LICENSE FOR USE ON A SINGLE COMPUTER SYSTEM AND +; CAN BE COPIED (WITH INCLUSION OF DIGITAL'S COPYRIGHT NOTICE) ONLY +; FOR USE IN SUCH SYSTEM, EXCEPT AS MAY OTHERWISE BE PROVIDED IN WRITING +; BY DIGITAL. +; DIGITAL EQUIPMENT CORPORATION ASSUMES NO RESPONSIBILITY FOR THE +; USE OR RELIABILITY OF ITS SOFTWARE ON EQUIPMENT THAT IS NOT SUPPLIED +; BY DIGITAL. +; COPYRIGHT (C) 1975, DIGITAL EQUIPMENT CORPORATION + +.TOC "MIT REVISION HISTORY" + +;10-OCT-78 - JPC STILL CAN'T BE MADE TO WIN - LOSES PG FLT STATUS +; - ADDED TIME/3T AT UXCT, TO SEE IF INDEXED-XCT LOSSAGE WILL CHANGE +; - REV.10 IS NOW INSTALLED, BUT ONE-PROCEED IS STILL REPORTED +; TO LOSE. THIS HASN'T BEEN DEBUGGED YET. +;09-MAY-78 - CORRECTED INSTRUCTION AT PIBYTE+2 TO DO MQ*4 NOT MQ*2 +; THIS ONLY APPLIES SYSTEMS WITH MULTIPLE DTE20S +; - CHANGED THE 'JPC' PARAMETER FILE TO TURN OFF NXT.INSTR.BITES, +; SINCE WITH NXT.INSTR.BITES ON, JPC TAKES TOO LONG FROM +; FETCH TO NICOND. I THINK THE NXT.INSTR.BITES BUG +; MAY HAVE BEEN FIXED IN REVISION 9, WE WILL SEE. +; - MAKE ADB FIELD DEFAULT TO AR*4 INSTEAD OF FM TO SAVE +; TIME AND AVOID PARITY CHECKING FM. (AFTER DEC 253) +;04-MAY-78 - KI INTERRUPT LOSES CONDITIONAL TURNED OFF, WE MADE +;DL10 USE KA10-TYPE INTERRUPTS QUITE A LONG TIME AGO. +;JRSTF'S SR=17 HACK IS GOING TO HAVE TO GO IN REV.10. (HMM, PERHAPS +;IT WILL STILL WORK, BUT IN REV.10 ABORT INSTR IS JUST AS GOOD.) +;IN REV.10 CAN WE TURN ON JPC AND TURN OFF PT DIR VAL BUG? +;10-MAR-77 (IO 50) - ADDED CODE UNDER "KI INTERRUPT LOSES" +;TO DETECT AND AVOID LOSSAGE WHERE CRETINOUS DL10 SENDS +;WRONG INTERRUPT COMMAND. WOULD DISABLE KI10 VECTOR +;INTERRUPTS ENTIRELY, EXCEPT THAT IMPTER USES THEM. +;28-SEP-76 (IO 45) - TURNED ARX PARITY CHECKING BACK ON +;IN ATTEMPT TO SEE IF THAT'S WHAT'S SCREWING TECO. +;11-SEP-76 (SKPJMP 31) PUT JRST 1, INSTRUCTION BACK IN, HOWEVER +;IT IS JUST A SLOW VERSION OF JRST, DOESN'T PORTALIFY. MRC KEEPS +;COMPLAINING THAT DEC PROGRAMS USE IT AND DECUUO HAS TO EMULATE IT. +;ALSO CHECKED THAT PDL INSTRUCTIONS CAN'T SET A TRAP AND THEN TAKE +;A PAGE FAULT -- IF THEY DID LOSSAGE WOULD OCCUR IN REVISION 10, +;WHICH FIXES LOST ONE PROCEEDS BY MAKING ABORT INSTR IOR TRAP CYC +;INTO TRAP REQ FLAGS INSTEAD OF JAMMING TRAP CYC IN. DIDN'T CHECK +;ARITHMETIC OVERFLOW CASES BUT THEY SHOULD BE OK. + +;7-JUL-76 ADD "CLR INTRPT INH" AT PFT TO PREVENT HANGING +;IN WGRANT FROM PG4++. HAPPENS IF PAGE FAULT ON FETCH OF +;INSTRUCTION IMMEDIATELY AFTER A PI CYCLE. COST = 1 LOCATION. + +;BELOW HERE NOT NECESSARILY IN ANY PARTICULAR ORDER + +;EMULATE I.T.S. PAGING BOX +;NEW INSTRUCTIONS: LPMR, SPM, XCTR, XCTRI, JRSTON +;DELETED INSTRUCTIONS: PORTAL, MAP, SXCT, PXCT, +EIS +; +;JPC FEATURE +; +;MISCELLANEOUS NEW INSTRUCTIONS: CIRC, MVSQZ, LSPGCM, LSPGCS +; +;MAKE POP P,P EXECUTE SAME WAY AS ON KA (STORE AC FIRST, THEN MEMORY) +; +;MOVN/MOVM CAN LOSE PAGE FAIL CODE BECAUSE OF TAKING TOO LONG BETWEEN +;FETCH AND NICOND. KLUDGED UP. LATER SWITCHED TO DEC'S WAY. +; +;SPEED UP SOJ BY GETTING -1 INTO THE MQ WHERE IT CAN BE ADDED TO FM. +; +;ONE-PROCEED FEATURE +;FIX JRSTF TO NOT TURN OFF TRAP FLAGS SO IT CAN BE ONE-PROCEEDED THROUGH +;FIX BUG WHERE PAGE FAULT ON FETCH OF INSTRUCTION JRSTF'ED TO DID AN +;'ABORT INSTR' ALTHOUGH THE NICOND HAD NOT BEEN CLOCKED, THUS LOSING +;THE TRAP FLAGS AND SCREWING ONE-PROCEED. +; +;MAKE BLKI AND BLKO WORK AS INTERRUPT INSTRUCTIONS. HAD LOSSAGE +;WITH SECOND WORD OF VECTORED INTERRUPTS, LOSSAGE WITH FIRST PART DONE +;FLAG, LOSSAGE WITH TAKING ANOTHER INTERRUPT WHILE TRYING TO GET THE +;EBUS EVEN THOUGH PI CYCLE WAS SET. +; +;CAN HANG TRYING TO GET THE EBUS IF BOTH PAGE FAULT AND INTERRUPT +;ON INSTRUCTION FETCH COMING OUT OF A PI CYCLE, CON INTRPT INH IS STILL SET. TRIED TO FIX THIS AT PIFET, LOST. SEE 7-JUL-76. +; +;MAKE DTE20 EXAMINE/DEPOSIT TO 'PHYSICAL' ADDRESS SPACE WORK WHEN +;THERE IS MORE THAN 256K OF MEMORY. +; +;THE HARDWARE CAN CONFUSE AN ADJACENT PAIR OF PT DIR VAL BITS, +;THUS CAUSING EXTRA PAGE REFILLS, IN KL PAGING MODE. CHANGE MICRO CODE +;TO CLEAR BOTH PT DIR ENTRIES WHEN IT CLEARS EITHER; THUS BOTH VALID +;BITS IN A PAIR WILL ALWAYS CONTAIN THE SAME VALUE. +; +;THE HARDWARE DOESN'T NECESSARILY SET UP USER VS EXEC CORRECTLY WHEN +;LOADING THE VMA, SO PAGE REFILL CODE HAS TO CHECK THE USER BIT IN +;THE VMA AND DO AN EXEC REF OR USER REF MACRO AFTER LOADING THE VMA. + +.TOC "DEC REVISION HISTORY" + +;REV WHY +;126 INSERT MISSING COMMA AT STRAC3-2 WHICH CAUSED DMUL TO HANG. +;125 REMOVE NXT INSTR FROM STAC1, STRAC3, & STAC4, MAKING THEM JUMP +; TO FINI INSTEAD. PROBLEM INVOLVES A RACE IF PAGE FAIL OCCURS +; WHILE WRITING FM. IF FM ADDRESS CHANGES BEFORE COND/FM WRITE +; GOES FALSE, APR BOARD MAY GRONK PARITY BIT OF SOME FM LOC'N. +; THIS RESULTS IN SOME SOME PATHS FROM FETCH TO NICOND BECOMING +; LONGER THAN 6 TICKS, SO THE FETCHES GOT SHUFFLED IN SOME PLACES. +; MICROCODE PATCH ELIMINATES MOST PROBABLE CAUSE, WHICH IS PAGE +; FAIL AT NICOND TIME WHILE WRITING AC OTHER THAN 0. IT DOES NOT +; TAKE CARE OF THE POSSIBILITY THAT COND/FM WRITE WILL GLITCH AT +; INSTR 1777 TIME. + ;124 FIXES IN SEVERAL PLACES TO SET AND CLEAR ACCOUNT ENABLE SO AS +; TO GET REPEATABLE ACCOUNTING MEASURES OF USEFUL WORK DONE. THE +; ENABLE IS NOW CLEARED FOR METER UPDATE CYCLES AND KL PAGE REFILL +; CYCLES. THE HARDWARE ALREADY TAKES CARE OF PI CYCLES. +;123 CORRECT 122 TO CONSTRAIN LOC "UNHALT", AND TO LOAD ARX FROM AR, +; SO AS TO LET "SKP AR EQ" WORK. PROBLEM AROSE BECAUSE MACRO ALSO +; TESTS ARX00-01. FIX EDIT, WHEN STORING DEST POINTER ON SELECT +; SIGNIFICANCE START, TO ELIMINATE AMBIGUITY IN DEST P FIELD. +;122 SPEC CHANGE TO EXIT FROM HALT LOOP, SO THAT AR0-8=0 WITH AR9-35 +; NON-ZERO LOADS AR INTO PC TO START PROCESSOR. THIS IS DIFFERENT +; FROM EXECUTING JRST BECAUSE PC FLAGS ARE CLEARED. +;121 FIX TO 120 TO ALLOW A CYCLE BETWEEN FILLER FROM MEMORY AND +; WRITING IT INTO FM (THUS PARITY CAN BE COMPUTED). ALSO CLEAR +; STATE REGISTER IN EDIT BEFORE GETTING NEXT PATTERN BYTE. +;120 FIX EIS TO TOLERATE PAGE FAIL ON READ OF FILL BYTE IN MOVSRJ +; OR B2D CONVERSION. REQUIRES GETTING FILLER BEFORE STORING DLEN +; ALSO INTEGRATE OPCODE COUNTING/TIMING CODE UNDER CONDITIONALS +;117 FIX PARITY ERROR CODE TO WRITEBACK AR ON RPW ERROR. +;116 REWRITE OF DDIV, SO THAT THE NO-DIVIDE TEST IS ON THE MOST +; SIGNIFICANT HALF OF THE MAGNITUDE OF THE DIVIDEND, RATHER THAN +; THE MAGNITUDE OF THE MOST SIGNIFICANT HALF. IN THE PROCESS, +; SAVE TIME AND SPACE. ALSO PUT IN CONDITIONAL ASSEMBLY VARIABLE +; "WRTST" TO INHIBIT WRITE TEST CYCLE FOR INSTRUCTIONS WHICH +; APPEAR NOT TO NEED IT, AND THUS TO SPEED THEM UP. +;115 FIX SBDIAG TO SET MCL REG FUNC TO INHIBIT EBOX MAY BE PAGED. +;114 RECODE STRING COMPARE TO SAVE SPACE AND TIME. CHANGE DEFAULTS +; FOR KLPAGING TO INCLUDE EIS, EXCLUDE TRACKS FEATURE. CHANGE +; KLPAGING (NEW SPEC) TO KEEP "LOGICALLY WRITABLE" IN SOFTWARE BIT +;113 RECODE KL PAGING TO ELIMINATE PROBLEM OF WRITING HARDWARE +; PAGE TABLE BEFORE CHECKING FOR AGE TRAP, AND THEREFORE LEAVING +; THE PAGE ACCESSIBLE AFTER THE TRAP. THE RECODING ALSO IMPROVES +; THE ALGORITHM IN THAT THE HARDWARE ENTRY INCLUDES THE W BIT SET +; IF THE CORE TABLES ALLOWED WRITE AND THE CST INDICATES WRITTEN, +; EVEN IF THE CURRENT REFERENCE WAS NOT A WRITE. +; ALSO FIX CODE WHICH WRITES PT DIR, TO GET WRITE REF BIT FROM +; VMA HELD INTO BIT 5 OF SAVED PAGE FAIL WORD. +;112 FIX PAGE FAIL CODE FOR USE WITH PROB SHEET 1396, WHICH LOADS +; PC IF PAGE FAIL OCCURS ON NICOND. THUS CODE NEEDN'T CHECK FOR +; FETCH AT CLEAN, WHICH CAUSED OTHER PROBLEMS ON PARITY ERRORS. +; CLEAR FE AND SC IN NXT INSTR MACRO (JUST CLEANLINESS). +;111 PATCH SEVERAL ROUTINES WITH THE FOLLOWING MACRO -- + FETCH WAIT "MEM/MB WAIT" +; TO PREVENT SEQUENCES IN WHICH PAGE FAIL INFO CAN GET LOST +; BECAUSE OF LONG TIME FROM REQUEST TO MB WAIT. THESE PATCHES +; SHOULD BE REMOVED AFTER AN ECO HAS BEEN INSTALLED TO FIX. +; IN ADDITION, EBUSX SUBROUTINE HAS BEEN MODIFIED TO PREVENT RACE +; CONDITION WHEN SETTING UP IO FUNCTION WITH COND/EBUS CTL AND +; MAGIC # BIT 4. MUST NOT CHANGE #5 THROUGH #8 ON NEXT CYCLE. +; FIX KLPAGING CODE TO GO BACK TO AREAD ON MAP REF, BECAUSE +; MEM/AD FUNC DOESN'T CORRECTLY RESTORE APR REG FUNC. ALSO MAKE +; THE CODE SMARTER ON NO MATCH CONDITION, SO REQUEST DOESN'T HAVE +; TO BE RESTARTED AND IMMEDIATELY FAIL AGAIN. + ;110 GIVE UP ON THE OLD STRING COMPARE CODE, INSTALLING MIKE NEWMAN'S +; VERSION. SOMEWHAT SLOWER, BUT GIVES THE RIGHT ANSWERS. +; FIX LDB CODE TO WAIT FOR MEM WORD EVEN IF INTERRUPT REQUEST +; SEEN, SO AS NOT TO GET CONFUSED WHEN IT ARRIVES OR PAGE FAILS. +; ALSO IMPROVE CLRPT ROUTINE USED BY CONO AND DATAO PAG TO START +; LOOP WITH VMA CLEARED AND PT WR SELECTION SETUP CORRECTLY. +;107 FIX STRING COMPARES TO CHECK FOR INTERRUPT. THIS INVOLVED +; CHECKING DURING GSRC ROUTINE, WHICH ELIMINATES NEED FOR CHECK +; IN SRCMOD (WHICH CALLS GSRC). IT ALSO REQUIRED CLEARING SFLGS +; AT STARTUP, AND ADJUSTING DLEN UPDATE CODE IN DEST FILL TO GET +; VALID LENGTH STORED ON INTERRUPT. +;106 ELIMINATE RACE IN DECODING OF # FIELD ON MTR BOARD BY HOLDING +; LOW 3 BITS THROUGH NEXT MICROINSTRUCTION. +; FIX LUUO AND MUUO TO ALLOW INTERRUPTS. +; FIX B2D OFFSET TO SIGN-EXTEND E1 AFTER INTERRUPT. FINISH 105, +; TO GET ENTIRE AR LOADED WHILE CLEARING MQ (ARL WAS HOLDING). +; FIX KL PAGING TO USE VMA/1 INSTEAD OF VMA/AD WHEN RESTORING VMA +; FROM VMA HELD OR COPIES THEREOF. +; FIX UFA NOT TO ALWAYS GET UNDERFLOW ON NEGATIVE RESULTS. +; SAME FIX AS EDIT 103 OF BREADBOARD. WHERE DID IT GET LOST? +;105 FIX KL PAGING AS REVISED BY EDIT 103 TO CORRECTLY RESTORE +; BR ON NO-MATCH CONDITION +; ANOTHER FIX TO B2D, TO CLEAR MQ ON ENTRY. BUG INVOLVED GARBAGE +; FROM MQ SHIFTING INTO ARX DURING DEVELOPMENT OF POWER OF TEN. +;104 FIX BINARY TO DECIMAL CONVERSION, WHICH WAS NOT GOING TO CLEAN +; ON FINDING AN INTERRUPT, AND ON RESTART WITH FPD SET, WAS NOT +; SETTING UP SLEN. TSK, TSK. CORRECT CLEANUP FOR DEST FILL IN +; MOVSRJ, WHICH WAS INCREMENTING BOTH SLEN AND DLEN, SHOULD +; HAVE BEEN NEITHER. FIX JSR, BROKEN BY EDIT 103. JUMP MUST BE +; TO E+1, NOT E. +;103 CREATE CONDITIONAL ASSEMBLY FOR EXTENDED ADDRESSING. UNDER IT, +; CREATE MEM FIELD DEFINITIONS, SUPPRESS SXCT. +; SAVE A WORD IN JSR BY USING JSTAC IN COMMON WITH PUSHJ. +; FORCE TIME FIELD IN CASES WHERE ASSEMBLER DEFAULT SCREWS UP. +; ADD INTERRUPT TESTS IN KL PAGING CODE TO PREVENT HANGS, AND +; REVISE PAGE FAIL WORD TO ELIMINATE THE NEW FAIL CODES. +;102 ATTEMPT ANOTHER FIX OF MOVSRJ, CVTBDX FILL. EDIT 71 LOSES +; DUE TO INCONSISTENCY -- DLEN UPDATE MUST NOT PRECEED CLEANUP. +; CREATE CONDITIONAL ASSEMBLY SWITCHES TO CONTROL EXTENDED +; INSTRUCTION SET, DOUBLE INTEGER ARITHMETIC, AND ADJBP. CHANGE +; DEFAULT OF IMULI.OPT, WHICH CAN GET SIGN WRONG ON OVERFLOW. +;101 FIX METER REQUEST CODE TO "ABORT INSTR" EVEN IF NOT SETTING +; PI CYCLE. THIS SHOULD FIX OCCASIONAL LOSS OF TRAPS PROBLEM. +;100 FIXES TO KL PAGING CODE TO PREVENT LOADING VMA FROM AD WHILE +; REQUESTING PHYSICAL REF. FIX JSR TO PREVENT FM PARITY STOP +; ON STORE TO AC. FIX 1777 TO FORCE RECIRCULATION OF AR/ARX, +; EVEN IF MBOX RESP STILL TRUE. +;77 FIX DDIV TO GET MQ SHIFTED LEFT ONE PLACE, WITHOUT INTRODUCING +; AN EXTRA BIT, AT DDVX1. THIS INVOLVES INHIBITING ADA TO PREVENT +; AD CRY0 FROM COMMING INTO MQ35. +;76 FIX UFA TO ALLOW AN EBOX CYCLE BETWEEN FETCH AND NICOND WHEN +; FRACTION SUM IS ZERO, AT UFA3. + ;75 PUT BACK INSTRUCTION "MBREL" REMOVED BY EDIT 64. NECESSARY TO +; ENSURE THAT EBOX REQUEST FOR FETCH DOESN'T COME UP WHILE +; REGISTER FUNCTION IS IN PROGRESS, WHICH WOULD CONFUSE MBOX ON +; STARTING THE FETCH. +;74 CHANGES TO EIS FOR NEW-SPEC AC USAGE. CHANGES TO KL PAGING FOR +; INDIRECT, IMMEDIATE SECTION POINTERS +;73 FIX JRA TO PREVENT WRITING AC WITH DATA FRESH FROM MEMORY (ALLOW +; A CYCLE FOR PARITY CHECK). FIX DPB CODE TAKE ONLY 3 TICKS ON +; RETURN FROM BYTEA, SO THAT CACHE DATA DOESN'T ARRIVE INTO AR +; AND ARX UNTIL DPB1, WHEN THE BYTE HAS GOTTEN OUT TO MQ. +;72 FIX DEFINITION OF SP MEM/UNPAGED TO INHIBIT VMA USER. FIX +; PAGE FAIL CODE TO CHECK FOR VMA FETCH BEFORE LOOKING AT +; INTERRUPT REQUEST. PROBLEM WAS INTERRUPT CONCURRENT WITH +; PAGE FAIL ON JRSTF TO USER. PC FLAGS GOT RESTORED, BUT VMA +; NEVER COPIED TO PC BECAUSE PAGE FAIL INHIBITED NICOND, AND +; INTERRUPT ABORTED PAGE FAIL HANDLING TO LOAD PC. +;71 DEFINE FMADR/AC4=6. FIX MOVFIL ROUTINE TO PUT AWAY UPDATED +; LENGTH DIFFERENCE WHEN INTERRUPTED, THUS AVOIDING RANDOMNESS +; IN MOVSRJ, CVTBDX. FIX CVTBD CALL TO MOVFIL TO PRESERVE SR. +; CHANGE STMAC AND PIDONE FROM "FIN XFER" TO "FIN STORE", BECAUSE +; STORE WAS IN PROGRESS, WHICH CAUSED FM WRITE IF AC REF, AND +; GOT A PARITY ERROR DUE TO ADB/FM. +;70 FIX PXCT 4,[POP ...], WHICH DIDN'T GET DEST CONTEXT SET FOR +; STORE. MUST USE SR_100 TO SET IT. +;67 FIX PROBLEM IN ADJBP BY WHICH BYTES/WORD WAS GETTING LOST +; WHEN DIVIDE ROUTINE LOADED REMAINDER INTO BR. SOLVED BY +; SAVING BYTES/WORD IN T1. +;66 FIX KL PAGING TO RESTORE VMA ON TRAP, SAVE ADDRESS OF POINTER +; CAUSING TRAP, AND NOT RESTORE ARX EXCEPT FOR BLT PAGE FAIL. +; ALSO SET TIME PARAMETER ON ADB/FM TO ALLOW TIME FOR PARITY +; CHECKING OF FM. +;65 FIX KL PAGING CODE TO DO MBWAIT AFTER DETERMINING THAT PARITY +; ERROR HAS NOT OCCURRED, SO AS TO GET CORRECT VMA TO SAVE. +; CREATE SYMBOLS FOR KL PAGE FAIL CODES. PUT CONDITIONAL +; ASSEMBLY AROUND IMULI OPTIMIZATION CODE, AND SXCT. CREATE +; SYMBOL "OPTIONS" IN # FIELD FOR MICROCODE OPTIONS. +;64 MICROCODE FOR KL10 PAGING (PAGE REFILL, MAP INSTR)... +; REMOVE UNNECESSARY INSTRUCTION MBREL: FROM SWEEP AND APRBO +; COSMETIC CHANGES TO KEEP COMMENTS & MACRO DEFINITIONS FROM +; OVERFLOWING LINE OF LISTING, AND INSERTION OF CONDITIONAL +; ASSEMBLY CONTROL OF LONG FLOATING POINT INSTRUCTIONS. +;63 IN MTR REQUEST ROUTINE, DON'T DISMISS WHEN PI CYCLE HASN'T +; BEEN SET. +;62 FIX RDMTR CODE TO PUT 35 IN SC BEFORE GOING TO DMOVEM CODE. +;61 FIX PIIBP ROUTINE TO USE CALL.M INSTEAD OF SPEC/CALL, +; WHICH GETS OVERRIDDEN BY P_P-S... IN MTR REQUEST SERVICE +; ROUTINE, DON'T SET PI CYCLE UNLESS REQUEST IS FOR VECTOR. +;60 FIX DATAO PAG TO DO MB WAIT AFTER STORING EBOX ACCT AND +; BEFORE CHANGING VMA. +;57 RE-CODE USES OF A@, B@ TO USE VMA/1, RATHER THAN VMA/AD, +; IN ORDER TO GET CORRECT CONTEXT ON INDIRECT WORD. SEE MCL4 + ;56 FIX SECOND PART OF PICYCLE (TAG NEXT:) TO ENSURE THAT +; PC+1 INH, KERNEL CYCLE, ETC REMAIN UP DURING 2ND PART. +; ALSO CHANGE SPEC/FLAG CTL FOR ECO 1261, WHICH REQUIRES +; #07 TO BE OPPOSITE OF #04 TO GENERATE SCD LEAVE USER. +;55 FIX SPEC INSTR/SET PI CYCLE TO INHIBIT INTERRUPTS +; (IN PARTICULAR, METER UPDATE REQUESTS). MAKE SURE VALID +; DATA SAVED ON IO PAGE FAIL AND PARITY ERRORS. REMOVE +; BACKWARDS BLT... IT BROKE TOO MANY PROGRAMS. +;54 FIX OVERFLOW CHECK IN IMULI OPTIMIZATION TO INH CRY 18 +; UPDATE TO USE CONDITIONAL ASSEMBLY IN MICRO VERS 20. +;53 FIX T1,T2 PARAMETERS ON BYTE DISP, SIGNS DISP +;52 CORRECT SHIFT AMOUNT FOR IMULI OPTIMIZATION, AND FIX MACRO +; DEFINITIONS FOR SET SR?, WHICH WERE ALWAYS SETTING SR0. +;51 OPTIMIZE IMULI OF TWO POSITIVE OPERANDS (TO SPEED UP SUBSCRIPT +; CALCULATIONS) BY TAKING ONLY 9 MULTIPLY STEPS AND STARTING +; NEXT INSTRUCTION FETCH EARLIER. OPTIMIZATION CAN BE REMOVED +; BY COMMENTING OUT TWO INSTRUCTIONS AT IMULI, AND ONE FOLLOWING +; IMUL. ALSO FIX APRBI/UVERS TO KEEP SERIAL # OUT OF LH. +;50 INTRODUCE SKIP/FETCH AND CODE IN PAGE FAIL RECOVERY TO LOAD +; PC FROM VMA IF PAGE FAIL OCCURED ON FETCH, BECAUSE NICOND +; CYCLE, WHICH SHOULD HAVE LOADED PC, GETS INHIBITED BY INSTR 1777 +; ALSO INCLUDE EXTENDED INSTRUCTION SET. +;47 UNDO XCT CHANGES OF EDIT 46, WHICH BROKE XCT DUE TO INSUFFICIENT +; TIME FOR DRAM HOLD BEFORE USING "A READ". ALSO FIX VECTOR +; INTERRUPT CODE TO LOOK AT CORRECT BITS FOR CONTROLLER NUMBER. +;46 FOLLOW-ON TO EDIT 45, SAVING 2 WORDS AND A CYCLE +; ALSO MOVE JRST TO 600, JFCL TO 700, UUO'S TO 100X AS PREPARATION +; FOR EXTENDED INSTRUCTION SET +;45 FIX SXCT TO LOOK AT AC FIELD OF SXCT, NOT SUBJECT INSTRUCTION, +; WHEN DECIDING WHETHER TO USE BASE-TYPE ADDRESS CALCULATION. +;44 FIX PAGE FAIL LOGIC TO WORK FOR EITHER PAGE FAIL OR PARITY +; ERROR. EDITS 42 AND 43 BOTH WRONG. ALSO CORRECT RACE IN +; WRITING PERFORMANCE ANALYSIS ENABLES TO PREVENT SPURIOUS COUNTS. +;43 CORRECT USE OF PF DISP BY EDIT 42. LOW BITS ARE INVERTED +;42 FIX BUGS INTRODUCED BY EDIT 40, WHICH MADE FLTR OF 1B0 HANG +; TRYING TO NEGATE IT, AND FIX UP EXPONENT CORRECTION ON LONG +; SHIFT LEFT. ALSO PUT IN CODE TO HANDLE PARITY ERROR PAGE +; FAILURES, AND SET TIME CONTROLS ON 43-47. +;41 REWRITE OF VECTOR INTERRUPT PROCESSING TO MAKE DTE VECTORS +; GO TO 142+8N, WHERE N IS DTE#. RH20 GO TO PROGRAMMED ADDRESS +; IN EPT, EXTERNAL DEVICES USE EXEC VIRTUAL ADDRESSES. +;40 IMPROVEMENTS TO FLOATING NORMALIZATION TO MAKE LONG SHIFTS +; FASTER, PRIMARILY TO HELP FLTR +;37 FIX FLOATING DIVIDE SO THAT THE TRUNCATED FORM OF A NEGATIVE +; QUOTIENT IS EQUAL TO THE HIGH-ORDER PART OF THE INFINITE- +; PRECISION QUOTIENT. SEE COMMENTS IN THE CODE. ALSO BUM +; A CYCLE OUT OF FLOATING DIVIDE BY STARTING THE NORMALIZE +; WHILE MOVING THE QUOTIENT INTO AR. +; SEVERAL CHANGES TO MAKE TRACKS FEATURE WORK +;36 FIX CONO MTR TO PUT DATA ON BOTH HALVES, SO PI CAN SEE PIA +;35 FIX CONI PI TO READ BACK WRITE EVEN PARITY ENABLES +;34 FIX BLT USE OF SR, SO NO CORRECTION OF ARX NECESSARY +;33 FIX PAGE TABLE REFERENCES TO FORCE UNPAGED REF. FIX TRAP +; TO SET PC+1 INHIBIT. + ;32 CORRECT SETTING OF SC FOR SHIFTING METER COUNTERS, TO GET +; 12 BITS UNUSED AT RIGHT WHEN IT GETS TO CORE. +;31 RECODE ASH AND ASHC TO SAVE SPACE +;30 FIX JFFO TO SHIFT AR CORRECTLY AT JFFO2. BUM ADJSP TO USE +; STMAC FOR UPDATING PDL POINTER. +;27 FIX CONI PAG TO READ EBUS. CORRECT DEFINITIONS OF MBOX +; REGISTER FUNCTIONS, WHICH HAD BITS 0 AND 3 INVERTED. +;26 FIX DEFINITIONS OF DIAG FUNC CONO MTR AND CONO TIM, WHICH +; WERE REVERSED +;25 FIX DECODING OF PHYSICAL DEVICE NUMBER IN PI FUNCTION CODE +; AND RE-CODE JFCL FOR FEWER MICROWORDS +;24 FIX JFFO TO SHIFT ON FIRST 6-BIT TEST STEP, AND JRSTF TO +; KEEP E AND XR DISTINCT. ALSO SET LOAD-ENABLE BITS IN +; DATAI PAG, WORD. +;23 FIX CONO PI, TO HOLD AR ONTO EBUS THRU REL EBUS, BECAUSE +; PI BOARD DELAYS CONO PI TO GET CONO SET EQUIVALENT. +;22 MORE JFCL FIXES. MUST USE FLAG CTL/JFCL WHILE CLEARING BITS, +; AS WELL AS WHILE TESTING THEM. BUM A WORD OUT OF JFFO BY +; MAKING THE SIXBIT COUNT NEGATIVE. CHANGES SO SHIFT SUBR +; RETURNS 2, BYTEA 1. FIX SETMB TO STORE BACK AND FETCH. +;21 RE-WRITE JFCL TO KEEP LOW OPCODE BITS OUT OF AR0-1, BECAUSE +; PC00 GETS PROPAGATED LEFT TO ADA -1 AND -2. +;20 FIX BLT TO LOAD BR WITH SRC-DST ADDR +; ALSO SET TIME PARAMETERS ON CONDITIONAL FETCH FUNCTIONS +;17 CHANGE SWEEP ONE PAGE TO PUT PAGE # IN E, RATHER THAN ADDR. +; ALSO CHANGE COND/FM WRITE TO MATCH ECO #1068. +;16 FIX JUMP FETCH MACRO TO LOAD VMA FROM PC+1 (TEST SATISFIED +; OVERRIDES THIS TO HOLD VMA). ALSO BUM ONE MICROWORD FROM MUUO. +;15 INCLUDE PAGE FAIL DISP IN DISP/ FIELD +; ALSO MAKE MUUO STORE PROCESS CONTEXT WORD AT 426, AND SETUP +; PCS FROM PC EXTENSION, CWSX FROM SXCT +;14 FIX DEFINITIONS OF SKIP/IO LEGAL, AC#0, SC0, EVEN PAR +; ALSO FIX DATAO PAG, TO SEND LH DATA ON BOTH HALVES OF EBUS +;13 ALIGN SETEBR SO CALL TO SHIFT RETURNS CORRECTLY +;12 MAKE SURE AD COPIES AR DURING DATAO, CONO, AND CLEAR AR AT +; SET DATAI TIME. +;11 FIXES TO CONTINUE CODE SO CONSOLE WORKS, AND CORRECTIONS TO +; PROTECTED DEP/EXAM SO PROTECTION PROTECTS. +;10 FIX A READ MACRO TO VMA/PC+1. AD OVERRIDES UNLESS DRAM A=1 +;07 RE-WRITE OF PI CYCLE CODE TO RECOGNIZE NEW EBUS SPEC. +;06 FIX DEFINITIONS OF SKIPS 40-57 BY COMPLEMENTING 3 LOW ORDER BITS +; FIX MULSUB TO CORRESPOND TO NEW CRA LOGIC +;05 FIX EBUS CTL DEFINITIONS TO GET F01 CORRECT. CORRECT FLAG CTL +; DEFINITIONS TO PREVENT LEAVE USER WHEN NOT WANTED, AND FIX +; JRST/JFCL TO HAVE FLAGS IN AR WHEN NEEDED. +;04 FIX RETURNS FROM MULSUB, PUT BETTER COMMENTS ON SNORM CODE, +; IMPROVE SNORM ALGORITHM TO MINIMIZE WORST-CASE TIME. +;03 FIX DISPATCH ADDRESS PROBLEMS, MOSTLY JRST/JFCL AND UUO'S. +;02 CHANGES PER INSTRUCTION SET REVIEW -- DELETE USE OF BIT12 OF +; BYTE POINTERS, CHANGE BLT TO PUT FINAL SRC,DST ADDRESSES IN AC, +; MAKE TRUNCATE FORM FLOATING POINT REALLY TRUNCATE, ELIMINATE +; LOCAL JSYS SUPPORT, DELETE PXCT OPCODE (XCT W/ NON-ZERO AC IN +; EXEC MODE), LUUO'S GO TO 40/41 OF CURRENT SPACE. +;01 UPDATES FOR .TITLE AND .TOC PSEUDO OPS, +; AND VARIOUS CHANGES FOR PROTO HARDWARE +;00 CREATION, BASED ON BREADBOARD AS OF EDIT 66 + .TOC "CONDITIONAL ASSEMBLY VARIABLE DEFINITIONS" + +; [COST ESTIMATES IN BRACKETS INDICATE NUMBER OF ADDITIONAL +; MICROINSTRUCTIONS REQUIRED BY TURNING ON THE FEATURE SWITCH] + +.DEFAULT/RPW=1 ;1 ENABLES READ-PAUSE-WRITE CYCLES FOR + ;NON-CACHED REFERENCES BY CERTAIN INSTRUCTIONS. + ; [COST = 0] + +.DEFAULT/WRTST=0 ;1 ENABLES WRITE-TEST CYCLES AT AREAD TIME FOR + ;INSTRUCTIONS LIKE MOVEM AND SETZM. [COST = 0] + +.DEFAULT/TRACKS=0 ;1 ENABLES STORING PC AFTER EVERY INSTRUCTION, + ; & CREATES DATAI/O PI TO READ/SETUP PC BUFFER + ;ADDRESS. [COST = 21 WDS] + +.DEFAULT/OP.CNT=0 ;1 ENABLES CODE TO BUILD A HISTOGRAM IN CORE + ; COUNTING USES OF EACH OPCODE IN USER & EXEC + +.DEFAULT/OP.TIME=0 ;1 ENABLES CODE TO ACCUMULATE TIME SPENT BY + ; EACH OPCODE + +.DEFAULT/BACK.BLT=0 ;1 ENABLES BLT TO DECREMENT ADDRESSES ON EACH + ;STEP IF E < RH(AC). BREAKS MANY PROGRAMS. + ; [COST = 9 WDS] + +.DEFAULT/FPLONG=1 ;1 ENABLES KA-STYLE DOUBLE PRECISION FLOATING + ;POINT INSTRUCTIONS: FADL, FSBL, FMPL, FDVL. + ; [COST = 32 WDS] + +.DEFAULT/UFA.DFN=1 ;1 ENABLES UFA AND DFN INSTRS + ; [COST = 17 WORDS] + +.DEFAULT/KLPAGE=0 ;1 ENABLES KL-MODE PAGING. [COST = 85 WDS] + + .IF/KLPAGE +.DEFAULT/XADDR=0 ;1 ENABLES EXTENDED ADDRESSING WITH NEW-TYPE + ; MCL BOARD + .IFNOT/KLPAGE +.SET/XADDR=0 ;CAN'T HAVE EXTENDED ADDRESSING WITHOUT KL PAGE + .ENDIF/KLPAGE + +.DEFAULT/IMULI.OPT=0 ;1 ENABLES OPTIMIZATION OF IMULI TO TAKE ONLY + ;NINE MULTIPLY STEPS [COST = 3 WDS] + ; WARNING: IS BUGGY! + .IFNOT/XADDR +.DEFAULT/SXCT=1 ;1 ENABLES SPECIAL XCT INSTR, WHICH ALLOWS + ; DIAGNOSTICS TO GENERATE LARGE ADDRESSES. + .IF/XADDR ; [COST = 10 WDS] +.SET/SXCT=0 ;DONT NEED SXCT WITH EXTENDED ADDRESSING + .ENDIF/XADDR + +.DEFAULT/EIS=1 ;1 ENABLES EIS INSTRS + +.DEFAULT/DECIMAL=1 ;1 ENABLES DECIMAL-BINARY AND + ; BINARY-DECIMAL CONVERSION EIS INSTRS + ; (WORKS ONLY IF EIS=1) + +.DEFAULT/DBL.INT=1 ;1 ENABLES DOUBLE INTEGER INSTRUCTIONS + ; [COST = 59 WORDS] + +.DEFAULT/ADJBP=1 ;1 ENABLES ADJUST BYTE POINTER + ; [COST = 24 WDS] + +.DEFAULT/ITSPAGE=0 ;1 ENABLES ITS PAGING FEATURES + ; [COST = 91 WDS] + +.DEFAULT/CIRC=0 ;1 ENABLES WINNING CIRC INSTRUCTION + ; [COST = 12 WDS] + +.DEFAULT/CIRC.BIG.OPT=0 ;1 ENABLES GROSS CIRC SPEEDUP + ; [COST = 16 WDS] + +.DEFAULT/MVSQZ=0 ;1 ENABLES MOVE SQUOZE INSTRUCTION + ; [COST = 13 WDS] + +.DEFAULT/LISP=0 ;1 ENABLES WINNING LISP INSTRS + ; [NOT YET IMPLEMENTED] + +.DEFAULT/MUSIC=0 ;1 ENABLES MUSIC PLAYING MICROCODE + ; [COST = ABOUT 100 WORDS??] + +.DEFAULT/JPC=0 ;1 ENABLES JPC FEATURE + ;[COST = 20 WDS] + ;TAKES A LITTLE EXTRA TIME, SOMEONE SHOULD COUNT IT UP. + +.DEFAULT/JPC TEST=0 ;1 ENABLES JPC TEST MODE + +.DEFAULT/JPC SUPPORT=0 ;1 IF JPC OR JPC TEST + +.DEFAULT/JPC.RING=0 ;1 ENABLES 16 JPC'S + ; [COST = COST OF JPC + 3 + 2*<# JPC'S> + ; = 55 WDS] + ;EXEC JPC RING IN AC BLK 4 + ;USER JPC RING IN AC BLK 5 + ;WARNING: NOT COMPLETELY CODED, DOES NOT WORK! + +.DEFAULT/KI INTERRUPT LOSES=0 ;1 ENABLES VECTOR INTERRUPT CHECKING + ;SEE PIVECT IN IO + +.DEFAULT/MAP=1 ;1 ENABLES LOSING MAP INSTRUCTION + ; [COST = 2+2*KLPAGE WDS] + +.DEFAULT/PFAIL.PIHACK=0 ;1 ENABLES PAGE FAILURE TURNING PI OFF + ; [COST = 4 WDS] + +.DEFAULT/JRSTON=0 ;1 ENABLES JRST 17, = PI ON PLUS JRST 2, + ; [COST = 3 WDS] + +.DEFAULT/LPM.SPM=0 ;1 ENABLES LPM AND SPM INSTRUCTIONS + ; AS OPCODES LPMR=076 AND SPM=077 + +.DEFAULT/XCTR=0 ;1 ENABLES OPCODES XCTR=074, XCTRI=075 + ; AND FLUSHES XCT/PXCT AMBIGUITY + ; [COST = 1 WD] + +.DEFAULT/NXT.INSTR.BITES=1 ;1 MEANS NXT INSTR IS + ; INCOMPATIBLE WITH FM WRITE + ; FOR AC1 AND #B# + ;SEE DEC REV HIST 125 FOR WHY + +.DEFAULT/PT DIR VAL BUG=1 ;1 MEANS HARDWARE CONFUSES ADJACENT + ;PT DIR VAL BITS IN KL PAGING MODE + +.DEFAULT/ONE PROCEED=1 ;1 ENABLES TRAP1+TRAP2+ADR BRK INH IN PC + ;TO PROCEED FOR ONE INSTRUCTION THEN + ;TAKE TRAP 3. [COST = ?? WDS] + +.IF/JPC TEST +.CHANGE/JPC SUPPORT=1 +.ENDIF/JPC TEST + +.IF/JPC +.CHANGE/JPC SUPPORT=1 +.ENDIF/JPC + +.IFNOT/JPC +.CHANGE/JPC.RING=0 +.ENDIF/JPC + +.IF/TRACKS ;SETUP CONTROL FOR COMMON CODE + .SET/INSTR.STAT=1 +.ENDIF/TRACKS +.IF/OP.CNT + .SET/INSTR.STAT=1 ;ENABLE COMMON CODE, ERROR IF TRACKS TOO +.ENDIF/OP.CNT +.IF/OP.TIME + .SET/INSTR.STAT=1 ;ERROR IF TRACKS OR OP.CNT ALSO SET +.ENDIF/OP.TIME + .DEFAULT/INSTR.STAT=0 ;IF NO STATISTICS, TURN OFF COMMON CODE + .TOC "HOW TO READ THE MICROCODE -- FORMATS & CONSTRUCTS" + +;(1) FIELD DEFINITIONS +; THESE OCCUR AT THE BEGINNING OF THE LISTING, IN THE SOURCE FILE +; DEFINE.MIC (CONTROL AND DISPATCH RAM DEFINITIONS). +; THEY HAVE THE FORM: +; SYMBOL/=J,K,L,M +; THE FIRST PARAMETER (J) IS MEANINGFUL ONLY WHEN "D" IS SPECIFIED +; AS THE DEFAULT MECHANISM, AND IN THAT CASE, GIVES THE DEFAULT VALUE OF +; THE FIELD IN OCTAL. +; THE SECOND PARAMETER (K) GIVES THE FIELD SIZE IN (DECIMAL) NUMBER +; OF BITS. +; THE THIRD PARAMETER (L) GIVES THE FIELD POSITION IN DECIMAL +; AS THE BIT NUMBER OF THE RIGHTMOST BIT OF THE FIELD. BITS ARE NUMBERED +; FROM 0 ON THE LEFT. NOTE THAT THE POSITION OF BITS IN THE MICROWORD +; SHOWN IN THE LISTING BEARS NO RELATION TO THE ORDERING OF BITS IN THE +; HARDWARE MICROWORD, WHERE FIELDS ARE OFTEN BROKEN UP AND SCATTERED. +; THE FOURTH PARAMETER (M) IS OPTIONAL, AND SELECTS A DEFAULT +; MECHANISM FOR THE FIELD. THE LEGAL VALUES OF THIS PARAMETER ARE THE +; CHARACTERS "D", "T", "P", OR "+". +; "D" MEANS J IS THE DEFAULT VALUE OF THE FIELD IF NO EXPLICIT +; VALUE IS SPECIFIED. +; "T" IS USED ON THE TIME FIELD TO SPECIFY THAT THE VALUE OF THE +; FIELD DEPENDS ON THE TIME PARAMETERS SELECTED FOR OTHER FIELDS. +; THE VALUE OF A FIELD WITH THIS SPECIFICATION DEFAULTS TO THE +; MAX OF , , . +; WITHIN THE KL10 MICROCODE, T1 PARAMETERS ARE USED TO SPECIFY +; FUNCTIONS WHICH DEPEND ON THE ADDER SETUP TIME, AND T2 PARAMETERS +; ARE USED FOR FUNCTIONS WHICH REQUIRE ADDITIONAL TIME FOR CORRECT +; SELECTION OF THE NEXT MICROINSTRUCTION ADDRESS. +; "P" IS USED ON THE PARITY FIELD TO SPECIFY THAT THE VALUE OF THE +; FIELD SHOULD DEFAULT SUCH THAT PARITY OF THE ENTIRE WORD +; IS ODD. IF THIS OPTION IS SELECTED ON A FIELD WHOSE SIZE (K) IS +; ZERO, THE MICRO ASSEMBLER WILL ATTEMPT TO FIND A BIT SOMEWHERE +; IN THE WORD FOR WHICH NO VALUE IS SPECIFIED OR DEFAULTED. +; "+" IS USED ON THE JUMP ADDRESS FIELD TO SPECIFY THAT THE DEFAULT +; JUMP ADDRESS IS THE ADDRESS OF THE NEXT INSTRUCTION ASSEMBLED (NOT, +; IN GENERAL, THE CURRENT LOCATION +1). +; IN GENERAL, A FIELD CORRESPONDS TO THE SET OF BITS WHICH PROVIDE +; SELECT INPUTS FOR MIXERS OR DECODERS, OR CONTROLS FOR ALU'S. +; EXAMPLES: +; AR/=0,3,26,D +; THE MICROCODE FIELD WHICH CONTROLS THE AR MIXER (AND THEREFORE +; THE DATA TO BE LOADED INTO AR ON EACH EBOX CLOCK) IS THREE BITS WIDE +; AND THE RIGHTMOST BIT IS SHOWN IN THE LISTING AS BIT 26 OF THE +; MICROINSTRUCTION. IF NO VALUE IS SPECIFICALLY REQUESTED FOR THE FIELD, +; THE MICROASSEMBLER WILL ENSURE THAT THE FIELD IS 0. +; AD/=0,6,17 +; THE FIELD WHICH CONTROLS THE AD IS 6 BITS WIDE, ENDING ON +; BIT 17. THE FOURTH PARAMETER OF THE FIELD IS OMITTED, SO THE FIELD +; IS AVAILABLE TO THE MICROASSEMBLER (IF NO VALUE IS EXPLICITLY +; CALLED OUT FOR THE FIELD) FOR MODIFICATION TO ENSURE ODD PARITY IN THE +; ENTIRE WORD. + ;(2) VALUE DEFINITIONS +; FOLLOWING A FIELD DEFINITION, SYMBOLS MAY BE CREATED IN THAT +; FIELD TO CORRESPOND TO VALUES OF THE FIELD. THE FORM IS: +; SYMBOL=N,T1,T2 +; "N" IS, IN OCTAL, THE VALUE OF SYMBOL WHEN USED IN THE FIELD. +; T1 AND T2 ARE OPTIONAL, AND SPECIFY PARAMETERS IN THE TIME FIELD +; CALCULATION FOR MICROINSTRUCTIONS IN WHICH THIS FIELD/SYMBOL IS USED. +; THE MICROASSEMBLER COMPUTES THE SUMS OF ALL THE T1'S AND ALL THE T2'S +; SPECIFIED FOR FIELD/SYMBOL SPECIFICATIONS IN A WORD, AND USES THE MAX +; OF THE TWO SUMS AS THE DEFAULT VALUE FOR THE FIELD WHOSE DEFAULT +; MECHANISM IS "T". EXAMPLES: +; AD/=0,6,17 ;FIELD DEFINITION IN WHICH FOLLOWING SYMBOLS EXIST +; XOR=31 +; A+B=6,1 +; HERE THE SYMBOLS "XOR" AND "A+B" ARE DEFINED FOR THE "AD" FIELD. +; TO THE ASSEMBLER, THEREFORE, WRITING "AD/XOR" MEANS PUT THE VALUE 31 +; INTO THE 6-BIT FIELD ENDING ON BIT 17 OF THE MICROWORD. THE SYMBOLS +; ARE CHOSEN FOR MNEMONIC SIGNIFICANCE, OF COURSE, SO ONE READING +; THE MICROCODE WOULD INTERPRET "AD/XOR" AS "THE OUTPUT OF AD SHALL BE THE +; EXCLUSIVE OR OF ITS A AND B INPUTS". SIMILIARLY, "AD/A+B" IS READ AS +; "AD PRODUCES THE SUM OF A AND B". THE SECOND PARAMETER IN THE DEFINITION +; OF "A+B" IS A CONTROL TO THE MICRO ASSEMBLER'S TIME-FIELD CALCULATION, +; WHICH TELLS THE ASSEMBLER THAT THIS OPERATION TAKES LONGER THAN THE +; BASIC CYCLE, AND THEREFORE THAT THE TIME FIELD SHOULD BE INCREASED. +; AR/=0,3,26,D ;FIELD DEFINITION FOR FOLLOWING SYMBOLS +; AR=0 +; AD=2 +; HERE THE SYMBOLS "AR" AND "AD" ARE DEFINED FOR THE FIELD NAMED +; "AR", WHICH CONTROLS THE AR MIXER. WE COULD WRITE AR/AR TO MEAN THAT +; THE AR MIXER SELECT INPUTS WOULD BE 0, WHICH IN THE +; HARDWARE SELECTS THE AR OUTPUT FOR RECIRCULATION TO THE REGISTER. IN +; PRACTICE, HOWEVER, WE WANT THIS TO BE THE DEFAULT CASE, SO THAT AR +; DOES NOT CHANGE UNLESS WE SPECIFICALLY REQUEST IT, SO THE FIELD +; DEFINITION SPECIFIES 0 AS THE DEFAULT VALUE OF THE FIELD. IF WE +; WANT AR LOADED FROM THE AD OUTPUT, WE WRITE "AR/AD" TO SET THE +; MIXER SELECTS TO PASS THE AD OUTPUT INTO THE AR. +; +;(3) LABEL DEFINITIONS +; A MICRO INSTRUCTION MAY BE LABELLED BY A SYMBOL FOLLOWED BY COLON +; PRECEDING THE MICROINSTRUCTION DEFINITION. THE ADDRESS OF THE +; MICROINSTRUCTION BECOMES THE VALUE OF THE SYMBOL IN THE FIELD NAMED "J". +; EXAMPLE: +; FOO: J/FOO +; THIS IS A MICROINSTRUCTION WHOSE "J" FIELD (JUMP ADDRESS) CONTAINS +; THE VALUE "FOO". IT ALSO DEFINES THE SYMBOL "FOO" TO BE THE ADDRESS +; OF ITSELF. THEREFORE, IF EXECUTED BY THE MICROPROCESSOR, IT WOULD +; LOOP ON ITSELF. +; +;(4) COMMENTS +; A SEMICOLON ANYWHERE ON A LINE CAUSES THE REST OF THE LINE +; TO BE IGNORED BY THE ASSEMBLER. THIS TEXT IS AN EXAMPLE OF COMMENTS. + ;(5) MICROINSTRUCTION DEFINITION +; A WORD OF MICROCODE IS DEFINED BY SPECIFYING A FIELD NAME, +; FOLLOWED BY SLASH (/), FOLLOWED BY A VALUE. THE VALUE MAY BE A +; SYMBOL DEFINED FOR THAT FIELD, AN OCTAL DIGIT STRING, OR A DECIMAL +; DIGIT STRING (DISTINGUISHED BY THE FACT THAT IT CONTAINS "8" AND/OR +; "9" AND/OR IS TERMINATED BY A PERIOD). SEVERAL FIELDS MAY BE SPECIFIED +; IN ONE MICROINSTRUCTION BY SEPARATING FIELD/VALUE SPECIFICATIONS WITH +; COMMAS. EXAMPLE: +; ADB/BR,ADA/AR,AD/A+B,AR/AD +; THE FIELD NAMED "ADB" IS GIVEN THE VALUE NAMED "BR" (TO +; CAUSE THE MIXER ON THE B SIDE OF AD TO SELECT BR), FIELD "ADA" HAS VALUE +; "AR", FIELD "AD" HAS VALUE "A+B", AND FIELD "AR" HAS VALUE "AD". +; +;(6) CONTINUATION +; THE DEFINITION OF A MICROINSTRUCTION MAY CONTINUED ONTO TWO OR +; MORE LINES BY BREAKING IT AFTER ANY COMMA. IN OTHER WORDS, IF THE +; LAST NON-BLANK, NON-COMMENT CHARACTER ON A LINE IS A COMMA, THE +; INSTRUCTION SPECIFICATION IS CONTINUED ON THE FOLLOWING LINE. +; EXAMPLE: +; ADB/BR,ADA/AR, ;SELECT AR & BR AS AD INPUTS +; AD/A+B,AR/AD ;TAKE THE SUM INTO AR +; BY CONVENTION, CONTINUATION LINES ARE INDENTED AN EXTRA TAB. +; +;(7) MACROS +; A MACRO IS A SYMBOL WHOSE VALUE IS ONE OR MORE FIELD/VALUE +; SPECIFICATIONS AND/OR MACROS. A MACRO DEFINITION IS A LINE CONTAINING +; THE MACRO NAME FOLLOWED BY A QUOTED STRING WHICH IS THE VALUE OF THE +; MACRO. EXAMPLE: +; AR_AR+BR "ADB/BR,ADA/AR,AD/A+B,AR/AD" +; THE APPEARANCE OF A MACRO IN A MICROINSTRUCTION DEFINITION IS EQUIVALENT +; TO THE APPEARANCE OF ITS VALUE. MACROS FOR VARIOUS FUNCTIONS +; ARE DEFINED IN "MACRO.MIC". +; +;(8) PSEUDO OPS +; THE MICRO ASSEMBLER HAS 10 PSEUDO-OPERATORS: +;.DCODE AND .UCODE SELECT THE RAM INTO WHICH SUBSEQUENT MICROCODE WILL +;BE LOADED, AND THEREFORE THE FIELD DEFINITIONS AND MACROS WHICH ARE +;MEANINGFUL IN SUBSEQUENT MICROCODE +;.TITLE DEFINES A STRING OF TEXT TO APPEAR IN THE PAGE HEADER, AND +;.TOC DEFINES AN ENTRY FOR THE TABLE OF CONTENTS AT THE BEGINNING. +;.SET DEFINES THE VALUE OF A CONDITIONAL ASSEMBLY PARAMETER, +;.CHANGE REDEFINES A CONDITIONAL ASSEMBLY PARAMETER, +;.DEFAULT ASSIGNS A VALUE TO AN UNDEFINED PARAMETER. +;.IF ENABLES ASSEMBLY IF THE VALUE OF THE PARAMETER IS NOT ZERO, +;.IFNOT ENABLES ASSEMBLY IF THE PARAMETER VALUE IS ZERO, AND +;.ENDIF RE-ENABLES ASSEMBLY IF SUPPRESSED BY THE PARAMETER NAMED. +;(9) LOCATION CONTROL +; A MICROINSTRUCTION "LABELLED" WITH A NUMBER IS ASSIGNED TO THAT +; ADDRESS. +; THE CHARACTER "=" AT THE BEGINNING OF A LINE, FOLLOWED BY +; A STRING OF 0'S, 1'S, AND/OR *'S, SPECIFIES A CONSTRAINT ON THE +; ADDRESS OF FOLLOWING MICROINSTRUCTIONS. THE NUMBER OF CHARACTERS +; IN THE CONSTRAINT STRING (EXCLUDING THE "=") IS THE NUMBER OF LOW-ORDER +; BITS CONSTRAINED IN THE ADDRESS. THE MICROASSEMBLER ATTEMPTS TO FIND +; AN UNUSED LOCATION WHOSE ADDRESS HAS 0 BITS IN THE POSITIONS +; CORRESPONDING TO 0'S IN THE CONSTRAINT STRING AND 1 BITS WHERE THE +; CONSTRAINT HAS 1'S. ASTERISKS DENOTE "DON'T CARE" BIT POSITIONS. +; IF THERE ARE ANY 0'S IN THE CONSTRAINT STRING, THE CONSTRAINT +; IMPLIES A BLOCK OF <2**N> MICROWORDS, WHERE N IS THE NUMBER OF 0'S +; IN THE STRING. ALL LOCATIONS IN THE BLOCK WILL HAVE 1'S IN THE ADDRESS +; BITS CORRESPONDING TO 1'S IN THE STRING, AND BIT POSITIONS DENOTED BY *'S +; WILL BE THE SAME IN ALL LOCATIONS OF THE BLOCK. +; IN SUCH A CONSTRAINT BLOCK, THE DEFAULT ADDRESS PROGRESSION IS +; COUNTING IN THE "0" POSITIONS OF THE CONSTRAINT STRING, BUT A NEW +; CONSTRAINT STRING OCCURING WITHIN A BLOCK MAY FORCE SKIPPING OVER +; SOME LOCATIONS OF THE BLOCK. WITHIN A BLOCK, A NEW CONSTRAINT +; STRING DOES NOT CHANGE THE PATTERN OF DEFAULT ADDRESS PROGRESSION, IT +; MERELY ADVANCES THE LOCATION COUNTER OVER THOSE LOCATIONS. THE +; MICROASSEMBLER WILL LATER FILL THEM IN. +; A NULL CONSTRAINT STRING ("=" FOLLOWED BY ANYTHING BUT "0", +; "1", OR "*") SERVES TO TERMINATE A CONSTRAINT BLOCK. +; EXAMPLES: +; =0 +; THIS SPECIFIES THAT THE LOW-ORDER ADDRESS BIT MUST BE ZERO-- +; THE MICROASSEMBLER FINDS AN EVEN-ODD PAIR OF LOCATIONS, AND PUTS +; THE NEXT TWO MICROINSTRUCTIONS INTO THEM. +; =11 +; THIS SPECIFIES THAT THE TWO LOW-ORDER BITS OF THE ADDRESS MUST +; BOTH BE ONES. SINCE THERE ARE NO 0'S IN THIS CONSTRAINT, THE +; ASSEMBLER FINDS ONLY ONE LOCATION MEETING THE CONSTRAINT. +; =0***** +; THIS SPECIFIES AN ADDRESS IN WHICH THE "40" BIT IS ZERO. DUE +; TO THE IMPLEMENTATION OF THIS FEATURE IN THE ASSEMBLER, THE DEFAULT +; ADDRESS PROGRESSION APPLIES ONLY TO THE LOW-ORDER 5 BITS, SO THIS +; CONSTRAINT FINDS ONE WORD IN WHICH THE "40" BIT IS ZERO, AND DOES +; NOT ATTEMPT TO FIND ONE IN WHICH THAT BIT IS A ONE. + .TOC "MICROCODE LISTING TEMPLATE" +;HERE IS A TEMPLATE WHICH CAN BE USED WITH THE MICROCODE +; LISTING TO IDENTIFY FIELDS IN THE OUTPUT -- + + +; ---- ---- ---- ---- ---- ---- ---- ---- +; [--] [--] []!! !!!! !!!! !![] [][] ![-] +; ! ! !!! !!!! !!!! !! ! ! ! ! + # = MAGIC NUMBERS +; ! ! !!! !!!! !!!! !! ! ! ! + MARK = SCOPE SYNC +; ! ! !!! !!!! !!!! !! ! ! ! +; ! ! !!! !!!! !!!! !! ! ! + DISP/SPEC = SPECIAL FUNCTIONS +; ! ! !!! !!!! !!!! !! ! + SKIP/COND = SPECIAL FUNCTIONS +; ! ! !!! !!!! !!!! !! ! +; ! ! !!! !!!! !!!! !! + TIME, MEM = UINST TIME & MEM FUNCTION +; ! ! !!! !!!! !!!! !+ VMA = VMA INPUT SELECT +; ! ! !!! !!!! !!!! + SH/ARMM = SH FUNCTION / ARMM SELECT +; ! ! !!! !!!! !!!! +; ! ! !!! !!!! !!!+ SC, FE = SC INPUT SELECT & FE LOAD +; ! ! !!! !!!! !!+ SCADB = SELECT FOR SCAD "B" INPUT +; ! ! !!! !!!! !+ SCADA = ENABLE AND SELECT FOR SCAD "A" INPUT +; ! ! !!! !!!! + SCAD = SC/FE ADDER FUNCTION +; ! ! !!! !!!! +; ! ! !!! !!!+ FM ADR = FAST MEMORY ADDRESS SELECT +; ! ! !!! !!+ BR, BRX, MQ = LOAD BR & BRX, SEL FOR MQ +; ! ! !!! !+ ARX = SELECT FOR ARX INPUT +; ! ! !!! + AR = SELECT FOR AR INPUT +; ! ! !!! +; ! ! !!+ ADB = SELECT FOR ADDER "B" INPUT +; ! ! !+ ADA = SELECT AND ENABLE FOR ADDER "A" INPUT +; ! ! + AD = OPERATION IN ADDER AND ADDER EXTENSION +; ! ! +; ! + J = BASE ADDRESS TO WHICH THIS MICROINSTRUCTION JUMPS +; ! +; + LOCATION IN CRAM INTO WHICH THIS WORD IS LOADED +; +; U/V = MICRO INSTRUCTION FOR CRAM + +;******************************************************************* + +; D = WORD FOR DRAM +; +; + LOCATION IN DRAM INTO WHICH THIS WORD IS LOADED +; ! +; ! + A = OPERAND ACCESS CONTROL +; ! !+ B = INSTRUCTION "MODE" +; ! !! + P = PARITY FOR THIS WORD +; ! !! ! +; ! !! ! + J = ADDRESS OF HANDLER FOR THIS INSTRUCTION +; [--] !! ! [--] +; ---- ---- ---- + .TOC "KL10 INSTRUCTION OPCODE MAP" + +; 0 1 2 3 4 5 6 7 +;000 UUO LUUO LUUO LUUO LUUO LUUO LUUO LUUO +;010 LUUO LUUO LUUO LUUO LUUO LUUO LUUO LUUO +;020 LUUO LUUO LUUO LUUO LUUO LUUO LUUO LUUO +;030 LUUO LUUO LUUO LUUO LUUO LUUO LUUO LUUO +;040 UUO UUO UUO UUO UUO UUO UUO UUO +;050 UUO UUO UUO UUO UUO UUO UUO UUO +;060 UUO UUO UUO UUO UUO UUO UUO UUO +;070 LSPGCM LSPGCS UUO UUO XCTR XCTRI LPMR SPM +; 0 1 2 3 4 5 6 7 +;100 LSPDBG UUO UUO UUO MVSQZ ADJSP UUO SXCT +;110 DFAD DFSB DFMP DFDV DADD DSUB DMUL DDIV +;120 DMOVE DMOVN FIX EXTEND DMOVEM DMOVNM FIXR FLTR +;130 UFA DFN FSC IBP ILDB LDB IDPB DPB +;140 FAD FADL FADM FADB FADR FADRI FADRM FADRB +;150 FSB FSBL FSBM FSBB FSBR FSBRI FSBRM FSBRB +;160 FMP FMPL FMPM FMPB FMPR FMPRI FMPRM FMPRB +;170 FDV FDVL FDVM FDVB FDVR FDVRI FDVRM FDVRB +; 0 1 2 3 4 5 6 7 +;200 MOVE MOVEI MOVEM MOVES MOVS MOVSI MOVSM MOVSS +;210 MOVN MOVNI MOVNM MOVNS MOVM MOVMI MOVMM MOVMS +;220 IMUL IMULI IMULM IMULB MUL MULI MULM MULB +;230 IDIV IDIVI IDIVM IDIVB DIV DIVI DIVM DIVB +;240 ASH ROT LSH JFFO ASHC ROTC LSHC CIRC +;250 EXCH BLT AOBJP AOBJN JRST JFCL XCT MAP +;260 PUSHJ PUSH POP POPJ JSR JSP JSA JRA +;270 ADD ADDI ADDM ADDB SUB SUBI SUBM SUBB +; 0 1 2 3 4 5 6 7 +;300 CAI CAIL CAIE CAILE CAIA CAIGE CAIN CAIG +;310 CAM CAML CAME CAMLE CAMA CAMGE CAMN CAMG +;320 JUMP JUMPL JUMPE JUMPLE JUMPA JUMPGE JUMPN JUMPG +;330 SKIP SKIPL SKIPE SKIPLE SKIPA SKIPGE SKIPN SKIPG +;340 AOJ AOJL AOJE AOJLE AOJA AOJGE AOJN AOJG +;350 AOS AOSL AOSE AOSLE AOSA AOSGE AOSN AOSG +;360 SOJ SOJL SOJE SOJLE SOJA SOJGE SOJN SOJG +;370 SOS SOSL SOSE SOSLE SOSA SOSGE SOSN SOSG +; 0 1 2 3 4 5 6 7 +;400 SETZ SETZI SETZM SETZB AND ANDI ANDM ANDB +;410 ANDCA ANDCAI ANDCAM ANDCAB SETM SETMI SETMM SETMB +;420 ANDCM ANDCMI ANDCMM ANDCMB SETA SETAI SETAM SETAB +;430 XOR XORI XORM XORB IOR IORI IORM IORB +;440 ANDCB ANDCBI ANDCBM ANDCBB EQV EQVI EQVM EQVB +;450 SETCA SETCAI SETCAM SETCAB ORCA ORCAI ORCAM ORCAB +;460 SETCM SETCMI SETCMM SETCMB ORCM ORCMI ORCMM ORCMB +;470 ORCB ORCBI ORCBM ORCBB SETO SETOI SETOM SETOB +; 0 1 2 3 4 5 6 7 +;500 HLL HLLI HLLM HLLS HRL HRLI HRLM HRLS +;510 HLLZ HLLZI HLLZM HLLZS HRLZ HRLZI HRLZM HRLZS +;520 HLLO HLLOI HLLOM HLLOS HRLO HRLOI HRLOM HRLOS +;530 HLLE HLLEI HLLEM HLLES HRLE HRLEI HRLEM HRLES +;540 HRR HRRI HRRM HRRS HLR HLRI HLRM HLRS +;550 HRRZ HRRZI HRRZM HRRZS HLRZ HLRZI HLRZM HLRZS +;560 HRRO HRROI HRROM HRROS HLRO HLROI HLROM HLROS +;570 HRRE HRREI HRREM HRRES HLRE HLREI HLREM HLRES +; 0 1 2 3 4 5 6 7 +;600 TRN TLN TRNE TLNE TRNA TLNA TRNN TLNN +;610 TDN TSN TDNE TSNE TDNA TSNA TDNN TSNN +;620 TRZ TLZ TRZE TLZE TRZA TLZA TRZN TLZN +;630 TDZ TSZ TDZE TSZE TDZA TSZA TDZN TSZN +;640 TRC TLC TRCE TLCE TRCA TLCA TRCN TLCN +;650 TDC TSC TDCE TSCE TDCA TSCA TDCN TSCN +;660 TRO TLO TROE TLOE TROA TLOA TRON TLON +;670 TDO TSO TDOE TSOE TDOA TSOA TDON TSON + .TOC "CONTROL RAM DEFINITIONS -- AD" +;FIELDS ARRANGED FOR READABILITY, NOT COMPACTNESS +; IN THE PROCESSOR, BITS ARE SCATTERED IN ANOTHER ORDER + +U0/=0,1,0,D ;BIT 0 UNUSED +J/=0,11,11,+ ;SYMBOLS WILL BE DEFINED BY TAGS (CRA1&CRA2) + +;MAIN ADDER CONTROLS + +AD/=0,6,17 ; (EDP3, EXCEPT CARRY IN, ON CTL1) + ;BIT 0 = CARRY IN, BIT 1 = BOOLE + ;BITS 2-5 = S8-S1 OF 10181 ALU + ;ARITHMETIC, AD AND ADX SEPARATED + ;72 BIT ARITHMETIC REQUIRES SPEC/AD LONG + A+1=40,1 + A+XCRY=00,1 +; A+ANDCB=01,1 +; A+AND=02,1 + A*2=03,1 + A*2+1=43,1 +; OR+1=44,1 +; OR+ANDCB=05,1 + A+B=06,1 + A+B+1=46,1 +; A+OR=07,1 + ORCB+1=50,1 + A-B-1=11,1 + A-B=51,1 +; AND+ORCB=52,1 +; A+ORCB=53,1 + XCRY-1=54,1 +; ANDCB-1=15,1 +; AND-1=16,1 + A-1=17,1 + ;ADDER LOGICAL FUNCTIONS + SETCA=20 + ORC=21 ;NAND + ORCA=22 + 1S=23 + ANDC=24 ;NOR + SETCB=25 + EQV=26 + ORCB=27 + ANDCA=30 + XOR=31 + B=32 + OR=33 + 0S=34 + ANDCB=35 + AND=36 + A=37 + ;BOOLEAN FUNCTIONS FOR WHICH CRY0 IS INTERESTING + CRY A EQ -1=60,1 ;GENERATE CRY0 IF A=1S, AD=SETCA + CRY A.B#0=36,1 ;CRY 0 IF A&B NON-ZERO, AD=AND + CRY A#0=37,1 ;GENERATE CRY0 IF A .NE. 0, AD=A + CRY A GE B=71,1 ;CRY0 IF A .GE. B, UNSIGNED; AD=XOR + .TOC "CONTROL RAM DEFINITIONS -- DATA PATH MIXERS" + +ADA/=0,3,20 ; (EDP3) + AR=0 + ARX=1 + MQ=2 + PC=3 +ADA EN/=0,1,18 ;ADA ENABLE ALSO ENABLES ADXA (EDP3) + EN=0 + 0S=1 +U21/=0,1,21,D ;BIT 21 UNUSED +ADB/=0,2,23 ;CONTROLS ADB AND ADXB (EDP3) + FM=0,,1 ;MUST HAVE TIME FOR PARITY CHECK + BR*2=1 + BR=2 + AR*4=3 +U23/=1,1,23,D ;PREVENT DEFAULT SELECTION OF FM +AR/=0,3,26,D ; (EDP1) + AR=0 + ARMM=0 ;REQUIRES SPECIAL FUNCTION + CACHE=1 ;ORDINARILY SELECTED BY HWARE + AD=2 + EBUS=3 + SH=4 + AD*2=5 + ADX=6 + AD*.25=7 +ARX/=0,3,29,D ; (EDP2) +; ARX=0 ;BY DEFAULT + CACHE=1 ;ORDINARILY BY MBOX RESP + AD=2 + MQ=3 + SH=4 + ADX*2=5 + ADX=6 + ADX*.25=7 +BR/=0,1,30,D ;DEFAULT TO RECIRCULATE (EDP4) + AR=1 +BRX/=0,1,31,D ;DEFAULT TO RECIRCULATE (EDP4) + ARX=1 +MQ/=0,1,32,D ;DEFAULT TO RECIRCULATE (EDP2) + SH=1 ;LOAD FROM SHIFT MATRIX + MQ*2=0 ;WITH SPEC/MQ SHIFT + MQ*.25=1 ;WITH SPEC/MQ SHIFT + MQ SEL=0 ;WITH COND/REG CTL + MQM SEL=1 ;WITH COND/REG CTL +FMADR/=0,3,35 ; (APR4&APR5) + AC0=0 ;IR 9-12 + AC1=1 ;+1 MOD 16 + XR=2 ;ARX 14-17 + VMA=3 ;VMA 32-35 + AC2=4 ;+2 MOD 16 + AC3=5 ;+3 MOD 16 + AC4=6 ;CURRENT BLOCK, AC+4 + #B#=7 ;BLOCK AND AC SELECTED BY # FIELD + .TOC "CONTROL RAM DEFINITIONS -- 10-BIT LOGIC" + +SCAD/=0,3,38 ; (SCD1) + A=0 + A-B-1=1 + A+B=2 + A-1=3 + A+1=4 + A-B=5 + OR=6 + AND=7 +SCADA/=0,3,41 ; (SCD1) + FE=0 + AR0-5=1 ;BYTE POINTER P FIELD + AR EXP=2 ; XOR + #=3 ;SIGN EXTENDED WITH #00 +SCADA EN/=0,1,39 ; (SCD1) + 0S=1 +U42/=0,1,42,D ;BIT 42 UNUSED +SCADB/=0,2,44 ; (SCD1) + SC=0 + AR6-11=1 ;BYTE POINTER S FIELD + AR0-8=2 + #=3 ;NO SIGN EXTENSION +U45/=0,1,45,D ;BIT 45 UNUSED +SC/=0,1,46,D ;RECIRCULATE BY DEFAULT (SCD2) + FE=0 ;WITH SCM ALT + SCAD=1 + AR SHIFT=1 ;WITH SCM ALT ;AR 18, 28-35 +FE/=0,1,47,D ;RECIRCULATE BY DEFAULT (SCD2) + SCAD=1 +U48/=0,1,48,D ;BIT 48 UNUSED + ;OTHER COMPLEX FUNCTIONS +SH/=0,2,50 ; (SH1) + SHIFT AR!ARX=0 ;LEFT BY (SC) + AR=1 + ARX=2 + AR SWAP=3 ;HALVES SWAPPED +ARMM/=0,2,50 ;SAME BITS AS SH CONTROL (SCD3) + #=0 ;MAGIC # 0-8 TO AR 0-8 + EXP_SIGN=1 ;AR1-8 _ AR0 + SCAD EXP=2 ;AR0-8_SCAD + SCAD POS=3 ;AR0-5_SCAD +U51/=0,1,51,D ;BIT 51 UNUSED +VMA/=0,2,53,D ;ALSO CONTROLLED BY SPECIAL FUNCTIONS + VMA=0 ;BY DEFAULT + PC=1 ;MAY BE OVERRIDDEN BY MCL LOGIC + PC+1=2 ; TO LOAD VMA FROM AD + AD=3 +TIME/=0,2,55,T ;CONTROLS MINIMUM MICROINSTRUCTION EXECUTION + ; TIME, COUNTING MBOX CLOCK TICKS (CLK) + ;ASSEMBLER GENERALLY TAKES CARE OF THIS + 2T=0 ;2 TICKS + 3T=1 ;3 TICKS + 4T=2 ;4 TICKS + 5T=3 ;5 TICKS (COND/DIAG FUNC & #00, --> .5 USEC) + .TOC "CONTROL RAM DEFINITIONS -- MEM SPECIAL FUNCTIONS" + +MEM/=0,4,59,D ; (MCL1) +; NOP=0 ;DEFAULT + ARL IND=1 ;CONTROL AR LEFT MUX FROM # FIELD + MB WAIT=2 ;WAIT FOR MBOX RESP IF PENDING +; SEC 0=3 ;CLEAR VMAX + A RD=4 ;OPERAND READ + B WRITE=5 ;CONDITIONAL WRITE ON DRAM B 01 + FETCH=6 ;LOAD NEXT INSTR TO ARX (CONTROL BY #) + REG FUNC=7 ;MBOX REGISTER FUNCTIONS +.IFNOT/XADDR ;OLD-STYLE MCL BOARD + A IND=10 ;A-TYPE INDIRECT + BYTE IND=11 ;BYTE-TYPE INDIRECT + LOAD AR=12 + LOAD ARX=13 + AD FUNC=14 ;FUNCTION FROM AD LEFT + BYTE RD=15 ;BYTE READ TO BOTH AR AND ARX + WRITE=16 ;FROM AR TO MEMORY + RPW=17 ;LOAD AR WITH RPW CYCLE +.IF/XADDR + AD FUNC=10 ;FUNCTION LOADED FROM AD LEFT + EA CALC=11 ;FUNCTION DECODED FROM # FIELD + LOAD AR=12 + LOAD ARX=13 + RW=14 ;READ, TEST WRITABILITY + RPW=15 ;READ-PAUSE-WRITE + WRITE=16 + IFET=17 ;UNCONDITIONAL FETCH +.ENDIF/XADDR + .TOC "CONTROL RAM DEFINITIONS -- SKIP/COND SPECIAL FUNCTIONS" + +SKIP/=0,6,65,D ;MICRO-PROGRAM SKIPS + ; 40-57 DECODED ON (CRA2) +; SPARE=40 + EVEN PAR=41,,1 ;AR PARITY IS EVEN + BR0=42 ;BR BIT 00 + ARX0=43 ;ARX BIT 00 + AR18=44 ;AR BIT 18 + AR0=45 ;AR BIT 00 + AC#0=46 ;IR9-12 .EQ. 0 + SC0=47 ;SC BIT 00 + SC .LT. 36=50 + SCAD0=51,,1 ;SIGN OF SCAD OUTPUT + SCAD#0=52,,1 ;SCAD OUTPUT IS NON-ZERO + ADX0=53,1 ;ADDER EXTENSION BIT 00 + AD CRY0=54,1 ;CARRY OUT OF AD BIT -2 (BOOLE IGNORED) + AD0=55,1 ;ADDER BIT 00 + AD#0=56,1 ;AD BITS 00-35 CONTAIN SOME ONES +; SPARE=57 + ; 60-77 DECODED ON (CON2) + FETCH=60 ;VMA FETCH (LAST CYCLE WAS A FETCH) + KERNEL=61 ;PC IS IN KERNEL MODE + USER=62 ;PC IS IN USER MODE + PUBLIC=63 ;PC IS PUBLIC (INCLUDING SUPER) + RPW REF=64 ;MIDDLE OF READ-PAUSE-WRITE CYCLE + PI CYCLE=65 ;PI CYCLE IN PROGRESS + -EBUS GRANT=66 ;PI HASN'T RELEASED BUS FOR CPU USE + -EBUS XFER=67 ;NO TRANSFER RECIEVED FROM DEVICE + INTRPT=70 ;AN INTERRUPT REQUEST WAITING FOR SERVICE + -START=71 ;NO CONTINUE BUTTON + RUN=72 ;PROCESSOR NOT HALTED + IO LEGAL=73 ;KERNEL, PI CYCLE, USER IOT, OR DEVICE .GE. 740 + P!S XCT=74 ;PXCT OR SXCT +; EBOX PF=75 ;EBOX SHOULD HANDLE THIS PAGE FAIL + AC REF=76,,1 ;VMA .LT. 20 ON READ OR WRITE + -MTR REQ=77 ;INTERRUPT REQUEST NOT DUE TO METER + +;SKIP/COND FIELD CONTINUED + +COND/=0,6,65,D ;NON-SKIP SPECIAL FUNCTIONS + ;0-7 DECODED ON (CTL2) +; NOP=0 ;BY DEFAULT + LD AR0-8=1 + LD AR9-17=2 + LD AR18-35=3 + AR CLR=4 + ARX CLR=5 + ARL IND=6 ;CONTROL AR LEFT, CALL, AND CLEAR BITS FROM # + REG CTL=7 ;CONTROL AR LOAD, EXP TST, AND MQ FROM # + ; 10-37 DECODED ON (CON1) + FM WRITE=10 ;WRITE AR INTO CURRENTLY ADDRESSED FM LOC + PCF_#=11 ;SET PC FLAGS FROM # FIELD + FE SHRT=12 ;SHIFT FE RIGHT 1 + AD FLAGS=13 ;SET PC CRY0, CRY1, OVRFLO, TRAP1 AS APPROPRIATE + LOAD IR=14 ;LATCH AD OR CACHE DATA INTO IR + SPEC INSTR=15 ;SET/CLR SXCT, PXCT, PICYC, TRAP INSTR FLAGS + SR_#=16 ;CONTROL FOR STATE REGISTER + SEL VMA=17 ;READ VMA THROUGH ADA/PC + DIAG FUNC=20 ;SELECT DIAGNOSTIC INFO ONTO EBUS + EBOX STATE=21 ;SET STATE FLOPS + EBUS CTL=22 ;I/O FUNCTIONS + MBOX CTL=23 +; SPARE=24 +; SPARE=25 +; SPARE=26 +; SPARE=27 + VMA_#=30 + VMA_#+TRAP=31 + VMA_#+MODE=32 + VMA_#+AR32-35=33 + VMA_#+PI*2=34 + VMA DEC=35 ;VMA_VMA-1 + VMA INC=36 ;VMA_VMA+1 + LD VMA HELD=37 ;HOLD VMA ON SIDE +U66/=0,1,66,D ;BIT 66 UNUSED + .TOC "CONTROL RAM DEFINITIONS -- DISP/SPEC SPECIAL FUNCTIONS" + +DISP/=10,5,71,D ;0-7 AND 30-37 ARE DISPATCHES (CRA1&CRA2) + DIAG=0 + DRAM J=1 + DRAM A RD=2 ;IMPLIES INH CRY18 + RETURN=3 ;POPJ RETURN + PG FAIL=4 ;PAGE FAIL TYPE DISP + SR=5 ;16 WAYS ON STATE REGISTER + NICOND=6 ;NEXT INSTRUCTION CONDITION + SH0-3=7,,2 ;16 WAYS ON HIGH-ORDER BITS OF SHIFTER + MUL=30 ;IMPLIES MQ SHIFT, AD LONG + DIV=31,,1 ;IMPLIES MQ SHIFT, AD LONG + SIGNS=32,1 ;AR0*4 + BR0*2 + AD0 + DRAM B=33 ;8 WAYS ON DRAM B FIELD + BYTE=34,,1 ;FPD*4 + BR12*2 + SCAD0 + NORM=35,2 ;IMPLIES AD LONG + EA MOD=36 ;@*2 + XR + EA TYPE=37 + +SPEC/=10,5,71,D ;NON-DISPATCH SPECIAL FUNCTIONS (CTL1) +; NOP=10 ;DEFAULT + INH CRY18=11 + MQ SHIFT=12 ;ENABLE MQ*2, MQ SHRT2 + SCM ALT=13 ;ENABLE FE, ARSHIFT + CLR FPD=14 + LOAD PC=15 + XCRY AR0=16 ;CARRY INTO AD IS XOR'D WITH AR00 + GEN CRY18=17 +.IFNOT/XADDR + SEC HOLD=20 ;INHIBIT LOADING VMAX + CALL=21 +.IF/XADDR + STACK UPDATE=20 ;CONTROL CRY18 IF LOCAL STACK +.ENDIF/XADDR + ARL IND=22 ;# SPECIFIES ARL MIX, ENABLES, & CALL + MTR CTL=23 ;# CONTROLS METERS + FLAG CTL=24 ;FUNCTION ENCODED IN # FIELD + SAVE FLAGS=25 ;TELLS PI CYCLE TO HOLD INTRPT + SP MEM CYCLE=26 ;MEM REQUEST IS MODIFIED BY # + AD LONG=27 ;AD BECOMES 72 BIT ALU + +U73/=0,2,73,D ;BITS 72-73 UNUSED + +MARK/=0,1,74,D ;FIELD SERVICE "MARK" BIT + .TOC "CONTROL RAM DEFINITIONS -- MAGIC NUMBER FIELD" + +#/=0,9,83,D ;THE INFAMOUS "MAGIC NUMBERS" + VERS=126 ;MICRO-CODE VERSION NUMBER + +.IF/ITSPAGE + PPRO=40 ;PAGE PROTECTION, READ ONLY + PPRWF=40 ;PAGE PROTECTION, READ/WRITE/FIRST + PPRW=50 ;PAGE PROTECTION, READ/WRITE +.ENDIF/ITSPAGE + + + +.IF/LISP + SEGLOG=11 ;LOG BASE 2 OF WORDS PER STORAGE SEGMENT + SEGLOG-5=4 + 44-SEGLOG=33 + + GCBMRK=400 ;BITS IN AR0-8 FIELD + GCBFOO=340 ; OF A GCST WORD + GCBCDR=20 + GCBCAR=10 +.ENDIF/LISP + +FM#/=0,7,83 ;LOW 7 BITS OF # USED TO ADDRESS FM + +;TABLE OF OPTIONS BITS +; 400 KL-MODE PAGING +; 200 EXTENDED ADDRESSING +; 100 +; 040 LISP INSTRUCTIONS +; 020 ITS-MODE PAGING +; 010 MUSIC MICROCODE +; 004 JPC FEATURE +; 002 IF JPC FEATURE, RING OF 16 JPC'S +; 001 TRACKS FEATURE OR INSTRUCTION STATISTICS + +Q400/=0,1,75 +.IFNOT/KLPAGE + Q=0 +.IF/KLPAGE + Q=1 +.ENDIF/KLPAGE +Q200/=0,1,76 +.IFNOT/XADDR + Q=0 +.IF/XADDR + Q=1 +.ENDIF/XADDR +Q100/=0,1,77 + Q=0 +Q40/=0,1,78 +.IFNOT/LISP + Q=0 +.IF/LISP + Q=1 +.ENDIF/LISP +Q20/=0,1,79 +.IFNOT/ITSPAGE + Q=0 +.IF/ITSPAGE + Q=1 +.ENDIF/ITSPAGE +Q10/=0,1,80 +.IFNOT/MUSIC + Q=0 +.IF/MUSIC + Q=1 +.ENDIF/MUSIC +Q4/=0,1,81 +.IFNOT/JPC + Q=0 +.IF/JPC + Q=1 +.ENDIF/JPC +Q2/=0,1,82 +.IFNOT/JPC.RING + Q=0 +.IF/JPC.RING + Q=1 +.ENDIF/JPC.RING +Q1/=0,1,83 +.IFNOT/INSTR.STAT + Q=0 +.IF/INSTR.STAT + Q=1 +.ENDIF/INSTR.STAT + ;VARIOUS SPECIAL FUNCTIONS ENABLE SPECIAL DECODING OF THE +; "MAGIC #" FIELD, AS FOLLOWS: + +;SPECIAL DATA PATH CONTROLS + +CALL/=0,1,75 ;ENABLED BY ARL IND (CTL2) + CALL=1 +AR0-8/=0,1,76 ;ENABLED BY ARL IND (CTL2) + LOAD=1 +CLR/=0,4,80 ;ENABLED BY ARL IND (CTL2) + MQ=10 + ARX=4 + ARL=2 + ARR=1 + AR=3 + AR+ARX=7 + AR+MQ=13 + ARX+MQ=14 + AR+ARX+MQ=17 + ARL+ARX=6 + ARL+ARX+MQ=16 + ARR+MQ=11 +ARL/=0,3,83 ;ENABLED BY ARL IND (CTL2) + ARL=0 + ARMM=0 ;REQUIRES SPECIAL FUNCTION + CACHE=1 ;ORDINARILY SELECTED BY HWARE + AD=2 + EBUS=3 + SH=4 + AD*2=5 + ADX=6 + AD*.25=7 +AR CTL/=0,3,77 ;ENABLED BY COND/REG CTL (CTL2) + AR0-8 LOAD=4 + AR9-17 LOAD=2 + ARR LOAD=1 + ARL LOAD=6 +EXP TST/=0,1,80 ;ENABLED BY COND/REG CTL (CTL1) + AR_EXP=1 +MQ CTL/=0,2,83 ;ENABLED BY COND/REG CTL (CTL2) +; MQ=0 ;WITH MQ/MQ SEL + MQ*2=1 ; " +; MQ*.5=2 ; " (DROPS BITS 0,6,12,18,24,30) + 0S=3 ; " + SH=0 ;WITH MQ/MQM SEL + MQ*.25=1 ; " + 1S=2 ; " + AD=3 ; " + ;SPECIAL CONTROL OF EBOX FLAGS & FUNCTIONS + +PC FLAGS/=0,9,83 ;ENABLED BY COND/PCF_# (SCD4) + AROV=420 ;SET ARITH OVFLO & TRAP1 + FLOV=620 ;SAME, PLUS FLOATING OVFLO + FPD=100 ;SET FIRST PART DONE + TRAP2=40 ;SET TRAP2 (PDL OVFLO) + TRAP1=20 ;SET TRAP1 (ARITH OVFLO) + TRAP3=60 ;SET TRAP1 & TRAP2 (ONE PROCEED) + FXU=630 ;FLOV + EXP UNDERFLOW + DIV CHK=424 ;NO DIVIDE + AROV + FDV CHK=624 ;FLOATING NO DIVIDE +FLAG CTL/=0,9,83 ;ENABLED BY SPEC/FLAG CTL (SCD5) + RSTR FLAGS=420 ;AS IN JRSTF + JFCL=602 ;FORCE PC 00 = AROV + JFCL+LD=622 ;SECOND PART OF JFCL -- CLEAR TESTED FLAGS + DISMISS=502 ;CLEAR PI CYCLE IF SET (CON5) + ; ELSE DISMISS HIGHEST PI HOLD + HALT=442 ;STOP PROCESSOR IF LEGAL (CON2) + SET FLAGS=20 ;AS IN MUUO + PORTAL=412 ;CLEAR PUBLIC IF PRIVATE INSTR +SPEC INSTR/=0,9,83 ;ENABLED BY COND/SPEC INSTR + SET PI CYCLE=714; (CON5) + KERNEL CYCLE=200;MAKE IO LEGAL, EXEC ADDR SPACE (CON4) + INH PC+1=100 ;TO MAKE JSR WORK IN TRAP, INTRPT (CON4) + SXCT=40 ;START SECTION XCT (MCL4) + PXCT=20 ;START PREV CONTXT XCT (MCL4) + INTRPT INH=10 ;INHIBIT INTERRUPTS (CON4) + INSTR ABORT=4 ; (CON2) + HALTED=302 ;TELL CONSOLE WE'RE HALTED (CON4) + CONS XCT=310 ;FLAGS FOR INSTR XCT'D FROM CONSOLE +; CONT=10 ;INHIBIT INTERRUPTS WHILE SINGLE STEPPING + CONT=0 ;DON'T, CAUSES HANG AT WGRANT. WILL THIS WIN? +FETCH/=0,9,83 ;ENABLED BY MEM/FETCH + UNCOND=400 + ;LOW 2 BITS DECODED ON (IR3) + COMP=201,2 ;DEPENDING ON AD AND DRAM B + SKIP=202,2 + TEST=203,1 + JUMP=502,2 ;AS IN JUMPX, ON AD AND DRAM B + JFCL=503,1 ;JUMP ON TEST CONDITION + ;SPECIAL CONTROLS & FUNCTIONS FOR MBOX + +SP MEM/=0,9,83 ;ENABLED BY SPEC/SP MEM CYCLE + FETCH=400 ;LOAD IR WHEN DATA ARRIVES (MCL5) + USER=200 ;FORCE USER OR UPT (MCL2) + EXEC=100 ;FORCE EXEC OR EPT (MCL3) + SEC 0=40 ;CLEAR VMAX (MCL4) + UPT EN=20 ;UPT IF USER EN (MCL3) + EPT EN=10 ;EPT IF NOT USER EN (MCL3) + CACHE INH=2 ; (MCL6) + UNPAGED=101 ; (MCL6) + EPT=111 + EPT FETCH=511 + UPT=221 + UPT FETCH=621 + PT=31 + PT FETCH=431 +MREG FNC/=0,9,83 ;ENABLED BY MEM/REG FUNC (APR6) + SBUS DIAG=407 ;PERFORM SBUS DIAGNOSTIC CYCLE + READ UBR=502 ;ASK MBOX TO LOAD UBR INTO EBUS REG + READ EBR=503 ;PUT EBR INTO EBUS REG + READ ERA=504 + WR REFILL RAM=505 ;DISGUISED AS A "READ REG" FUNCTION + LOAD CCA=601 ;START A SWEEP + LOAD UBR=602 ;SETUP UBR FROM VMA + LOAD EBR=603 ;SETUP EBR FROM VMA + MAP=140 ;GET PHYS ADDR CORRESPONDING TO VMA (MCL6) +MBOX CTL/=0,9,83 ;ENABLED BY COND/MBOX CTL (APR5) + SET PAGE FAIL=200 + SET IO PF ERR=100 + PT DIR WR=20,1 ;WRITE PAGE TABLE DIRECTORY + PT WR=10,1 ;WRITE PAGE TABLE ENTRY SELECTED BY VMA + NORMAL=0 ;RESET PT WR SELECTION + PT DIR CLR=1 ;SELECT FOR CLEARING PT DIR (PAG3) + CLR PT LINE=21 ;CLEAR VALID FOR 8 ENTRIES +MTR CTL/=0,3,83 ;FUNCTION DECODING FOR METERS (MTR3) + CLR TIME=0 ; USUALLY USED WITH DIAG FUNC + CLR PERF=1 + CLR E CNT=2 + CLR M CNT=3 + LD PA LH=4 + LD PA RH=5 + CONO MTR=6 + CONO TIM=7 + ;I/O FUNCTIONS + +EBUS CTL/=0,9,83 ;ENABLED BY COND/EBUS CTL (APR3) + GRAB EEBUS=400 ;"EBUS RETURN" TAKES ECL EBUS FOR EBOX + REQ EBUS=200 + REL EBUS=100 ; (CON3) + EBUS DEMAND=60 ;ASSERT DEMAND, KEEP CS, FUNC + EBUS NODEMAND=20;DROP DEMAND, KEEP CS, FUNC +; CTL_IR=10 ;SELECT F01 & F02 FROM IR +; DISABLE CS=4 ;TURN OFF CONTROLLER SELECT +; DATAIO=2 ;0 FOR CONI/O +; INPUT=1 ;0 FOR OUTPUT + IO INIT=30 ;ENABLE IR3-9 TO EBUS CONTROLLER SELECT, + ; IR10-12 (DECODED) TO FUNCTION + ; AND AR ONTO EBUS IF FUNCTION IS OUTPUT + DATAO=26 ;0'S TO CS, DATAO TO FCN, AND AR TO EBUS + DATAI=27 ;0'S TO CS, DATAI TO FCN + REL EEBUS=0 ;LEGGO +DIAG FUNC/=0,9,83 ;ENABLED BY COND/DIAG FUNC (CTL3) + .5 USEC=400,3 ;STRETCH CLOCK TO LET EBUS SETTLE (CON?) + LD PA LEFT=404,3 ;LH PERF ANAL CONTROLS FROM RH (MTR) + LD PA RIGHT=405,3 ;RH PA CONTROLS FROM RH (MTR) + CONO MTR=406,3 ;ACCOUNTING CONTROLS (MTR) + CONO TIM=407,3 ;INTERVAL TIMER CONTROLS (MTR) + CONO APR=414,3 ; (CON3) + CONO PI=415,3 ; (CON3) + CONO PAG=416,3 ;CACHE & PAGING CTL (CON3) + DATAO APR=417,3 ;ADDRESS BREAK (CON3) + DATAO PAG=620,3 ;AC BLOCKS & PREV CONTXT (CON3) + LD AC BLKS=425,3 ;FORCE LOADING AC BLOCKS + LD PCS+CWSX=426,3 ;FORCE LOADING PREV CONTXT SEC, CWSX + CONI PI(R)=500,3 ;PI HOLD & ACTIVE TO LH (PI) + CONI PI(L)=501,3 ;PI GEN TO LH (PI) + CONI APR(R)=510,3 ;APR INTERRUPT & PIA TO LH (APR6) + RD TIME=510,3 ;TIME BASE TO RH (MTR5) + DATAI PAG(L)=511,3 ;AC BLOCKS, PREV CONTXT TO LH (APR6) + RD PERF CNT=511,3 ;PERFORMANCE COUNT TO RH (MTR5) + CONI APR(L)=512,3 ;APR INTERRUPT ENABLES TO LH (APR6) + RD EBOX CNT=512,3 ;EBOX COUNT TO RH (MTR5) + DATAI APR=513,3 ;ADDR BREAK CONDITIONS TO LH (APR6) + RD CACHE CNT=513,3 ;CACHE COUNT TO RH (MTR5) + RD INTRVL=514,3 ;INTERVAL TIMER TO RH (MTR5) + RD PERIOD=515,3 ;PERIOD REGISTER TO RH (MTR5) + CONI MTR=516,3 ;CONTROLS & PIA TO RH (MTR5) + RD MTR REQ=517,3 ;ENCODED UPDATE REQUEST TO 20-22 (MTR5) + CONI PI(PAR)=530,3 ;WRITE EVEN PARITY ENABLES TO RH (CON1) + CONI PAG=531,3 ;CACHE & TRAP CTL TO RH (CON1) + RD EBUS REG=567,3 ;EBUS REGISTER IN MBOX (MBZ1 & MBC1) + +PARITY/=0,0,0,P ;USE ANY AVAILABLE FIELD FOR PARITY + .TOC "DISPATCH RAM DEFINITIONS" +;FIELDS ARE ARRANGED FOR EASY READING, NOT COMPACTNESS + + .DCODE +A/=0,3,2 ;OPERAND FETCH MODE + IMMED=0 ;IMMEDIATE + IMMED-PF=1 ;IMMEDIATE, START PREFETCH + WR-TST=3 ;TEST WRITABILITY + READ=4 ;READ ONLY + READ-PF=5 ;READ, THEN PREFETCH + RD-WR=6 ;READ WRITE (SEPARATE CYCLES) + RD-P-WR=7 ;READ PAUSE WRITE + +B/=0,3,5 ;STORE RESULTS AT-- + DBL AC=1 ;DOUBLE RESULT TO AC & AC+1 + DBL BOTH=2 ;MULB, DIVB, ETC + SELF=3 ;SELF MODE INSTRUCTIONS + AC=5 ;SINGLE RESULT TO AC, PREFETCH IN PROG + MEM=6 ;RESULT TO MEMORY + BOTH=7 ;SINGLE RESULT TO MEMORY AND AC + + SJC-=3 ;SKIP JUMP COMPARE CONTROLS + SJCL=2 + SJCE=1 + SJCLE=0 + SJCA=7 + SJCGE=6 + SJCN=5 + SJCG=4 +B0/=0,1,3 ;INVERTS VARIOUS TEST, SKIP, AND JUMP CONTROLS + CRY0(0)=0 ;TEST TST CAUSES PC SKIP IF CRY0=0 + CRY0(1)=1 ; SAME IF CRY0=1 +B1-2/=0,2,5 ;FLOATING RESULT STORE MODE + AC=1 ;RESULT TO AC + MEM=2 ;RESULT JUST TO MEM + BOTH=3 ;RESULT TO BOTH + +PARITY/=0,1,11,P + +J/=0,10,23 ;EXECUTOR (40&20-BITS ALWAYS 0) + .UCODE diff --git a/src/ucode/eis.6 b/src/ucode/eis.6 new file mode 100755 index 00000000..c8271ee3 --- /dev/null +++ b/src/ucode/eis.6 @@ -0,0 +1,642 @@ +.IF/EIS +KO "EXTE INSTUaԓS"EODING" + +;GET HERE WITH E0 IN BR, (E0) IN AR +; (S THEEATION WORD, AND HAS THE NORMAL -10 3ԥUCTION +; FORMAABITS 0-8 ARE OPCODE, 9-12 IGNOQb,A13 @, 14-17 XR,񢝉ND 18-35 Y. THE AC USED sŧ FROM THE *ED INSéION.NC*ԋXSckY +;E"Ή:FE_#pi0[ [20,SKP SCAD0, ;r"× LEGAL OPERATION +; ARX_AR,AR_BRX ;OPR'RX, GA FROMXOX EXT1: AR_BR,J/UUO ;OPCODE > 17 + AR0-8_FE+#,#/20 ;PLUG OPR INEgDAAC + g R,LOA$YAR_ARX,ARL_0.M, + EA MOD DISP +=00 +EXTNc_AR,AR_BR,Kة5 ;SAVE E1, RE1,O SAVE E0 + ARLMYAR_ARX+XR,J/EXTCE EN AR NDRCT,SKP INTRPT,J/EXT3 + GEN ARX+XR,A INDRCT, + SKP INTRPT,J/EXT3 +=0 +EXT3: AR_MEM,ARX_flTi_MEM,TAKE INTRPEET4: ARL_0.M,EA MOD D4,/EXT2 + +EXT5: /,VMA_AR+1,IR DItJ_2000 ;ENTER EXTENDED INSTH$ADLER + +;THE EXgDD INSTRUCT3 I "HIDg"AUNDER THE LUUO'S BY THIS +; USE OF Ri 4,/2000" TO iЃTCH T*HM. TPLUO'S $Ñ +; H5HE SAME OPCODESiXTENDED OPERATIONS AQPArc΋D UNIQUE +; CRA&OATIONS IN "3A,0A1a17. WHEN WE SPECIFY J/2000, +; THEA ADDRESS B͋ha*OAlY WHICH ACCESSES CRAM LOCATIONS +; 2  0c!EAUSE ADDRESS BITS 01 AND 02 ARE IGNAWHEN BIT 00 +; 4TUE (CRA, CRM). + +2005: AR_AC3,J/CMĉ;HIDDBHIND aͧ +200΄ÙR AR,ARX_1S,SC_kc5.,J/EDIT ;HIDDBgDAL-EDIT +.IF/DECIMAL +2010: AR_AC0 COMP,J/DBIN ;HIDDEN BEHIND L-DBIN +2011: AR_AC1,ARL/AD,SC_1,ARX+MQ_0.M, + BYTE DISP,J/BDEC ;HIDDEN BEHIND L-BDEC +.ENDIF/DECIMAL +2012: AR_AC3,LOAD AR,J/MVST ;HIDDEN BEHIND L-MVS + .TOC "EIS -- STRING MOVE" +; HERE WITH AC3 (DEST LEN) IN AR +;SLEN IS THE COMPLEMENT OF THE SHORTER STRING LENGTH +;DLEN IS - + +MVST: BR/AR,AR_MEM, ;HOLD AC3, WAIT FOR FILLER + FE_AR0-8,SKP SCAD NE ;CHECK FOR FLAGS IN DEST LEN +=0 ARX_AC0,J/MVST1 ;GET SRC LEN, FLAGS + AR_E0,J/UUO ;NO FLAGS ALLOWED IN DST LEN +MVST1: FILL_AR,AR_ARX ;SAVE FILL CHAR + FE_AR0-8,AR0-8_#,#/0 ;SEPARATE FLAGS OFF + ARX_AR,AR_AR-BR,SKP AD0 ;COMPUTE SRC-DST LEN +=0 DLEN_AR,AR_BR COMP,J/MVST2 ;SRC LONGER + DLEN_AR,AR_ARX COMP ;DST LONGER +MVST2: SLEN_AR,ARX_AR,MQ_AR,AR_0S ;-SHORT LEN -1 TO MQ + AR0-8_FE,BRX/ARX ; AND BRX + SFLGS_AR,B DISP +=100 CLR AR,ARX_1S,SC_#,#/15.,J/MOVS2;TRANSLATE, BUILD MASK + AR_E1,J/MVSO1 ;OFFSET, SIGN EXTEND E1 + ARX_BRX+1,AR/ADX,SR_SRC,J/MOVST1 ;LEFT JUSTIFY + AR_DLEN,SKP AD0,J/MOVRJ ;RIGHT JUSTIFY + +MVSO1: ARX_DSTP,SKP AR18,ARL_0.M ;CHECK SIGN FOR EXTENDING +=0 +MVSO2: E1_AR,AR_ARX,J/MVSO3 ;SAVE AGAIN, GET POINTER + ARL_1S,J/MVSO2 ;NEG, MAKE MINUS +MVSO3: SC_S,CLR ARX,AR_1S ;PREPARE TO BUILD MASK +MOVS2: AR_SHIFT,SR_SRC + MSK_AR +=000 +MOVELP: AR_SLEN+1,CALL,J/SRCMOD ;PICK UP SOURCE BYTE + AR_DLEN,J/MOVSTX ;(1) LENGTH EXHAUSTED +=100 +MOVPUT: SR_SRC+DST,CALL,J/PUTDST ;(4) NORMAL, STORE DST BYTE + I FETCH,AR_DLEN,J/MVABT ;(5) ABORT +=110 SR_SRC,J/MOVELP ;(6) DPB DONE += +;HERE TO ABORT A STRING MOVE DUE TO TRANSLATE OR OFFSET FAILURE + +MVABT: BR/AR,AR_-SLEN,SKP AR0 ;WHICH STRING LONGER? +=0 +MVABT1: AC3_AR,FETCH WAIT,J/MVABT2 ;PUT AWAY DEST LEN + AR_AR-BR,J/MVABT1 ;DEST LEN WAS GREATER + +MVABT2: AR_SLEN COMP,SKP BR0 ;GET UNDECREMENTED SLEN +=0 AR_AR+BR ;SRC LONGER BY (DLEN) +MVEND: AR_AR*SFLGS,AD/OR,SR_0,J/STAC ;PUT BACK REMAINING LENGTH + ;HERE TO BEGIN RIGHT-JUSTIFIED MOVE + +=00 +MOVRJ: ARX_AR,AR_SRCP,SR_SRC,J/MVSKP ;SRC LONGER, SKIP OVER SOME + SR_DSTF,CALL,J/MOVF1 ;DST LONGER, FILL IT +=11 ARX_BRX+1,AR/ADX,SR_SRC,J/MOVST1 ;DONE FILLING + +=0 +MVSKP: ARX_ARX-1 (AD),FE_#,#/36., + SIGNS DISP,SKP INTRPT,J/MVSK1 + P_FE-S,AR_AR+1,J/MVSKP +=110 +MVSK1: P_P-S,SKP SCAD0,J/MVSKP ;BUMP POINTER + SRCP_AR,GEN ARX,SIGNS DISP,AR_0.M +=110 BRX/ARX,AR_SLEN COMP,ARX/AD,J/MVSK3 ;INTERRUPTED + DLEN_AR,J/MVSK4 ;DONE FILLING + +MVSK3: AC3_AR,AR_ARX*BRX,AD/A+B+1 ;DEST HAS SHORT LEN + SR_0,J/STRPF2 ;FIX UP AC0, SERVE INTRPT + +;HERE FOR NO-MODIFICATION STRING MOVES + +=000 +MOVST1: SLEN_AR,BRX/ARX, ;PUT UPDATED LEN AWAY + AR+ARX+MQ_0.M,CALL.M, + SIGNS DISP,J/GSRC +MOVSTX: SKP AR0,ARX_AR,AR_0S,J/MOVST2 ;SHORT LEN EXHAUSTED +=010 SR_SRC+DST,CALL,J/PUTDST +=110 +MVSK4: ARX_BRX+1,AR/ADX,SR_SRC,J/MOVST1 += +=00 +MOVST2: TEST ARX,TEST FETCH, ;SKIP IF BOTH LENGTHS =0 + AC3_AR,AR_ARX,J/MVEND ;CLEAR DEST LEN, REBUILD SRC + SR_DST,CALL,J/MOVF1 ;SOURCE GONE, FILL OUT DST +=11 AR_SFLGS,VMA_PC+1,J/SFET1 ;DONE FILLING + +;NOTE -- IT AIN'T AS EASY AS IT LOOKS TO BUM A CYCLE OUT OF THIS +; ROUTINE, BECAUSE AN INTERRUPT, IF ANY, HAS TO BE TAKEN AFTER THE +; POINTER UPDATE AND BEFORE THE LENGTH UPDATE. GOOD HUNTING! +=01* +MOVF1: AR_FILL,CALL,J/PUTDST + AR_DLEN+1,SKP INTRPT,J/MOVF2 +=0 +MOVF2: DLEN_AR,SIGNS DISP,J/MOVF3 ;DONE? + SR DISP,J/CLEAN ;BREAK OUT FOR INTERRUPT +=011 +MOVF3: RETURN2 ;YES, DONE + J/MOVF1 ;NO, DO ANOTHER + .TOC "EIS -- STRING COMPARE" + +;HERE WITH AC3 (DEST LENGTH) IN AR + +CMPS: BR/AR,ARX_AR,FE_AR0-8,AR_AC0 ;DEST LEN TO BR, GET SRC LEN + FE_FE OR AR0-8, ;GATHER HIGH BITS OF LEN'S + SKP AR GT BR ;WHICH STRING LONGER? +=0 +CMPS1: LOAD AR,AR_ARX-1,ARX_AR-1, ;SRC SHORTER + GEN FE,SKP SCAD NE,J/CMPS2 ;CHECK LEN'S PURE + VMA_VMA+1,J/CMPS1 ;SRC LONGER, GET DST FILLER +=0 +CMPS2: AR_MEM,BR/AR,BRX/ARX,J/CMPS4 ;DECREMENTED LEN'S TO BR'S + MB WAIT,AR_E0,J/UUO ;OOPS, ILLEGAL BITS IN LEN'S + +;HERE IS THE COMPARE LOOP. +; MQ CONTAINS THE FILL CHARACTER FOR THE SHORTER STRING, +; BR CONTAINS THE REMAINING DESTINATION LENGTH, +; BRX CONTAINS THE REMAINING SOURCE LENGTH +=0 +CMPS3: ARX0_MQ35,J/CMPSX ;WE GOT INEQUALITY. GET SIGN +CMPS4: MQ_AR,ARX_AR,FE_#,#/36., ;FILL TO MQ & ARX + AR_BR,SKP ARX0 ;MORE CHARS IN SRC STRING? +=000 AR_SRCP,ARX_SRCP, ;READY WITH SRC POINTER + SR_ED(S),CALL,J/GSRC1 ;GO GET SRC BYTE + AR_ARX,ARX_0S,SR_0,SIGNS DISP ;SRC DONE. TEST DEST LEN +=010 T0_AR,AR_MQ,SIGNS DISP,J/CMPS5 ;SRC (OR SRC FILL) TO T0, +=110 ;TEST FOR END OF DEST STRING +CMPSX: GEN ARX,CMS FETCH,J/NOP ;QUIT WITH COMPARE COND IN ARX += +;HERE TO GET DESTINATION BYTE. SRC IS IN T0, FILL CHAR IN AR +;HERE WITH SIGNS DISP, TO AVOID CALL ON CMPDST IF DST LEN EXHAUSTED + +=101 +CMPS5: SR_ED(+D),CALL,J/CMPDST ;GO FOR DESTINATION BYTE + AR_AR*T0,AD/XOR, ;AR ZERO IF EQUAL + ARX/MQ,MQ_MQ*2 ;FILL TO ARX, CRY TO MQ35 + BR/AR,BRX/ARX, ;EQUALITY TO BR, FILL TO BRX + AR_BR,ARX_BRX,SKP BR0 ;LENGTHS TO AR, ARX +=0 AC3_AR,ARX_AR,AR_ARX (AD), ;UPDATE DEST LEN IN AC3 + SIGNS DISP,J/CMPS6 ;TEST SRC LEN + ARX_AR,AR_ARX (AD) ;DEST LEN EXHAUSTED +=110 +CMPS6: AC0_AR,AR_ARX-1,ARX_AR-1,J/CMPS7 ;UPDATE SRC LEN IN AC0 + AR_ARX-1,ARX_AR-1 ;SRC EXHAUSTED PREVIOUSLY + +CMPS7: BR/AR,BRX/ARX, ;LENGTHS TO BR'S + SKP BR EQ,AR/ADX,J/CMPS3 ;CHECK FOR EQUALITY + +=0 +CMPDST: AR_DSTP,ARX_DSTP,FE_#,#/36., ;GET DEST BYTE FOR COMPARE + CALL,J/IDST ;UPDATE DEST POINTER + SC_FE+SC,SKP INTRPT,J/LDB1 ;GET DEST BYTE + .TOC "EIS -- DECIMAL TO BINARY CONVERSION" +; HERE WITH AC0 (SRC LEN) IN AR COMPLEMENTED +; IN THE LOOP, AC3 CONTAINS 10 (DECIMAL), BR'BRX HAS ACCUMULATED BINARY + +.IF/DECIMAL + +DBIN: BR/AR,FE_AR0-8 COMP,AR0-8_#,#/-1 ;FORCE OUT FLAGS + SLEN_AR,AR_0S,SIGNS DISP +=101 AR0-8_FE,MQ_0.S,ARX_AC4,J/DBS1 ;BUILD SFLGS + B DISP ;OFFSET OR TRANSLATE? +=110 AR0-8_FE,J/DBST ;TRANSLATE, LET S FLAG SET LATER + AR0-8_FE OR #,#/400 ;OFFSET, SET S FLAG +DBST: SFLGS_AR,AR_0S,ARX_0S,J/DBS2 ;CLEAR BINARY + +DBS1: SFLGS_AR,ARX_ARX*2 ;HERE WHEN SIG ALREADY ON + AR_AC3 ;ACCUMULATED BINARY IN AR +DBS2: BR_AR LONG,AR_1,CLR ARX + AR_AR*10,B DISP,SC_#,#/4 ;GET CONSTANT 10 FOR COMPARE +=110 AC3_AR,AR_ARX,ARX_1S,J/DBS3 ;PREPARE TO BUILD MASK + AC3_AR ;OFFSET + AR_E1 ;GET OFFSET + ARL_1S.M,SKP AR18 ;SIGN EXTEND IT +=0 ARL_0S ;OOPS, TWAS POS + E1_AR,AR_1S ;NOW READY TO BUILD MASK +DBS3: AR_SHIFT,SR_DB + MSK_AR,AR_BR LONG ;SAVE MASK, GET INITIAL INPUT + +=0*0 +DBINLP: BR_AR LONG,AR_SLEN+1, ;BINARY BACK TO BR, COUNT LENGTH + CALL,J/SRCMOD ;PICK UP A DIGIT + SKP AR2,VMA_PC+1,J/DBXIT ;(1) DONE, TEST M FLAG + ARX_AR,AR+MQ_0.M,GEN AR-AC3, ;(4) NORMAL, ADD IN DIGIT + SKP CRY0,J/DBIN2 ;TEST FOR DIGIT >9 + AR_SLEN COMP,J/DBABT ;(5) ABORT + +;HERE TO ADD IN A DIGIT + +=0 +DBIN2: BR_AR LONG,AR_BR LONG,J/DBIN3 ;DIGIT TO BR LONG, BINARY TO AR LONG + AR_SLEN COMP,J/DBABT ;DIGIT >9, ABORT + +DBIN3: AR_AR*5 LONG ;ALREADY HAVE BINARY *2 + AR_2(AR+BR) LONG,J/DBINLP ;ADD IN DIGIT, SHIFT LEFT + +;HERE ON ABORT + +DBABT: AR_AR*SFLGS,AD/OR ;COMBINE FLAGS WITH +LEN REMAINING + AC0_AR,AR_BR LONG,SC_#,#/35., ;PUT BACK UNUSED LENGTH + VMA_PC+1,J/STOR34 ;END WITH NO SKIP + +;HERE AT END + +=0 +DBXIT: AR_BR LONG,VMA_VMA+1, ; M FLAG=0 + SC_#,#/35.,J/STOR34 ;GO FOR NEXT INSTR + AR_-BR LONG,VMA_VMA+1, ;NEGATE + SC_#,#/35. +STOR34: AC3_AR,AR_SIGN,FETCH ;STORE HIGH PART + AR_SHIFT,SR_0 ;GET LOW READY +STAC4: AC4_AR,FINISH + .TOC "EIS -- BINARY TO DECIMAL CONVERSION" +; AC0,AC1 = BINARY INTEGER INPUT +; AC3 = FLAGS, MAX LENGTH OF DECIMAL STRING +; AC4 = DESTINATION STRING POINTER +; TEMPS ARE USED AS FOLLOWS: +; SLEN= # OF SIGNIFICANT DIGITS +; T1,2= 10.**(SLEN) THE LOWEST POWER OF TEN LARGER THAN BINARY + +;FPD IS SET IF THE INSTRUCTION WAS INTERRUPTED AFTER +; CONVERSION OF THE BINARY INTEGER TO FRACTION FORM. +; (AND THUS BY IMPLICATION, AFTER STORING FILLERS) + +=011 +BDEC: ARX_SHIFT,AR_AC0,SKP AD0, ;BINARY INTEGER NOW IN AR LONG + SC_#,#/20,J/BD1 ;IS IT NEGATIVE? + ARX_AR,AR_E1,B DISP ;CONT FROM INTRPT OR PGF +=0 +BDDR1: AR_AC3,SR_BDT,J/BDDR3 ;RESUME WITH FRACTION IN AR LONG + SKP AR18,ARL_0.M ;OFFSET MODE. EXTEND E1 +=0 +BDDR2: E1_AR,J/BDDR1 ;GET REST OF FRACTION + ARL_1S,J/BDDR2 ;E1 NEGATIVE +BDDR3: BR/AR,CLR EXP, ;SEPARATE FLAGS & LENGTH + BRX/ARX,ARX_AC0 ;LOW FRAC TO BRX, HI TO ARX + AR_AR*BR,AD/ANDCA,BR/AR ;JUST FLAGS TO AR, JUST LEN TO BR + AC3_AR,AR_ARX ;GET HI FRAC TO AR + BR/AR,VMA_PC+1, ;FRAC TO BR LONG, GET VMA READY + AR_-BR,SKP CRY0,J/BDDR4 ;CHECK FOR MORE TO GO + +=0 +BD1: SKP AR NE,AD LONG,J/BD2 ;TEST FOR ZERO LONG + AR_-AR LONG,SC_#,#/30,J/BD3 ;MAKE POSITIVE, SET N&M FLAGS +=00 +BD2: BR_AR LONG,AR_1 LONG, ;BINARY RIGHT-ALIGNED IN BR, + SC_#,FE_#,#/20.,J/BD4 ;LOOK FOR LARGER POWER OF TEN +BD3: BR_AR LONG,AR_AC3, ;SAVE POS BINARY, GET AC FLAGS + CALL,J/SETFLG ; SET FLAGS AS NEEDED +=11 AC3_AR,AR_BR*.5 LONG,J/BD2 ;SAVE NEW FLAGS, SHIFT BINARY RIGHT + +;HERE TO FIND THE SMALLEST POWER OF TEN LARGER THAN THE BINARY INTEGER. +;BINARY IS IN BR LONG, AND POSITIVE UNLESS IT WAS 1B0. IN THIS CASE THE +;COMPARISON WILL NEVER FIND A LARGER POWER OF TEN, BUT THE COUNT IN FE +;WILL RUN OUT, AND WE WILL CORRECTLY COMPUTE 22 DIGITS REQUIRED. + +=010 ;IGNORE BR SIGN +BD4: AR_AR*10 LONG,FE_FE-1,J/BD6 ;THIS POWER IS TOO SMALL + SC_FE-SC-1,T1_AR,AR_ARX,J/BD7 ;THIS POWER IS BIG ENOUGH + FE_FE-1 ;10.**21 IS TOO SMALL, USE 22 + SC_FE-SC-1,T1_AR,AR_ARX,J/BD7 ;10.**21 IS BIG ENOUGH + +BD6: GEN AR-BR-1,DISP/DIV,J/BD4 ;COMPARE BINARY TO 10**N + ;HERE HAVING FOUND THE NUMBER OF DIGITS REQUIRED TO REPRESENT THE +; GIVEN INTEGER. THE ONE'S COMPLEMENT OF THE NUMBER OF DIGITS IS NOW +; IN SC, AND T1/T2 IS GETTING A POWER OF TEN LARGER THAN THE INPUT. + +=0* +BD7: T2_AR,AR_1S,CALL,J/GETSC ;SAVE (10**N), GET -# OF DIGITS + SLEN_AR,ARX_AR*4 COMP ;-# OF SIGNIFICANT DIGITS-1 + AR_AC3 ;GET FLAGS, LENGTH + FE_AR0-8,AR0-8_#,#/0 ;LEN IN AR, FLAGS IN FE + AR_ARX*.25-AR-1,SKP CRY0, ;-# OF FILL CHARS -1 + SC_FE-#,#/400 ;SC0 SET IF S FLAG =0 +=0 ARX_AR+1,AR_0.M,J/BD8 ;ENOUGH SPACE. -FILL CNT TO ARX + I FETCH,J/NOP ;OVERFLOW +BD8: AR0-8_FE.M,SKP SC0, ;FLAGS TO AR. S FLAG =0? + GEN ARX COMP,SIGNS DISP ; OR EXACT LENGTH? +=110 T0_AR,LOAD AR,J/BDF1 ;FLAGS TO T0, GET FILLER +BD9: AC3_AR,J/BDDV1 ;NO FILL. FLAGS TO AC3 + +=00 +BDF1: AR_MEM,SR_BDF,CALL,J/RET1 ;GET FILLER, GO WAIT FOR PARITY + FILL_AR,AR_ARX,CALL,J/MOVF2 ;FILL AS REQUIRED +=11 AR_T0,J/BD9 ;GET FLAGS BACK + ;SETUP FOR LONG DIVISION OF BINARY BY 10**N +;BR STILL HAS BINARY RIGHT ALIGNED (IE, LOW SIGN SQUEEZED OUT BY +; SHIFTING HIGH WORD RIGHT). BR IS POSITIVE UNLESS INPUT INTEGER WAS +; 1B0, IN WHICH CASE BR IS -1B1. T1,T2 HAS LARGER POWER OF TEN, UNLESS +; BINARY EXCEEDS 10**21, IN WHICH CASE T1,T2 CONTAINS 10**21. SINCE +; BINARY CANNOT BE AS LARGE AS 2 * 10**21, THE FIRST DIVIDE STEP +; IS GUARANTEED TO GENERATE A 1 IN THIS CASE ONLY, AND TO REDUCE THE +; BINARY TO LESS THAN 10**21. + +BDDV1: ARX_T2,CLR AR ;FILL DONE. GET 10**N +=110 AR_T1,MQ_AR, ;D'SOR SET IN AR, MQ CLR + SKP BR0,CALL,J/BDDV2 ; CHK D'END SIGN + ARX_AR,AR_AC0,SET FPD,B DISP ;DONE, GET FULL QUO IN AR LONG +=0 AR_AR+1 LONG,SR_BDT,J/BDD1 ;PREVENT 9'S DISEASE + BR_AR LONG,AR_E1 ;OFFSET MODE, MUST SIGN EXT E1 + ARL_0.M,SKP AR18 +=0 +BDE2: E1_AR,AR_BR+1 LONG,J/BDD1 ;UPDATE E1 + ARL_1S,J/BDE2 ;MAKE FULL E1 NEG + +=000 +BDDV2: AR_BR LONG,BR_AR LONG, ;BEGIN LONG DIVISION + SC_#,FE_#,#/34., ;STEP COUNTS FOR BOTH PARTS + CALL,J/DDVSUB + AR_-BR,ARX/ADX,BR_AR LONG, ;HERE IF BINARY WAS 1B0 + SC_#,FE_#,#/34., ; IT'S NOW 1B1 + CALL,J/DDVSUB +=011 AC0_AR,AR_MQ,ARL/AD,MQ_0.M, ;HALF DONE WITH DIVISION + FE_SC,J/DDVLP ;RESUME WITH ADD STEP +=101 AC0_AR,AR_MQ,ARL/AD,MQ_0.M, + FE_SC,J/DDVSUB ;RESUME WITH SUBTRACT STEP += + ;HERE WITH QUOTIENT OF /<10**N> IN AR LONG, WITH THE +; BINARY POINT BETWEEN BITS 0 AND 1 OF AR. THUS, BIT 0 WILL BE SET +; IFF THE INPUT INTEGER WAS GREATER THAN OR EQUAL TO 10**21. +; SINCE THIS IS A TRUNCATED FRACTION, IT IS NOT GREATER THAN THE TRUE +; QUOTIENT, AND THE ERROR IS LESS THAN 2**-71. WE ADD 2**-71, TO +; GUARANTEE THAT OUR FRACTION IS GREATER THAN THE TRUE QUOTIENT, +; WITH AN ERROR NO GREATER THAN 2**-71. WE WILL THEN MULTIPLY THIS +; FRACTION BY 10 N TIMES, REMOVING THE INTEGER PART AT EACH STEP +; TO EXTRACT THE N DIGITS. SINCE N IS AT MOST 21, THIS IS A MULTIPLI- +; CATION BY AT MOST 10**21, SO THE ERROR IS AT MOST (2**-71)*(10**21). +; SINCE THIS IS LESS THAN ONE, THE ERROR DOES NOT INTRUDE INTO THE +; OUTPUT DIGIT STRING. + +;HERE IS LOOP TO EXTRACT DIGITS FROM FRACTION IN AC0,AC1 + +BDD1: BR_AR LONG,VMA_PC+1, ;START NEXT LOOP ITERATION + AR_SLEN+1,SKP CRY0 ;ANY MORE DIGITS? +=0 ;HERE TO RESUME AFTER INTERRUPT +BDDR4: SLEN_AR,MQ_AR,SC_1, ;YES, SAVE LENGTH REMAINING + AR_BR LONG, ; AND GET FRACTION + SIGNS DISP,J/BDD2 ;CHECK FOR 1ST DIGIT OF 10**21 + AR_0S,ARX_0S,CLR FPD, ;NO, DONE. CLEAR AC0 & AC1 + VMA_VMA+1 + AC0_AR,FETCH,J/STRAC1 ;MOVE FETCH WHEN TIMING FIXED +=101 ;LOOK AT BR0 ONLY +BDD2: AR_AR*1.25 LONG,SC_#,#/4 ;NEXT DIGIT TO AR0-3 + ARX_AR,AR_0S,SKP INTRPT ;READY TO SHIFT IN DIGIT +=0 AR_SHIFT,B DISP,J/BDD3 ;STORE IT + AR_BR LONG,SR_0,J/B2DPF ;UPDATE REGS & QUIT + +;HERE TO STORE DIGIT IN AR FOR BDEC +=0 +BDD3: VMA_AR+E1,LOAD AR,J/BDD4 ;TRANSLATE: GET TABLE ENTRY + AR_AR+E1,J/BDD7 ;OFFSET AR AND STORE IT + +BDD4: SKP MQ EQ -1,TIME/3T,ARX_0.M ;LAST DIGIT? +=0 +BDD5: AR_MEM,J/BDD6 ;NO, STORE RH (POS DIGIT) + ARX_AC3,J/BDD5 ;YES, LOOK AT M FLAG +BDD6: SKP ARX2,ARX_AR SWAP,ARL_0.M +=100 +BDD7: SR_BDD,CALL,J/PUTDST + AR_ARX,ARL_0.M,J/BDD7 ;M SET ON LAST DIGIT, USE LH + + AR_BR LONG,SR_BDT, ;GET FRACTION BACK + SIGNS DISP ;CHECK BR0 FOR INTEGER PART += +=101 AR_AR*10 LONG ;DISCARD PREVIOUS DIGIT + P_P AND #,#/37,J/BDD1 ;CLEAR AR0, GO FOR NEXT + +.ENDIF/DECIMAL + .TOC "EIS -- SRCMOD SUBROUTINE TO GET MODIFIED SOURCE BYTE" + +;SLEN = COMPLEMENT OF LENGTH +;MSK = MASK +;E1 = EFFECTIVE ADDRESS OF OPERATION WORD (SIGN EXTENDED IF OFFSET) + +;CALL WITH: AR_SLEN+1,CALL,J/SRCMOD +;RETURNS: 1 LENGTH EXHAUSTED: FLAGS IN AR +; 2 (EDIT ONLY) NO SIGNIFICANCE: FLAGS IN FE +; 3 (EDIT ONLY) SIGNIFICANCE START: BYTE IN AR, FLAGS IN FE +; 4 NORMAL: BYTE IN AR +; 5 ABORT: OUT OF RANGE OR TRANSLATE FAILURE +; BR, BRX, PRESERVED. +; B=0 IF TRANSLATE, =1 IF OFFSET MODE, =2 IF EDIT, =4 IF CVTDBT + + +=00 +SRCMOD: SLEN_AR,AR+ARX+MQ_0.M,CALL.M, ;PUT LENGTH AWAY, GET BYTE + SIGNS DISP,J/GSRC ;CHECK FOR LENGTH EXHAUSTION + AR_SFLGS,SR_0,RETURN1 ;LEN =0, DONE + E1,TIME/2T,B DISP ;BYTE IN AR +=110 AR_AR*.5 LONG,E1,J/XLATE ;LOW BIT TO ARX0, BYTE/2 TO AR LOW + AR_AR+E1,TIME/3T ;OFFSET, ADD OFFSET, TEST MASK + TEST AR.MSK,SKP CRY0,RETURN4 ;RETURN 4 IF OK, 5 OUT OF RANGE + +;HERE ON TRANSLATE-MODE OPERATIONS, WITH THE BYTE/2 IN AR, AND +; THE LEAST SIGNIFICANT BIT OF THE BYTE IN ARX0. PERFORM THE +; TABLE LOOKUP, AND OPERATE AS CONTROLLED BY THE HIGH THREE BITS +; OF THE TABLE ENTRY. + +XLATE: VMA_AR+E1,LOAD AR ;GET FUNCTION FROM TABLE + +TRNAR: AR_MEM,SKP ARX0,SC_#,#/18. ;WHICH HALF? +=0 ARX_AR,AR0-3 DISP, ;LH, MOVE TO ARX LEFT + AR_SFLGS,J/TRNFNC + ARX_AR SWAP,AR18-21 DISP, ;RH, MOVE THAT TO ARX LEFT + AR_SFLGS,J/TRNFNC + ;HERE ON TRANSLATE OPERATION TO PERFORM FUNCTIONS REQUIRED BY +; THE 3 HIGH ORDER BITS OF THE TRANSLATE FUNCTION HALFWORD. +; WE HAVE DISPATCHED ON THOSE THREE BITS, WITH THE FUNCTION +; HALFWORD IN LH(ARX), AND THE FLAGS FROM AC0 IN AR. + +=0001 +TRNFNC: SFLGS_AR,FE_P,AR_SHIFT, ;SAVE FLAGS, GET FCN IN AR RIGHT + SIGNS DISP,J/TRNRET ;WAS S FLAG ALREADY SET? +TRNABT: SFLGS_AR,FE_P AND #,#/3,RETURN5 ;ABORT + P_P AND #,#/67,J/TRNFNC ;CLEAR M FLAG + P_P OR #,#/10,J/TRNFNC ;SET M FLAG +TRNSIG: P_P OR #,#/20,J/TRNFNC ;SET N FLAG + P_P OR #,#/20,J/TRNABT ;SET N AND ABORT + P_P AND #,#/67,J/TRNSIG ;CLEAR M, THEN SET N + P_P OR #,#/30,J/TRNFNC ;SET N AND M + +=011 +TRNRET: ARX_AR*MSK,AD/AND, ;S FLAG IS 0, GET BYTE IN AR + SKP AR18,B DISP,J/TRNSS ;IS THIS EDIT? + AR_AR*MSK,AD/AND,RETURN4 ;RETURN NORMAL SINCE S FLAG SET + +=100 +TRNSS: AR_DLEN,B DISP,J/TRNNS1 ;NO SIG ON MOVE OR D2B + AR_SFLGS,SC_#,#/40,J/TRNSS1 ;SIG START, SET FLAG + VMA_E0+1,LOAD AR,RETURN2 ;EDIT NO SIG. GET FILL + AR_DSTP,FE_#,#/36.,RETURN3 ;EDIT SIG START + +=0** +TRNNS1: AR_AR-1,J/TRNNS2 ;COMPENSATE FOR IGNORING SRC + AR_SLEN+1,J/SRCMOD ;D2B HAS NO DEST LENGTH +TRNNS2: DLEN_AR,SIGNS DISP +=011 AR_SLEN,J/SRCMOD ;SLEN = DST LEN, DON'T CHANGE IT + AR_SLEN+1,J/SRCMOD ;SLEN REFLECTS SRC LENGTH + ; COUNT DOWN FOR BYTE SKIPPED +TRNSS1: P_P OR SC + SFLGS_AR,AR_ARX,RETURN4 ;RETURN WITH SIG SET + ;SUBROUTINE TO GET BYTE FROM SOURCE STRING +; CALL GSRC WITH SIGNS DISP TO CHECK FOR LENGTH EXHAUSTION +; [TIME = 17 + 3(BP OVERFLOW)] + +=011 +GSRC: AR_DLEN,RETURN1 ;LEN RAN OUT +GETSRC: AR_SRCP,ARX_SRCP,FE_#,#/36. +=0 +GSRC1: P_P-S,SC/SCAD,CALL.M, ;UPDATE POINTER + SKP SCAD0,J/GSRC2 ;TEST FOR WORD OVERFLOW + SC_FE+SC,SKP INTRPT,J/LDB1 ;GET BYTE & RETURN TO CALLER +=0 +GSRC2: SRCP_AR,ARX_AR,FE_S, ;STORE POINTER, + EA MOD DISP,J/BFETCH ; GO EVALUATE THE ADDRESS + AR_AR+1,P_FE-S,SC/SCAD,J/GSRC2 + +;SUBR TO STORE AR IN DEST STRING +; [TIME = 24 + 3(BP OVERFLOW)] + +=00 +PUTDST: MQ_AR,AR_DSTP,ARX_DSTP, + FE_#,#/36.,CALL,J/IDST + AR_MQ,SC_#-SC,#/36.,SKP SCAD0, + CALL,J/DPB1 +=11 MEM_AR,RETURN6 + + + +;SUBROUTINES TO UPDATE STRING POINTERS + +IDST: P_P-S,SC/SCAD,SKP SCAD0 ;TEST FOR WORD OVERFLOW +=0 +IDST1: DSTP_AR,ARX_AR,FE_S, ;STORE POINTER, + EA MOD DISP,J/BFETCH ; GO GET THE WORD ADDRESSED + AR_AR+1,P_FE-S,SC/SCAD,J/IDST1 +.ENDIF/EIS + +XFERW: FIN XFER,MB WAIT,RETURN2 ;FINISH TRANSFER, RETURN + +.IF/EIS + .TOC "EIS -- EDIT FUNCTION" +; HERE WITH E0, E1 SETUP, 0 IN AR, -1 IN ARX, AND 15 IN SC + +EDIT: AR_SHIFT,ARX_AC0 ;MASK TO AR, FLAGS ETC TO ARX +=1*0 MSK_AR,AR_ARX (AD), ;SAVE MASK, GET FLAGS IN AR + VMA_ARX,LOAD AR, ;GET FIRST PATTERN OPERATOR + CALL,J/TRNABT ;GET PBN INTO FE +EDITLP: SC_# AND AR0-8,#/30, ;PBN*8 IN SC + SFLGS_AR,ARX_AR ;UPDATED AC NOW IN AC AND ARX +=0* SC_FE+SC,SR_0,CALL,J/XFERW ;PATTERN IN AR, PBN*9 IN SC + AR_SHIFT,SH DISP,SC_#,#/5 ;PATTERN BYTE TO AR0-8, +=0001 ; DISP ON HIGH 3 BITS +EDDISP: GEN #+AR0-8,#/-5, + SKP SCAD0,J/EDOPR ;(0XX) OPERATE GROUP + AR_AR*8,SKP ARX0,J/EDMSG ;(1XX) MESSAGE + J/EDNOP ;(2XX) UNDEFINED + J/EDNOP ;(3XX) UNDEFINED + J/EDNOP ;(4XX) UNDEFINED + MQ_ARX,ARX_ARX*4, + SC_FE+1,J/EDSKPT ;(5XX) SKIP IF MINUS + MQ_ARX,ARX_ARX*2, + SC_FE+1,J/EDSKPT ;(6XX) SKIP IF NON-ZERO + AR_AR*8,SC_FE+1,J/EDSKP ;(7XX) SKIP ALWAYS + +;HERE TO DECODE OPERATE GROUP +=0 +EDOPR: J/EDNOP ;OPR .GE. 005 UNDEFINED + SH DISP,J/OPDISP ;(00X), DISP ON LOW 3 BITS +=000 +OPDISP: AR_ARX,SC_#,#/-4, ;(000) STOP + VMA_PC+1,J/EDSTOP + SR_ED(S),J/EDSEL ;(001) SELECT + AR_DSTP,SKP ARX0,J/EDSSIG ;(002) START SIGNIFICANCE + AR_ARX,J/EDFLDS ;(003) FIELD SEPARATOR + VMA_AC3,LOAD ARX, ;(004) EXCH MARK AND DEST + MQ_ARX,J/EDEXMD += +;HERE TO TERMINATE EDIT INSTRUCTION +; SC HAS -4, FE HAS CURRENT PBN, VMA HAS PC IF ABORT, PC+1 IF DONE + +EDSTOP: FE_FE-#,#/3,SKP SCAD0 +=0 AR_AR+1,INH CRY18, + P_P AND SC,J/SFET1 + P_P+1 +SFET1: FETCH+1,J/STORAC + ;HERE FOR SKPM & SKPN, WITH APPROPRIATE BIT IN ARX0 + +EDSKPT: AR_AR*8,SKP ARX0,ARX/MQ ;SKIP DISTANCE TO AR0-5 + +;HERE AT END OF OPERATION TO UPDATE PBN +=0 +EDNOP: FE_FE-#,#/3,SKP SCAD0, ;END OF PATTERN WORD? + AR_ARX,J/EDNXT1 +EDSKP: FE_P+SC,J/EDNOP ;ADD SKIP DISTANCE +=0 +EDNXT1: AR_AR+1,INH CRY18, ;BUMP TO NEXT WORD + FE_FE-#,#/4, ;REDUCE PBN + SKP SCAD0,J/EDNXT1 + FE_FE+#,#/4 ;RESTORE PBN POS, INCR IT + SC_P AND #,#/74,VMA_AR,LOAD AR ;FLAGS & EDIT BIT TO SC, GET PATTERN + P_FE OR SC,J/EDITLP ;SET NEW PBN, GO DO NEXT PATTERN + +;HERE TO EXCHANGE MARK AND DESTINATION POINTERS + +EDEXMD: AR_DSTP ;READY TO STORE DEST PTR + FIN XFER,STORE ;WAIT FOR MARK, STORE DSTP + MEM_AR,AR_ARX ;READY TO UPDATE DSTP + DSTP_AR,ARX/MQ,J/EDNOP ;DONE, GET NEXT OPR + +;HERE FOR FIELD SEPARATOR (CLEAR FLAGS IN AC 0-2) + +EDFLDS: P_P AND #,#/7,J/EDSEND ;EASY ENOUGH + +;HERE FOR SIG START + +=00 +EDSSIG: VMA_AC3,STORE,CALL,J/EDFLT ;SAVE MARK, GET FLOAT + FE_FE-#,#/3,SKP SCAD0, ;S FLAG ALREADY SET, NOP + AR_ARX,J/EDNXT1 +=11 +EDSEND: FE_P AND #,#/3,ARX_AR,J/EDNOP ;READY TO DO NEXT OP + +;HERE FOR MESSAGE CHAR + +=00 +EDMSG: VMA_E0+1,LOAD AR,J/EDSFIL ;NO SIG, PUT FILLER + SC_P,AR_0S,CALL,J/GETSC ;GET MESSAGE SELECT IN AR +=11 VMA_AR+E0+1,LOAD AR,J/EDMPUT ;STORE MESSAGE + ;HERE FOR SELECT + +=0* +EDSEL: AR_SRCP,ARX_SRCP,FE_#,#/36., + CALL,J/GSRC1 ;GO GET SRC BYTE + AR_AR*.5 LONG,E1 ;GOT IT, DIVIDE BY 2 +=000 VMA_AR+E1,LOAD AR,CALL,J/TRNAR ;GO TRANSLATE BY HALFWORDS +=010 +EDSFIL: AR_MEM,J/EDSF1 ;(2) NO SIGNIFICANCE, STORE FILL + GEN P-S,SKP SCAD0,BRX/ARX,J/EDSFLT ;(3) SIG START, DO FLOAT CHAR +EDSPUT: SR_ED(+D),CALL,J/PUTDST ;(4) NORMAL, STORE AT DST + VMA/PC,SC_#,#/-4,J/EDSTOP ;(5) ABORT +EDFPUT: AR_SFLGS,J/EDSEND ;(6) BUMP PBN AND GO TO NEXT +EDMPUT: AR_MEM,J/EDSPUT ;FILL OR MSG IN AR, STORE IT + + +;HERE WHEN TIME TO STORE FILL CHAR + +EDSF1: SKP AR NE,J/EDFPUT ;IS THERE ONE? + +;HERE WHEN SELECT STARTS SIGNIFICANCE + +=00 +EDSFLT: VMA_AC3,STORE,CALL,J/EDFLT ;STORE DEST AT MARK ADDR + P_FE,AR_AR+1,J/EDSFLT ;FORCE STANDARD POINTER FORM +=11 SFLGS_AR,AR_BRX,J/EDSPUT ;SET S FLAG, GET BYTE, STORE IT + +;HERE IS SUBROUTINE TO STORE FLOAT CHAR + +EDFLT: MEM_AR,AR_2 ;GET FLOAT FROM E0+2 +=0* VMA_AR+E0,LOAD AR,CALL,J/XFERW + SKP AR NE +=100 AR_SFLGS,SC_#,#/40,J/SETFLG ;NO FLOAT CHR, SET S FLAG + SR_ED(+D),CALL,J/PUTDST ;STORE FLOAT CHR IN DST +=111 AR_SFLGS,SC_#,#/40 ;SET S FLAG AND RETURN +SETFLG: P_P OR SC,RETURN3 ;NO FLOAT CHR, SET S FLAG + +.ENDIF/EIS + \ No newline at end of file diff --git a/src/ucode/fp.5 b/src/ucode/fp.5 new file mode 100755 index 00000000..46057ea6 --- /dev/null +++ b/src/ucode/fp.5 @@ -0,0 +1,552 @@ +.TOC "SINGLE FLOATING ADD & SUB -- FAD, FADR, FSB, FSBRCE  .DCODE +.1O/UFA. 130: I, J/UUO ;UFA + I, J/UUO ;DFN +.ENDIF/UFA.DFN + +140: R, FL-AC, B0/0, J/FAD + R, B0/0, J/FADL + RW, FL-MEM, B0/0, J/FAD + RW, FL-BOTH,B0/0, J/FAD + + R, FL-AC, J/FADR + I, FL-AC, B0/0, J/FADRI + RW, FL-MEM, J/FADR + RW, ŸTH, J/FADR + +150: R, FL-AC, B0/1, J/FSB + R, B0/1, J/FSBL + RW, FL-MEM, B0/1, J/FSB + RW, FL-BOTH,B0/1, J/FSB + + R, F`Y J/FSBR + I, F`Y B0/1, J/FSBRI + RW, FL-MEM, J/FSBR + RW, FL-BOTH, J/FSBR + .UCODE + +.IFNOT/FPLONG +=00**00 +FAD: +FSB: SR_#,#/1,B DISP,J/FADR ;FLAG NO ROUND, GO FAD/FSB +FMP: SR_#,#/1,J/FMPR +FDV: SR_#,#/1,J/FDVR +FADL: +FSBL: +FMPL: +FDVL: AR_BR,J/UUO ;LONG MODE BECOMES UUO += +.IF/FPLONG +=00***0 +FAD: +FSB: SR_#,#/1,B DISP,J/FADR ;FLAG TRUNCATE MODE, GO FAD +FADL: +FSBL: SR_#,#/2,B DISP,J/FADR ;FLAG LONG MODE +.ENDIF/FPLONG += +=00*010 +FADRI: +FSBRI: AR_AR SWAP,B DISP +FADR: FE_EXP,EXP_SIGN,SC/SCAD, + ARX_0S,J/FAS +=111 +FSBR: FE_EXP,SC/SCAD,EXP_SIGN,ARX_0S += AR_-AR,J/FAS ;NEGATE SUBTRAHEND + ;FIND OPERAND WITH LARGER EXP, LEAVING IT IN BR, +; AND ITS EXP-1 IN FE. THE SMALLER OPERAND IS LEFT IN AR, +; SHIFTED RIGHT BY THE DIFFERENCE BETWEEN THE EXPONENTS -1 + +FAS: BR/AR,BRX/ARX,AR_AC0 ;SAVE MEM OP IN BR, GET AC + SC_EXP-SC,EXP_SIGN,SKP SCAD0 ;FIND LARGER OPERAND +=0 FE_FE+SC,BR/AR,AR_BR*2,J/FAS1 ;AC EXP .GE. MEM + MQ_AR,SC_#+SC,#/37., ;MEM OP LARGER, SHIFT AC OP + SKP SCAD0,J/FAS2 ;COMPUTE SHIFT AMOUNT + +FAS1: MQ_AR,SC_#-SC,#/36.,SKP SCAD0 ;CHECK SHIFT AMOUNT +=0 +FAS2: MQ_SHIFT,ARX/MQ,AR_SIGN,J/FAS3 ;LOW TO MQ, READY TO GET HI + AR_SIGN,ARX_AR, ;HERE IF EXP DIFF .GT. 36 + SC_#+SC,#/36.,SKP SCAD0 ; .GT. 72? +=0 ARX_SHIFT,MQ_0.M,FE_FE+1,J/FAS5 + ARX_AR,MQ_0.M,FE_FE+1,J/FAS5 ;SHIFTED CLEAR OUT + +FAS3: AR_SHIFT,ARL/SH,ARX/MQ, + MQ_0.M,FE_FE+1 ;READY TO ADD + +FAS5: AR_(AR+2BR)*.25,ARX/ADX*.25, ;HERE FOR ADD OR SUB + NORM,J/SNORM + .TOC "SINGLE FLOATING MULTIPLY -- FMP, FMPR" + + .DCODE +160: R, FL-AC, J/FMP + R, J/FMPL + RW, FL-MEM, J/FMP + RW, FL-BOTH,J/FMP + + R, FL-AC, J/FMPR + I, FL-AC, J/FMPRI + RW, FL-MEM, J/FMPR + RW, FL-BOTH,J/FMPR + .UCODE +.IF/FPLONG +=00***0 +FMP: SR_#,#/1,J/FMPR ;FLAG TRUNCATE MODE +FMPL: SR_#,#/2,J/FMPR ;LONG MODE += +.ENDIF/FPLONG +=00***0 +FMPRI: AR_AR SWAP +FMPR: SC_EXP,EXP_SIGN,ARX_0S ;PREPARE M'IER FRACTION + += MQ_AR,AR_AC0,FE_#,#/-14. ;M'IER TO MQ, GET M'CAND +=01* SC_EXP+SC,EXP_SIGN, ;SEPARATE M'CAND FRACTION FROM EXP + CALL.S,J/MULSUB ;AND BEGIN MULTIPLY +=11* FE_#+SC,#/-200,NORM AR,J/SNORM += + .TOC "rgGE FLO5$Ώ DIVIDE --VY FDVR" + + .DCODE +170: RcL[0 /FDV + R, FL-AC, J/F  RW, FL-MEM, J/FDV + RW, FL-BOTH,J/FDV + + R, FL-AC, J/FDVR + I, FL-AC, J/FDVRI + RW, FL-MEM, J/FDVR + RW, FL-BOTH,J/FDVR + .UCODE +.IF/FPLONG +=00***0 +FDVL: Fء-1,EXP_SIGN,ARX+MQ_0.S,J/+LcD: SR_#,#/1,J/FDVR ;FLAG TRUNpjEAMODE += +.I/FPLOƊ{00***EFVRI: 4 SWAP +FDVNӇlPW1,EXP_SIGN,ARX+MQ_0.S ;SETUP DIVISOR +=OX0a BR/AK!R/ARX,"DIVISOH*OABR, CBX + 40,FE_ke7., ;j IVIDE TEP CgT SK a,CALLƉVCHKCE=c0 SKP0YCALL,KI- ;OkBGIN D5ӓON + qj L NO k,/IFNODO DIV1"ASORRY񢆊wRETUR$EE WIT(՟TIENTg RX. PTOK 29$֓DE ST)ATO +;ANTEE ֓NG A SΉING B5EEN IF$EAFIRSTE GENEPjE +; AjϩIENT Rj F ZER HEREFATHE MpO QUOT1gTAIS EI" ; INA7 OR AD NOR+əL FIN$AIN ON)ԋP. +OXa AR_AVF_FE+#ײY ;NEjIE QUObΩ + StB EQ,JVEG ;CaAFOR MUO TO͋ + ARiXU.25,AV/X*.25қ, ;JUI 36 B5)WAY FS栛SB + 1ߍE+#,#J_SNORM.O QUOT1gTY NORM3$ڋ += +;HERE IF QUOTIENT SHOULD BE NEGATIVE, WITH POSITIVE FORM INNA AND 4.A SKIPc EMAINi QIN BR($AZERO.$ATHIS piY +; W!̋AR AR BCAUSEi ONTAITE ENT4UOTIE ; IF, HOWEVER, THE REMAINDER IS NOT ZERO, WE INFER +; Tj N INF3ԋ PREC4ϝ DIVIrgAWOULD΋RATE EAONESNI THE 5gԓENT. c HAT Ih*H CASE+ALEAVEiXAWITH "; QUOTIENT, SO THE NEGATION PROCESS WILL WORK CORRECTLY TO RETURN񢝠HE HIODER P4 F THEgFNITE-ÓSION cIVE QINT. +DVNEGBiũ SR1,4*.25 GYNORM,KΟRM + 4_aS,J/FE ;R`ɝDER W O ZERE wHERE DVL +I/FPLOƊ ;FDVƋ_EXP-+"ء_SIGNRAARX+M#E=a00 +F1u AR_AlVB_AR L ;SAV"IISOR 3B LONG񢄉C_#,#W,ALL tY TO r$Ʃ LOW kIEND + ARX_SHIFT,AR_AC0, ;DIVIDEND IN PLACE + SC_FE,FE_#,#/24., ;EXP TO SC, STEP COUNT TO FE + SKP AD0,J/FDVCHK ;GO CHECK FOR NO DIVIF{010 C3&,KP BR %/DVL2 .ABEGIN$֓DE + qj L NO k,/IFNODAN'T kIE, AB  +=11`ҿAC0,SWѬG/5, sAQUO, ATRUNC5"ODE + SR DISP,J/FDVL4 ; WAS IT 26 OR 27 STEPS? + AR_AC0,SR_#,#/1, ;POS QƊ SR D4,/FDVLE= + +;COME HERE TO START THE DIVISION. ON THE FIRST STEP, WE CHErƊw TO SPWETHERP1AHAS Bg ENERAb N THEjϩIENT.$ASO, +; 26 ADDITIONAL STEPS WILL GENERATE THE FULL 27 SIGNIFICANT BITS +; OF$EAQUOTI.A IF N e7 STEAE REQiE. + +DVL2:1$֓DE,ARA-BR),4/DX*2,KDL3 ;F4ADIVID)ԋP + D5ċ,AR_2(AR+BJVAX/ADX*2 ; DOESj ҃PAA1? += 3u DISP/DIV,MQ/MQ*2, sAeAAN EXIVIDE STEP񢄉R_2(AR+BR),ARX/1,*e,J/DIVLP ; WITHj OUNTING FE + SRVS_#+SCױYJ/DIV- ;Y e7 STEPS WINRMALIQPQE 4/IV,MQhei_ei-R),ARX/ADX*2,J/kL + SRVS_#+SCױYKIcE wWE COPHRE AFTER DgGATHE DIVISION, EITHER H7ASTEPS񢝠h)EiE TO GENERAPAAMmE QUOT1gTAFROM MmE +; OPERANDS. 렍1ҋAWHAT EXPON PRMAINDER SHOULD HAVE.񢆊{EFVL4: SC_EXP-#,#웮Y"DIVIDEND EXP-27BD_BR,StA %/DVL6 qAREMAI"Y"ө D'EN)ɏN + Swء-#,#/M, ;D'END Em񢄉WRYSKP AR0 +NEE WITH REMAINDEH$AAR, IEP IN pƊwɡc 'END (AND THEREEAREM) NEGATIVE.CE=a +FDVL6: E/Ӈԋ DISP, ;TEST FOR UNDERFLƊ SKP AR EQƉVL7 ; EM =0 + AR_-BR,SKP CRY0, .EATE REM, CHECK =0 + GEN pBPDSP ; AND L堍OR EX*ƙE=c10 EXP_-SC-1,J/+Lo ;ONE'S COMPLEgTA(  AR_0S ;REM =0 OR EXP UFLOOXa +FDVL7: AloiXWMQ_0.wpkEAQf" AR_MQ,ASӝR2 ;G'OMALIZE QUOTIENT + AR)/FDVL7 +.ENDIF/FPLONE  +;SUBR TOEh#OOTING NO DIVIDE +; ENTER WITH SKP ON DIVIgDASIGN, IN AR LONG, WITH +;$֓SOR EXP IN SC, kIOR IN BR + +=0QVHK: SC_EXP-SC,E/ӓSP BR0ƉVCK1 + AR_-AR LONG,J/FDVCHK ;j OSITIPDbEE=aDrغGEN AR-2BR,SKP tY ;TEuFH'OADIVIDE pWSC,#/-۬ETURN2 ;AND CORRECT EXP + GEN AR+2BR,SKP CRY0, ;SAME TEST, NEG DIVISOR + pWSC,#/-۬*ҝ2 ;AN)E EXPҥIE ]TOC "A,AFSC, IBP" +;ENTWTH (E($A4]IF/UF+F񢄮sE 130: R, J/UFAҡW, J/DFN + .UCODE +=00**Lӝ a-8,AR0-8_#װY"]ӃPL"ء!̥ SO C3  ARX_0S,J/DFN1 ; DETECT FRACgA UFA: FE_EXP,SC/SCAD,EXP_SIGN,AV/ += +=000 BR_AR LONG,AR_AC0,CALL,J/(D =1000iX4A_SIGNiL_AD, ;READ(*OAUNNORMALIZ)̓"AOP + 0̙VJ_r$Ʃ_SIGNiX_AD ;LOSTLER O UE ITSǝ_AR+BK)ˡb wIS REufTArcΓaT? + SC_F$! = +=`c_AR,J/FINI"DCi ESULT AC + SKP EXP NE,BR/AR ;IS RIGHT SHIFT REQ'D? +=04A4,ETCH WAIT,Kƃ4 ;NO$ARESULT NEGE WRU.5,GEN FE-kgSP SCA'EYFETCH WAIT +=0 oc,SET FLOV + FE_UYSC/SCAD,SKP AR0 +=0 +UFA4B`a-8_SCө0؉t'Y PUT IN EXP STR2cȩ \_[SC-1,J/STAC1 ;NEG, ⠇hLMENT OF EXE  +DFN.`YSKP CRY0 ; LOW FRACTION =0? +=0 ALFE,ST"]өORE LOW WORD BArT MEM + ARX_AC0 COMP,J/STMAC ;AsЙEMENTHGH WORD + AR0-8_FE,STORE, ;LOW WORD WAS ZERO, INSTALLlP ARX_-AC0,J/STMAC h#ũ NEGATED HIGH WORD +.ENDIF/UFA.DFNC.DCODE +132: I, FL-AC, J/FSC + R, J/IBP ;ADJBP IF AC .NE. 0 + .UCODE +=00***0 +.IF/ADJBP +IBP: SKP AC#0,J/IBP1 ;IS IT IBP, OR ADJBP? +.IFNOT/ADJBP +IBP: J/IBP2 +.ENDIF/ADJBP + + +;FSC +;ENTER WITH E IN AR +=00**** +FSC: SC_EA,ARX+MQ_0.M, + AR_AC0,ARL/AD += FE_EXP+SC,EXP_SIGN,J/SNR2 ;NORMALIZE SCALED RESULT + .TOC "FIX, FIXR, FLTR, EXTEND" + + .DCODE +122: R, J/FIX ;UNROUNDED +.IF/EIS + R, J/EXTEND ;EXTENDED INSTRUCTION SET +.IFNOT/EIS + I, J/UUO +.ENDIF/EIS + +126: R, J/FIXR ;ROUNDED + R, FL-AC, J/FLTR + .UCODE + +;FLTR +;ENTER WITH (E) IN AR +=00***0 +FLTR: FE_#,#/277,ARX_AR,SKP AR0, ;BINARY POINT TO RIGHT OF ARX + AR_SIGN,J/SNORM ; SIGN EXTENDED. GO NORMALIZE + +;FIX AND FIXR +;ENTER WITH (E) IN AR +; FIX AND FIXR DIFFER ONLY IN THE ROUNDING CRITERION: +;FIXR ADDS 1 TO THE INTEGER PART IF THE FRACTION PART IS ONE-HALF +;OR GREATER. FIX DROPS THE FRACTION PART OF POSITIVE NUMBERS, BUT ADDS +;1 TO THE INTEGER PART OF NEGATIVE NUMBERS IF THE FRACTION PART IS NOT +;ALL ZERO. +; THIS IS IMPLEMENTED BY CHOOSING A FRACTION (THE ROUNDING +;CONSTANT) TO ADD TO THE INPUT, SUCH THAT A CARRY WILL OCCUR INTO THE +;INTEGER PART UNDER THE APPROPRIATE CONDITIONS. FOR FIXR, THE ROUNDING +;CONSTANT IS EXACTLY ONE-HALF. FOR FIX, IT IS ZERO ON POSITIVE INPUT, +;OR THE LARGEST POSSIBLE FRACTION (ALL 1S) ON NEGATIVE INPUT. + +=00**** +FIXR: FE_EXP-#,#/244,SKP SCAD0, ;GET BINARY POINT POSITION + ARX_1B1,J/FIX1 ;GET ROUNDING CONSTANT += +.IFNOT/EIS +;1005: ;REALLY IN SKPJMP FILE TO PREVENT 1005 BEING USED TWICE +;FIX: FE_EXP-#,#/244,SKP SCAD0, ;GET BINARY POINT POSITION +; ARX_AR SIGN,J/FIX1 ;SET ROUNDING CONSTANT, GO FIX +.IF/EIS +=00***0 +FIX: FE_EXP-#,#/244,SKP SCAD0, ;GET BINARY POINT POSITION + ARX_AR SIGN,J/FIX1 ;SET ROUNDING CONSTANT, GO FIX +EXTEND: FE_#+AR0-8,#/-20,SKP SCAD0, ;VALID EXTENDED OPERATION? + ARX_AR,AR_BRX,J/EXT1 ; OPR TO ARX, AC TO AR += +.ENDIF/EIS +=0 +FIX1: SET AROV,J/IFNOP ;CAN'T DO IT, GIVE UP + BR/AR,CLR AR,ARX_ARX*2 ;ROUNDING CONSTANT READY IN ARX + BR_AR LONG,AR_BR,CLR ARX, ;MANTISSA TO AR LONG + SC_#,#/9. ;READY TO SHIFT OFF EXPONENT + ARX_SHIFT,AR_SIGN, ;MANTISSA LEFT ALIGNED IN ARX + SC_FE+#,#/36.,SKP SCAD0 ;ANY INTEGER BITS? +=0 MQ_SHIFT, ;YES, PUT THEM IN MQ + AR_ARX (ADX),CLR ARX, ;SHIFT MANTISSA LEFT 36 PLACES + I FETCH,J/FIX2 ;AND PREFETCH NEXT + AR_0S,I FETCH,J/STORAC ;ALL SIGNIFICANCE LOST + +FIX2: ARX_SHIFT,AR_MQ ;INTEGER IN AR, FRACTION IN ARX + AR_AR+BR,AD LONG,J/STAC ;ROUND AND STORE + .TOC "SINGLE PRECISION FLOATING NORMALIZATION" + +;HERE TO NORMALIZE SINGLE PRECISION RESULTS +;SR2-3 TELL HOW TO STORE RESULTS: +;XX00 ... ROUND, SINGLE PRECISION +;XX01 ... TRUNCATE, SINGLE PRECISION +;XX10 ... LONG MODE (IMPLIES TRUNCATION) +;IN ADDITION, THIS CODE SETS SR 1 IF ANSWER IS NEGATIVE, SO X1YZ +; CORRESPONDS TO X0YZ EXCEPT THAT THE RESULT MUST BE NEGATED. + +;DISPATCH TO SNORM WITH "DISP/NORM,AR/AD*.25" +; THUS THE 8 POSSIBILITIES ARE: +;SNORM AD=0 AR=0 EITHER ANSWER IS ZERO, OR MSB IS IN ARX +;SNORM+1 AD0 AR NEG RESULT IS NEG. MAKE POS, TRY AGAIN +;SNORM+2 AD1-6 AR3-8 MSB TOO FAR LEFT, SHIFT RIGHT & RETRY +;SNORM+3 AD7 AR9 RESULT IS CORRECTLY NORMALIZED +;SNORM+4 AD8 AR10 SHIFT LEFT ONCE FOR NORMALIZATION +;SNORM+5 AD9 AR11 SHIFT LEFT 2 PLACES +;SNORM+6 AD10 AR12 SHIFT LEFT THRICE +;SNORM+7 AD11-35 AR13-35 SHIFT LEFT A LOT, TRY AGAIN + +=000 +SNORM: AR_ARX,ARL/SH,SKP ARX NE, ;AR IS ZERO, GET ARX + ARX_0.M,J/SNZERO + NORM -AR,SET SR1,J/SNORM ;REMEMBER NEGATIVE, GO POSITIVE +SNR2: AR_AR*.25 LONG,FE_FE+#,#/2, ;SHIFT RIGHT, + NORM,J/SNORM ;TRY AGAIN + SR DISP,J/SROUND ;AD7 -> AR9, IS ROUND REQ'D? + AR_AR*2 LONG,FE_FE-1, ;AD8 -> AR10, ONCE LEFT AND DONE + SR DISP,J/SROUND + AR_AR*4 LONG,FE_FE-#,#/2, ;AD9 -> AR11 + SR DISP,J/SROUND + AR_AR*8 LONG,FE_FE-#,#/3, ;AD10 -> AR12 + SR DISP,J/SROUND + ADA EN/0S,ADB/AR*4,AD/ANDCA, ;GENERATE AR*4 + AR/AD*2,ARX/ADX*2, ; AR_AR*8 LONG + SC_#,#/12., ;READY TO SHIFT FARTHER + GEN CRY18,SKP CRY0 ; TEST AR0-19 FOR ZERO + +=0 AR_AR*8 LONG,BR_AR LONG, ;IT WAS IN AR13-19 + FE_FE-#,#/6,NORM,J/SN1 ; NOW IN AR10-16, AD8-14 + MQ_SHIFT,AR_ARX (ADX), ;13-19=0, SHIFT TO TRY 20-35 + CLR ARX,SC_#,#/10. + ARX_SHIFT,AR_MQ*.25, ;REPOSITION FRACTION IN AR LONG + FE_FE-#,#/13., ;COMPENSATE EXPONENT + NORM,J/SNORM +=100 +SN1: AR_BR*2 LONG,FE_FE+#,#/2, ;MSB IN AD8, SO IN BR10 + SR DISP,J/SROUND + AR_BR*4 LONG,FE_FE+1, ;MSB IN AD9, THUS IN BR11 + SR DISP,J/SROUND + SR DISP,J/SROUND ;AD10 -> AR9, A LUCKY GUESS + AR_AR*8 LONG,BR_AR LONG, ;TRY SHIFTING 3 MORE + FE_FE-#,#/3,NORM,J/SN1 + ;HERE WHEN AD ENTIRELY ZERO ON NORMALIZE ATTEMPT. SKIP IF ARX +; IS NOT ZERO, HAVING COPIED IT TO AR (IE, LEFT SHIFT 36 PLACES). +; OTHERWISE, THE ENTIRE RESULT IS ZERO, SO WE STORE THAT. +=0 +SNZERO: CLR FE,AR+ARX+MQ_0.M, ;RESULT = 0 + SR DISP,J/SRND5 + AR_AR*.25 LONG,FE_FE-#,#/34., ;HAVE MOVED LEFT 36, GO RIGHT 2 + NORM,J/SNORM ;AND TRY THAT + + +;WE GET HERE WITH A NORMALIZED POSITIVE FRACTION IN AR'ARX, +; THE CORRECTED EXPONENT IN FE, AND SR INDICATES THE PROPER SIGN +; FOR THE RESULT AND WHETHER THE ANSWER SHOULD BE ROUNDED, +; TRUNCATED, OR LONG. + +.IF/FPLONG +=100 +.IFNOT/FPLONG +=1*0 +.ENDIF/FPLONG +SROUND: BR_AR LONG,AR_0S,J/SRND2 ;PREPARE TO ROUND BY ADDING THE + ; PART OF THE FRACTION WE WILL + ; DISCARD (CARRY IF ARX0) + BR_AR LONG,CLR AR,ARX_1S, ;TRUNCATE MODE + SR DISP,J/STRNC ; HANDLING DEPENDS ON SIGN +.IF/FPLONG + BR_AR LONG,CLR AR,ARX_1S, ;LONG MODE + SC_#,#/9. += ARX_SHIFT,SR DISP ;MASK = 0,,000777 TO ARX +=01* + BR_AR LONG,AR_BR LONG,J/SRND4 ;POS, TRUNCATE BY ANDING + AR_AR+BR,ARX/ADX,BR_AR LONG, ;NEG, MUST DIDDLE + NORM,J/SRND3 ; NORM FORCES LONG ARITH +.ENDIF/FPLONG + ;HERE TO PERFORM ROUNDING OR TRUNCATION OF SINGLE-PRECISION RESULTS, +; AND CHECK FOR CARRY INTO EXPONENT FIELD REQUIRING RENORMALIZATION + +=0*1 +STRNC: AR_BR,CLR ARX,J/SRND4 ;POS TRUNCATE, GO STUFF IN EXP +SRND2: AR_AR+BR,NORM,CLR ARX ;NORM FORCES LONG ARITH + ; SO THIS ADDS ARX TO BR'BRX +=1*0 +SRND3: AR_AR*.5,FE_FE+1 ;RENORMALIZE +SRND4: EXP_FE TST,SR DISP, ;STUFF EXP, CHECK NEG OR LONG + ARX_ARX*BRX,AD/ANDCB ;CLEAR TRUNCATED FRACTION + +;HERE TO STORE RESULT AS A FUNCTION OF SINGLE OR LONG PRECISION +; AND POSITIVE OR NEGATIVE... +.IF/FPLONG +=001 +.IFNOT/FPLONG +=0*1 +.ENDIF/FPLONG +SRND5: SR_0,B WRITE,J/ST6 ;POS & NOT LONG +.IF/FPLONG +SLNG3: AC0_AR,AR_0S,SC_#,#/27.,J/SLNG4 ;STORE HIGH PART OF LONG ANS +.ENDIF/FPLONG + AR_-AR,SR_0,B WRITE,J/ST6 ;NEG & NOT LONG +.IF/FPLONG + AR_-AR LONG,J/SLNG3 ;LONG NEG, MAKE IT SO + +SLNG4: AR_SHIFT,I FETCH + AR0-8_FE-SC,BYTE DISP, ;TEST FOR EXP UNDERFLOW + SKP AR EQ ; OR LOW WORD ZERO + +=110 +.ENDIF/FPLONG +STRAC1: SR_0,J/STAC1 ;PUT AWAY LOW WORD OF LONG RESULT +.IF/FPLONG + AR_0S,SR_0,J/STAC1 ;CLEAR LOW WORD IN AC1 +.ENDIF/FPLONG + .TOC "DOUBLE FLOATING ARITHMETIC -- DFAD, DFSB, DFMP, DFDV" + + .DCODE +110: R, B/0, J/DFLOAT ;DFAD + R, B/2, J/DFLOAT ;DFSB + R, B/4, J/DFLOAT ;DFMP + R, B/6, J/DFLOAT ;DFDV + .UCODE + +=00**0* +DFLOAT: FE_EXP,EXP_SIGN,SC/SCAD,MQ_0.S, + VMA_VMA+1,LOAD ARX, + CALL.S,J/XFERW ;GET LOW WORD + ARX_ARX*2,B DISP ;LOW BIT 0 IGNORED += +=00* +DFAS: BR_AR LONG,AR_AC1*2,J/DFAS1 ;MEM OP READY, GET AC OP + + AR_-AR LONG,J/DFAS ;DFSB, NEGATE AND ADD + + AR_AC1,BR_AR LONG, ;HERE FOR DOUBLE FLOATING MUL + FE_#,#/-18.,J/DFMP + + GEN AR*AC0,AD/XOR,SKP AD0, ;DFDV. WILL QUO BE NEG? + BR_AR LONG, ;SAVE D'SOR IN BR, BRX + SC_FE-1,J/DFDV + ;HERE FOR DFAD AND DFSB +; MEM OPERAND IS IN BR (NEGATED IF DFSB) +; FE AND SC HAVE ITS EXPONENT + +=0*0 +DFAS1: ARX_AR,AR_AC0,CALL,J/EXPD ;AC OPERAND IN PLACE +=1*0 +DFAS2: ARX_AR,AR_SIGN, ;GET SHIFTED HIGH WORD + GEN #+SC,#/-36., ;IS ANY SHIFT REQUIRED? + SKP SCAD0,J/DFAS3 + ARX_AR,AR_SIGN, ;DIFF IS > 36 + SC_#+SC,#/36.,SKP SCAD0 ;CHECK FOR >72 +=0 AC0_AR,MQ_SHIFT,AR_ARX (ADX), + ARX/MQ,J/DFAS4 ;36 < DIFF < 72 + AR_BR,ARL/AD,ARX_BRX, ;DIFF >72 + MQ_0.M,J/DNTRY ;NORMALIZE LARGER OP +=0 +DFAS3: AR_ARX,ARL/SH,ARX/MQ, ;NO SHIFT REQUIRED + MQ_0.M,J/DFAS5 + AR_SHIFT ;BEGIN SHIFTING SMALLER OP + AC0_AR,AR_ARX,ARX/MQ ;HI PART TO AC + MQ_SHIFT,AR_ARX (ADX), ;MID PART TO MQ + CLR ARX ;SHIFT ZEROS IN FROM RIGHT +DFAS4: MQ_SHIFT,ARX/MQ,AR_AC0 ;ALL PIECES NOW IN PLACE +DFAS5: AR_AR+BR,ARX/ADX,SC_#,#/4, ;HERE WHEN OPERANDS ALIGNED + NORM,J/DNORM ;ADD, AND NORMALIZE RESULT + + +;SUBROUTINE TO CHOOSE OPERAND WITH SMALLER EXPONENT, AND +; PREPARE FOR SHIFTING IT. +; ENTER WITH ONE OPERAND FRACTION IN BR, ITS EXPONENT IN FE & SC, +; THE OTHER OP IN AR WITH ITS EXPONENT IN AR0-8 +; RETURN THE LARGER EXPONENT IN FE, AND 36-(MAGNITUDE OF DIFFERENCE) +; IN SC. RETURN 4 IF SC POSITIVE, 5 IF NEGATIVE. + +EXPD: SC_EXP-SC,EXP_SIGN,SKP SCAD0 ;COMPARE MAGNITUDES +=0 AR_BR,ARX_BRX,BR/AR,BRX/ARX, ;AC OP IS LARGER MAGNITUDE + FE_FE+SC,J/EXPD1 ;ITS EXP TO FE + MQ_ARX,SC_#+SC,#/36., ;CHECK FOR EXP DIFF > 36 + SKP SCAD0,RETURN4 +EXPD1: MQ_ARX,SC_#-SC,#/36., ;AC EXP .GE. MEM + SKP SCAD0,RETURN4 ;SHIFT MEM OP + ;DFMP +; GET HERE WITH MEM OPERAND (M'CAND) IN BR!BRX +; AR HAS (AC1), LOW HALF OF M'IER + +=00* +DFMP: MQ_AR,AR_0S,ARX_0S, ;SETUP LOW M'IER + SC_#+SC,#/-200, ;CORRECT EXPONENT + CALL,J/MULREE ;MULTIPLY BY THE LOW PART +=10* AR_AR+BR LONG ;OOPS, LOW SIGN WAS SET + MQ_AR,AR_AC0,FE_#,#/-14. ;READY TO CONTINUE WITH HIGH PART + +;HERE TO USE HIGH MULTIPLIER + + SC_EXP+SC,EXP_SIGN.M, ;EXTRACT EXP FROM HIGH WORD + SKP AR0 ;CHECK FOR NEG M'IER +=010 +DFMP2: MQ_AR,AR_MQ,CALL,J/MULREE ;GO BACK IN FOR HIGH PART + EXP_1,J/DFMP2 ;OOPS, NEG, MOVE SIGN TO BIT 8 +=110 +DNTRY: SC_#,#/4,GEN AR,NORM,J/DNORM ;NORMALIZE THE ANSWER += + + +;DFDV +; GET HERE WITH DIVISOR IN BR!BRX, ITS EXP-1 IN SC +; SKIP IF D'SOR AND D'END SIGNS DIFFER + +=000 +DFDV: AR_AC1*2,CALL,J/DFDV1 ;GET LOW D'END, GO START DIVIDE + SR_1,AR_AC1*2,CALL,J/DFDV1 ;NOTE NEG QUO + +=011 AC1_AR,AR_MQ,ARL/AD,FE_FE+1, ;HERE FROM DDVSUB. NEW STEP CNT + MQ_0.M,CALL.M,J/DIV+ ; SAVE HIGH QUO, RESUME +=101 AC1_AR,AR_MQ,ARL/AD,FE_FE+1, + MQ_0.M,CALL.M,J/DIV- + +=111 AR_AC1,ARX/MQ,SC_#,#/4, ;POSITIVE QUOTIENT TO AR LONG + NORM,J/DNORM ;NORMALIZE AND ROUND + +=00 +DFDV1: ARX_AR,AR_AC0,SKP AD0, ;TEST DIVIDEND SIGN + FE_#,#/26., ;SETUP COUNT FOR HIGH QUO + CALL,J/FDVCHK ;GO CHECK DIVIDABILITY +=10 SKP BR0,J/DDVSUB ;BEGIN DIVISION (RETURN ABOVE) + SET FL NO DIV,J/IFNOP ;ABORT THE DIVISION + .TOC "DOUBLE PRECISION NORMALIZATION" + +=000 +DNORM: SKP ARX+MQ NE,SC_#,#/35.,J/DNZERO ;AR=0 + BR/AR,BRX/ARX,AR_MQ COMP, ;RESULT NEG, MAKE POS + SR_1,J/DNNEG ;FLAG NEGATIVE + AR_AR*.25 LONG,MQ_MQ*.25, + FE_FE+#,#/4,J/DNHI ;MSB IN AR 1-6 + AR_AR*.25 LONG, + FE_FE+#,#/2,J/DROUND ;MSB IN AR7 + AR_AR*.5 LONG,FE_FE+1 ;MSB IN AR8 +DROUND: AR_AR+1,ARX/ADX,NORM, ;MSB IS AR9, RIGHT ON + SC_#,#/35.,J/DRND1 + (AR+ARX+MQ)*2,FE_FE-1,J/DROUND ;MSB IN AR10 + AR_SHIFT,FE_FE-SC ;SOMEWHERE IN AR 11-35 + +DNSHFT: BR/AR,AR_ARX,ARX/MQ ;SHIFT THE WHOLE THING + MQ_SHIFT,AR_ARX (ADX),CLR ARX + MQ_SHIFT,ARX/MQ,AR_BR,SC_#,#/10., + NORM,J/DNORM ;GIVE IT ANOTHER GO + +DNNEG: AR_AR+1,SKP CRY0 ;COMPLETE NEGATION OF MQ +=0 MQ_AR,AR_BR COMP,ARX_BRX COMP, + NORM,J/DNORM ;NORMALIZE THE POS FORM + MQ_AR,AR_-BR,ARX/ADX,NORM,J/DNORM + +DNHI: (AR+ARX+MQ)*.25,J/DNTRY ;GO TRY AGAIN + +=0 +DNZERO: SR_0,AR_0S,ARX_0S,J/DBLST ;RESULT = 0, STORE THAT + AR_SHIFT,FE_FE-SC,J/DNSHFT ;NOT ZERO, SHIFT AND TRY AGAIN + +=110 +DRND1: AR_AR*.5 LONG,FE_FE+1 ;ROUNDING BLEW THE NORM, GO RIGHT + EXP_FE TST,SR DISP,CLR MQ, ;STUFF EXP IN, CHECK RESULT SIGN + BRX/ARX,ARX_1 ;READY IF NEGATION NECESSARY + +=0 AC0_AR,AR_SHIFT,ARX_BRX, ;STORE HIGH WORD, READY LOW + I FETCH,J/STD1 + ARX_ARX*BRX,AD/ANDCA,SR_0 ;CLEAR ROUNDING BIT + AR_-AR LONG,J/DBLST ;NEGATE RESULT AND STORE + \ No newline at end of file diff --git a/src/ucode/io.51 b/src/ucode/io.51 new file mode 100755 index 00000000..bcae7d5b --- /dev/null +++ b/src/ucode/io.51 @@ -0,0 +1,1219 @@ +.TOC "I/O INSTRUCTIONS" + +; BITS 10-12 OF INSTRUCTION GET MAPPED TO IR 7-9 FOR I/O INSTRUCTIONS +; THE DEVICE ADDRESS IS BROKEN DOWN AS ONE OF THE FIRST 7, OR ALL OTHERS + .DCODE + +;DEVICE 000 (APR) + +700: W, J/APRBI ;BLKI APR, OPTIONS, SERIAL # + W, DATAI, J/APRDI ;DATAI APR, ADDRESS COMPARE + I, J/APRBO ;BLKO APR, REFILL RAM + R, DATAO, J/APRDO ;DATAO APR, ADDRESS COMPARE + I, CONO, J/APRCO ;CONO APR, APR FLAGS + I, CONI, J/APRCI ;CONI APR, + I, CONSZ, J/APRCI ;CONSZ APR, + I, CONSO, J/APRCI ;CONSO APR, + +;DEVICE 004 (PI) + +710: W, M, J/PIBI ;BLKI PI, READ ERA + W, B/3, J/PIDI ;DATAI PI, UNASSIGNED + R, J/PIBO ;BLKO PI, SBUS DIAGNOSTIC + R, B/0, J/PIDO ;DATAO PI, UNASSIGNED + I, CONO, J/PICO ;CONO PI, PI SYSTEM CONTROL + I, CONI, J/PICI ;CONI PI, IN PROGRESS, ENABLE + I, CONSZ, J/PICI + I, CONSO, J/PICI + +;DEVICE 010 (PAG) + +720: RW, BLKI, J/PAGBI ;BLKI PAG, UNASSIGNED + W, DATAI, J/PAGDI ;DATAI PAG, USER CONTEXT + I, J/PAGBO ;BLKO PAG, INVAL PAGE TABLE + R, DATAO, J/PAGDO ;DATAO PAG, USER CONTEXT + I, CONO, J/PAGCO ;CONO PAG, EXEC CONTEXT + I, CONI, J/PAGCI ;CONI PAG, + I, CONSZ, J/PAGCI + I, CONSO, J/PAGCI + +;DEVICE 014 (CCA) + +730: I, J/SWEEP ;8 FUNCTIONS TO SWEEP THE CACHE + I, J/SWEEP ;SWPIA INVALIDATE ALL CACHE, NO CORE UPDATE + I, J/SWEEP ;SWPVA VALIDATE ALL CORE, LEAVE CACHE VALID + I, J/SWEEP ;SWPUA UNLOAD ALL CACHE TO CORE, CLEAR CACHE + I, J/SWEEP + I, J/SWEEP ;SWPIO INVALIDATE ONE PAGE + I, J/SWEEP ;SWPVO VALIDATE ONE PAGE + I, J/SWEEP ;SWPUO UNLOAD ONE PAGE + ;I/O CONT'D + +;DEVICE 020 (TIM) + +740: W, B/1, J/RDMTR ;BLKI TIM, PERF CNT + W, B/0, J/RDMTR ;DATAI TIM, TIME BASE + R, DATAO, J/TIMBO ;BLKO TIM, PA ENABLES +.IFNOT/MUSIC + R, DATAO, J/TIMDO ;DATAO TIM, UNDEFINED +.IF/MUSIC + I, DATAO, J/PLAY ;DATAO TIM, MUSIC PLAYER +.ENDIF/MUSIC + I, CONO, J/TIMCO ;CONO TIM, SETUP INTERVAL TIMER + I, CONI, J/TIMCI ;CONI TIM, RD INTERVAL & PERIOD + I, CONSZ, J/TIMCI + I, CONSO, J/TIMCI + +;DEVICE 024 (MTR) + +750: W, B/3, J/RDMTR ;BLKI MTR, CACHE CNT + W, B/2, J/RDMTR ;DATAI MTR, EBOX CNT + I, J/UUO ;BLKO MTR, UNDEFINED + I, J/UUO ;DATAO MTR, UNDEFINED + I, CONO, J/MTRCO ;CONO MTR, ACCT & TB CTL + I, CONI, J/MTRCI ;CONI MTR, SAME + I, CONSZ, J/MTRCI + I, CONSO, J/MTRCI + +;DEVICE 030 + +760: RW, BLKI, J/BLKIO + W, DATAI, J/IO + RW, BLKO, J/BLKIO + R, DATAO, J/IO + I, CONO, J/CONO + W, CONI, J/IO + I, CONSZ, J/CONS + I, CONSO, J/CONS + +;DEVICES 034-774 (ALL OTHERS) + +770: RW, BLKI, J/BLKIO + W, DATAI, J/IO + RW, BLKO, J/BLKIO + R, DATAO, J/IO + I, CONO, J/CONO + W, CONI, J/IO + I, CONSZ, J/CONS + I, CONSO, J/CONS + + .UCODE + .TOC "EXTERNAL DEVICE I/O INSTRUCTIONS" + +=00*000 +BLKIO: SKP IO LEGAL,CALL,J/IOCHK ;FIRST VERIFY INSTR VALIDITY + BYTE DISP,J/BLK1 ;TEST FPD +CONS: ;HERE FOR CONSO, CONSZ TO LOAD + ; BR IN CASE OF UUO +CONO: BR/AR,ARL_ARR,ARR_ARR ;CONDITIONS TO BOTH HALVES +=10 +IO: FIN XFER,MB WAIT, ;WAIT FOR MBOX IF BLKI/O + SKP IO LEGAL,CALL,J/GTEBUS +RELEEB: REL ECL EBUS,B WRITE ;XFER DONE, WHAT TO DO? += +=1*010 +IOTEND: FIN STORE,MB WAIT,J/BLK4 ;BLKI/BLKO + TEST AR.BR,TEST FETCH,J/NOP ;CONSZ + MEM_AR,SKP PI CYCLE,J/IOFET ;DATA/CON I/O + TEST AR.BR,TEST FETCH,J/NOP ;CONSO + +;BLKO/BLKI SCREWED AROUND WITH TO TRY TO STOP PI LOSSAGE. +BLK4: TEST BRL,TEST FETCH,SKP PI CYCLE,J/CLRFPD + +=1****0 +IOFET: I FETCH,J/NOP ;HERE IF NOT PI CYCLE + DISMISS,J/PIFET ;DISMISS INTRPT AFTER DATA/CON I/O + +=1**010 +BLK2: MEM_AR,BR/AR,VMA_AR,B DISP,J/BLK3 +BLK1: AR_AR+1,GEN CRY18,STORE,J/BLK2 ;UPDATE POINTER WORD +=111 SKP PI CYCLE,J/BLK2 ;IF FPD & NOT PI, DON'T INCREMENT +=1*101 ;DO DATAI OR DATAO +BLK3: LOAD AR,SET FPD,J/IO ;GET DATA TO OUTPUT + SET FPD,J/IO ;INPUT, DO IO BEFORE MEM +;NOTE NOTE NOTE SET FPD INHIBITED BY HARDWARE IF PI CYCLE (SCD5) + +;SUBROUTINES TO HANDLE EBUS +;CALL WITH "SKP IO LEGAL" +;ENTER AFTER LOADING AR IF OUTPUT FUNCTION + +=00 +GTEBUS: AR_BR,J/UUO ;HERE IF IO ILLEGAL IN THIS MODE + REQ EBUS,CALL,J/WGRANT ;ASK PI SYSTEM FOR BUS +=11 ;RETURN TO TRANSFER ROUTINE + +;SUBROUTINE TO PERFORM EBUS TRANSFER +;SETUP CONTROLLER SELECT AND FUNCTION LINES BEFORE CALL +;IF OUTPUT, ALSO PUT AR ONTO EBUS DATA LINES + +EBUSX: GEN AR,TIME/5T, ;WAIT AFTER ASSERTING FUNCTION + SET EBUS DEMAND,J/WXFER ; AFTER 300 NS, ASSERT DEMAND +=0 +EBUSW: AR_EBUS,GEN AR, + CLR EBUS DEMAND,J/RELEB ;STROBE DATA AND DROP DEMAND +WXFER: GEN AR,SKP -EBUS XFER,J/EBUSW ;WAIT FOR TRANSFER + +RELEB: GEN AR,REL EBUS,TIME/5T, ;DROP DATA, CS, AND FCN + RETURN3 ;AFTER 150 NS, THEN RELEASE BUS + + +;SUBROUTINE TO WAIT FOR PI SYSTEM TO GRANT EBUS +; IT WILL EITHER SEND EBUS GRANT, OR PI READY + +=0 +WGRANT: SKP -EBUS GRANT,J/WGRNT1 ;GOT IT? + DROP EBUS REQ,J/TAKINT +=0 +WGRNT1: IO INIT,GEN AR,J/WGRNT2 ;GOT IT, SETUP CS, FCN, AND DATA + SKP INTRPT,J/WGRANT ;DIDN'T GET IT, TEST FOR INTERUPT +WGRNT2: GEN AR,TIME/5T, ;JUST WAIT + EBUS CTL/IO INIT,RETURN3 + +;HERE TO START PI CYCLE TRANSFER. HOLD EBUS CTL SELECTION + +EBUSI: TIME/5T,EBUS CTL/DATAI,J/EBUSX +EBUSO: GEN AR,TIME/5T,EBUS CTL/DATAO,J/EBUSX + +;SUBROUTINES TO CHECK IO LEGALITY FOR INTERNAL I/O INSTRUCTIONS + +2002: ;ACCESSIBLE ON EXTEND [0] +IOCHK: AR_BR,J/UUO ;NAUGHTY, MUST'NT DO +2003: +RET1: RETURN1 ;ONE-CYCLE NULL ROUTINE + +=0 +GETEEB: AR_BR,J/UUO ;IO ILLEGAL IN THIS MODE +GTEEB1: GET ECL EBUS,RETURN1 + .TOC "INTERNAL DEVICE FUNCTIONS -- APR, CCA" + +=00***0 +SWEEP: BR/AR,SC_#,#/9.,CALL, + SKP IO LEGAL,J/IOCHK ;ALLOWED? + AR_SHIFT ;MOVE PAGE # TO PLACE += VMA_AR,SWEEP CACHE ;START A SWEEP +MBREL: MB WAIT,J/IFNOP ;COMPLETE REG FUNC BEFORE FETCH + + +=00**00 +APRDO: CALL,SKP IO LEGAL,J/GETEEB ;SET ADDR BREAK + DATAO APR,J/RELEEB +APRBO: BR/AR,CALL,SKP IO LEGAL,J/IOCHK ;SET CACHE REFILL ALGORITHM + WR REFILL RAM,J/MBREL ;INFO ALREADY IN VMA += + +=00*000 +APRDI: CALL,SKP IO LEGAL,J/GETEEB ;READ ADDR BREAK + DATAI APR(L),J/RELEEB +=010 +APRBI: CALL,SKP IO LEGAL,J/IOCHK ;RETURN MICRO VERSION, SERIAL # + AR_SERIAL,TIME/3T, ;READ SERIAL NUMBER + CALL,J/UVERS ;GET MICRO-CODE VERSION IN AR +=111 ARL_ARR.S,AR_BR ;COMB SERIAL WITH VERSION += AR0-8_#,#OPTIONS,STORE,J/STMEM ;SET OPTION FLAGS + + +=00**00 +APRCO: BR/AR,ARL_ARR.M,ARR_ARR,CALL.M, ;SET APR FLAGS + SKP IO LEGAL,J/GETEEB + CONO APR,J/RELEEB +APRCI: BR/AR,CALL, + SKP IO LEGAL,J/GETEEB ;READ APR FLAGS + CONI APR(R) ;GET RIGHT HALF OF APR CONDITIONS += ARX_AR SWAP,CONI APR(L) ;NOW LH COND TO AR LEFT + AR_ARX,ARL_ARL,J/RELEEB ;COMBINE HALVES + .TOC "INTERNAL DEVICE FUNCTIONS -- PI" + +=00*000 +.IFNOT/INSTR.STAT +PIDO: +PIDI: AR_BR,J/UUO ;DATAI/O PI, UNASSIGNED + +.IF/INSTR.STAT +;DATAO PI, SETS UP BUFFER POINTERS FOR TRACKS +;DATAI PI, READS CURRENT BUFFER POINTER + +PIDI: +PIDO: BR/AR,ARL+ARX_0.M,CALL.M, ;CHECK IO LEGALITY + SKP IO LEGAL,J/IOCHK + SC_#,#/9.,B DISP,SKP BR0,J/PIDX ;NOW, WHAT TO DO? +.ENDIF/INSTR.STAT + +PIBI: READ ERA,J/RDEBRG ;GET AND STORE +=0 +PIBO: CALL,SKP IO LEGAL,J/IOCHK ;SBUS DIAGNOSTIC + SBUS DIAG ;SEND THE DIAG FUNCTION FROM AR += AR/CACHE,VMA_VMA+1, + STORE,J/STMEM ;GET AND STORE THE RESPONSE + +=00*000 +PICO: BR/AR,ARL_ARR.M,ARR_ARR, + CALL.M,SKP IO LEGAL,J/PICOM1 +=11 CONO PI,J/PICOM2 ;SEND THE DATA +=00*100 +PICI: BR/AR,CALL,SKP IO LEGAL,J/PICOM1 +=11 CONI PI(R) ;READ RH TO AR LEFT += ARX_AR SWAP, ;RH COND TO ARX RH + CONI PI(PAR) ; AND PARITY ENABLES TO RH + BRX/ARX,ARX_AR, ;READY TO COMB RH PARTS + CONI PI(L) ; AND LH TO AR LEFT + AR_ARX*BRX,AD/OR,ARL_ARL ;COMBINE THEM +PICOM2: REL EBUS,GEN AR,B WRITE,J/IOTEND + +=0 +PICOM1: AR_BR,J/UUO ;LOSE + REQ EBUS,J/WGRANT ;OK, WAIT TO GET FULL EBUS + .TOC "TRACKS SUPPORT" + +.IF/INSTR.STAT +=00 +PIDX: CLR TRACKS EN,J/IFNOP ;TURN TRACKS OFF +.IF/TRACKS + ARX_SHIFT,ARL_BRL,ARR_0.S,J/PIDO2 +.IFNOT/TRACKS + TRX_AR,J/PIDO3 ;SAVE TABLE PAGE #, TURN ON +.ENDIF/TRACKS + +=11 AR_TRX ;READ BACK POINTER + ARL_0.M ;GET INDEX PART + AR_AR+TRB,STORE,J/STMEM ;DONE WITH DATAI + +PIDO2: TRX_AR,AR_ARX ;SET UP INDEX + TRB_AR ;AND BASE +PIDO3: SET TRACKS EN,J/IFNOP ;TURN TRACKS ON + +.IF/TRACKS +;HERE WHEN NICOND FINDS TRACKS ENABLED +=0 +TRK1: TRX_AR,J/TRK2 ;PUT BACK UPDATED INDEX + AR_AR SWAP ;END OF BUFFER. RESET + AR_-AR,J/TRK1 ; ORIGINAL INDEX + +TRK2: ARL_0.M + VMA_AR+TRB ;ADDRESS TRACKS BUFFER + AR_PC,STORE,PHYS REF ; PUT PC THERE + MEM_AR,VMA/PC,CLR TRACKS EN ;PREVENT NICOND SEEING TRACKS + SET TRACKS EN ;...UNTIL NEXT TIME + DISP/NICOND,J/NEXT ;GO DO NEXT INSTR +.ENDIF/TRACKS + .IF/OP.CNT +;HERE WHEN NICOND FINDS OPCODE COUNTING ENABLED +; SKIP IF USER MODE + +=0 +OPCT1: AR_TRX,SKP AC REF,J/OPCT2 ;TRX HAS PAGE # FOR EXEC TABLE + AR_TRX+1,SKP AC REF ; NEXT PAGE IS FOR USER +=0 +OPCT2: AR_SHIFT,J/OPCT3 ;OPCODE INDEXES INTO TABLE + ARX_FM(VMA),J/OPCT2 ;GET INSTR FROM FM +OPCT3: VMA_AR,LOAD AR,PHYS REF ;GET TABLE ENTRY + AR_MEM + AR_AR+1,STORE ;ADD THIS OCCURANCE TO IT + MEM_AR,VMA_PC,CLR TRACKS EN + SET TRACKS EN ;LET US GET BACK NEXT NICOND + DISP/NICOND,J/NEXT ;GO DO INSTR IN ARX +.ENDIF/OP.CNT +.IF/OP.TIME +;HERE TO ADD UP TIME SPENT IN INSTR'S + +OPTM1: BR_AR LONG,AR_ARX,ARX_TRB, ;THIS INSTR TO AR, LAST TO ARX + SKP AC REF +=0 +OPTM2: TRB_AR,J/OPTM3 ;SAVE NEXT INSTR + AR_FM(VMA),J/OPTM2 ;GET NEXT INSTR FROM FM +OPTM3: SC_#,#/9.,SKP USER ;WHICH TABLE SHALL WE USE? +=0 AR_TRX,J/OPTM4 ;EXEC + AR_TRX+1 ;USER +OPTM4: ARX_SHIFT,RD+CLR PA ;TABLE ADDR TO ARX, TIME TO AR + VMA_ARX,LOAD ARX,PHYS REF ;GET TABLE ENTRY + AR_AR-BR,ARL_0.S ;COMPENSATE TIME FOR THIS CODE + BR/AR,AR_MEM,SKP AR18 ;IF THIS WAS AN ENABLED STATE, +=0 AR_AR+BR,STORE ;WRITE IT BACK + MEM_AR,VMA/PC ;NOW SETUP NEXT INSTR AGAIN + ARX_BRX,SET TRK+PA EN ;RESTORE STATISTICS FLAGS + DISP/NICOND,J/NEXT +.ENDIF/OP.TIME +.ENDIF/INSTR.STAT + .TOC "INTERNAL DEVICE FUNCTIONS -- PAG" + +=00**00 +PAGBO: BR/AR,CLR FE,CALL, ;INVALIDATE ONE PAGE TABLE LINE + SKP IO LEGAL,J/IOCHK +PAGBO1: PT SEL_INVAL,J/PTLOOP ;SETUP INITIAL PT WR SELECT +PAGDO: ARX_AR (AD),ARR_ARL,ARL_ARL.M, ;SETUP USER CONTEXT + CALL.M,SKP IO LEGAL,J/GETEEB + DATAO PAG(L),AR_ARX ;SETUP AC BLOCKS, PREV CTXT += SKP AR2,SC_#,#/9. +=0 +TIMCO1: MTR CTL/CONO TIM,J/RELEEB ;DO NOT CHANGE UBR + MQ_SHIFT,SKP AR18,AR_0S ;STORE ACCT? +=0 AR0-8_#,#/100,CALL,J/PAGD2 ;YES, START WITH EBOX CNT + VMA_MQ,LOAD UBR,J/CLRPT ;NO, JUST CLEAR PAGE TABLE +=0 +PAGD2: ARX_AR,SC_#,#/13.,CALL,J/EMTR ;UPDATE THE EBOX ACCT + MB WAIT,AR0-8_#,#/140 ;READY TO GET CACHE ACCT + ARX_AR,SC_#,#/13.,J/CMTR ;RETURN ABOVE TO CLR PT + + +=00**00 +PAGDI: SC_#,#/70,SKP IO LEGAL, + CALL,J/GETEEB + DATAI PAG(L),CALL,J/PCTXT ;FIRST GET AC BLOCKS & CWSX +PAGBI: AR_BR,J/UUO ;BLKI PAG, IS UNASSIGNED + AR_SHIFT,ARL_BRL,J/RELEEB ;COMBINE UBR WITH AC BLKS, CWSX += +PCTXT: P_SC ;PLUG IN LOAD-ENABLE BITS +=1***0* + BR/AR,AR_0S,READ UBR, ;ASK MBOX FOR UBR LOC'N + CALL,J/XFERW ;NOW READ IT + AR_EBUS REG + ARX_AR,AR_0S,SC_#,#/27., ;READY TO MOVE INTO POSITION + RETURN3 +=00**00 +PAGCO: BR/AR,ARL_ARR.M,ARR_ARR,ARX_0S, ;SET EXEC CONTEXT + SKP IO LEGAL,CALL.M,J/GETEEB + CONO PAG,J/SETEBR ;SET CACHE, SEC, TRAP EN FLAGS + +PAGCI: BR/AR,AR_0S,CALL,SKP IO LEGAL, ;READ EXEC CONTEXT + SC_#,#/9.,J/GETEEB + CONI PAG ;READ CACHE, SEC, TRAP EN += +=1***0* + ARX_AR SWAP,AR_0S,READ EBR, ;SETUP EPT LOC'N TO READ + CALL,J/XFERW + AR_EBUS REG, ;GET EBR IN AR + BRX/ARX,ARX_0S ;SAVE FLAGS IN LH OF BRX + ARX_SHIFT,REL ECL EBUS ;MOVE EBR LOC LEFT + ARR_0.M,ADB/BR,ADA EN/EN,AD/OR,ARL/ADX ;COMBINE, THEN PUT IN RH + AR_AR SWAP,B WRITE,J/IOTEND ;STORE THE RESULT +;HERE TO FINISH CONO PAG, + +=1***0* +SETEBR: SC_#,#/9.,CALL,J/SHIFT ;MOVE EBR LOC'N TO POSITION + VMA_AR,LOAD EBR,J/CLRPT ;SETUP EBR + +;HERE TO CLEAR HWARE PAGE TABLE +; AFTER SETTING EBR OR UBR + +CLRPT: REL ECL EBUS ;DON'T HANG UP BUS FOR THIS +=0* +CLRPT1: AR_1,CLR ARX,MB WAIT, ;WAIT FOR U/E BR LOAD + SC_#,#/12.,CALL,J/SHIFT ;GET 1B23 + BR/AR,AR_0S,VMA/AD, ;START CLEARING AT ZERO + FE_#,#/63.,J/PAGBO1 ;SETUP LOOP COUNT +=110 +PTLOOP: AR_AR+BR,VMA/AD,FE_FE-1, ;SELECT A LINE OF PT + CLR PT LINE,TIME/3T, ;DO THE WORK + BYTE DISP,J/PTLOOP ;LOOP TO CLEAR ALL + PT SEL_NORMAL,J/IFNOP ;RESET PT WR SELECTION + .TOC "INTERNAL DEVICE FUNCTIONS -- TIM & MTR" + +=00***0 +RDMTR: AR_BR,CALL, ;GET E TO AR + SKP IO LEGAL,J/GETEEB ;GRAB CONTROL OF EBUS + MQ_AR,AR_0S, ;SAVE E IN MQ + SC_#,#/13.,B DISP ;WHICH COUNTER? += +=00 AR_TIME BASE,J/RDMTR1 ;DATAI TIM, + AR_PERF CNT,J/RDMTR1 ;BLKI TIM, + AR_EBOX CNT,J/RDMTR1 ;DATAI MTR, + AR_CACHE CNT,J/RDMTR1 ;BLKI MTR, + +=0 +RDMTR1: ARL+ARX_0.M,B DISP, ;SHIFT COUNT INTO POSITION + CALL.M,J/MTRDBL ;ADD DOUBLE WORD FROM PT + AR_AR+BR LONG,REL ECL EBUS + VMA_MQ,STORE,SC_#,#/35.,J/DMVM1 ;STORE TOTAL AT E & E+1 + +=00**00 +TIMCO: BR/AR,CALL,SKP IO LEGAL,J/GETEEB + CONO TIM,J/TIMCO1 +TIMCI: BR/AR,AR_0S,CALL, + SKP IO LEGAL,J/GETEEB + AR_INTERVAL ;INTERVAL GOES TO LH += ARX_AR SWAP,AR_0S + AR_PERIOD ;PERIOD TO RH +TIMBO1: MTR CTL/LD PA LH, ;KEEP MTR DECODE FOR TIMBO + ARL_ARXL,J/RELEEB ;COMBINE PERIOD WITH INTERVAL + +=00**00 +MTRCO: BR/AR,ARL_ARR.M,ARR_ARR, + CALL.M,SKP IO LEGAL,J/GETEEB + CONO MTR,J/MTRCO1 +MTRCI: BR/AR,AR_0S,CALL, + SKP IO LEGAL,J/GETEEB + CONI MTR ;READ BACK CONDITIONS += +MTRCO1: ARL_0.S,MTR CTL/CONO MTR,J/RELEEB + +=00*000 ;only =00***0 needed except dram bites the bag + ;so try to hack TIMBO and TIMDO into nearby addresses +TIMBO: ARX_AR,AR_0S,CALL, ;SAVE ENABLES, CLEAR AR + SKP IO LEGAL,J/GETEEB ;CHECK LEGALITY, GET BUS + BLKO TIM(L),AR_ARX ;TURN OFF BY CLEARING LH ENABLES + BLKO TIM(R),AR_AR SWAP ;SEND RH + BLKO TIM(L),J/TIMBO1 ;SEND LH, TURNING ON AGAIN + +.IFNOT/MUSIC +TIMDO: AR_BR,J/UUO ;DATAO TIM, UNDEFINED +.IF/MUSIC +PLAY: SKP PI CYCLE,BR/AR,AR_MUSTIM,J/PLAY0 ;MUSIC PLAYER +.ENDIF/MUSIC += + ;HERE WHEN METER INCREMENT REQUEST DETECTED + +MTRREQ: GET ECL EBUS ;TAKE CONTROL OF BUS + AR_MTR REQ ;WHAT TYPE REQUEST? +=0 MQ_AR,AR_AR*2,CALL, ;GET READY TO DISP + VMA_#,#/514,J/MTRRQ0 + REL ECL EBUS ;DONE + SET ACCOUNT EN,J/PIFET ;FETCH NEXT INSTR + +MTRRQ0: ARX_AR SWAP,DISP/SH0-3,AR_0S, ;DISPATCH ON REQUEST TYPE + SC_#,#/13. +=000 + RD+CLR TB,J/TMTR1 ;TIME BASE + RD+CLR PA,J/PMTR1 ;PERF ANALYSIS CNT +EMTR: RD+CLR E CNT,J/EMTR1 ;EBOX CNT +CMTR: RD+CLR C CNT,J/CMTR1 ;CACHE CNT + REL ECL EBUS ;INTERVAL -- VECTOR INTERRUPT += SET PI CYCLE + SET ACCOUNT EN,J/PIINST + +TMTR1: MTR CTL/CLR TIME,J/MTRRQ1 ;HOLD SELECTS FOR +PMTR1: MTR CTL/CLR PERF,J/MTRRQ1 ;MTR CTL FUNCTION +EMTR1: MTR CTL/CLR E CNT,J/MTRRQ1 ; TO PREVENT RACE +CMTR1: MTR CTL/CLR M CNT,J/MTRRQ1 ; AND POSSIBLE GLITCHES + +;HERE WITH RELEVANT COUNT IN ARR, GARBAGE IN ARL + +=0 +MTRRQ1: ARL+ARX_0.M,ARX0-3 DISP, ;CLEAR GARBAGE & RE-DISPATCH + CALL.M,J/MTRDBL ; TO ADD DOUBLE COUNTER FROM PT + AR_AR+BR LONG,SC_#,#/35., + VMA_VMA-1,STORE ;STORE BACK IN PROCESS TABLE + MEM_AR,AR_0S,ABORT INSTR ;HI PART TO MEM + AR_SHIFT,VMA_VMA+1,STORE,RETURN1 + +;HERE TO PICK UP DOUBLEWORD FROM PROCESS TABLE +; AND ADD CURRENT CONTENTS OF APPROPRIATE METER + +=00 +MTRDBL: AR_0S,ARX_SHIFT, + VMA_#,#/510,J/RDEMTR ;TIME BASE IN EPT 510-511 + AR_0S,ARX_SHIFT, + VMA_#,#/512,J/RDEMTR ;PERF CNT IN EPT 512-513 + AR_0S,ARX_SHIFT, + VMA_#,#/504,J/RDUMTR ;EBOX ACCT IN UPT 504-505 + AR_0S,ARX_SHIFT, + VMA_#,#/506,J/RDUMTR ;CACHE ACCT IN UPT 506-507 + +RDEMTR: BR_AR LONG, ;SAVE COUNT IN BR!BRX + LOAD AR,EPT REF,J/RDMTR2;GET HIGH WORD FROM EPT +RDUMTR: BR_AR LONG,LOAD AR,UPT REF ; OR UPT AS APPROP +=0* +RDMTR2: FIN XFER,VMA_VMA+1,LOAD ARX, ;NOW GET LOW WORD + CALL,J/XFERW ;GO WAIT FOR IT + ARX_ARX*2,RETURN1 + .TOC "PRIORITY INTERRUPT PROCESSING" +;HERE WHEN PRIORITY INTERRUPT REQUEST DETECTED +;PI LOGIC HAS DONE HANDSHAKE TO BRING FUNCTION WORD IN ON EBUS +; FUNCTION WORD IS NOW IN AR, SC=2 + +;THE FORMAT OF THE FUNCTION WORD IS -- +; 0-2 ADDRESS SPACE FOR THE FUNCTION +; 0=EPT +; 1=EXEC VIRTUAL +; 4=PHYSICAL +; OTHERS UNDEFINED +; 3-5 FUNCTION TO PERFORM (SEE LIST BELOW AT PIDISP) +; 6 FUNCTION QUALIFIER +; 7-10 PHYSICAL DEVICE # ON EBUS +; 11-12 UNDEFINED +; 13-35 ADDRESS FOR FUNCTION + +;IN THE CASE OF A STANDARD OR A VECTOR INTERRUPT, THE 'FE' +;REGISTER, WHICH IS NOT CLOBBERED BY THE BASIC INSTRUCTION +;LOOP NOR BY BLKO/BLKI, IS USED TO REMEMBER WHETHER IT WAS +;A STANDARD OR A VECTOR INTERRUPT. (0 FOR STANDARD, +;-1 FOR VECTOR.) IN THE CASE OF A VECTOR +;INTERRUPT, AC 'T0' IS USED TO REMEMBER THE FUNCTION WORD. +;THIS ALLOWS THE CORRECT ADDRESS FOR THE SECOND WORD OF +;A TWO-WORD INTERRUPT TO BE DETERMINED. THIS MAKES THE +;MIT IMPTERFACE WORK. NOTE THAT THIS HACK DOES NOT WORK +;FOR DTE20 OR RH20 VECTOR INTERRUPTS, BUT NO ONE WOULD +;EVER USE BLKO/BLKI WITH THOSE DEVICES. +;[COST = 2 WORDS] + +PICYC1: SET PI CYCLE,SH DISP ;START PI CYCLE +=1000 ;3-5 IS FUNCTION TO PERFORM +PIDISP: VMA_40+PI*2,CLR FE,J/PIINST ;(0) STANDARD INTERRUPT + VMA_40+PI*2,CLR FE,J/PIINST ;(1) DITTO + MQ_AR,T0_AR,J/PIVECT ;(2) VECTOR + VMA_AR,MQ_AR,LOAD AR,J/PIINCR ;(3) INCREMENT + VMA_AR,MQ_AR,SKP AR6,J/PIDATO ;(4) DATAO + VMA_AR,MQ_AR,TIME/5T,J/PIDATI ;(5) DATAI + MQ_AR,AR_AR*4,SKP AR6,J/PIBYTE ;(6) BYTE TRANSFER + VMA_40+PI*2,CLR FE,J/PIINST ;(7) UNDEFINED + +;HERE FOR 2ND INTERRUPT INSTRUCTION (PI OV) +=110 +PICYC2: VMA_41+PI*2,J/PIINST ;2ND PART OF STD INT +PICY2V: VMA_T0+1,LOAD ARX,J/XCTW ;2ND PART OF VECTOR INT + +PIINST: EPT FETCH,J/XCTW ;SAVE INSTRUCTION ADDRESS + +PIVECT: +.IF/KI INTERRUPT LOSES ;KLUDGE +;IN AC BLK 7, R4 GETS PI FCN WD, R5 GETS PI LEVEL +;(ONLY ON VECTOR INTERRUPTS) + E0_AR,MQ_AR + VMA_40+PI*2 + COND/LD VMA HELD + AR_VMA HELD + E1_AR + AR_MQ +.ENDIF/KI INTERRUPT LOSES ;END OF KLUDGE + AR_AR*4,SC_#,#/5 ;HERE FOR VECTOR INTR + FE_# AND S,#/30,AR_0S,SH DISP ;WHAT KIND OF DEVICE? +=0011 VMA_MQ,EPT FETCH,J/XCTW ;CHAN 0-3 + VMA_MQ,EPT FETCH,J/XCTW ;CHAN 4-7 + AR0-8_FE+#,#/142,J/DTEVEC ;DTE 0-3 +.IFNOT/KI INTERRUPT LOSES + VMA_MQ,LOAD ARX,FE_-1,J/XCTW ;EXTERNAL DEVICE +.IF/KI INTERRUPT LOSES + AR_MQ,ARL_0S ;EXTERNAL DEVICE + SKP AR NE ;SEE IF ADDR = 0 +=0 + DISMISS ;YES, FLUSH + VMA_MQ,LOAD ARX,FE_-1,J/XCTW ;NO, TAKE THE INT +.ENDIF/KI INTERRUPT LOSES + +=0* +DTEVEC: ARX_AR,AR_0S,SC_#,#/9.,CALL,J/SHIFT + VMA_AR,EPT FETCH,J/XCTW + +=0101 +PILD: LOAD AR,EPT REF,J/XFERW ;GET DATUM FROM EPT + LOAD AR,J/XFERW ; OR EXEC VIRTUAL ADDR SPACE + VMA_AR,READ EBR,J/PIKLG1 ; OR PHYSICAL MEMORY, AS REQUESTED + J/PIDONE ;IN CASE OF EBUS PROBLEMS + +;KLUDGE - NEED MEM/REG FUNC TO LOAD VMA EXT +PIKLG1: LOAD AR,PHYS REF,J/XFERW ;NOW DO THE MEMORY CYCLE + +;HERE TO PERFORM INCREMENT FUNCTION + +PIINCR: AR_MEM,SKP AR6 ;GET WORD, INCR OR DECR? +=0 AR_AR+1,STORE,J/PIDONE + AR_AR-1,STORE,J/PIDONE + ;HERE FOR DATAO (EXAMINE) FUNCTION + +=0000 +PIDATO: AR0-3 DISP,CALL.M,J/PILD ;GET DATA FROM REQUESTED ADR SPC + AR_AR*4,SC_#,#/13., + CALL,J/RDEX ;RESTRICTED EXAMINE +PIOUT: AR_MEM,SET DATAO,CALL,J/EBUSO ;SEND DATA +PIDONE: MEM_AR,DISMISS ;DONE, DISMISS & RESUME NORMAL +PIFET: VMA/PC,FETCH,J/NOP ;RESUME AS BEFORE +=0101 VMA_AR-1,CALL,J/DEXCHK ;GO PROT/RELOC THIS EXAM +=0111 VMA_AR+BR,LOAD AR,PHYS REF,J/PIOUT +=1111 J/PIOUT ;PROT VIOLATION. SEND 0 + +;HERE FOR DATAI (DEPOSIT) FUNCTION + +=10 +PIDATI: SET DATAI,TIME/5T,CALL,J/EBUSI ;READ THE DATA + ARX_AR,AR_MQ ;DATUM TO ARX, GET FCN WORD + BRX/ARX,SKP AR6 ;RESTRICTED? +=0000 AR0-3 DISP,ARX_AR,J/PIST ;NO, STORE AS REQUESTED + AR_AR*4,SC_#,#/13.,CALL,J/RDEX ;YES, GET PROT/RELOC ADDR +=0101 VMA_AR+1,CALL,J/DEXCHK ;VERIFY LEGALITY +=0111 VMA_AR+BR,J/PSTOR ;GO STORE RELOCATED +=1111 J/PIDONE ;PROT VIOLATION, STORE NOTHING + +=0101 +PIST: AR_BRX,STORE,EPT REF,J/PIDONE + AR_BRX,STORE,J/PIDONE +PSTOR: VMA_ARX,READ EBR,J/PIKLG2 ;KLUDGE TO SET VMA EXT + J/PIDONE + +PIKLG2: AR_BRX,STORE,PHYS REF,J/PIDONE ;NOW DO THE MEM CYCLE + +=10 +RDEX: FE_# AND S,#/30,AR_MQ,CLR ARX, ;DTE# *8 TO FE, ADDR TO AR + CALL,J/ROTS + AR_SHIFT ;ADDRESS NOW IN AR + BR/AR,AR0-8_FE+#,#/145 ;SAVE ADDR TO BR, GET EPT LOC +GTAR08: ARX_AR,AR_0S,SC_#,#/9. + AR_SHIFT,RETURN4 + +=0* +DEXCHK: CALL,J/PILD ;PROTECTION WORD FROM EPT + SKP AR GT BR ;ALLOWED? +=0 AR_0S,RETURN12 ;NO, SEND 0, STORE NOTHING + VMA_VMA+1,LOAD AR,EPT REF,J/XFERW ;YES, GET RELOCATION WORD + ;HERE FOR BYTE TRANSFERS + +=000 +PIBYTE: FE_# AND S,#/30,CALL,J/PIBPA ;OUT... GET BP ADDR + SET DATAI,CALL,J/EBUSI ;IN ... FIRST READ THE DATA +=011 ARX_AR,AR_MQ*4,J/PIDPB ;GOT IT, GO DEPOSIT IT + +=100 VMA_AR,CALL,J/PIIBP ;GO INCREMENT OUTPUT BP + SC_FE+SC,CALL,J/LDB1 ;GO LOAD BYTE FROM IT +=111 J/PIOUT ;THEN SEND BYTE + +=000 +PIDPB: BRX/ARX,FE_# AND S,#/30, ;HERE WITH INPUT DATA + CALL,J/PIBPA +=100 VMA_AR+1,CALL,J/PIIBP ;GO INCREMENT INPUT BYTE PTR + AR_BRX,SC_#-SC,#/36., ;STORE BYTE WITH IT + SKP SCAD0,CALL,J/DPB1 +=111 J/PIDONE + +PIBPA: AR0-8_FE+#,#/140,J/GTAR08 + +=00* +PIIBP: CALL,J/PILD ;GET POINTER FROM EPT + P_P-S,SKP SCAD0,CALL.M,J/IBPS ;INCREMENT IT +=11* ARX_AR,SC_P,J/BYTEA ;NOW EVALUATE ITS ADDR + .TOC "KL-MODE PAGE REFILL LOGIC" + +.IF/KLPAGE +;HERE ON ANY PAGE FAILURE +;THE POSSIBLE CAUSES ARE -- +; 1: A PARITY ERROR WAS DETECTED IN AR OR ARX FOLLOWING A READ +; REFERENCE. IN THIS CASE WE SAVE THE BAD WORD IN A RESERVED +; LOCATION IN FAST MEMORY BLOCK 7, AND RETURN A PAGE FAIL CODE +; INDICATING THE ERROR. +; 2: THE MBOX DETECTED A PROPRIETARY VIOLATION OR PAGE TABLE PARITY +; ERROR, OR THE EBOX FOUND THE SELECTED ADDRESS BREAK CONDITION. +; IN THIS CASE, WE RETURN THE PAGE FAIL CODE GENERATED BY THE +; MBOX (SEE PRINT PAG4). +; 3: A REFERENCE OCCURRED FOR A VIRTUAL PAGE FOR WHICH THE HARDWARE +; PAGE TABLE DIRECTORY HAD NO VALID MATCH. IN THIS CASE, WE +; WRITE THE PAGE TABLE DIRECTORY FROM THE VMA, AND CLEAR THE +; ACCESS BITS FOR ALL PAGE ENTRIES CONTROLLED BY THE SELECTED +; DIRECTORY ENTRY. WE THEN JOIN THE REFILL CODE, BELOW. +; 4: A REFERENCE OCCURRED FOR A VIRTUAL PAGE FOR WHICH THE ACCESS BIT +; IN THE HARDWARE PAGE TABLE WAS OFF, OR A WRITE OCCURRED TO A +; PAGE WHOSE WRITABLE BIT WAS OFF. IN THIS CASE, WE EVALUATE THE +; PAGING POINTERS IN CORE TO DETERMINE WHETHER THE ACCESS SHOULD +; BE ALLOWED, AND IF SO, THE PHYSICAL PAGE TO WHICH IT SHOULD BE +; TRANSLATED. WE THEN EITHER PAGE FAULT, OR WRITE A PAGE ENTRY +; INTO THE HARDWARE PAGE TABLE AND RESTART THE REFERENCE. + + +2377: CLR ACCOUNT EN,FORCE AR-ARX,J/PF1 +1777: CLR ACCOUNT EN,FORCE AR-ARX +PF1: SV.AR_AR,AR_ARX ;SAVE CURRENT AR + SV.ARX_AR ; AND ARX IN CASE PARITY ERROR + GET ECL EBUS,PF DISP,J/PF2 +=1100 +PF2: ;ANY PARITY ERROR? +=1101 AR_SV.AR,SC_#,#/156, ;YES. AR HAS THE BAD WORD. + SKP RPW,J/PFPAR ;CHECK FOR MIDDLE OF RPW CYCLE + AR_SV.ARX,SC_#,#/157,J/PFPAR ;YES. ARX HAS THE BAD WORD. +; BAG-BITING NO-OP ;ARX PARITY ERROR IS +; ;FRAUDULENT EVEN IN REV.7 + AR_EBUS REG,MB WAIT,J/PF3 ;NO. GET PAGE FAIL WORD + +;HERE ON ANY PARITY ERROR +;SKIP IF MIDDLE OF READ-PAUSE-WRITE CYCLE, IN WHICH CASE WE +; MUST WRITEBACK THE DATA TO PREVENT INCOMPLETE CYCLE +=0 +PFPAR: VMA_VMA HELD,MAP,J/PFPAR1 ;GET MAP INFO ON REF + STORE,J/PFPAR ;WRITEBACK WITH GOOD PARITY +PFPAR1: SV.PAR_AR,MB WAIT, ;SAVE WORD WITH BAD PARITY + SC_#+SC,#/160 ;GET PF CODE 36 OR 37 + AR_EBUS REG ;READ MAP INFO + P_P OR SC,J/PF3 ;INSERT PF CODE + ;HERE WITH PAGE FAIL WORD IN AR + +PF3: REL ECL EBUS,PF DISP ;EBOX HANDLING? +=0111 SV.PFW_AR,SR DISP,J/CLEAN ;NO, GO CLEAN UP + SV.PFW_AR,AR_BR,BR/AR ;YES, GET BR TOO + SV.BR_AR,AR_0S ;SAVE BR + AR0-8_FE ;NOW SAVE 10-BIT REGS + ARX_AR (AD),AR0-8_SC ;FE TO ARX, SC TO AR + ARR_ARL,ARL_ARX (ADX), ;FE IN ARL, SC IN ARR + ARX_VMA HELD ;GET VMA WHICH FAILED + SV.SC_AR,AR_ARX, ;HOLD SC & FE + GEN BR*2,SIGNS DISP ;TEST FOR PT DIR MATCH +=110 +PGRF1: +.IFNOT/ITSPAGE + SV.VMA_AR,AR_AR SWAP, ;GET SEC # TO AR32-35 + EA MOD DISP,J/PGRF2 ; SEC < 20? +.IF/ITSPAGE + SV.VMA_AR,J/PGRF2 ;AR, ARX HAVE VMA; BR HAS PFW +.ENDIF/ITSPAGE + +.IFNOT/PT DIR VAL BUG +;HERE TO WRITE PT DIR, & CLR 4 PAGE ENTRIES + + AR_0S,COND/MBOX CTL,MBOX CTL/2, ;READY TO CLEAR EVEN PAIR + FE_P AND #,#/2,SC/SCAD ;GET WRITE REF BIT TO FE & SC + COND/MBOX CTL,MBOX CTL/33, ;CLR EVEN, WR DIR, SEL ODD + TIME/3T,FE_FE+SC,SC/SCAD; WR REF = 4 NOW + COND/MBOX CTL,MBOX CTL/10, ;CLR ODD, RESET NORMAL SELECT + TIME/3T,FE_FE+SC,AR_BR ;GET PFW BACK, WR REF = 10 + SC_# AND AR0-8,#/401 ;GET USER & PAGED REF BITS + AR0-8_FE OR SC ;COMBINE WITH WR REF BIT + SV.PFW_AR,BR/AR,AR_ARX,J/PGRF1 ;REJOIN MAIN PATH +.IF/PT DIR VAL BUG +;HERE IF NO PT DIR MATCH. MUST WRITE ZEROS INTO THE PAGE TABLE +;LOCATIONS THAT COME UNDER THIS DIR ENTRY, AND WRITE THE DIR ENTRY. +;BECAUSE THE PT DIR VAL BITS COME IN PAIRS +;(ONE FOR EACH 2K), AND THERE IS A HARDWARE BUG THAT SOMETIMES CONFUSES +;THE TWO BITS IN A PAIR, WE ARRANGE FOR THE TWO BITS ALWAYS TO HAVE +;THE SAME VALUE BY CLEARING BOTH SETS OF PAGE TABLE ENTRIES. + + ;FIRST CLR THE 4 P ADDRESSED + SV.VMA_AR,AR_1 LONG ;AR := 0, ARX := 1 + COND/MBOX CTL,MBOX CTL/2, ;READY TO CLEAR EVEN PAIR + ARX_ARX*4 ;ARX := 4 + COND/MBOX CTL,MBOX CTL/33,TIME/3T, ;CLR EVEN, WR DIR, SEL ODD + ARX_ARX*8 ;ARX := 40 + COND/MBOX CTL,MBOX CTL/10,TIME/3T, ;CLR ODD, RESET NORMAL SELECT + ARX_ARX*8 ;ARX := 400 + COND/MBOX CTL,MBOX CTL/2, ;READY TO CLEAR EVEN PAIR + ARX_ARX*8 ;ARX := 4000 + GEN ARX*SV.VMA,AD/XOR,VMA/AD ;SET UP VMA TO OTHER GROUP OF 4 P + GEN SV.PFW,SKP AD0 ;COMPENSATE FOR HARDWARE BUG +=0 EXEC REF,J/PTDC1 + USER REF,J/PTDC1 +PTDC1: COND/MBOX CTL,MBOX CTL/33,TIME/3T ;CLR EVEN, WR DIR, SEL ODD + COND/MBOX CTL,MBOX CTL/10,TIME/3T, ;CLR ODD, RESET NORMAL SELECT + AR_BR,FE_#,#/10 ;AR GETS PFW, FE GETS WRITE REF BIT +.IFNOT/ITSPAGE ;CORRECT THE PAGE FAIL CODE + SC_# AND AR0-8,#/401 ;SC GETS USER AND PAGED REF BITS + AR0-8_FE OR SC ;COMBINE WITH WR REF BIT + SV.PFW_AR,BR/AR ;STORE CORRECTED PFW + AR_SV.VMA ;NOW DO WHAT PGRF1 DOES + ARX_AR,AR_AR SWAP, ;GET SEC # TO AR32-35 + EA MOD DISP,J/PGRF2 ; SEC < 20? +.IF/ITSPAGE + AR_SV.VMA,ARX_SV.VMA,J/PGRF2 ;AR, ARX HAVE VMA; BR HAS PFW +.ENDIF/ITSPAGE + +.ENDIF/PT DIR VAL BUG + +.IFNOT/ITSPAGE + +;HERE TO TRACE PAGE POINTERS FOR THIS ADDRESS +;VMA WHICH FAILED IS IN ARX AND IN AR WITH THE HALVES SWAPPED +;PAGE FAIL WORD IS IN BR + +=01 +PGRF2: VMA_#+AR32-35,#/440, ;YES. + SIGNS DISP,J/PGRF3 ; USER REF? + VMA_#+AR32-35,#/460, ;NO + SIGNS DISP,J/PGRF3 +=101 +PGRF3: LOAD AR,EPT REF, ;GET SEC PTR FROM EPT + ARX_AR,FE_-1,J/SECPTR ;PAGE NO TO ARX0-8 + LOAD AR,UPT REF,ARX_AR,FE_-1 ;SEC PTR FROM UPT + +;HERE TO FIND PAGE MAP WITH SECTION POINTER + +SECPTR: AR_MEM,SC_#,#/9 ;GET SECTION POINTER + FE_FE AND AR0-8,BR/AR, ;COMBINE ACCESS BITS + ARL_0.M,AR0-3 DISP ;SPT INDEX IN ARR, DISP ON TYPE +=1001 AR_SV.BR,J/PFT ;NO ACCESS TO SECTION +SECIMM: AR_SHIFT,VMA_AR+CBR,J/PGRF5 ;IMMEDIATE +LDIND: VMA_AR+SBR,J/GTSPT ;SHARED SEC = INDRCT PAG + VMA_AR+SBR,AR_ARX ;INDRCT SEC. LOOK IN SPT + BR/AR,AR_BR,LOAD AR,PHYS REF ;CALL FOR SPT ENTRY + ARX_SHIFT,AR_MEM ;WORD IN PT TO ARX0-8 + AR_SHIFT,ARX_BR ;NEW SEC PTR ADDR TO AR + GEN # AND AR0-8,#/77,SKP SCAD NE, + VMA_AR +=0 LOAD AR,PHYS REF,J/SECPTR + AR_SV.BR,J/PFT ;TRAP, SEC MAP NOT IN CORE + +GTSPT: LOAD AR,PHYS REF ;GET PAGE TABLE ADDR + AR_MEM,J/SECIMM + +;HERE WITH PAGE NO OF PAGE TABLE IN AR, +; VIRTUAL PAGE NO WITHIN SECTION IN ARX0-8 + +PGRF5: GEN # AND AR0-8,#/77, ;IS PAGE TABLE IN CORE? + SKP SCAD NE +=0 LOAD AR,PHYS REF, ;GET CST ENTRY FOR PAGE TABLE + BR/AR,J/PGRF6 ;SAVE PAGE PTR ADDR IN BR + AR_SV.BR,J/PFT ;NOT IN CORE, PAGE FAIL TRAP +PGRF6: AR_MEM,FE_FE AND #,#/164 ;HERE IS CST FOR PAGE TABLE + AR_AR AND CSMSK,SKP P NE ;BEGIN CST UPDATE +=0 AR_SV.BR,J/PFT ;AGE TRAP, PT BEING SWAPPED + AR_AR OR PUR,STORE ;PUT CST WORD BACK + MEM_AR,VMA_BR + LOAD AR,PHYS REF ;GET PAGE MAP ENTRY + AR_MEM,FE_FE OR #,#/100 ;PAGE POINTER + ;HERE WITH PAGE MAP ENTRY IN AR +;FE HAS ACCUMULATED ACCESS BITS -- APWSC*4, S HAS BEEN CLEARED +;SC CONTAINS 9. + + FE_FE AND AR0-8,AR0-3 DISP, ;COMBINE PWSC, DISP ON TYPE + ARX_SV.VMA ;GET BACK SAVED VMA +=1001 AR_SV.BR,J/PFT ;0=NO ACCESS +LDIMM: ARL_SHIFT,FE_FE SHRT, ;1=IMMEDIATE, LOAD PT + ARX_ARX*2 COMP, ; GET -WR REF TO ARX03 + SC_1,J/LDPT ; READY TO TEST WR REF BIT + VMA_AR+SBR,J/LDSHR ;2=SHARED, GET SPT ENTRY + ARL_0.M,ARX_SHIFT,J/LDIND ;3=INDIRECT, LOOP + +;HERE TO GET SHARED PAGE POINTER OUT OF SPT + +LDSHR: LOAD AR,PHYS REF + AR_MEM,FE_FE OR #,#/100,J/LDIMM ;TREAT SPT ENTRY AS IMMED + +;HERE WITH IMMEDIATE PAGE NO IN AR TO LOAD INTO PT + +LDPT: GEN # AND AR0-8,#/77,SKP SCAD NE, ;PAGE IN CORE? + ARX_AR,AR_ARX*.25 ;GET -WR REF TO AR05 +=0 VMA_ARX+CBR,AR_ARX, ;PAGE IS IN CORE. GET CST + SC_P AND SC,J/GTCST ;-WR REF TO SC + AR_SV.BR,J/PFT ;PAGE NOT IN CORE + +;NOW GET CST ENTRY FOR THIS PAGE + +GTCST: LOAD AR,PHYS REF,ARX_AR SWAP, + SC_-SC,AR_1 ;SC=0 IF WR REF, ELSE -1 + GEN FE AND #,#/10,SKP SCAD NE, ;SKIP IF WRITABLE + BR/AR,MB WAIT ;GET CST ENTRY & BIT FOR TESTING +=0 GEN P AND SC,SKP SCAD NE, ;FAIL IF WRITING OR AGE=0 + AR_AR AND CSMSK,J/NOTWR ;STRIP OLD AGE FROM CST + TEST AR.BR,SKP CRY0, ;WRITABLE--SKIP IF CST WRITTEN + GEN #-SC,#/-1,BYTE DISP ; OR THIS IS WRITE REF +=110 FE_FE-#,#/4,J/STCST ;TEMPORARILY UNWRITABLE, SET S + AR_AR*BR,AD/OR, ;SET CST WRITTEN BIT + FE_FE OR #,#/4 ;SET SOFT BIT = WRITABLE +STCST: AR_AR AND CSMSK,SKP P NE ;CLEAR OLD AGE, TEST IT +=0 +NOTWR: AR_SV.BR,J/PFT ;WRITE OR AGE TRAP + AR_AR OR PUR,STORE ;SET USE BITS, STORE BACK CST + MB WAIT,VMA_SV.VMA, ;RELOAD VMA FOR ORIGINAL REF + AR_SV.VMA,SC_1 ;READY TO TEST VMA USER + GEN P AND SC,SKP SCAD NE, ;TEST VMA USER + ARL_ARXL.M,ARR_0.M, ;PHYS PAGE# TO ARL, APWSC0 TO SC + SC_FE,ARX_AR (AD) ; MAP BIT TO ARX +=0 P_P OR SC#,EXEC REF,J/WRHPT ;BUILD PT ENTRY, CLEAR VMA USER + P_P OR SC#,USER REF ; OR SET USER, AS NECESSARY +WRHPT: WR PT ENTRY,FE_#,#/10,AR_ARX*4 ;UPDATE HARDWARE TABLE + +.IF/ITSPAGE + +;HERE TO START HACKING PAGE MAP +;AR, ARX HAVE VMA. BR HAS PFW. +;AR, ARX, BR, FE, SC, SV.VMA, SV.PFW HAVE BEEN STORED. + +PGRF2: ARL_0S,SIGNS DISP ;SKIP ON PFW BIT 0 (USER MODE) +=101 AR_ARX (ADX),ARX_AR (AD), ; WILL HAVE FOR SHIFT + SC_#,#/25., ;SC GETS SHIFT AMOUNT FOR PG TBL INDEX + AR18-21 DISP,J/PGEXRF ;DISPATCH ON VMA 2.9 FOR DBR SELECT + AR_ARX (ADX),ARX_AR (AD), ; WILL HAVE FOR SHIFT + SC_#,#/25., ;SC GETS SHIFT AMOUNT FOR PG TBL INDEX + AR18-21 DISP,J/PGUSRF ;DISPATCH ON VMA 2.9 FOR DBR SELECT +=0111 +PGEXRF: FE_AR0-8,AR_SHIFT,ARX_DBR4,J/RDDBR ;ARR GETS INDEX INTO ITS PAGE TABLE. + FE_AR0-8,AR_SHIFT,ARX_DBR3,J/RDDBR0 ; AR0 TELLS WHICH HALFWORD. +=0111 ; FE 1.5 GETS WRITE REF BIT. +PGUSRF: FE_AR0-8,AR_SHIFT,ARX_DBR1,J/RDDBR ; ARX GETS ONE OF FOUR DBR'S + FE_AR0-8,AR_SHIFT,ARX_DBR2,J/RDDBR0 ; DEPENDING ON EXEC/USER AND VMA 2.9. + +;HERE TO PICK UP ITS PAGE TABLE ENTRY + +RDDBR0: ARX_ARX-CN100 ;COMPENSATORY CROCK +RDDBR: SC_AR0-8,AR_BR,BR/AR ;SC _ 1/2 WD BIT, BR _ PTW INDEX + VMA_ARX+BR,SC_SC AND #,#/400 ;SET UP VMA BEFORE PHYS REF + ;(BUG IN MCL BOARD: MCL USER EN) + LOAD AR VIA RPW,BR/AR,PHYS REF, ;BR NOW HAS PFW AGAIN. + GEN SC,SKP SCAD NE ;FETCH PTW, SKIP ON HALF. +=0 + AR_MEM,CLR ARX,SC_#,#/0,J/RDBRLH ;SC GETS 0 FOR LEFT HALF, + AR_MEM,CLR ARX,SC_#,#/18.,J/RDBRRH ; 18. FOR RIGHT HALF +RDBRLH: AR_AR*LH.AGE,AD/ANDCB, ;AND OUT APPROPRIATE AGE BITS, + STORE,J/PACCDS ; AND STORE BACK +RDBRRH: AR_AR*RH.AGE,AD/ANDCB, + STORE,J/PACCDS + +;HERE TO DETERMINE ACCESS ALLOWED BY ITS PAGE TABLE ENTRY + +PACCDS: MEM_AR,ARL_SHIFT.C,ARR_0.C, ;GET PAGE TABLE HALFWORD IN ARL, + SC_1,SH DISP ; CLEAR ARR, DISPATCH ON ACCESS +=0011 + SC_PF.PNA,AR_BR,J/PFT69 ;00 NO ACCESS + SC_#,#/PPRO,AR_SHIFT,J/PFWLOS ;01 READ ONLY ;AR GETS SHIFTED + SC_#,#/PPRWF,AR_SHIFT,J/PFWLOS ;10 R/W FIRST ; FOR KL-10 SIZE + SC_#,#/PPRW,AR_SHIFT,J/PGSTO ;11 READ/WRITE ; PAGES (.5K) + +PFWLOS: GEN FE AND #,#/20,SKP SCAD NE ;LOSE IF WRITE ATTEMPT +=0 +PGSTO: SCADA/#,SCADB/AR0-8,SCAD/AND, ;CLEAR OUT ACCESS AND AGE BITS + AR0-8_SCAD#,#/37, + J/PGSTO1 + SC_PF.ILW,AR_BR ;WRITE INTO READ ONLY OR R/W/F LOSES +PFT69: P_SC#,ARX_SV.BR ;SET PAGE FAIL CODE + SV.PFW_AR,AR_ARX,J/PFT ;GO TAKE PAGE FAULT + +;HERE TO WRITE TWO KI-10 PAGE MAP ENTRIES + +PGSTO1: SCADA/AR0-5,SCADB/SC,SCAD/OR, ;OR IN APPROPRIATE KI-10 + P_SCAD#,ARX_SV.VMA ; STYLE ACCESS BITS + GEN ARX*CN1000,AD/ANDCB,VMA/AD ;VMA ADDRESS FOR LOW HALF PAGE + GEN SV.PFW,SKP AD0 ;SKIP IF USER REFERENCE +=0 EXEC REF,J/PGSTO2 ;FIX IT UP (BUG IN MCL BOARD + USER REF,J/PGSTO2 ; HAVING TO DO WITH PXCT) +PGSTO2: WR PT ENTRY,ADA/AR,AD/A+XCRY, ;WRITE IT, THEN BUMP ARL + GEN CRY18,AR/AD ; FOR HIGH .5K ENTRY + GEN ARX*CN1000,AD/OR,VMA/AD ;VMA ADDRESS FOR HIGH HALF PAGE + GEN SV.PFW,SKP AD0 ;SKIP IF USER REFERENCE +=0 EXEC REF,J/PGSTO3 ;FIX IT UP (BUG IN MCL BOARD + USER REF,J/PGSTO3 ; HAVING TO DO WITH PXCT) +PGSTO3: WR PT ENTRY,AR_ARX*4,FE_#,#/10 ;WRITE 2ND PTW. SET UP FE AND S +.ENDIF/ITSPAGE + ;HERE WHEN MAP INFO WRITTEN INTO HARDWARE PAGE TABLE +; WE NOW NEED ONLY RESTORE THE REGISTERS WE HAVE USED, AND RESTART THE +; MEMORY REFERENCE WHICH FAILED, RETURNING TO THE MICROINSTRUCTION +; WHICH WAITS FOR ITS COMPLETION. (EXCEPT FOR MAP) +; THIS SCREWING AROUND WITH FE_EXP,FE_-SC-1 ETC. LOOKS USELESS, +; BUT IT IS NECESSARY BECAUSE THESE KLUDGIFEROUS REGISTERS HAVE 11 +; BITS, EVEN THOUGH YOU CAN ONLY READ 9 OF THEM. THE HARDWARE FORCES +; THE TWO HIGHEST BITS TO BE IDENTICAL, BUT WE WANT TO FORCE THE THREE +; HIGHEST BITS TO BE IDENTICAL. AS FAR AS I KNOW, THE ONLY WAY TO +; READ THOSE TWO EXTRA BITS IS VIA SKIP/SCAD0 OR SKIP/SC0. + +.IF/MAP + GEN FE AND S,SKP SCAD NE, ;TEST FOR MAP INSTR + AR_SV.SC +=0 +.IFNOT/MAP + AR_SV.SC +.ENDIF/MAP + SC_EXP,FE_EXP,SKP AR0, ;RESTORE FE + AR_AR SWAP,ARX_SV.BR,J/PGRST1 +.IF/MAP + AR_SV.VMA,ARX_SV.VMA,J/COMPEA ;*MAP* RESTART FROM AREAD +.ENDIF/MAP +=0 +PGRST1: SC_EXP,SKP AR0, ;RESTORE SC + AR_ARX,ARX_SV.AR,J/PGRST2 + FE_-SC-1,J/PGRST1 ;MAKE FE NEG +=0 +PGRST2: BR/AR,AR_ARX,ARX_SV.ARX,J/PGRST3 ;RESTORE BR AND AR AND ARX + BR/AR,AR_ARX,ARX_SV.ARX,SC_-SC-1 ;MAKE SC NEG + +PGRST3: REQ SV.VMA ;RESTART REQUEST THAT FAILED + SET ACCOUNT EN,RETURN0 ;RESTART MICROINSTRUCTION THAT FAILED + + +;HERE ON A TRAP CONDITION DETECTED BY REFILL LOGIC +;AR CONTAINS SAVED BR + +;IF WE PAGE FAULTED ON THE FETCH OF THE INSTRUCTION IMMEDIATELY +;AFTER A PI CYCLE, CON INT DISABLE IS STILL ON BECAUSE THE NICOND +;THAT OUGHT TO HAVE CLEARED IT DIDN'T GET CLOCKED. SO CLEAR IT +;NOW. IF PFAIL.PIHACK, COULD HANG AT WGRANT BECAUSE PI BOARD +;THINKS INTERRUPTS ARE ENABLED BUT CON BOARD DOESN'T. IF NO +;PFAIL.PIHACK, ONLY LOSS IS THAT INTERRUPT WON'T PREEMPT PG FLT. + +PFT: CLR INTRPT INH ;CLEAR CON INT DISABLE + BR/AR,VMA_SV.VMA, ;RESTORE BR & VMA + SR DISP,J/CLEAN ;TAKE TRAP + .IFNOT/KLPAGE +.TOC "KI-MODE PAGE FAIL HANDLING" + +2377: CLR ACCOUNT EN,FORCE AR-ARX,J/PFSAVE +1777: CLR ACCOUNT EN,FORCE AR-ARX ;DON'T CHARGE PAGE FAIL TO USER +PFSAVE: SV.AR_AR,AR_ARX ;PRESERVE AR, ARX + SV.ARX_AR,SR DISP,J/CLEAN ;NOW CHECK FOR CLEANUP REQUIRED + +.ENDIF/KLPAGE +;HERE ON PAGE FAIL OR INTERRUPT WHICH REQUIRES CLEANUP IN ORDER +; TO BE CORRECTLY RESTARTABLE AFTER SERVICE... + +=1*0000 +CLEAN: FE_#,#/37,SKP INTRPT,J/PGF1 ;HERE FOR INTRPT OR PGF? + +.IF/EIS +;(1) HERE ON EDIT SOURCE FAIL +=0001 AR_SRCP,SR_0,J/BACKS ;BACK UP SRC POINTER +.IF/DECIMAL +;(2) HERE ON ANY FAILURE IN DECIMAL TO BINARY +=0010 AR_BR LONG,SR_1,J/D2BPF ;GET ACCUMULATED BINARY + +;(3) HERE ON DST FAIL IN BINARY TO DECIMAL FILL +=0011 AR_DLEN COMP,SR_#,#/4,J/B2DFPF +.ENDIF/DECIMAL +;(4) HERE ON EDIT DST FAIL WITH NO SRC POINTER UPDATE +=0100 AR_DSTP,SR_0,J/BACKD ;BACK UP DST POINTER ONLY + +;(5) HERE ON EDIT DST FAIL AFTER UPDATING SRC POINTER +=0101 AR_DSTP,SR_1,J/BACKD ;BACK UP DST, THEN SRC +.IF/DECIMAL +;(6) HERE ON DESTINATION FAILURE IN BINARY TO DECIMAL +=0110 AR_DSTP,SR_BDT,J/BACKD ;BACK UP DST, THEN SAVE FRACTION +.ENDIF/DECIMAL +.ENDIF/EIS +;(7) HERE ON BLT FAILURE +=0111 +.IF/KLPAGE + ARX_SV.ARX,J/BLTPF ;GET DEST ADDR AGAIN +.IFNOT/KLPAGE +BLTPF: AR_ARX+BR,SR_0,J/BLTPF1 ;CURRENT SRC ADDR +.ENDIF/KLPAGE +.IF/EIS +.IF/DECIMAL +;(10) HERE ON TRANSLATION FAILURE IN BINARY TO DECIMAL +=1000 AR_BR LONG,SR_0,J/B2DPF ;GET BINARY FRACTION +.ENDIF/DECIMAL + +;(11) HERE ON SRC FAILURE IN COMPARE OR MOVE STRING +=1001 AR_DLEN,SR_1,J/STRPF ;PUT LENGTHS BACK, THEN BACK SRC + +;(12) HERE ON DST FAILURE IN COMPARE OR MOVE STRING +=1010 AR_DLEN,SR_#,#/4,J/STRPF + +;(13) HERE ON DST FAILURE AFTER UPDATING SRC IN COMPARE OR MOVE +=1011 AR_DSTP,SR_SRC,J/BACKD ;BACK DST, THEN HANDLE AS SRC FAIL + +;(14) HERE ON DST FILL FAILURE IN MOVRJ +=1100 AR_DLEN,SR_#,#/4,J/STRPF4 +.ENDIF/EIS +.IF/KLPAGE +.IF/MAP +;(15) HERE ON PAGE FAILURE IN MAP INSTRUCTION. RETURN PAGE FAIL WORD +=1101 AR_SV.PFW,J/IFSTAC ;RETURN PFW IN AC +.ENDIF/MAP +.ENDIF/KLPAGE + +;(16) LISP?? + +;(17) HERE ON PAGE FAIL ON FETCH OF INSTRUCTION AFTER A JRSTF. +; DOING AN ABORT INSTR WOULD SCREW UP THE FLAGS, BECAUSE +; THE NICOND THAT ADVANCES THE FLAGS (CYC_REQ, REQ_0) +; WAS NOT CLOCKED. SO WE FAKE ONE UP NOW. +=1111 VMA/PC,DISP/NICOND,#/0,J/JRSTFC += ;END OF 'CLEAN' DISPATCH TABLE + +;SECOND INST FOR JRSTF CLEANUP +=1111 +JRSTFC: PC_VMA,SR_0,J/CLEAN ;DISP/NICOND CLOBBERED PC + ;HERE ON ANY PAGE FAILURE OR PI REQUEST IN LONG INSTRUCTIONS +; SKIP IF PI REQUEST, WHICH TAKES PRIORITY + +.IF/KLPAGE +=0 +PGF1: MB WAIT,VMA_#,#/500,J/PGF2 + SET ACCOUNT EN,J/TAKINT ;CLEANUP DONE, SERVE INTRPT +PGF2: AR_SV.PFW,SKP PI CYCLE,J/PGF4 ;GET BACK PAGE FAIL WORD +.IFNOT/KLPAGE +=0 +PGF1: GET ECL EBUS,CLR SC, + PF DISP,J/PGF2 + SET ACCOUNT EN,J/TAKINT ;HERE TO SERVE INTRPT, DO IT +=1100 +PGF2: +=01 AR_SV.AR,FE_FE-1, ;AR PARITY ERROR + SKP RPW,J/PGF6 ;DO WE NEED TO RESTART RPW? +=10 VMA_VMA HELD,MAP,SC_FE ;ARX PARITY ERROR, PF CODE 37 +PGF3: MB WAIT,VMA_#,#/500 + AR_EBUS REG ;READ PAGE FAIL WORD + REL ECL EBUS + P_P OR SC,SKP PI CYCLE ;STUFF ERROR CODE IF PARITY +.ENDIF/KLPAGE +=00 +PGF4: ARX_AR,AR_VMA HELD,SC_#,#/13., ;READY TO COMBINE PF WORD + CALL,J/ROTS ; WITH ADDRESS + SV.IOPF_AR,J/IOPGF ;SAVE IO PG FAIL WORD +=11 +.IFNOT/PFAIL.PIHACK +.IFNOT/LPM.SPM + AR_SHIFT,STORE,UPT REF ;PUT PAGE FAIL WORD AT 500 +.IF/LPM.SPM + AR_SHIFT,STORE,EPT REF ;STORE PFW AT 500 + UPFW_AR ;ALSO IN LPM/SPM VARIABLES +.ENDIF/LPM.SPM +.IF/PFAIL.PIHACK + MQ_SHIFT,AR_1,GEN CRY18, ;SAVE PAGE FAIL WORD IN MQ + ARX/AD,SC_#,#/8 ; AND GENERATE MAGIC BITS +=00 AR_SHIFT,REQ EBUS,CALL,J/WGRANT ;GOBBLE DOWN EBUS +=11 CONO PI ;TURN OFF PI SYSTEM + REL EBUS ;RELEASE EBUS +.IFNOT/LPM.SPM + AR_MQ,STORE,UPT REF +.IF/LPM.SPM + AR_MQ,STORE,EPT REF ;STORE PFW AT 500 + UPFW_AR ;AND IN LPM/SPM VARIABLES +.ENDIF/LPM.SPM +.ENDIF/PFAIL.PIHACK + ABORT INSTR ;RECOVER TRAP FLAGS, IF ANY + FIN STORE,AR_PC, + VMA_VMA+1,STORE ;STORE OLD PC AT 501 +.IFNOT/KLPAGE + REL ECL EBUS +.ENDIF/KLPAGE +.IFNOT/LPM.SPM + FIN STORE,VMA_VMA+1,LOAD AR ;GET NEW PC FROM 502 +.IF/LPM.SPM + MEM_AR,VMA_VMA+1 ;DON'T CHANGE TO FIN STORE! + LOAD AR,EPT REF +.ENDIF/LPM.SPM + SET ACCOUNT EN,J/NEWPC + +;HERE ON PAGE FAIL DURING PI CYCLE + +IOPGF: SET IO PF ;TROUBLE... + SET ACCOUNT EN,J/PIDONE + +.IFNOT/KLPAGE +;HERE ON PARITY ERROR IN AR. SKIP IF READ-PAUSE-WRITE IN PROGRESS +=0 +PGF6: VMA_VMA HELD,MAP, ;AR PARITY ERROR + SC_FE,J/PGF3 ;PF CODE 36 + STORE,J/PGF6 ;COMPLETE CYCLE, WITH GOOD PAR +.ENDIF/KLPAGE + .TOC "PAGE FAIL/INTERRUPT CLEANUP FOR SPECIAL INSTRUCTIONS" + +;HERE ON BLT PAGE FAIL + +.IF/KLPAGE +BLTPF: AR_ARX+BR,SR_0 ;CURRENT SRC ADDR +.ENDIF/KLPAGE +BLTPF1: AR_ARX (AD),ARL_ARR +PGFAC0: AC0_AR,SR DISP,J/CLEAN ;BEGIN NORMAL PF WORK + +.IF/EIS +;HERE ON VARIOUS CASES OF STRING/EDIT FAILURE + +BACKS: P_P+S + SRCP_AR,SR DISP,J/CLEAN ;RE-DISPATCH FOR MORE + +BACKD: P_P+S + DSTP_AR,SR DISP,J/CLEAN + +.IF/DECIMAL +D2BPF: AC3_AR,AR_0S,SC_#,#/35. ;PUT AWAY HIGH BINARY + AR_SHIFT,ARX_-SLEN ;LOW TO AR, REMAINING LEN TO ARX + AC4_AR,AR_ARX,J/STRPF2 ;PUT LOW AWAY + +B2DFPF: AR_AR*T0,AD/OR,J/B2DPF2 + +B2DPF: AC0_AR,AR_ARX ;HIGH FRACTION TO AC + AC1_AR ;LOW TO AC1 + AR_AC3 ;GET FLAGS +B2DPF2: AR_AR*SLEN,AD/A-B,J/STRPF3 ;REBUILD FLAGS+LEN +.ENDIF/DECIMAL + +STRPF: BR/AR,AR_-SLEN,SKP AR0 ;WHICH IS LONGER? +=0 +STRPF1: AC3_AR,AR_AR+BR,J/STRPF2 ;SRC LONGER + ARX_AR,AR_AR*SFLGS,AD/OR ;DST. BUILD SRC LEN+FLAGS + AC0_AR,AR_ARX-BR ;THAT'S AWAY, MAKE DST LEN +STRPF3: AC3_AR,SR DISP,J/CLEAN ;OK, NOW BACK UP SRC IF REQ'D + +STRPF2: AR_AR*SFLGS,AD/OR,J/PGFAC0 + +STRPF4: BR/AR,AR_SLEN COMP,SKP AR0,J/STRPF1 +.ENDIF/EIS diff --git a/src/ucode/its.9 b/src/ucode/its.9 new file mode 100755 index 00000000..89d54b2c --- /dev/null +++ b/src/ucode/its.9 @@ -0,0 +1,14 @@ +.TOC "MICROCODE CONDITIONAL ASSEMBLY PARAMETERS FOR ITS" + +.SET/ITSPAGE=1 ;ITS-STYLE PAGING +.SET/MAP=0 ;NO MAP INSTRUCTION +.SET/PFAIL.PIHACK=1 ;PI OFF ON PAGE FAILURE +.SET/JRSTON=1 ;JRST 17, TURNS ON PI THEN DOES JRST 2, +.SET/LPM.SPM=1 ;LPMR AND SPM INSTRUCTIONS +.SET/XCTR=1 ;XCTR INSTRUCTIONS (PXCT AND PXCTI) +.SET/EIS=0 ;NO STRING STUFF FOR NOW +.SET/DECIMAL=0 ;NO DECIMAL STUFF FOR NOW +.SET/CIRC=1 ;WINNING CIRC INSTRUCTION +.SET/MVSQZ=0 ;RANDOM MVSQZ INSTRUCTION +.SET/KLPAGE=1 ;U CODE CONTROLS PAGE REFILLS +.SET/NXT.INSTR.BITES=0 ;FIXED IN REV 9? diff --git a/src/ucode/jpc.4 b/src/ucode/jpc.4 new file mode 100755 index 00000000..f3aa3953 --- /dev/null +++ b/src/ucode/jpc.4 @@ -0,0 +1,6 @@ +.TOC "PARAMETER FILE FOR SINGLE JPC FEATURE" + +.SET/JPC.RING=0 +.SET/JPC=1 +;.SET/NXT.INSTR.BITES=0 ;CAN'T RUN WITH THIS=1, HAS PF GTR 6 TICKS LOSSAGE +;ABOVE COMMENTED OUT SINCE IT IS NOW THE DEFAULT AND PROVOKES A CRUFTY WARNING diff --git a/src/ucode/jpcr.3 b/src/ucode/jpcr.3 new file mode 100755 index 00000000..2a16f1b4 --- /dev/null +++ b/src/ucode/jpcr.3 @@ -0,0 +1,5 @@ +.TOC "PARAMETER FILE FOR RING OF 16 JPC'S FEATURE" + +.SET/JPC.RING=1 +.SET/JPC=1 + \ No newline at end of file diff --git a/src/ucode/jpctst.2 b/src/ucode/jpctst.2 new file mode 100755 index 00000000..79037156 --- /dev/null +++ b/src/ucode/jpctst.2 @@ -0,0 +1,4 @@ +.TOC "PARAMETER FILE FOR TESTING SINGLE JPC FEATURE" + +.SET/JPC TEST=1 + \ No newline at end of file diff --git a/src/ucode/lisp.18 b/src/ucode/lisp.18 new file mode 100755 index 00000000..68b93e7a --- /dev/null +++ b/src/ucode/lisp.18 @@ -0,0 +1,126 @@ +.TOC "LISP INSTRUCTIONS" + +.IF/LISP +;;; MARK: LSPGCM A,FOO +;;; LISP GARBAGE COLLECTION MARK INSTRUCTION. +;;; IF THE GCSTBR IS NOT SET UP, BEHAVES AS A UUO (OPCODE 070). +;;; OTHERWISE, MARKS THE ITEM IN A IF POSSIBLE, THEN RETURNS +;;; TO ONE OF SEVERAL PLACES: +;;; MARK-1 BOTH CAR AND CDR NEED MARKING (CAR IN A, CDR IN A+1) +;;; MARK ONE OF CAR OR CDR NEED MARKING (ITEM IN A) +;;; MARK+1 ITEM ALREADY MARKED, OR NOT MARKABLE +;;; FOO+N BIT 4.8 WAS SET IN GCST TABLE (N=BITS 4.3-4.1), +;;; INDICATING SOMETHING FUNNY LIKE A SYMBOL OR A SAR. + +;TO HELP SEE WHAT'S GOING ON, ;AR ARX BR BRX MQ +; REGISTER CONTENTS AFTER EACH STEP ARE SHOWN ;------ ------- ------- ------- ------- + +;LSPGCM: BR/AR,MQ_AR,AR_GCSTBR,SKP AD NE,J/LGCM0 ;START OF GC MARK INSTR +=0 +LGCM0: AR_BR,J/UUO ;GCSTBR NOT SET UP => UUO + SC_#,#/44-SEGLOG,BR/AR,ARX_AC0,AR_0.C ;0 ITEM GCSTBR EFFADR + ARX_SHIFT,AR_ARX (AD) ;ITEM SEG# GCSTBR EFFADR + VMA_ARX+BR,LOAD ARX,AR_SHIFT ;WD#_33 -LOAD- EFFADR + SC_AR0-8 AND #,#/37,BR/AR,AR_0.C ;0 -LOAD- WD#_33 EFFADR + ARX_MEM,AR0-8_#,#/400 ;SETZ TBLENT WD#_33 EFFADR + SKP ARX0,SC_#-SC,#/44,BRX/ARX ;SETZ TBLENT WD#_33 TBLENT EFFADR +=0 I FETCH,J/NOP ;NOT MARKABLE => NEXT INSTRUCTION + AR_ARX (AD),ARX_AR ;TBLENT SETZ WD#_33 TBLENT EFFADR + AR_0S,FE_AR0-8 AND #, + #/207,SKP SCAD NE ;0 SETZ WD#_33 TBLENT EFFADR +;HERE FOR MARKABLE NON-FUNNY THINGS +=0 MQ_SHIFT,AR_BRX,ARX_BR, + SC_#,#/SEGLOG-5,J/LGCM1 ;TBLENT WD#_33 TBLENT MARKBIT +;HERE FOR MARKABLE FUNNY THINGS (SYMBOLS, ETC.) + VMA_MQ,FE_FE-#,#/201,BYTE DISP +=110 +LGCM3: VMA_VMA+1,FE_FE-1,BYTE DISP,J/LGCM3 ;LOOP TO GENERATE EFFADR+N + FETCH,J/NOP + +LGCM1: ARX_SHIFT,AR_MQ ;MARKBIT BITSADR TBLENT + BR/AR,VMA_ARX,LOAD AR ;-LOAD- MARKBIT TBLENT + AR_MEM ;BITS MARKBIT TBLENT + AD/AND,ADA/AR,ADB/BR,SKP AD NE +=0 I FETCH,J/NOP ;ALREADY MARKED + AR_AR*BR,AD/ANDCB,STORE ;BITS\MARKBIT TBLENT + MEM_AR,AR_BRX ;TBLENT + GEN # AND AR0-8,#/GCBCDR,SKP SCAD NE +=0 I FETCH,J/NOP ;DON'T MARK THROUGH + VMA_AC0,LOAD ARX ;TBLENT -LOAD- + ARX_MEM,VMA/PC,GEN # AND AR0-8, + #/GCBCAR,SKP SCAD NE ; CARCDR +=0 ARL_0.S,ARR_ARXR,J/LGCM2 ;ONLY MARK CDR + ARL_0.S,ARR_ARXR,VMA_VMA-1 ;0,,CDR CARCDR + ARX_AR (AD),SKP AD NE,ARR_0.S,ARL_ARXL ;0,,CAR 0,,CDR +=0 REFETCH,AR_AR SWAP,J/STAC ;CDR IS NIL => MARK ONLY CAR + ARX_AR (AD),SKP AD NE,AR_ARX ;0,,CDR 0,,CAR +=0 +LGCM2: REFETCH,J/STAC ;CAR IS NIL => MARK ONLY CDR + AC1_AR,AR_ARX + AR_AR SWAP,FETCH,J/STAC ;CDR IN AC1, CAR IN AC0, RET TO INST-1 + +;;; SWEEP: LSPGCS A,N +;;; LISP GARBAGE COLLECTION SWEEP INSTRUCTION. +;;; IF THE GCSTBR IS NOT SET UP, BEHAVES AS A UUO (OPCODE 071). +;;; OTHERWISE, SWEEPS UP A SECTION OF MEMORY. +;;; A/ AOBJN POINTER TO REGION OF MEMORY TO SWEEP: <# CELLS>,, +;;; THE CELLS ARE N WORDS LONG. +;;; A+1/ POINTER TO NEXT WORD OF MARK BITS TO USE. A BIT=0 => MARKED. +;;; A+2/ FREELIST (TO BE ADDED TO THE FRONT OF). +;;; A+3/ COUNT OF RECLAIMED CELLS, TO BE INCREMENTED. +;;; THE INSTRUCTION OPERATES IN GROUPS OF 40 WORDS (ONE WORD OF MARK BITS). +;;; IT CHECKS FOR INTERRUPTS ONLY THAT OFTEN, AFTER CHECKPOINTING ITSELF +;;; BACK INTO THE FOUR AC'S. IF A PAGE FAULT OR OTHER MEMORY ERROR OCCURS, +;;; IT WILL RESTART CORRECTLY AT THE BEGINNING OF THE GROUP OF 40 WORDS. + + +;LSPGCS: BR/AR,SC_EA,AR_GCSTBR,SKP AD NE,J/LGCS0 ;START OF GC SWEEP INSTR + +=0 +LGCS0: AR_BR,J/UUO ;MAYBE CRAP OUT AS UUO + AR_BR+1000000 ;BR GETS 1,,N (FOR BUMPING AOBJN PTR) + ARX_AC2,BR/AR ;WE STANDARDLY KEEP THE FREELIST IN BRX, + BRX/ARX,VMA_AC1,LOAD ARX ; THE AOBJN PTR IN ARX, THE COUNT IN MQ, + AR_AC3,FE_SC ; AND THE MARK BITS POINTED TO BY AC1 + MQ_AR,CLR AR,SC_#,#/40,J/LGCS1 ; IN AR (CONSTANTLY SHIFTED OVER). + +=010 +LGCS7: NXT INSTR ;DONE, NO INTERRUPT + NXT INSTR ;DONE, INTERRUPT PENDING +LGCS1: ARX_MEM,J/LGCS6 ;NOT DONE, NO INTERRUPT + FIN XFER,REFETCH,J/NOP ;NOT DONE, INTERRUPT PENDING += + +LGCS6: AR_SHIFT,ARX_AR (AD),SC_#,#/4 + ARX_AC0,AR_SHIFT,SH DISP,SC_#,#/-40,J/LGCS3 + +=0**0 +LGCS2: AR_AC1+1,VMA/AD,SKP ARX0,J/LGCS4 +LGCS3: AR_SHIFT,SH DISP,SC_FE+SC,SKP SCAD0,ARX_ARX+BR,J/LGCS2 + AR_AC1+1,VMA/AD,SKP ARX0,J/LGCS4 + AR_ARX (AD),ARX_AR += AR_BR,BR/AR + AR_BRX,ARX_BR,VMA_BR,BR/AR,BRX/ARX,STORE + MEM_AR,AR_MQ+1 + MQ_AR,AR_BRX,BRX/ARX,J/LGCS3 + +=0 +LGCS4: I FETCH,AC1_AR,AR_MQ,MQ_ARX,J/LGCS5 + LOAD ARX,AC1_AR,AR_MQ,MQ_ARX +LGCS5: AC3_AR,AR_BRX + AC2_AR,AR_MQ + AC0_AR + AD/0S,SIGNS DISP,SKP INTRPT,J/LGCS7 + +.ENDIF/LISP + +.TOC "LISP DEBUGGING INSTRUCTION" + +;;; LSPDBG A, +;;; PUTS STBR IN A, GCSTBR IN A+1 + +;LSPDBG: AR_GCSTBR,J/LSPDB1 + +LSPDB1: AC1_AR,I FETCH + AR_STBR,J/STAC + \ No newline at end of file diff --git a/src/ucode/lithp.2 b/src/ucode/lithp.2 new file mode 100755 index 00000000..8a8b4297 --- /dev/null +++ b/src/ucode/lithp.2 @@ -0,0 +1,4 @@ +.TOC "PARAMETER FILE FOR LISP MICROCODE" + +.SET/LISP=1 + \ No newline at end of file diff --git a/src/ucode/macro.43 b/src/ucode/macro.43 new file mode 100755 index 00000000..ba2e2e93 --- /dev/null +++ b/src/ucode/macro.43 @@ -0,0 +1,1264 @@ +.TOC "MACROS -- AC TRANSFERS" + +GEN AC0 "FMADR/AC0,ADB/FM,AD/B" +AR_AC0 "FMADR/AC0,ADB/FM,AD/B,AR/AD" +AR_AC1 "FMADR/AC1,ADB/FM,AD/B,AR/AD" +AR_AC2 "FMADR/AC2,ADB/FM,AD/B,AR/AD" +AR_AC3 "FMADR/AC3,ADB/FM,AD/B,AR/AD" +AR_AC4 "FMADR/AC4,ADB/FM,AD/B,AR/AD" + +AC0_AR "FMADR/AC0,COND/FM WRITE" +AC1_AR "FMADR/AC1,COND/FM WRITE" +AC2_AR "FMADR/AC2,COND/FM WRITE" +AC3_AR "FMADR/AC3,COND/FM WRITE" +AC4_AR "FMADR/AC4,COND/FM WRITE" + +ARX_AC0 "FMADR/AC0,ADB/FM,AD/B,ARX/AD" +ARX_AC1 "FMADR/AC1,ADB/FM,AD/B,ARX/AD" +ARX_AC2 "FMADR/AC2,ADB/FM,AD/B,ARX/AD" +ARX_AC3 "FMADR/AC3,ADB/FM,AD/B,ARX/AD" +ARX_AC4 "FMADR/AC4,ADB/FM,AD/B,ARX/AD" + +AR_-AC0 "FMADR/AC0,ADB/FM,ADA EN/0S,AD/A-B,AR/AD" +AR_AC0 COMP "FMADR/AC0,ADB/FM,AD/SETCB,AR/AD" +AR_AC1 COMP "FMADR/AC1,ADB/FM,AD/SETCB,AR/AD" +AR_AC1*2 "FMADR/AC1,ADB/FM,AD/B,AR/AD*2" +AR_AC3*2 "FMADR/AC3,ADB/FM,AD/B,AR/AD*2" + +GEN AR*AC0 "FMADR/AC0,ADB/FM,ADA/AR" +AR_AR*AC0 "FMADR/AC0,ADB/FM,ADA/AR,AR/AD" ;GENERAL BINARY OPERATION +AR_AR*AC1 "FMADR/AC1,ADB/FM,ADA/AR,AR/AD" + +AR_AC0+1 "ADA EN/0S,ADB/FM,FMADR/AC0,AD/A+B+1,AR/AD" +AR_AC1+1 "ADA EN/0S,ADB/FM,FMADR/AC1,AD/A+B+1,AR/AD" +ARX_AC0+1 "ADA EN/0S,ADB/FM,FMADR/AC0,AD/A+B+1,ARX/AD" +ARX_AC1+1 "ADA EN/0S,ADB/FM,FMADR/AC1,AD/A+B+1,ARX/AD" +ARX_-AC0 "ADA EN/0S,ADB/FM,FMADR/AC0,AD/A-B,ARX/AD" +ARX_AC0 COMP "ADB/FM,FMADR/AC0,AD/SETCB,ARX/AD" + +AR_XR "FMADR/XR,ADB/FM,AD/B,AR/AD" +AR_FM(VMA) "FMADR/VMA,ADB/FM,AD/B,AR/AD" +ARX_FM(VMA) "FMADR/VMA,ADB/FM,AD/B,ARX/AD" + .TOC "MACROS -- DATA PATH TRANSFERS AND SHIFTS" + +MQ_AR "SH/AR,MQ/SH" +MQ_ARX "SH/ARX,MQ/SH" +AR_MQ "ADA/MQ,AD/A,AR/AD" + +MQ_SHIFT "SH/SHIFT AR!ARX,MQ/SH" +AR_SHIFT "SH/SHIFT AR!ARX,AR/SH" +ARX_SHIFT "SH/SHIFT AR!ARX,ARX/SH" +MQ_AD "COND/REG CTL,MQ CTL/AD,MQ/MQM SEL" +MQ_AR (AD) "ADA/AR,AD/A,MQ_AD" +(MQ)*.25 "COND/REG CTL,MQ/MQM SEL,MQ CTL/MQ*.25" +(MQ)*2 "COND/REG CTL,MQ/MQ SEL,MQ CTL/MQ*2" + +AR_ARX "SH/ARX,AR/SH" +AR_ARX (ADX) "ADA EN/EN,AD/A,AR/ADX" +AR_ARX (AD) "ADA/ARX,AD/A,AR/AD" +ARX_AR "SH/AR,ARX/SH" +ARX_AR (AD) "ADA/AR,AD/A,ARX/AD" +BR_AR LONG "BR/AR,BRX/ARX" + +AR_AR*2 "ADA/AR,AD/A,AR/AD*2" +AR_AR*4 "ADB/AR*4,AD/B,AR/AD" +AR_AR*8 "ADB/AR*4,AD/B,AR/AD*2" +ARX_ARX*2 "ADA EN/EN,AD/A,ARX/ADX*2" +ARX_ARX*4 "ADB/AR*4,AD/B,ARX/ADX" +ARX_ARX*8 "ADB/AR*4,AD/B,ARX/ADX*2" +AR_AR*2 LONG "ADA/AR,AD/A,AR/AD*2,ARX/ADX*2" +AR_AR*4 LONG "ADB/AR*4,AD/B,AR/AD,ARX/ADX" +AR_AR*8 LONG "ADB/AR*4,AD/B,AR/AD*2,ARX/ADX*2" +AR_ARX*2 "ADA/ARX,AD/A,AR/AD*2" +AR_ARX*4 "ADB/AR*4,AD/B,AR/ADX" +MQ_MQ*2 "SPEC/MQ SHIFT,MQ/MQ*2" +AR_AR*.25 "ADA/AR,AD/A,AR/AD*.25" +AR_ARX*.25 "ADA/ARX,AD/A,AR/AD*.25" +AR_MQ*.25 "ADA/MQ,AD/A,AR/AD*.25" +AR_MQ*4 "ADA/MQ,AD/A*2,AR/AD*2" +ARX_ARX*.25 "ADA EN/EN,AD/A,ARX/ADX*.25" +MQ_MQ*.25 "SPEC/MQ SHIFT,MQ/MQ*.25" +(AR+ARX+MQ)*2 "ADA/AR,AD/A,AR/AD*2,ARX/ADX*2,(MQ)*2" +(AR+ARX+MQ)*.25 "ADA/AR,AD/A,AR/AD*.25,ARX/ADX*.25,(MQ)*.25" +AR_AR*.5 "ADA/AR,AD/A*2,AR/AD*.25" +ARX_ARX*.5 "ADA/EN,AD/A*2,ARX/ADX*.25" +AR_AR*.5 LONG "ADA/AR,AD/A*2,SPEC/AD LONG,AR/AD*.25,ARX/ADX*.25" + +AR_ARX COMP "ADA EN/EN,AD/SETCA,AR/ADX" +AR_BR COMP "ADB/BR,AD/SETCB,AR/AD" +ARX_BRX COMP "ADB/BR,AD/SETCB,ARX/ADX" +AR_BR COMP LONG "ADB/BR,AD/SETCB,AR/AD,ARX/ADX" +AR_MQ COMP "ADA/MQ,AD/SETCA,AR/AD" +ARX_AR*4 COMP "ADB/AR*4,AD/SETCB,ARX/AD" +ARX_ARX*2 COMP "ADA EN/EN,AD/SETCA,ARX/ADX*2" +MQ_BR COMP "ADB/BR,AD/SETCB,MQ_AD" +MQ_ARX COMP "ADA/ARX,AD/SETCA,MQ_AD" + AR_-AR "ADA EN/0S,ADB/AR*4,AD/A-B,AR/AD*.25" +AR_BR "ADB/BR,AD/B,AR/AD" +AR_BRX "ADB/BR,AD/B,AR/ADX" +ARX_BRX "ADB/BR,AD/B,ARX/ADX" +AR_BR LONG "ADB/BR,AD/B,AR/AD,ARX/ADX" +ARX_BR "ADB/BR,AD/B,ARX/AD" +AR_-BR "ADB/BR,ADA EN/0S,AD/A-B,AR/AD" +AR_-BRX "ADB/BR,ADA EN/0S,AD/A-B,AR/ADX" +ARX_-BRX "ADB/BR,ADA EN/0S,AD/A-B,ARX/ADX" +AR_BR*2 "ADB/BR*2,AD/B,AR/AD" +ARX_BRX*2 "ADB/BR*2,AD/B,ARX/ADX" +ARX_BRX*2+1 "ADA EN/0S,ADB/BR*2,AD/A+B+1,ARX/ADX" +AR_BR+1 "ADB/BR,ADA EN/0S,AD/A+B+1,AR/AD" +ARX_BR*2 "ADB/BR*2,AD/B,ARX/AD" +AR_BR*4 LONG "ADB/BR*2,AD/B,AR/AD*2,ARX/ADX*2" +AR_BR*.5 "ADB/BR*2,AD/B,AR/AD*.25" +AR_BR*.5 LONG "ADB/BR*2,AD/B,AR/AD*.25,ARX/ADX*.25" +AR_MQ*2 "ADA/MQ,AD/A,AR/AD*2" + +GEN AR "ADA/AR,AD/A" +GEN ARX "ADA/ARX,AD/A" +GEN ARX COMP "ADA/ARX,AD/SETCA" +GEN MQ "ADA/MQ,AD/A" +GEN BR*2 "ADB/BR*2,AD/B" +FORCE AR-ARX "ADB/AR*4,AD/B,AR/AD*.25,ARX/ADX*.25" + .TOC "MACROS -- ARITHMETIC" + +GEN AR+1 "ADA/AR,AD/A+1" +GEN AR-1 "ADA/AR,AD/A-1" +AR_AR+1 "ADA/AR,AD/A+1,AR/AD" +AR_AR-1 "ADA/AR,AD/A-1,AR/AD" +AR_AR+BR "ADA/AR,ADB/BR,AD/A+B,AR/AD" +ARX_AR+BR "ADA/AR,ADB/BR,AD/A+B,ARX/AD" +GEN AR*BR "ADA/AR,ADB/BR" +GEN AR+BR "ADA/AR,ADB/BR,AD/A+B" +GEN AR-BR "ADA/AR,ADB/BR,AD/A-B" +GEN AR-BR-1 "GEN AR*BR,AD/A-B-1" +AR_AR-BR "ADA/AR,ADB/BR,AD/A-B,AR/AD" +ARX_-AR-1 "ADA/AR,AD/SETCA,ARX/AD" +AR_AR-BR-1 "GEN AR*BR,AD/A-B-1,AR/AD" +ARX_AR+1 "ADA/AR,AD/A+1,ARX/AD" +ARX_AR-1 "ADA/AR,AD/A-1,ARX/AD" +ARX_ARX+1 "ADA EN/EN,AD/A+1,ARX/ADX" +ARX_ARX-1 "ADA EN/EN,AD/A-1,ARX/ADX" +ARX_ARX-1 (AD) "ADA/ARX,AD/A-1,ARX/AD" +AR_ARX-1 "ADA EN/EN,AD/A-1,AR/ADX" +ARX_BRX+1 "ADA EN/0S,ADB/BR,AD/A+B+1,ARX/ADX" +AR_ARX+BR "ADA/ARX,ADB/BR,AD/A+B,AR/AD" +ARX_ARX+BR "ADA/ARX,ADB/BR,AD/A+B,ARX/AD" +AR_ARX-BR "ADA/ARX,ADB/BR,AD/A-B,AR/AD" +GEN AR-AC3 "FMADR/AC3,ADB/FM,ADA/AR,AD/A-B" +AR_MQ+1 "ADA/MQ,AD/A+1,AR/AD" +MQ_MQ+1 "ADA/MQ,AD/A+1,MQ_AD" +AR_MQ-1 "ADA/MQ,AD/A-1,AR/AD" +AR_MQ-BR "ADA/MQ,ADB/BR,AD/A-B,AR/AD" +AR_MQ+AC0 "FMADR/AC0,ADB/FM,ADA/MQ,AD/A+B,AR/AD" +AR_MQ*AC1 "FMADR/AC1,ADB/FM,ADA/MQ,AR/AD" +AR_MQ*AC2 "FMADR/AC2,ADB/FM,ADA/MQ,AR/AD" +AR_MQ*AC3 "FMADR/AC3,ADB/FM,ADA/MQ,AR/AD" + +AR_AR*BR "ADA/AR,ADB/BR,AR/AD" +AR_ARX*BR "ADA/ARX,ADB/BR,AR/AD" +ARX_AR*BR "ADA/AR,ADB/BR,ARX/AD" +AR_2(AR*BR) "ADA/AR,ADB/BR,AR/AD*2" +AR_2(AR+BR) "AR_2(AR*BR),AD/A+B" +AR_2(AR-BR) "AR_2(AR*BR),AD/A-B" +AR_(AR+BR)*.25 "ADA/AR,ADB/BR,AD/A+B,AR/AD*.25" +AR_(AR-BR)*.25 "ADA/AR,ADB/BR,AD/A-B,AR/AD*.25" +AR_(AR+2BR)*.25 "ADA/AR,ADB/BR*2,AD/A+B,AR/AD*.25" +AR_(AR-2BR)*.25 "ADA/AR,ADB/BR*2,AD/A-B,AR/AD*.25" +GEN AR+2BR "ADA/AR,ADB/BR*2,AD/A+B" +GEN AR-2BR "ADA/AR,ADB/BR*2,AD/A-B" +ARX_ARX*BRX "ADA/AR,ADB/BR,ARX/ADX" +ARX_ARX+BRX "ARX_ARX*BRX,AD/A+B" +AR_ARX*BRX "ADA/AR,ADB/BR,AR/ADX" + +AR_AR*10 "ADA/AR,ADB/AR*4,AD/A+B,AR/AD*2" +ARX_ARX*5 "ADA/AR,ADB/AR*4,AD/A+B,ARX/ADX" +AR_BR+1000000 "AR/AD,AD/A+B,ADA EN/0S,ADB/BR,GEN CRY18" +AR_2(AR+1) "ADA/AR,AD/A+1,AR/AD*2" +AR_ARX*.25-AR-1 "ADB/AR*4,ADA/ARX,AD/A-B-1,AR/AD*.25" +AR_(ARX OR AR*4)*.25 "ADA/ARX,ADB/AR*4,AD/OR,AR/AD*.25" +ARX_ARX*-6 "ADA EN/EN,ADB/AR*4,AD/A-B,ARX/ADX*2" +ARX0_MQ35 "ADA/MQ,AD/A*2+1,ARX/ADX*.25" + .TOC "MACROS -- SCRATCH AC'S (BLOCK 7)" + +;PARITY ERROR DIAGNOSIS/RECOVERY INFORMATION + +.IFNOT/KLPAGE +SV.AR_AR "FMADR/#B#,FM#/160,COND/FM WRITE" ;AR SAVED +SV.ARX_AR "FMADR/#B#,FM#/161,COND/FM WRITE" ;ARX SAVED +AR_SV.AR "FMADR/#B#,FM#/160,AR_FM" +.ENDIF/KLPAGE +SV.IOPF_AR "FMADR/#B#,FM#/162,COND/FM WRITE" ;IO PAGE FAIL WORD + +T0 "FMADR/#B#,FM#/166" +T1 "FMADR/#B#,FM#/171" +T2 "FMADR/#B#,FM#/172" +E0 "FMADR/#B#,FM#/164" +E1 "FMADR/#B#,FM#/165" +SLEN "FMADR/#B#,FM#/170" ;MUST BE 170 +MSK "FMADR/#B#,FM#/167" +FILL "FMADR/#B#,FM#/173" +SFLGS "FMADR/AC0" +SRCP "FMADR/AC1" +DLEN "FMADR/AC3" +DSTP "FMADR/AC4" + +AR_FM "ADB/FM,AD/B,AR/AD" +AR_FM+1 "ADB/FM,ADA EN/0S,AD/A+B+1,AR/AD" +FM_AR "COND/FM WRITE" +ARX_FM "ADB/FM,AD/B,ARX/AD" + +.IF/INSTR.STAT +;ACCESS TO AC'S WHICH CONTROL TRACKS FEATURE +TRB "FMADR/#B#,FM#/176" +TRX "FMADR/#B#,FM#/177" +AR_TRB "TRB,AR_FM" +AR_AR+TRB "TRB,ADB/FM,ADA/AR,AD/A+B,AR/AD" +ARX_TRB "TRB,ARX_FM" +VMA_TRB "TRB,ADB/FM,AD/B,VMA/AD" +VMA_AR+TRB "TRB,ADB/FM,ADA/AR,AD/A+B,VMA/AD" +TRB_AR "TRB,FM_AR" +AR_TRX "TRX,AR_FM" +TRX_AR "TRX,FM_AR" +AR_TRX+1 "TRX,ADB/FM,ADA EN/0S,AD/A+B+1,AR/AD" +.ENDIF/INSTR.STAT + T0_AR "T0,FM_AR" +T1_AR "T1,FM_AR" +T2_AR "T2,FM_AR" +E0_AR "E0,FM_AR" +E1_AR "E1,FM_AR" +SLEN_AR "SLEN,FM_AR" +DLEN_AR "DLEN,FM_AR" +MSK_AR "MSK,FM_AR" +FILL_AR "FILL,FM_AR" +SRCP_AR "SRCP,FM_AR" +SFLGS_AR "SFLGS,FM_AR" +DSTP_AR "DSTP,FM_AR" + +AR_T0 "T0,AR_FM" +AR_AR+T0 "T0,ADB/FM,ADA/AR,AD/A+B,AR/AD" +AR_AR-T0 "T0,ADB/FM,ADA/AR,AD/A-B,AR/AD" +AR_AR*T0 "T0,ADB/FM,ADA/AR,AR/AD" +VMA_T0+1 "T0,ADB/FM,ADA EN/0S,AD/A+B+1,VMA/AD" +GEN AR*T0 "T0,ADB/FM,ADA/AR" +AR_T1 "T1,AR_FM" +AR_T2 "T2,AR_FM" +AR_AR+T1 "T1,ADB/FM,ADA/AR,AD/A+B,AR/AD" +ARX_T2 "T2,ARX_FM" +AR_SLEN "SLEN,AR_FM" +AR_SLEN+1 "SLEN,ADB/FM,ADA EN/0S,AD/A+B+1,AR/AD" +AR_SLEN COMP "SLEN,ADB/FM,AD/SETCB,AR/AD" +AR_-SLEN "SLEN,ADB/FM,ADA EN/0S,AD/A-B,AR/AD" +ARX_-SLEN "SLEN,ADB/FM,ADA EN/0S,AD/A-B,ARX/AD" +AR_AR*SLEN "SLEN,ADB/FM,ADA/AR,AR/AD" +AR_DLEN "DLEN,AR_FM" +AR_DLEN+1 "DLEN,ADB/FM,ADA EN/0S,AD/A+B+1,AR/AD" +AR_DLEN COMP "DLEN,ADB/FM,AD/SETCB,AR/AD" +AR_-DLEN "DLEN,ADB/FM,ADA EN/0S,AD/A-B,AR/AD" +AR_E0 "E0,AR_FM" +VMA_E0+1 "E0,ADB/FM,ADA EN/0S,AD/A+B+1,VMA/AD" +VMA_AR+E0 "E0,ADB/FM,ADA/AR,AD/A+B,VMA/AD" +VMA_AR+E0+1 "E0,ADB/FM,ADA/AR,AD/A+B+1,VMA/AD" +AR_E1 "E1,AR_FM" +VMA_AR+E1 "E1,ADB/FM,ADA/AR,AD/A+B,VMA/AD" +AR_AR+E1 "E1,ADB/FM,ADA/AR,AD/A+B,AR/AD" +GEN AR+E1 "E1,ADB/FM,ADA/AR,AD/A+B" +AR_AR*MSK "MSK,ADB/FM,ADA/AR,AR/AD" +ARX_AR*MSK "MSK,ADB/FM,ADA/AR,ARX/AD" +AR_FILL "FILL,AR_FM" +AR_SRCP "SRCP,AR_FM" +ARX_SRCP "SRCP,ARX_FM" +AR_SFLGS "SFLGS,AR_FM" +AR_AR*SFLGS "SFLGS,ADB/FM,ADA/AR,AR/AD" +AR_DSTP "DSTP,AR_FM" +ARX_DSTP "DSTP,ARX_FM" + .TOC "MACROS -- ITS AC BLOCKS USAGE TABLE" + +;ITS USES THE EIGHT ACCUMULATOR BLOCKS AS FOLLOWS: +; +;BLOCK 0 EXEC MODE ACCUMULATORS +;BLOCK 1 USER MODE ACCUMULATORS +;BLOCK 2 MUSIC REGISTERS (.IF/MUSIC) +; 0 MUSAOB AOBJN POINTER TO MUSIC DATA +; 1 MUSDEV DATAO INSTR TO MUSIC DEVICE +; 2 MUSMIN MINIMUM LENGTH MUSIC QUANTUM +; 3 MUSTIM TIME FOR NEXT INTERVAL +; 4 MUSBT1 BITS FOR NEXT FROBBING +; 5 MUSBT2 BITS FOR TIME AFTER THAT +; 6 CHDTIM TIME LEFT FOR CURRENT CHORD +; 7 CN7777 MUST CONTAIN 7777 (OCTAL) +; 10 V1BR BASE REG FOR VOICE TABLE 1 +; 11 V2BR BASE REG FOR VOICE TABLE 2 +; 12 V3BR BASE REG FOR VOICE TABLE 3 +; 13 V4BR BASE REG FOR VOICE TABLE 4 +; 14 V5BR BASE REG FOR VOICE TABLE 5 +; 15 V6BR BASE REG FOR VOICE TABLE 6 +; 16 UNUSED +; 17 UNUSED +;BLOCK 3 MUSIC REGISTERS (.IF/MUSIC) +; 0 V1CTR COUNTER FOR FROBBING VOICE 1 +; 1 V2CTR COUNTER FOR FROBBING VOICE 2 +; 2 V3CTR COUNTER FOR FROBBING VOICE 3 +; 3 V4CTR COUNTER FOR FROBBING VOICE 4 +; 4 V5CTR COUNTER FOR FROBBING VOICE 5 +; 5 V6CTR COUNTER FOR FROBBING VOICE 6 +; 6 UNUSED +; 7 UNUSED +; 10 V1TIM TIME BETWEEN VOICE 1 FROBBINGS +; 11 V2TIM TIME BETWEEN VOICE 2 FROBBINGS +; 12 V3TIM TIME BETWEEN VOICE 3 FROBBINGS +; 13 V4TIM TIME BETWEEN VOICE 4 FROBBINGS +; 14 V5TIM TIME BETWEEN VOICE 5 FROBBINGS +; 15 V6TIM TIME BETWEEN VOICE 6 FROBBINGS +; 16 UNUSED +; 17 UNUSED +;BLOCK 4 EXEC MODE JPC RING (.IF/JPC.RING) +;BLOCK 5 USER MODE JPC RING (.IF/JPC.RING) +;BLOCK 6 VARIOUS PAGING BOX AND OTHER REGISTERS +; 0 UPFW PFW AS OF THE LAST REAL PAGE FAILURE +; 1 DBR1 DBR FOR USER LOW HALF +; 2 DBR2 DBR FOR USER HIGH HALF +; 3 DBR3 DBR FOR EXEC HIGH HALF +; 4 DBR4 DBR FOR EXEC LOW HALF +; 5 LH.AGE AGE BITS IN LEFT HALFWORD +; 6 RH.AGE AGE BITS IN RIGHT HALFWORD +; 7 CN1000 MUST CONTAIN 1000 FOR PAGING BOX CODE +; 10 CN100 MUST CONTAIN 100 FOR PAGING BOX CODE +; 11 UNUSED +; 12 SV.VMA SAVED VMA DURING PAGE FAIL +; 13 SV.BR SAVED BR DURING PAGE FAIL +; 14 XJPC EXEC JPC (EXEC JPC RING POINTER IF RING) +; 15 JPC USER JPC (JPC RING POINTER IF JPC RING) +; 16 SV.AR SAVED AR DURING PAGE FAIL +; 17 SV.ARX SAVES ARX DURING PAGE FAIL +;BLOCK 7 VARIOUS RANDOM REGISTERS +; 0 SV.PAR SAVED WORD WITH BAD PARITY DURING PARITY ERROR +; 1 SV.PFW SAVED PAGE FAIL WORD +; 2 SV.IOPF SAVED I/O PAGE FAIL WORD +; 3 SV.SC SAVE FE,,SC DURING PAGE FAIL +; 4 E0 TEMP FOR STRING STUFF ETC. +; 5 E1 +; 6 T0 +; 7 MSK +; 10 SLEN +; 11 T1 +; 12 T2 +; 13 GCSTBR GC SEGMENT TABLE BASE REG (.IF/LISP) +; 14 STBR SEGMENT TABLE BASE REG (.IF/LISP) +; 15 UNUSED +; 16 TRB BASE AOBJN POINTER FOR TRACKS FEATURE +; 17 TRX CURRENT AOBJN POINTER FOR TRACKS + .TOC "MACROS -- KL-MODE PAGING REGISTERS" + +.IF/KLPAGE +.IFNOT/ITSPAGE +CSMSK "FMADR/#B#,FM#/140" +PUR "FMADR/#B#,FM#/141" +CBR "FMADR/#B#,FM#/142" +SBR "FMADR/#B#,FM#/143" +PFA "FMADR/#B#,FM#/144" +SV.VMA "FMADR/#B#,FM#/145" +SV.BR "FMADR/#B#,FM#/150" +SV.SC "FMADR/#B#,FM#/151" +SV.PFW "FMADR/#B#,FM#/152" +.IF/ITSPAGE +UPFW "FMADR/#B#,FM#/140" ;PFW AS OF LAST REAL PAGE FAIL +DBR1 "FMADR/#B#,FM#/141" ;USER LOW +DBR2 "FMADR/#B#,FM#/142" ;USER HIGH +DBR3 "FMADR/#B#,FM#/143" ;EXEC HIGH +DBR4 "FMADR/#B#,FM#/144" ;EXEC LOW +LH.AGE "FMADR/#B#,FM#/145" +RH.AGE "FMADR/#B#,FM#/146" +CN1000 "FMADR/#B#,FM#/147" +CN100 "FMADR/#B#,FM#/150" +SV.VMA "FMADR/#B#,FM#/152" +SV.BR "FMADR/#B#,FM#/153" +.IF/JPC SUPPORT +XJPC "FMADR/#B#,FM#/154" ;EXEC JPC (OR RING PTR) +JPC "FMADR/#B#,FM#/155" ;JPC (OR JPC RING PTR) +.ENDIF/JPC SUPPORT +SV.PFW "FMADR/#B#,FM#/161" +SV.SC "FMADR/#B#,FM#/163" +.ENDIF/ITSPAGE +SV.AR "FMADR/#B#,FM#/156" ;GROSS KLUDGES AT PF2 AND PFPAR +SV.ARX "FMADR/#B#,FM#/157" ; DEPEND ON THESE THREE +SV.PAR "FMADR/#B#,FM#/160" ; VALUES BEING WHAT THEY ARE + +PFA_AR "PFA,FM_AR" +SV.PFW_AR "SV.PFW,FM_AR" +SV.VMA_AR "SV.VMA,FM_AR" +SV.AR_AR "SV.AR,FM_AR" +SV.ARX_AR "SV.ARX,FM_AR" +SV.BR_AR "SV.BR,FM_AR" +SV.SC_AR "SV.SC,FM_AR" +SV.PAR_AR "SV.PAR,FM_AR" +.IF/ITSPAGE +DBR1_AR "DBR1,FM_AR" +DBR2_AR "DBR2,FM_AR" +LH.AGE_AR "LH.AGE,FM_AR" +RH.AGE_AR "RH.AGE,FM_AR" +UPFW_AR "UPFW,FM_AR" +.IF/JPC SUPPORT +JPC_AR "JPC,FM_AR" +XJPC_AR "XJPC,FM_AR" +.ENDIF/JPC SUPPORT +.ENDIF/ITSPAGE + +AR_SV.PFW "SV.PFW,AR_FM" +AR_SV.VMA "SV.VMA,AR_FM" +ARX_SV.VMA "SV.VMA,ARX_FM" +VMA_SV.VMA "SV.VMA,ADB/FM,AD/B,VMA/AD" +REQ SV.VMA "SV.VMA,ADB/FM,AD/B,VMA/1,MEM/AD FUNC" +AR_SV.AR "SV.AR,AR_FM" +ARX_SV.AR "SV.AR,ARX_FM" +AR_SV.ARX "SV.ARX,AR_FM" +ARX_SV.ARX "SV.ARX,ARX_FM" +AR_SV.BR "SV.BR,AR_FM" +ARX_SV.BR "SV.BR,ARX_FM" +AR_SV.SC "SV.SC,AR_FM" +.IF/ITSPAGE +AR_DBR1 "DBR1,AR_FM" +AR_DBR2 "DBR2,AR_FM" +ARX_DBR1 "DBR1,ARX_FM" +ARX_DBR2 "DBR2,ARX_FM" +ARX_DBR3 "DBR3,ARX_FM" +ARX_DBR4 "DBR4,ARX_FM" +AR_LH.AGE "LH.AGE,AR_FM" +AR_UPFW "UPFW,AR_FM" +GEN SV.PFW "AD/B,ADB/FM,SV.PFW" +.IF/JPC SUPPORT +AR_JPC "JPC,AR_FM" +AR_XJPC "XJPC,AR_FM" +.IF/JPC.RING +AR_JPC+1 "JPC,AR_FM+1" +AR_XJPC+1 "XJPC,AR_FM+1" +.ENDIF/JPC.RING +.ENDIF/JPC SUPPORT +.ENDIF/ITSPAGE + +AR_AR+SBR "SBR,ADB/FM,ADA/AR,AD/A+B,AR/AD" +VMA_AR+SBR "SBR,ADB/FM,ADA/AR,AD/A+B,VMA/AD" +ARX_AR+CBR "CBR,ADB/FM,ADA/AR,AD/A+B,ARX/AD" +VMA_AR+CBR "CBR,ADB/FM,ADA/AR,AD/A+B,VMA/AD" +ARX_ARX+CBR "CBR,ADB/FM,ADA/ARX,AD/A+B,ARX/AD" +VMA_ARX+CBR "CBR,ADB/FM,ADA/ARX,AD/A+B,VMA/AD" +AR_AR AND CSMSK "CSMSK,ADB/FM,ADA/AR,AD/AND,AR/AD" +AR_AR OR PUR "PUR,ADB/FM,ADA/AR,AD/OR,AR/AD" +AR_ARX OR PUR "PUR,ADB/FM,ADA/ARX,AD/OR,AR/AD" +AR_PUR+AR0 "PUR,ADB/FM,ADA EN/0S,AD/A+B,SPEC/XCRY AR0,AR/AD" +.IF/ITSPAGE +AR_AR*LH.AGE "LH.AGE,ADA/AR,ADB/FM,AR/AD" +AR_AR*RH.AGE "RH.AGE,ADA/AR,ADB/FM,AR/AD" +GEN ARX*CN1000 "CN1000,ADA/ARX,ADB/FM" +GEN ARX*SV.VMA "SV.VMA,ADA/ARX,ADB/FM" +ARX_ARX-CN100 "CN100,ADA/ARX,ADB/FM,AD/A-B,ARX/AD" +.ENDIF/ITSPAGE + +;DEFINE PAGE FAIL CODES GENERATED BY MICROCODE + +SC_PF.ILW "SC_#,#/24" ;ILLEGAL WRITE +SC_PF.PNA "SC_#,#/33" ;PAGE NO ACCESS +; PF.APE 36 ;AR PARITY ERROR +; PF.XPE 37 ;ARX PARITY ERROR +.ENDIF/KLPAGE + .TOC "MACROS -- ITS JPC RING REGISTERS" + +XJPC0 "FMADR/#B#,FM#/100" ;EXEC JPC RING - AC BLK 4 +XJPC1 "FMADR/#B#,FM#/101" +XJPC2 "FMADR/#B#,FM#/102" +XJPC3 "FMADR/#B#,FM#/103" +XJPC4 "FMADR/#B#,FM#/104" +XJPC5 "FMADR/#B#,FM#/105" +XJPC6 "FMADR/#B#,FM#/106" +XJPC7 "FMADR/#B#,FM#/107" +XJPC10 "FMADR/#B#,FM#/110" +XJPC11 "FMADR/#B#,FM#/111" +XJPC12 "FMADR/#B#,FM#/112" +XJPC13 "FMADR/#B#,FM#/113" +XJPC14 "FMADR/#B#,FM#/114" +XJPC15 "FMADR/#B#,FM#/115" +XJPC16 "FMADR/#B#,FM#/116" +XJPC17 "FMADR/#B#,FM#/117" + +JPC0 "FMADR/#B#,FM#/120" ;USER JPC RING - AC BLK 5 +JPC1 "FMADR/#B#,FM#/121" +JPC2 "FMADR/#B#,FM#/122" +JPC3 "FMADR/#B#,FM#/123" +JPC4 "FMADR/#B#,FM#/124" +JPC5 "FMADR/#B#,FM#/125" +JPC6 "FMADR/#B#,FM#/126" +JPC7 "FMADR/#B#,FM#/127" +JPC10 "FMADR/#B#,FM#/130" +JPC11 "FMADR/#B#,FM#/131" +JPC12 "FMADR/#B#,FM#/132" +JPC13 "FMADR/#B#,FM#/133" +JPC14 "FMADR/#B#,FM#/134" +JPC15 "FMADR/#B#,FM#/135" +JPC16 "FMADR/#B#,FM#/136" +JPC17 "FMADR/#B#,FM#/137" + +XJPC0_AR "XJPC0,FM_AR" +XJPC1_AR "XJPC1,FM_AR" +XJPC2_AR "XJPC2,FM_AR" +XJPC3_AR "XJPC3,FM_AR" +XJPC4_AR "XJPC4,FM_AR" +XJPC5_AR "XJPC5,FM_AR" +XJPC6_AR "XJPC6,FM_AR" +XJPC7_AR "XJPC7,FM_AR" +XJPC10_AR "XJPC10,FM_AR" +XJPC11_AR "XJPC11,FM_AR" +XJPC12_AR "XJPC12,FM_AR" +XJPC13_AR "XJPC13,FM_AR" +XJPC14_AR "XJPC14,FM_AR" +XJPC15_AR "XJPC15,FM_AR" +XJPC16_AR "XJPC16,FM_AR" +XJPC17_AR "XJPC17,FM_AR" + +JPC0_AR "JPC0,FM_AR" +JPC1_AR "JPC1,FM_AR" +JPC2_AR "JPC2,FM_AR" +JPC3_AR "JPC3,FM_AR" +JPC4_AR "JPC4,FM_AR" +JPC5_AR "JPC5,FM_AR" +JPC6_AR "JPC6,FM_AR" +JPC7_AR "JPC7,FM_AR" +JPC10_AR "JPC10,FM_AR" +JPC11_AR "JPC11,FM_AR" +JPC12_AR "JPC12,FM_AR" +JPC13_AR "JPC13,FM_AR" +JPC14_AR "JPC14,FM_AR" +JPC15_AR "JPC15,FM_AR" +JPC16_AR "JPC16,FM_AR" +JPC17_AR "JPC17,FM_AR" + .TOC "MACROS -- REGISTERS FOR MUSIC" + + +MUSAOB "FMADR/#B#,FM#/40" +MUSDEV "FMADR/#B#,FM#/41" +MUSMIN "FMADR/#B#,FM#/42" +MUSTIM "FMADR/#B#,FM#/43" +MUSBT1 "FMADR/#B#,FM#/44" +MUSBT2 "FMADR/#B#,FM#/45" +CHDTIM "FMADR/#B#,FM#/46" +CN7777 "FMADR/#B#,FM#/47" +V1BR "FMADR/#B#,FM#/50" +V2BR "FMADR/#B#,FM#/51" +V3BR "FMADR/#B#,FM#/52" +V4BR "FMADR/#B#,FM#/53" +V5BR "FMADR/#B#,FM#/54" +V6BR "FMADR/#B#,FM#/55" +V1CTR "FMADR/#B#,FM#/60" +V2CTR "FMADR/#B#,FM#/61" +V3CTR "FMADR/#B#,FM#/62" +V4CTR "FMADR/#B#,FM#/63" +V5CTR "FMADR/#B#,FM#/64" +V6CTR "FMADR/#B#,FM#/65" +V1TIM "FMADR/#B#,FM#/70" +V2TIM "FMADR/#B#,FM#/71" +V3TIM "FMADR/#B#,FM#/72" +V4TIM "FMADR/#B#,FM#/73" +V5TIM "FMADR/#B#,FM#/74" +V6TIM "FMADR/#B#,FM#/75" + +GEN MUSDEV "MUSDEV,ADB/FM,AD/B" + +AR_MUSTIM "MUSTIM,AR_FM" +AR_MUSBT1 "MUSBT1,AR_FM" +AR_MUSBT2 "MUSBT2,AR_FM" +AR_MUSAOB+1 "MUSAOB,AR_FM+1" +AR_CN7777 "CN7777,AR_FM" +AR_AR*MUSBT1 "MUSBT1,ADA/AR,ADB/FM,AR/AD" +AR_ARX+CHDTIM "CHDTIM,ADA/ARX,ADB/FM,AD/A+B,AR/AD" +AR_AR+V1TIM "V1TIM,ADA/AR,ADB/FM,AD/A+B,AR/AD" +AR_AR+V2TIM "V2TIM,ADA/AR,ADB/FM,AD/A+B,AR/AD" +AR_AR+V3TIM "V3TIM,ADA/AR,ADB/FM,AD/A+B,AR/AD" +AR_AR+V4TIM "V4TIM,ADA/AR,ADB/FM,AD/A+B,AR/AD" +AR_AR+V5TIM "V5TIM,ADA/AR,ADB/FM,AD/A+B,AR/AD" +AR_AR+V6TIM "V6TIM,ADA/AR,ADB/FM,AD/A+B,AR/AD" +AR_ARX+V1CTR "V1CTR,ADA/ARX,ADB/FM,AD/A+B,AR/AD" +AR_ARX+V2CTR "V2CTR,ADA/ARX,ADB/FM,AD/A+B,AR/AD" +AR_ARX+V3CTR "V3CTR,ADA/ARX,ADB/FM,AD/A+B,AR/AD" +AR_ARX+V4CTR "V4CTR,ADA/ARX,ADB/FM,AD/A+B,AR/AD" +AR_ARX+V5CTR "V5CTR,ADA/ARX,ADB/FM,AD/A+B,AR/AD" +AR_ARX+V6CTR "V6CTR,ADA/ARX,ADB/FM,AD/A+B,AR/AD" + +MUSTIM_AR "MUSTIM,FM_AR" +MUSBT1_AR "MUSBT1,FM_AR" +MUSBT2_AR "MUSBT2,FM_AR" +MUSAOB_AR "MUSAOB,FM_AR" +CHDTIM_AR "CHDTIM,FM_AR" +V1CTR_AR "V1CTR,FM_AR" +V2CTR_AR "V2CTR,FM_AR" +V3CTR_AR "V3CTR,FM_AR" +V4CTR_AR "V4CTR,FM_AR" +V5CTR_AR "V5CTR,FM_AR" +V6CTR_AR "V6CTR,FM_AR" +V1TIM_AR "V1TIM,FM_AR" +V2TIM_AR "V2TIM,FM_AR" +V3TIM_AR "V3TIM,FM_AR" +V4TIM_AR "V4TIM,FM_AR" +V5TIM_AR "V5TIM,FM_AR" +V6TIM_AR "V6TIM,FM_AR" + .TOC "MACROS -- LISP-RELATED REGISTERS" + +GCSTBR "FMADR/#B#,FM#/173" +STBR "FMADR/#B#,FM#/174" + +GEN STBR "STBR,AD/B,ADB/FM" + +AR_GCSTBR "GCSTBR,AR_FM" +AR_STBR "STBR,AR_FM" + .TOC "MACROS -- CONSTANT GENERATION" + +AR_1S "AD/1S,AR/AD" +ARX_1S "AD/1S,ARX/AD" +MQ_1S "COND/REG CTL,MQ CTL/1S,MQ/MQM SEL" +AR_0S "AD/0S,AR/AD" +ARX_0S "AD/0S,ARX/AD" +AR_SIGN "AD/XCRY-1,SPEC/XCRY AR0,AR/AD" +ARX_AR SIGN "AD/XCRY-1,SPEC/XCRY AR0,ARX/AD" +AR_0.C "COND/ARL IND,CLR/AR" +ARL_0.C "COND/ARL IND,CLR/ARL" +ARR_0.C "COND/ARL IND,CLR/ARR" +ARX_0.C "COND/ARL IND,CLR/ARX" +MQ_0.C "COND/ARL IND,CLR/MQ" +AR_0.S "SPEC/ARL IND,CLR/AR" +ARL_0.S "SPEC/ARL IND,CLR/ARL" +ARR_0.S "SPEC/ARL IND,CLR/ARR" +ARX_0.S "SPEC/ARL IND,CLR/ARX" +MQ_0.S "SPEC/ARL IND,CLR/MQ" +AR_0.M "MEM/ARL IND,CLR/AR" +ARL_0.M "MEM/ARL IND,CLR/ARL" +ARR_0.M "MEM/ARL IND,CLR/ARR" +ARX_0.M "MEM/ARL IND,CLR/ARX" +MQ_0.M "MEM/ARL IND,CLR/MQ" +ARX+MQ_0.M "MEM/ARL IND,CLR/ARX+MQ" +AR+ARX+MQ_0.M "MEM/ARL IND,CLR/AR+ARX+MQ" +ARL+ARX+MQ_0.M "MEM/ARL IND,CLR/ARL+ARX+MQ" +ARL+ARX_0.M "MEM/ARL IND,CLR/ARL+ARX" +AR+MQ_0.M "MEM/ARL IND,CLR/AR+MQ" +AR+MQ_0.S "SPEC/ARL IND,CLR/AR+MQ" +ARR+MQ_0.S "SPEC/ARL IND,CLR/ARR+MQ" +ARX+MQ_0.S "SPEC/ARL IND,CLR/ARX+MQ" +CLR AR "COND/AR CLR" +CLR ARX "COND/ARX CLR" +CLR MQ "COND/REG CTL,MQ/MQ SEL,MQ CTL/0S" +AR_1 "ADA EN/0S,AD/A+1,AR/AD" +ARX_1 "ADA EN/0S,AD/A+1,ARX/AD" +AR_1 LONG "ADA EN/0S,AD/A+1,AR/AD*.25,ARX/ADX" +MQ_1 "ADA EN/0S,AD/A+1,COND/REG CTL,MQ/MQM SEL,MQ CTL/AD" +AR_2 "ADA EN/0S,AD/A+1,AR/AD*2" +ARX_1B1 "ADA EN/0S,AD/A+1,ARX/ADX*.25" + .TOC "MACROS -- ADDRESS MANIPULATION" + +GEN AR+XR "FMADR/XR,ADB/FM,ADA/AR,AD/A+B" +GEN ARX+XR "FMADR/XR,ADB/FM,ADA/ARX,AD/A+B" +VMA_AR+XR "GEN AR+XR,VMA/AD" +VMA_ARX+XR "GEN ARX+XR,VMA/AD" +AR_AR+XR "GEN AR+XR,AR/AD" +AR_ARX+XR "GEN ARX+XR,AR/AD" +VMA_ARX "ADA/ARX,AD/A,VMA/AD" +VMA_AR "ADA/AR,AD/A,VMA/AD" +VMA_AR+1 "ADA/AR,AD/A+1,VMA/AD" +VMA_AR-1 "ADA/AR,AD/A-1,VMA/AD" +VMA_MQ "ADA/MQ,AD/A,VMA/AD" +VMA_BR "ADB/BR,AD/B,VMA/AD" +VMA_AR+BR "ADA/AR,ADB/BR,AD/A+B,VMA/AD" +VMA_ARX+BR "ADA/ARX,ADB/BR,AD/A+B,VMA/AD" +VMA_ARX+FM "ADA/ARX,ADB/FM,AD/A+B,VMA/AD" +VMA_AC0 "FMADR/AC0,ADB/FM,AD/B,VMA/AD" +VMA_AC1 "FMADR/AC1,ADB/FM,AD/B,VMA/AD" +VMA_AC3 "FMADR/AC3,ADB/FM,AD/B,VMA/AD" + +VMA_PC+1 "VMA/PC+1" +VMA_VMA-1 "VMA/VMA,COND/VMA DEC" +VMA_VMA+1 "VMA/VMA,COND/VMA INC" +VMA_# "VMA/1,COND/VMA_#" +VMA_40 "VMA/1,COND/VMA_#,#/40" +VMA_41 "VMA/1,COND/VMA_#,#/41" +VMA_40+PI*2 "VMA/1,COND/VMA_#+PI*2,#/40" +VMA_41+PI*2 "VMA/1,COND/VMA_#+PI*2,#/41" +VMA_420+TRAP "VMA/1,COND/VMA_#+TRAP,#/420" +VMA_430+MODE "VMA/1,COND/VMA_#+MODE,#/430" +VMA_#+AR32-35 "VMA/1,COND/VMA_#+AR32-35" +PC_VMA "SPEC/LOAD PC" + +AR_PC "ADA/PC,AD/A,AR/AD" +AR_PC+1 "ADA/PC,AD/A+1,AR/AD,SPEC/SAVE FLAGS" +ARR_PC+1 "ADA/PC,AD/A+1,AR/AD" +ARX_PC "ADA/PC,AD/A,ARX/AD" + +REQ VMA HELD "COND/SEL VMA,ADA/PC,AD/A,VMA/1,MEM/AD FUNC" +VMA_VMA HELD "COND/SEL VMA,ADA/PC,AD/A,VMA/AD" +AR_VMA HELD "COND/SEL VMA,AR_PC" +ARX_VMA HELD "COND/SEL VMA,ARX_PC" + .TOC "MACROS -- LONG (72-BIT) ARITHMETIC" + +AR_AR+1 LONG "AR_AR+1,ARX/ADX,SPEC/AD LONG" +AR_BR+1 LONG "ADA EN/0S,ADB/BR,AD/A+B+1,AR/AD,ARX/ADX,SPEC/AD LONG" +GEN -AR LONG "ADB/AR*4,ADA EN/0S,AD/A-B,SPEC/AD LONG" +AR_AD*.25 LONG "AR/AD*.25,ARX/ADX*.25,SPEC/AD LONG" +AR_-AR LONG "GEN -AR LONG,AR_AD*.25 LONG" +AR_-BR LONG "ADA EN/0S,ADB/BR,AD/A-B,AR/AD,ARX/ADX,SPEC/AD LONG" +AR_BR*2 LONG "ADB/BR*2,AD/B,AR/AD,ARX/ADX" +AR_-BR*2 LONG "ADA EN/0S,ADB/BR*2,AD/A-B,AR/AD,ARX/ADX,SPEC/AD LONG" +AR_AR+BR LONG "AR_AR+BR,ARX/ADX,SPEC/AD LONG" +AR_AR-BR LONG "AR_AR-BR,ARX/ADX,SPEC/AD LONG" +AR_2(AR+BR) LONG "AR_2(AR*BR),AD/A+B,ARX/ADX*2,SPEC/AD LONG" +AR_AR*5 LONG "ADA/AR,ADB/AR*4,AD/A+B,AR/AD,ARX/ADX,SPEC/AD LONG" +AR_AR*10 LONG "ADA/AR,ADB/AR*4,AD/A+B,AR/AD*2,ARX/ADX*2,SPEC/AD LONG" +AR_AR*1.25 LONG "ADA/AR,ADB/AR*4,AD/A+B,AR_AD*.25 LONG" +AR_AR*.25 LONG "ADA/AR,AD/A,AR/AD*.25,ARX/ADX*.25" + +.TOC "MACROS -- HALFWORD MANIPULATION" + +AR_AR SWAP "SH/AR SWAP,AR/SH" +ARX_AR SWAP "SH/AR SWAP,ARX/SH" +MQ_AR SWAP "SH/AR SWAP,MQ/SH" +ARL_AC0 "FMADR/AC0,ADB/FM,AD/B,COND/ARL IND,ARL/AD" +ARL_ARX "COND/ARL IND,ARL/AD,ADA/ARX,AD/A" +ARR_AC0 "AR_AC0" +ARL_ARR "COND/ARL IND,ARL/SH,SH/AR SWAP" +ARL_ARR.S "SPEC/ARL IND,ARL/SH,SH/AR SWAP" +ARL_ARR.M "MEM/ARL IND,ARL/SH,SH/AR SWAP" +ARR_ARL "SH/AR SWAP,AR/SH" +ARR_ARR "AR/AR" +ARL_ARL "COND/ARL IND,ARL/ARL" +ARL_ARL.M "MEM/ARL IND,ARL/ARL" +ARL_ARXL "SPEC/ARL IND,SH/ARX,ARL/SH" +ARR_BRXR "SPEC/ARL IND,AD/B,ARL/ADX,ADB/BR" +ARR_ARXR "SH/ARX,AR/SH" +ARL_ARXL.M "MEM/ARL IND,SH/ARX,ARL/SH" +ARL_ARX (ADX) "ADA EN/EN,AD/A,MEM/ARL IND,ARL/ADX" +ARR_0S "AR_0S" +ARL_0S "COND/ARL IND,CLR/ARL" +ARR_1S "AR_1S" +ARL_1S "AD/1S,COND/ARL IND,ARL/AD" +ARL_1S.M "AD/1S,MEM/ARL IND,ARL/AD" +ARL_BRL "ADB/BR,AD/B,COND/ARL IND,ARL/AD" +ARL_BRL.S "ADB/BR,AD/B,SPEC/ARL IND,ARL/AD" +ARR_ARX "AR_ARX" +ARL_SHIFT.C "COND/ARL IND,ARL/SH,SH/SHIFT AR!ARX" +ARL_BRL.M "ADB/BR,AD/B,MEM/ARL IND,ARL/AD" +ARL_SHIFT "MEM/ARL IND,SH/SHIFT AR!ARX,ARL/SH" + .TOC "MACROS -- SC" + +CLR SC "SCADA EN/0S,SCAD/A,SC/SCAD" +GEN # AND SC "SCADA/#,SCADB/SC,SCAD/AND" +SC_# "SCADA/#,SCAD/A,SC/SCAD" +SC_#-SC "SCADA/#,SCADB/SC,SCAD/A-B,SC/SCAD" +SC_#-SC-1 "SCADA/#,SCADB/SC,SCAD/A-B-1,SC/SCAD" +SC_#+SC "SCADA/#,SCADB/SC,SCAD/A+B,SC/SCAD" +SC_SC AND # "SCADA/#,SCADB/SC,SCAD/AND,SC/SCAD" +SC_# OR SC "SCADA/#,SCADB/SC,SCAD/OR,SC/SCAD" +SC_P AND SC "SCADA/AR0-5,SCADB/SC,SCAD/AND,SC/SCAD" +SC_P AND # "SCADA/AR0-5,SCADB/#,SCAD/AND,SC/SCAD" +SC_# AND S "SCADA/#,SCADB/AR6-11,SCAD/AND,SC/SCAD" +SC_P-# "SCADA/AR0-5,SCADB/#,SCAD/A-B,SC/SCAD" +SC_S "SCADB/AR6-11,SCADA EN/0S,SCAD/A+B,SC/SCAD" +SC_P "SCADA/AR0-5,SCAD/A,SC/SCAD" +SC_-SC "SCADA EN/0S,SCADB/SC,SCAD/A-B,SC/SCAD" +SC_-SC-1 "SCADA EN/0S,SCADB/SC,SCAD/A-B-1,SC/SCAD" +SC_1 "SCADA EN/0S,SCAD/A+1,SC/SCAD" +SC_1S "SCADA EN/0S,SCAD/A-1,SC/SCAD" +SC_FE "SPEC/SCM ALT,SC/FE" +SC_FE+1 "SCADA/FE,SCAD/A+1,SC/SCAD" +SC_FE-1 "SCADA/FE,SCAD/A-1,SC/SCAD" +SC_FE+SC "SCADA/FE,SCADB/SC,SCAD/A+B,SC/SCAD" +SC_FE-SC "SCADA/FE,SCADB/SC,SCAD/A-B,SC/SCAD" +SC_FE-SC-1 "SCADA/FE,SCADB/SC,SCAD/A-B-1,SC/SCAD" +SC_FE+# "SCADA/FE,SCADB/#,SCAD/A+B,SC/SCAD" +SC_AR0-8 AND # "SCADA/#,SCADB/AR0-8,SCAD/AND,SC/SCAD" +SC_FE-# "SCADA/FE,SCADB/#,SCAD/A-B,SC/SCAD" +SC_FE AND # "SCADA/FE,SCADB/#,SCAD/AND,SC/SCAD" +SC_EA "SPEC/SCM ALT,SC/AR SHIFT" +SC_# AND AR0-8 "SCADA/#,SCADB/AR0-8,SCAD/AND,SC/SCAD" +SC_EXP "SCADA/AR EXP,SCAD/A,SC/SCAD" +SC_EXP+1 "SCADA/AR EXP,SCAD/A+1,SC/SCAD" +SC_EXP-1 "SCADA/AR EXP,SCAD/A-1,SC/SCAD" +SC_EXP+SC "SCADA/AR EXP,SCADB/SC,SCAD/A+B,SC/SCAD" +SC_EXP-# "SCADA/AR EXP,SCADB/#,SCAD/A-B,SC/SCAD" +SC_EXP-SC "SCADA/AR EXP,SCADB/SC,SCAD/A-B,SC/SCAD" + +SC_AR0-8 "SCADA EN/0S,SCADB/AR0-8,SCAD/A+B,SC/SCAD" + .TOC "MACROS -- FE" + +FE_S "SCADA EN/0S,SCADB/AR6-11,SCAD/A+B,FE/SCAD" +FE_# AND S "SCADA/#,SCADB/AR6-11,SCAD/AND,FE/SCAD" +FE_P "SCADA/AR0-5,SCAD/A,FE/SCAD" +FE_SC "SCADA EN/0S,SCADB/SC,SCAD/A+B,FE/SCAD" +FE_-SC-1 "SCADA EN/0S,SCADB/SC,SCAD/A-B-1,FE/SCAD" +FE_# "SCADA/#,SCAD/A,FE/SCAD" +FE_+# "SCADA EN/0S,SCADB/#,SCAD/A+B,FE/SCAD" +FE_#+SC "SCADA/#,SCADB/SC,SCAD/A+B,FE/SCAD" +FE_#-SC "SCADA/#,SCADB/SC,SCAD/A-B,FE/SCAD" +FE_FE+SC "SCADA/FE,SCADB/SC,SCAD/A+B,FE/SCAD" +FE_FE-SC "SCADA/FE,SCADB/SC,SCAD/A-B,FE/SCAD" +FE_FE+# "SCADA/FE,SCADB/#,SCAD/A+B,FE/SCAD" +FE_FE-# "SCADA/FE,SCADB/#,SCAD/A-B,FE/SCAD" +FE_FE OR # "SCADA/FE,SCADB/#,SCAD/OR,FE/SCAD" +FE_FE AND # "SCADA/FE,SCADB/#,SCAD/AND,FE/SCAD" +FE_EXP "SCADA/AR EXP,SCAD/A,FE/SCAD" +FE_EXP+1 "SCADA/AR EXP,SCAD/A+1,FE/SCAD" +FE_EXP-1 "SCADA/AR EXP,SCAD/A-1,FE/SCAD" +FE_EXP+SC "SCADA/AR EXP,SCADB/SC,SCAD/A+B,FE/SCAD" +FE_EXP-# "SCADA/AR EXP,SCADB/#,SCAD/A-B,FE/SCAD" +FE_AR0-8 "SCADA EN/0S,SCADB/AR0-8,SCAD/A+B,FE/SCAD" +FE_AR0-8 COMP "SCADA EN/0S,SCADB/AR0-8,SCAD/A-B-1,FE/SCAD" +FE_#+AR0-8 "SCADA/#,SCADB/AR0-8,SCAD/A+B,FE/SCAD" +FE_AR0-8 AND # "SCADA/#,SCADB/AR0-8,SCAD/AND,FE/SCAD" +FE_FE OR AR0-8 "SCADA/FE,SCADB/AR0-8,SCAD/OR,FE/SCAD" +FE_FE AND AR0-8 "SCADA/FE,SCADB/AR0-8,SCAD/AND,FE/SCAD" +GEN P AND # "SCADA/AR0-5,SCADB/#,SCAD/AND" +GEN P AND SC "SCADA/AR0-5,SCADB/SC,SCAD/AND" +FE_P AND # "SCADA/AR0-5,SCADB/#,SCAD/AND,FE/SCAD" +FE_P AND SC "SCADA/AR0-5,SCADB/SC,SCAD/AND,FE/SCAD" +FE_P+SC "SCADA/AR0-5,SCADB/SC,SCAD/A+B,FE/SCAD" +FE_FE SHRT "COND/FE SHRT,FE/0" +CLR FE "SCADA EN/0S,SCAD/A,FE/SCAD" +FE_1 "SCADA EN/0S,SCAD/A+1,FE/SCAD" +FE_-1 "SCADA EN/0S,SCAD/A-1,FE/SCAD" +FE_FE+1 "SCADA/FE,SCAD/A+1,FE/SCAD" +FE_FE-1 "SCADA/FE,SCAD/A-1,FE/SCAD" +GEN SC "SCADB/SC,SCADA EN/0S,SCAD/A+B" +GEN -SC-1 "SCADB/SC,SCADA EN/0S,SCAD/A-B-1" +GEN FE "SCADA/FE,SCAD/A" +GEN FE-SC "SCADA/FE,SCADB/SC,SCAD/A-B" +GEN FE AND SC "SCADA/FE,SCADB/SC,SCAD/AND" +GEN FE AND # "SCADA/FE,SCADB/#,SCAD/AND" +GEN FE-1 "SCADA/FE,SCAD/A-1" +GEN FE-# "SCADA/FE,SCADB/#,SCAD/A-B" +GEN FE AND S "SCADA/FE,SCADB/AR6-11,SCAD/AND" +GEN #+SC "SCADA/#,SCADB/SC,SCAD/A+B" +GEN #-SC "SCADA/#,SCADB/SC,SCAD/A-B" +GEN #+AR0-8 "SCADA/#,SCADB/AR0-8,SCAD/A+B" +GEN # AND AR0-8 "SCADA/#,SCADB/AR0-8,SCAD/AND" +GEN P-S "SCADA/AR0-5,SCADB/AR6-11,SCAD/A-B" + .TOC "MACROS -- AR MIXER MIXER (BITS 0-8)" + +GEN P-# "SCADA/AR0-5,SCADB/#,SCAD/A-B" +P_SCAD "SPEC/ARL IND,ARL/ARMM,AR0-8/LOAD,ARMM/SCAD POS" +P_SCAD.M "MEM/ARL IND,ARL/ARMM,AR0-8/LOAD,ARMM/SCAD POS" +P_SCAD.C "COND/ARL IND,ARL/ARMM,AR0-8/LOAD,ARMM/SCAD POS" +P_SCAD# "COND/LD AR0-8,AR/ARMM,ARMM/SCAD POS" +P_P-S "SCADA/AR0-5,SCADB/AR6-11,SCAD/A-B,P_SCAD.M" +P_P+S "SCADA/AR0-5,SCADB/AR6-11,SCAD/A+B,P_SCAD" +P_P+1 "SCADA/AR0-5,SCAD/A+1,P_SCAD" +P_SC "SCADA EN/0S,SCADB/SC,SCAD/A+B,P_SCAD.M" +P_SC# "SCADA EN/0S,SCADB/SC,SCAD/A+B,P_SCAD#" +P_-SC "SCADA EN/0S,SCADB/SC,SCAD/A-B,P_SCAD.M" +P_P OR SC "SCADA/AR0-5,SCADB/SC,SCAD/OR,P_SCAD.M" +P_P OR SC# "SCADA/AR0-5,SCADB/SC,SCAD/OR,P_SCAD#" +P_P AND SC "SCADA/AR0-5,SCADB/SC,SCAD/AND,P_SCAD.M" +P_P OR # "SCADA/AR0-5,SCADB/#,SCAD/OR,P_SCAD#" +P_P AND # "SCADA/AR0-5,SCADB/#,SCAD/AND,P_SCAD#" +P_P+# "SCADA/AR0-5,SCADB/#,SCAD/A+B,P_SCAD#" +P_P-# "SCADA/AR0-5,SCADB/#,SCAD/A-B,P_SCAD#" +P_FE "SCADA/FE,SCAD/A,P_SCAD" +P_# "SCADA/#,SCAD/A,P_SCAD#" +GEN S AND # "SCADA/#,SCADB/AR6-11,SCAD/AND" +P_FE-S "SCADA/FE,SCADB/AR6-11,SCAD/A-B,P_SCAD.C" +P_FE+SC "SCADA/FE,SCADB/SC,SCAD/A+B,P_SCAD.C" +P_FE OR SC "SCADA/FE,SCADB/SC,SCAD/OR,P_SCAD" +EXP_SCAD "MEM/ARL IND,ARL/ARMM,AR0-8/LOAD,ARMM/SCAD EXP" +EXP_SCAD.C "COND/REG CTL,AR CTL/AR0-8 LOAD,AR/ARMM,ARMM/SCAD EXP" +EXP TST "COND/REG CTL,EXP TST/AR_EXP" +CLR P "SCADA EN/0S,SCAD/A,P_SCAD" +P_1S "SCADA EN/0S,SCAD/A-1,P_SCAD" +CLR EXP "SCADA EN/0S,SCAD/A,EXP_SCAD" +EXP_1 "SCADA EN/0S,SCAD/A+1,EXP_SCAD" +EXP_SIGN "SPEC/ARL IND,ARL/ARMM,AR0-8/LOAD,ARMM/EXP_SIGN" +EXP_SIGN.C "COND/ARL IND,ARL/ARMM,AR0-8/LOAD,ARMM/EXP_SIGN" +EXP_SIGN.M "MEM/ARL IND,ARL/ARMM,AR0-8/LOAD,ARMM/EXP_SIGN" +EXP_SC "SCADA EN/0S,SCADB/SC,SCAD/A+B,EXP_SCAD" +EXP_-SC-1 "SCADA EN/0S,SCADB/SC,SCAD/A-B-1,EXP_SCAD" +EXP_FE TST "SCADA/FE,SCAD/A,EXP_SCAD.C,EXP TST" +EXP_-SC-1 TST "SCADA EN/0S,SCADB/SC,SCAD/A-B-1,EXP_SCAD.C,EXP TST" +AR0-8_SCAD "SPEC/ARL IND,ARL/ARMM,AR0-8/LOAD,ARMM/SCAD EXP" +AR0-8_SCAD# "ARMM/SCAD EXP,AR/ARMM,COND/LD AR0-8" +AR0-8_SCAD.M "MEM/ARL IND,ARL/ARMM,AR0-8/LOAD,ARMM/SCAD EXP" +AR0-8_SCAD.R "ARMM/SCAD EXP,AR/ARMM,COND/REG CTL,AR CTL/AR0-8 LOAD" +AR0-8_SC "SCADA EN/0S,SCADB/SC,SCAD/A+B,AR0-8_SCAD" +AR0-8_-SC-1 "SCADA EN/0S,SCADB/SC,SCAD/A-B-1,AR0-8_SCAD" +AR0-8_FE "SCADA/FE,SCAD/A,AR0-8_SCAD" +AR0-8_FE.M "SCADA/FE,SCAD/A,AR0-8_SCAD.M" +AR0-8_FE.R "GEN FE,AR0-8_SCAD.R" +AR0-8_FE# "SCADA/FE,SCAD/A,ARMM/SCAD EXP,AR/ARMM,COND/LD AR0-8" +AR0-8_FE-SC "SCADA/FE,SCADB/SC,SCAD/A-B,AR0-8_SCAD.M" +AR0-8_FE OR SC "SCADA/FE,SCADB/SC,SCAD/OR,AR0-8_SCAD.M" +AR0-8_FE+# "SCADA/FE,SCADB/#,SCAD/A+B,AR0-8_SCAD#" +AR0-8_FE OR # "SCADA/FE,SCADB/#,SCAD/OR,AR0-8_SCAD#" +AR0-8_# AND AR0-8 "SCADA/#,SCADB/AR0-8,SCAD/AND,AR0-8_SCAD#" +AR0-8_# "COND/LD AR0-8,AR/ARMM,ARMM/#" + .TOC "MACROS -- MICROPROGRAM SKIPS" + +SKP AR0 "SKIP/AR0" +SKP ARX0 "SKIP/ARX0" +SKP BR0 "SKIP/BR0" +SKP AD0 "SKIP/AD0" +SKP ADX0 "SKIP/ADX0" +SKP AR18 "SKIP/AR18" +SKP SC0 "SKIP/SC0" +SKP SCAD0 "SKIP/SCAD0" +SKP AD NE "SKIP/AD#0" +SKP SCAD NE "SKIP/SCAD#0" +SKP CRY0 "SKIP/AD CRY0" +SKP INTRPT "SKIP/INTRPT" +SKP AC#0 "SKIP/AC#0" +SKP -START "SKIP/-START" +SKP RUN "SKIP/RUN" +SKP KERNEL "SKIP/KERNEL" +SKP USER "SKIP/USER" +SKP P!S XCT "SKIP/P!S XCT" +SKP RPW "SKIP/RPW REF" +SKP AC REF "SKIP/AC REF" +SKP FETCH "SKIP/FETCH" +SKP SC LE 36 "SCADB/SC,SCADA/#,#/-36.,SCAD/A+B,SKIP/SCAD0" +SKP SC NE "SCADB/SC,SCADA EN/0S,SCAD/A+B,SKIP/SCAD#0" +SKP FE0 "SCADA/FE,SCAD/A,SKIP/SCAD0" +SKP EXP NE "SCADA/AR EXP,SCAD/A,SKIP/SCAD#0" +SKP P NE "SCADA/AR0-5,SCAD/A,SKIP/SCAD#0" +SKP AR GT BR "ADA/AR,ADB/BR,AD/XOR,SKIP/AD CRY0" +SKP AR GT FM "ADA/AR,ADB/FM,AD/XOR,SKIP/AD CRY0" +SKP ARX LT BRX "ADA EN/EN,ADB/BR,AD/A-B,SKIP/ADX0" +SKP ARX LE BRX "ADA EN/EN,ADB/BR,AD/A-B-1,SKIP/ADX0" +SKP MQ EQ -1 "ADA/MQ,AD/CRY A EQ -1,SKIP/AD CRY0" +SKP AR SIG "ADA/AR,AD/A+XCRY,SPEC/XCRY AR0,SKIP/AD#0" +SKP AC0- "FMADR/AC0,ADB/FM,AD/B,SKIP/AD0" +SKP AC0+ "FMADR/AC0,ADB/FM,AD/SETCB,SKIP/AD0" +SKP AR1 "ADA/AR,AD/A*2,SKIP/AD0" +SKP AR2 "ADB/AR*4,AD/B,SKIP/AD0" +SKP AR6 "SCADB/AR6-11,SCADA/#,#/40,SCAD/AND,SKIP/SCAD#0" +SKP AR NE "ADA/AR,AD/CRY A#0,SKIP/AD CRY0" +SKP ARX2 "ADB/AR*4,AD/B,SKIP/ADX0" +SKP ARX NE "ADA/ARX,AD/CRY A#0,SKIP/AD CRY0" +SKP BR EQ "ADA EN/0S,ADB/BR,AD/CRY A GE B,SKIP/AD CRY0" +SKP BR EQ -1 "ADA EN/0S,ADB/BR,AD/A+B+1,SKIP/AD CRY0" +SKP ARX+MQ NE "ADA/MQ,AD/CRY A#0,SPEC/AD LONG,SKIP/AD CRY0" +SKP AR EQ "ADA EN/0S,ADB/AR*4,AD/ORCB+1,SKIP/AD CRY0" + +.TOC "MACROS -- CRY0 GENERATORS" + +NO CRY "AD/SETCA" +TEST AR "ADA/AR,AD/CRY A#0" +TEST ARX "ADA/ARX,AD/CRY A#0" +TEST ARX.AR*4 "ADA/ARX,ADB/AR*4,AD/CRY A.B#0" +TEST AR.AC0 "FMADR/AC0,ADB/FM,ADA/AR,AD/CRY A.B#0" +TEST AR.BR "ADB/BR,ADA/AR,AD/CRY A.B#0" +TEST AR.MSK "MSK,ADB/FM,ADA/AR,AD/CRY A.B#0" +TEST BRL "ADA EN/0S,ADB/BR,AD/ORCB+1,GEN CRY18" + .TOC "MACROS -- SUBROUTINE CALL AND RETURNS" + +CALL "SPEC/CALL" +CALL.M "MEM/ARL IND,CALL/CALL" +CALL.S "SPEC/ARL IND,CALL/CALL" +CALL.C "COND/ARL IND,CALL/CALL" + +RETURN0 "DISP/RETURN,J/0" +RETURN1 "DISP/RETURN,J/1" +RETURN2 "DISP/RETURN,J/2" +RETURN3 "DISP/RETURN,J/3" +RETURN4 "DISP/RETURN,J/4" +RETURN5 "DISP/RETURN,J/5" +RETURN6 "DISP/RETURN,J/6" +RETURN7 "DISP/RETURN,J/7" +RETURN10 "DISP/RETURN,J/10" +RETURN12 "DISP/RETURN,J/12" + +.TOC "MACROS -- DISPATCHES" + +IR DISP "DISP/DRAM J" +B DISP "DISP/DRAM B" +EA MOD DISP "DISP/EA MOD" +EA TYPE DISP "DISP/EA TYPE" +NXT INSTR "MEM/MB WAIT,DISP/NICOND,#/0,J/NEXT" ;MUSTN'T CLEAR FE! +.IF/NXT.INSTR.BITES +NXT INSTR AFTER AC1 "J/FINI" +FINISH "J/FINI" ;USE INSTEAD OF NXT INSTR IF FM WRITE +.IF/JPC SUPPORT +NXT INSTR AFTER JPC "J/FINI" +.ENDIF/JPC SUPPORT +.IFNOT/NXT.INSTR.BITES +NXT INSTR AFTER AC1 "NXT INSTR" +FINISH "NXT INSTR" ;USE INSTEAD OF NXT INSTR IF FM WRITE +.IF/JPC SUPPORT +NXT INSTR AFTER JPC "NXT INSTR" +.ENDIF/JPC SUPPORT +.ENDIF/NXT.INSTR.BITES +SH DISP "SH/SHIFT AR!ARX,DISP/SH0-3" +AR0-3 DISP "SH/AR,DISP/SH0-3" +AR18-21 DISP "SH/AR SWAP,DISP/SH0-3" +ARX0-3 DISP "SH/ARX,DISP/SH0-3" +BYTE DISP "DISP/BYTE" +SIGNS DISP "DISP/SIGNS" +SR DISP "DISP/SR" +PF DISP "DISP/PG FAIL" +NORM "DISP/NORM" +NORM AR "ADB/AR*4,AD/B,DISP/NORM" +NORM -AR "ADA EN/0S,ADB/AR*4,AD/A-B,AR/AD*.25,ARX/ADX*.25,DISP/NORM" + .TOC "MACROS -- I/O OPERATIONS ON EBUS" + +AR_EBUS "AR/EBUS,TIME/5T" +IO INIT "COND/EBUS CTL,EBUS CTL/IO INIT" +SET DATAO "COND/EBUS CTL,EBUS CTL/DATAO" +SET DATAI "COND/EBUS CTL,EBUS CTL/DATAI,AD/0S,AR/AD" +REQ EBUS "COND/EBUS CTL,EBUS CTL/REQ EBUS" +REL EBUS "COND/EBUS CTL,EBUS CTL/REL EBUS" +DROP EBUS REQ "COND/EBUS CTL,EBUS CTL/0" +SKP -EBUS GRANT "SKIP/-EBUS GRANT" +SKP -EBUS XFER "SKIP/-EBUS XFER" +SET EBUS DEMAND "COND/EBUS CTL,EBUS CTL/EBUS DEMAND" +CLR EBUS DEMAND "COND/EBUS CTL,EBUS CTL/EBUS NODEMAND" +SKP IO LEGAL "SKIP/IO LEGAL" +SKP PI CYCLE "SKIP/PI CYCLE" +GET ECL EBUS "COND/EBUS CTL,EBUS CTL/GRAB EEBUS" +REL ECL EBUS "COND/EBUS CTL,EBUS CTL/REL EEBUS" + +DIAG OUT "COND/DIAG FUNC,ADA/AR,AD/A" +DIAG IN "COND/DIAG FUNC,AR/EBUS" +AR_EBUS REG "DIAG IN,DIAG FUNC/RD EBUS REG" +AR05_SCD ADDR BRK CYC "DIAG IN,DIAG FUNC/537" +AR03-04_SCD TRAP CYC "DIAG IN,DIAG FUNC/530" +DATAO APR "DIAG OUT,DIAG FUNC/DATAO APR" +DATAI APR(L) "DIAG IN,DIAG FUNC/DATAI APR" +CONO APR "DIAG OUT,DIAG FUNC/CONO APR" +CONI APR(L) "DIAG IN,DIAG FUNC/CONI APR(L)" +CONI APR(R) "DIAG IN,DIAG FUNC/CONI APR(R)" +CONO PI "DIAG OUT,DIAG FUNC/CONO PI" +CONI PI(L) "DIAG IN,DIAG FUNC/CONI PI(L)" +CONI PI(R) "DIAG IN,DIAG FUNC/CONI PI(R)" +CONI PI(PAR) "DIAG IN,DIAG FUNC/CONI PI(PAR)" +DATAO PAG(L) "DIAG OUT,DIAG FUNC/DATAO PAG" +DATAI PAG(L) "DIAG IN,DIAG FUNC/DATAI PAG(L)" +CONO PAG "DIAG OUT,DIAG FUNC/CONO PAG" +CONI PAG "DIAG IN,DIAG FUNC/CONI PAG" +AR_SERIAL "AR/ARMM,COND/REG CTL,AR CTL/ARR LOAD" +LD PREV CTXT "COND/DIAG FUNC,DIAG FUNC/LD PCS+CWSX,ADA/PC,AD/A" + +AR_TIME BASE "DIAG IN,DIAG FUNC/RD TIME" +RD+CLR TB "SPEC/MTR CTL,AR_TIME BASE" +AR_PERF CNT "DIAG IN,DIAG FUNC/RD PERF CNT" +RD+CLR PA "SPEC/MTR CTL,AR_PERF CNT" +AR_EBOX CNT "DIAG IN,DIAG FUNC/RD EBOX CNT" +RD+CLR E CNT "SPEC/MTR CTL,AR_EBOX CNT" +AR_CACHE CNT "DIAG IN,DIAG FUNC/RD CACHE CNT" +RD+CLR C CNT "SPEC/MTR CTL,AR_CACHE CNT" +AR_INTERVAL "DIAG IN,DIAG FUNC/RD INTRVL" +AR_PERIOD "DIAG IN,DIAG FUNC/RD PERIOD" +CONI MTR "DIAG IN,DIAG FUNC/CONI MTR" +AR_MTR REQ "DIAG IN,DIAG FUNC/RD MTR REQ" +CONO TIM "SPEC/MTR CTL,DIAG OUT,DIAG FUNC/CONO TIM" +CONO MTR "SPEC/MTR CTL,DIAG OUT,DIAG FUNC/CONO MTR" +BLKO TIM(L) "SPEC/MTR CTL,DIAG OUT,DIAG FUNC/LD PA LEFT" +BLKO TIM(R) "SPEC/MTR CTL,DIAG OUT,DIAG FUNC/LD PA RIGHT" + .TOC "MACROS -- MEMORY ACCESS" + +LOAD AR "MEM/LOAD AR" +LOAD ARX "MEM/LOAD ARX" +LOAD IR "COND/LOAD IR" +LOAD AR VIA RPW "MEM/RPW" +EXIT "DISP/DRAM B,MEM/B WRITE,J/ST0" +EXIT DBL "MB WAIT,J/ST2AC" ;"I FETCH,J/DSTAC" WHEN TIMING FIXED +STORE "MEM/WRITE" +B WRITE "DISP/DRAM B,MEM/B WRITE" +I FETCH "VMA/PC+1,MEM/FETCH,FETCH/UNCOND" +REFETCH "VMA/PC,MEM/FETCH,FETCH/UNCOND" +FETCH "MEM/FETCH,FETCH/UNCOND" +FETCH+1 "COND/VMA INC,MEM/FETCH,FETCH/UNCOND" +COMP FETCH "AD/XOR,VMA/PC+1,MEM/FETCH,FETCH/COMP" +SKIP FETCH "ADA/AR,AD/A,VMA/PC+1,MEM/FETCH,FETCH/SKIP" +JUMP FETCH "VMA/PC+1,MEM/FETCH,FETCH/JUMP" +TEST FETCH "VMA/PC+1,MEM/FETCH,FETCH/TEST" +JFCL FETCH "VMA/PC+1,MEM/FETCH,FETCH/JFCL" +CMS FETCH "VMA/PC+1,MEM/FETCH,FETCH/SKIP" +A READ "VMA/PC+1,DISP/DRAM A RD,MEM/A RD,#/0,J/0" +A INDRCT "MEM/A IND,VMA/1" +BYTE READ "MEM/BYTE RD" +BYTE INDRCT "MEM/BYTE IND,VMA/1" + +MB WAIT "MEM/MB WAIT" +FIN STORE "FMADR/VMA" ;FINISH STOREING +FIN XFER "FMADR/VMA,ADB/FM,AD/B" ;FINISH XFER WHILE STARTING ANOTHER +AR_MEM "MEM/MB WAIT,FMADR/VMA,ADB/FM,AD/B" +ARX_MEM "MEM/MB WAIT,FMADR/VMA,ADB/FM,AD/B" +MEM_AR "FMADR/VMA,MEM/MB WAIT" +EPT REF "SPEC/SP MEM CYCLE,SP MEM/EPT" +EPT FETCH "MEM/LOAD ARX,SPEC/SP MEM CYCLE,SP MEM/EPT FETCH" +UPT REF "SPEC/SP MEM CYCLE,SP MEM/UPT" +UPT FETCH "MEM/LOAD ARX,SPEC/SP MEM CYCLE,SP MEM/UPT FETCH" +PT REF "SPEC/SP MEM CYCLE,SP MEM/PT" +PT FETCH "MEM/LOAD ARX,SPEC/SP MEM CYCLE,SP MEM/PT FETCH" +PHYS REF "SPEC/SP MEM CYCLE,SP MEM/UNPAGED" +EXEC REF "SPEC/SP MEM CYCLE,SP MEM/EXEC" +USER REF "SPEC/SP MEM CYCLE,SP MEM/USER" +MAP "MEM/REG FUNC,MREG FNC/MAP" +LOAD EBR "MEM/REG FUNC,MREG FNC/LOAD EBR" +LOAD UBR "MEM/REG FUNC,MREG FNC/LOAD UBR" +READ EBR "MEM/REG FUNC,MREG FNC/READ EBR" +READ UBR "MEM/REG FUNC,MREG FNC/READ UBR" +READ ERA "MEM/REG FUNC,MREG FNC/READ ERA" +SWEEP CACHE "MEM/REG FUNC,MREG FNC/LOAD CCA" +SBUS DIAG "MEM/REG FUNC,MREG FNC/SBUS DIAG" +WR REFILL RAM "MEM/REG FUNC,MREG FNC/WR REFILL RAM" + +CLR PT LINE "COND/MBOX CTL,MBOX CTL/CLR PT LINE" +WR PT ENTRY "COND/MBOX CTL,MBOX CTL/PT WR" +PT SEL_INVAL "COND/MBOX CTL,MBOX CTL/PT DIR CLR" +PT SEL_NORMAL "COND/MBOX CTL,MBOX CTL/NORMAL" + .TOC "MACROS -- FLAG CONTROL" + +TRAP1 "COND/PCF_#,PC FLAGS/TRAP1" +TRAP2 "COND/PCF_#,PC FLAGS/TRAP2" +TRAP3 "COND/PCF_#,PC FLAGS/TRAP3" +SET FPD "COND/PCF_#,PC FLAGS/FPD" +CLR FPD "SPEC/CLR FPD" +SET AROV "COND/PCF_#,PC FLAGS/AROV" +SET NO DIVIDE "COND/PCF_#,PC FLAGS/DIV CHK" +SET FLOV "COND/PCF_#,PC FLAGS/FLOV" +SET FL NO DIV "COND/PCF_#,PC FLAGS/FDV CHK" +EXP TEST "COND/REG CTL,EXP TST/AR_EXP" + +GEN CRY18 "SPEC/GEN CRY18" +INH CRY18 "SPEC/INH CRY18" +AD LONG "SPEC/AD LONG" +AD FLAGS "COND/AD FLAGS" +SET FLAGS_AR "SPEC/FLAG CTL,FLAG CTL/SET FLAGS" +RSTR FLAGS_AR "SPEC/FLAG CTL,FLAG CTL/RSTR FLAGS" +JFCL T "SPEC/FLAG CTL,FLAG CTL/JFCL" +JFCL S "SPEC/FLAG CTL,FLAG CTL/JFCL+LD" +DISMISS "SPEC/FLAG CTL,FLAG CTL/DISMISS" +PORTAL "SPEC/FLAG CTL,FLAG CTL/PORTAL" +HALT "SPEC/FLAG CTL,FLAG CTL/HALT" + +SET PI CYCLE "COND/SPEC INSTR,SPEC INSTR/SET PI CYCLE" +SET PC+1 INH "COND/SPEC INSTR,SPEC INSTR/INH PC+1" +CLR INTRPT INH "COND/SPEC INSTR,SPEC INSTR/0" +TAKE INTRPT "SKIP/-MTR REQ,J/MTRINT" +ABORT INSTR "COND/SPEC INSTR,SPEC INSTR/INSTR ABORT" +SET SXCT "COND/SPEC INSTR,SPEC INSTR/SXCT" +SET PXCT "COND/SPEC INSTR,SPEC INSTR/PXCT" +SET HALTED "COND/SPEC INSTR,SPEC INSTR/HALTED" +CONTINUE "COND/SPEC INSTR,SPEC INSTR/CONT" +SET CONS XCT "COND/SPEC INSTR,SPEC INSTR/CONS XCT" + +SET IO PF "COND/MBOX CTL,MBOX CTL/SET IO PF ERR" + + +#OPTIONS "Q400/Q,Q200/Q,Q100/Q,Q40/Q,Q20/Q,Q10/Q,Q4/Q,Q2/Q,Q1/Q" + +BAG-BITING NO-OP "FORCE AR-ARX" ;TO FIX GODDAMN TIMING SCREWS +SET MTR PA EN "COND/EBOX STATE,#/225" +CLR MTR PA EN "COND/EBOX STATE,#/025" +CLR ACCOUNT EN "COND/EBOX STATE,#/145" +SET ACCOUNT EN "COND/EBOX STATE,#/105" +SET TRACKS EN "COND/EBOX STATE,#/131" +CLR TRACKS EN "COND/EBOX STATE,#/121" +SET TRK+PA EN "COND/EBOX STATE,#/231" +CLR TRK+PA EN "COND/EBOX STATE,#/021" + .TOC "MACROS -- STATE REGISTER CONTROL" + +SR_# "COND/SR_#" ;USED FOR NON-PAGE-FAIL APPLICATIONS +SR_0 "COND/SR_#,#/0" +SR_1 "COND/SR_#,#/1" +SR_BLT(SRC) "COND/SR_#,#/607" ;CONTEXT CONTROLLED BY PXCT 2,1 +SR_BLT(DST) "COND/SR_#,#/107" ; BY PXCT 10,4 +.IF/EIS +SR_ED(S) "COND/SR_#,#/1" +SR_ED(+D) "COND/SR_#,#/24" +.IF/DECIMAL +SR_DB "COND/SR_#,#/2" ;D2B ANYWHERE +SR_BDF "COND/SR_#,#/3" ;B2D STORING FILLERS +SR_BDD "COND/SR_#,#/6" ;B2D AFTER UPDATING DST PTR +SR_BDT "COND/SR_#,#/10" ;B2D IN TRANSLATION +.ENDIF/DECIMAL +SR_SRC "COND/SR_#,#/11" +SR_DST "COND/SR_#,#/12" +SR_SRC+DST "COND/SR_#,#/13" +SR_DSTF "COND/SR_#,#/14" +.ENDIF/EIS +.IF/MAP +SR_MAP "COND/SR_#,#/15" ;CATCH MAP PAGE FAILURES +.ENDIF/MAP +.IF/LISP +SR_LIST "COND/SR_#,#/16" ;LISP LIST HACKERY +.ENDIF/LISP +SR_JRSTF "COND/SR_#,#/17" ;FOR JRSTF ABORT INSTR BUG + +SET SR1 "COND/SR_#,#/64" +SET SR2 "COND/SR_#,#/62" +SET SR3 "COND/SR_#,#/61" +CLR SR2 "COND/SR_#,#/20" + +.TOC "DISPATCH RAM MACROS" + + .DCODE + +;"A FIELD" MACROS +; DECODED TO TELL WHAT TO DO WITH EFFECTIVE ADDRESS +; AND WHETHER TO PREFETCH FROM PC+1 + +I "A/IMMED" +I-PF "A/IMMED-PF" +W "A/WR-TST" +R "A/READ" +R-PF "A/READ-PF" +RW "A/RD-WR" +.IF/RPW +RPW "A/RD-P-WR" +.IFNOT/RPW +RPW "A/RD-WR" +.ENDIF/RPW +.IF/WRTST +IW "A/WR-TST" +.IFNOT/WRTST +IW "A/IMMED" +.ENDIF/WRTST + ;"B FIELD" MACROS +; DECODED BY MOST INSTRUCTIONS TO TELL WHERE TO STORE RESULTS, +; BUT USED BY OTHERS TO HOLD VARIOUS "MODE" INFORMATION + +AC "B/AC" +M "B/MEM" +S "B/SELF" +B "B/BOTH" +DBL AC "B/DBL AC" +DBL B "B/DBL BOTH" +FL-AC "B1-2/AC" +FL-MEM "B1-2/MEM" +FL-BOTH "B1-2/BOTH" + +TN- "B0/CRY0(1),B1-2/0" +TNE "B0/CRY0(0),B1-2/0" +TNA "B0/CRY0(0),B1-2/0" +TNN "B0/CRY0(1),B1-2/0" +TZ- "B0/CRY0(1),B1-2/1" +TZE "B0/CRY0(0),B1-2/1" +TZA "B0/CRY0(0),B1-2/1" +TZN "B0/CRY0(1),B1-2/1" +TC- "B0/CRY0(1),B1-2/2" +TCE "B0/CRY0(0),B1-2/2" +TCA "B0/CRY0(0),B1-2/2" +TCN "B0/CRY0(1),B1-2/2" +TO- "B0/CRY0(1),B1-2/3" +TOE "B0/CRY0(0),B1-2/3" +TOA "B0/CRY0(0),B1-2/3" +TON "B0/CRY0(1),B1-2/3" + +SJC- "B/SJC-" +SJCL "B/SJCL" +SJCE "B/SJCE" +SJCLE "B/SJCLE" +SJCA "B/SJCA" +SJCGE "B/SJCGE" +SJCN "B/SJCN" +SJCG "B/SJCG" + +BLKI "B0/CRY0(0),B1-2/2" +BLKO "B0/CRY0(0),B1-2/0" +DATAI "B/6" +DATAO "B/4" +CONI "B/6" +CONO "B/4" +CONSO "B0/CRY0(1),B1-2/1" +CONSZ "B0/CRY0(0),B1-2/1" + + .UCODE + \ No newline at end of file diff --git a/src/ucode/music.16 b/src/ucode/music.16 new file mode 100755 index 00000000..016ba46e --- /dev/null +++ b/src/ucode/music.16 @@ -0,0 +1,233 @@ +.TOC "MUSIC MICROCODE" + +.IF/MUSIC + +;;; MUSIC MICROCODE FOR KL-10 +;;; +;;; BASIC SETUP: +;;; THERE ARE SIX VOICES. +;;; MUSIC IS PLAYED BY PUTTING BITS IN A REGISTER +;;; WHICH LIVES IN THE NETWORK IMP INTERFACE. THIS +;;; REGISTER IS LOADED BY A DATAO. THE BITS ARE LOADED +;;; AT SUCH A RATE THAT THE LOW SIX BITS PRODUCE SQUARE +;;; WAVES OF THE CORRECT FREQUENCIES. TO ACCOMPLISH THIS, +;;; THE KL-10'S 10.-USEC INTERVAL TIMER IS USURPED. +;;; +;;; FOR EACH VOICE THERE IS A BASE REGISTER (VNBR), +;;; A TIME (VNTIM, THE INVERSE OF THE FREQUENCY), +;;; AND A COUNTER (VNCTR). +;;; THERE ARE ALSO SEVERAL OTHER REGISTERS: +;;; MUSDEV CONTAINS A DATAO INSTRUCTION TO THE REGISTER. +;;; MUSMIN THE MINIMUM INTERVAL BETWEEN CHANGES TO THE +;;; REGISTER. USED TO PREVENT GOBBLING TOO MUCH +;;; MACHINE TIME. MEASURED IN 10.-USEC UNITS, +;;; WITH THE BINARY POINT BETWEEN THE HALVES +;;; OF THE WORD. +;;; CN7777 CONTAINS 7777, WHICH IS THE MAXIMUM INTERVAL +;;; THE TIMER'S 12.-BIT COUNTER CAN HANDLE. +;;; MUSBT1 THE BITS TO LOAD INTO THE REGISTER WHEN THE +;;; TIMER NEXT GOES OFF. +;;; MUSBT2 THE BITS TO TOGGLE AFTER THE REGISTER IS LOADED. +;;; MUSAOB AN AOBJN POINTER TO THE MUSIC DATA. +;;; MUSTIM THE QUANTITY FOR THE INTERVAL TIMER'S LIMIT +;;; REGISTER AFTER IT NEXT GOES OFF. THIS IS IN +;;; THE LEFT HALF, WITH THE CONTROL BITS FOR THE TIMER. +;;; CHDTIM THE TIME REMAINING FOR THE CURRENT CHORD, +;;; IN 10.-USEC UNITS. +;;; EACH BASE REGISTER POINTS TO A 64.-WORD TABLE. EACH +;;; ENTRY IS THE INVERSE FREQUENCY OF A TONE FOR THAT VOICE, +;;; MEASURED IN 10.-USEC UNITS, WITH THE BINARY POINT +;;; BETWEEN THE HALVES OF THE WORD. +;;; THE AOBJN POINTER POINTS TO A TABLE OF 2-WORD ENTRIES. +;;; THE FIRST WORD OF EACH ENTRY HAS SIX 6-BIT BYTES, ONE +;;; FOR EACH VOICE, THE FIRST VOICE BEING LEFTMOST. +;;; EACH BYTE IS USED AS AN INDEX INTO A VOICE TABLE TO +;;; FETCH AN INVERSE FREQUENCY. THE SECOND WORD IS THE +;;; LENGTH OF THE CHORD IN 10.-USEC TICKS (BINARY POINT +;;; AT THE RIGHT END OF THE WORD). WHEN THIS WORD IS +;;; FETCHED, IT IS WRITTEN BACK WITH THE SIGN BIT SET SO +;;; THAT THE MACRO-CODE CAN CHECK THE PROGRESS OF THE +;;; MUSIC PLAYER. +;;; +;;; THE MUSIC ALGORITHM: +;;; THE INSTRUCTION PLAY=DATAO TIM, IS PUT IN THE FIRST +;;; LOCATION OF THE INTERVAL TIMER'S INTERRUPT VECTOR. +;;; WHEN EXECUTED AS A PI INSTRUCTION, PLAY DOES: +;;; +;;; CONO TIM,<460000+C(MUSTIM)> ;RESET TIMER, RESTART +;;; DATAO MUSREG,MUSBT1 +;;; XOR MUSBT2 INTO MUSBT1 +;;; SET MUSBT2 TO 0 +;;; COMPUTE MUSTIM=LOGAND(<-1,,0>, +;;; MAX(MUSMIN, +;;; MIN(V1CTR, V2CTR, ..., +;;; V6CTR, 7777))) +;;; FOR N FROM 1 TO 6 DO +;;; BEGIN +;;; SUBTRACT MUSTIM FROM VCTR +;;; IF RESULT NEGATIVE, SET BIT IN MUSBT2 +;;; FOR VOICE , AND KEEP ADDING +;;; VTIM INTO VCTR UNTIL POSITIVE +;;; END +;;; SUBTRACT MUSTIM FROM CHDTIM +;;; IF RESULT NEGATIVE THEN +;;; IF MUSAOB HAS RUN OUT THEN +;;; TAKE PI CYCLE 2 (SECOND INT INSTR) +;;; ELSE BEGIN +;;; FETCH VOICES WORD (SIX 6-BIT BYTES) +;;; FETCH DURATION WORD, PUT IN CHDTIM +;;; BUMP MUSAOB BY <2,,2> +;;; FOR N FROM 1 TO 6 DO +;;; BEGIN +;;; CLEAR VCTR +;;; FETCH VTIM TO THE WORD +;;; ADDRESSED BY C(VBR) +;;; PLUS A 6-BIT BYTE +;;; END +;;; DISMISS INTERRUPT +;;; END + + +=0 +PLAY0: AR_BR,J/UUO ;IF NOT PI CYCLE, BE A UUO + GET ECL EBUS,AR_AR SWAP + CONO TIM ;START THE TIMER FOR NEXT TICK + REL ECL EBUS + GEN MUSDEV,LOAD IR ;SET UP FOR DATAO TO REGISTER +=10 AR_MUSBT1,CALL,SKP IO LEGAL,J/GTEBUS ;DO THE DATAO + AR_MUSBT2 ;XOR MUSBT2 INTO MUSBT1 + AR_AR*MUSBT1,AD/XOR + MUSBT1_AR + AR_CN7777,BRX/ARX ;FIND MIN OF 7777 AND ALL VNCTRS + BR/AR,SKP AR GT FM,V1CTR,ARX/AD ;"SKP GT" IS AN XOR OPERATION +=0 +PLAY01: BR/AR,SKP AR GT FM,V2CTR,ARX/AD,J/PLAY23 + AR_ARX*BR,AD/XOR,J/PLAY01 ;XOR'ING IN XOR'D QUANTITY +=0 +PLAY12: BR/AR,SKP AR GT FM,V3CTR,ARX/AD,J/PLAY23 + AR_ARX*BR,AD/XOR,J/PLAY12 +=0 +PLAY23: BR/AR,SKP AR GT FM,V4CTR,ARX/AD,J/PLAY34 + AR_ARX*BR,AD/XOR,J/PLAY23 +=0 +PLAY34: BR/AR,SKP AR GT FM,V5CTR,ARX/AD,J/PLAY45 + AR_ARX*BR,AD/XOR,J/PLAY34 +=0 +PLAY45: BR/AR,SKP AR GT FM,V6CTR,ARX/AD,J/PLAY56 + AR_ARX*BR,AD/XOR,J/PLAY45 +=0 +PLAY56: BR/AR,SKP AR GT FM,MUSMIN,ARX/AD,J/PLAY6M + AR_ARX*BR,AD/XOR,J/PLAY56 +=0 +PLAY6M: AR_ARX*BR,AD/XOR ;MAX RESULT WITH MUSMIN + ARL_ARL,CLR/ARR + ARX_-AR-1,P_#,#/6 ;CONTROL BITS FOR TIMER + MUSTIM_AR + +;THE THEORY BEHIND USING "ARX_-AR-1" INSTEAD OF "ARX_-AR" IS TO +;AVOID UNFORTUNATE COINCIDENCES WHERE WE REACH ZERO EXACTLY, +;SINCE WE ARE REALLY DOING A SIGN BIT CHECK. THE EXTRA 1 ONLY +;THROWS IT OFF BY (10. USEC)*(2^-18) = .38 PICOSEC. + +PLAYV1: AR_ARX+V1CTR,SKP AD0 +=0 V1CTR_AR,BRX/ARX,ARX_BRX*2,J/PLAYQ1 + BRX/ARX,ARX_BRX*2+1 + BRX/ARX,ARX_BRX,J/PLAYZ1 +=0 +PLAYX1: V1CTR_AR,J/PLAYV2 +PLAYZ1: AR_AR+V1TIM,SKP AD0,J/PLAYX1 +PLAYQ1: BRX/ARX,ARX_BRX + +PLAYV2: AR_ARX+V2CTR,SKP AD0 +=0 V2CTR_AR,BRX/ARX,ARX_BRX*2,J/PLAYQ2 + BRX/ARX,ARX_BRX*2+1 + BRX/ARX,ARX_BRX,J/PLAYZ2 +=0 +PLAYX2: V2CTR_AR,J/PLAYV3 +PLAYZ2: AR_AR+V2TIM,SKP AD0,J/PLAYX2 +PLAYQ2: BRX/ARX,ARX_BRX + +PLAYV3: AR_ARX+V3CTR,SKP AD0 +=0 V3CTR_AR,BRX/ARX,ARX_BRX*2,J/PLAYQ3 + BRX/ARX,ARX_BRX*2+1 + BRX/ARX,ARX_BRX,J/PLAYZ3 +=0 +PLAYX3: V3CTR_AR,J/PLAYV4 +PLAYZ3: AR_AR+V3TIM,SKP AD0,J/PLAYX3 +PLAYQ3: BRX/ARX,ARX_BRX + +PLAYV4: AR_ARX+V4CTR,SKP AD0 +=0 V4CTR_AR,BRX/ARX,ARX_BRX*2,J/PLAYQ4 + BRX/ARX,ARX_BRX*2+1 + BRX/ARX,ARX_BRX,J/PLAYZ4 +=0 +PLAYX4: V4CTR_AR,J/PLAYV5 +PLAYZ4: AR_AR+V4TIM,SKP AD0,J/PLAYX4 +PLAYQ4: BRX/ARX,ARX_BRX + +PLAYV5: AR_ARX+V5CTR,SKP AD0 +=0 V5CTR_AR,BRX/ARX,ARX_BRX*2,J/PLAYQ5 + BRX/ARX,ARX_BRX*2+1 + BRX/ARX,ARX_BRX,J/PLAYZ5 +=0 +PLAYX5: V5CTR_AR,J/PLAYV6 +PLAYZ5: AR_AR+V5TIM,SKP AD0,J/PLAYX5 +PLAYQ5: BRX/ARX,ARX_BRX + +PLAYV6: AR_ARX+V6CTR,SKP AD0 +=0 V6CTR_AR,BRX/ARX,ARX_BRX*2,AR_ARX,J/PLAYQ6 + BRX/ARX,ARX_BRX*2+1 + BRX/ARX,ARX_BRX,J/PLAYZ6 +=0 +PLAYX6: V6CTR_AR,J/PLAY40 +PLAYZ6: AR_AR+V6TIM,SKP AD0,J/PLAYX6 +PLAYQ6: BRX/ARX,ARX_BRX + +PLAY40: AR_BRX,ARX_AR SWAP + MUSBT2_AR + AR_ARX+CHDTIM,SKP AD0 +=0 CHDTIM_AR,J/PIDONE + AR_MUSAOB+1,GEN CRY18,SKP AD0 +=0 J/PICY2V + VMA_AR,LOAD ARX + AR_AR+1,GEN CRY18 + MUSAOB_AR + ARX_MEM + VMA_VMA+1,LOAD AR + AR_MEM + CHDTIM_AR + P_P OR #,#/40,STORE + MEM_AR,AR_0S,SC_#,#/6 + + V1CTR_AR,ARX_SHIFT,AR_ARX (AD) + VMA_ARX+FM,V1BR,ARX_SHIFT,LOAD AR + AR_MEM + V1TIM_AR,AR_0S + + V2CTR_AR,ARX_SHIFT,AR_ARX (AD) + VMA_ARX+FM,V2BR,ARX_SHIFT,LOAD AR + AR_MEM + V2TIM_AR,AR_0S + + V3CTR_AR,ARX_SHIFT,AR_ARX (AD) + VMA_ARX+FM,V3BR,ARX_SHIFT,LOAD AR + AR_MEM + V3TIM_AR,AR_0S + + V4CTR_AR,ARX_SHIFT,AR_ARX (AD) + VMA_ARX+FM,V4BR,ARX_SHIFT,LOAD AR + AR_MEM + V1TIM_AR,AR_0S + + V5CTR_AR,ARX_SHIFT,AR_ARX (AD) + VMA_ARX+FM,V5BR,ARX_SHIFT,LOAD AR + AR_MEM + V1TIM_AR,AR_0S + + V6CTR_AR,ARX_SHIFT,AR_ARX (AD) + VMA_ARX+FM,V6BR,ARX_SHIFT,LOAD AR + AR_MEM + V6TIM_AR,J/PIDONE + +.ENDIF/MUSIC + \ No newline at end of file diff --git a/src/ucode/muzak.2 b/src/ucode/muzak.2 new file mode 100755 index 00000000..12467694 --- /dev/null +++ b/src/ucode/muzak.2 @@ -0,0 +1,4 @@ +.TOC "PARAMETER FILE FOR MUSIC MICROCODE" + +.SET/MUSIC=1 + \ No newline at end of file diff --git a/src/ucode/shift.6 b/src/ucode/shift.6 new file mode 100755 index 00000000..72f38d72 --- /dev/null +++ b/src/ucode/shift.6 @@ -0,0 +1,209 @@ +.TOC "ROTATES AND LOGICAL SHIFTS -- ROT, LSH, JFFO" + + .DCODE +240: I, B/0, J/ASH + I, B/0, J/ROT + I, B/2, J/LSH + I, J/JFFO + I, B/1, J/ASHC + I, J/ROTC + I, J/LSHC +.IFNOT/CIRC + I, J/UUO +.IF/CIRC + I, J/CIRC +.ENDIF/CIRC + .UCODE + +;ENTER WITH 0,E IN AR +; NOTE THAT VALUES OF SC GREATER THAN 36 +; CAUSE THE SHIFTER TO SELECT ARX. + +=00***0 +LSH: AR_AC0,ARL/AD,ARX_0.M,SC_EA, + SKP AR18,J/SHR1 + +JFFO: AR_AC0,SKP AD NE,SC_#,#/6 += +=0 AC1_AR,I FETCH,J/NOP ;AC WAS ZERO, NO JUMP + ARX+MQ_0.M,FE_P,SKP SCAD NE, ;TEST FIRST 6 BITS + AR_SHIFT,ARL/SH ;DISCARD THEM +=1****0 +JFFO1: AR_SHIFT,FE_P,SKP SCAD NE, ;TEST NEXT 6 BITS + ARX_ARX-1,J/JFFO1 ;LOOP, COUNTING, TILL NE + P_FE,ARR_0.S, ;RESTORE 6 NON-ZERO BITS + ARX_ARX*-6 ;GET POS GROUP COUNT*6 +=*1***0 +JFFO2: SKP AR0,AR_2(AR+1), ;LOOP TO FIND A 1 + ARX_ARX+1,J/JFFO2 ;COUNTING AS WE GO +.IFNOT/JPC + AR_ARX-1,FETCH,J/STRAC1 +.IF/JPC + AR_ARX-1,FETCH,SKP USER +=0 AC1_AR,AR_PC,SC_#,#/32.,J/JPCEX + AC1_AR,AR_PC,SC_#,#/32.,J/JPCUSR +.ENDIF/JPC + +=00***0 +ASH: SC_EA,SKP AR18, ;GET SHIFT AMOUNT + AR_0S,J/ASHL ;SET LOW PART = 0 +ROT: AR_AC0,ARX_AC0,SC_EA,SKP AR18 += +;SINGLE-WORD LSH/ROT +; FOR ROT, B=0, AR AND ARX BOTH CONTAIN AC +; FOR LSH, B=2, AR HAS AC, ARX IS ZERO + +=00 +SHR1: AR_SHIFT,SC_#+SC,#/-36., ;DO POS (LEFT) SHIFT, CHK RANGE + SKP SCAD0,J/SHR2 + ARX_AR (AD),AR_ARX (ADX), + SC_#+SC,#/36., + B DISP,SKP SCAD0,J/SHR1 ;MAKE NEG SHIFT TO EQUIV POS +SHR2: AR_SHIFT,SC_#+SC,#/-36., + SKP SCAD0,J/SHR2 ;BRING SC INTO RANGE + AC0_AR,I FETCH,J/NOP ;DONE + .TOC "ROTATE AND LOGICAL SHIFT COMBINED -- ROTC, LSHC" + +=00***0 +ASHC: SC_EA,SKP AR18, ;SETUP SHIFT COUNT + AR_AC1*2,J/ASHL ;GET LOW WORD +ROTC: ARX_AC1 += AR_AC0,SC_EA,SKP AR18 ;SETUP BOTH AC'S +=1****0 +ROT3: MQ_SHIFT,ARX_AR (AD), + AR_ARX (ADX),J/ROT4 + ARX_AR (AD),AR_ARX (ADX), + SC_#+SC,#/36.,SKP SCAD0,J/ROT3 + +ROT4: AR_MQ,ARX_SHIFT, + SC_#+SC,#/-36.,SKP SCAD0 +=0 MQ_SHIFT,ARX_AR (AD), + AR_ARX (ADX),J/ROT4 +STDAC: AC0_AR,AR_ARX,I FETCH,J/STRAC1 + + +.IFNOT/CIRC +1004: ;NEXT TO UUO +.IF/CIRC +=00**00 +.ENDIF/CIRC +LSHC: ARX_AC1,MQ_0.M,J/LSHC1 +.IF/CIRC +=01 +CIRC: MQ_AR,AR_AC1,FE_#,SC_#,#/35.,CLR ARX,CALL,J/WDREV +=11 SC_EA,AR_AC0,SKP AR18,J/CIRC3 +.ENDIF/CIRC += +LSHC1: AR_AC0,SC_EA,FE_#,#/36.,SKP AR18 +=*1***0 +LSH2: MQ_SHIFT,AR_ARX (ADX), + ARX/MQ,FE_#,#/-36.,J/LSH3 + ARX_AR (AD),AR_0.M,MQ_ARX, + SC_FE+SC,SKP SCAD0,J/LSH2 + +LSH3: AR_MQ,ARL/AD,ARX_SHIFT,MQ_0.M, + SC_FE+SC,SKP SCAD0 +=0 MQ_SHIFT,AR_ARX (ADX),ARX/MQ,J/LSH3 + AC0_AR,AR_ARX,I FETCH,J/STRAC1 + .TOC "CIRC INSTRUCTION" + +.IF/CIRC +=1****0 +CIRC3: MQ_SHIFT,ARX_AR (AD),AR_ARX (ADX),J/CIRC4 + ARX_AR (AD),AR_ARX (ADX),SC_#+SC,#/36.,SKP SCAD0,J/CIRC3 + +CIRC4: AR_MQ,ARX_SHIFT,SC_#+SC,#/-36.,SKP SCAD0 +=1***00 + MQ_SHIFT,ARX_AR (AD),AR_ARX (ADX),J/CIRC4 + AC0_AR,AR_ARX,FE_#,SC_#,#/35.,ARX_0S,CALL,J/WDREV +=11 AR_ARX,CLR SC,I FETCH,J/STD1 + + +;SUBROUTINE TO REVERSE A WORD IN AR, RETURNING IT IN ARX. +;ON ENTRY, ARX MUST BE CLEAR, AND SC AND FE MUST BOTH CONTAIN 35. +;ON EXIT, MQ IS COPIED INTO AR. + +.IFNOT/CIRC.BIG.OPT +=*1***0 +WDREV: BRX/ARX,SH DISP,J/WDREV1 + AR_MQ,RETURN2 +=1*0111 +WDREV1: FE_FE-1,SC/SCAD,SKP SCAD0,ARX_BRX*2,J/WDREV + FE_FE-1,SC/SCAD,SKP SCAD0,ARX_BRX*2+1,J/WDREV +.IF/CIRC.BIG.OPT +=1****0 +WDREV: SH DISP,BR/AR,AR_ARX (ADX),SC_#,#/32.,J/WDREV1 + AR_MQ,RETURN2 + +=1*0000 +WDREV1: AR_BR,ARX_SHIFT,FE_FE-#,#/4,SC/SCAD,SKP SCAD0,J/WDREV + AR_SHIFT,SC_#,#/10,J/WDREV2 + AR_SHIFT,SC_#,#/4,J/WDREV2 + AR_SHIFT,SC_#,#/14,J/WDREV2 + AR_SHIFT,SC_#,#/2,J/WDREV2 + AR_SHIFT,SC_#,#/12,J/WDREV2 + AR_SHIFT,SC_#,#/6,J/WDREV2 + AR_SHIFT,SC_#,#/16,J/WDREV2 + AR_SHIFT,SC_#,#/1,J/WDREV2 + AR_SHIFT,SC_#,#/11,J/WDREV2 + AR_SHIFT,SC_#,#/5,J/WDREV2 + AR_SHIFT,SC_#,#/15,J/WDREV2 + AR_SHIFT,SC_#,#/3,J/WDREV2 + AR_SHIFT,SC_#,#/13,J/WDREV2 + AR_SHIFT,SC_#,#/7,J/WDREV2 + AR_SHIFT,SC_#,#/17,J/WDREV2 + +WDREV2: AR0-5_AR0-5 OR SC + AR_BR,ARX_AR,FE_FE-#,#/4,SC/SCAD,SKP SCAD0,J/WDREV +.ENDIF/CIRC.BIG.OPT +.ENDIF/CIRC + .TOC "ARITHMETIC SHIFTS -- ASH, ASHC" + +;COMMON CODE FOR ARITHMETIC SHIFTS + +=*1***0 +ASHL: ARX_AR,AR_AC0, ;INPUT NOW IN AR LONG + SKP SC NE,J/ASHL1 ;CHECK FOR NULL SHIFT + ARX_AR,AR_AC0, ;HERE IF RIGHT SHIFT + SC_#+SC,#/36.,SKP SCAD0 ;CHECK FOR LONG ONE +=1****0 +ASHR1: BR/AR,ARX_SHIFT,AR_SIGN,J/ASHR2 ;LOW OUTPUT TO ARX + ARX_AR,AR_SIGN, ;HERE IF SHIFT COUNT .GT. 36 + SC_#+SC,#/36., ;BRING COUNT UP BY 36 + SKP SCAD0,J/ASHR1 ;LOOP TILL COUNT REASONABLE + +ASHR2: BRX/ARX,ARX_BR, ;HIGH INPUT TO ARX + B DISP,J/ASHX + +;HERE FOR LEFT ARITHMETIC SHIFT + +=*1***0 +ASHL1: I FETCH,J/NOP ;SHIFT 0 IS A NOP + BR_AR LONG,AR_SIGN ;SAVE INPUT, GEN SIGN WORD + BR/AR,AR_BR*2 LONG ;SAVE SIGN, GET MAGNITUDE BITS +=0* +ASHL2: BRX/ARX,ARX_AR,AR_BR, ;HI IN TO ARX, LOW TO BRX + CALL,J/SHIFT ;CALL SHIFTER TO GET BITS LOST + SKP AR SIG ;ANY SIGNIFICANT BITS? +=1****0 +ASHL3: AR_ARX,ARX_BRX, ;RESTORE HI TO AR, LOW TO ARX + GEN #+SC,#/-36.,SKP SCAD0,J/ASHL4 + SET AROV,J/ASHL3 ;BITS SHIFTED OUT NE SIGN +=*1***0 +ASHL4: AR_ARX,ARX_0S, ;HERE IF E .GT. 36 + SC_#+SC,#/-36.,J/ASHL2 ;SHIFT 36 PLACES, TRY AGAIN + MQ_SHIFT,AR_BRX,CLR ARX, ;HIGH OUTPUT TO MQ, + SC_#+SC,#/-1,B DISP ;COMPENSATE FOR EXTRA SHIFT +=1****0 +ASHL5: AR_BR,BRX/ARX,ARX/MQ, ;SIGN TO AR, HIGH OUT TO ARX + SC_#,#/35., ;READY TO COMBINE THEM + B DISP,J/ASHX ;STORE AS APPROPRIATE + ARX_SHIFT,J/ASHL5 ;LOW OUTPUT TO ARX + +;HERE TO GET FINAL RESULTS. + +=*1***0 +ASHX: AR_SHIFT,I FETCH,J/STORAC ;HERE AFTER ASH + AR_SHIFT,ARX_BRX, ;HERE AFTER ASHC + SC_#,#/35.,J/ST2AC + \ No newline at end of file diff --git a/src/ucode/skpjmp.32 b/src/ucode/skpjmp.32 new file mode 100755 index 00000000..ff1fff9e --- /dev/null +++ b/src/ucode/skpjmp.32 @@ -0,0 +1,957 @@ +.TOC "TEST GROUP" + + .DCODE +600: I-PF, J/TDN ;TRN- IS NOP + I-PF, J/TDN ;SO IS TLN- + I, TNE, J/TDXX + I, TNE, J/TSXX + I, TNA, J/TDX + I, TNA, J/TSX + I, TNN, J/TDXX + I, TNN, J/TSXX + +610: I-PF, J/TDN ;TDN- IS A NOP + I-PF, J/TDN ;TSN- ALSO + R, TNE, J/TDXX + R, TNE, J/TSXX + R, TNA, J/TDX + R, TNA, J/TSX + R, TNN, J/TDXX + R, TNN, J/TSXX + +620: I, TZ-, J/TDX + I, TZ-, J/TSX + I, TZE, J/TDXX + I, TZE, J/TSXX + I, TZA, J/TDX + I, TZA, J/TSX + I, TZN, J/TDXX + I, TZN, J/TSXX + +630: R, TZ-, J/TDX + R, TZ-, J/TSX + R, TZE, J/TDXX + R, TZE, J/TSXX + R, TZA, J/TDX + R, TZA, J/TSX + R, TZN, J/TDXX + R, TZN, J/TSXX + +640: I, TC-, J/TDX + I, TC-, J/TSX + I, TCE, J/TDXX + I, TCE, J/TSXX + I, TCA, J/TDX + I, TCA, J/TSX + I, TCN, J/TDXX + I, TCN, J/TSXX + +650: R, TC-, J/TDX + R, TC-, J/TSX + R, TCE, J/TDXX + R, TCE, J/TSXX + R, TCA, J/TDX + R, TCA, J/TSX + R, TCN, J/TDXX + R, TCN, J/TSXX + 660: I, TO-, J/TDX + I, TO-, J/TSX + I, TOE, J/TDXX + I, TOE, J/TSXX + I, TOA, J/TDX + I, TOA, J/TSX + I, TON, J/TDXX + I, TON, J/TSXX + +670: R, TO-, J/TDX + R, TO-, J/TSX + R, TOE, J/TDXX + R, TOE, J/TSXX + R, TOA, J/TDX + R, TOA, J/TSX + R, TON, J/TDXX + R, TON, J/TSXX + .UCODE + +;THESE 64 INSTRUCTIONS ARE DECODED BY MASK MODE (IMMEDIATE OR MEMORY) +; IN THE A FIELD, DISPATCH TO HERE ON THE J FIELD, AND RE-DISPATCH +; FOR THE MODIFICATION ON THE B FIELD. + +; ENTER WITH 0,E OR (E) IN AR, B FIELD BITS 1 AND 2 AS FOLLOWS: +; 0 0 NO MODIFICATION +; 0 1 ZEROS +; 1 0 COMPLEMENT +; 1 1 ONES +; THIS ORDER HAS NO SIGNIFICANCE EXCEPT THAT IT CORRESPONDS TO THE +; ORDER OF INSTRUCTIONS AT TGROUP. + +;THE HIGH ORDER BIT OF THE B FIELD (B0) IS XOR'D WITH AD CRY0 TO +; DETERMINE THE SENSE OF THE SKIP: +; 0 SKIP IF CRY0=1 (TXX- AND TXXN) +; 1 SKIP IF CRY0=0 (TXXA AND TXXE) + +=00*000 +TDX: TEST FETCH,NO CRY, ;TDXA AND TRXA + B DISP,J/TDN + +TSX: AR_AR SWAP,TEST FETCH,NO CRY, ;TSX, TSXA, TLX, AND TLXA + B DISP,J/TDN + +TSXX: AR_AR SWAP ;TSXE, TSXN, TLXE, AND TLXN + +TDXX: TEST AR.AC0,TEST FETCH,B DISP ;TDXE, TDXN, TRXE, AND TRXN + +TDN: J/FINI ;NO MODIFICATION +TDZ: AR_AR*AC0,AD/ANDCA,TIME/2T,J/STAC ;ZEROS +TDC: AR_AR*AC0,AD/XOR,TIME/2T,J/STAC ;COMP +TDO: AR_AR*AC0,AD/OR,TIME/2T,J/STAC ;ONES += + .TOC "COMPARE -- CAI, CAM" + + .DCODE +300: I, SJC-, J/CAIM ;CAI + I, SJCL, J/CAIM + I, SJCE, J/CAIM + I, SJCLE, J/CAIM + I, SJCA, J/CAIM + I, SJCGE, J/CAIM + I, SJCN, J/CAIM + I, SJCG, J/CAIM + +310: R, SJC-, J/CAIM ;CAM + R, SJCL, J/CAIM + R, SJCE, J/CAIM + R, SJCLE, J/CAIM + R, SJCA, J/CAIM + R, SJCGE, J/CAIM + R, SJCN, J/CAIM + R, SJCG, J/CAIM + .UCODE + +=00**** +CAIM: GEN AR*AC0,COMP FETCH,J/NOP += + .TOC "ARITHMETIC SKIPS -- AOS, SOS, SKIP" +;ENTER WITH (E) IN AR + + .DCODE +330: R, SJC-, J/SKIP ;NOT A NOP IF AC .NE. 0 + R, SJCL, J/SKIP + R, SJCE, J/SKIP + R, SJCLE, J/SKIP + R, SJCA, J/SKIP + R, SJCGE, J/SKIP + R, SJCN, J/SKIP + R, SJCG, J/SKIP + .UCODE + +=00**** +SKIP: FIN STORE,SKIP FETCH, + SKP AC#0,J/STSELF ;STORE IN SELF MODE += + + .DCODE +350: RPW, SJC-, J/AOS + RPW, SJCL, J/AOS + RPW, SJCE, J/AOS + RPW, SJCLE, J/AOS + RPW, SJCA, J/AOS + RPW, SJCGE, J/AOS + RPW, SJCN, J/AOS + RPW, SJCG, J/AOS + .UCODE + +=00**** +AOS: AR_AR+1,AD FLAGS,STORE,J/SKIP += + + .DCODE +370: RPW, SJC-, J/SOS + RPW, SJCL, J/SOS + RPW, SJCE, J/SOS + RPW, SJCLE, J/SOS + RPW, SJCA, J/SOS + RPW, SJCGE, J/SOS + RPW, SJCN, J/SOS + RPW, SJCG, J/SOS + .UCODE + +=00**** +SOS: AR_AR-1,AD FLAGS,STORE,J/SKIP += + .TOC "CONDITIONAL JUMPS -- JUMP, AOJ, SOJ, AOBJ" +; ENTER WITH E IN VMA + + .DCODE +320: I, SJC-, J/JUMP + I, SJCL, J/JUMP + I, SJCE, J/JUMP + I, SJCLE, J/JUMP + I, SJCA, J/JUMP + I, SJCGE, J/JUMP + I, SJCN, J/JUMP + I, SJCG, J/JUMP + .UCODE + +=00**** +.IFNOT/JPC +JUMP: AR_AC0,JUMP FETCH,J/NOP +.IF/JPC +JUMP: AR_AC0,JUMP FETCH,B DISP,J/JMPJPC +.ENDIF/JPC += + + .DCODE +340: I, SJC-, J/AOJ + I, SJCL, J/AOJ + I, SJCE, J/AOJ + I, SJCLE, J/AOJ + I, SJCA, J/AOJ + I, SJCGE, J/AOJ + I, SJCN, J/AOJ + I, SJCG, J/AOJ + .UCODE + +=00**** +.IFNOT/JPC +AOJ: AR_AC0+1,AD FLAGS,JUMP FETCH,J/STORAC +.IF/JPC +AOJ: AR_AC0+1,AD FLAGS,JUMP FETCH,J/AOJJPC +.ENDIF/JPC += + + .DCODE +360: I, SJC-, J/SOJ + I, SJCL, J/SOJ + I, SJCE, J/SOJ + I, SJCLE, J/SOJ + I, SJCA, J/SOJ + I, SJCGE, J/SOJ + I, SJCN, J/SOJ + I, SJCG, J/SOJ + .UCODE + +;THE BASIC INSTRUCTION DISPATCH LOADS MQ WITH -1 +;SO THAT WHEN WE GET HERE WE CAN ADD -1 TO THE AC IN +;A SINGLE MICRO-INSTRUCTION. +=00**** +.IFNOT/JPC +SOJ: AR_MQ+AC0,AD FLAGS,JUMP FETCH,J/STORAC +.IF/JPC +SOJ: AR_MQ+AC0,AD FLAGS,JUMP FETCH,J/SOJJPC +.ENDIF/JPC += + .DCODE +252: I, SJCGE, J/AOBJ + I, SJCL, J/AOBJ + .UCODE + +=00**** +.IFNOT/JPC +AOBJ: AR_AC0+1,GEN CRY18,JUMP FETCH,J/STORAC +.IF/JPC +AOBJ: AR_AC0+1,GEN CRY18,JUMP FETCH,J/AOBJPC +.ENDIF/JPC += + .TOC "AC DECODE JUMPS -- JRST, JFCL" + + .DCODE +254: I, J/JRST ;DISPATCHES TO 1 OF 16 ON AC BITS + I,TNN, J/JFCL + .UCODE + +;A READ DETECTS JRST, AND DISPATCHES TO ONE OF 16 LOC'NS ON AC BITS + +600: ;DRAM REQUIRES JRST AT MULTIPLE OF 200 +.IFNOT/JPC +JRST: J/FINI ;(0) A READ PREFETCHES ON JRST 0, +.IF/JPC +JRST: AR_PC,SKP USER, ;(0) A READ PREFETCHES - GO STORE JPC + SC_#,#/32.,J/JPCEX +.ENDIF/JPC +601: +.IFNOT/ITSPAGE + PORTAL,BR/AR,J/BRJMP ;(1) PORTAL +.IF/ITSPAGE + BR/AR,J/BRJMP ;(1) NO PUBLIC PAGES => NO PORTAL +.ENDIF/ITSPAGE +602: +JRST2: EA MOD DISP,BR/AR,AR_ARX, ;(2) JRSTF + SC_#,#/9,J/JRSTF +603: J/UUO ;(3) +604: HALT,SKP IO LEGAL,J/IHALT ;(4) HALT +605: J/UUO ;(5) +606: J/UUO ;(6) +607: J/UUO ;(7) +610: DISMISS,BR/AR,J/BRJMP ;(10) +611: J/UUO ;(11) +612: DISMISS,J/JRST2 ;(12) JEN +613: J/UUO ;(13) +614: J/UUO ;(14) +615: J/UUO ;(15) +616: J/UUO ;(16) +617: +.IFNOT/JRSTON + J/UUO ;(17) +.IF/JRSTON +JRST17: BR/AR,BRX/ARX,AR_1,GEN CRY18, ;(17) JRSTON + ARX/AD,SC_#,#/7,J/JRSTON +.ENDIF/JRSTON + +;JRST AND RESTORE FLAGS HAIR + +=11***0 +JRSTF: AR_PC,RSTR FLAGS_AR,J/JRSTF1 ;RESTORE FROM INDIRECT WORD + AR_XR,J/JRSTF ;INDEXED, RESTORE FROM REGISTER + +;JRST AND RESTORE FLAGS HAIR - ONE-PROCEED VERSION. +;WE HAVE TO PREVENT JRSTF FROM TURNING OFF THE TRAP FLAGS. +;THIS MAKES ONE-PROCEED THROUGH JRST 2, WORK. +;IT DOESN'T HURT ANYTHING BECAUSE THE TRAP FLAGS NEVER NORMALLY +;STAY ON DURING EXECUTION OF AN INSTRUCTION. +;MUST COME TO JRSTF WITH 9 IN SC DUE TO DISP/SPEC & # CONFLICT. +; +;EVEN GROSSER HAIR- IF WE TOOK A PAGE FAULT ON THE INSTRUCTION +;FETCH AT THE NICOND, COULD DO AN ABORT INSTR AND LOSE THE +;TRAP FLAGS. MOSTLY THIS SCREWS ONE-PROCEED, BUT IT COULD +;SCREW OVERFLOW TRAPS IF INTERRUPTED OUT OF THEN THE PAGE +;SWAPPED OUT BEFORE PROGRAM RESUMED. +;TO FIX THIS WE DO 'SR_JRSTF' AND LET THE INSTRUCTION +;CLEAN-UP HANDLER TAKE CARE OF THE FLAGS. + +;YET GROSSER HAIR! IN ORDER TO STORE THE RIGHT JPC, +;JRSTF DOES AR_PC AND THEN THE USER MODE FLAG IN THERE +;IS CHECKED, SINCE THE ONE IN THE HARDWARE HAS BEEN +;CLOBBERED BY THIS TIME. TO AVOID USING # TO DO THIS, +;JRSTF1 HAS TO PUT 1 INTO SC (USER = PC BIT 05 = LOW P BIT) + +.IFNOT/ONE PROCEED +JRSTF1: SR_JRSTF,SC_1,J/BRJRF +.IF/ONE PROCEED +JRSTF1: SR_JRSTF,SC_1,SH DISP,J/BRJRF ;DISPATCH ON OLD TRAP BITS +=1*0011 +.ENDIF/ONE PROCEED +.IFNOT/JPC +BRJRF: +BRJMP: VMA_BR,FETCH,J/NOP +.IF/JPC +BRJRF: VMA_BR,FETCH,GEN P AND SC,SKP SCAD NE,J/JPCEX +.ENDIF/JPC +.IF/ONE PROCEED ;DISP TABLE AFTER BRJRF + TRAP1,J/BRJRF ;TURN TRAP 1 BACK ON + TRAP2,J/BRJRF ;TURN TRAP 2 BACK ON + TRAP3,J/BRJRF ;TURN TRAP 3 BACK ON +.ENDIF/ONE PROCEED +.IF/JPC +BRJMP: VMA_BR,FETCH,J/JPCIFY +.ENDIF/JPC + +.IF/JRSTON +;OKAY TO DO THIS INSTR IN USER MODE, SINCE WHEN IN +; USER MODE THE PI SYSTEM SHOULD BE ON ANYWAY. +;THIS INSTRUCTION IS USEFUL IN CONJUNCTION WITH THE +; PFAIL.PIHACK BUSINESS. +=*1**00 +JRSTON: AR_SHIFT,ARX_BRX,REQ EBUS,CALL,J/WGRANT ;GOBBLE EBUS +=11 CONO PI ;TURN ON PI SYSTEM +.IF/ONE PROCEED + SC_#,#/9 ;SET UP SC FOR JRSTF +.ENDIF/ONE PROCEED + REL EBUS,AR_ARX, ;RELEASE EBUS, THEN + EA MOD DISP,J/JRSTF ; GO DO A JRSTF +.ENDIF/JRSTON + + +700: ;JFCL MUST BE AT JRST+100 +JFCL: ARX_BRX,SC_#,#/13. ;GET BACK AC FIELD +=1***0* + AR_SHIFT,ARX_0S, ;MOVE AC TO AR32-35 + SC_#,#/32.,CALL,J/SHIFT ;SHIFTER WILL MOVE TO 0-3 + BR/AR,AR_PC,JFCL T ;GET PC FLAGS INTO AR +.IFNOT/JPC + TEST AR.BR,JFCL FETCH ;JUMP IF TEST SATISFIED + AR_AR*BR,AD/ANDCB ;CLEAR TESTED FLAGS IN AR + JFCL S,J/FINI ;SET PC FROM THEM +.IF/JPC + ARX_AR*BR,AD/ANDCB,SC_#,#/32. ;SET UP SC FOR JPC RING + TEST AR.BR,JFCL FETCH,AR_ARX,SKP CRY0 +=*1***0 + JFCL S,J/FINI ;NO JUMP, ALL DONE + JFCL S,AR_PC,SKP USER,J/JPCEX ;JUMP, GO RECORD JPC +.ENDIF/JPC + .TOC "HALT LOOP" +;HERE WHILE PROCESSOR IS "HALTED" + +1016: +UUO107: ;OP 107 COMES HERE +IHALT: J/UUO ;HERE IF HALT IN USER/SUPER MODE +1017: +DHALT: AR_0S,SET HALTED, ;KERNEL OR CONSOLE HALT + VMA/PC,PC_VMA ; IF JRST 4, COPY EA TO PC +=1****0 +HALT1: SKP -START,TIME/3T, ;CHECK FOR CONTINUE BUTTON + FE_AR0-8,ARX_AR,J/HALT2 ;PICK UP OPCODE IN CASE XCT + TAKE INTRPT ;HERE IF EXAMINE/DEPOSIT UP +=1****0 +HALT2: GEN FE-1,BYTE DISP,CONTINUE,J/UNHALT ;INSTR FROM SWITCHES? + SKP INTRPT,J/HALT1 +=110 +UNHALT: SET CONS XCT,J/UXCT ;XCT ONE FROM "SWITCHES" + SKP AR EQ,J/START ;NOT AN INSTR. START, OR CONT? + + +.TOC "MAP, XCT" + + .DCODE +256: R, J/XCT ;OPERAND FETCHED AS DATA +.IF/MAP + I, AC, J/MAP +.IFNOT/MAP + J/UUO +.ENDIF/MAP + .UCODE + +.IF/MAP +=00***0 +.IFNOT/MAP +1001: ;GET XCT NEAR UUO +.ENDIF/MAP +.IFNOT/XCTR +XCT: SKP INTRPT,J/XCT1 ;CHECK FOR XCT . LOOP +.IF/XCTR +XCT: SKP INTRPT,J/UXCT ;CHECK FOR XCT LOOP +.ENDIF/XCTR + +.IF/MAP +MAP: MAP,BR/AR ;MAP E, GO READ BACK EBRG += +.IF/KLPAGE ;IN KL PAGING MODE, + SR_MAP ;MAP CAN PAGE FAIL +.ENDIF/KLPAGE +.IFNOT/MAP +.IFNOT/XCTR += +.ENDIF/XCTR +.ENDIF/MAP +=11***0 +RDEBRG: AR_0S,SKP IO LEGAL,MB WAIT, ;FINISH READ REG FUNC + CALL,J/GETEEB ;AND GET EBUS + AR_EBUS REG ;READ DATA + REL ECL EBUS,B WRITE,J/ST6 ;GIVE IT TO USER + .TOC "ITS PAGE MAP INSTRUCTIONS -- LPM, SPM" + +;THE WORDS LOADED OR STORED BY LPM AND SPM ARE AS FOLLOWS: +; (E) JPC (OR JPC RING POINTER) +; (E+1) ADDRESS BREAK WORD +; (E+2) PFW AS OF MOST RECENT PAGE FAIL +; (E+3) DBR1 +; (E+4) DBR2 + +.IF/LPM.SPM +=00**00 +LPM: ARX_AR,VMA_VMA+1,LOAD AR,J/LPM1 ;ARX_JPC,FETCH MAR + +=10 +SPM: CALL,SKP KERNEL,J/IOCHK ;SPM OKAY ONLY IN KERNEL MODE +.IFNOT/JPC SUPPORT + VMA_VMA+1 += +.IF/JPC SUPPORT + AR_JPC,STORE += MEM_AR,VMA_VMA+1 +.ENDIF/JPC SUPPORT + AR_UPFW,STORE,VMA_VMA+1 + MEM_AR,VMA_VMA+1 + AR_DBR1,STORE + MEM_AR,VMA_VMA+1 + AR_DBR2,STORE,J/STMEM + +=11***0 +LPM1: AR_MEM,CALL,SKP KERNEL,J/GETEEB ;LPM LEGAL ONLY IN KERNEL MODE + DATAO APR + REL ECL EBUS,AR_ARX +.IF/JPC SUPPORT + JPC_AR +.ENDIF/JPC SUPPORT + VMA_VMA+1,LOAD AR + AR_MEM,VMA_VMA+1 + BAG-BITING NO-OP + UPFW_AR,LOAD AR + AR_MEM,VMA_VMA+1 + BAG-BITING NO-OP + DBR1_AR,LOAD AR + AR_MEM + BAG-BITING NO-OP + DBR2_AR,J/CLRPT1 ;REALLY LPMR - CLEAR PAGE TABLE +.ENDIF/LPM.SPM + .TOC "STACK INSTRUCTIONS -- PUSHJ, PUSH, POP, POPJ" + + .DCODE +260: I, J/PUSHJ + R, B/0, J/PUSH + W, J/POP + I, J/POPJ + .UCODE + +;PUSHJ +; ENTER WITH E IN AR +;PUSH +; ENTER WITH (E) IN AR + +=00***0 +PUSH: ARX_AC0+1,GEN CRY18,SKP CRY0, ;BUMP BOTH HALVES OF AC, + VMA/AD,STORE,J/STMAC ;PUT AR ONTO LIST + +PUSHJ: BR/AR,AR_PC+1 ;SAVE JUMP ADDR, GET PC += ARX_AC0+1,GEN CRY18,SKP CRY0, ;COMPUTE STACK ADDRESS + VMA/AD,STORE,J/JSTAC ;AND PREPARE TO STORE PC +=*1**00 +JRA1: VMA_AR,LOAD ARX,CALL,J/XFERW ;GET SAVED AC +=10 +.IFNOT/JPC +JSTAC: FIN STORE,VMA_BR,FETCH, ;STORE PC, JUMP ADDR TO VMA + AR_ARX,J/STORAC ;PREPARE TO STORE AC VALUE +.IF/JPC +JSTAC: FIN STORE,VMA_BR,FETCH, ;STORE AC, THEN RECORD JPC + AR_ARX,SKP USER,J/JPCSTO +.ENDIF/JPC + MEM_AR,TRAP2,J/JSTAC ;CAUSE PDL OVRFLO + +=1****0 +STMAC: FIN STORE,I FETCH, ;STORE RESULT, GET NEXT INSTR + AR_ARX,B DISP,J/STSELF ;STORE AC IF B=0 + MEM_AR,TRAP2, ;PDL OVFLO, CAUSE TRAP + AR_ARX,J/IFSTAC ;UPDATE AC BEFORE TRAPPING + + +;POP, POPJ + +=00***0 +;ENTER WITH C(AC) IN AR, E IN BR, OK TO WRITE IN E +POP: VMA_AR,LOAD ARX,J/POP1 ;BEGIN DATA FETCH FROM STACK + +;ENTER WITH E IN AR +POPJ: AR_AC0,VMA/AD,LOAD ARX ;START FETCH FROM STACK += AR_AR-1,INH CRY18,SKP CRY0 ;DECR STACK POINTER, CHECK UNDERFLOW +.IFNOT/JPC.RING +=*1***0 + ARX_MEM,TRAP2,J/POPJ1 ;UNDERFLOW OCCURRED + ARX_MEM ;GET STACK WORD +.IFNOT/JPC +POPJ1: AC0_AR,VMA_ARX,FETCH,J/NOP ;SET NEW AC VALUE, JUMP +.IF/JPC +POPJ1: AC0_AR,VMA_ARX,FETCH,J/JPCIFY +.ENDIF/JPC +.IF/JPC.RING +=*1***0 + ARX_MEM,TRAP2 ;TWO TICKS SLOWER ON OVERFLOW, BUT WHO CARES? + ARX_MEM,SKP USER,SC_#,#/32. ;JPC.RING NEEDS 32. IN SC + AC0_AR,VMA_ARX,FETCH,J/JPCEX + AC0_AR,VMA_ARX,FETCH,J/JPCUSR +.ENDIF/JPC.RING + + +POP1: AR_AR-1,INH CRY18,SKP CRY0 ;ADJUST POINTER, CHECK TRAP +=*1***0 + ARX_MEM,TRAP2 ;PDL OVFLO, CAUSE TRAP + ARX_MEM,SR_#,#/100 ;SET DEST CONTEXT FLAG + AR_ARX,AC0_AR, ;FIRST STORE AC + VMA_BR,STORE,J/STMEM ;THEN MEMORY + + ;PUT RESULT AWAY, THEN AC + .TOC "SUBROUTINE CALL/RETURN -- JSR, JSP, JSA, JRA" + + .DCODE +264: I, J/JSR + I, J/JSP + I, J/JSA + I, J/JRA + .UCODE + +=00***0 +.IFNOT/JPC +JSP: AR_PC+1,FETCH,J/STORAC +.IF/JPC +JSP: AR_PC+1,FETCH,SKP USER,J/JPCSTO +.ENDIF/JPC + +JSR: AR_PC+1,STORE += +.IFNOT/JPC + FIN STORE,VMA_VMA+1,FETCH,J/NOP +.IF/JPC + FIN STORE,VMA_VMA+1,FETCH,J/JPCIFY +.ENDIF/JPC + +=00***0 +JSA: ARX_AR SWAP,AR_AC0,STORE,J/JSA1 ;SAVE E IN ARX LEFT, GET AC + +JRA: BR/AR,AR_AC0 ;GET AC, SAVE JUMP ADDR += ARR_ARL,ARL_0.M,J/JRA1 ;GET AC LEFT + +JSA1: FIN STORE,VMA_VMA+1,FETCH ;JUMP TO E+1 +.IFNOT/JPC + ARR_PC+1,ARL_ARXL,J/STAC ;PC+1,,E GOES TO AC +.IF/JPC + ARR_PC+1,ARL_ARXL,SKP USER,J/JPCSTO +.ENDIF/JPC + .TOC "UUO'S" +;LUUO'S TRAP TO CURRENT CONTEXT +; EXTENDED INSTRUCTION SET IS "HIDDEN" BENEATH LUUO OPCODES + + .DCODE +000: I, J/UUO +.IF/EIS + I, SJCL, J/L-CMS ;CMSL HIDDEN BENEATH LUUO + I, SJCE, J/L-CMS + I, SJCLE, J/L-CMS + I, B/2, J/L-EDIT ;EDIT HIDDEN UNDER 004 + I, SJCGE, J/L-CMS + I, SJCN, J/L-CMS + I, SJCG, J/L-CMS + +.IF/DECIMAL +010: I, B/1, J/L-DBIN ;CVTDBO + I, B/4, J/L-DBIN ;CVTDBT + I, B/1, J/L-BDEC ;CVTBDO + I, B/0, J/L-BDEC ;CVTBDT +.IFNOT/DECIMAL +010: I, J/LUUO + I, J/LUUO + I, J/LUUO + I, J/LUUO +.ENDIF/DECIMAL + +014: I, B/1, J/L-MVS ;MOVSO + I, B/0, J/L-MVS ;MOVST + I, B/2, J/L-MVS ;MOVSLJ + I, B/3, J/L-MVS ;MOVSRJ +.IFNOT/EIS + I, J/LUUO + I, J/LUUO + I, J/LUUO + +004: I, J/LUUO + I, J/LUUO + I, J/LUUO + I, J/LUUO + +010: I, J/LUUO + I, J/LUUO + I, J/LUUO + I, J/LUUO + +014: I, J/LUUO + I, J/LUUO + I, J/LUUO + I, J/LUUO +.ENDIF/EIS + ;USER UUO'S 20-37 + +020: I, J/LUUO + I, J/LUUO + I, J/LUUO + I, J/LUUO + +024: I, J/LUUO + I, J/LUUO + I, J/LUUO + I, J/LUUO + +030: I, J/LUUO + I, J/LUUO + I, J/LUUO + I, J/LUUO + +034: I, J/LUUO + I, J/LUUO + I, J/LUUO + I, J/LUUO + ;MONITOR UUO'S -- TRAP TO EXEC + +040: I, J/MUUO ;CALL + I, J/MUUO ;INIT + I, J/MUUO + I, J/MUUO + I, J/MUUO + I, J/MUUO + I, J/MUUO + I, J/MUUO ;CALLI + I, J/MUUO ;OPEN + I, J/MUUO ;TTCALL + I, J/MUUO + I, J/MUUO + I, J/MUUO + I, J/MUUO ;RENAME + I, J/MUUO ;IN + I, J/MUUO ;OUT +.IFNOT/JPC TEST + I, J/MUUO ;SETSTS + I, J/MUUO ;STATO + I, J/MUUO ;GETSTS + I, J/MUUO ;STATZ + I, J/MUUO ;INBUF + I, J/MUUO ;OUTBUF + I, J/MUUO ;INPUT + I, J/MUUO ;OUTPUT +.IF/JPC TEST + I, SJC-, J/TJMP + I, SJCL, J/TJMP + I, SJCE, J/TJMP + I, SJCLE, J/TJMP + I, SJCA, J/TJMP + I, SJCGE, J/TJMP + I, SJCN, J/TJMP + I, SJCG, J/TJMP +.ENDIF/JPC TEST + + +.IFNOT/LISP + I, J/MUUO ;CLOSE + I, J/MUUO ;RELEAS +.IF/LISP + I, J/LSPGCM ;LSPGCM (OPCODE 070) + I, J/LSPGCS ;LSPGCS (OPCODE 071) +.ENDIF/LISP + I, J/MUUO ;MTAPE + I, J/MUUO ;UGETF +.IFNOT/XCTR + I, J/MUUO ;USETI + I, J/MUUO ;USETO +.IF/XCTR + R, J/PXCT ;PXCT FOR ITS (OPCODE 074) + R, J/PXCT ;PXCTI FOR ITS (OPCODE 075) +.ENDIF/XCTR +.IFNOT/LPM.SPM + I, J/MUUO ;LOOKUP + I, J/MUUO ;ENTER +.IF/LPM.SPM + R, J/LPM ;LOAD PAGE MAP (OPCODE 076) + W, J/SPM ;STORE PAGE MAP (OPCODE 077) +.ENDIF/LPM.SPM + +;EXPANSION OPCODES + +100: +.IFNOT/LISP + I, J/UUO ;UJEN + I, J/UUO +.IF/LISP + I, J/LSPDBG ;LSPDBG (OPCODE 100, TEMP) + I, J/LSP101 +.ENDIF/LISP + I, J/UUO + I, J/UUO + .UCODE + ;HERE FOR UNDEFINED OPS (UUO'S) AND ILLEGAL INSTRUCTIONS +;E IS IN AR, OPCODE AND AC IN BRX + +1002: ;FIXED ADDRESS TO COOPERATE + ;WITH EXTEND AND OTHER OPS +UUO: ;UNDEFINED OP'S .GE. 100 +MUUO: ARX_BRX,SC_#,#/13., + SKP INTRPT,CALL,J/ROTS +1003: AR_SHIFT,VMA_#,#/424,J/MUUO1 + +;HERE ON LUUO'S +; E IN AR, INSTR IN BRX +1005: +.IFNOT/EIS +FIX: FE_EXP-#,#/244,SKP SCAD0, ;GET BINARY POINT POSITION + ARX_AR SIGN,J/FIX1 ;SET ROUNDING CONSTANT, GO FIX +.IF/EIS +L-CMS: J/LUUO ;LOC FOR HIDING STRING COMPARE +.ENDIF/EIS +1006: +.IF/EIS +L-EDIT: ;HIDE EDIT HERE +.ENDIF/EIS +LUUO: ARX_BRX,SC_#,#/13., + CALL,SKP INTRPT,J/ROTS ;COMBINE E WITH UUO +1007: AR_SHIFT,VMA_40,STORE ;STORE OPCODE ETC AT 40 + FIN STORE,VMA_41, + LOAD ARX,J/XCTW ;GO PERFORM 41 + +.IF/EIS +.IF/DECIMAL +1010: +L-DBIN: J/LUUO ;DBIN AT 2010 +1011: +L-BDEC: J/LUUO ;BDEC AT 2011 +.ENDIF/DECIMAL +1012: +L-MVS: J/LUUO ;MOVE STRING AT 2012 +.ENDIF/EIS + +.IF/JPC TEST +=00**** +TJMP: AR_AC0,JUMP FETCH,B DISP,J/JMPJPC +.ENDIF/JPC TEST + +.IF/LISP +=00***0 +LSPGCM: BR/AR,MQ_AR,AR_GCSTBR,SKP AD NE,J/LGCM0 ;START OF GC MARK INSTR +LSPGCS: BR/AR,SC_EA,AR_GCSTBR,SKP AD NE,J/LGCS0 ;START OF GC SWEEP INSTR += +=00***0 +LSPDBG: AR_GCSTBR,J/LSPDB1 +LSP101: J/UUO += +.ENDIF/LISP + ;HERE ON MUUO'S +; E IN AR, OP AND AC IN BRX + +;MUUO: ARX_BRX,SC_#,#/13.,CALL,J/ROTS +; AR_SHIFT,VMA_#,#/424 +MUUO1: STORE,UPT REF ;FIRST, STORE INSTRUCTION + FIN STORE,AR_PC+1,VMA_VMA+1,STORE ;NEXT, PC +=11**00 + MEM_AR,VMA_VMA+1,SC_#,#/70, + CALL,J/GTEEB1 + DATAI PAG(L),CALL,J/PCTXT ;GET PROCESS CONTEXT VARIABLES +=11 LD PREV CTXT ;PCS FROM PC, CWSX FROM SXCT + AR_SHIFT,ARL_BRL.S, ;COMBINE UBR WITH AC BLKS, CWSX + STORE, ; STORE THAT AT 426 + COND/EBUS CTL,EBUS CTL/2; & RELEASE ECL EBUS + MEM_AR,VMA_430+MODE ;NOW READY TO GET NEW PC + LOAD AR,UPT REF ;FETCH NEW PC +NEWPC: AR_MEM,SR_0,J/START ;USE IT + + +;ROTATE SUBROUTINE + +=11***0 +ROTS: AR_SHIFT,ARX_SHIFT,SC_#-SC,#/36.,RETURN3 + TAKE INTRPT ;FIXES LUUO IN USER 41 LOOP BUG + .TOC "JSYS, ADJSP" + + .DCODE +104: +.IFNOT/MVSQZ + I, J/UUO ;JSYS +.IF/MVSQZ + R, J/MVSQZ +.ENDIF/MVSQZ + I, B/0, J/ADJSP + .UCODE + +;HERE FOR ADJSP INSTRUCTION +; ENTER WITH E IN AR, PREFETCH IN PROGRESS + +.IFNOT/MVSQZ +1000: ;PUT ADJSP NEXT TO UUO +.IF/MVSQZ +=00***0 +MVSQZ: FE_#,#/5,ARX_0S,MQ_MQ*.25, ;FE COUNTS LOOP, CLEAR MQ00, + J/MVSQZ0 ;ARX ACCUMULATES SQUOZE +.ENDIF/MVSQZ +ADJSP: ARL_ARR,ARR_ARR ;PUT E IN BOTH HALVES += AR_AR*AC0,AD/A+B,INH CRY18, ;ADJUST POINTER, + ARX/AD,SKP AR0 ;SKIP IF NEGATIVE +=0 GEN AR*AC0,AD/ANDCA, ;TEST FOR - TO + CHANGE + SKP AD0,J/STMAC + GEN AR*AC0,AD/ANDCB, ;TEST FOR + TO - CHANGE + SKP AD0,J/STMAC + + +.IF/MVSQZ +=1****0 +MVSQZ0: ARX_ARX*8,GEN P-#,#/41, + SKP SCAD0,J/MVSQZ1 + AR_ARX,I FETCH,J/STORAC +=1****0 +MVSQZ1: P_P-#,#/26,ARX_ARX*5,J/MVSQZ5 + GEN P-#,#/20,ARX_ARX*5, + SKP SCAD0 +=1****0 + P_P-#,#/17,J/MVSQZ5 + GEN P-#,#/16,SKP SCAD NE +=1****0 + P_#,#/45,J/MVSQZ5 + GEN P-#,#/1,SKP SCAD0 +=1****0 + P_P+#,#/42 +MVSQZ5: BR/AR,BRX/ARX,ARX_AR,AR_0S,SC_#,#/6 + ARX_SHIFT,AR_BR + ARX_ARX+BRX,AR_SHIFT, + FE_FE-1,SKP SCAD0,J/MVSQZ0 +.ENDIF/MVSQZ + .TOC "XCT, PXCT, SXCT" +;HERE FOR EXTENDED ADDRESSING INSTRUCTIONS + +.IFNOT/XCTR +=1****0 +XCT1: SKP USER,J/PXCT ;HERE ON XCT, NO INTERRUPT + TAKE INTRPT ;GET OUT OF LONG XCT CHAIN +=1****0 +.IFNOT/XADDR +PXCT: BR/AR,ARX_AR,SET PXCT,J/PXCTEA ;SETUP CONTROL FLOPS +.IF/XADDR +PXCT: SET PXCT +.ENDIF/XADDR +UXCT: ARX_AR (AD),LOAD IR,J/XCTGO, ;COPY INSTR TO ARX, IR + TIME/3T ;MAYBE THIS WILL FIX SUSPECTED LOSSAGE? +.IF/XCTR +=00***0 +PXCT: CALL,SKP KERNEL,J/IOCHK ;XCTR OKAY ONLY IN KERNEL MODE + SKP INTRPT,J/XCTR ;XCTR AND XCTRI + +=*1***0 +XCTR: BR/AR,ARX_AR,SET PXCT,J/PXCTEA + TAKE INTRPT +=*1***0 +UXCT: ARX_AR (AD),LOAD IR,J/XCTGO + TAKE INTRPT +.ENDIF/XCTR + + .DCODE +.IFNOT/SXCT +106: I, J/UUO + I, J/UUO +.IF/SXCT ;NOTE: THE SXCT INSTRUCTION IS A TEMPORARY MECHANISM +106: R, J/SXCT ;INTENDED FOR DIAGNOSTICS ONLY + I, J/UUO107 +.ENDIF/SXCT + .UCODE + +.IF/SXCT +1014: ;PUT NEXT TO UUO107 +SXCT: SKP KERNEL,CALL,J/IOCHK ;LEGAL IN KERNEL MODE ONLY +1015: BR/AR,ARX_AR,AR_AC0, ;SHUFFLE INSTR TO GET BASE REG + SET SXCT ;SETUP HARDWARE FLAGS + SKP AC#0 ;CHOOSE LOOP FOR EA CALC +=0 BR/AR,AR_BR,LOAD IR, ;AC0 IS BASE INDEX + BRX/ARX,ARL_0.M, + EA MOD DISP,J/SXCTB +.ENDIF/SXCT + ;EXTENDED ADDRESSING CONTINUED + +.IFNOT/XADDR +PXCTEA: AR_BR,LOAD IR,ARL_0.M, ;GET EXT ADDR FROM XR OR INDRCT + BRX/ARX,J/XIND2 +=00 +PXLOOP: GEN AR,A READ ;GO DO INSTR + AR_AR+XR,A READ + GEN AR,A INDRCT,SKP INTRPT,J/XIND1 + GEN AR+XR,A INDRCT,SKP INTRPT + +=1****0 +XIND1: AR_MEM,ARX_MEM,EA TYPE DISP,J/XIND2 + MB WAIT,TAKE INTRPT +=1***00 +XIND2: EA MOD DISP,J/PXLOOP ;CURRENT OR PREV WITHOUT CWSX + AR_ARX (AD),A READ ;PREV AND CWSX +.IF/SXCT + AR_ARX (AD),A READ ;SXCT 0, + EA MOD DISP,J/SXCTB ;SXCT B, + +=1***00 +SXCTB: AR_AR+BR,A READ ;GO + AR_AR+XR,ARL_0.C,J/SXCTB ;NO MORE INDIRECTS + GEN AR,A INDRCT, ;FOLLOW INDRCT POINTER + SKP INTRPT,J/XIND1 + GEN AR+XR,A INDRCT, + SKP INTRPT,J/XIND1 +.ENDIF/SXCT +.ENDIF/XADDR + \ No newline at end of file