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TT2500 - Functional Specifications.

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Overview of TT2500 hardware.
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2500 - FUNCTIONAL SPECIFICATIONS
WORD LENGTH - 16 BITS
CYCLE TIME - 220 nanoseconds
MEMORY SIZE - control memory, 1K expandable to 4K
main memory, 4K expandable to 64K
REGISTERS - 8 working registers
- 32 scratch pad registers
- 15 deep push down stack
- 5 special registers
GRAPHIC DISPLAY - size 11" x 11"
- working area 8" x 8"
- resolution 512 x 512
- write speed 2,000,000 points/sec
- phosphor high speed, white
TEXT DISPLAY - size 15
- lines 30
- characters/line 72
- fonts programmable
- characters 8x16 dot matrix
- phosphor green
The TT2500 is a high speed bus-oriented minicomputer, designed for
education. It is especially suited for systems involving animated
graphics, real time device control, and emulation of "high level" order
codes.
The basic TT2500 system includes processor, memory, graphics display,
text display, keyboard, communications interface, bootstrap loader, real
time clock, cassette tape unit, power supply and cabinets.
The TT2500 processor is a register oriented, parallel
transfer computer using 16 bit, two's complement arithmetic. The cycle
time of a typical instruction is 220 nanoseconds.
The basic arithmetic and logical operations of the machine are
performed on 8 high speed working registers. There are also 32 fast
scratch pad registers and a number of special purpose registers.
The TT2500 has two random access memories. Programs are stored in
1024 words of 40 nanosecond static bipolar memory. This control memory
may be expanded to 4096 words. Data is stored in a dynamic
semiconductor main memory. The basic machine is supplied with 4096
words of main memory, expandable to 65,536 words. Both the main memory
and the control memory use 16 bit words, and data may be transferred
freely between them.
The 2500 is especially suited for use as a micro-programmed
machine. In this mode the program in the control memory is an
interpreter for a more complex order code. This higher level instruction
set is referred to as Macro-code. Macro-code programs are stored in
main memory. The 2500 has several features to make this interpretation
efficient.
INPUT/OUTPUT
INPUT/OUTPUT on the 2500 is done in a particularly straightforward
manner. Data may be transferred from any working register to any of 16
output devices in a single 250 nanosecond instruction. Similarly data
may be read from any of 16 input devices. All communication with the
outside world is done through an I/O bus. It is quite simple to attach
new physical devices to this bus.
Animated pictures are displayed as points and vectors on an 11 inch
screen. The resolution of this display is 512 x 512 points.
The text display will display 30 lines of 72 characters each. The
character fonts are defined by the user and may be changed under
processor control.
ORGANIZATION OF THE 2500
ARITHMETIC LOGIC UNIT (ALU)
The arithmetic logic Unit, or ALU is used to perform 16 different
arithmetic, logical and shift operations. Operations are done on 16
bits in parallel. Two's complement arithmetic is used. The ALU is
capable of performing, logic, arithmetic or shift of up to 16 places in
a single instruction cycle. The arithmetic logic unit generates signals
that indicate carry, overflow, zero results and negative result. These
signals may be used for conditional branching.
BUS (24 lines)
The BUS is the primary data path both internally and with the
outside world. The BUS consists of 16 data lines, 6 device address
lines, a READ line, and a WRITE line. Data may be transferred in either
direction on the BUS via tri-state TTL signals. A device may read data
from the BUS whenever its bus address is on the address lines and the
READ line goes low. An addressed device may write while the WRITE line
is low. When a device is not selected its outputs should be in the high
impedance state. Devices transfer data to and from the BUS in less than
50 nanoseconds.
CONTROL MEMORY
The control memory is a high speed random access bipolar memory in
which the currently running program is stored. The access time of this
memory is 40 nanoseconds. In applications where the computer is to be
dedicated to a single usage this random access memory (RAM) can be
replaced by a read only memory (ROM). The control memory may be
expanded in 1K increments, up to 4K.
CONTROL UNIT
The control unit executes instruction from the control memory. In
each 220 nanosecond cycle the control unit performs a data computation
and an address calculation simulteneously. When the control unit
receives an instruction it takes one cycle to decode it, calculate the
address of the next instruction, and set up the data computation for the
next cycle. At the same time it performs the data computation set up by
the previous instruction. Because of this overlap the Control Unit
executes an instruction once every 220 nanoseconds even though it may
take 440 nanoseconds to complete a single instruction. This overlap is
invisible to the user. The control unit is responsible for supervising
the bus.
MACRO REGISTER
The MACRO REGISTER, or MR, is a special 16 bit register with
features that make it useful in the interpretation of a macro order
code. In this mode the macro command is stored in the MR after fetching
it from main memory. The flow of the control program may then be
determined by various bits in the macro command. MR is also a counter.
This is useful in programming short fast loops such as multiply or
divide routines.
MEMORY ADDRESS REGISTER
The Memory Address Register, or MAR, is a 16 bit register that
holds the address of the main memory location currently being written
into or read from.
( The contents of this register cannot be read onto the bus. )
MEMORY DATA REGISTER
All data to and from the Main Memory is first loaded into the 16
bit Memory Data Register, or MDR. In applications where a 16 bit main
memory word is insufficient an extension register may be added to the
MDR.
MAIN MEMORY
Main memory holds all data and Macro-code to be operated on. It is
a random access dynamic semiconductor memory, made from 4K NMOS chips.
The cycle time is 750 nanoseconds. The access time is 500 nanoseconds.
The Main Memory is minimally 4096 words, and may be expanded to as large
as 65,536 words. This memory will lose all data when power is turned
off, unless a battery-powered memory-save device is attached.
PROGRAM COUNTER
The program counter, or PC, holds the control memory address of the
next instruction. It is a 12 bit register which may be loaded from the
stack or the control memory. It may also be incremented or added to
from the BUS. During normal program flow the PC is incremented after
each instruction. When a jump or branch instruction is encountered the
jump address is loaded into it directly from the control memory. During
a return from a subroutine call the PC is loaded from the top of the
STACK. Certain special instructions such as SKIP and DISPATCH
instruction may add BUS data to the current PC contents.
SCRATCH PAD
The Scratch Pad is composed of 32 16 bit registers designated S0
through S31. It is used for temporary storage being much faster than
main memory. Data may be read from or written into the Scratch Pad in a
single cycle. Data cannot be operated on while in the scratch pad; it
must first be moved into the working registers.
STACK
The 2500 is equipped with a hardware pushdown stack, 15 words deep.
Each word is 12 bits wide. This stack is used for storing the return
addresses of subroutines. Each time a subroutine call is executed the
current contents of the PC is saved by pushing it onto the top of the
stack. When returning from a subroutine the top of the stack is popped
off into the PC. Because the stack is 15 deep the user may have
subroutines nested up to 15 levels. Attempts to use more than 15 levels
of subroutine will result in program errors.
WORKING REGISTERS
All arithmetic logical and shift operations are performed on data
stored in the 8 working registers designated R0 through R7. Each of
these 16 bit registers is loaded directly from the bus. Data from each
of these registers may be switched into either input of the ALU. The
working registers cannot write data onto the bus directly, but must pass
through the ALU. When interpreting a macro order code R7 is normally
used as the macro program counted, and R6 as the macro stack pointer.
ARITHMETIC
ADD
SUBtract
INCrement
DECrement Immediate
eXtended ADD if Carry
eXtended SUBtract
LOGIC
AND
Inclusive OR (IOR)
eXclusive OR (XOR) Immediate
Not OR (NOR) if Carry
ANDNot (ANDN)
SHIFTING
Arithmetic Right Shift (ARS)
Double Arithmetic Right Shift (DARS)
Triple Arithmetic Right Shift (TARS) Immediate
ROTate (ROT) if Carry
Mask and ROTate (MROT)
TRANSFER
( Register
( Scratch pad
PUT into ( Main memory
GET from ( Macro Register
( Processor Statur Register
( Memory Date Register
LOaD constant into register (LOD)
SET macro conditions
WRITE Control Memory
CONTROL
( Always
( if Carry
( if oVerflow
JUMP IF (relative: 11 bit signed offset) ( if Zero
( if Negative
( if Interrupt
( if Macro register 7128
JUMP (absolute, 12 bit address) ( if Flat
PUSH onto stack and Jump
POP from stack and Jump
DISpatch on bus bits DISBUS
DISpatch on interrupts DISINT
DISpatch on Conditions DISND
DISpatch on Flags DISFLG
INPUT/OUTPUT
COMmunication link
INput CASsett
KEYboard
COMmunication link
CASsett
OUTput
VECtor generator
PEN
TEXT display
TRANSFER
Input/Output
Main memory
PUT into Register
GET from Scratch pad
Processor status register
Memory Date register
Control
How to do things
Arithmetic - All arithmetic is done using the working registers and the
ALU. Here are the basic arithmetic instructions:
ADD ADD
SUBtract SUB
INCrement (add one) INC
DECrement (subtract one) DEC
eXtended ADD (A plus B plus carry) XADD
eXtended SUBtract (A minus B minus CARRY) XSUB
Each of these instructions comes in three different flavors: Normal,
Immediate, and Conditional.
The normal form of the addition instruction is -
ADD 1 2
This will cause the contents of working register 2 to be added to
the contents of working register 1. The result is stored in register 1.
Register 2 is not effected.
The immediate form of the addition instruction look like this:
ADDI 1 2 45
This instruction with add the number 45 with the contents of
working register 2 and put the result in working register 1. Again
register 2 is left unchanged. Immediate instructions use an extra word
of control memory for the 16 bit literal. They take two cycles to
execute.
The conditional form of an instruction is exactly the same as the
normal form, except that nothing takes place unless the previous
operation resulted in a carry. This form is not very useful except in
writing fast multiplication routines. It looks like this:
ADDC 1 2
All arithmetic instructions have all three forms, so that the
complete set looks like this:
ADD ADDI ADDC
SUB SUBI SUBC
INC INCI INCC
DEC DECI DECC
XADD XADDI XADDC
XSUB XSUBI XSUBC
XADD 2 3
adds the contents of register 2 plus the contents of register 3 plus the
carry from the previous operation. This is the fastest way to do double
precision arithmetic.
XSUB does the right thing for double precision subtraction.
Example:
ADD 1 2 ; add low order bits
XADD 3 4 ; add high order bits
or
SUB 1 2 ; double precision
XSUB 3 4 ; is easy as pie
LOGIC
The basic logical instructions are:
AND AND
Inclusive OR IOR
eXclusive OR XOR
Not OR NOR
AND Not (A and (Not B)) ANON
Like the arithmetic functions each of these instructions comes in
all three flavors, making the complete set:
AND ANDI ANDC
IOR IROI IORC
XOR XORI XORC
NOR NORI NORC
ANON ANDNI ANDNC
These instructions are used in the same manner as the arithmetic
instruction.
SHIFTING
Arithmetic right shifts (right shifts with the sign bit propagated)
of up to three places may be done in a single cycle. The instructions
are:
Arithmetic Right Shift ARS
Double Arithmetic Right Shift DARS
Triple Arithmetic Right Shift TARS
The ROTate instruction allows data to be shifted around in a circle
up to 16 places in a single cycle.
ROT 1 5
This rorates the contents of register 1 five places.
You can also perform an AND after the rotate using the Mask RoTate
(MROT) instruction.
EXAMPLE:
GETR 2 1 ; brings data from 1 to 2
MROT 3 5 ; this causes the data (coming from 1) to be rotated
; five places on its way into 2!
and the previous contents of register 1.
;and it also AND's the shifted data with 3 and leaves result in 3!
Note that the shifted result, before ANDing, is left in register 2.
All of the shift instructions come in normal, immediate and
conditional form. Here is the complete list:
ARS ARSI ARSC
DARS DARSI DARSC
TARS TARSI TARSC
ROT ROTI ROTC
MROT MROTI MROTC
The MROTI instruction is useful.
EXAMPLE:
PUTR 2 1
MROTI 2 5 177 ; the contents of register 1 rotated 5 places,
ANDed with the number 177, and loaded into
register 2.
MOVING DATA AROUND
Data in a working register is put other places using a PUT instruction.
PUTR 1 2
will put the contents of register 1 into register 2.
PUTS 1 2
will put the contents of register 1 into scratch pad location 2.
PUTM 1 2
will put it into the main memory location addressed by register 1.
PUTPSR 1
will put the contents of register 1 into the processor status register.
PUTMDR 1
will put it into the memory data register.
PUTMR 1
will put it into the macro register. To get things into a working
register use one of the GET instructions.
GETR 1 2
loads register 1 with the contents of register 2
GETS 1 2
loads it from scratch pad 2.
GETM 2
loads from the memory addressed by 2 into the memory data register.
GETMDR 1
loads register one with the contents of the memory data register and
GETPSR 1
loads it from the processor status register.
GETMR 1
will load it from the macro register.
The three more data transfer instructions
SET conditions SET
LOaD register LOD
Write Control Memory WCM
SET sets the least significant four bits of the processor status
register to be the carry, overflow, zero condition and sign bit of the
most recent result.
LOD 1 2525
will load the number 2525 in register 1.
WCM 3
will write the contents of register 3 into the control memory location
addressed by the macro register.
PUSHJ 425
would be used to jump to a subroutine a location 425. Before it
transfers control it saves the current pc on the top of the stack.
POPJ
returns from the subroutine by poping of the top of the stack and
jumping there. Since the stack is 15 deep this allows nesting of
subroutines up to 15 levels.