From 96451ce11d8ec0f4e5b25a98033f0220d5606e80 Mon Sep 17 00:00:00 2001 From: Lars Brinkhoff Date: Wed, 19 Jun 2019 17:38:34 +0200 Subject: [PATCH] 8080DF - MIDAS macros to assemble 8080 software. --- src/klh/8080df.21 | 252 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 252 insertions(+) create mode 100644 src/klh/8080df.21 diff --git a/src/klh/8080df.21 b/src/klh/8080df.21 new file mode 100644 index 00000000..9b058608 --- /dev/null +++ b/src/klh/8080df.21 @@ -0,0 +1,252 @@ +COMMEN / This file contains the definitions necessary to use MIDAS as a +fast powerful 8080 assembler. The only idiosyncracy requiring source +code conversion is the decision not to use hex notation; not only is it +unlikely that we will ever borrow any 8080 software, such notation is +quite easy to change in the source and using octal makes life easier for +people used to DEC equipment./ +; Register Definitions + A==7 ; Accumulator + B==0 ; General reg (BC high) + C==1 ; General reg (BC low) + D==2 ; General reg (DE high) + E==3 ; General reg (DE low) + H==4 ; General & Memory Address reg (HL high) + L==5 ; General & Memory Address reg (HL low) + M==6 ; Non-ex reg, defined to indicate Memory reference + SP==6 ; Stack Pointer, defined here for use as register pair. +; Instruction Opcode definitions (primarily for DDT symbols) + ; Accumulator Ops + IRP op,,[ADD,ADC,SUB,SBB,ANA,XRA,ORA,CMP] + %%.op==200+.irpcnt_3 + IRP reg,,[B,C,D,E,H,L,M,A] + op!.!reg=<%%.op+.irpcnt>_27. + TERMIN + TERMIN + IRP r1,,[B,C,D,E,H,L,M,A] + %%.op==100+.irpcnt_3 + IRP r2,,[B,C,D,E,H,L,M,A] + MOV.!r1!r2=<%%.op+.irpcnt>_27. + TERMIN + TERMIN + ; Simple invariant opcodes + IRP pair,,[[NOP,000],[HLT,166],[DI,363],[EI,373] + [XCHG,353],[XTHL,343],[SPHL,371],[PCHL,351] + [SHLD,042],[LHLD,052],[STA,062],[LDA,072] + [OUT,323],[IN,333] + [RET,311],[JMP,303],[CALL,315]] + IRP op,val,[pair] + op!.=val_27. + .istop + TERMIN + TERMIN + IRP op,,[RLC,RRC,RAL,RAR,DAA,CMA,STC,CMC] + op!.=<007+<.irpcnt_3>>_27. + TERMIN + IRP op,,[ADI,ACI,SUI,SBI,ANI,XRI,ORI,CPI] + op!.=<306+<.irpcnt_3>>_27. + TERMIN + ; Misc - PUSH/POP and RST + IRP rp,,[B,D,H,P] ; P = PSW + PUSH.!rp=<305+.irpcnt_4>_27. + POP.!rp=<301+.irpcnt_4>_27. + TERMIN + IRP r,,[0,1,2,3,4,5,6,7] + RST.!r=<307+>_27. + TERMIN + ; Other Register referencing opcodes + IRP reg,,[B,C,D,E,H,L,M,A] + INR.!reg=<004+.irpcnt_3>_27. + DCR.!reg=<005+.irpcnt_3>_27. + MVI.!reg=<006+.irpcnt_3>_27. + TERMIN + ; Register-Pair opcodes + IRP rp,,[B,D,H,SP] + LXI.!rp=<001+.irpcnt_4>_27. + DAD.!rp=<011+.irpcnt_4>_27. + INX.!rp=<003+.irpcnt_4>_27. + DCX.!rp=<013+.irpcnt_4>_27. + TERMIN + IRP rp,,[B,D] + LDAX.!rp=<012+.irpcnt_4>_27. + STAX.!rp=<002+.irpcnt_4>_27. + TERMIN + ; Conditionals + IRP cond,,[NZ,Z,NC,C,PO,PE,P,M] + R!cond!.=<300+.irpcnt_3>_27. + J!cond!.=<302+.irpcnt_3>_27. + C!cond!.=<304+.irpcnt_3>_27. + TERMIN +; Instruction Macro definitions + ; Define single-byte invariant opcodes + RLC==RLC. ; Rotate Accumulator Left + RRC==RRC. ; Rotate Accumulator Right + RAL==RAL. ; Rotate Accumulator Left + RAR==RAR. ; Rotate Accumulator Right + DAA==DAA. ; Decimal Adjust Accumulator + CMA==CMA. ; Complement Accumulator + STC==STC. ; Set Carry + CMC==CMC. ; Complement Carry + PCHL==PCHL. ; Jump H and L Indirect - move H and L to PC + SPHL==SPHL. ; Move HL to SP + XTHL==XTHL. ; Exchange Stack Top with H and L + XCHG==XCHG. ; Exchange H and L with D and E + DI==DI. ; Disable Interrupts + EI==EI. ; Enable Interrupts + HLT==HLT. ; Halt + ; Define auxiliary stuff for following. + NOP=400_27. ; "op-code" for No Operation (zeros) + .LO.=401_27. ; "op-code" indicating lo-order data byte + .HI.=402_27. ; "op-code" indicating hi-order data byte + DEFINE %%word val16 + .LO. <&377> ; low order byte + .HI. <_-8.> ; high order byte + TERMIN + ; Define Direct Addressing instructions - SHLD, LHLD, STA, LDA. + IRP op,,[SHLD,LHLD,STA,LDA] + DEFINE op addr + op!. addr + %%word [addr] + TERMIN + TERMIN + ; Define Single-Register instructions + IRP op,,[ADD,ADC,SUB,SBB,ANA,XRA,ORA,CMP] + %%!op==200+<.irpcnt_3> ; .IRPCNT not evaled in macro def + DEFINE op r + <%%!op+r>_27. + TERMIN + TERMIN + ; Define 2-byte instructions with data + IRP op,,[ADI,ACI,SUI,SBI,ANI,XRI,ORI,CPI] + DEFINE op data + op!. data + .LO. data&377 + TERMIN + TERMIN + ; Define JMP and Conditional Jumps + DEFINE JMP addr ; Jump to Address + JMP. addr + %%word [addr] + TERMIN + IRP op,,[JNZ,JZ,JNC,JC,JPO,JPE,JP,JM] + DEFINE op addr + op!. addr + %%word [addr] + TERMIN + TERMIN + ; Define CALL and Conditional Calls + DEFINE CALL addr ; Call to Subroutine + CALL. addr + %%word [addr] + TERMIN + IRP op,,[CNZ,CZ,CNC,CC,CPO,CPE,CP,CM] + DEFINE op addr + op!. addr + %%word [addr] + TERMIN + TERMIN + ; Define RET and Conditional Returns + RET==RET. ; Return from Subroutine + IRP op,,[RNZ,RZ,RNC,RC,RPO,RPE,RP,RM] ; Order important! + op==op!. + TERMIN + ; Define various others individually + DEFINE MOV r1,r2 ; Move from Register or Memory + <100++r2>_27. + TERMIN + DEFINE MVI r,data ; Move Immediate + <006+>_27. data + .LO. data&377 + TERMIN + DEFINE LXI rp,data ; Load Register Pair Immediate + <001+<_3>>_27. data + %%word [data] + TERMIN + DEFINE LDAX rp ; Load Accumulator Indirect + <012+<_3>>_27. ; RP's B and D only, H and SP illegal + TERMIN + DEFINE STAX rp ; Store Accumulator Indirect + <002+<_3>_27. ; RP's B and D only, H and SP illegal + TERMIN + DEFINE INX rp ; Increment Register Pair + <003+<_3>>_27. + TERMIN + DEFINE DCX rp ; Decrement Register Pair + <013+<_3>>_27. + TERMIN + DEFINE DAD rp ; Add Register Pair to H and L + <011+<_3>>_27. + TERMIN + DEFINE PUSH rp ; Push Register Pair + IFSE [rp][PSW] PUSH.P + .ELSE <305+<_3>>_27. + TERMIN + DEFINE POP rp ; Pop Register Pair + IFSE [rp][PSW] POP.P + .ELSE <301+<_3>>_27. + TERMIN + DEFINE DCR r ; Decrement Register + <005+>_27. + TERMIN + DEFINE INR r ; Increment Register + <004+>_27. + TERMIN + DEFINE RST n ; Restart + <307+>_27. + TERMIN + DEFINE IN port ; Input from Port + IN. port + .LO. port&377 + TERMIN + DEFINE OUT port ; Output to Port + OUT. port + .LO. port&377 + TERMIN +; Assembler Pseudo Definitions + DEFINE .PAGE ; Ignore this. + TERMIN + DEFINE .SPACE num ; Also ignore this - listing formatter. + TERMIN + DEFINE .LST ; Listing on. + .LSTON + TERMIN + DEFINE .NLST ; Listing off + .LSTOFF + TERMIN + DEFINE .LOC n ; Like LOC/ORG + LOC n + TERMIN + DEFINE .TXT *chars ; Like ASCII /chars/ + IRPC ch,,[chars] + .ascvl /ch + TERMIN + TERMIN + DEFINE .TXTZ *chars ; Like ASCIZ /chars/ + .TXT [chars] + 0 + TERMIN + DEFINE .END ; I wonder if this will work? + END + TERMIN + DEFINE .RADX n ; Set default number radix + RADIX n + TERMIN + DEFINE .BLK nbytes ; Allocate storage + BLOCK nbytes + TERMIN + DEFINE .WORD -line ; Assemble words. (note wholeline dummy) + IRPW trunc,,[ + line] + IRP wd,,[trunc] + 377&wd + wd_-8. + TERMIN + TERMIN + TERMIN + DEFINE .BYTE -line ; Similar to .WORD + IRPW trunc,,[ + line] + IRP wd,,[trunc] + 377&wd + TERMIN + TERMIN + TERMIN