SUBTTL NOTES

COMMENT 
NOTES:
--------------------------------------------------------------------------------
WIRE FORMAT:

                       (ALPH)                      (ALPH)   
WIRES --- <HEADER> ------------- <EQUIVALENTS> --------- ... other signals ...
             SIG1    - \             -SIG1                 
              |           \                                 
              | (NNAM)    |                                 
              
           |                                
           <OTHER NAME>   |                                
             NAM2ND       |                                 
             (WPIN) ------                               
              |                                             
              | (NNAM)                                
              
                                            

Note: Only the "header" signal has the wire. The equivalents are alpha sorted
	after the header, as is the NAM2ND list.

---------------------------------------------------------------------------

Body list:
	Bodies are in list (WBDY) sorted by BLOC, BID, and containing file.
	Bodies with the same slot locn, but different BIDs are stored
	separately.

	After all the normal bodies, there are "connector bodies" which
	bundle all the pins for one paddle together. 

Locations: 
	The board slot is given by FCRD in the wirelist header. 
	For normal bodies the slot specification is stored in BLOC. 
	The pin location is found in PINN.

	For connector bodies the BLOC gives the paddle (or jack locn) and
	the pin# is the pin locn within the jack. 
	However there is also an 18 bit format that combines the loc and pin#.
	There exist routines, CPNMRG and CPNSEP to convert both ways.
	The main reason this is different from DIPs is:
	  o  In the drawing program, only 18 bits are allocated for
		CPIN location on the board. Therefore the "dip location"
		and pin name must fit in one halfword.
	  o  For backpanel wirelists, the "body loc" is the card B-R-S,
		and the PINN is the CPIN loc.

---------------------------------------------------------------------------

HASHTB:
All the signals are strung onto one list, however segments are pointed to by
buckets in the hash table.
Each entry is:
	Previous(List),, end of list

(The first bucket is used for generated signal names.)
The first bucket is initialized to point to the wire header "WIRES" slot.

---------------------------------------------------------------------------
Invented PWR/GND signals.

When the bodies are read in from a WD file, any DIPTYPE that has pins
marked as type PWR or GND will have a signal created for it, marked
by the INVENT bit. The Volts column of the DIP definition is used to
create a signal called "+5.0V" for example.

When signal names are read-in, GND, VCC, HI, NC, and all forms like +5.0V
are checked for, and appropriate bits set in the signals flags.

When a DIP pin that was V or G is explicitly wired in the input file,
the invented pin is found and deleted. This allows user wiring of DIP pins that
normally get automatically connected to power or ground.
---------------------------------------------------------------------------

SUBTTL	DATA STRUCTURES
;		STRUCTURE DEFINTIONS

FSTLEN__2			;THIS WILL ACCUMULATE LONGEST BLOCK


;PC OR D LIST HEADERS

SBLOCK
HWDS	(BKNM,BLST)		;BACK PANEL FILENAME LIST AND WIRE LIST
				;BKNM MUST BE LEFT HALF POINTER
HWDS	(WLNM,WIRL)		;TITLE STRING AND D WIRELIST POINTER
				;WIRL MUST BE RIGHT HALF
HWDS	(WLID,PCWL)		;ID STRING AND PC WIRELIST POINTER
				;PCWL MUST BE RIGHT HALF
HWDS	(,INXT)			;NEXT WIRE LIST (ID)
EBLOCK	LSTHEAD
NIL,<BKNM#,BLST#,WLNM#,WIRL#,WLID#,PCWL#,INXT#,LSTHEAD#,>

;FILENAME BLOCK FOR LIST OF FILENAMES FOR BACK PANEL LIST
;AND SINGLE CARD WIRE LISTS

SBLOCK
FWD	(FILN)			;FILENAME
HWDS	(FEXT,)			;EXT AND UNUSED
FWD	(FPPN)			;PPN
FWD	(FDAT)			;DATE AND TIME FROM LOOKUP OF DRW FILE
FWD	(FPOL)			;NUMBER OF POLARITY CHECK ERRORS FOUND BY DWG PROG
HWDS	(FNXT,FMOD)		;NEXT FILENAME LINK AND MODULE NAME POINTER
				;FNXT MUST BE LEFT HALF POINTER
HWDS	(FVAR,FPRF)		;VARIABLE AND PREFIX
HWDS	(TIT1,TIT2)		;TITLE LINES 1 AND 2
HWDS	(FREV,AUTHOR)		;REVISION STRING AND AUTHOR
HWDS	(FPROJ,FPAGE)		;PROJECT AND PAGE STRINGS
HWDS	(FOF,FNXH)		;OF STRING AND NEXT HIGHER ASSEMBLY STRING
HWDS	(FWWT,FNOM)		;BOARD TYPE STRING AND NOMENCLATURE TYPE STRING
HWDS	(MUBN,MLBN,E,E)		;VARIABLE UPPER, LOWER BOUNDS FROM INPUT TERM
HWDS	(MCRD,MVLS)		;CARD LOC, VARIABLE LIST FROM INPUT TERM
EBLOCK	FBLK
NIL,<FILN#,FEXT#,FPPN#,FDAT#,FPOL#,FNXT#,FMOD#,FVAR#,FPRF#,TIT1#,TIT2#,FREV#,
AUTHOR#,FPROJ#,FPAGE#,FOF#,FNXH#,FWWT#,FNOM#,MUBN#,MLBN#,MCRD#,MVLS#,FBLK#,>


;NORMAL WIRE LIST HEADER UNIT (ONE CARD)

SBLOCK
HWDS	(NGEN,NXTWL)		;GEN NUMBER AND NEXT WLBLOCK
				;NXTWL MUST BE RIGHT HALFWORD
HWDS	(FILS,WIRES)		;FILENAME LIST AND SIGNAL LIST
				;WIRES MUST BE RIGHT HALFWORD
HWDS	(FCRD,WBDY)		;LAST CARD AND LOC BLOCKS
				;WBDY MUST BE RIGHT HALFWORD
FWD(HASHTB)			;FIRST WORD OF HASH TABLE
INDEX__INDEX+HASHL-1		;REST OF TABLE
EBLOCK	WLBLOCK
NIL,<NGEN#,NXTWL#,FILS#,WIRES#,FCRD#,WBDY#,HASHTB#,WLBLOCK#,>


;BODY BLOCK

SBLOCK
HWDS	(DIPT,NXTB)		;DIPTYPE POINTER AND NEXT BODY
HWDS	(BID,BPIN)		;BODY ID AND BODY PIN LIST
				;BPIN MUST BE RIGHT HALF POINTER
HWDS	(BBIT,BPAK)		;BODY BITS,,	PACKAGE CODE FROM D
HWDS	(PRPX,PRTN)		;EXTRA PROPERTIES LIST AND PART NUMBER BLOCK POINTER
HWDS	(BLOC,FILB)		;BODY LOC AND FILENAME POINTER
FWD	(BNAM)			;FIRST WORD OF BODY NAME (THE REST FOLLOW SEQUENTIALLY)
EBLOCK	BHEAD
NIL,<DIPT#,NXTB#,BID#,BPIN#,BBIT#,BPAK#,PRPX#,PRTN#,BLOC#,FILB#,BNAM#,BHEAD#,>

;WIRE HEADER

SBLOCK
HWDS	(WBIT,ALPH)		;WIRE BITS AND TEXT LINK
				;ALPH MUST BE RIGHT HALF POINTER
HWDS	(TBIT,WPIN)		;TYPE BITS AND PIN LIST
				;WPIN MUST BE RIGHT HALF POINTER
HWDS	(NNAM,WTMP)		;NEXT NAME FOR WIRE AND TMP STORE
HWDS	(WVOL,WRN,E,)		;VOLTAGE (SPWR) AND WIRE RULE NUMBER (BP ONLY)
FWD	(SCMP)			;COMPARE WORD
FWD	(SPNT)			;PRINT NAME (MUST FOLLOW SCMP)
EBLOCK	WHEAD
NIL,<WBIT#,ALPH#,TBIT#,WPIN#,NNAM#,WTMP#,WVOL#,WRN#,SCMP#,SPNT#,WHEAD#,>
;WBIT - type bits for signal (SNC, etc.)
;TBIT - combined type bits for pins on this wire

;PIN BLOCK

SBLOCK
HWDS	(PBDY,NXTP)		;BODY POINTER AND NEXT PIN
				;NXTP MUST BE RIGHT HALF POINTER
HWDS	(HPNT,NXBP)		;POINTER TO WHEAD AND BODY PIN LINK
HWDS	(PID,PINN)		;POINT ID AND PIN #
INDEX__INDEX-1
HWDS	(CBIT,)			;FOR BACK PANEL, PID IS REALLY CBIT
HWDS	(PBIT,FILP)		;PIN BITS AND FILENAME POINTER
HWDS	(PTYP,RDCN)		;TYPE POINTER AND REDAC LIBRARY NUMBER
INDEX__INDEX-1
HWDS	(HILD,LILD,E,E)		;HI LOADING FOR BP PIN, NOT PTYP, RDCN
EBLOCK	PHEAD
HWDS	(HOLD,LOLD,E,E)		;LOW LOADING FOR BP PIN.
HWDS	(FILO,)			;SOURCE FILE BLOCK POINTER AND UNUSED
EBLOCK	BPHEAD
NIL,<PBDY#,NXTP#,HPNT#,NXBP#,PID#,PINN#,CBIT#,PBIT#,FILP#,PTYP#,RDCN#,
HILD#,LILD#,HOLD#,LOLD#,FILO#,BPHEAD#,>

;DIP TYPE HEADER BLOCK

SBLOCK
HWDS	(DNAM,NXTD)		;DIPNAME AND NEXT POINTER
HWDS	(DPNN,DPIN)		;NUMBER OF PINS ACTUALLY DEFINED ON DIP, DIP PIN LIST
FWD	(DTMP)			;TMP CELL FOR DIP COUNTS
HWDS	(PRPN,PRPV)		;PROPERTY NAME LIST, PROPERTY VALUE LIST
HWDS	(DPAK,)			;PACKAGE CODE FOR DIP
EBLOCK	DHEAD
NIL,<DNAM#,NXTD#,DPNN#,DPIN#,DTMP#,PRPN#,PRPV#,DPAK#,DHEAD#,>

;DIP PIN BLOCK

SBLOCK
HWDS	(DPBIT,DPNXT)		;BITS AND NEXT
FWD	(DUSE)			;SIXBIT USE FIELD
HWDS	(LHI,LLOW,E,E)		;HI AND LOW LOADING
HWDS	(SCTB,SCTP)		;SECT BITS AND SECT PIN #
HWDS	(PSWP,DPNM)		;PIN SWAPPING/SHARING # AND PIN NAME
EBLOCK	DPHEAD
NIL,<DPBIT#,DPNXT#,DUSE#,LHI#,LLOW#,SCTB#,SCTP#,PSWP#,DPNM#,DPHEAD#,>

;PROPERTY NAME BLOCK

SBLOCK
HWDS	(PRNN,PRNS)		;NEXT PROPERTY NAME BLOCK AND PROPERTY NAME STRING
EBLOCK	PNBK
NIL,<PRNN#,PRNS#,PNBK#,>

;PROPERTY VALUE BLOCK

SBLOCK
HWDS	(PRBT,PRNV)		;PROPERTY VALUE BITS AND NEXT PROPERTY VALUE BLOCK
HWDS	(PRPP,PRNP)		;PREVIOUS PROPERTY VALUE (UP TREE) AND NEXT PROPERTY VALUE (DOWN TREE)
HWDS	(PRNB,PRVS)		;PROPERTY NAME BLOCK AND PROPERTY VALUE STRING
EBLOCK	PVBK
NIL,<PRBT#,PRNV#,PRPP#,PRNP#,PRNB#,PRVS#,PVBK#,>

;BACK PANEL MODULE INFO BLOCK

SBLOCK
HWDS	(MNUM,MNXT)		;MODULES PER MACHINE, NEXT MODULE BLOCK
HWDS	(MNAM,)			;MODULE NAME STRING
EBLOCK	BMOD
NIL,<MNUM#,MNXT#,MNAM#,BMOD#,>

;PARTS LIST THREAD BLOCK

SBLOCK
HWDS	(PLBT,NXPL)		;PLBK BITS, NEXT PLBK
HWDS	(PLPT,MDCN)		;POINTER TO PVBK OF PART NUMBER, MASTER PART COUNT LIST(MDBLOCK)
EBLOCK	PLBK
NIL,<PLBT#,NXPL#,PLPT#,MDCN#,PLBK#,>

;MASTER COUNT DIPTYPE BLOCK

SBLOCK
HWDS	(MDIP,MDNX)		;DIPTYPE, NEXT (MDBLOCK)
HWDS	(,MXPT)			;POINTER TO EXTRA PART BLOCK (MXBLOCK)
EBLOCK	MDBLOCK
NIL,<MDIP#,MDNX#,MXPT#,MDBLOCK#,>

;MASTER COUNT EXTRA PROPERTY BLOCK

SBLOCK
HWDS	(MPRX,MXNX)		;EXTRA PROPERTY LIST, NEXT (MXBLOCK)
HWDS	(,MCPT)			;PART COUNT BLOCK POINTER
EBLOCK	MXBLOCK
NIL,<MPRX#,MXNX#,MCPT#,MXBLOCK#,>


;MASTER COUNT PART COUNT BLOCK

SBLOCK
HWDS	(MODC,MCNX)		;MODULE COUNT BLOCK POINTER (BMOD), NEXT (MCBLOCK)
FWD	(MAPP)			;APPROXIMATE COUNT
FWD	(MREA)			;REAL COUNT
EBLOCK	MCBLOCK
NIL,<MODC#,MCNX#,MAPP#,MREA#,MCBLOCK#,>


;DIRECTORY LIST BLOCK

SBLOCK
HWDS	(DEXT,DIRNXT)
FWD	(DFIL)
FWD	(DPPN)
HWDS	(,CVAR)			;CARD AND VARIABLE LIST POINTER (MUST BE RIGHT HALF)
EBLOCK	DIRHEAD
NIL,<DEXT#,DIRNXT#,DFIL#,DPPN#,CVAR#,DIRHEAD#,>


;CARD LOC AND BOUND BLOCK

SBLOCK
HWDS	(,NSLC)			;NEXT SLICE
HWDS	(CDLC,VLST)		;CARD LOC AND VARIABLE LIST POINTER
HWDS	(LBND,UBND,E,E)		;UPPER AND LOWER BOUNDS (EXTEND SIGN ON FETCH)
EBLOCK	CBND
NIL,<NSLC#,CDLC#,VLST#,LBND#,UBND#,CBND#,>


;VARIABLE BLOCK IN VARLIST

SBLOCK
HWDS	(VAL,NVAR,E)		;VALUE(EXTEND SIGN ON FETCH) AND NEXT
HWDS	(WID,LET)			;WIDTH,,LETTER
EBLOCK	VBLK
NIL,<VAL#,NVAR#,WID#,LET#,VBLK#,>


;GND AND VCC PIN BLOCKS FOR ROUTER

ROUTE,<
SBLOCK
HWDS	(PNTR,NWRD)			;PIN POINTER,,NEXT BLOCK
FWD	(PNAM)				;PIN NAME
EBLOCK	WBLK
>;ROUTE
NIL,<PNTR#,NWRD#,PNAM#,WBLK#,>


;CURRENT@VOLTAGE LIST FOR WLS FILE

SBLOCK
HWDS	(VLTS,NXTM,E)		;VOLTS (W/SIGN) AND NEXT BLOCK POINTER
FWD	(MAMP)			;# OF MILLIAMPS AT VOLTS
EBLOCK	MABLK
NIL,<VLTS#,NXTM#,MAMP#,MABLK#,>


;2 WORD TMP LIST BLOCK

SBLOCK
HWDS	(TVAL,NXTT)		;FLAG,,		LINK
HWDS	(TLFT,TRHT)		;LEFT AND RIGHT TEMP CELLS
EBLOCK	TBLK
NIL,<TVAL#,NXTT#,TLFT#,TRHT#,TBLK#,>


;COUNT BLOCK FOR WSS, WCS, AND WLS PRINT SUBR
SBLOCK
HWDS	(CFIL,NXTC)		;FILE POINTER AND NEXT
HWDS	(ICNT,OCNT)		;# INPUTS, #OUTPUTS
HWDS	(CCNT,ZCNT)		;# CONNECTORS+BITS, # TERMINATORS
EBLOCK	CBLK
NIL,<CFIL#,NXTC#,ICNT#,OCNT#,CCNT#,ZCNT#,CBLK#,>
SUBTTL	BITS


; BODY ENTRY (BBIT)
BTMP1__400000		;TEMP MARK BIT
PRX2ND__200000		;SECOND OCCURENCE OF THIS PRPX POINTER
BPACKP__100000		;PACKAGE PROP OTHER THAN DEFAULT WAS SEEN

BWILD__1000		;THIS IS A WILD CONNECTOR
BEDGE__400		;EDGE PIN BODY
 CBODY__BEDGE!BWILD	;CON BODY BITS
BANYPOS__200		;INDICATES XPOS AND YPOS ARE VALID
BXPOSL__3		;3 BITS WORTH
BXPOSB__4		;4 FROM RIGHT
BYPOSL__2		;2 BITS WORTH
BYPOSB__2		;2 FROM RIGHT

;BITS FROM D WHICH MUST BE STORED IN BODY BITS ABOVE

;BITS IN PIN ENTRY IN WIRE LIST (PBIT)
PTMP1__400000		;MARK BIT
PTMP2__200000		;ANOTHER

TRMBTS__140000		;TERMINATOR RULE BITS (FOR CON ONLY)
	TRMBSZ__2	;NUMBER OF BITS
	TRMBPS__3	;LOW ORDER BIT
CANYPOS__20000
	;17400 POS BITS
CXPOSL__3
CXPOSB__12		;DISTANCE FROM RIGHT EDGE OF HALFWORD
CYPOSL__2
CYPOSB__10		;DISTANCE FROM RIGHT EDGE OF HALFWORD

DUP__200		;THIS PIN IS A DUPLICATE OF ANOTHER PIN IN RUN
PIDPIN__100		;NO PIN #, USED PID!
PSHARE__40		;THIS INPUT LOAD IS ALREADY SHARED WITH ANOTHER PIN
INVENT__20		;THIS IS AN INVENTED POWER OR GROUND PIN
;QBITS USED ONLY ON BP PINS

QBITS__37		;BIT MASK TO GET QUALIFIER LETTER FROM THIS HALFWORD
			;LSB OF BIT MASK MUST EQUAL 17
			;
 IS FOR TABLE TEST INSIDE SIGSUB


;POINT BITS FROM DRAWING PROG ('WD' FILE)
DEFPIN__4000		;THIS PIN IS DEFAULTED, NOT EXPLICIT (BODY PINS ONLY)
CPNBTS__6000		;BITS FOR TERMINATOR RULES (CPINS ONLY)
	CPNBPS__7	;LOW ORDER BIT POS
	CPNBSZ__2	;# OF BITS

;BITS IN DPBIT, TBIT, AND CBIT (TYPE BITS)
INLD__400000		;INPUT LOAD
OUTLD__200000		;OUTPUT LOAD
NULLD__100000		;NO LOADING AT PRESENT
GND__40000		;GROUND CONNECTION
PWR__20000		;POWER CONNECTION
	VPWR__=500	;TTL POWER
TRI__10000		;TRI-STATE OUTPUT
SHARE__4000		;SHARE INPUT LOAD BIT (OR EXTRA OUTPUT)
OPENC__2000		;OPEN COLLECTOR OUTPUT
PULL__1000		;THIS OUTPUT IS A PULLUP
ECL__400		;ECL PIN
TTL__200		;TTL PIN
CLK__100		;CLK SEEN AS FIRST 3 CHARS OF USE
TERM__40		;TERMINATOR PIN
FFOUT__20		;FLIP-FLOP OUTPUT
DRVREQ__10		;DRIVE REQUIRED FOR THIS INPUT
FFIN__4			;FLIP-FLOP INPUT

ANYCON__1		;THERE IS A CONNECTOR IN THIS RUN (NOT USED IN DPBIT)

;BITS FROM OLD VERSION DIP FILE
VEE__200		;-5.5V ECL POWER
	VEEVLT__-=520
OTTL__100		;OLD TTL BIT
VBB__40			;-1.5V ECL THRESHOLD
	VBBVLT__-=150
VTT__20			;-2V ECL TERMINATORS
	VTTVLT__-=200
OCLK__10		;OLD CLK BIT


ALLTYP__INLD!OUTLD!NULLD!GND!PWR!TRI!SHARE!OPENC!PULL!TERM	;ALL TYPE BITS
INBITS__INLD!SHARE!NULLD				;ALL INPUT BITS


;BITS IN WBIT (WIRE BITS)

SNC__400000		;THIS WIRE HAS THE NAME "NC"

SHI__200000		;THIS WIRE HAS THE NAME "HI"

SPWR__100000		;THIS WIRE HAS THE NAME "VCC"

SGND__40000		;THIS WIRE HAS THE NAME "GND"

SCANON__20000		;THIS SIGNAL IS THE CANONICAL +5.00V

CABRUN__400		;PUT C QUALIFIER ON EDGE PINS
WNULL__200		;COMPLETELY NULL WIRE
WSINGL__100		;WIRE WITH ONLY 1 PIN

GLB2__40		;THIS IS THE SIGNAL TO COME OUT IN THE SIMPLE FILE

GLB1__20		;THIS IS ONLY SIGNAL TO GO TO BACK PANEL
GENSIG__10		;THIS IS A GENERATED SIGNAL
WTMP1__4		;TEMP MARK BIT FOR WIRE HEADER
SIG1__2			;THIS SIGNAL BLOCK IS THE FIRST OF A SET OF EQUIVALENT NAMES
NAM2ND__1		;INTERNAL WIRE HEADER BIT FOR SECOND NON-EQUIVALENT NAME OF SIGNAL

SIGBIT__SNC!SHI!SPWR!SGND	;WIRE TYPE BITS


;RUN BITS FROM DRAWING PROG ('WD' FILE)
CABBDY__1		;"CABLE" BODY PIN ON RUN


ROUTE,<
;BITS IN PNTBL WORD USED BY ROUTER
RPGPIN__400000		;THIS IS A POWER OR GROUND PIN, IT IS NOT IN WIRE LIST
RERPIN__200000		;THIS PIN IS IN ERROR IN SOME WAY, DON'T WIRE IT!
ROUMRK__100000		;MARK BIT FOR ROUTER
;BITS 5-14 ORDER #
;BITS 15-17 "SCT" CHARS
>;ROUTE


;BITS IN PROPERTY VALUE BLOCKS
DEFPRP__400000		;THIS IS THE DEFAULT PROPERTY AT THIS LEVEL
PARTNM__200000		;THIS IS A PART NUMBER BLOCK
PNUSED__100000		;THIS PART NUMBER BLOCK IN USE
NULVAL__40000		;THIS IS A NULL VALUE STRING AND SHOULDN'T NORMALLY BE PRINTED

PRTMP1__1		;TEMP MARK BIT


;BITS IN PLBK FOR PARTS LIST THREAD
PL2ND__400000		;THIS IS SECOND OCCURENCE OF SAME PART NUMBER