;;; -*-midas-*-
	.sbttl	Macros for CPU compatibility for PDP11 processors

;;; ;;; General info:
;;; ;;; 	These macros make all PDP-11s look alike in software.

.if ndf pdp11
.print "
The value of PDP11 must be defined before the CPU macro package
is inserted.
"
.error (see previous print)
.endc

.if z <pdp11-02>		;define things for the lsi11/2
  qbus==1			;yas a qbus
  hasxor==1			;xor includes SXT, XOR, MMARK, SOB, RTT
  hasspl==0			;only 11/45 and 11/70 have SPL
  haseis==0			;doesn't have the the Extended Instructions
.endc

.if z <pdp11-05>*<pdp11-10>
  qbus==0			;no qbus on these old beasts
  hasxor==0			;nor xor
  hasspl==0			;only 11/45 and 11/70 have SPL
  haseis==0			;nor EIS
.endc

.if z <pdp11-34>
  qbus==0			;no qbus on this slighty old beast
  hasxor==1			;winning XOR and friends
  hasspl==0			;only 11/44, 11/45, and 11/70 have SPL
  haseis==1			;has winning EIS
.endc

.if z <pdp11-23>
  qbus==1			;super losing QBUS
  hasxor==1			;winning XOR and friends
  hasspl==0			;only 11/45 and 11/70 have SPL
  haseis==1			;and EIS instructions
.endc

	.sbttl	Standard register definitions and priorities

r0=%0
r1=%1
r2=%2
r3=%3
r4=%4
r5=%5
sp=%6
pc=%7
ps==177776			;the processor status word

pr0==000
pr1==040
pr2==100
pr3==140
pr4==200
pr5==240
pr6==300
pr7==340

psw.t==bit.04
psw.n==bit.03
psw.z==bit.02
psw.v==bit.01
psw.c==bit.00

;;; e.g., movea #foo,r4,r5
.macro movea adder,base,dest,dstmod
	mov base,dest
	add adder,dest'dstmod
.endm

	.sbttl	Instruction macros

.if z qbus

;;; MTPS and MFPS exist only on qbus versions. Others should use
;;; either SPL or direct from mthe psw

.macro	mtps src
.nlist
	movb src,@#ps
.list
.endm

.macro	mfps dst
.nlist
	movb @#ps,dst
.list
.endm

.endc

.if z hasspl

;;; Only the 11/45 and 11/70 have the SPL instruction
.macro	spl n
.nlist
	mtps #n*40
.list
.endm

.endc

.if z hasxor			;XOR and friends

; SOB macro expands into code which performs identically to
; the SOB instruction found on more powerfull 11 processors
.macro	sob r,addr
.nlist
	dec r
	bne addr
.list
.endm

; RTT macro expands into a RTI.  This is so RTTs can be used in
; places where they would be called for on 11/40s, 11/45s etc.
.macro	rtt
	rti
.endm


; XOR macro simulates XOR instruction on 11/45.
; Caution: this macro is not intended to work with
; (Rn)+, -(Rn) or (SP) destinations.
.macro	xor r,d
.nlist
	mov r,-(sp)
	bic d,(sp)
	bic r,d
	bis (sp)+,d
.list
.endm


; SXT macro performs sign extend as on PDP11/45. (requires if/else macro)
.macro	sxt d
.nlist
	if mi,<mov #-1,d>
	else <clr d>
.list
.endm

.endc	; hasxor


%muldv==0			;not needed, or in hardware
.if eq  haseis
; ASH macro generates a series of ASR or ASL instructions to
; simulate the 11/45 ASH instruction.
.macro	ash src,r
.ntype %.m,r
.iif ne  %.m&70,	.error ASH dst must be register
.ntype %.m,src
.iif ne  %.m-27,	.error ASH macro must have constant shift
%.m===0'src
	.if ge  %.m
	 .rept %.m
	  asl r
	  .endr
	.iff
	 .rept -%.m
	  asr r
	  .endr
	.endc
.endm


; MUL macro generates call to either MUL1 or MUL2 depending upon
; whether register destination is even or odd.  Simulates 11/45 MUL.

.macro	mul src,r
.ntype %.m,r
.iif ne  %.m&70,	.error MUL dst must be register
	mov src,-(sp)
	mov r,-(sp)
	.iif ne  %.m&1,	jsr r5,mul1
	.ielse		jsr r5,mul2
	mov (sp)+,r
	.iif eq  %.m&1,	mov (sp)+,r+1
%muldv==-1
.endm


; DIV macro generates call to DIV2 to simulate 11/45 DIV instruction.
.macro	div src,r
.ntype %.m,r
.iif ne  %.m&70,	.error DIV dst must be register
	mov r,-(sp)
	mov r+1,-(sp)
	mov src,-(sp)
	jsr r5,div2
	mov (sp)+,r+1
	mov (sp)+,r
%muldv==-1
.endm

.endc	; eq haseis