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65 lines
2.0 KiB
Plaintext
65 lines
2.0 KiB
Plaintext
09/06/93 JMBW Created (from KSDEFS, ucode, and Alan's email)
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Page tables are pointed to by DBR1-DBR4: ("descriptor base registers")
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DBR1 user space low 128K
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DBR2 user space high 128K
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DBR3 exec space high 128K
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DBR4 exec space low 128K (not present on all KA10 paging boxes)
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(identity mapped in ITS anyway)
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Each DBR contains the physical address of a 64-word block:
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LH RH
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+-----+-----+
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| 0 | 1 |
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+-----+-----+
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| 2 | 3 |
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. . .
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. . .
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| 174 | 175 |
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+-----+-----+
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| 176 | 177 |
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+-----+-----+
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where halfwords 0-177 contain the entries for pages 0-177 (1K each) in the
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segment addressed by that DBR.
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Note that the EPT and UPT have nothing to do with paging.
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Page table entry (halfword):
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1 1 1 1 1 1 1 1
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0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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|ACC|///|A|C|///| PHYSICAL PAGE NO. |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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ACC (access)
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00 no access allowed
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01 read only
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10 read/write/first (=01, for software "dirty" bit)
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11 read/write
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A (age bit)
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cleared on first access (was 3-bit field on KA10, set to 000)
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C (cacheable)
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if 1, data from this page may be put in cache
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The physical page # is the ITS page # (not DEC), i.e. shift the page number
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left ten bits to get the absolute base address of the 1K page.
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The DBRs are loaded by the LDBR1-LDBR4 instructions (which usurp the opcodes
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for WRSPB, WRCSB, WRPUR, and WRCSTM), which also flush the cache and both
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halves of the TLB (including the half not mapped by the DBR being loaded).
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These instructions use the immediate operand as the physical address of the
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page tables, which means they have to be in the first 256K (Alan says in fact
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they are always in the first 128K). The user DBRs can also be loaded by LPMR
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(702^9 17,), which also loads the quantum timer (and the JPCs, if supported by
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this microcode).
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The DBRs may be retrieved by SDBR1-SDBR4 (which usurp RDSPB, RDCSB, RDPUR,
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RDCSTM), which each store the DBR at the address given by the EA. Similarly,
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SPM (702^9 7,) is the reverse of LPMR.
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