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84 lines
2.9 KiB
Plaintext
Executable File
84 lines
2.9 KiB
Plaintext
Executable File
;;; -*- Mode: Midas -*-
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;;; Copyright (c) 1999 Massachusetts Institute of Technology
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;;; See the COPYING file at the top-level directory of this project.
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.AUXIL
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;;; Canonical symbol definition macro, FOO==BAR with error check.
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IFNDEF DEFSYM,[
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DEFINE DEFSYM X/
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IRPS Z,,[X]
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IFNDEF Z,X
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.ELSE [ $$TEM1==Z
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X
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IFN Z-$$TEM1,.ERR Z MULTIPLY .QUOTE`.QUOTE/DEFINED/`
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]
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.ISTOP
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TERMIN TERMIN
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$$TEMP==1
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] ;IFNDEF DEFSYM
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.ELSE, $$TEMP==0
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; The ACC IMP interface on the KS implements two separate Unibus IO
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; devices, for input and output. Both of these devices transfer data in
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; 32-bit mode only over the Unibus via DMA. Because of the DMA data
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; transfer the interrupt structure is trivial, and uses NETCHN only.
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;
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; Apparently the reset bits in the two CSRs are wired together, so
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; resetting one side of the machine resets both. This action also drops
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; the HOST READY line to the IMP.
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;
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; You must set %LHSE whenever hte HOST READY line is high, or the IMP
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; will be allowed to freely throw away data. This is true across IMP
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; message boundaries, and even if no input request is active.
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;
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;ACC LH-DH IMP Interface Bits
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;Interrupt information
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DEFSYM %LHVEC==250 ;Input side interrupt vector (non-standard)
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;Output side assumed to be %LHVEC+4
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DEFSYM %LHPRI==6 ;Interrupt priority (non-standard)
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DEFSYM %LHBAS==767600 ;Base of LH/DH Unibus register address space
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;Unibus Registers
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DEFSYM %LHICS=:%LHBAS ;Control and Status, Input side
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DEFSYM %LHIDB=:%LHBAS+2 ;Data Buffer, Input
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DEFSYM %LHICA=:%LHBAS+4 ;Current Word Address, Input
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DEFSYM %LHIWC=:%LHBAS+6 ;Word Count, Input
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DEFSYM %LHOCS=:%LHBAS+10 ;Control and Status, Output side
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DEFSYM %LHODB=:%LHBAS+12 ;Data Buffer, Output
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DEFSYM %LHOCA=:%LHBAS+14 ;Current Word Address, Output
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DEFSYM %LHOWC=:%LHBAS+16 ;Word Count, Output
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;Bits in CSRs
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; Bits common to input and output
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DEFSYM %LHERR==1_15. ;Error present
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DEFSYM %LHNXM==1_14. ;Non Existant Memory on DMA
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DEFSYM %LHMRE==1_9. ;Master Ready Error (ready bounce during xfr)
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DEFSYM %LHRDY==1_7. ;Device Ready (modifying LHDH regs allowed)
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DEFSYM %LHIE==1_6. ;Interrupt Enable
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DEFSYM %LHA17==1_5. ;Address bit 17 for extended unibus xfrs
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DEFSYM %LHA16==1_4. ;Address bit 16 for extended unibus xfrs
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DEFSYM %LHRST==1_1. ;Interface Reset
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DEFSYM %LHGO==1 ;GO - Start DMA Transfer
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; Input side
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DEFSYM %LHEOM==1_13. ;End-of-Message received from IMP
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DEFSYM %LHHR==1_11. ;Host Ready (ACC's relay closed, debounced)
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DEFSYM %LHINR==1_10. ;IMP not ready
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DEFSYM %LHIBF==1_8. ;Input Buffer Full
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DEFSYM %LHSE==1_3. ;Store Enable (0 == flush data instead)
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DEFSYM %LHHRC==1_2. ;Host Ready Relay Control (1 to close relay)
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; Output side
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DEFSYM %LHWC0==1_13. ;Output Word Count is zero
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DEFSYM %LHOBE==1_8. ;Output Buffer Empty
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DEFSYM %LHBB==1_3. ;Bus Back (loopback enable for testing)
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DEFSYM %LHELB==1_2. ;Send EOM indication to IMP at end of xfr
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; (enable Last Bit Flag)
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IFN $$TEMP,EXPUNG DEFSYM
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