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150 lines
5.3 KiB
C
150 lines
5.3 KiB
C
/* DVUBA.H - Definitions for emulating KS10 Unibus Adapters
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*/
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/* $Id: dvuba.h,v 2.3 2001/11/10 21:28:59 klh Exp $
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*/
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/* Copyright © 1992, 1993, 2001 Kenneth L. Harrenstien
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** All Rights Reserved
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**
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** This file is part of the KLH10 Distribution. Use, modification, and
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** re-distribution is permitted subject to the terms in the file
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** named "LICENSE", which contains the full text of the legal notices
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** and should always accompany this Distribution.
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**
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** This software is provided "AS IS" with NO WARRANTY OF ANY KIND.
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**
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** This notice (including the copyright and warranty disclaimer)
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** must be included in all copies or derivations of this software.
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*/
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/*
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* $Log: dvuba.h,v $
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* Revision 2.3 2001/11/10 21:28:59 klh
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* Final 2.0 distribution checkin
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*
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*/
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/*
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** Portions of this file were derived from AI:KSHACK;KSDEFS 193
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*/
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#ifndef DVUBA_INCLUDED
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#define DVUBA_INCLUDED 1
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#ifdef RCSID
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RCSID(dvuba_h,"$Id: dvuba.h,v 2.3 2001/11/10 21:28:59 klh Exp $")
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#endif
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/* Define types to use for holding new-IO unibus addresses and register
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** values.
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** Unibus addresses are 18 bits.
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** Unibus device registers are only 16 bits.
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** Since an "int" is guaranteed to always have at least 16
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** bits, and is normally the most computationally efficient
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** type, that's what we'll use here.
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** All bets are off for the peculiar non-unibus devices such as the
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** memory status register (36-bit) and "unibus adapter" (32-bit).
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**
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*/
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#ifndef WORD10_INT18 /* Ensure uint18 is defined */
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# include "word10.h"
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#endif
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typedef uint18 dvuadr_t; /* Device: Unibus Address */
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typedef unsigned int dvureg_t; /* Device: Unibus Register value */
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#ifndef KLH10_DEVUBA_MAX
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# define KLH10_DEVUBA_MAX 10 /* Max # of devs on each unibus */
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#endif
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/* In the ITS system source,
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** Unibus #1 has mnemonic UBAQ (for QSK => DSK).
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** #3 has mnemonic UBAI
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*/
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/* Unibus Paging RAM - one per Unibus, 0763000-763077 inclusive */
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#define UB_UBAPAG 0763000 /* UBA Paging RAM (One per Unibus) */
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#define UBA_UBALEN 64 /* Length of UBA Paging RAM */
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#define UB_UBAEND (UB_UBAPAG+UBA_UBALEN) /* First non-valid addr */
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/* When read: */
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#define UBA_PPAR 0020000 /* 4.5 RAM parity bit */
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#define UBA_PRPW 0010000 /* 4.4 Force read-pause-write */
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#define UBA_P16B 0004000 /* 4.3 Disable upper two bits on Unibus transfers */
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#define UBA_PFST 0002000 /* 4.2 Fast mode enable */
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#define UBA_PVAL 0001000 /* 4.1 Entry is valid */
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#define UBA_PPVL 0000400 /* 3.9 Parity is valid */
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/*
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$UPPAG==:121200,, ; 3.2 - 2.2 ITS page number
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; 2.1 ITS half page
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; 3.2 - 2.1 DEC page number
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*/
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/* When written: */
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#define UBA_QRPW 0400000 /* 2.9 Force read-pause-write */
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#define UBA_Q16B 0200000 /* 2.8 Disable 18-bit UB xfer (hi 2 bits) */
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#define UBA_QFST 0100000 /* 2.7 Enable Fast (36-bit) xfer mode */
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#define UBA_QVAL 0040000 /* 2.6 Entry is valid */
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#define UBA_QPAG 0003777 /* 2.2 - 1.2 ITS page number */
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/* 1.1 ITS half page */
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/* 2.2 - 1.1 DEC page number */
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/* Unibus Status Register - one per Unibus */
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#define UB_UBASTA 0763100 /* UBA Status Register (One per Unibus) */
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/* [R=Read, W=Write, C=Cleared by writing a 1,
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*=Cleared by any write]
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*/
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#define UBA_BTIM 0400000 /* 2.9 Unibus timeout [R/C] */
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#define UBA_BBAD 0200000 /* 2.8 Bad mem data (on NPR transfer) [R/C] */
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/* (Master will timeout instead if UBA_BDXF set) */
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#define UBA_BPAR 0100000 /* 2.7 KS10 bus parity error [R/C] */
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#define UBA_BNXD 0040000 /* 2.6 CPU addressed non-ex device [R/C] */
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#define UBA_BHIG 0004000 /* 2.3 Intrpt req on BR7 or BR6 (high) [R] */
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#define UBA_BLOW 0002000 /* 2.2 Intrpt req on BR5 or BR4 (low) [R] */
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#define UBA_BPWR 0001000 /* 2.1 Power low [R|*] */
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#define UBA_BDXF 0000200 /* 1.8 Disable xfr on uncorrectable data[R/W]*/
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#define UBA_BINI 0000100 /* 1.7 Issue Unibus init [W] */
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#define UBA_BPIH 0000070 /* 1.6-1.4 PI lev for BR7 or BR6 (hi) [R/W] */
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#define UBA_BPIL 0000007 /* 1.3-1.1 PI lev for BR5 or BR4 (low) [R/W] */
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#define UB_UBAMNT 0763101 /* UBA Maintenance (One per Unibus) */
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/* 1.2 Spare maintenance bit (?)
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1.1 Change NPR address (?)
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*/
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/* Other Unibus devices */
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/* KS10 Memory Status Register, controller 0 */
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#define UB_KSECCS 0100000 /* Memory Status Register, ctlr 0 */
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/* Define internal structure to emulate the above Unibii
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*/
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extern struct ubctl {
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h10_t ubpmap[UBA_UBALEN]; /* Contents of UBA paging RAM */
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h10_t ubsta; /* Unibus Status Register */
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int ubn; /* Unibus # (1 or 3) */
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int ubhilev; /* "High" PI level bit assignment */
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int ublolev; /* "Low" " " " " */
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int *ubpireqs; /* Address of place to put UB PI reqs */
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int ubndevs; /* # devices on bus */
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struct device *ubdevs[KLH10_DEVUBA_MAX+1]; /* Devs on bus */
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dvuadr_t ubdvadrs[KLH10_DEVUBA_MAX*2]; /* Beg and end addrs */
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} dvub1, dvub3;
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extern void dvub_init(void);
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int dvub_add(FILE *, struct device *, int);
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extern uint32 /* All reads return 32 bits */
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ub_read (w10_t), /* (ioaddr) */
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ub_bread(w10_t), /* (ioaddr) */
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uba_read(struct ubctl *, dvuadr_t); /* (ub, uaddr) */
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extern void /* All writes take 18 bits */
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ub_write(w10_t, h10_t), /* (ioaddr, val) */
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ub_bwrite(w10_t, h10_t), /* (ioaddr, val) */
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uba_write(struct ubctl *, dvuadr_t, h10_t); /* (ub, uaddr, val) */
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extern paddr_t ub1_pivget(int); /* For PI system */
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extern paddr_t ub3_pivget(int);
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#endif /* ifndef DVUBA_INCLUDED */
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