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133 lines
5.1 KiB
C
133 lines
5.1 KiB
C
/* DVRH11.H - RH11 Controller definitions
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*/
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/* $Id: dvrh11.h,v 2.3 2001/11/10 21:28:59 klh Exp $
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*/
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/* Copyright © 1992, 1993, 1997, 2001 Kenneth L. Harrenstien
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** All Rights Reserved
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**
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** This file is part of the KLH10 Distribution. Use, modification, and
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** re-distribution is permitted subject to the terms in the file
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** named "LICENSE", which contains the full text of the legal notices
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** and should always accompany this Distribution.
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**
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** This software is provided "AS IS" with NO WARRANTY OF ANY KIND.
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**
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** This notice (including the copyright and warranty disclaimer)
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** must be included in all copies or derivations of this software.
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*/
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/*
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* $Log: dvrh11.h,v $
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* Revision 2.3 2001/11/10 21:28:59 klh
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* Final 2.0 distribution checkin
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*
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*/
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/*
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** Portions of this file were derived from AI:SYSTEM;RH11 DEFS48
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*/
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#ifndef RH11_INCLUDED
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#define RH11_INCLUDED 1
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#ifdef RCSID
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RCSID(dvrh11_h,"$Id: dvrh11.h,v 2.3 2001/11/10 21:28:59 klh Exp $")
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#endif
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#ifndef RH11_NSUP
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# define RH11_NSUP 3
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#endif
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extern struct device *dvrh11_create(FILE *f, char *s); /* Initialization entry point */
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/* RH11 Unibus register definitions:
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*/
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#if 0
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/* Default RH11 addresses and interrupt vectors */
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#define UBA1_RH_ADDR 0776700 /* UBA #1 RH11 registers start here */
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#define UBA1_RH_BR 6 /* Interrupts occur on level 6 (high pri) */
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#define UBA1_RH_VEC 0254 /* with this vector */
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#define UBA3_RH_ADDR 0772440 /* UBA #3 RH11 registers start here */
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#define UBA3_RH_BR 6 /* Interrupts occur on level 6 (high pri) */
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#define UBA3_RH_VEC 0224 /* with this vector */
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#endif
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/* RH11 register definitions. Note that the ordering of these is different
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** from that of the RH20.
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**
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** The CS1 register is shared between the RH11 and the currently selected
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** drive. All others are either completely in the RH11 or completely in
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** each drive. (this info per KSREF.MEM 12/78 p.3-6)
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**
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** RH11-only registers:
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** CS1 bits 15-13, 10-6 inclusive (0163700)
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** WC, BA, CS2, DB
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** Each-Drive registers:
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** CS1 bits 12-11, 5-0 inclusive (0014077)
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** DA, DS, ER1, AS, LA, MR, DT, SN, OF, DC, CC, ER2, ER3, EC1, EC2
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** (Note AS is actually a summary of all drives)
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*/
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#define RH11R_CS1 0 /* (RH/DR) CTRL AND STATUS 1. */
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#define RH11R_WC 1 /* (RH) WORD COUNT. */
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#define RH11R_BA 2 /* (RH) UNIBUS ADDRESS. */
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#define RH11R_ADR 3 /* (DR) DESIRED ADDRESS. */
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#define RH11R_CS2 4 /* (RH) CTRL AND STATUS 2. */
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#define RH11R_STS 5 /* (DR) DRIVE STATUS. */
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#define RH11R_ER1 6 /* (DR) ERROR 1. */
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#define RH11R_ATN 7 /* (DR*) ATTENTION SUMMARY. */
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#define RH11R_LAH 010 /* (DR) LOOK AHEAD. */
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#define RH11R_BUF 011 /* (DR) DATA BUFFER. */
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#define RH11R_MNT 012 /* (DR) MAINTENANCE. */
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#define RH11R_TYP 013 /* (DR) DRIVE TYPE. */
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#define RH11R_SER 014 /* (DR) SERIAL NUMBER. */
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#define RH11R_OFS 015 /* (DR) OFFSET. */
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#define RH11R_CYL 016 /* (DR) DESIRED CYLINDER. */
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#define RH11R_CCY 017 /* (DR) CURRENT CYLINDER (RM03/80 unused) */
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#define RH11R_ER2 020 /* (DR) ERROR 2 (RM03/80 unused) */
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#define RH11R_ER3 021 /* (DR) ERROR 3 */
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#define RH11R_POS 022 /* (DR) ECC POSITION. */
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#define RH11R_PAT 023 /* (DR) ECC PATTERN. */
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#define RH11R_N 024 /* # of RH11 registers */
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/* RH-internal register bits */
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#define RH_CS1_RH11 0163700 /* RH11 bits in CS1 */
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#define RH_CS1_DRIVE 014077 /* DR bits in CS1: Bit12+RH_XDVA+RH_XCMD */
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/* CS1: (RH/DR) CTRL AND STATUS 1 */
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/* Apparently only RH_XTRE and RH_XMCP cause errors */
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/* SC is only set if some ATTN bits are on */
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#define RH_XSC (1<<15) /* [RH] RO -I Special Condition */
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#define RH_XTRE (1<<14) /* [RH] R/W 2 Transfer Error (set it to clear?) */
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#define RH_XMCP (1<<13) /* [RH] RO 2 Control Bus Parity Error */
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/* (1<<12) * [dr] ??? */
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#define RH_XDVA (1<<11) /* [dr] RO - Drive Available */
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#define RH_XPSE (1<<10) /* [RH] ? - Port Select */
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#define RH_XA17 (1<<9) /* [RH] R/W - UB Address Extension Bit 17 */
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#define RH_XA16 (1<<8) /* [RH] R/W - UB Address Extension Bit 16 */
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#define RH_XRDY (1<<7) /* [RH] RO 2 Ready (for next command) */
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#define RH_XIE (1<<6) /* [RH] R/W 2 Interrupt Enable */
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#define RH_XCMD 077 /* [dr] R/W 2 Bits 1-5 specify commands. */
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#define RH_XGO (1<<0) /* [dr] R/W 2 GO bit */
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/* CS2: (RH) CTRL AND STATUS 2 */
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/* [i2] - Used by ITS,T20 */
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#define RH_YDLT (1<<15) /* RO 2 Data Late == CSW_OVN Overrun */
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#define RH_YWCE (1<<14) /* RO - Write Check Error */
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#define RH_YPE (1<<13) /* RO 2 Parity Error == CSW_MPAR */
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#define RH_YNED (1<<12) /* RO 2 Non-existant Drive */
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#define RH_YNEM (1<<11) /* RO 2 BA is NXM during DMA == CSW_NXM */
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#define RH_YPGE (1<<10) /* RO 2 Program Error == CSW_RH20E RH error */
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#define RH_YMXF (1<<9) /* RO 2 Missed Transfer == CSW_RH20E RH error */
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#define RH_YMDP (1<<8) /* RO 2 Mass Data Bus Parity Error == CSW_MPAR */
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#define RH_YOR (1<<7) /* ? - Output Ready (for Silo buffer diag.) */
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#define RH_YIR (1<<6) /* ? - Input Ready (for Silo buffer diag.) */
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#define RH_YCLR (1<<5) /* R/W 2 Controller Clear */
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#define RH_YPAT (1<<4) /* ? - Parity Test */
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#define RH_YBAI (1<<3) /* ? - Unibus Address Increment Inhibit */
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#define RH_YDSK 07 /* R/W 2 Unit Select */
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#endif /* ifndef RH11_INCLUDED */
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