mirror of
https://github.com/PDP-10/klh10.git
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58b59dbaa1
by the late MRC, Mark Crispin. Source: probably the former http://panda.com/tops-20/ . panda-dist.tar.gz dated Mar 30 2007.
719 lines
22 KiB
C
719 lines
22 KiB
C
/* INMOVE.C - Word move instruction routines
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*/
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/* $Id: inmove.c,v 2.3 2001/11/10 21:28:59 klh Exp $
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*/
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/* Copyright © 1992, 1993, 2001 Kenneth L. Harrenstien
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** All Rights Reserved
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**
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** This file is part of the KLH10 Distribution. Use, modification, and
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** re-distribution is permitted subject to the terms in the file
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** named "LICENSE", which contains the full text of the legal notices
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** and should always accompany this Distribution.
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**
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** This software is provided "AS IS" with NO WARRANTY OF ANY KIND.
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**
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** This notice (including the copyright and warranty disclaimer)
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** must be included in all copies or derivations of this software.
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*/
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/*
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* $Log: inmove.c,v $
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* Revision 2.3 2001/11/10 21:28:59 klh
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* Final 2.0 distribution checkin
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*
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*/
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#include "klh10.h"
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#include "kn10def.h" /* Machine defs */
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#include "kn10ops.h" /* PDP-10 ops */
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#ifdef RCSID
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RCSID(inmove_c,"$Id: inmove.c,v 2.3 2001/11/10 21:28:59 klh Exp $")
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#endif
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/* See CODING.TXT for guidelines to coding instruction routines. */
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/* Full-word data stuff */
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insdef(i_exch) /* EXCH AC,E */
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{
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register vmptr_t p = vm_modmap(e); /* Check access, get pointer */
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register w10_t w;
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w = vm_pget(p); /* Save mem in temporary loc */
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vm_pset(p, ac_get(ac)); /* Move c(AC) to E */
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ac_set(ac, w); /* Move c(E) to AC */
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return PCINC_1;
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}
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/* MOVEx group - MOVE, MOVEI, MOVEM, MOVES */
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insdef(i_move) /* MOVE AC,E */
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{
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ac_set(ac, vm_read(e));
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return PCINC_1;
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}
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insdef(i_movei) /* MOVEI AC,E */
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{
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ac_setlrh(ac, 0, va_insect(e));
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return PCINC_1;
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}
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insdef(i_movem) /* MOVEM AC,E */
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{
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vm_write(e, ac_get(ac));
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return PCINC_1;
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}
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insdef(i_moves) /* MOVES AC,E */
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{
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register vmptr_t p = vm_modmap(e); /* Make write access ref */
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if (ac) ac_set(ac, vm_pget(p));
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return PCINC_1;
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}
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/* MOVSx group - MOVS, MOVSI, MOVSM, MOVSS */
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insdef(i_movs) /* MOVS AC,E */
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{
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register w10_t w;
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w = vm_read(e);
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ac_setlrh(ac, RHGET(w), LHGET(w));
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return PCINC_1;
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}
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insdef(i_movsi) /* MOVSI AC,E */
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{
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ac_setlrh(ac, va_insect(e), 0);
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return PCINC_1;
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}
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insdef(i_movsm) /* MOVSM AC,E */
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{
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register w10_t w;
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LRHSET(w, ac_getrh(ac), ac_getlh(ac));
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vm_write(e, w);
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return PCINC_1;
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}
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insdef(i_movss) /* MOVSS AC,E */
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{
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register vmptr_t p = vm_modmap(e); /* Make R/W access ref */
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register w10_t w;
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LRHSET(w, vm_pgetrh(p), vm_pgetlh(p));
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vm_pset(p, w); /* Store back in mem */
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if (ac) ac_set(ac, w);
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return PCINC_1;
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}
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/* MOVNx group - MOVN, MOVNI, MOVNM, MOVNS */
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insdef(i_movn) /* MOVN AC,E */
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{
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register w10_t w;
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w = vm_read(e);
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op10mf_movn(w); /* Negate, setting flags if necessary */
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ac_set(ac, w);
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return PCINC_1;
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}
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insdef(i_movni) /* MOVNI AC,E */
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{
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register w10_t w;
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LRHSET(w, 0, va_insect(e));
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op10mf_movn(w); /* Negate, setting flags if 0 */
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ac_set(ac, w);
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return PCINC_1;
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}
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insdef(i_movnm) /* MOVNM AC,E */
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{
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register vmptr_t p = vm_wrtmap(e); /* Check mem ref first */
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register w10_t w;
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w = ac_get(ac);
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op10mf_movn(w); /* Negate, setting flags if necessary */
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vm_pset(p, w);
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return PCINC_1;
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}
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insdef(i_movns) /* MOVNS AC,E */
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{
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register vmptr_t p = vm_modmap(e); /* Check mem ref first */
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register w10_t w;
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w = vm_pget(p);
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op10mf_movn(w); /* Negate, setting flags if necessary */
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vm_pset(p, w);
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if (ac) ac_set(ac, w);
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return PCINC_1;
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}
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/* MOVMx group - MOVM, MOVMI, MOVMM, MOVMS */
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insdef(i_movm) /* MOVM AC,E */
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{
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register w10_t w;
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w = vm_read(e);
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op10mf_movm(w); /* Make pos, setting flags if necessary */
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ac_set(ac, w);
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return PCINC_1;
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}
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#if 0
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insdef(i_movmi) /* MOVMI AC,E is identical to MOVEI AC,E */
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#endif
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insdef(i_movmm) /* MOVMM AC,E */
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{
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register vmptr_t p = vm_wrtmap(e); /* Check mem ref first */
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register w10_t w;
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w = ac_get(ac);
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op10mf_movm(w); /* Make pos, setting flags if necessary */
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vm_pset(p, w);
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return PCINC_1;
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}
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insdef(i_movms) /* MOVMS AC,E */
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{
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register vmptr_t p = vm_modmap(e); /* Check mem ref first */
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register w10_t w;
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w = vm_pget(p);
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op10mf_movm(w); /* Make pos, setting flags if necessary */
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vm_pset(p, w);
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if (ac) ac_set(ac, w);
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return PCINC_1;
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}
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/* Double-word data move instructions.
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** DMOVE and DMOVEM are handled differently from the other instructions
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** that manipulate double words, for greater efficiency.
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**
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** There is a large fuzzy gray area surrounding the question of page fails
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** for double-word operands. In general the KLH10 tries not to do anything
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** at all if a page fail would happen on either the first or second word,
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** thus avoiding the issue of intermediate results.
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**
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** BUT! Examination of the ucode indicates otherwise:
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** KL DMOVE/DMOVN: Atomic; both words are fetched before any ACs are set.
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** A pagefail on read of 2nd word leaves no ACs changed.
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** KL DMOVEM/DMOVNM: First gets both ACs, then stores.
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** 1st (high) word is stored, then 2nd (low);
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** A pagefail on write of 2nd word leaves 1st already stored.
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**
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** KS DMOVE/DMOVN: same as KL.
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** KS DMOVEM/DMOVNM: 2nd word is stored, then 1st!?
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**
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** The KL diag (DFKEA) agrees with the KL for DMOVE and DMOVEM (DMOVN/M is
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** not tested).
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**
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** Given this discrepancy, the KLH10's approach isn't so bad. But just to
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** be ultra safe, I'll attempt to emulate the KS/KL lossage.
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*/
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/* DMOVE checks to see if the double can be copied directly into the
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** ACs. If not, intermediate storage must be used to allow for the
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** possibility of a page fault between words, or AC/address wraparound, or
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** AC overlap if mem ref is to ACs.
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*/
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insdef(i_dmove) /* DMOVE AC,E */
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{
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/* See if fast move OK, normally true. Hope the testing doesn't end up
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** using more time than the conservative case!
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** NOTE this assumes C structure copies are done sequentially. If this
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** is not true, must test for e == ac+1 instead.
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*/
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if (ac_issafedouble(ac) /* ACs contiguous? */
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&& vm_issafedouble(e) /* Mem locs safe too? */
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&& (va_insect(e) != ac_off(ac,-1))) /* no AC overlap with Mem? */
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*ac_mapd(ac) = vm_pgetd(vm_xrwmap(e,VMF_READ|VMF_DWORD)); /* Yep! */
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else {
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register dw10_t d; /* Conservative case, use intermed stg */
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vm_dread(e, d); /* Fetch the double */
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ac_dset(ac, d); /* Set in ACs */
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}
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return PCINC_1;
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}
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insdef(i_dmovem) /* DMOVEM AC,E */
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{
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/* See if fast move OK, normally true. Hope the testing doesn't end up
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** using more time than the conservative case!
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** NOTE this assumes C structure copies are done sequentially. If this
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** is not true, must test for e == ac-1 instead.
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*/
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if (ac_issafedouble(ac) /* ACs contiguous? */
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&& vm_issafedouble(e) /* Mem locs safe too? */
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&& (va_insect(e) != ac_off(ac,1))) /* no AC overlap with Mem? */
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vm_psetd(vm_xrwmap(e,VMF_WRITE|VMF_DWORD), *ac_mapd(ac)); /* Yep! */
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else {
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register dw10_t d; /* Conservative case, use intermed stg */
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#if KLH10_CPU_KL
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ac_dget(ac, d); /* Get from ACs */
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vm_write(e, d.w[0]); /* Do first word */
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va_inc(e);
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vm_write(e, d.w[1]); /* Do second word */
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#elif KLH10_CPU_KS
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register vaddr_t va;
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ac_dget(ac, d); /* Get from ACs */
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va = e;
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va_inc(va);
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vm_write(va, d.w[1]); /* Do second word first! */
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vm_write(e, d.w[0]); /* Do first word last! */
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#else /* What I'd really prefer to use - atomic double write */
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register vmptr_t p0, p1;
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p0 = vm_xrwmap(e, VMF_WRITE); /* Check access for 1st word */
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va_inc(e); /* Bump E by 1, may wrap funnily */
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p1 = vm_xrwmap(e, VMF_WRITE); /* Check access for 2nd word */
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ac_dget(ac, d); /* Get from ACs */
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vm_pset(p0, d.w[0]); /* Set 1st from AC */
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vm_pset(p1, d.w[1]); /* Set 2nd from AC+1 */
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#endif
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}
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return PCINC_1;
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}
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/* DMOVN is a vanilla double-precision arithmetic instruction.
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** May set flags.
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*/
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insdef(i_dmovn) /* D_MOVN AC,E */
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{
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register dw10_t d;
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vm_dread(e, d); /* Fetch into D */
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op10mf_dmovn(d); /* Negate in place, with flags */
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ac_dset(ac, d); /* Store in ACs */
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return PCINC_1;
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}
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/* DMOVNM requires special-casing due to differing order of operation
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** for the double-word memory store.
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** May set flags. Note flags are set prior to possible page fail,
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** thus potentially losing just like the ucode.
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*/
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insdef(i_dmovnm) /* DMOVNM AC,E */
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{
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register dw10_t d;
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ac_dget(ac, d); /* Fetch AC, AC+1 into D */
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op10mf_dmovn(d); /* Negate in place, with flags! */
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if (vm_issafedouble(e)) /* Fast move OK? */
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vm_psetd(vm_xrwmap(e,VMF_WRITE|VMF_DWORD), d); /* Yep! */
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else {
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#if KLH10_CPU_KL
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vm_write(e, HIGET(d)); /* Do first word */
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va_inc(e);
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vm_write(e, LOGET(d)); /* Do second word */
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#elif KLH10_CPU_KS
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register vaddr_t va;
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va = e;
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va_inc(va);
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vm_write(va, LOGET(d)); /* Do second word first! */
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vm_write(e, HIGET(d)); /* Do first word last! */
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#else /* What I'd really prefer to use - atomic double write */
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register vmptr_t p0, p1;
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p0 = vm_xrwmap(e, VMF_WRITE); /* Check access for 1st word */
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va_inc(e); /* Bump E by 1, may wrap funnily */
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p1 = vm_xrwmap(e, VMF_WRITE); /* Check access for 2nd word */
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vm_pset(p0, HIGET(d)); /* Set 1st (high) */
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vm_pset(p1, LOGET(d)); /* Set 2nd (low) */
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#endif
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}
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return PCINC_1;
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}
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/* BLT. (XBLT is handled by the EXTEND instr code) */
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/* BLT - with optimization for case where dest is source+1.
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** Note test for using same mapping, since BLT can be used for
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** transfers between user and exec maps!
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*/
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/* Note special page map context references for BLT.
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** These are so PXCT can work by twiddling the context pointers.
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** For:
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** Computing E - normal ea_calc() using XEA map
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** Store word to destination - normal XRW map
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** Read word from source - special XBRW map
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*/
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#define vm_srcread(a) (vm_pget(vm_xbrwmap((a), VMF_READ)))
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/* Additional PXCT note for KLX:
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** Uhler claims both source and dest must use the same (previous)
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** context (thus the only valid AC values are 5 and 15 -- bits 10 and 12
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** must always be set!)
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** It isn't clear whether a KLX is expected to ignore those bits
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** and always use previous context, or if it simply does undefined things
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** if those bits are off (requesting current context).
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** For simplicity this code does implement current context mapping
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** even on a KLX, which corresponds to the latter option. As long as
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** the monitor only uses valid AC bit combinations this is okay.
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*/
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/* There are some ambiguities in the DEC PRM p.2-8 description of BLT.
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* Do the KI/KA test for RH[AC] >= RH(E) just as the KS/KL do, or can
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the destination block wrap around?
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[Assume yes, no dest wraparound]
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* What happens if AC *is* in the destination block?
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[Assume value indeterminate unless last word of xfer, then is
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that value.]
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* What happens if AC is in the source block?
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[Assume value indeterminate, but if no pager/int, is original value]
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[WRONG!!!! Turns out that for KS/KL, the AC is updated immediately
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with the final src,,cnt value! So any copy involving that AC as
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source will contain the "final" value. Aborts due to pagefail
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or PI will re-clobber it with the correct intermediate value.
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Exhibited by this test: MOVE 1,[1,,1] ? BLT 1,1
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which leaves 2,,2 in AC1.]
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* Exactly what is left in the AC for the KL case of RH[AC] > RH(E)?
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The PRM says as if the "reverse xfer" happened, but does this
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mean the last locs that wd have been referenced, or the next ones?
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[Assume latter - the "next" ones.]
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* The footnote on PRM p.2-8 claims an extended KL will count from section
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0 up into 1. Exactly what does this mean? That a source block
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could consist of stuff from sect 0 mem, then the ACs (cuz 1,,0-17 is
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used to ref the ACs), then sect 1 mem? What about the optimized
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case where dest == src+1, would this still use the original
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word value or would the BLT start reading from the sect 1 source?
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[Assume we don't need to emulate this lossage. Yeech.]
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* !! Note from Uhler document that source and dest are incremented in-section
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only, even if addresses are global, without altering local/global flag
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that pager uses.
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*/
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insdef(i_blt)
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{
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register int32 cnt; /* Note signed */
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register vaddr_t src, dst;
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register vmptr_t vp;
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#if KLH10_EXTADR
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src = dst = e; /* E sets default section & l/g flag */
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va_setinsect(src, ac_getlh(ac)); /* Set up source addr */
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va_setinsect(dst, ac_getrh(ac)); /* Set up dest addr */
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#else
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va_lmake(src, 0, ac_getlh(ac));
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va_lmake(dst, 0, ac_getrh(ac));
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#endif
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cnt = (va_insect(e) - va_insect(dst)); /* # words to move, less 1 */
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if (cnt <= 0) {
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/* Special case, either just 1 word or dest block would wrap
|
||
** (So-called "reverse transfer" attempt). Main reason for
|
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** handling this specially is to emulate KL rev-xfer weirdness.
|
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*/
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register vmptr_t rp;
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/* First ensure we can carry out the single xfer expected */
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if (!(rp = vm_xbrwmap(src, VMF_READ|VMF_NOTRAP))
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|| !(vp = vm_xrwmap(dst, VMF_WRITE|VMF_NOTRAP))) {
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pag_fail(); /* Ugh, take page-fail trap */
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}
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/* OK, now if KL or KS, pre-clobber AC appropriately *before*
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** the copy, so that if AC is involved, behavior will emulate
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** the machines. Sigh.
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*/
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#if KLH10_CPU_KL
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/* KL always updates as if the full reverse xfer happened */
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ac_setlrh(ac, (va_insect(src)+cnt+1) & H10MASK,
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(va_insect(dst)+cnt+1) & H10MASK);
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#elif KLH10_CPU_KS
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/* KS only reflects what actually got xfered (according to PRM;
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** it may in fact behave like the KL for all I know!)
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*/
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ac_setlrh(ac, (va_insect(src)+1) & H10MASK,
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(va_insect(dst)+1) & H10MASK);
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#endif
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vm_pset(vp, vm_pget(rp)); /* Copy directly from source */
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return PCINC_1;
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}
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#if KLH10_CPU_KS || KLH10_CPU_KL
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||
/* Before starting xfer, clobber AC to final value. This emulates
|
||
** the peculiar way the KS/KL do things. Note that due to this
|
||
** pre-clobberage, there is no need to store a final value at the
|
||
** end of a successful BLT. Any aborts MUST TAKE CARE to store the proper
|
||
** intermediate value!!
|
||
*/
|
||
ac_setlrh(ac, (va_insect(src)+cnt+1) & H10MASK,
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(va_insect(dst)+cnt+1) & H10MASK);
|
||
#endif /* KS || KL */
|
||
|
||
if ((va_insect(src)+1) == va_insect(dst) /* Special case? */
|
||
&& (cpu.vmap.xrw == cpu.vmap.xbrw)) { /* Must have same mapping! */
|
||
|
||
/* Simple set-memory-to-value BLT */
|
||
register w10_t w;
|
||
|
||
/* Get first word and remember that. Just in case it helps the
|
||
** compiler optimize, use xrw map instead of xbrw since we only
|
||
** come here if they're the same.
|
||
*/
|
||
if (!(vp = vm_xrwmap(src, VMF_READ|VMF_NOTRAP))) {
|
||
ac_setlrh(ac, va_insect(src), /* Oops, save AC */
|
||
va_insect(dst));
|
||
pag_fail(); /* Take page-fail trap */
|
||
}
|
||
w = vm_pget(vp); /* Get word, remember it */
|
||
|
||
do {
|
||
CLOCKPOLL(); /* Keep clock going */
|
||
if (INSBRKTEST()) { /* Watch for interrupt */
|
||
ac_setlrh(ac, va_insect(src), /* Oops, save AC */
|
||
va_insect(dst));
|
||
apr_int(); /* Take interrupt */
|
||
}
|
||
if (!(vp = vm_xrwmap(dst, VMF_WRITE|VMF_NOTRAP))) {
|
||
ac_setlrh(ac, va_insect(src), /* Oops, save AC */
|
||
va_insect(dst));
|
||
pag_fail(); /* Take page-fail trap */
|
||
}
|
||
vm_pset(vp, w); /* Store word value */
|
||
va_linc(src); /* Do LOCAL increment of addrs! */
|
||
va_linc(dst);
|
||
} while (--cnt >= 0);
|
||
}
|
||
else do {
|
||
|
||
/* Normal BLT transfer */
|
||
register vmptr_t rp;
|
||
CLOCKPOLL(); /* Keep clock going */
|
||
if (INSBRKTEST()) { /* Watch for interrupt */
|
||
ac_setlrh(ac, va_insect(src), /* Oops, save AC */
|
||
va_insect(dst));
|
||
apr_int(); /* Take interrupt */
|
||
}
|
||
|
||
if (!(rp = vm_xbrwmap(src, VMF_READ|VMF_NOTRAP))
|
||
|| !(vp = vm_xrwmap(dst, VMF_WRITE|VMF_NOTRAP))) {
|
||
ac_setlrh(ac, va_insect(src), /* Oops, save AC */
|
||
va_insect(dst));
|
||
pag_fail(); /* Take page-fail trap */
|
||
}
|
||
vm_pset(vp, vm_pget(rp)); /* Copy directly from source */
|
||
va_linc(src); /* Add 1 to both addrs */
|
||
va_linc(dst); /* Again, LOCAL increment only */
|
||
|
||
} while (--cnt >= 0);
|
||
|
||
#if 0 /* No longer needed, code done inline to avoid this check */
|
||
/* Broke out of loop, see if page-failed or not */
|
||
if (cnt >= 0) { /* Use this as indicator */
|
||
ac_setlrh(ac, va_insect(src), /* Oops, save AC */
|
||
va_insect(dst));
|
||
pag_fail(); /* Ugh, take page-fail trap */
|
||
}
|
||
#endif
|
||
|
||
#if 0 /* KLH10_CPU_KS || KLH10_CPU_KL */
|
||
/* This is no longer used. Instead, to more accurately emulate the
|
||
** KS/KL, the final AC value is stored immediately at the start of
|
||
** the BLT code, so if nothing goes wrong, nothing needs to be done.
|
||
*/
|
||
|
||
/* End of BLT, but KS/KL must leave AC pointing
|
||
** to what would be the next transfer... unless AC happens
|
||
** to be the last destination!
|
||
**
|
||
** vp still points to last destination, so we can use that for testing,
|
||
** avoiding hassle of determining whether dst is an ac reference!
|
||
*/
|
||
if (ac_map(ac) != vp)
|
||
ac_setlrh(ac, va_insect(src), va_insect(dst));
|
||
#endif /* KS || KL */
|
||
|
||
return PCINC_1;
|
||
}
|
||
|
||
#if 0 /* Old version, saved in memory of simpler times */
|
||
|
||
insdef(i_blt)
|
||
{
|
||
register w10_t w, val;
|
||
register int optim;
|
||
|
||
e &= H10MASK;
|
||
w = ac_get(ac); /* Get src,,dst */
|
||
|
||
if ((LHGET(w)+1)&H10MASK == RHGET(w)) /* Special case? */
|
||
&& (cpu.vmap.xrw == cpu.vmap.xbrw)) { /* Must be same mapping! */
|
||
val = vm_srcread(LHGET(w));
|
||
optim = TRUE;
|
||
} else optim = FALSE;
|
||
for (;;) {
|
||
vm_write(RHGET(w), (optim ? val : vm_srcread(LHGET(w))));
|
||
if (RHGET(w) >= e) { /* Last word? Note also stop if AC.rh > E */
|
||
break; /* Win! */
|
||
}
|
||
LHSET(w, (LHGET(w)+1)&H10MASK); /* Add 1 to both halves */
|
||
RHSET(w, (RHGET(w)+1)&H10MASK);
|
||
ac_set(ac, w); /* Store back in AC in case of pagefail */
|
||
|
||
CLOCKPOLL(); /* Keep clock going */
|
||
if (INSBRKTEST()) apr_int(); /* Watch for interrupt */
|
||
}
|
||
|
||
/* End of BLT, but to emulate KS10 exactly must leave AC pointing
|
||
** to what would be the next transfer... unless AC is last destination.
|
||
*/
|
||
if (ac != RHGET(w)) {
|
||
LHSET(w, (LHGET(w)+1)&H10MASK); /* Add 1 to both halves */
|
||
RHSET(w, (RHGET(w)+1)&H10MASK);
|
||
ac_set(ac, w); /* Store back in AC */
|
||
}
|
||
return PCINC_1;
|
||
}
|
||
#endif /* 0 - old version */
|
||
|
||
/* BLTBU and BLTUB
|
||
**
|
||
** New KS10 instructions, not documented in PRM; behavior here is based
|
||
** on description from Alan. These are like BLT but transfer blocks of 8-bit
|
||
** bytes, packing or unpacking between "Byte format" and "Unibus format".
|
||
**
|
||
** "Byte format" is the normal PDP-10 format:
|
||
** <byte0><byte1><byte2><byte3><4 unused bits>
|
||
**
|
||
** "Unibus format" is sort of like the screwy PDP-11 byte order:
|
||
** <2-bits><byte1><byte0><2-bits><byte3><byte2>
|
||
**
|
||
** It isn't clear whether the <2-bits> fields are meaningful or whether they
|
||
** are mapped to and from the 4-bit field in Byte format.
|
||
** [Assume not mapped; extra bits are cleared in both directions]
|
||
**
|
||
** [Alan sez:
|
||
** Of course in the case of a device that can put 18 bits of data on the
|
||
** Unibus, the extra bits show up where the diagram says "2 BITS". (There is
|
||
** a bit in the UBA map that says whether the UBA should expect 18-bit data to
|
||
** be written to that page. I have no idea what happens if you set it wrong,
|
||
** perhaps it just controls whether the extra bits are passed through or
|
||
** written as 0.)]
|
||
*/
|
||
|
||
|
||
#if KLH10_CPU_KS
|
||
|
||
/* BLTBU - Like BLT but transforms each word from Byte to Unibus format.
|
||
** BLTUB - Ditto, Unibus to Byte format.
|
||
** For more explanation of the code, see BLT.
|
||
*/
|
||
#define defblt(name) \
|
||
insdef(name) { register w10_t w, val; \
|
||
register vaddr_t src, dst; \
|
||
register uint18 stop = va_insect(e); \
|
||
w = ac_get(ac); \
|
||
va_lmake(src, 0, LHGET(w)); \
|
||
va_lmake(dst, 0, RHGET(w)); \
|
||
for (;;) { \
|
||
val = vm_srcread(src); \
|
||
blttransform(val); \
|
||
vm_write(dst, val); \
|
||
if (RHGET(w) >= stop) \
|
||
break; \
|
||
LHSET(w, (LHGET(w)+1)&H10MASK); \
|
||
RHSET(w, (RHGET(w)+1)&H10MASK); \
|
||
ac_set(ac, w); \
|
||
CLOCKPOLL(); \
|
||
if (INSBRKTEST()) apr_int(); \
|
||
va_inc(src); \
|
||
va_inc(dst); \
|
||
} \
|
||
if (ac != RHGET(w)) { \
|
||
LHSET(w, (LHGET(w)+1)&H10MASK); \
|
||
RHSET(w, (RHGET(w)+1)&H10MASK); \
|
||
ac_set(ac, w); \
|
||
} \
|
||
return PCINC_1; \
|
||
}
|
||
|
||
/* Byte fmt to Unibus fmt, clears extra bits */
|
||
#define blttransform(v) \
|
||
RHSET(v, ((RHGET(v)<<4)&(0377<<8)) \
|
||
| ((LHGET(v)&03)<<6) | ((RHGET(v)>>12)&077) ); \
|
||
LHSET(v, ((LHGET(v)>>10)&0377) | ((LHGET(v)<<6)&(0377<<8)) )
|
||
defblt(i_bltbu)
|
||
#undef blttransform
|
||
|
||
|
||
/* Unibus fmt to Byte fmt, clears extra bits */
|
||
#define blttransform(v) \
|
||
LHSET(v, ((LHGET(v)&0377)<<10) \
|
||
| ((LHGET(v)&(0377<<8))>>6) \
|
||
| ((RHGET(v)>>6)&03) ); \
|
||
RHSET(v, ((RHGET(v)>>4)&(0377<<4)) \
|
||
| ((RHGET(v)&&077)<<12) )
|
||
defblt(i_bltub)
|
||
#undef blttransform
|
||
|
||
#endif /* KS */
|
||
|
||
#if KLH10_EXTADR
|
||
|
||
/* XMOVEI and XHLLI.
|
||
** These two instructions are not as straightforward as they
|
||
** might seem. One might expect them to simply:
|
||
** (1) use whatever the section number of the EA is, or
|
||
** (2) always set LH = 1 if reference is to an AC.
|
||
**
|
||
** In fact, they do neither.
|
||
** The use of LH=1 to represent a global AC address happens ONLY if:
|
||
** (a) EA is local, (b) section # is non-zero, and (c) in-section
|
||
** address is 0-17 inclusive.
|
||
**
|
||
** In particular, a local reference to 0,,AC (even if made while PC_ISEXT)
|
||
** will be stored as 0,,AC and not 1,,AC.
|
||
** Likewise, a global reference to 0,,AC is stored as 0,,AC even though
|
||
** it *DOES* reference the ACs, just like 1,,AC!
|
||
**
|
||
** The following table sums it up:
|
||
**
|
||
** LOCAL 0,,AC => 0,,AC
|
||
** LOCAL NZ,,AC => 1,,AC
|
||
** LOCAL *,,NAC => *,,NAC
|
||
** GLOBAL *,,* => *,,*
|
||
**
|
||
** This behavior is coded into the va_iscvtacref() macro.
|
||
**
|
||
** Finally, this same conversion is also done for the EA stored as a result
|
||
** of a LUUO, MUUO, or pagefail trap.
|
||
** (what about PC?)
|
||
*/
|
||
|
||
/* XMOVEI - Actually an extended SETMI.
|
||
** Special boolean variant when using extended addressing
|
||
*/
|
||
insdef(i_xmovei)
|
||
{
|
||
if (va_iscvtacref(e))
|
||
ac_setlrh(ac, 1, va_insect(e)); /* Global AC reference */
|
||
else
|
||
ac_setlrh(ac, va_sect(e), va_insect(e));
|
||
return 1;
|
||
}
|
||
|
||
|
||
/* XHLLI - Actually an extended HLLI.
|
||
** Special halfword variant when using extended addressing
|
||
*/
|
||
insdef(i_xhlli)
|
||
{
|
||
if (va_iscvtacref(e))
|
||
ac_setlh(ac, 1); /* Global AC reference */
|
||
else
|
||
ac_setlh(ac, va_sect(e));
|
||
return 1;
|
||
}
|
||
|
||
#endif /* KLH10_EXTADR */
|