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237 lines
9.4 KiB
C
237 lines
9.4 KiB
C
/* DVRH20.H - RH20 Massbus Controller definitions (generic)
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*/
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/* $Id: dvrh20.h,v 2.3 2001/11/10 21:28:59 klh Exp $
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*/
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/* Copyright © 1993, 2001 Kenneth L. Harrenstien
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** All Rights Reserved
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**
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** This file is part of the KLH10 Distribution. Use, modification, and
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** re-distribution is permitted subject to the terms in the file
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** named "LICENSE", which contains the full text of the legal notices
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** and should always accompany this Distribution.
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**
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** This software is provided "AS IS" with NO WARRANTY OF ANY KIND.
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**
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** This notice (including the copyright and warranty disclaimer)
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** must be included in all copies or derivations of this software.
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*/
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/*
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* $Log: dvrh20.h,v $
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* Revision 2.3 2001/11/10 21:28:59 klh
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* Final 2.0 distribution checkin
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*
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*/
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#ifndef RH20_INCLUDED
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#define RH20_INCLUDED 1
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#ifdef RCSID
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RCSID(dvrh20_h,"$Id: dvrh20.h,v 2.3 2001/11/10 21:28:59 klh Exp $")
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#endif
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#ifndef RH20_NSUP
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# define RH20_NSUP 8
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#endif
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extern struct device *dvrh20_create(FILE *, char *);
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/* RH20 Massbus Data Channel definitions
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*/
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/* Channel Status/Logout area in the EPT
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*/
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#define RH20_EPT_CCL(n) (0+(n<<2)) /* Channel Command List */
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#define RH20_EPT_CST(n) (1+(n<<2)) /* Channel Status & Pointer */
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#define RH20_EPT_CCW(n) (2+(n<<2)) /* Current Channel Cmd Word */
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#define RH20_EPT_CIV(n) (3+(n<<2)) /* Unused by hardware; software
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** uses for PI vectoring
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*/
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/* Format of Channel Command Word
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*/
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#define CCW_OP 0700000 /* LH: Channel Command Opcode */
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# define CCW_HLT 0000000 /* LH: HALT opcode */
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# define CCW_JMP 0200000 /* LH: JUMP opcode */
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# define CCW_XFR 0400000 /* LH: XFER opcode, plus next 2 bits: */
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# define CCW_XHLT 0200000 /* LH: Xfer cmd: "Halt after xfer" */
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# define CCW_XREV 0100000 /* LH: Xfer cmd: "Reverse xfer" */
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#define CCW_CNT 077760 /* LH: Word Count (positive) */
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#define CCW_ADR 017 /* LH: High bits of 22-bit address */
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/* B18-35 Low bits of ditto */
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/* Channel Status Word
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*/
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#define CSW_SET 0400000 /* B0 - Always set 1 */
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#define CSW_MPAR 0200000 /* B1 - Mem Par Err during CCW fetch */
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#define CSW_NOAPE 0100000 /* B2 - Set if NO mem addr par err */
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#define CSW_NOWC0 040000 /* B3 - CCW count NOT 0 when CSW set */
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#define CSW_NXM 020000 /* B4 - Chan referenced NXM */
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#define CSW_LXFE 0400 /* B9 - Last Transfer Error */
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#define CSW_RH20E 0200 /* B10 - RH20 tried to start not-ready chn */
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#define CSW_LWCE 0100 /* B11 - Long Word Count Error */
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#define CSW_SWCE 040 /* B12 - Short Word Count Error */
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#define CSW_OVN 020 /* B13 - Overrun */
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#define CSW_HIADR 017 /* B14-17 High bits of 22-bit CCW addr+1 */
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/* B18-35 Low bits of ditto */
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#define CSW_CLRSET (CSW_SET|CSW_NOAPE) /* Set CSW to this when clearing */
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/* RH20 Device Number assignment
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*/
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#define DEVRH20(n) (0540+((n)<<2))
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/* RH20 CONO bits.
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*/
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#define RH20CO_CRAE 04000 /* B24 - Clears RAE and associated PI req */
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#define RH20CO_CMC 02000 /* B25 - Clear Massbus Controller. Resets
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** RH20 and all drives to power-up state.
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** Will hang channel if xfer in progress,
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** unless RCLP also set.
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*/
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#define RH20CO_TEC 01000 /* B26 - Clear all xfer error indicators */
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#define RH20CO_MBE 0400 /* B27 - MassBus Enable */
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#define RH20CO_RCLP 0200 /* B28 - Reset Cmd List Ptr (inits channel) */
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#define RH20CO_DSCRF 0100 /* B29 - Clears cmd file xfer if hung
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** (ie if previous data xfer caused xfer
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** error, CONI bits 18-23, 26).
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*/
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#define RH20CO_MEAE 040 /* B30 - Allow Massbus ATTN to generate PI */
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#define RH20CO_ST 020 /* B31 - Stop Transfer. (nothing cleared) */
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#define RH20CO_CCMD 010 /* B32 - Clear Cmd Done, clears CONI bit 32
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** and associated PI request.
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*/
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#define RH20CO_PIA 07 /* B33-35 - PI channel assignment (0 = none) */
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/* RH20 CONI bits.
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*/
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#define RH20CI_DPE 0400000 /* B18 - Data Parity Error */
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#define RH20CI_DEE 0200000 /* B19 - Drive Exception (xfer error) */
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#define RH20CI_LWCE 0100000 /* B20 - Long Word Count Error */
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#define RH20CI_SWCE 040000 /* B21 - Short Word Count Error */
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#define RH20CI_CE 020000 /* B22 - Channel Error */
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#define RH20CI_DR 010000 /* B23 - Drive Response Error (ie no-ex) */
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#define RH20CI_RAE 04000 /* B24 - External Register Address error */
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#define RH20CI_CNR 02000 /* B25 - Channel Ready */
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#define RH20CI_DOE 01000 /* B26 - Data Overrun */
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#define RH20CI_MBE 0400 /* B27 - MassBus Enable */
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#define RH20CI_MBA 0200 /* B28 - MassBus ATTN */
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#define RH20CI_SCRF 0100 /* B29 - Secondary regs loaded */
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#define RH20CI_MBAE 040 /* B30 - Enable PI on RH20CI_MBA */
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#define RH20CI_PCRF 020 /* B31 - Primary regs loaded, xfer in progrs */
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#define RH20CI_CMD 010 /* B32 - Command Done */
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#define RH20CI_PIA 07 /* B33-35 - PIA set by previous CONO */
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/* RH20 DATAO/DATAI word format
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** If the LR bit of the word is clear, the prep reg is written.
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** Otherwise, the RS field selects the register to write, but
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** the RS, DRAES, and DS fields are always copied to the prep reg.
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** Normally the read and write formats are the same, except for
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** a few bits in the word returned from external regs.
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*/
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/* Bits used for writes to prep reg and external regs */
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#define RH20DO_RS 0770000 /* LH: Register Select */
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#define RH20DO_LR 04000 /* LH: Load Register (0 = prep reg) */
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#define RH20DO_DRAES 0400 /* LH: DRAE Suppress */
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#define RH20DO_DS 07 /* LH: Drive Select */
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#define RH20DO_CBEP 0400000 /* RH: Cause even parity error (diag only) */
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/* Additional external reg bits used for DATAI */
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#define RH20DI_CBPE 01000 /* LH: Control Bus Par Err during DATAI */
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#define RH20DI_TRA 0200 /* LH: Transfer Received */
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#define RH20DI_CPA 0200000 /* RH: State of parity bit on massbus */
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#define RH20DI_ERD 0177777 /* RH: External Register Data (16 bits) */
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/* Bits used for internal BAR */
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#define RH20DO_ADR 0177777 /* RH: Disk: BlkAdr, Tape: FrameCnt */
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/* Bits used for internal TCR */
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#define RH20DO_RCLP 02000 /* LH: Reset Channel when xfer started */
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#define RH20DO_SES 0200 /* LH: Store Chan Status at end of xfer */
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#define RH20DO_DTES 0200000 /* RH: Prevent drive errs from stopping xfer */
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#define RH20DO_NBC 0177700 /* RH: Negative block count (sectors/recs) */
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#define RH20DO_MFC 077 /* RH: Drive command code to use for xfer */
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/* Bits used for internal IVIR */
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# define RH20DO_IVR 0777 /* RH: EPT offset for PI function word */
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/* RH20 register definitions:
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The RH20 has provision for 64 (0100) registers. Only the
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high 8 of these (070-077) are in the RH20 itself (internal); the others are
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registers of the currently selected drive (external).
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*/
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/* RH20 Internal Registers.
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** Note:
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** There is also a "preparation register" that is set by all DATAOs
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** and used to set up the source for a DATAI, although the register
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** itself is not directly addressed.
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*/
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#define RH20_1ST 070 /* First internal register */
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#define RH20_SBAR 070 /* R/W Secondary Block Address Reg */
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#define RH20_STCR 071 /* R/W Secondary Transfer Control Reg */
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#define RH20_PBAR 072 /* RO Primary Block Address Reg */
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#define RH20_PTCR 073 /* RO Primary Transfer Control Reg */
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#define RH20_IVIR 074 /* R/W Interrupt Vector Index Reg */
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#define RH20_RR 075 /* RO Read Reg (Diagnostic only) */
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#define RH20_WR 076 /* WO Write Reg (Diagnostic only) */
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#define RH20_DCR 077 /* WO Diagnostic Control Reg (Diags only) */
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/* RH20 External Registers.
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** These are not necessarily defined or used by the respective drives,
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** but do provide a standard framework.
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** Those commented as [I2] are external regs that T20 claims are
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** device independent. [-2] are apparently unused by KL T20.
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**
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** RH11 regs not in drive: CS1 (partial), CS2, WC, BA, ATN?
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** RH11 drive regs unknown mapping: BUF
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*/
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/* RH11 RP07 */
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#define RHR_CSR 0 /* R/W CS1 CS1 Control/command */
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#define RHR_STS 01 /* RO [I2] STS DS Status */
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#define RHR_ER1 02 /* R/W ER1 ER1 Error 1 */
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#define RHR_MNT 03 /* R/W [-2] MNT MR1 Maintenance */
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#define RHR_ATTN 04 /* R/W [I2] ATN AS Attention Summary */
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#define RHR_BAFC 05 /* R/W [I2] ADR DA Block Addr or Frame Cnt */
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#define RHR_DT 06 /* RO [I2] TYP DT Drive Type */
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#define RHR_LAH 07 /* RO LAH LA Cur BlkAdr or R/W ChkChr */
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#define RHR_SN 010 /* RO [-2] SER SN [*] Serial Number */
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#define RHR_OFTC 011 /* R/W OFS OF Offset or TapeControl */
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#define RHR_DCY 012 /* R/W CYL DC Desired Cylinder Addr */
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#define RHR_CCY 013 /* RO [-2] CCY CC Current Cylinder Addr */
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#define RHR_ER2 014 /* R/W ER2 ER2 [*] Error 2 */
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#define RHR_ER3 015 /* R/W ER3 ER3 Error 3 */
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#define RHR_EPOS 016 /* RO POS EC2? ECC Position */
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#define RHR_EPAT 017 /* RO PAT EC2? ECC Pattern */
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#define RHR_N 020 /* # of RH20 external registers */
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/* [*] NOTE!!
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** There is a discrepancy in the RH20 doc, p. RH/2-20, External
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** Register Summary. Register 10 is shown as ER2 and reg 14 as SN,
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** which disagrees with virtually everything else I've seen, which
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** have reg 10=SN and reg 14=ER2 !!! The following refs all agree
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** on this latter interpretation:
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**
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** T20 RP04 defs in PHYP4.MAC.
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** T10 RH20 defs in DEVPRM.MAC.
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** RP07 Tech Manual.
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** TM03 Tech Manual and T20 defs.
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**
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** Hence, I've gone with the latter in my above definitions.
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**
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** NOTE!
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** Not clear what is actually returned in ATTN. RH20 doc says all
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** drives respond when RS=ATTN, so resulting value is somehow a summary
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** of the ATTN bit for all drives. If pattern is same as that for RH11
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** then unit 0 is rightmost bit. From T20 code this appears to be true.
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*/
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#endif /* ifndef RH20_INCLUDED */
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