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105 lines
3.8 KiB
C
105 lines
3.8 KiB
C
/* DVLHDH.H - ACC LH-DH IMP Interface definitions
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*/
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/* $Id: dvlhdh.h,v 2.3 2001/11/10 21:28:59 klh Exp $
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*/
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/* Copyright © 1992, 1993, 2001 Kenneth L. Harrenstien
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** All Rights Reserved
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**
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** This file is part of the KLH10 Distribution. Use, modification, and
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** re-distribution is permitted subject to the terms in the file
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** named "LICENSE", which contains the full text of the legal notices
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** and should always accompany this Distribution.
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**
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** This software is provided "AS IS" with NO WARRANTY OF ANY KIND.
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**
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** This notice (including the copyright and warranty disclaimer)
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** must be included in all copies or derivations of this software.
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*/
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/*
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* $Log: dvlhdh.h,v $
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* Revision 2.3 2001/11/10 21:28:59 klh
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* Final 2.0 distribution checkin
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*
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*/
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/*
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** Portions of this file were derived from AI:SYSTEM;LHDH DEFS5
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*/
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#ifndef DVLHDH_INCLUDED
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#define DVLHDH_INCLUDED 1
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#ifdef RCSID
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RCSID(dvlhdh_h,"$Id: dvlhdh.h,v 2.3 2001/11/10 21:28:59 klh Exp $")
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#endif
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/*
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; The ACC IMP interface on the KS implements two separate Unibus IO
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; devices, for input and output. Both of these devices transfer data in
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; 32-bit mode only over the Unibus via DMA. Because of the DMA data
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; transfer the interrupt structure is trivial, and uses NETCHN only.
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;
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; Apparently the reset bits in the two CSRs are wired together, so
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; resetting one side of the machine resets both. This action also drops
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; the HOST READY line to the IMP.
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;
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; You must set %LHSE whenever the HOST READY line is high, or the IMP
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; will be allowed to freely throw away data. This is true across IMP
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; message boundaries, and even if no input request is active.
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;
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*/
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extern struct device *dvlhdh_create(FILE *f, char *s);
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/* ACC LH-DH IMP Interface Bits. */
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#if 0 /* Default BR, VEC, ADDR settings for AI ITS */
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/* On Unibus #3: */
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#define UB_LHDH_BR 6 /* Interrupts occur on level 6 (non-std) */
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#define UB_LHDH_IVEC 0250 /* Input side interrupt vector (non-std) */
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#define UB_LHDH_OVEC 0254 /* Output side assumed to be LH_IVEC+4 */
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#define UB_LHDH 0767600 /* Base of LH/DH Unibus reg address space */
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#endif
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/* LHDH Registers - 16-bit word offsets from base address */
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#define LHR_ICS 0 /* Input Control and Status */
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#define LHR_IDB 1 /* Input Data Buffer */
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#define LHR_ICA 2 /* Input Current Word Address */
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#define LHR_IWC 3 /* Input Word Count */
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#define LHR_OCS 4 /* Output Control and Status */
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#define LHR_ODB 5 /* Output Data Buffer */
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#define LHR_OCA 6 /* Output Current Word Address */
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#define LHR_OWC 7 /* Output Word Count */
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#define LHR_N 8 /* # of registers */
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/* Bits in CSRs */
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/* Bits common to input and output */
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#define LH_ERR (1<<15) /* Error present */
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#define LH_NXM (1<<14) /* Non Existant Memory on DMA */
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#define LH_MRE (1<<9) /* Master Ready Error (ready bounce during xfr) */
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#define LH_RDY (1<<7) /* Device Ready (modifying LHDH regs allowed) */
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#define LH_IE (1<<6) /* Interrupt Enable */
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#define LH_A17 (1<<5) /* Address bit 17 for extended unibus xfrs */
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#define LH_A16 (1<<4) /* Address bit 16 for extended unibus xfrs */
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#define LH_RST (1<<1) /* Interface Reset */
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#define LH_GO 01 /* GO - Start DMA Transfer */
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/* Input side */
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#define LH_EOM (1<<13) /* End-of-Message received from IMP */
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#define LH_HR (1<<11) /* Host Ready (ACC's relay closed, debounced) */
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#define LH_INR (1<<10) /* IMP not ready */
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#define LH_IBF (1<<8) /* Input Buffer Full */
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#define LH_SE (1<<3) /* Store Enable (0 == flush data instead) */
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#define LH_HRC (1<<2) /* Host Ready Relay Control (1 to close relay) */
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/* Output side */
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#define LH_WC0 (1<<13) /* Output Word Count is zero */
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#define LH_OBE (1<<8) /* Output Buffer Empty */
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#define LH_BB (1<<3) /* Bus Back (loopback enable for testing) */
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#define LH_ELB (1<<2) /* Send EOM indication to IMP at end of xfr */
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/* (enable Last Bit Flag) */
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#endif /* ifndef DVLHDH_INCLUDED */
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