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249 lines
10 KiB
C
249 lines
10 KiB
C
/* DVTM03.H - RH11/TM03 Controller definitions
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*/
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/* $Id: dvtm03.h,v 2.3 2001/11/10 21:28:59 klh Exp $
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*/
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/* Copyright © 1993, 2001 Kenneth L. Harrenstien
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** All Rights Reserved
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**
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** This file is part of the KLH10 Distribution. Use, modification, and
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** re-distribution is permitted subject to the terms in the file
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** named "LICENSE", which contains the full text of the legal notices
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** and should always accompany this Distribution.
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**
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** This software is provided "AS IS" with NO WARRANTY OF ANY KIND.
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**
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** This notice (including the copyright and warranty disclaimer)
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** must be included in all copies or derivations of this software.
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*/
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/*
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* $Log: dvtm03.h,v $
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* Revision 2.3 2001/11/10 21:28:59 klh
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* Final 2.0 distribution checkin
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*
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*/
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/*
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** Portions of this file were derived from AI:SYSTEM;TM03S DEFS4
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*/
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#ifndef DVTM03_INCLUDED
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#define DVTM03_INCLUDED 1
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#ifdef RCSID
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RCSID(dvtm03_h,"$Id: dvtm03.h,v 2.3 2001/11/10 21:28:59 klh Exp $")
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#endif
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#include "dvrh20.h" /* Temp: get RHR ext reg defs */
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/* Initialization & sole entry point for TM02/3 driver
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*/
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#include "kn10dev.h"
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extern struct device *dvtm03_create(FILE *f, char *s);
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/* NOTE:
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Of the RH20 external registers, the following are the ones
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recognized (or not) by the TM02/TM03:
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*/
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#if 0
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RHR_CSR 0 /* R/W CS1 Control/command */
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RHR_STS 01 /* RO [I2] STS Status */
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RHR_ER1 02 /* R/W ER1 Error 1 */
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RHR_MNT 03 /* R/W [-2] MNT Maintenance */
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RHR_ATTN 04 /* R/W [I2] ATN? Attention Summary */
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RHR_BAFC 05 /* R/W [I2] ADR Block Address or Frame Count */
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RHR_DT 06 /* RO [I2] TYP Drive Type */
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RHR_LAH 07 /* RO LAH Current BlkAdr or R/W ChkChr */
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--*-- RHR_ER2 010 /* R/W ER2 Error 2 */
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RHR_OFTC 011 /* R/W OFS Offset or TapeControl */
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--NO-- RHR_DCY 012 /* R/W CYL Desired Cylinder Addr */
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--NO-- RHR_CCY 013 /* RO [-2] CCY Current Cylinder Addr */
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--NO-- RHR_SN 014 /* RO [-2] SER Serial Number */
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--NO-- RHR_ER3 015 /* R/W ER3 Error 3 */
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--NO-- RHR_EPOS 016 /* RO POS ECC Position */
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--NO-- RHR_EPAT 017 /* RO PAT ECC Pattern */
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#endif /* 0 */
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/*
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--*-- = The RH20 doc (p.2-20) says the TM02 uses reg 014 for SN, and 010 is
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unused.
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HOWEVER, the TM03 doc says reg 010 is SN, and 014 is unused; this also
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agrees with the TOPS-20 monitor code. So RHR_ER2 is used in the TM02
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emulation to refer to the transport serial number, rather than RHR_SN.
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(The doc agrees on all other regs.)
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*/
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#if 0 /* ITS AI RH11/TM03 defs */
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/* RH11/TM03 Interrupt vector: */
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#define UB_TM03_BR 6
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#define UB_TM03_VEC 0224 /*(224/4 = 45) Interrupts occur on level 6 */
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/* (high priority) on UBA #1. */
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#ifndef UB_TM03
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# define UB_TM03 0772440 /* Unibus address of first register */
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#endif
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#endif /* 0 */
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/* KLH: There is a source/binary inconsistency here.
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** TM03S.DEFS3 defines the base address as 772440 and that is what
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** the last AI ITS (1643) uses.
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** This is also what the DEC T20 code expects.
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** So that's what I'm using.
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** but TM03S.DEFS4 defines it as 772400 for some reason???
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**
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** Also, all of those files are wrong about claiming it is on UBA #1;
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** as far as I can tell it is always on UBA #3 (DEC T20 confirms this).
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*/
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/* RH11/TM03 Unibus register addresses: */
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/* Note: CS1 bits are shared by controller (RH) & drive (DR) */
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/* CS1: (RH/DR R/W) CTRL AND STATUS 1. (RH11:0, RH20:0) */
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# define TM_1SC (1<<15) /* RH: Special Condition */
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# define TM_1TE (1<<14) /* RH: Transfer Error */
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# define TM_1MP (1<<13) /* RH: Massbus Control Bus Parity Error */
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# define TM_1DA (1<<11) /* DR: Drive Available */
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# define TM_1A7 (1<<9) /* RH: UB Address Extension Bit 17 */
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# define TM_1A6 (1<<8) /* RH: UB Address Extension Bit 16 */
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# define TM_1RY (1<<7) /* RH: Ready */
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# define TM_1IE (1<<6) /* RH: Interrupt Enable */
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# define TM_1CM 077 /* DR: Bits 0-5 specify commands. */
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# define TM_1GO 01 /* DR: GO bit */
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/* Commands with bit 0 (GO) included: */
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# define TM_NOP 01 /* No Operation */
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# define TM_UNL 03 /* Unload */
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# define TM_REW 07 /* Rewind */
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# define TM_CLR 011 /* Formatter clear (reset errs etc) */
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# define TM_RIP 021 /* Read-In Preset (not used by T20) */
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# define TM_ER3 025 /* Erase three inch gap */
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# define TM_WTM 027 /* Write Tape Mark */
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# define TM_SPF 031 /* Space Forward */
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# define TM_SPR 033 /* Space Reverse */
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# define TM_WCF 051 /* Write Check FOrward */
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# define TM_WCR 057 /* Write Check Reverse */
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# define TM_WRT 061 /* Write Forward */
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# define TM_RDF 071 /* Read Forward */
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# define TM_RDR 077 /* Read Data Reverse */
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/* WC: (RH R/W) WORD COUNT. (RH11:1, RH20:-) */
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/* BA: (RH R/W) UNIBUS ADDRESS. (RH11:2, RH20:-) */
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/* FC: (DR R/W) TAPE FRAME COUNT (RH11:3, RH20:5) */
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/* CS2: (RH R/W) CTRL AND STATUS 2. (RH11:4, RH20:-) */
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# define TM_2DL (1<<15) /* Data Late */
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# define TM_2UP (1<<13) /* Unibus Parity Error */
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# define TM_2NF (1<<12) /* Non-existant Formatter */
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# define TM_2NM (1<<11) /* %TMBA is NXM during DMA */
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# define TM_2PE (1<<10) /* Program Error */
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# define TM_2MT (1<<9) /* Missed Transfer */
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# define TM_2MP (1<<8) /* Massbus Data Bus Parity Error */
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# define TM_2OR (1<<7) /* Output Ready (for Silo buffer diag.) */
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# define TM_2IR (1<<6) /* Input Ready (for Silo buffer diag.) */
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# define TM_2CC (1<<5) /* Controller Clear */
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# define TM_2PT (1<<4) /* Parity Test */
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# define TM_2AI (1<<3) /* Unibus Address Increment Inhibit */
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# define TM_2FS 07 /* Formatter select */
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/* FS: (DR RO) FORMATTER STATUS. (RH11:5, RH20:1) "STS" for RP */
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/* SS=SelectedSlave, S=AnySlave, M=TM03 fmtr */
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# define TM_SATA (1<<15) /* 100000 (M) Attention Active */
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# define TM_SERR (1<<14) /* 040000 (M) Error Summary */
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# define TM_SPIP (1<<13) /* 020000 (M/SS) Positioning in Progress */
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# define TM_SMOL (1<<12) /* 010000 (SS) Medium On-Line */
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# define TM_SWRL (1<<11) /* 04000 (SS) Write Locked */
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# define TM_SEOT (1<<10) /* 02000 (SS) End of Tape */
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/* (1<<9)*//* unused */
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# define TM_SDPR (1<<8) /* 0400 (M) Formatter Present (hardwired) */
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# define TM_SDRY (1<<7) /* 0200 (M) Drive/Formatter Ready */
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# define TM_SSSC (1<<6) /* 0100 (S) Any-Slave Status Change */
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# define TM_SPES (1<<5) /* 040 (SS) Phase Encoded (1600BPI) Mode */
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# define TM_SDWN (1<<4) /* 020 (SS) Settling Down */
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# define TM_SIDB (1<<3) /* 010 (M) PE Ident Burst Detected */
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# define TM_STM (1<<2) /* 04 (M) Tape Mark detected */
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# define TM_SBOT (1<<1) /* 02 (SS) Beginning of Tape */
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# define TM_SSLA (1<<0) /* 01 (SS) Slave Attention (came on-line
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** manually while selected;
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** cleared by init & drive clr)
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*/
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/* ERR: (DR RO) ERROR 1. (RH11:6, RH20:2) (ER1) */
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/* B=terminates in-progress data xfer, A=no */
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# define TM_ECDE (1<<15) /* (A) Correctable Data/CRC Error */
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# define TM_EUNS (1<<14) /* (B) Unsafe */
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# define TM_EOPI (1<<13) /* (B) Operation Incomplete */
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# define TM_EDTE (1<<12) /* (B) Controller Timing Error */
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# define TM_ENEF (1<<11) /* (B) Non Executable Function */
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# define TM_ECS (1<<10) /* (A) Correctable Skew/Illegal Tape Mark Error */
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# define TM_EFCE (1<<9) /* (A) Frame Count Error */
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# define TM_ENSG (1<<8) /* (A) Non-standard Gap */
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# define TM_EPEF (1<<7) /* (A) PE Format/LRC Error */
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# define TM_EINC (1<<6) /* (A) Incorrectable Data/Hard Error */
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# define TM_EMDP (1<<5) /* (A) Massbus Data Parity Error */
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# define TM_EFMT (1<<4) /* (B) Format Select Error */
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# define TM_EMCP (1<<3) /* (A) Massbus Control Parity Error */
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# define TM_ERMR (1<<2) /* (A) Register Modification Refused */
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# define TM_EILR (1<<1) /* (A) Illegal (non-ex) Register */
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# define TM_EILF (1<<0) /* (B) Illegal Function code */
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# define TM_EHD 044077 /* Hard errors - US,NEF,MD,FS,MC,RMR,ILR,ILF */
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/* ASN: (DR* R/W) ATTENTION SUMMARY. (RH11:7, RH20:4) (ATN) */
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/* Each bit 7-0 corresponds to a formatter asserting ATA. */
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/* Or is that "slave", because this is a drive register??? */
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/* Most likely formatter, akin to RP drives */
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/* CCR: (DR RO) CHECK CHARACTER REGISTER (RO) (RH11:010, RH20:7) (LAH) */
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# define TM_CDP (1<<8) /* Dead Track Parity/CRC Parity */
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# define TM_CEI 0177 /* Error Information */
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/* BUF: (DR R/W) DATA BUFFER. (RH11:011, RH20:-) */
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/* MNT: (DR R/W) MAINTENANCE. (RH11:012, RH20:3) */
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/* TYP: (DR RO) DRIVE TYPE. (RH11:013, RH20:6) */
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# define TM_DTNS (1<<15) /* 2.7 Not Sector addressed (always on) */
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# define TM_DTTA (1<<14) /* 2.6 Tape (always on) */
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# define TM_DTMH (1<<13) /* 2.5 Moving Head (always off) */
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# define TM_DT7C (1<<12) /* 2.4 7-track (always off) */
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# define TM_DTDC (1<<11) /* 2.3 Dual controller (always off) */
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# define TM_DTSS (1<<10) /* 2.2 Slave Selected (Slave Present) */
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/* (1<<9) */ /* 2.1 Unused */
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# define TM_DTDT 0777 /* 1.9 - 1.1 Selected Slave Type Number. */
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# define TM_DT00 010 /* 10= No slave */
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# define TM_DT16 011 /* 11= TE16 45 in/sec */
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# define TM_DT45 012 /* 12= TU45 75 in/sec */
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# define TM_DT77 014 /* 14= TU77 125 in/sec */
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# define TM_DTTM03 050 /* Bit set if TM03, else TM02 */
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# define TM_DTTM02 010 /* lowest & highest TM03 types are 050-057
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** " & " TM02 " " 010-017
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*/
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/* SER: (DR RO) SERIAL NUMBER. (RH11:014, RH20:010) */
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/* TC: (DR R/W) TAPE CONTROL REGISTER (RH11:015, RH20:011) (OFTC) */
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/* Selects & configures a slave transport */
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# define TM_TAC (1<<15) /* (RO) Acceleration (not up to speed) */
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# define TM_TFCS (1<<14) /* Frame Count Status */
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# define TM_TSA (1<<13) /* Slave Address (selected slave) Changed */
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# define TM_TEA (1<<12) /* Enable Abort on data transfer error */
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/* (ie ERR bits 15,7,6,5) */
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# define TM_TDS (07<<8) /* Density Select Field */
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# define TM_D02 00 /* 200 BPI (TM02 only) */
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# define TM_D05 01 /* 556 BPI (TM02 only) */
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# define TM_D08 02 /* 800 BPI NRZI (ITS thinks this is 3?) */
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# define TM_D16 04 /* 1600 BPI PE */
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# define TM_TFS (017<<4) /* Format Select */
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# define TM_FCD 00 /* PDP10 Core Dump */
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# define TM_FAA 02 /* ANSI-ASCII (TM02 only) */
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# define TM_FIC 03 /* Industry Compatible (32 bit mode) */
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# define TM_TEP (1<<3) /* Even Parity (for 800 NRZI only) */
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# define TM_TTS 07 /* Transport (Slave) Select */
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#endif /* ifndef DVTM03_INCLUDED */
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