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342 lines
10 KiB
Plaintext
342 lines
10 KiB
Plaintext
UNIVERSAL DEFS -- DX20 specific macro definitions for RDREG
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SUBTTL G.M. Uhler/GMU
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;This file contains the DX20 specific macro definitions for RDREG
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;to interpret the DX20 massbus registers. The format of the macros
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;is decribed when each macro is defined. The RDREG formats are
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;intended to be general enough so that the only work necessary to
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;make RDREG support a new device connected to an RH20 is to provide
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;a new universal file containing the macro definitions for that
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;device. This is the first such universal file.
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.DIRECTIVE .XTABM,FLBLST,.NOBIN
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SALL
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;Copyright (C) 1980,1981,1982,1983 by
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;Digital Equipment Corporation, Maynard, Mass.
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;
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;
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;This software is furnished under a license and may be used and copied
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;only in accordance with the terms of such license and with the
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;inclusion of the above copyright notice. This software or any other
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;copies thereof may not be provided or otherwise made available to any
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;other person. No title to and ownership of the software is hereby
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;transferred.
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;
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;The information in this software is subject to change without notice
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;and should not be construed as a commitment by Digital Equipment
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;Corporation.
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;
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;Digital assumes no responsibility for the use or reliability of its
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;software on equipment which is not supplied by Digital.
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DX2VER==1 ;Major version
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DX2MIN==0 ;Minor version
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DX2EDT==2 ;Edit number
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DX2WHO==0 ;Who edited
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SUBTTL Assembly parameters and drive type register definitions
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;The following definition controls whether RDREG will ask for the
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;DATAO/DATAI drive select field in addition to the RH20 device
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;code. For those devices that are always in massbus slot 0 (the
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;DX20 for example), set FTDSEL to a 0 and RDREG will always use
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;a drive select field of zero. For those devices that do require
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;a drive select code, set FTDSEL to -1 and RDREG will ask for and
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;use the drive select value specified by the user.
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FTDSEL==0 ;Don't need drive select for DX20s
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;The following macro defines the drive type register values for those
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;devices that we can interpret. The arguments to the DTRTYP macro
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;are as follows:
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;
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; 1 - Octal value of drive type (right 9 bits)
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; 2 - Corresponding mnemonic for this drive type (this mnemonic
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; is used in the second level macro definitions below)
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DEFINE DRVTYP,<
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DTRTYP 60,TX02 ;;Tape style DX20s have a DT of 60
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DTRTYP 61,RP20 ;;Disk style DX20s have a DT of 61
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>
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SUBTTL First level massbus register definitions
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;The following macro defines the registers that we want to read and
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;interpret in the device. The arguments to the XX macro are as
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;follows:
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;
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; 1 - Massbus register number (register select field)
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; 2 - Mnemonic for the register
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;
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;Note that the CONI definition MUST be first. RDREG depends on this
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;and will work incorrectly if it is not.
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DEFINE REGS,<
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XLIST
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XX 0,CONI ;;CONI - Must be first
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XX 0,CR ;;Control register
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XX 1,SR ;;Status register
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XX 2,ER ;;Error register
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XX 3,MR ;;Maintenance register
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XX 4,AS ;;Attention summary register
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XX 6,DT ;;Drive type register
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XX 20,GPR0 ;;General purpose register 0
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XX 21,GPR1 ;;General purpose register 1
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XX 22,GPR2 ;;General purpose register 2
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XX 23,GPR3 ;;General purpose register 3
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XX 24,GPR4 ;;General purpose register 4
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XX 25,GPR5 ;;General purpose register 5
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XX 26,GPR6 ;;General purpose register 6
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XX 27,GPR7 ;;General purpose register 7
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XX 30,DIA0 ;;Diagnostic register 0
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XX 31,DIA1 ;;Diagnostic register 1
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XX 32,DIA2 ;;Diagnostic register 2
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XX 33,DIA3 ;;Diagnostic register 3
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XX 34,DIA4 ;;Diagnostic register 4
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XX 35,DIA5 ;;Diagnostic register 5
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XX 36,DIA6 ;;Diagnostic register 6
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XX 37,DIA7 ;;Diagnostic register 7
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XX 70,SBAR ;;Secondary block address register
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XX 71,STCR ;;Secondary transfer control register
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XX 72,PBAR ;;Primary block address register
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XX 73,PTCR ;;Primary transfer control register
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XX 74,IVIR ;;Interrupt vector index register
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LIST
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>
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SUBTTL Second level massbus register definitions
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;The following macros define the bits and fields in each of the
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;massbus registers that we want to interpret. For each massbus
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;register mnemonic that we defined in the first level macro definition
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;above, we define a macro with the same name here that gives the
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;bit and field definitions for that register. The arguments to
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;the FIELDS macro are as follows:
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;
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; 1 - The bit mask of the bit or field in the 36 bit word
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; 2 - The text associated with the bit or field
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; 3 - One of BIT, VAL, or NVAL to indicate that this entity is a
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; bit, a field containing a positive number, or a field containing
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; a negative number, repectively. RDREG only interprets BIT values
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; if the bit is on. VAL values are always printed as a field. NVAL
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; values are first negated and then always printed as a field.
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; 4 - Either ALL or one of the drive type mnemonics defined by
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; the DRVTYP macro above. ALL values are interpreted for
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; all of the legal drive types. Values that are given with
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; a specific drive type mnemonic are only interpreted if the
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; device is of that drive type.
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DEFINE CR,<
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FIELDS 1B35,<Go>,BIT,ALL
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FIELDS 77B35,<Fnc>,VAL,ALL
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>
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DEFINE SR,<
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FIELDS 1B20,<Attention>,BIT,ALL
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FIELDS 1B21,<Composite error>,BIT,ALL
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FIELDS 1B22,<Link present>,BIT,ALL
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FIELDS 1B23,<MP run>,BIT,ALL
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>
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DEFINE ER,<
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FIELDS 1B35,<ILF>,BIT,ALL
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FIELDS 1B34,<ILR>,BIT,ALL
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FIELDS 1B33,<RMR>,BIT,ALL
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FIELDS 1B32,<CB par err>,BIT,ALL
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FIELDS 1B31,<DB par err>,BIT,ALL
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FIELDS 1B30,<UB par err>,BIT,ALL
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FIELDS 1B29,<MP stop>,BIT,ALL
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FIELDS 1B28,<MP err>,BIT,ALL
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FIELDS 17B27,<Error class>,VAL,ALL
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FIELDS 17B23,<Sub-class>,VAL,ALL
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>
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DEFINE MR,<
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FIELDS 1B31,<Single cycle>,BIT,ALL
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FIELDS 1B32,<Even parity>,BIT,ALL
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FIELDS 1B33,<MP start>,BIT,ALL
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FIELDS 1B34,<DX reset>,BIT,ALL
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>
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DEFINE AS,<
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FIELDS 377B35,<Attentions>,VAL,ALL
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>
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DEFINE DT,<
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FIELDS 377B35,<Drive type>,VAL,ALL
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>
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DEFINE GPR0,<
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FIELDS 1B21,<Status modifier>,BIT,ALL
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FIELDS 1B22,<Control unit end>,BIT,ALL
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FIELDS 1B23,<Busy>,BIT,ALL
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FIELDS 1B24,<Channel end>,BIT,ALL
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FIELDS 1B25,<Device end>,BIT,ALL
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FIELDS 1B26,<Unit check>,BIT,ALL
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FIELDS 1B27,<Unit exception>,BIT,ALL
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FIELDS 1B28,<Status update>,BIT,ALL
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FIELDS 177B35,<Status index>,VAL,ALL
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>
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DEFINE GPR1,<
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FIELDS 377B35,<Drive>,VAL,RP20
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FIELDS 1B21,<Status modifier>,BIT,RP20
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FIELDS 1B22,<Control unit end>,BIT,RP20
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FIELDS 1B23,<Busy>,BIT,RP20
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FIELDS 1B24,<Channel end>,BIT,RP20
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FIELDS 1B25,<Device end>,BIT,RP20
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FIELDS 1B26,<Unit check>,BIT,RP20
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FIELDS 1B27,<Unit exception>,BIT,RP20
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FIELDS 377B35,<Drive number>,VAL,TX02
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FIELDS 17B27,<Drive mode>,VAL,TX02
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FIELDS 17B23,<Data mode>,VAL,TX02
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>
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DEFINE GPR2,<
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FIELDS 1B21,<Ignore length>,BIT,RP20
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FIELDS 1B22,<Diagnostic mode>,BIT,RP20
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FIELDS 1B23,<Command retry>,BIT,RP20
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FIELDS 1B25,<Disable sense>,BIT,RP20
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FIELDS 1B26,<Force sense>,BIT,RP20
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FIELDS 1B27,<Whole track>,BIT,RP20
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FIELDS 377B35,<Argument>,VAL,RP20
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FIELDS 377B35,<Size of EST>,VAL,TX02
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>
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DEFINE GPR3,<
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FIELDS 377B35,<Drive number>,VAL,RP20
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FIELDS 377B35,<TIE byte>,VAL,TX02
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FIELDS 1B25,<Disable sense>,BIT,TX02
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FIELDS 1B26,<Force sense>,BIT,TX02
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FIELDS 1B27,<Enable TIE recovery>,BIT,TX02
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>
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DEFINE GPR4,<
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FIELDS 177777B35,<Cylinder>,VAL,RP20
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FIELDS 377B35,<Drive>,VAL,TX02
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FIELDS 1B21,<Status modifier>,BIT,TX02
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FIELDS 1B22,<Control unit end>,BIT,TX02
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FIELDS 1B23,<Busy>,BIT,TX02
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FIELDS 1B24,<Channel end>,BIT,TX02
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FIELDS 1B25,<Device end>,BIT,TX02
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FIELDS 1B26,<Unit check>,BIT,TX02
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FIELDS 1B27,<Unit exception>,BIT,TX02
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>
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DEFINE GPR5,<
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FIELDS 377B27,<Head>,VAL,RP20
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FIELDS 377B35,<Record>,VAL,RP20
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FIELDS 177777B35,<Byte count>,NVAL,TX02
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>
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DEFINE GPR6,<
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FIELDS 177777B35,<Extended status 0>,VAL,ALL
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>
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DEFINE GPR7,<
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FIELDS 177777B35,<Extended status 1>,VAL,ALL
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>
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DEFINE DIA0,<
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FIELDS 177777B35,<Microcontroller instruction register>,VAL,ALL
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>
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DEFINE DIA1,<
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FIELDS 1B20,<IR enable>,BIT,ALL
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FIELDS 1B21,<Microstore enable>,BIT,ALL
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FIELDS 1B22,<PC enable>,BIT,ALL
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FIELDS 1B23,<PC auto increment>,BIT,ALL
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FIELDS 7777B35,<PC>,VAL,ALL
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>
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DEFINE DIA2,<
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FIELDS 377B27,<ALU B input>,VAL,ALL
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FIELDS 377B35,<ALU A input>,VAL,ALL
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>
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DEFINE DIA3,<
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FIELDS 377B27,<Source ROM outputs>,VAL,ALL
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FIELDS 377B35,<Destination ROM outputs>,VAL,ALL
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>
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DEFINE DIA4,<
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FIELDS 377B27,<FROM7-FROM0>,VAL,ALL
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FIELDS 1B28,<IR par>,BIT,ALL
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FIELDS 1B29,<BALU par gen>,BIT,ALL
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FIELDS 1B30,<AC par>,BIT,ALL
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FIELDS 1B31,<SMUX par>,BIT,ALL
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FIELDS 17B35,<UBUS int>,VAL,ALL
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>
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DEFINE DIA5,<
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FIELDS 377B27,<BALU7-BALU0>,VAL,ALL
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FIELDS 377B35,<MEM7-MEM0>,VAL,ALL
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>
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DEFINE DIA6,<
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FIELDS 377B27,<IMUX7-IMUX0>,VAL,ALL
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FIELDS 377B35,<BR7-BR0>,VAL,ALL
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>
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DEFINE DIA7,<
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FIELDS 1B20,<C>,BIT,ALL
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FIELDS 1B21,<Z>,BIT,ALL
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FIELDS 1B22,<IR par err>,BIT,ALL
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FIELDS 1B23,<St O/U flw>,BIT,ALL
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FIELDS 1B24,<ALU A par err>,BIT,ALL
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FIELDS 1B25,<ALU B par err>,BIT,ALL
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FIELDS 1777B35,<MA9-MA0>,VAL,ALL
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>
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DEFINE SBAR,<
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FIELDS 377B27,<Head>,VAL,RP20
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FIELDS 377B35,<Record>,VAL,RP20
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FIELDS 177777B35,<Byte count>,NVAL,TX02
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>
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DEFINE STCR,<
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FIELDS 1777B29,<Block count>,NVAL,ALL
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FIELDS 77B35,<Command>,VAL,ALL
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>
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DEFINE PBAR,<
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FIELDS 377B27,<Head>,VAL,RP20
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FIELDS 377B35,<Record>,VAL,RP20
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FIELDS 177777B35,<Byte count>,NVAL,TX02
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>
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DEFINE PTCR,<
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FIELDS 1777B29,<Block count>,NVAL,ALL
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FIELDS 77B35,<Command>,VAL,ALL
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>
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DEFINE IVIR,<
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FIELDS 777B35,<EPT relative interrupt offset>,VAL,ALL
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>
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DEFINE CONI,<
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FIELDS 1B18,<DB par err>,BIT,ALL
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FIELDS 1B19,<Drv exc>,BIT,ALL
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FIELDS 1B20,<Long WC>,BIT,ALL
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FIELDS 1B21,<Short WC>,BIT,ALL
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FIELDS 1B22,<Chan err>,BIT,ALL
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FIELDS 1B23,<Drive resp err>,BIT,ALL
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FIELDS 1B24,<Reg acc err>,BIT,ALL
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FIELDS 1B25,<Chan rdy>,BIT,ALL
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FIELDS 1B26,<Overrun>,BIT,ALL
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FIELDS 1B27,<MBE>,BIT,ALL
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FIELDS 1B28,<Attn>,BIT,ALL
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FIELDS 1B29,<STCR full>,BIT,ALL
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FIELDS 1B30,<AIE>,BIT,ALL
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FIELDS 1B31,<PTCR full>,BIT,ALL
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FIELDS 1B32,<Done>,BIT,ALL
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FIELDS 7B35,<PI>,VAL,ALL
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>
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END
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