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.ps,70;.ap;.title TGHA Version 4 Documentation
.style headers 6,0,0 !causes all headers to be taken as is, no capitalizing
.set paragraph 0,1,2 !causes no indenting on first line in paragraph
.display number RL !number title and toc with lower case roman numerals
.c;TGHA - THE GREAT HEURISTIC ALGORITHM
.s2
.c;COPYRIGHT (C) 1979, 1981, 1984, 1986
.s
.c;DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS.
THIS SOFTWARE IS FURNISHED UNDER A LICENSE FOR USE ONLY ON A SINGLE COMPUTER
SYSTEM AND MAY BE COPIED ONLY WITH THE INCLUSION OF THE ABOVE COPYRIGHT NOTICE.
THIS SOFTWARE, OR ANY OTHER COPIES THEREOF, MAY NOT BE PROVIDED OR OTHERWISE
MADE AVAILABLE TO ANY OTHER PERSON EXCEPT FOR USE ON SUCH SYSTEM AND TO ONE WHO
AGREES TO THESE LICENSE TERMS. TITLE TO AND OWNERSHIP OF THE SOFTWARE SHALL AT
ALL TIMES REMAIN IN DIGITAL EQUIPMENT CORPORATION.
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE AND SHOULD
NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL EQUIPMENT CORPORATION.
DIGITAL EQUIPMENT CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OR
RELIABILITY OF ITS SOFTWARE IN EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL
EQUIPMENT CORPORATION.
.page
.subtitle Table of Contents
.autosubtitle !causes header level 1's to be used as subtitles
.center;Table of Contents
.right;Page
.right;----
.!the next cmd inserts the table of contents produced by TOC.EXE
.require "TGHA.RNT" !name of file for runoff to process
.display number D !number pages with decimal numbers
.ps,78;.rm78;.number page 1;.lm0
.page;.hl1 Abstract
TGHA is the MOS memory analyzer program that is run by the monitor whenever a
correctable error occurs in an MF20 or MG20 memory array. It has the
responsibility for keeping the MOS memory in a viable condition using the
MF20/MG20 maintenance features.
When run by the monitor, TGHA obtains data about the MOS memory error from the
monitor. TGHA can also be run by a user with at least maintenance privileges.
In this mode, TGHA is used to create ASCII files (bit to text) from TGHA's data
base. HISTORY.LST contains information about the hardware configuration, the
state of the controller corrective logic, and a list of logged errors.
TRACE.LST contains entries tracking the corrective action taken by TGHA. TGHA
version 4 can be run with either or both MF20 (16K) and MG20 (64K) array
modules in the memory system. However, both types cannot be installed within
the same controller.
.ls
.le;TGHA sources will not be available to customers.
.le;This document applies to both TOPS-10 and TOPS-20 unless otherwise
specified.
.le;If the memory boot portion of KLI does not configure a block of
MOS memory due to multiple bit errors, TGHA will indicate what memory and how
much memory was not configured. The message will appear on the CTY, in the
TGHA trace file, and in ERROR.SYS.
.le;If the memory boot portion of KLI finds a parity error, KLI will use the
spare bit and configure the block. TGHA, upon finding that a spare bit was set
into use by KLI, will never use that spare bit for any other purpose. Upon
finding such a condition, tgha will output an appropriate message on the CTY,
in the trace file, and in ERROR.SYS.
.le;If a parity error ever occurs during swapping in of a spare bit, the spare
bit will then be flagged as if KLI had set the spare bit into use (see previous
paragraph). Similar CTY, trace file and SPEAR entries will be made.
.els
.page;.hl1 Installation Instructions
TGHA data and trace file names are TGHA.DAT and TGHA.TRA respectively. The old
files TGHAV2.* or TGHAV3.* should be renamed to preserve the database.
.hl2 Installation On TOPS-10
For TGHA to run properly on TOPS-10, the following lines must be entered in
OPR.ATO after DAEMON is started:
.ls
.le;:SLOG
.le;:DEF TGHA=
.le;R TGHA
.els
Since TGHA makes entries in ERROR.SYS via DAEMON, DAEMON must be running before
TGHA is started. After TGHA starts, it detaches itself. TGHA.EXE must reside
in the SYS: [1,4] area.
.hl2 Installation On TOPS-20
TGHA.EXE must reside in the SYSTEM: area (usually including PS:<SYSTEM>). The
TOPS-20 monitor starts TGHA automatically at system startup as a fork (process)
of job 0.
If the monitor cannot find TGHA at system startup, TGHA will not be run by the
monitor. If TGHA is not running, the monitor will throw away the error data
that might have been collected by TGHA, and the system will continue to run.
.page;.hl1 An Overview Of TGHA
.hl2 Running TGHA
TGHA is run at system startup by the monitor (TOPS-20) or by OPSER (TOPS-10).
This TGHA is informed by the monitor when a MOS memory error occurs.
Timesharing is stopped and TGHA performs bit substitution as required. After
TGHA runs, timesharing is continued. This is called the "system" TGHA.
Field Service can run TGHA to obtain a listing of TGHA's database. This is
called "user" TGHA. The same TGHA.EXE is used for both "system" and "user"
TGHA.
.hl3 Initial System Start Up
At initial system start up, the TOPS-20 monitor runs the system TGHA under job
0, or TOPS-10 OPSER runs the system TGHA. TGHA will first enable single bit
error reporting throughout MOS memory. TGHA will then either build the history
file if it does not already exist, or verify that it knows about all of the
MF20/MG20 hardware that is on line. If the history file exists and new MOS
memory hardware appears, TGHA will add this new hardware to its history file.
Once the initial start up initialization is complete, TGHA then looks for any
MOS memory errors that have occurred since the system was booted.
.hl3 Dumping TGHA Database
TGHA is run by field service personnel to list TGHA's database. In this mode,
TGHA knows that it is not the "system" TGHA, and it does not get called by the
monitor to look for MOS memory errors.
.nt
In order to run TGHA manually, the user must have the maintenance capabilities
enabled (TOPS-20) or be running as [1,2] (TOPS-10). This is required because
TGHA looks at the MOS memory to determine the current configuration.
.en
Under TOPS-20 enter "SYSTEM:TGHA" to the monitor prompt. Under TOPS-10 enter
"R TGHA". TGHA will respond with a "TGHA>" prompt.
The HELP command ("HELP"<cr>) produces the following text:
.tp 16;.lm8;.lt
Command Purpose
EXIT Exit from TGHA.
HELP Type this text.
HISTORY Dump history file database.
SCRAP Give instructions on how to scrap TGHA databases.
TRACE Dump trace file database.
.el;.lm0
The history and trace dump files will be created in the current path (TOPS-10)
or connected directory (TOPS-20). The trace listing will be called TRACE.LST.
The history listing will be called HISTORY.LST (TOPS-20) or HISTORY.LST
(TOPS-10). These files are listable versions of the TGHA database and the
trace file.
Although TGHA.TRA may look readable, remember that it is the equivalent of a
ring buffer. The oldest data is over written when the file becomes large
enough. This prevents the trace file from becoming uselessly large. TRACE.LST
is in chronological order, the oldest entries first.
When TGHA is run in "user" mode, the only functions available are the dumping
of the database files. No changes in the memory configuration or the use of
the spare bits can be done by TGHA in "user" mode.
.hl2 TGHA Files
TGHA files for both TOPS-10 and TOPS-20 include the following:
.lt
File Purpose Creation Mechanism
---- ------- -------------------
TGHA.EXE TGHA executable file Monitor tape
TGHA.HLP TGHA help file Monitor tape
TGHA.DOC TGHA documentation Monitor tape
TGHA.DAT TGHA history file TGHA.EXE when first run
TGHA.TRA TGHA trace file TGHA.EXE when first run
TGHA.BAD Bad copy of TGHA.DAT TGHA.EXE when the database
gets confused
.el
TGHA.DAT will not grow as errors are incurred. TGHA will purge old data as its
databases fill up. The only way that TGHA.DAT will grow is if new hardware is
brought on line (a storage module is swapped or a new controller is added to
the system). TGHA requires all of the history data that it has collected to
remain intact so that it can make correct decisions about corrective action.
.nt
TGHA.DAT should only be deleted under very rare circumstances. It contains
important history information.
.en
.hl2 MOS Memory Errors
When a MOS memory correctable error occurs, the monitor wakes up the system
TGHA. TGHA then gets the data for the error from the monitor. This is called
a chronological error. They are stored in order of occurrence in the history
database. There is a separate chronological error list for each module.
Only when the chronological error list is full does TGHA go off and attempt to
resolve a known error from this list.
.hl3 Known Error Determination
Known error determination is done statistically using the CHI SQUARED goodness
of fit formula. Starting with the first chronological error in the storage
module, the formula is used to test the distribution of the other errors in the
chronological error list for each type of possible hardware error.
For instance, the first hardware failure considered is a "full MUX failure". A
table is built by scanning all of the other errors in the storage module and
tallying only those errors that are covered by the specific type of hardware
error being considered, in this case, a full MUX failure. The table for a full
MUX failure is distributed by block and subblock number. This translates into
a distribution by chip since there are 16 chips involved in a full MUX failure.
If the the distribution is even enough, the Chi Squared goodness of fit test
will succeed, and a known error is declared.
This continues until either the hardware error type is found or all of the
error types have been tried.
The last type of hardware error considered is a cell error. If there are more
than a minimum number of errors of the same cell (typically 5), then a cell
error is declared.
After an error type has been found, all of the chronological errors that are
influenced by the known error type are eliminated from the chronological error
list. This procedure continues for each remaining error in the chronological
error list.
After the known error routine has been run, the corrective action routine is
called.
.hl3 Corrective Action
The goal of the corrective action routines is to determine the optimum
corrective action given the current known errors. This is done on a per group
basis.
First, the worst error in the group is found. This is the error that affect
the most amount of memory. Once the worst error has been found, the applicable
spare bits are used to cover it. If there is more than one known error in the
group, a scan is done to set all ICE (Inhibit Correctable Error reporting) bits
within the scope of the worst error. This procedure is repeated until all
known errors for the group have been analyzed.
There is one exception to the previous procedure. If the memory boot portion
of KLI (Double Bit Error scan) has used a spare bit to handle a double bit
error, TGHA will not change the use of that specific spare bit. If TGHA were
to attempt to use such a spare bit for another purpose, the possibility of
parity errors resulting would be too great to risk.
If a parity error occurs during the setting of a spare bit, TGHA will set the
same considerations on that spare bit as if KLI had set it.
On the occurrence of the previous conditions, appropriate ERROR.SYS entries
will be made.
.hl3 Parity Errors
Parity errors are handled like parity errors always have been. If the monitor
successfully continues after the parity error, it will attempt to take the page
of memory with the parity error offline.
The monitor then runs TGHA if the page was successfully removed. The monitor
may not be able to take the page with the parity error off line. This would be
the case if the page was part of the resident monitor. TGHA will enter parity
errors in its trace file, not the history file database.
TGHA will make an entry in the trace file and ERROR.SYS indicating physical
address, block of memory, and the orientation of the 4 storage modules
containing the error.
.page;.hl1 History File (TGHA.DAT)
The history file is made up of 3 different types of pages. They are the
directory page, group pages, and storage module pages. The sequence starts out
with one directory page. This page contains configuration information about
all of the MOS memory on the system. The next page is a group page followed by
four storage module pages. The pattern of a group and four succeeding storage
module pages is repeated for each group currently on line. A storage module
page for each storage module that has gone away is then listed.
.hl2 Directory Page
The first page of the history file contains the current configuration of the
memory, including the location of each storage module by serial number. Note
that the serial number in the history file is in the same format as the sticker
on the storage module itself.
The location of the storage modules in memory is documented in the history list
file for archival and Field Service reasons. The errors logged in the history
file are dependent upon the orientation of the storage modules. If they are
moved, the error corrections in the memory may have different characteristics.
If Field Service wishes to replace a storage module, the exact location by
serial number is therefore documented.
.hl2 Group Page
The group page contains information specific to the configuration of the group.
The last time the group was used in this configuration may be useful if groups
of storage modules are removed and put back into the memory later. The time of
the last change to the group is useful when determining where the most recent
errors have occurred in memory.
Let it be noted here that the chronological list of errors in the history file
and the entries in the trace file are tagged with the date and time. This is
required when correlating corrective action with memory modules.
.hl3 Spare Bit Substitution RAM Fields
The group page also contains a map of the current state of the Spare Bit
Substitution RAM. The Spare Bit Substitution RAM is used to direct bit
replacement with the spare bit RAMs.
The value of the Spare Bit Substitution RAM contains 4 fields. These are shown
below.
.tp 21;.b;.lm 12;.i-12
Field Bits##Meaning
.b;.i-12
#######400##Either KLI used this spare bit to cover a parity
error or a parity occurred during a bit swap. The 400 bit is in the TGHA
database only, and is not used in the actual bitswap process.
.b;.i-12
#######374##The octal value of the bit being replaced. To find the value of
the bit being replaced, this field must be shifted to the right by 2 places,
and the decimal equivalent value of the octal digits is the word bit being
replaced.
.b;.i-12
#########2##Set means correctable error reporting is disabled. Clear means
correctable error reporting is enabled. This bit is referred to as the "ICE"
(Ignore Correctable Errors) bit.
.b;.i-12
#########1##Bit Substitution RAM value parity bit.
.lm0;.b
.hl3 Bit Substitution RAM Examples
Three possible values for the Bit Substitution RAM are shown below.
.tp 20;.b;.lm6;.i-6
Value##Meaning
.b;.i-6
256#-#The spare bit is not in use. The value of the bit to be swapped points
to the spare bit. The spare bit is in decimal bit position 43.
.i-6
####-#Correctable error reporting is disabled for this Bit Substitution RAM
address.
.b;.i-6
255#-#Spare bit is not in use (same as previous example).
.i-6
####-#Correctable error reporting is enabled.
.b;.i-6
652#-#The 400 bit on indicates that this use of this spare bit prevents a
parity error from occurring. TGHA will not change this value. The Bit
substitution RAM data requires odd parity.
.i-6
####-#Bit 42 of the MF20 data path is being swapped (the parity bit).
.lm0;.b
The actual spare bit address in SBDIAG function 7 is 7 bits wide. The address
in the group page accounts for only the lower 5 bits. The high order 2 bits is
the group number within the controller. The group field is determined from the
group position in the memory controller, and not the group database. Therefore
the group portion of the field is not, and indeed cannot, be kept within the
Spare Bit RAM address table. This portion of the SBDIAG function is filled in
at execution time.
.hl2 Storage Module Page
A Storage Module Page contains information relating specifically to the storage
module. The serial number appears in the same format as the sticker on the
module itself. This is critical for field returns, which require that this
page be attached to the storage module if it is to be returned to the factory
for repairs. The last time the module was used can be useful in tracking
module swaps made in the MOS memory subsystem and field returns.
The known error list contains the error information related to the known errors
resolved from chronological errors by TGHA. Most of the information in each
entry is used by TGHA to determine overlap of errors. This overlap is
important when considering the optimum use of the spare bits.
The storage module chip location is included to facilitate module repair.
The time of resolution of the error may give an indication of the rate of
deterioration of failure of the module.
The current chronological error list for the storage module will include any
errors that have not been resolved into known errors yet. There may be
included in this list any soft errors that have occurred. These soft errors
will be removed from the list sometime after a minimum default (about 1 week).
.hl2 Unused Storage Module Page
Any storage modules that are in the TGHA history file, yet are not presently in
use, follow the other pages in the database. The inclusion of the unused
storage modules in the history file is required for the case when field service
has replaced a storage module, reloaded the system, and wants a copy of the
history file for that storage module so that the error data can be included
with the module when the module is returned for repairs.
Since these storage modules are no longer part of any configured group, no
group information is given.
.hl2 HISTORY.LST Sample
The HISTORY command causes the history database to be dumped to the file
HISTORY.LST. The following examples are from a HISTORY.LST file.
.hl3 Sample Directory Page
The directory page is always the first page of a HISTORY.LST file. It shows
all useful information from the directory page of the TGHA.DAT file. The
memory configuration shown includes 768Kw MF20 and 2048Kw MG20 memory.
.tp14;.lt
TGHA History file for System 2866 15-Nov-86 10:39:52 Page 1
History file data base version 2
Controller Group Number Storage module serial numbers by field
No. & Type 0 1 2 3
10 MF20 0 1480561 3260135 1480573 0430757
1 3290431 3280343 3280307 3290397
2 3260153 0070679 3300561 3300504
11 MG20 0 4080029 4080043 4080040 5170481
1 4080028 4370970 4080074 4461311
2
.el
.hl3 Sample Group Data Page
The Group Data Page is output for each group of memory in each controller
configured in the system. It is followed by Storage Module Data for each
storage module in the group.
.tp13;.lt
Group Data for System 2866 15-Nov-86 10:39:52 Page 2
Controller: 10 Group: 0
The last time this group was used was 14-Nov-86 11:38:36
The last time a change was made to this group was never
Bit Substitution Map:
000/ 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255
020/ 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255
.el
.hl3 Sample Storage Module Data Page
The Storage Module Data is output for each storage module listed in the TGHA
database. Each storage module's data is output with the storage modules
configured in each group. The data for storage modules that are not being used
is output after all active storage modules have been listed.
.tp22;.lt
Storage Module Data for System 2871 15-Nov-86 10:50:32 Page 20
Controller: 11 Group: 1 Field: 2
Storage module serial number 5220677, RAM size 64K
The last time this storage module was used was 15-Nov-86 10:50:30
No known errors determined yet for this module
Chronological errors:
Block Subblock BIFN Row Column E # Time
1 0 1 124 300 37 10-Oct-86 12:05:32
1 3 3 104 300 62 10-Oct-86 12:05:32
2 0 2 217 10 55 20-Oct-86 06:53:11
2 0 2 217 10 55 20-Oct-86 06:56:11
2 0 2 217 10 55 20-Oct-86 07:01:11
2 0 2 217 10 55 20-Oct-86 07:06:11
2 0 2 217 10 55 20-Oct-86 07:10:57
2 0 2 217 10 55 20-Oct-86 07:13:40
2 0 2 247 12 55 20-Oct-86 18:35:43
.el
.page;.hl1 Trace File (TGHA.TRA)
The trace file contains dated entries indicating what corrective action has
been taken by TGHA. If the TGHA software runs into confusion or a database
gets full, entries into the trace file will also reflect the difficulty.
Serious MOS memory hardware errors will also be entered in the trace file.
.hl2 Spare Bit Swap
The following is an example of the trace file for a spare bit swap for bit 42.
When the swap completes, the another message is put in the trace file.
.lt
********
11-Oct-86 15:50:12
Bit Substitution: Controller 10, Group 0, Block 1, Word (bits 33-35) 3
The Bit Sub RAM data is going to be changed to 124 (octal), bit 42 (decimal).
11-Oct-86 15:50:12
Bit Substitution: Completed normally
********
.el
.hl2 Parity Error (Double Bit Error)
The following is an example of a parity error. This message is caused by a
double bit error in MF20 memory. TGHA just dumps the information to the CTY
and to the trace file. No further action is taken by TGHA.
.tp6;.lt
********
11-Oct-82 19:20:02
Parity error at address 1001475, block 0
Storage module serial numbers by field:
0 = 7460209 1 = 7460108 2 = 7460117 3 = 7460200
********
.el
The MOS memory diagnostics should be run and the offending storage module
replaced.
.hl2 Serious Hardware Failure
The following is an example of a serious MOS memory failure. This error
message is seen after a full Mux failure. Although the error has been
corrected using the spare bits, the probability of a parity error due to
further hardware degradation has risen to an uncomfortable state.
.tp7;.lt
********
19-Jun-86 20:20:02
TGHA has temporarily corrected a serious MOS memory failure.
Call Field Service to report this Full Mux failure condition.
********
.el
This message also appears on the CTY. The MOS memory diagnostics should be run
and the offending storage module replaced.
.hl2 Use Of Spare Bit By KLI
The following is an example of KLI using the spare bit in its DBE (Double Bit
Error) scan when it configures memory. When TGHA detects this condition, it
will display this information since this prevents TGHA from using the spare bit
if another problem develops with the same word in memory.
.tp8;.lt
********
24-Jul-86 07:11:07
The memory boot in KLI has used the spare bit to prevent a parity error.
This condition should be corrected as soon as possible.
Controller Group Block Word (bits 33-35)
10 0 1 5
********
.el
This message also appears on the CTY. The MOS memory diagnostics should be run
and the offending storage module replaced.
.hl2 KLI Detected Bad Block
If KLI has not configured a block of MOS memory because of an error that cannot
be repaired using the spare bit, the block will not be configured.
.tp10;.lt
********
13-Jun-86 10:33:00
The following blocks of MOS memory are marked as bad and are not on line:
Controller Group Block
10 1 3
10 2 1
This consists of 128K of memory that is off line.
Call Field Service to report this condition.
********
.el
This message also appears on the CTY. The MOS memory diagnostics should be run
and the offending storage module replaced.
.hl2 Missing Database
If TGHA finds that there is no database and that a MOS memory controller was
last initialized by TGHA, TGHA will output the following message:
.tp8;.lt
********
19-Jul-86 12:35:21
MF20 Controller 10 was last initialized by TGHA, but TGHA has lost its
database. Run TGHA and use the SCRAP command to see recovery instructions.
********
.el
.hl3 Missing or Damaged Database Implications
In this situation, TGHA cannot determine whether any spare bits in use were set
by the memory boot in KLI or TGHA. This information was stored in the TGHA
database, which went away for some reason. TGHA must therefore assume that all
spare bits in use were set by KLI to prevent parity errors.
This means that these spare bits will not be available for correction of
further hardware failures in the memory. This is not an ideal situation for
TGHA to be in, and will not rectify its self automatically. Although this
situation is not immediately critical, it degrades the performance of TGHA.
The recovery procedure can be deferred to a convenient time, like a Field
Service PM or a scheduled system reload.
.hl3 Database Recovery Procedure
.nt
This is the ONLY time that the TGHA database file (TGHA.DAT) should be
explicitly deleted. Although this destroys all of the known error history,
the known errors will be resolved by TGHA in the same manner as before. The
probability of this situation arising is very low. This drastic action is
explained only to cover this situation.
.en
.tp10;.ls
.le;Copy any existing PS:<SYSTEM>TGHA.DAT to PS:<SYSTEM>TGHA.BAD.
.le;Delete PS:<SYSTEM>TGHA.DAT.
.le;Bring the system down (^ECEASE, Parser's SHUTDOWN command).
.le;Run KLI.
.le;Enter KLI's DIALOG mode.
.le;Answer FORCE in response to the "reconfigure memory" question.
.le;Continue through KLI dialog and reboot the system.
.le;TGHA will run and create a new TGHA.DAT file.
.els
A message similar to the one above will be given when the SCRAP command is
given to TGHA.
.hl2 Software State Word
The software state of the memory indicates whether KLI or TGHA was the last
program to make any changes in the Bit Substitution RAM. Although the software
bits in SBDIAG function were designed for this purpose, conflicts made them
impractical. The information is flagged in a word in the Bit Substitution RAM
instead of using the software state bits. When TGHA goes to check the state of
the software state word in the Bit Substitution RAM, and TGHA finds that the
data is not of the format that either KLI or TGHA uses, the following message
will be output:
.tp6;.lt
********
22-Nov-86 13:02:59
In Controller 10, the Bit Sub RAM state word was garbage.
TGHA is assuming a DBE scan was done last.
********
.el
This is a very strange state since the Spare Bit Substitution RAM address used
for the software state word is not in the address space used for swapping of
memory bits. It is suggested that the MOS memory diagnostics be run at the
next convenient time.
.hl2 CPU ID Change
If TGHA detects that the CPU options or serial number (as read by the APRID
instuction) has changed, the following information is put into the trace file.
No action needs to be taken.
.tp6;.lt
********
28-Oct-86 11:44:44
The CPU ID has changed from 660442375467 to 660442375356
********
.el
.page;.hl1 SPEAR
The SPEAR (ERROR.SYS) entries made by TGHA have the following format. The
standard SPEAR headers have been omitted from the following examples.
.hl2 New Known Error
.lt
********
13-Jun-86 10:33:00
A new MF20 known error has been declared.
Storage module serial number: 838009, RAM size = 16K
Block: 1, Subblock: 0, Bit In Field (10): 11, Row: 71, Column: 24,
E Number 192, Error Type: Chip
********
.el
This entry is created whenever a error is detected by TGHA. There is no
immediate action to be taken.
.hl2 Serious MOS Memory Hardware Failure
.lt
********
19-Jun-86 20:20:02
TGHA has temporarily corrected a serious MOS memory failure.
Call Field Service to report this Full Mux failure condition.
********
.el
See section 5.3 for more information. It is suggested that the MOS memory
diagnostics be run at the next convenient time.
.hl2 Use Of Spare Bit By KLI
.lt
********
25-Dec-86 13:20:29
The memory boot in KLI has used the spare bit to prevent a parity error.
This condition should be corrected as soon as possible.
Controller Group Block Word (bits 33-35)
10 0 1 2
********
.el
See section 5.4 for more information. It is suggested that the MOS memory
diagnostics be run at the next convenient time.
.hl2 KLI Detected Bad Block
.lt
********
13-Jun-86 10:33:00
The following blocks of MOS memory are marked as bad and are not on line:
Controller Group Block
10 1 3
10 2 1
This consists of 128K of memory that is off line.
Call Field Service to report this condition.
********
.el
See section 5.5 for more information. It is suggested that the MOS memory
diagnostics be run at the next convenient time.
.hl2 Missing Database
.lt
********
19-Jul-86 12:35:21
MF20 Controller 10 was last initialized by TGHA, but TGHA has lost its
database. Run TGHA and use the SCRAP command to see recovery instructions.
********
.el
See section 5.6 for more information.
.hl2 Software State Word
.lt
********
22-Nov-86 13:02:59
In Controller 10, the Bit Sub RAM state word was garbage.
TGHA is assuming a DBE scan was done last.
********
.el
See section 5.7 for more information. It is suggested that the MOS memory
diagnostics be run at the next convenient time.
.page;.hl1 Storage Organization
MOS Memory Control board slot numbers and basic functions are listed in the
following table. M8579/M8570 memory array boards occupy slots 8 to 19.
.lm4;.lt
Number Name Slot Function
M8574 WRP 04 XBUS Data/Write Path/ECC Generation/Spare Out
M8576 CTL 05 XBUS and Cycle Control/Word and Group Select/PROM Read
M8575 SYN 06 Spare In/Check/Correct/Address 14-21/Voltage Margin
M8577 ADT 07 MOS Address/Timing/Refresh/Block Select/Error
.el;.lm0
.hl2 Groups, Fields, Blocks, and Subblocks
MF20/MG20 storage is composed of groups, fields, blocks, and subblocks.
A "group" is a set of four storage boards. There may be up to three groups
installed in each MF20 backplane.
A "field" is one board (11 bits) wide. Four fields used in parallel give a 44
bit word: 36 data bits, 6 ECC (Error Check and Correct) bits, one 43 bit parity
bit, and one spare bit. A bit's group and field numbers uniquely pick the
bit's storage board.
A "block" is four times the RAM size. There are one to four blocks in each
group, but there are almost always four blocks in a group. Its start address
is programmable (SBDIAG function 12). Each block has 4 subblocks.
A "subblock" is the basic storage unit. Subblocks are 1 word (44 bits) wide,
and are selected by address 34-35. Every 4th word of a block's memory belongs
to a given subblock. There is 1 spare bit RAM per subblock.
During a memory cycle all of the block's fields and subblocks are always
cycled, with the 4 XBUS request bits specifying which subblock's words are
actually to be used.
.hl2 Calculating M8579 (MF20) RAM "E" Number
To calculate the "E" number of a RAM on an M8579 board you need the Block
Number (BN), Word Number (WN), and Bit-In-Field Number (BIFN). Use error
address bits 14-21 in an SBDIAG function 12 to read the address response RAM.
Bits 12-13 of the SBDIAG echo are BN. Error address bits 34-35 are WN. BIFN
can be derived from the table in section 7.4 using the bit number from either
the syndrome (from SBDIAG function 6.1) or the known error data pattern. Use
the BIFN from section 7.4 to select a number from the table below, and plug
that number into the formula to get the actual "E" number.
.tp5;.lm8;.lt
BIFN: 0 1 2 3 4 5 6 7 8 9 10
Table: 19. 38. 57. 76. 96. 116. 149. 167. 188. 204. 224.
Formula: Enumber = table(BIFN) - (4 * WN) - BN
.el;.lm0
The M8579 storage boards do not have any E numbers etched on them, making it
difficult to locate a specific DIP. Use the map below to locate MOS RAM dips
or DC008 MUX DIPs. Example: The E number for Block (BLK) 2, Subblock (SBLK) 1,
bit 18 would be 51. Use BLK and SBLK to find the row. Using the bit number,
look in the lower table to find the column.
The map is oriented as if you held the board with the component side up and the
connector edge towards you. Note that the row of MUX chips is staggered.
.tp23;.lm8;.lt
BLK SBLK Map of M8579 RAM and MUX chips by E numbers
--- ---- --------------------------------------------
0 0 224 204 188 167 149 116 96 76 57 38 19
1 0 223 203 187 166 148 115 95 75 56 37 18
2 0 222 202 186 165 147 114 94 74 55 36 17
3 0 221 201 185 164 146 113 93 73 54 35 16
0 1 220 200 184 163 145 112 92 72 53 34 15
1 1 219 199 183 162 144 111 91 71 52 33 14
2 1 218 198 182 161 143 110 90 70 51 32 13
3 1 217 197 181 160 142 109 89 69 50 31 12
0 2 216 196 180 159 141 108 88 68 49 30 11
1 2 215 195 179 158 140 107 87 67 48 29 10
2 2 214 194 178 157 139 106 86 66 47 28 9
3 2 213 193 177 156 138 105 85 65 46 27 8
0 3 212 192 176 155 137 104 84 64 45 26 7
1 3 211 191 175 154 136 103 83 63 44 25 6
2 3 210 190 174 153 135 102 82 62 43 24 5
3 3 209 189 173 152 134 101 81 61 42 23 4
MUX 207 205 171 169 131 98 79 59 40 20 2
.el;.lm0
.hl2 Calculating M8570 (MG20) RAM "E" Number
Calculating the "E" number of an M8570 RAM is very similar to the calculations
for an M8579.
To calculate the "E" number of a RAM on an M8570 board you need the Block
Number (BN), Word Number (WN), and Bit-In-Field Number (BIFN). Use error
address bits 14-21 in an SBDIAG function 12 to read the address response RAM.
Bits 12-13 of the SBDIAG echo are BN. Error address bits 34-35 are WN. BIFN
can be derived from the table in section 7.4 using the bit number from either
the syndrome (from SBDIAG function 6.1) or the known error data pattern. Use
the BIFN from the table in section 7.4 to select a number from the table below,
and plug that number into the formula to get the actual "E" number.
.tp5;.lm8;.lt
BIFN: 0 1 2 3 4 5 6 7 8 9 10
Table: 19. 38. 57. 75. 92. 112. 146. 165. 183. 202. 221.
Formula: Enumber = Table(BIFN) - (4 * WN) - BN
.el;.lm0
M8570 storage boards do not have any E numbers etched on them, making it
difficult to locate a specific DIP. Use the map below to locate MOS RAM dips
or DC008 MUX DIPs. Example: The E number for block (BLK) 2, Subblock (SBLK) 1,
bit 18 would be 51. Use BLK and SBLK to find the row. Using the bit number,
look in the lower table to find the column. The map is oriented as if you held
the board with the component side up and the connector edge towards you. Note
that the row of MUX chips is staggered.
.tp23;.lm8;.lt
BLK SBLK Map of M8570 RAM and MUX chips by E numbers
--- --- --------------------------------------------
0 0 221 202 183 165 146 112 92 75 57 38 19
1 0 220 201 182 164 145 111 91 74 56 37 18
2 0 219 200 181 163 144 110 90 73 55 36 17
3 0 218 199 180 162 143 109 89 72 54 35 16
0 1 217 198 179 161 142 108 88 71 53 34 15
1 1 216 197 178 160 141 107 87 70 52 33 14
2 1 215 196 177 159 140 106 86 69 51 32 13
3 1 214 195 176 158 139 105 85 68 50 31 12
0 2 213 194 175 157 138 104 84 67 49 30 11
1 2 212 193 174 156 137 103 83 66 48 29 10
2 2 211 192 173 155 136 102 82 65 47 28 9
3 2 210 191 172 154 135 101 81 64 46 27 8
0 3 209 190 171 153 134 100 80 63 45 26 7
1 3 208 189 170 152 133 99 79 62 44 25 6
2 3 207 188 169 151 132 98 78 61 43 24 5
3 3 206 187 168 150 131 97 77 60 42 23 4
MUX 204 203 185 148 128 114 95 58 40 20 2
.el;.lm0
.tp48
.hl2 Table of KL10 Bit Number to Bit In Field
.lm10;.lt
KL10 Bit Bit in Syndrome
Bit Use Field Field (Note 1)
---- ------ ----- ------ --------
00 data 0 02 014
01 data 1 02 024
02 data 0 03 030
03 data 1 03 034
04 data 0 04 044
05 data 1 04 050
06 data 0 05 054
07 data 1 05 060
08 data 0 06 064
09 data 1 06 070
10 data 0 07 074
11 data 1 07 104
12 data 0 08 110
13 data 1 08 114
14 data 0 09 120
15 data 1 09 124
16 data 0 10 130
17 data 1 10 134
18 data 2 02 140
19 data 3 02 144
20 data 2 03 150
21 data 3 03 154
22 data 2 04 160
23 data 3 04 164
24 data 2 05 170
25 data 3 05 174
26 data 2 06 204
27 data 3 06 210
28 data 2 07 214
29 data 3 07 220
30 data 2 08 224
31 data 3 08 230
32 data 2 09 234
33 data 3 09 240
34 data 2 10 244
35 data 3 10 250
36 ECC32 0 00 200
37 ECC16 1 00 100
38 ECC8 0 01 040
39 ECC4 1 01 020
40 ECC2 2 00 010
41 ECC1 3 00 004
42 ECCPAR 2 01 000
43 spare 3 01 (Note 2)
.el;.lm0
Note 1: The syndrome is a six bit number and is shown here octally grouped as
it would appear in an SBDIAG function 6.1 echo in bits 07-12. Note that the
43 bit parity bit is not included in this list.
Note 2: The spare bit has no associated syndrome. If the spare bit happens to
be replacing the bit which your syndrome points to, then the error is in the
spare bit and not the bit which the syndrome points to.
.hl2 Table of KL10 Bit Number to Field
.lm8;.tp 8;.lt
Field KL10 bit numbers as positioned in field
----- -------------------------------------------
0 16 14 12 10 08 06 04 02 00 38 36
1 17 15 13 11 09 07 05 03 01 39 37
2 34 32 30 28 26 24 22 20 18 42 40
3 35 33 31 29 27 25 23 21 19 43 41
.el;.lm0
.hl2 Table of Slot Numbers to Group, Field, and Bit
.lt
Slot Group Field Bits
---- ----- ----- --------------------------------
8 2 0 36,38,00,02,04,06,08,10,12,14,16
9 1 0 same
10 0 0 same
11 2 1 37,39,01,03,05,07,09,11,13,15,17
12 1 1 same
13 0 1 same
14 2 2 40,42,18,20,22,24,26,28,30,32,34
15 1 2 same
16 0 2 same
17 2 3 41,43,19,21,23,25,27,29,31,33,35
18 1 3 same
19 0 3 same
.el
.hl2 M8579/M8570 Array Board PROM Data
Every storage array board has associated with it a serial number and other
related data. There is one 32 bit PROM "word" per board which is read using
function 2. Which word you get depends upon bits 9-12. Four SBDIAGs are
necessary to read the entire word by varying the byte number in bits 13 and 14.
The layout of a PROM word is illustrated in the following table.
.tp26;.lt
M8570/M8579 PROM Data
PROM byte: 0 1 2 3
PROM bit: 01234567012345670123456701234567
Content: YYYYWWWWWW###########PPABNNSSMMM
YYYY is the 4 bit year number which is the BCD equivalent of the
last digit of the calendar year.
WWWWWW is the 6 bit week number.
##...## is an 11 bit serial number which is restarted from 1 each week.
PP is a MOS RAM population code: 00 - MOS RAM block 0 exists
01 - blocks 0 and 1 exist
10 - blocks 0, 1, and 2 exist
11 - board is fully populated
A Parity bit such that bytes 0-2 of the word have even parity.
B Another parity bit such that byte 3 has odd parity.
NN Is the 2 bit "timing number". This number determines which
distinct timing is to be used with the RAMs on this board.
SS Is the MOS RAM size code: 11 - 4k RAMs
10 - 16K RAMs (MF20)
01 - 32K RAMs
00 - 64K RAMs (MG20)
MMM Is the 3 bit MOS RAM manufacturer code:
000 - MOSTEK 100 - Motorola
001 - Intel 101 - Texas Instruments
010 - Fujitsu 110 - Other (DEC, DEC part number, etc.)
011 - Hitachi 111 - Unassigned
.el
There are actually 8 PROM words per array board, of which only one is allowed
out by the state of the 3 jumpers. If no jumper is cut then word 0 is
selected, if all are cut then word 7 is selected. These jumpers are cut in
relation to the manufacturer of the MOS RAMs on the board. Note also that the
serial number is also printed on the board in the form: YWW_#_#_#_#
.nt
Please make sure when an array board is sent in for repair that the error
typeout showing the serial number is attached to the board.
.en
.page;.hl1 Errors
.hl2 Error Correction Code (ECC) Calculation
Calculation of the ECC is based upon bit changes from a data word of all zeros.
The ECC for all zeros is defined to be 11 111 11 (or 376 as it would appear in
bits 07-13 of an SBDIAG function 6.0).
To calculate the ECC for any given word, take each "1" bit from the data word,
get the syndrome for that bit from the table below, and XOR it into the
previous ECC. Initially the ECC is the ECC for a data word of zero.
If there are more ones than zeros in the word then do the same as above only
apply the syndromes for each "0" bit and use the initial ECC value of 10 101 11
(256 octal). Note that the following relation always holds:
.b
.c;ECC(X) = 120 XOR ECC(NOT X)
.b
In other words, the ECC for the complement of a word differs from the ECC of
the word by 120 octal.
.hl3 Syndrome and 43 Bit Parity Table
.lt
Bit Fcn 6 Syn Syn Syn Syn Syn Syn 43b
number Octal 32 16 8 4 2 1 Par
--- ----- --- --- --- --- --- --- ---
00 016 0 0 0 0 1 1 1
01 026 0 0 0 1 0 1 1
02 032 0 0 0 1 1 0 1
03 034 0 0 0 1 1 1 0
04 046 0 0 1 0 0 1 1
05 052 0 0 1 0 1 0 1
06 054 0 0 1 0 1 1 0
07 062 0 0 1 1 0 0 1
08 064 0 0 1 1 0 1 0
09 070 0 0 1 1 1 0 0
10 076 0 0 1 1 1 1 1
11 106 0 1 0 0 0 1 1
12 112 0 1 0 0 1 0 1
13 114 0 1 0 0 1 1 0
14 122 0 1 0 1 0 0 1
15 124 0 1 0 1 0 1 0
16 130 0 1 0 1 1 0 0
17 136 0 1 0 1 1 1 1
18 142 0 1 1 0 0 0 1
19 144 0 1 1 0 0 1 0
20 150 0 1 1 0 1 0 0
21 156 0 1 1 0 1 1 1
22 160 0 1 1 1 0 0 0
23 166 0 1 1 1 0 1 1
24 172 0 1 1 1 1 0 1
25 174 0 1 1 1 1 1 0
26 206 1 0 0 0 0 1 1
27 212 1 0 0 0 1 0 1
28 214 1 0 0 0 1 1 0
29 222 1 0 0 1 0 0 1
30 224 1 0 0 1 0 1 0
31 230 1 0 0 1 1 0 0
32 236 1 0 0 1 1 1 1
33 242 1 0 1 0 0 0 1
34 244 1 0 1 0 0 1 0
35 250 1 0 1 0 1 0 0
-- -- -- -- -- -- --
10 15 18 19 20 20 20 = Sum of syndrome one bits
.el
.hl3 Example ECC and 43 Bit Parity Calculation
Example: Calculate the ECC and 43 bit parity for a data word of 3.
.lm8;.lt
376 is ECC for zero
250 is syndrome and 43b par for bit 35
244 is syndrome and 43b par for bit 34
--- XOR all of the above
362 is the ECC for a data word of 3
.el;.lm0
Another method for computing the ECC is as follows: for each of the 7 ECC bits
take the data word, logically AND it with the appropriate mask below, and
compute the result's odd parity. That bit is one of the ECC bits.
.lm8;.lt
000000 001777 ECC 32
000177 776000 ECC 16
037600 776007 ECC 8
343617 036170 ECC 4
554663 146631 ECC 2
665325 253252 ECC 1
732351 455514 43B PAR
.el;.lm0
Bits 03, 09, 10, 13, 15, 25, and 32 (040624 002010) form a set which is
one of many possible "independent" bit sets. By varying the values of
these 7 bits one can generate all 128 ECC codes, though not in any
special order. Adding bit 35 allows playing with the spare bit but does
not alter the independence of this bit set.
Note that the octal number 200,,2217 (33555599 decimal) is a small,
relatively easy to remember number which produces an all zeros ECC.
.hl2 Error Detection And Correction
When a write is done the memory calculates an ECC based upon the data it got
from the CPU. The data and the ECC are then put in memory. When a read is
done the controller gets the data and the old ECC from memory. It then
computes a new ECC on the data and XORs the old and new ECCs which results in a
syndrome. Obviously if there was no error in memory The old and new ECCs will
be the same, and the syndrome will be zero since XORing equal values produces
0.
Now, when there is an error in one bit the new syndrome will differ from what
it would have been by a value equal to the syndrome of the bad bit. Thus
XORing the new syndrome with the old one from memory will result in a syndrome
equal to that of the bad bit. The syndrome mapped to a bit which, in turn, is
used to complement (ie correct) the bad bit. See the example in the next section.
When one bit is bad on a read then, obviously, the parity of the 43 bit word
from memory will be bad. Bad parity is what causes the controller to recognize
a correctable error. The controller then goes off and computes the syndrome.
If the syndrome is that of one of the ecc bits then the mapped correction bit
goes nowhere since we don't send the ECC back to the CPU.
If there is no parity error and the syndrome is zero then there is no
correction necessary. However a double bit (uncorrectable) error gives good
parity (since 2 bits are bad) and a nonzero syndrome. This is how it
recognizes an double bit error. When a double bit error is detected it ships
the data, as is, to the CPU while forcing bad XBUS parity. See the table
following for a concise list of error conditions.
.hl3 Syndrome/Parity Bit Meanings
.lm8;.lt
Syndrome Parity Meaning and Action Taken
-------- ------ ------------------------
Zero OK Everything is OK.
Take data as it is.
Zero Bad 43 bit parity bit is bad.
Use the data as it is.
1,2,4,8, Bad An ECC bit is bad.
16,32 Use the data as it is.
Not 0,1,2 Bad A data bit is bad.
4,8,16,32 Correct it and send back corrected word.
Not 0 OK This is a non-correctable error.
Put data on XBUS as it is plus bad parity.
.el;.lm0
.hl3 Example of Error Correction
Write a 3 to memory, assume that bit 27 is stuck high in memory. This example
shows how ECC is applied in that case.
.lm4;.lt
As shown previously, the ECC for 3 is 362, therefore:
3<362> goes to memory.
On the read bit 27 is stuck high so that we see:
403<362> from memory.
We calculate the new ECC:
374 is ECC for 0 (less 43b par bit)
250 is syndrome for bit 35
244 is syndrome for bit 34
210 is syndrome for bit 27
--- XOR the whole mess together
170 is the new ECC.
We now calculate the syndrome:
360 is the old ECC (less 43b par bit)
170 is the new ECC
--- XOR
210 is the syndrome
The hardware maps the syndrome to the proper bit and XORs the bit:
403 is data from memory
400 is the mapped bit
--- XOR
3 is what goes back to the CPU.
Hocus-Pocus Presto-Chango, the error is gone!
.el;.lm0
.hl3 Double Bit Error Syndromes
This is the table of syndromes vs. all possible bit pairs which could cause a
double bit error with that syndrome. The syndrome is the octal number on the
left. Remember that it is only 6 bits but is shown aligned as it is in an
SBDIAG function 6.1. All the bit pairs which would result in a given syndrome
are on the line to the right of the syndrome. These pairs are decimal KL10 bit
numbers with the lower number of the pair to the left of the comma. The pairs
are in order by the lower number.
.tp20;.lt
Syn Bit pairs which could cause a DBE with the given syndrome
--- ---------------------------------------------------------
374 15,35 16,34 17,33 18,32 19,31 20,30 21,29 22,28 23,27 24,26 25,36
370 14,35 16,33 17,34 18,31 19,32 20,29 21,30 22,27 23,28 24,36 25,26
364 14,34 15,33 17,35 18,30 19,29 20,32 21,31 22,26 23,36 24,28 25,27
360 14,33 15,34 16,35 18,29 19,30 20,31 21,32 22,36 23,26 24,27 25,28
354 11,35 12,34 13,33 18,28 19,27 20,26 21,36 22,32 23,31 24,30 25,29
350 12,33 13,34 18,27 19,28 20,36 21,26 22,31 23,32 24,29 25,30 35,37
344 11,33 13,35 18,26 19,36 20,28 21,27 22,30 23,29 24,32 25,31 34,37
340 11,34 12,35 18,36 19,26 20,27 21,28 22,29 23,30 24,31 25,32 33,37
334 11,31 12,30 13,29 14,28 15,27 16,26 17,36 23,35 24,34 25,33 32,37
330 11,32 12,29 13,30 14,27 15,28 16,36 17,26 22,35 24,33 25,34 31,37
324 11,29 12,32 13,31 14,26 15,36 16,28 17,27 22,34 23,33 25,35 30,37
320 11,30 12,31 13,32 14,36 15,26 16,27 17,28 22,33 23,34 24,35 29,37
314 11,27 12,26 13,36 14,32 15,31 16,30 17,29 19,35 20,34 21,33 28,37
310 11,28 12,36 13,26 14,31 15,32 16,29 17,30 18,35 20,33 21,34 27,37
304 11,36 12,28 13,27 14,30 15,29 16,32 17,31 18,34 19,33 21,35 26,37
300 11,26 12,27 13,28 14,29 15,30 16,31 17,32 18,33 19,34 20,35 36,37
274 01,35 02,34 03,33 04,31 05,30 06,29 07,28 08,27 09,26 10,36 32,38
270 02,33 03,34 04,32 05,29 06,30 07,27 08,28 09,36 10,26 31,38 35,39
264 01,33 03,35 04,29 05,32 06,31 07,26 08,36 09,28 10,27 30,38 34,39
260 01,34 02,35 04,30 05,31 06,32 07,36 08,26 09,27 10,28 29,38 33,39
254 00,33 04,27 05,26 06,36 07,32 08,31 09,30 10,29 28,38 34,40 35,41
250 00,34 04,28 05,36 06,26 07,31 08,32 09,29 10,30 27,38 33,40 35,42
244 00,35 04,36 05,28 06,27 07,30 08,29 09,32 10,31 26,38 33,41 34,42
240 04,26 05,27 06,28 07,29 08,30 09,31 10,32 33,42 34,41 35,40 36,38
234 00,29 01,27 02,26 03,36 08,35 09,34 10,33 28,39 30,40 31,41 32,42
230 00,30 01,28 02,36 03,26 07,35 09,33 10,34 27,39 29,40 31,42 32,41
224 00,31 01,36 02,28 03,27 07,34 08,33 10,35 26,39 29,41 30,42 32,40
220 00,32 01,26 02,27 03,28 07,33 08,34 09,35 29,42 30,41 31,40 36,39
214 00,36 01,31 02,30 03,29 04,35 05,34 06,33 26,40 27,41 28,42 32,39
210 00,26 01,32 02,29 03,30 05,33 06,34 27,42 28,41 31,39 35,38 36,40
204 00,27 01,29 02,32 03,31 04,33 06,35 26,42 28,40 30,39 34,38 36,41
200 00,28 01,30 02,31 03,32 04,34 05,35 26,41 27,40 29,39 33,38 36,42
174 00,22 01,20 02,19 03,18 04,16 05,15 06,14 07,13 08,12 09,11 10,37
17,38 21,39 23,40 24,41 25,42
170 00,23 01,21 02,18 03,19 04,17 05,14 06,15 07,12 08,13 09,37 10,11
16,38 20,39 22,40 24,42 25,41
164 00,24 01,18 02,21 03,20 04,14 05,17 06,16 07,11 08,37 09,13 10,12
15,38 19,39 22,41 23,42 25,40
160 00,25 01,19 02,20 03,21 04,15 05,16 06,17 07,37 08,11 09,12 10,13
14,38 18,39 22,42 23,41 24,40
154 00,18 01,24 02,23 03,22 04,12 05,11 06,37 07,17 08,16 09,15 10,14
13,38 19,40 20,41 21,42 25,39
150 00,19 01,25 02,22 03,23 04,13 05,37 06,11 07,16 08,17 09,14 10,15
12,38 18,40 20,42 21,41 24,39
144 00,20 01,22 02,25 03,24 04,37 05,13 06,12 07,15 08,14 09,17 10,16
11,38 18,41 19,42 21,40 23,39
140 00,21 01,23 02,24 03,25 04,11 05,12 06,13 07,14 08,15 09,16 10,17
18,42 19,41 20,40 22,39 37,38
134 00,14 01,12 02,11 03,37 04,24 05,23 06,22 07,21 08,20 09,19 10,18
13,39 15,40 16,41 17,42 25,38
130 00,15 01,13 02,37 03,11 04,25 05,22 06,23 07,20 08,21 09,18 10,19
12,39 14,40 16,42 17,41 24,38
124 00,16 01,37 02,13 03,12 04,22 05,25 06,24 07,19 08,18 09,21 10,20
11,39 14,41 15,42 17,40 23,38
120 00,17 01,11 02,12 03,13 04,23 05,24 06,25 07,18 08,19 09,20 10,21
14,42 15,41 16,40 22,38 37,39
114 00,37 01,16 02,15 03,14 04,20 05,19 06,18 07,25 08,24 09,23 10,22
11,40 12,41 13,42 17,39 21,38
110 00,11 01,17 02,14 03,15 04,21 05,18 06,19 07,24 08,25 09,22 10,23
12,42 13,41 16,39 20,38 37,40
104 00,12 01,14 02,17 03,16 04,18 05,21 06,20 07,23 08,22 09,25 10,24
11,42 13,40 15,39 19,38 37,41
100 00,13 01,15 02,16 03,17 04,19 05,20 06,21 07,22 08,23 09,24 10,25
11,41 12,40 14,39 18,38 37,42
074 00,07 01,05 02,04 03,38 06,39 08,40 09,41 10,42 11,24 12,23 13,22
14,21 15,20 16,19 17,18 25,37 30,35 31,34 32,33
070 00,08 01,06 02,38 03,04 05,39 07,40 09,42 10,41 11,25 12,22 13,23
14,20 15,21 16,18 17,19 24,37 29,35 31,33 32,34
064 00,09 01,38 02,06 03,05 04,39 07,41 08,42 10,40 11,22 12,25 13,24
14,19 15,18 16,21 17,20 23,37 29,34 30,33 32,35
060 00,10 01,04 02,05 03,06 07,42 08,41 09,40 11,23 12,24 13,25 14,18
15,19 16,20 17,21 22,37 29,33 30,34 31,35 38,39
054 00,38 01,09 02,08 03,07 04,40 05,41 06,42 10,39 11,20 12,19 13,18
14,25 15,24 16,23 17,22 21,37 26,35 27,34 28,33
050 00,04 01,10 02,07 03,08 05,42 06,41 09,39 11,21 12,18 13,19 14,24
15,25 16,22 17,23 20,37 27,33 28,34 35,36 38,40
044 00,05 01,07 02,10 03,09 04,42 06,40 08,39 11,18 12,21 13,20 14,23
15,22 16,25 17,24 19,37 26,33 28,35 34,36 38,41
040 00,06 01,08 02,09 03,10 04,41 05,40 07,39 11,19 12,20 13,21 14,22
15,23 16,24 17,25 18,37 26,34 27,35 33,36 38,42
034 00,39 01,40 02,41 03,42 04,09 05,08 06,07 10,38 11,16 12,15 13,14
17,37 18,25 19,24 20,23 21,22 26,31 27,30 28,29 32,36
030 00,01 02,42 03,41 04,10 05,07 06,08 09,38 11,17 12,14 13,15 16,37
18,24 19,25 20,22 21,23 26,32 27,29 28,30 31,36 39,40
024 00,02 01,42 03,40 04,07 05,10 06,09 08,38 11,14 12,17 13,16 15,37
18,23 19,22 20,25 21,24 26,29 27,32 28,31 30,36 39,41
020 00,03 01,41 02,40 04,08 05,09 06,10 07,38 11,15 12,16 13,17 14,37
18,22 19,23 20,24 21,25 26,30 27,31 28,32 29,36 39,42
014 00,42 01,02 03,39 04,05 06,38 07,10 08,09 11,12 13,37 14,17 15,16
18,21 19,20 22,25 23,24 26,27 28,36 29,32 30,31 34,35 40,41
010 00,41 01,03 02,39 04,06 05,38 07,09 08,10 11,13 12,37 14,16 15,17
18,20 19,21 22,24 23,25 26,28 27,36 29,31 30,32 33,35 40,42
004 00,40 01,39 02,03 04,38 05,06 07,08 09,10 11,37 12,13 14,15 16,17
18,19 20,21 22,23 24,25 26,36 27,28 29,30 31,32 33,34 41,42
000 A zero syndrome never causes a double bit error.
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FUNCTION 00 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > !CLEAR* *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! 0-5 * ! ! * ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ! < FUNCTION NUMBER > *
TO MEM 4* ! ! * ! ! * ! ! * ! ! * ! 0 ! 0 * 0 ! 0 ! 0 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5*CONTR!CORR !INCMP* <PARITY ERRORS> *INTERLEAVE ! <LAST WORD REQUESTS > *<LAST TYPE>! < ERROR ADDRESS *
FROM MEM 6* ERR ! ERR !CYCLE*READ !WRITE! ADR * 1 ! 1 ! RQ0 * RQ1 ! RQ2 ! RQ3 * RD ! WR ! 14 * 15 ! 16 ! 17 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* ERROR ADDRESS (CONTINUED) > *
FROM MEM 8* 18 ! 19 ! 20 * 21 ! 22 ! 23 * 24 ! 25 ! 26 * 27 ! 28 ! 29 * 30 ! 31 ! 32 * 33 ! 34 ! 35 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
FUNCTION 01 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! *<GROUP LOOPBACK >* *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! ! * ! ! *ENABL! GN2 ! GN1 * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ! < STATUS > !LD EN! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! * ! ! * !DSABL! SF2 * SF1 !25-27! * ! 0 ! 0 * 0 ! 0 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* ! <MEM CONTROLLER TYPE> * <LPBK GRP SEL> * *
FROM MEM 6* ! ! * ! ! * ! ! 0 * 1 ! 0 ! 1 * 0 ! 1 ! 2 * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* ! < STATUS > ! *
FROM MEM 8* ! ! * ! ! * !DSABL! SF2 * SF1 ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
SF2 and SF1 are software flags do not effect the hardware, nor does the hardware affect them except to clear them on power-up.
Their combined meanings are: 0/controller was just powered up; 1/all rams but adresp are loaded, crude patching is done and
Bitsub RAM says which blocks may be used; 2/same as 1 but controller is configured; 3/same as 2 except that TGHA has finished its
work.
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FUNCTION 02 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! * < SM PROM SELECT > !<PROM BYTE>* *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! ! * GN2 ! GN1 ! FN2 * FN1 ! 2 ! 1 * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ! < DIAG MIXER INPUT SELECT > ! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! * ! ! 2 * 3 ! 4 ! 5 * 6 ! ! * ! 0 ! 0 * 0 ! 1 ! 0 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* !<ERROR WD#>! < SELECTED DIAG DATA OR PROM DATA > * *
FROM MEM 6* ! ! * ! ! 2 * 1 ! 0 ! 1 * 2 ! 3 ! 4 * 5 ! 6 ! 7 * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* ! < MOS ADDRESS (SINGLE STEP ONLY) > !<CTL RAM PAR ERR>! *
FROM MEM 8* ! ! 0 * 1 ! 2 ! 3 * 4 ! 5 ! 6 * 7 ! TIM ! SUB * ADR ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
Note: bits 23-27 are only used during single step diagnostic tests. The leftmost 1 bit selects the corresponding mixer input
for reading diagnostic signals. If 23-27 are 0 then the data returned is the selected SM PROM word. Note also that
bits 26-27 are used to select the address which is sent back in the MOS address field.
FUNCTION 03 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! !FAST * !<FIXED VAL LOGIC RAMS >!LD EN*LD EN! *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! ! BUS * !ACKN !D VLD*RDA34!RDA35! 10 *11-13! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ! < FIXED VALUE LOGIC RAM LOAD ADDRESS > ! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! 0 * 1 ! 2 ! 3 * 4 ! 5 ! 6 * 7 ! ! * ! 0 ! 0 * 0 ! 1 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* !FAST * !<FIXED VAL LOGIC RAMS >! *
FROM MEM 6* ! ! * ! ! * ! ! BUS * !ACKN !D VLD*RDA34!RDA35! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* *
FROM MEM 8* ! ! * ! ! * ! ! * ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
Notes: The ACKN RAM (bit 10) uses address bits 1-7 only.
The fast-bus bit is disconnected internally and is left in only for diagnostic compatability.
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FUNCTION 04 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > !PORT * * < SINGLE STEP CLOCK CONTROL *
TO MEM 2* 0 ! 1 ! ? * ? ! ? !LPBK * ! ! *A COM!B COM!D VLD* ! !SSCLK*SSMOD! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* SS CLK CTL > *REFR !LD EN! * < REFRESH INTERVAL (GATED CLOCK/16) > ! < FUNCTION NUMBER > *
TO MEM 4* ! !RNOW *ALLOW!24-30! * 1 ! 2 ! 3 * 4 ! 5 ! 6 * 7 ! 0 ! 0 * 1 ! 0 ! 0 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* * < SS CLOCK CONTROL ECHO > ! *
FROM MEM 6* ! ! * ! ! * ! ! *A COM!B COM! * ! ! *SSMOD! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* *REFR ! ! < REFRESH INTERVAL COUNTER > ! *
FROM MEM 8* ! ! *ALLOW! ! 0 * 1 ! 2 ! 3 * 4 ! 5 ! 6 * 7 ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
Note: if port loopback is set (bit 5) the controller will just echo anything sent out by SBDIAG as long as the proper
controller number is given. Only an SBUS reset can clear this condition.
FUNCTION 05 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! * < SINGLE STEP SIMULATED REQUEST BITS > ! *LD EN! *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! *ST A !ST B ! RQ0 * RQ1 ! RQ2 ! RQ3 * RD ! WR ! * SS ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ! < SINGLE STEP REQUEST SIMULATED ADDRESS BITS > ! < FUNCTION NUMBER > *
TO MEM 4* ! ! 14 * 15 ! 16 ! 17 * 18 ! 19 ! 20 * 21 ! ! 34 * 35 ! 0 ! 0 * 1 ! 0 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* *
FROM MEM 6* ! ! * ! ! * ! ! * ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* * < SS MOS RAS > ! *
FROM MEM 8* ! ! * ! ! * 0 ! 1 ! 2 * 3 ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
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FUNCTION 06 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! ! < DIAGNOSTIC DATA TO SY OR WP BOARD > *LD EN! *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! 32 ! 16 * 8 ! 4 ! 2 * 1 !MISC !MISC *07-14! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* !<ECC DIAG SUBFCN>! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! * ! ! * ! 4 ! 2 * 1 ! ! * ! 0 ! 0 * 1 ! 1 ! 0 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* ! < DIAGNOSTIC DATA FROM SY OR WP BOARD > * *
FROM MEM 6* ! ! * ! ! * ! 32 ! 16 * 8 ! 4 ! 2 * 1 !MISC !MISC * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* * < SS MOS CAS > ! *
FROM MEM 8* ! ! * ! ! * 0 ! 1 ! 2 * 3 ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
Note: SBDIAG function 6 does different things depending on the subfunction code in bits 25-27:
6.0 Read the ECC register on the SYN board.
6.1 Read the syndrome buffer on the SYN board. This function is also normally used by monitor.
6.2 Sel diag bits 07-13 in place of MOS bits 36-42, force zeros on 00-35, run thru a correction pass, and return 00-35.
*** Please note that fcn 6.2 returns the entire word, not just bits 7-14. ***
6.3 Unused
6.4 Write ECC complement reg if bit 15 set, then read it back.
6.5 Write ECC complement reg if bit 15 set, then enable it to be sent to mem in place of d36-42 on next write to mem.
6.6 Read d36-43 mixer.
6.7 Enable latching of d36-43 mixer after next write.
7 8 9 10 11 12 13 14 7 8 9 10 11 12 13 14
+-----+-----*-----+-----+-----*-----+-----+-----* +-----+-----*-----+-----+-----*-----+-----+-----*
SUBFUNCTION ! < MEM BITS 36-43 LATCHED ON LAST RD ERROR > * SUBFUNCTION ! < ECC BITS TO BE COMPLEMENTED ON WR > ! PAR *
6.0 !ECC32!ECC16*ECC8 !ECC4 !ECC2 *ECC1 !E PAR!SPARE* 6.4 ! 32 ! 16 * 8 ! 4 ! 2 * 1 !E PAR! CTL *
+-----+-----*-----+-----+-----*-----+-----+-----* +-----+-----*-----+-----+-----*-----+-----+-----*
+-----+-----*-----+-----+-----*-----+-----+-----* +-----+-----*-----+-----+-----*-----+-----+-----*
SUBFUNCTION ! <SYNDROME LATCHED ON LAST RD ERR> !<ERR TYPE >* SUBFUNCTION ! <BITS 36-43 AS WRITTEN TO MEM AFTER FCN 6.7 > *
6.1 ! 32 ! 16 * 8 ! 4 ! 2 * 1 ! CORR! DBL * 6.6 !ECC32!ECC16*ECC8 !ECC4 !ECC2 *ECC1 !E PAR!SPARE*
+-----+-----*-----+-----+-----*-----+-----+-----* +-----+-----*-----+-----+-----*-----+-----+-----*
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FUNCTION 07 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! ! < BIT SUBSTITUTION RAM DATA (BIT NUMBERS) > *LD EN! *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! 32 ! 16 * 8 ! 4 ! 2 * 1 ! ICE ! PAR *07-14! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* * < BIT SUBSTITUTION RAM LOAD ADDRESS > ! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! * GN2 ! GN1 ! BN2 * BN1 ! 33 ! 34 * 35 ! ! * ! 0 ! 0 * 1 ! 1 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* ! < BIT SUBSTITUTION RAM DATA ECHO > * *
FROM MEM 6* ! ! * ! ! * ! 32 ! 16 * 8 ! 4 ! 2 * 1 ! ICE ! PAR * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* * < SS MOS WR EN > ! *
FROM MEM 8* ! ! * ! ! * 0 ! 1 ! 2 * 3 ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
"ICE" means ignore correctable error (ie don't set correctable error flag)
FUNCTION 10 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! ! < VOLTAGE MARGINS > ! < V MARGIN ENABLES > *LD EN! *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * !12.60!5.25 *-2.10!-5.46! 12 * 5 ! -2 !-5.2 *07-14! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* !CORR * CLR ! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! * ! ! * ! ! DIS *DCBAD! ! * ! 0 ! 1 * 0 ! 0 ! 0 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* ! < VOLTAGE MARGINS > ! < V MARGINS ENABLED > * *
FROM MEM 6* ! ! * ! ! * !12.60!5.25 *-2.10!-5.46! 12 * 5 ! -2 !-5.2 * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* !CORR * DC ! *
FROM MEM 8* ! ! * ! ! * ! ! DIS * BAD ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
Note: the voltages given above apply for ones in bits 7-10 where enabled by bits 11-14. The voltages corresponding to zeros
in bits 7-10 are 11.40, 4.75, -1.90, and -4.94. More than one margin may be set concurrently.
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FUNCTION 11 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! ! < TIMING RAM LOAD ADR... *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! ! * ! ! * ! 0 ! 1 * 2 ! 3 ! 4 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ...ADR > !LD EN* < TIMING RAM DATA > ! ! < FUNCTION NUMBER > *
TO MEM 4* 5 ! 6 !21-30* RAS ! CAS ! PAR *WR EN!2ND A!D RDY*B CLR! ! * ! 0 ! 1 * 0 ! 0 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* *
FROM MEM 6* ! ! * ! ! * ! ! * ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* * < TIMING RAM DATA ECHO > ! ! 4K *-DSEL! *
FROM MEM 8* ! ! * RAS ! CAS ! PAR *WR EN!2ND A!D RDY*B CLR! ! EN *CYCEN! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
FUNCTION 12 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! ! < ADDRESS RESPONSE RAM DATA > *LD EN! *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! ! PAR *TYPE ! GN2 ! GN1 * BN2 ! BN1 !DESEL*08-14! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ! < ADDRESS RESPONSE RAM LOAD ADDRESS > ! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! 14 * 15 ! 16 ! 17 * 18 ! 19 ! 20 * 21 ! ! * ! 0 ! 1 * 0 ! 1 ! 0 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* ! < ADDRESS RESPONSE RAM ECHO > * *
FROM MEM 6* ! ! * ! ! * ! ! PAR *TYPE ! GN2 ! GN1 * BN2 ! BN1 !DESEL* ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* *
FROM MEM 8* ! ! * ! ! * ! ! * ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
Note: "DESEL" (bit 14) is "box deselected on 1".
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00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
APRID *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
700000 * < MICROCODE OPTIONS > * < MICROCODE VERSION NUMBER > *
LH(E) *KLPAG!XADDR!UNSTD* ! ! * ! !TRCKS* ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
* < HARDWARE OPTIONS > * < PROCESSOR SERIAL NUMBER > *
RH(E) *50 HZ!CACHE!CHANL* XADR!MSTR ! * ! ! * ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
CONO APR, *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
700200 * ! I/O ! SELECTED FLAGS * < SELECT FLAG > ! * PI LEVEL *
E * !RESET! EN * DIS ! CLR ! SET * SBUS! NXM ! IOPF*MBPAR!C DIR!ADR P*POWER!SWEEP! * 4 ! 2 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
CONI APR, *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
700240 * * < ENABLED FLAGS > ! *
LH(E) * ! ! * ! ! * SBUS! NXM ! IOPF*MBPAR!C DIR!ADR P*POWER!SWEEP! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
* !SWEEP! * SBUS! ! I/O * MB !CACHE! ADDR*POWER!SWEEP! INT * PI LEVEL *
RH(E) * ! BUSY! * ! ! * ERR ! NXM ! PGF * PAR ! DIR ! PAR * FAIL! DONE! REQ * 4 ! 2 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
RDERA *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
700400 * WORD NO !SWEEP* CHAN! DATA SRC *WRITE! ! PHYSICAL ADDRESS *
LH(E) * ! ! REF * REF ! ! * REF ! JUNK! JUNK* ! ! * ! ! 14 * 15 ! 16 ! 17 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
* < PHYSICAL ADDRESS OF FIRST WORD OF TRANSFER > *
RH(E) * 18 ! 19 ! 20 * 21 ! 22 ! 23 * 24 ! 25 ! 26 * 27 ! 28 ! 29 * 30 ! 31 ! 32 * 33 ! 34 ! 35 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
DATA SRC WRITE = 0 WRITE = 1
00 MEMORY (READ, RPW) CHANNEL (STORE STATUS)
01 CHANNEL (DATA STORE)
10 EBOX STORE FROM AR
11 READ FROM CACHE WRITEBACK FROM CACHE
(PG REFILL OR CHAN READ)
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
CONO PI, *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
700600 * WRITE EVEN PAR * ! DROP!CLEAR* REQ ! TURN CHAN * TURN SYS ! < SELECT CHANNEL > *
E * ADDR! DATA! DIR * ! INT ! SYS * INT ! ON ! OFF * OFF ! ON ! 1 * 2 ! 3 ! 4 * 5 ! 6 ! 7 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
.el
[End of TGHA.DOC]
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