diff --git a/Board Files/NullCIC.kicad_pcb b/Board Files/NullCIC.kicad_pcb
new file mode 100644
index 0000000..aa9d4f3
--- /dev/null
+++ b/Board Files/NullCIC.kicad_pcb	
@@ -0,0 +1,381 @@
+(kicad_pcb (version 20171130) (host pcbnew "(5.1.2)-2")
+
+  (general
+    (thickness 1.6)
+    (drawings 7)
+    (tracks 24)
+    (zones 0)
+    (modules 4)
+    (nets 18)
+  )
+
+  (page A4)
+  (layers
+    (0 F.Cu signal)
+    (31 B.Cu signal)
+    (32 B.Adhes user)
+    (33 F.Adhes user)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (41 Cmts.User user)
+    (42 Eco1.User user)
+    (43 Eco2.User user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.25)
+    (trace_clearance 0.2)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.2)
+    (via_size 0.8)
+    (via_drill 0.4)
+    (via_min_size 0.4)
+    (via_min_drill 0.3)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (edge_width 0.05)
+    (segment_width 0.2)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.12)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0.051)
+    (solder_mask_min_width 0.25)
+    (aux_axis_origin 0 0)
+    (visible_elements 7FFFFFFF)
+    (pcbplotparams
+      (layerselection 0x010fc_ffffffff)
+      (usegerberextensions false)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 0)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+  (net 1 /GND)
+  (net 2 /RST-Out)
+  (net 3 "Net-(U1-Pad14)")
+  (net 4 /RST-In)
+  (net 5 "Net-(U1-Pad13)")
+  (net 6 "Net-(U1-Pad6)")
+  (net 7 "Net-(U1-Pad12)")
+  (net 8 "Net-(U1-Pad5)")
+  (net 9 "Net-(U1-Pad11)")
+  (net 10 "Net-(U1-Pad4)")
+  (net 11 "Net-(U1-Pad10)")
+  (net 12 "Net-(U1-Pad3)")
+  (net 13 "Net-(U1-Pad2)")
+  (net 14 "Net-(U1-Pad1)")
+  (net 15 /VCC)
+  (net 16 "Net-(U2-Pad1)")
+  (net 17 "Net-(U1-Pad15)")
+
+  (net_class Default "This is the default net class."
+    (clearance 0.2)
+    (trace_width 0.25)
+    (via_dia 0.8)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net /GND)
+    (add_net /RST-In)
+    (add_net /RST-Out)
+    (add_net /VCC)
+    (add_net "Net-(U1-Pad1)")
+    (add_net "Net-(U1-Pad10)")
+    (add_net "Net-(U1-Pad11)")
+    (add_net "Net-(U1-Pad12)")
+    (add_net "Net-(U1-Pad13)")
+    (add_net "Net-(U1-Pad14)")
+    (add_net "Net-(U1-Pad15)")
+    (add_net "Net-(U1-Pad2)")
+    (add_net "Net-(U1-Pad3)")
+    (add_net "Net-(U1-Pad4)")
+    (add_net "Net-(U1-Pad5)")
+    (add_net "Net-(U1-Pad6)")
+    (add_net "Net-(U2-Pad1)")
+  )
+
+  (module Resistor_SMD:R_0805_2012Metric (layer F.Cu) (tedit 5B36C52B) (tstamp 5E5EE3A9)
+    (at 151.77 81.34 180)
+    (descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5E5EE2D3)
+    (attr smd)
+    (fp_text reference R1 (at 0 -1.65) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 0R (at 0 1.65) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 0 270) (layer F.Fab)
+      (effects (font (size 0.5 0.5) (thickness 0.08)))
+    )
+    (fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.258578 0.71) (end 0.258578 0.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start -0.258578 -0.71) (end 0.258578 -0.71) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
+    (fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
+    (fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 4 /RST-In))
+    (pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+      (net 1 /GND))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0805_2012Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_DIP:DIP-16_W7.62mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5E5DC7E4)
+    (at 147.9 73.1)
+    (descr "16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
+    (tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
+    (path /5E5D6A32)
+    (fp_text reference " " (at 3.34 -2.37) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 10NES_CIC (at 3.81 20.11) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 3.81 8.89) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 8.7 19.3) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.1 19.3) (end 8.7 19.3) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.1 -1.55) (end -1.1 19.3) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 6.46 19.11) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.16 19.11) (end 6.46 19.11) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.16 -1.33) (end 1.16 19.11) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.635 19.05) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 6.985 19.05) (end 0.635 19.05) (layer F.Fab) (width 0.1))
+    (fp_line (start 6.985 -1.27) (end 6.985 19.05) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
+    (fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
+    (pad 16 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 15 /VCC))
+    (pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 1 /GND))
+    (pad 15 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 17 "Net-(U1-Pad15)"))
+    (pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 4 /RST-In))
+    (pad 14 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 3 "Net-(U1-Pad14)"))
+    (pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 6 "Net-(U1-Pad6)"))
+    (pad 13 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 5 "Net-(U1-Pad13)"))
+    (pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 8 "Net-(U1-Pad5)"))
+    (pad 12 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 7 "Net-(U1-Pad12)"))
+    (pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 10 "Net-(U1-Pad4)"))
+    (pad 11 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 9 "Net-(U1-Pad11)"))
+    (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 12 "Net-(U1-Pad3)"))
+    (pad 10 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 11 "Net-(U1-Pad10)"))
+    (pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 13 "Net-(U1-Pad2)"))
+    (pad 9 thru_hole oval (at 7.62 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 2 /RST-Out))
+    (pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 14 "Net-(U1-Pad1)"))
+    (model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-16_W7.62mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_TO_SOT_SMD:SOT-353_SC-70-5 (layer F.Cu) (tedit 5A02FF57) (tstamp 5E5DBDA5)
+    (at 151.61 77.03 90)
+    (descr "SOT-353, SC-70-5")
+    (tags "SOT-353 SC-70-5")
+    (path /5E5D9296)
+    (attr smd)
+    (fp_text reference U2 (at 2.56 -0.01 180) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 74LVC1GU04DRL (at 0 2 270) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start -0.175 -1.1) (end -0.675 -0.6) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.675 1.1) (end -0.675 1.1) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.675 -1.1) (end 0.675 1.1) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.6 1.4) (end 1.6 1.4) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.675 -0.6) (end -0.675 1.1) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.675 -1.1) (end -0.175 -1.1) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.6 -1.4) (end 1.6 -1.4) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.6 -1.4) (end -1.6 1.4) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.6 1.4) (end 1.6 -1.4) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.7 1.16) (end 0.7 1.16) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0.7 -1.16) (end -1.2 -1.16) (layer F.SilkS) (width 0.12))
+    (fp_text user %R (at 0 0) (layer F.Fab)
+      (effects (font (size 0.5 0.5) (thickness 0.075)))
+    )
+    (pad 5 smd rect (at 0.95 -0.65 90) (size 0.65 0.4) (layers F.Cu F.Paste F.Mask)
+      (net 15 /VCC))
+    (pad 4 smd rect (at 0.95 0.65 90) (size 0.65 0.4) (layers F.Cu F.Paste F.Mask)
+      (net 2 /RST-Out))
+    (pad 2 smd rect (at -0.95 0 90) (size 0.65 0.4) (layers F.Cu F.Paste F.Mask)
+      (net 4 /RST-In))
+    (pad 3 smd rect (at -0.95 0.65 90) (size 0.65 0.4) (layers F.Cu F.Paste F.Mask)
+      (net 1 /GND))
+    (pad 1 smd rect (at -0.95 -0.65 90) (size 0.65 0.4) (layers F.Cu F.Paste F.Mask)
+      (net 16 "Net-(U2-Pad1)"))
+    (model ${KISYS3DMOD}/Package_TO_SOT_SMD.3dshapes/SOT-353_SC-70-5.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:CP_Elec_4x5.3 (layer F.Cu) (tedit 5BCA39CF) (tstamp 5E5DBD6E)
+    (at 151.72 87.44 90)
+    (descr "SMD capacitor, aluminum electrolytic, Vishay, 4.0x5.3mm")
+    (tags "capacitor electrolytic")
+    (path /5E5DAB45)
+    (attr smd)
+    (fp_text reference C1 (at -4.26 0.02 180) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 0.47uF (at 0 3.2 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 0.8 0.8) (thickness 0.12)))
+    )
+    (fp_line (start -3.35 1.05) (end -2.4 1.05) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -3.35 -1.05) (end -3.35 1.05) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.4 -1.05) (end -3.35 -1.05) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.4 1.05) (end -2.4 1.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.4 -1.25) (end -2.4 -1.05) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.4 -1.25) (end -1.25 -2.4) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.4 1.25) (end -1.25 2.4) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.25 -2.4) (end 2.4 -2.4) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.25 2.4) (end 2.4 2.4) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 2.4 1.05) (end 2.4 2.4) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 3.35 1.05) (end 2.4 1.05) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 3.35 -1.05) (end 3.35 1.05) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 2.4 -1.05) (end 3.35 -1.05) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 2.4 -2.4) (end 2.4 -1.05) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.75 -1.81) (end -2.75 -1.31) (layer F.SilkS) (width 0.12))
+    (fp_line (start -3 -1.56) (end -2.5 -1.56) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.26 1.195563) (end -1.195563 2.26) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.26 -1.195563) (end -1.195563 -2.26) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.26 -1.195563) (end -2.26 -1.06) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.26 1.195563) (end -2.26 1.06) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.195563 2.26) (end 2.26 2.26) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.195563 -2.26) (end 2.26 -2.26) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.26 -2.26) (end 2.26 -1.06) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.26 2.26) (end 2.26 1.06) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.374773 -1.2) (end -1.374773 -0.8) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.574773 -1) (end -1.174773 -1) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.15 1.15) (end -1.15 2.15) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.15 -1.15) (end -1.15 -2.15) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.15 -1.15) (end -2.15 1.15) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.15 2.15) (end 2.15 2.15) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.15 -2.15) (end 2.15 -2.15) (layer F.Fab) (width 0.1))
+    (fp_line (start 2.15 -2.15) (end 2.15 2.15) (layer F.Fab) (width 0.1))
+    (fp_circle (center 0 0) (end 2 0) (layer F.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 1.8 0 90) (size 2.6 1.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.15625)
+      (net 1 /GND))
+    (pad 1 smd roundrect (at -1.8 0 90) (size 2.6 1.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.15625)
+      (net 2 /RST-Out))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/CP_Elec_4x5.3.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (gr_line (start 157.04 92.83) (end 157.04 71.05) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 157.04 71.05) (end 146.19 71.05) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 146.19 92.83) (end 157.04 92.83) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 146.19 71.23) (end 146.19 92.83) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 146.19 71.05) (end 146.19 71.23) (layer Edge.Cuts) (width 0.05) (tstamp 5E5DCE44))
+  (gr_text NullCIC (at 152.74 81.88 90) (layer B.SilkS)
+    (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+  )
+  (gr_text Redherring32 (at 150.57 81.88 90) (layer B.SilkS)
+    (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+  )
+
+  (segment (start 152.37 84.99) (end 151.72 85.64) (width 0.25) (layer F.Cu) (net 1))
+  (segment (start 148.699999 90.080001) (end 147.9 90.88) (width 0.25) (layer F.Cu) (net 1))
+  (segment (start 150.59499 88.18501) (end 148.699999 90.080001) (width 0.25) (layer F.Cu) (net 1))
+  (segment (start 150.59499 86.76501) (end 150.59499 88.18501) (width 0.25) (layer F.Cu) (net 1))
+  (segment (start 151.72 85.64) (end 150.59499 86.76501) (width 0.25) (layer F.Cu) (net 1))
+  (segment (start 152.7075 84.6525) (end 152.7075 81.34) (width 0.25) (layer F.Cu) (net 1))
+  (segment (start 151.72 85.64) (end 152.7075 84.6525) (width 0.25) (layer F.Cu) (net 1))
+  (segment (start 152.7075 78.4275) (end 152.26 77.98) (width 0.25) (layer F.Cu) (net 1))
+  (segment (start 152.7075 81.34) (end 152.7075 78.4275) (width 0.25) (layer F.Cu) (net 1))
+  (segment (start 153.88 89.24) (end 155.52 90.88) (width 0.25) (layer F.Cu) (net 2))
+  (segment (start 152.26 76.655) (end 152.26 76.08) (width 0.25) (layer F.Cu) (net 2))
+  (segment (start 153.88 78.275) (end 152.26 76.655) (width 0.25) (layer F.Cu) (net 2))
+  (segment (start 153.88 89.24) (end 153.88 78.275) (width 0.25) (layer F.Cu) (net 2))
+  (segment (start 153.36 90.88) (end 155.52 90.88) (width 0.25) (layer F.Cu) (net 2))
+  (segment (start 151.72 89.24) (end 153.36 90.88) (width 0.25) (layer F.Cu) (net 2))
+  (segment (start 151.61 80.5625) (end 151.61 77.98) (width 0.25) (layer F.Cu) (net 4))
+  (segment (start 150.8325 81.34) (end 151.61 80.5625) (width 0.25) (layer F.Cu) (net 4))
+  (segment (start 149.225 82.9475) (end 150.8325 81.34) (width 0.25) (layer F.Cu) (net 4))
+  (segment (start 149.225 87.015) (end 149.225 82.9475) (width 0.25) (layer F.Cu) (net 4))
+  (segment (start 147.9 88.34) (end 149.225 87.015) (width 0.25) (layer F.Cu) (net 4))
+  (segment (start 154.38863 73.1) (end 155.52 73.1) (width 0.25) (layer F.Cu) (net 15))
+  (segment (start 153.365 73.1) (end 154.38863 73.1) (width 0.25) (layer F.Cu) (net 15))
+  (segment (start 150.96 75.505) (end 153.365 73.1) (width 0.25) (layer F.Cu) (net 15))
+  (segment (start 150.96 76.08) (end 150.96 75.505) (width 0.25) (layer F.Cu) (net 15))
+
+)
diff --git a/Board Files/NullCIC.pro b/Board Files/NullCIC.pro
new file mode 100644
index 0000000..152769c
--- /dev/null
+++ b/Board Files/NullCIC.pro	
@@ -0,0 +1,33 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
diff --git a/Board Files/NullCIC.sch b/Board Files/NullCIC.sch
new file mode 100644
index 0000000..d176432
--- /dev/null
+++ b/Board Files/NullCIC.sch	
@@ -0,0 +1,88 @@
+EESchema Schematic File Version 4
+EELAYER 29 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L NES-CPU-11:10NES_CIC U1
+U 1 1 5E5D6A32
+P 6300 4850
+F 0 "U1" H 6300 5515 50  0000 C CNN
+F 1 "10NES_CIC" H 6300 5424 50  0000 C CNN
+F 2 "Package_DIP:DIP-16_W7.62mm" H 6300 5550 50  0001 C CNN
+F 3 "" H 6350 4950 50  0001 C CNN
+	1    6300 4850
+	1    0    0    -1  
+$EndComp
+$Comp
+L 74xGxx:74LVC1GU04DRL U2
+U 1 1 5E5D9296
+P 7300 4850
+F 0 "U2" V 7396 4606 50  0000 R CNN
+F 1 "74LVC1GU04DRL" V 7305 4606 50  0000 R CNN
+F 2 "Package_TO_SOT_SMD:SOT-353_SC-70-5" H 7300 4600 50  0001 C CNN
+F 3 "http://www.ti.com/lit/ds/symlink/sn74lvc1gu04.pdf" H 7225 4850 50  0001 C CNN
+	1    7300 4850
+	0    -1   -1   0   
+$EndComp
+Text Label 6750 4450 0    50   ~ 0
+VCC
+Text Label 5850 5150 2    50   ~ 0
+GND
+Text Label 7100 4850 2    50   ~ 0
+VCC
+Text Label 7500 4850 0    50   ~ 0
+GND
+Text Label 7300 5050 3    50   ~ 0
+RST-In
+Text Label 7300 4550 1    50   ~ 0
+RST-Out
+Text Label 6750 5150 0    50   ~ 0
+RST-Out
+Text Label 5850 5050 2    50   ~ 0
+RST-In
+Wire Wire Line
+	6150 5550 5850 5550
+Wire Wire Line
+	5850 5550 5850 5150
+Wire Wire Line
+	6450 5550 6750 5550
+Wire Wire Line
+	6750 5550 6750 5150
+$Comp
+L Device:R R1
+U 1 1 5E5EE2D3
+P 5300 4900
+F 0 "R1" H 5230 4854 50  0000 R CNN
+F 1 "0R" H 5230 4945 50  0000 R CNN
+F 2 "Resistor_SMD:R_0805_2012Metric" V 5230 4900 50  0001 C CNN
+F 3 "~" H 5300 4900 50  0001 C CNN
+	1    5300 4900
+	-1   0    0    1   
+$EndComp
+Text Label 5300 5050 3    50   ~ 0
+GND
+Text Label 5300 4750 1    50   ~ 0
+RST-In
+$Comp
+L Device:CP C1
+U 1 1 5E5DAB45
+P 6300 5550
+F 0 "C1" V 6045 5550 50  0000 C CNN
+F 1 "0.47uF" V 6136 5550 50  0000 C CNN
+F 2 "Capacitor_SMD:CP_Elec_4x5.3" H 6338 5400 50  0001 C CNN
+F 3 "~" H 6300 5550 50  0001 C CNN
+	1    6300 5550
+	0    1    1    0   
+$EndComp
+$EndSCHEMATC