diff --git a/Electrical/Board_003/.gitignore b/Electrical/Board_003/.gitignore new file mode 100644 index 00000000..5e756a94 --- /dev/null +++ b/Electrical/Board_003/.gitignore @@ -0,0 +1,3 @@ +*.kicad_pcb-bak +*.bak +*.bck diff --git a/Electrical/Board_003/README.md b/Electrical/Board_003/README.md new file mode 100644 index 00000000..f970383f --- /dev/null +++ b/Electrical/Board_003/README.md @@ -0,0 +1,42 @@ + +# Overview + +This board can be used to simulate a M-Bus master unit instead of +connecting to the real AMS unit, i.e. usable for test and development. +It takes a 5 V TTL level input (serial) signal and converts it +to a M-bus level signal. It only supports sending. Based on +[MBus_USB.pdf](https://github.com/rscada/libmbus/blob/master/hardware/MBus_USB.pdf)1. +It depends on an external power source capable of delivering 25-40 Volt. +Most DC-DC boost/step-up converter modules2 should be fine for this. + +![](mbus_master.png) + +## BOM + +* D1 13V zener +* Q1-Q3 NPN transistor +* Q4 PNP transistor +* R1 1k +* R2 6.8k +* R3 1 (optional, can be shorted instead) +* R4 150 +* R5 22k +* R6 220k + +Note for the zener. This board depends on the zener to operate below 1mA, +e.g. like 1N5350 whereas a BZX55 will probably not operate properly. + +![](zener_ok.png?raw=true) ![](zener_not_ok.png?raw=true) + +This could be accomplished by reducing the 22k resistor so that it +draws enough current. + + + +------------- + +1 +See also https://electronics.stackexchange.com/questions/99388/designing-a-m-bus-master-up-to-10-slaves/ and https://electronics.stackexchange.com/a/214477/568. + +2 +Like for instance [this one](http://hobbycomponents.com/power/698-xl60009-dc-dc-step-up-boost-converter) for £3. diff --git a/Electrical/Board_003/doc/MBus_USB.pdf b/Electrical/Board_003/doc/MBus_USB.pdf new file mode 100644 index 00000000..354162f6 Binary files /dev/null and b/Electrical/Board_003/doc/MBus_USB.pdf differ diff --git a/Electrical/Board_003/doc/minimaster.tif b/Electrical/Board_003/doc/minimaster.tif new file mode 100644 index 00000000..feeaec6c Binary files /dev/null and b/Electrical/Board_003/doc/minimaster.tif differ diff --git a/Electrical/Board_003/mbus_master-cache.lib b/Electrical/Board_003/mbus_master-cache.lib new file mode 100644 index 00000000..75df3562 --- /dev/null +++ b/Electrical/Board_003/mbus_master-cache.lib @@ -0,0 +1,143 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# BC547 +# +DEF BC547 Q 0 0 Y N 1 F N +F0 "Q" 200 75 50 H V L CNN +F1 "BC547" 200 0 50 H V L CNN +F2 "TO_SOT_Packages_THT:TO-92_Molded_Narrow" 200 -75 50 H I L CIN +F3 "" 0 0 50 H I L CNN +ALIAS BC546 BC548 BC549 BC550 BC337 BC338 +$FPLIST + TO?92* +$ENDFPLIST +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 25 0 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 200 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# BD140 +# +DEF BD140 Q 0 0 Y N 1 F N +F0 "Q" 200 75 50 H V L CNN +F1 "BD140" 200 0 50 H V L CNN +F2 "TO_SOT_Packages_THT:TO-126_Vertical" 200 -75 50 H I L CIN +F3 "" 0 0 50 H I L CNN +ALIAS BD136 BD138 BD234 BD236 BD238 +$FPLIST + TO?126* +$ENDFPLIST +DRAW +C 50 0 111 0 1 12 N +P 2 0 1 0 0 0 25 0 N +P 2 0 1 0 100 -100 25 -25 N +P 2 0 1 0 100 100 25 25 N +P 3 0 1 20 25 75 25 -75 25 -75 F +P 5 0 1 0 55 -75 75 -55 35 -35 55 -75 55 -75 F +X E 1 100 -200 100 U 50 50 1 1 P +X C 2 100 200 100 D 50 50 1 1 P +X B 3 -200 0 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# Conn_01x02 +# +DEF Conn_01x02 J 0 40 Y N 1 F N +F0 "J" 0 100 50 H V C CNN +F1 "Conn_01x02" 0 -200 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Connector*:*_??x*mm* + Connector*:*1x??x*mm* + Pin?Header?Straight?1X* + Pin?Header?Angled?1X* + Socket?Strip?Straight?1X* + Socket?Strip?Angled?1X* +$ENDFPLIST +DRAW +S -50 -95 0 -105 1 1 6 N +S -50 5 0 -5 1 1 6 N +S -50 50 50 -150 1 1 10 f +X Pin_1 1 -200 0 150 R 50 50 1 1 P +X Pin_2 2 -200 -100 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# D_Zener_Small_ALT +# +DEF D_Zener_Small_ALT D 0 10 N N 1 F N +F0 "D" 0 90 50 H V C CNN +F1 "D_Zener_Small_ALT" 0 -90 50 H V C CNN +F2 "" 0 0 50 V I C CNN +F3 "" 0 0 50 V I C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +P 2 0 1 0 30 0 -30 0 N +P 3 0 1 0 -10 40 -30 40 -30 -40 N +P 4 0 1 0 30 40 -30 0 30 -40 30 40 F +X K 1 -100 0 70 R 50 50 1 1 P +X A 2 100 0 70 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Electrical/Board_003/mbus_master.kicad_pcb b/Electrical/Board_003/mbus_master.kicad_pcb new file mode 100644 index 00000000..48d0c0d2 --- /dev/null +++ b/Electrical/Board_003/mbus_master.kicad_pcb @@ -0,0 +1,905 @@ +(kicad_pcb (version 4) (host pcbnew 4.0.7) + + (general + (links 22) + (no_connects 0) + (area 134.924999 74.924999 165.075001 100.075001) + (thickness 1.6) + (drawings 14) + (tracks 50) + (zones 0) + (modules 14) + (nets 11) + ) + + (page A4) + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user hide) + (49 F.Fab user hide) + ) + + (setup + (last_trace_width 0.25) + (trace_clearance 0.2) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.2) + (segment_width 0.2) + (edge_width 0.15) + (via_size 0.6) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.15) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.524 1.524) + (pad_drill 0.762) + (pad_to_mask_clearance 0.2) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x00030_80000001) + (usegerberextensions false) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15) + (hpglpenoverlay 2) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 /EXT_PWR) + (net 2 GND) + (net 3 "Net-(J1-Pad2)") + (net 4 /MBus-) + (net 5 "Net-(Q1-Pad2)") + (net 6 "Net-(Q1-Pad1)") + (net 7 "Net-(Q2-Pad2)") + (net 8 "Net-(Q2-Pad1)") + (net 9 "Net-(Q3-Pad3)") + (net 10 "Net-(D1-Pad2)") + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.6) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net /EXT_PWR) + (add_net /MBus-) + (add_net GND) + (add_net "Net-(D1-Pad2)") + (add_net "Net-(J1-Pad2)") + (add_net "Net-(Q1-Pad1)") + (add_net "Net-(Q1-Pad2)") + (add_net "Net-(Q2-Pad1)") + (add_net "Net-(Q2-Pad2)") + (add_net "Net-(Q3-Pad3)") + ) + + (module Pin_Headers:Pin_Header_Straight_1x02_Pitch1.27mm (layer F.Cu) (tedit 5A70ED90) (tstamp 5A70DE66) + (at 138.684 96.012) + (descr "Through hole straight pin header, 1x02, 1.27mm pitch, single row") + (tags "Through hole pin header THT 1x02 1.27mm single row") + (path /5A6C56AB) + (fp_text reference J1 (at -2.54 3.048) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Conn_01x02 (at 0 2.965) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.525 -0.635) (end 1.05 -0.635) (layer F.Fab) (width 0.1)) + (fp_line (start 1.05 -0.635) (end 1.05 1.905) (layer F.Fab) (width 0.1)) + (fp_line (start 1.05 1.905) (end -1.05 1.905) (layer F.Fab) (width 0.1)) + (fp_line (start -1.05 1.905) (end -1.05 -0.11) (layer F.Fab) (width 0.1)) + (fp_line (start -1.05 -0.11) (end -0.525 -0.635) (layer F.Fab) (width 0.1)) + (fp_line (start -1.11 1.965) (end -0.30753 1.965) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.30753 1.965) (end 1.11 1.965) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.11 0.76) (end -1.11 1.965) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.11 0.76) (end 1.11 1.965) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.11 0.76) (end -0.563471 0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.563471 0.76) (end 1.11 0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.11 0) (end -1.11 -0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.11 -0.76) (end 0 -0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.55 -1.15) (end -1.55 2.45) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.55 2.45) (end 1.55 2.45) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.55 2.45) (end 1.55 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.55 -1.15) (end -1.55 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0.635 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 thru_hole rect (at 0 0) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 2 GND)) + (pad 2 thru_hole oval (at 0 1.27) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 3 "Net-(J1-Pad2)")) + (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x02_Pitch1.27mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Pin_Headers:Pin_Header_Straight_1x02_Pitch1.27mm (layer F.Cu) (tedit 5A70ED53) (tstamp 5A70DE6C) + (at 148.844 77.724 90) + (descr "Through hole straight pin header, 1x02, 1.27mm pitch, single row") + (tags "Through hole pin header THT 1x02 1.27mm single row") + (path /5A6C5520) + (fp_text reference J2 (at -2.54 -2.032 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Conn_01x02 (at 0 2.965 90) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.525 -0.635) (end 1.05 -0.635) (layer F.Fab) (width 0.1)) + (fp_line (start 1.05 -0.635) (end 1.05 1.905) (layer F.Fab) (width 0.1)) + (fp_line (start 1.05 1.905) (end -1.05 1.905) (layer F.Fab) (width 0.1)) + (fp_line (start -1.05 1.905) (end -1.05 -0.11) (layer F.Fab) (width 0.1)) + (fp_line (start -1.05 -0.11) (end -0.525 -0.635) (layer F.Fab) (width 0.1)) + (fp_line (start -1.11 1.965) (end -0.30753 1.965) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.30753 1.965) (end 1.11 1.965) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.11 0.76) (end -1.11 1.965) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.11 0.76) (end 1.11 1.965) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.11 0.76) (end -0.563471 0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.563471 0.76) (end 1.11 0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.11 0) (end -1.11 -0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.11 -0.76) (end 0 -0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.55 -1.15) (end -1.55 2.45) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.55 2.45) (end 1.55 2.45) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.55 2.45) (end 1.55 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.55 -1.15) (end -1.55 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0.635 180) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 thru_hole rect (at 0 0 90) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 2 GND)) + (pad 2 thru_hole oval (at 0 1.27 90) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 1 /EXT_PWR)) + (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x02_Pitch1.27mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Pin_Headers:Pin_Header_Straight_1x02_Pitch1.27mm (layer F.Cu) (tedit 5A70EDC2) (tstamp 5A70DE72) + (at 162.052 83.82 180) + (descr "Through hole straight pin header, 1x02, 1.27mm pitch, single row") + (tags "Through hole pin header THT 1x02 1.27mm single row") + (path /5A6C5F4D) + (fp_text reference J3 (at -0.508 3.556 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Conn_01x02 (at 0 2.965 180) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.525 -0.635) (end 1.05 -0.635) (layer F.Fab) (width 0.1)) + (fp_line (start 1.05 -0.635) (end 1.05 1.905) (layer F.Fab) (width 0.1)) + (fp_line (start 1.05 1.905) (end -1.05 1.905) (layer F.Fab) (width 0.1)) + (fp_line (start -1.05 1.905) (end -1.05 -0.11) (layer F.Fab) (width 0.1)) + (fp_line (start -1.05 -0.11) (end -0.525 -0.635) (layer F.Fab) (width 0.1)) + (fp_line (start -1.11 1.965) (end -0.30753 1.965) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.30753 1.965) (end 1.11 1.965) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.11 0.76) (end -1.11 1.965) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.11 0.76) (end 1.11 1.965) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.11 0.76) (end -0.563471 0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.563471 0.76) (end 1.11 0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.11 0) (end -1.11 -0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.11 -0.76) (end 0 -0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.55 -1.15) (end -1.55 2.45) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.55 2.45) (end 1.55 2.45) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.55 2.45) (end 1.55 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.55 -1.15) (end -1.55 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0.635 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 thru_hole rect (at 0 0 180) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 4 /MBus-)) + (pad 2 thru_hole oval (at 0 1.27 180) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 1 /EXT_PWR)) + (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x02_Pitch1.27mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module TO_SOT_Packages_THT:TO-92_Molded_Narrow (layer F.Cu) (tedit 5A70ECEA) (tstamp 5A70DE79) + (at 147.32 92.964 270) + (descr "TO-92 leads molded, narrow, drill 0.6mm (see NXP sot054_po.pdf)") + (tags "to-92 sc-43 sc-43a sot54 PA33 transistor") + (path /5A6C58F3) + (fp_text reference Q1 (at 1.524 2.54 360) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value BC337 (at 1.27 2.79 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 1.27 -3.56 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.53 1.85) (end 3.07 1.85) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.5 1.75) (end 3 1.75) (layer F.Fab) (width 0.1)) + (fp_line (start -1.46 -2.73) (end 4 -2.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.46 -2.73) (end -1.46 2.01) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4 2.01) (end 4 -2.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4 2.01) (end -1.46 2.01) (layer F.CrtYd) (width 0.05)) + (fp_arc (start 1.27 0) (end 1.27 -2.48) (angle 135) (layer F.Fab) (width 0.1)) + (fp_arc (start 1.27 0) (end 1.27 -2.6) (angle -135) (layer F.SilkS) (width 0.12)) + (fp_arc (start 1.27 0) (end 1.27 -2.48) (angle -135) (layer F.Fab) (width 0.1)) + (fp_arc (start 1.27 0) (end 1.27 -2.6) (angle 135) (layer F.SilkS) (width 0.12)) + (pad 2 thru_hole circle (at 1.27 -1.27) (size 1 1) (drill 0.6) (layers *.Cu *.Mask) + (net 5 "Net-(Q1-Pad2)")) + (pad 3 thru_hole circle (at 2.54 0) (size 1 1) (drill 0.6) (layers *.Cu *.Mask) + (net 2 GND)) + (pad 1 thru_hole rect (at 0 0) (size 1 1) (drill 0.6) (layers *.Cu *.Mask) + (net 6 "Net-(Q1-Pad1)")) + (model ${KISYS3DMOD}/TO_SOT_Packages_THT.3dshapes/TO-92_Molded_Narrow.wrl + (at (xyz 0.05 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module TO_SOT_Packages_THT:TO-92_Molded_Narrow (layer F.Cu) (tedit 5A70ECF1) (tstamp 5A70DE80) + (at 147.32 86.868 270) + (descr "TO-92 leads molded, narrow, drill 0.6mm (see NXP sot054_po.pdf)") + (tags "to-92 sc-43 sc-43a sot54 PA33 transistor") + (path /5A70EDBB) + (fp_text reference Q2 (at 1.016 2.54 360) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value BC337 (at 1.27 2.79 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 1.27 -3.56 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.53 1.85) (end 3.07 1.85) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.5 1.75) (end 3 1.75) (layer F.Fab) (width 0.1)) + (fp_line (start -1.46 -2.73) (end 4 -2.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.46 -2.73) (end -1.46 2.01) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4 2.01) (end 4 -2.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4 2.01) (end -1.46 2.01) (layer F.CrtYd) (width 0.05)) + (fp_arc (start 1.27 0) (end 1.27 -2.48) (angle 135) (layer F.Fab) (width 0.1)) + (fp_arc (start 1.27 0) (end 1.27 -2.6) (angle -135) (layer F.SilkS) (width 0.12)) + (fp_arc (start 1.27 0) (end 1.27 -2.48) (angle -135) (layer F.Fab) (width 0.1)) + (fp_arc (start 1.27 0) (end 1.27 -2.6) (angle 135) (layer F.SilkS) (width 0.12)) + (pad 2 thru_hole circle (at 1.27 -1.27) (size 1 1) (drill 0.6) (layers *.Cu *.Mask) + (net 7 "Net-(Q2-Pad2)")) + (pad 3 thru_hole circle (at 2.54 0) (size 1 1) (drill 0.6) (layers *.Cu *.Mask) + (net 6 "Net-(Q1-Pad1)")) + (pad 1 thru_hole rect (at 0 0) (size 1 1) (drill 0.6) (layers *.Cu *.Mask) + (net 8 "Net-(Q2-Pad1)")) + (model ${KISYS3DMOD}/TO_SOT_Packages_THT.3dshapes/TO-92_Molded_Narrow.wrl + (at (xyz 0.05 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module TO_SOT_Packages_THT:TO-92_Molded_Narrow (layer F.Cu) (tedit 5A70ECFA) (tstamp 5A70DE87) + (at 142.748 82.804) + (descr "TO-92 leads molded, narrow, drill 0.6mm (see NXP sot054_po.pdf)") + (tags "to-92 sc-43 sc-43a sot54 PA33 transistor") + (path /5A70ED17) + (fp_text reference Q3 (at -2.54 1.016) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value BC337 (at 1.27 2.79) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 1.27 -3.56) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.53 1.85) (end 3.07 1.85) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.5 1.75) (end 3 1.75) (layer F.Fab) (width 0.1)) + (fp_line (start -1.46 -2.73) (end 4 -2.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.46 -2.73) (end -1.46 2.01) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4 2.01) (end 4 -2.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4 2.01) (end -1.46 2.01) (layer F.CrtYd) (width 0.05)) + (fp_arc (start 1.27 0) (end 1.27 -2.48) (angle 135) (layer F.Fab) (width 0.1)) + (fp_arc (start 1.27 0) (end 1.27 -2.6) (angle -135) (layer F.SilkS) (width 0.12)) + (fp_arc (start 1.27 0) (end 1.27 -2.48) (angle -135) (layer F.Fab) (width 0.1)) + (fp_arc (start 1.27 0) (end 1.27 -2.6) (angle 135) (layer F.SilkS) (width 0.12)) + (pad 2 thru_hole circle (at 1.27 -1.27 90) (size 1 1) (drill 0.6) (layers *.Cu *.Mask) + (net 8 "Net-(Q2-Pad1)")) + (pad 3 thru_hole circle (at 2.54 0 90) (size 1 1) (drill 0.6) (layers *.Cu *.Mask) + (net 9 "Net-(Q3-Pad3)")) + (pad 1 thru_hole rect (at 0 0 90) (size 1 1) (drill 0.6) (layers *.Cu *.Mask) + (net 10 "Net-(D1-Pad2)")) + (model ${KISYS3DMOD}/TO_SOT_Packages_THT.3dshapes/TO-92_Molded_Narrow.wrl + (at (xyz 0.05 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module TO_SOT_Packages_THT:TO-126_Vertical (layer F.Cu) (tedit 5A70EBE8) (tstamp 5A70DE8E) + (at 161.544 88.392 270) + (descr "TO-126, Vertical, RM 2.54mm") + (tags "TO-126 Vertical RM 2.54mm") + (path /5A6C614C) + (fp_text reference Q4 (at 7.62 0 360) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value BD136 (at 2.54 3.27 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 2.54 -3.12 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1)) + (fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1)) + (fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12)) + (fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12)) + (fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12)) + (fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05)) + (pad 1 thru_hole rect (at 0 0 270) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask) + (net 4 /MBus-)) + (pad 2 thru_hole oval (at 2.54 0 270) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask) + (net 2 GND)) + (pad 3 thru_hole oval (at 5.08 0 270) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask) + (net 10 "Net-(D1-Pad2)")) + (model ${KISYS3DMOD}/TO_SOT_Packages_THT.3dshapes/TO-126_Vertical.wrl + (at (xyz 0.1 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Diodes_THT:D_A-405_P7.62mm_Horizontal (layer F.Cu) (tedit 5A70ED77) (tstamp 5A70E314) + (at 145.796 77.724 180) + (descr "D, A-405 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf") + (tags "D A-405 series Axial Horizontal pin pitch 7.62mm length 5.2mm diameter 2.7mm") + (path /5A6C5A7F) + (fp_text reference D1 (at 5.588 -2.032 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value D_Zener_Small_ALT (at 3.81 2.41 180) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 3.81 0 180) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 1.21 -1.35) (end 1.21 1.35) (layer F.Fab) (width 0.1)) + (fp_line (start 1.21 1.35) (end 6.41 1.35) (layer F.Fab) (width 0.1)) + (fp_line (start 6.41 1.35) (end 6.41 -1.35) (layer F.Fab) (width 0.1)) + (fp_line (start 6.41 -1.35) (end 1.21 -1.35) (layer F.Fab) (width 0.1)) + (fp_line (start 0 0) (end 1.21 0) (layer F.Fab) (width 0.1)) + (fp_line (start 7.62 0) (end 6.41 0) (layer F.Fab) (width 0.1)) + (fp_line (start 1.99 -1.35) (end 1.99 1.35) (layer F.Fab) (width 0.1)) + (fp_line (start 1.15 -1.41) (end 1.15 1.41) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.15 1.41) (end 6.47 1.41) (layer F.SilkS) (width 0.12)) + (fp_line (start 6.47 1.41) (end 6.47 -1.41) (layer F.SilkS) (width 0.12)) + (fp_line (start 6.47 -1.41) (end 1.15 -1.41) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.08 0) (end 1.15 0) (layer F.SilkS) (width 0.12)) + (fp_line (start 6.54 0) (end 6.47 0) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.99 -1.41) (end 1.99 1.41) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.15 -1.7) (end -1.15 1.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.15 1.7) (end 8.8 1.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 8.8 1.7) (end 8.8 -1.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 8.8 -1.7) (end -1.15 -1.7) (layer F.CrtYd) (width 0.05)) + (pad 1 thru_hole rect (at 0 0 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask) + (net 1 /EXT_PWR)) + (pad 2 thru_hole oval (at 7.62 0 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask) + (net 10 "Net-(D1-Pad2)")) + (model ${KISYS3DMOD}/Diodes_THT.3dshapes/D_A-405_P7.62mm_Horizontal.wrl + (at (xyz 0 0 0)) + (scale (xyz 0.393701 0.393701 0.393701)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5A70EC9C) (tstamp 5A70E319) + (at 152.4 86.36 270) + (descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf") + (tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm") + (path /5A6C5956) + (fp_text reference R1 (at 4.572 2.032 360) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 1k (at 5.08 2.31 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1)) + (fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1)) + (fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12)) + (fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05)) + (pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 5 "Net-(Q1-Pad2)")) + (pad 2 thru_hole oval (at 10.16 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 3 "Net-(J1-Pad2)")) + (model ${KISYS3DMOD}/Resistors_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl + (at (xyz 0 0 0)) + (scale (xyz 0.393701 0.393701 0.393701)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5A70EC38) (tstamp 5A70E31E) + (at 138.684 82.296 270) + (descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf") + (tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm") + (path /5A70EEBF) + (fp_text reference R2 (at 5.588 2.54 360) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 6k8 (at 5.08 2.31 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1)) + (fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1)) + (fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12)) + (fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05)) + (pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 10 "Net-(D1-Pad2)")) + (pad 2 thru_hole oval (at 10.16 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 8 "Net-(Q2-Pad1)")) + (model ${KISYS3DMOD}/Resistors_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl + (at (xyz 0 0 0)) + (scale (xyz 0.393701 0.393701 0.393701)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5A70EDE0) (tstamp 5A70E323) + (at 148.336 82.296) + (descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf") + (tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm") + (path /5A70EF3B) + (fp_text reference R3 (at 6.096 2.032) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 1 (at 5.08 2.31) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1)) + (fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1)) + (fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12)) + (fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05)) + (pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 9 "Net-(Q3-Pad3)")) + (pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 7 "Net-(Q2-Pad2)")) + (model ${KISYS3DMOD}/Resistors_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl + (at (xyz 0 0 0)) + (scale (xyz 0.393701 0.393701 0.393701)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5A70EC89) (tstamp 5A70E328) + (at 142.748 86.36 270) + (descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf") + (tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm") + (path /5A70EE1E) + (fp_text reference R4 (at 8.128 2.032 360) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 150 (at 5.08 2.31 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1)) + (fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1)) + (fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12)) + (fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05)) + (pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 9 "Net-(Q3-Pad3)")) + (pad 2 thru_hole oval (at 10.16 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 6 "Net-(Q1-Pad1)")) + (model ${KISYS3DMOD}/Resistors_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl + (at (xyz 0 0 0)) + (scale (xyz 0.393701 0.393701 0.393701)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5A70ECAA) (tstamp 5A70E32D) + (at 156.464 86.36 270) + (descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf") + (tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm") + (path /5A70EB33) + (fp_text reference R5 (at 4.572 -2.54 360) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 22k (at 5.08 2.31 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1)) + (fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1)) + (fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12)) + (fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05)) + (pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 10 "Net-(D1-Pad2)")) + (pad 2 thru_hole oval (at 10.16 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 2 GND)) + (model ${KISYS3DMOD}/Resistors_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl + (at (xyz 0 0 0)) + (scale (xyz 0.393701 0.393701 0.393701)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer F.Cu) (tedit 5A70EDCD) (tstamp 5A70E332) + (at 152.908 77.724) + (descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf") + (tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm") + (path /5A70E602) + (fp_text reference R6 (at 5.08 2.54) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 220k (at 5.08 2.31) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1)) + (fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1)) + (fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12)) + (fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05)) + (pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 1 /EXT_PWR)) + (pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 4 /MBus-)) + (model ${KISYS3DMOD}/Resistors_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl + (at (xyz 0 0 0)) + (scale (xyz 0.393701 0.393701 0.393701)) + (rotate (xyz 0 0 0)) + ) + ) + + (gr_text "M-Bus\nsimulator\ntransmit only\nRev A 2018" (at 154.432 91.44) (layer B.SilkS) + (effects (font (size 1 1) (thickness 0.25)) (justify mirror)) + ) + (gr_text - (at 148.336 75.692) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (gr_text + (at 150.368 75.692) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (gr_text 24-40V (at 151.384 80.264) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.25))) + ) + (gr_text - (at 164.084 82.296) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (gr_text + (at 164.084 83.82) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (gr_text M-Bus (at 162.052 85.852) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.25))) + ) + (gr_text + (at 136.144 97.028) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (gr_text - (at 136.144 95.504) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (gr_text "TTL serial" (at 141.224 99.06) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.25))) + ) + (gr_line (start 135 75) (end 135 100) (angle 90) (layer Edge.Cuts) (width 0.15)) + (gr_line (start 135 100) (end 165 100) (angle 90) (layer Edge.Cuts) (width 0.15)) + (gr_line (start 165 75) (end 165 100) (angle 90) (layer Edge.Cuts) (width 0.15)) + (gr_line (start 135 75) (end 165 75) (angle 90) (layer Edge.Cuts) (width 0.15)) + + (segment (start 162.052 82.55) (end 162.052 81.788) (width 0.25) (layer F.Cu) (net 1)) + (segment (start 157.988 77.724) (end 152.908 77.724) (width 0.25) (layer F.Cu) (net 1) (tstamp 5A70E86C)) + (segment (start 162.052 81.788) (end 157.988 77.724) (width 0.25) (layer F.Cu) (net 1) (tstamp 5A70E868)) + (segment (start 145.796 77.724) (end 147.32 79.248) (width 0.25) (layer F.Cu) (net 1)) + (segment (start 150.114 78.994) (end 150.114 77.724) (width 0.25) (layer F.Cu) (net 1) (tstamp 5A70E85C)) + (segment (start 149.86 79.248) (end 150.114 78.994) (width 0.25) (layer F.Cu) (net 1) (tstamp 5A70E859)) + (segment (start 147.32 79.248) (end 149.86 79.248) (width 0.25) (layer F.Cu) (net 1) (tstamp 5A70E856)) + (segment (start 152.908 77.724) (end 150.114 77.724) (width 0.25) (layer F.Cu) (net 1)) + (segment (start 138.684 97.282) (end 138.938 97.282) (width 0.25) (layer F.Cu) (net 3)) + (segment (start 138.938 97.282) (end 139.7 98.044) (width 0.25) (layer F.Cu) (net 3) (tstamp 5A70E8CC)) + (segment (start 139.7 98.044) (end 150.876 98.044) (width 0.25) (layer F.Cu) (net 3) (tstamp 5A70E8D1)) + (segment (start 150.876 98.044) (end 152.4 96.52) (width 0.25) (layer F.Cu) (net 3) (tstamp 5A70E8D4)) + (segment (start 162.052 83.82) (end 162.052 87.884) (width 0.25) (layer F.Cu) (net 4)) + (segment (start 162.052 87.884) (end 161.544 88.392) (width 0.25) (layer F.Cu) (net 4) (tstamp 5A70E891)) + (segment (start 163.068 77.724) (end 163.576 78.232) (width 0.25) (layer F.Cu) (net 4)) + (segment (start 163.576 78.232) (end 163.576 82.804) (width 0.25) (layer F.Cu) (net 4) (tstamp 5A70E872)) + (segment (start 163.576 82.804) (end 162.56 83.82) (width 0.25) (layer F.Cu) (net 4) (tstamp 5A70E886)) + (segment (start 162.56 83.82) (end 162.052 83.82) (width 0.25) (layer F.Cu) (net 4) (tstamp 5A70E88A)) + (segment (start 152.4 86.36) (end 152.4 90.424) (width 0.25) (layer F.Cu) (net 5)) + (segment (start 152.4 90.424) (end 148.59 94.234) (width 0.25) (layer F.Cu) (net 5) (tstamp 5A70E8BD)) + (segment (start 147.32 92.964) (end 144.272 96.012) (width 0.25) (layer F.Cu) (net 6)) + (segment (start 144.272 96.012) (end 143.256 96.012) (width 0.25) (layer F.Cu) (net 6) (tstamp 5A70E8B0)) + (segment (start 143.256 96.012) (end 142.748 96.52) (width 0.25) (layer F.Cu) (net 6) (tstamp 5A70E8B6)) + (segment (start 147.32 89.408) (end 147.32 92.964) (width 0.25) (layer F.Cu) (net 6)) + (segment (start 158.496 82.296) (end 152.908 82.296) (width 0.25) (layer B.Cu) (net 7)) + (segment (start 149.352 87.376) (end 148.59 88.138) (width 0.25) (layer B.Cu) (net 7) (tstamp 5A70E96E)) + (segment (start 149.352 85.852) (end 149.352 87.376) (width 0.25) (layer B.Cu) (net 7) (tstamp 5A70E969)) + (segment (start 152.908 82.296) (end 149.352 85.852) (width 0.25) (layer B.Cu) (net 7) (tstamp 5A70E965)) + (segment (start 144.018 81.534) (end 146.05 81.534) (width 0.25) (layer F.Cu) (net 8)) + (segment (start 146.812 86.36) (end 147.32 86.868) (width 0.25) (layer F.Cu) (net 8) (tstamp 5A70E951)) + (segment (start 146.812 82.296) (end 146.812 86.36) (width 0.25) (layer F.Cu) (net 8) (tstamp 5A70E94A)) + (segment (start 146.05 81.534) (end 146.812 82.296) (width 0.25) (layer F.Cu) (net 8) (tstamp 5A70E946)) + (segment (start 138.684 92.456) (end 141.732 92.456) (width 0.25) (layer F.Cu) (net 8)) + (segment (start 141.732 92.456) (end 147.32 86.868) (width 0.25) (layer F.Cu) (net 8) (tstamp 5A70E8DB)) + (segment (start 145.288 82.804) (end 147.828 82.804) (width 0.25) (layer B.Cu) (net 9)) + (segment (start 147.828 82.804) (end 148.336 82.296) (width 0.25) (layer B.Cu) (net 9) (tstamp 5A70E918)) + (segment (start 142.748 86.36) (end 142.748 85.344) (width 0.25) (layer B.Cu) (net 9)) + (segment (start 142.748 85.344) (end 145.288 82.804) (width 0.25) (layer B.Cu) (net 9) (tstamp 5A70E912)) + (segment (start 142.748 82.804) (end 142.748 80.772) (width 0.25) (layer F.Cu) (net 10)) + (segment (start 150.368 80.264) (end 156.464 86.36) (width 0.25) (layer F.Cu) (net 10) (tstamp 5A70E93B)) + (segment (start 143.256 80.264) (end 150.368 80.264) (width 0.25) (layer F.Cu) (net 10) (tstamp 5A70E936)) + (segment (start 142.748 80.772) (end 143.256 80.264) (width 0.25) (layer F.Cu) (net 10) (tstamp 5A70E934)) + (segment (start 161.544 93.472) (end 160.02 93.472) (width 0.25) (layer F.Cu) (net 10)) + (segment (start 160.02 93.472) (end 158.496 91.948) (width 0.25) (layer F.Cu) (net 10) (tstamp 5A70E897)) + (segment (start 158.496 91.948) (end 158.496 88.392) (width 0.25) (layer F.Cu) (net 10) (tstamp 5A70E899)) + (segment (start 158.496 88.392) (end 156.464 86.36) (width 0.25) (layer F.Cu) (net 10) (tstamp 5A70E89C)) + (segment (start 138.684 82.296) (end 142.24 82.296) (width 0.25) (layer F.Cu) (net 10)) + (segment (start 142.24 82.296) (end 142.748 82.804) (width 0.25) (layer F.Cu) (net 10) (tstamp 5A70E841)) + (segment (start 138.176 77.724) (end 138.176 81.788) (width 0.25) (layer F.Cu) (net 10)) + (segment (start 138.176 81.788) (end 138.684 82.296) (width 0.25) (layer F.Cu) (net 10) (tstamp 5A70E83A)) + + (zone (net 2) (net_name GND) (layer B.Cu) (tstamp 5A70E999) (hatch edge 0.508) + (connect_pads (clearance 0.508)) + (min_thickness 0.254) + (fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508)) + (polygon + (pts + (xy 164.592 99.568) (xy 135.128 99.568) (xy 135.128 75.184) (xy 164.592 75.184) + ) + ) + (filled_polygon + (pts + (xy 164.29 76.977477) (xy 164.110811 76.709302) (xy 163.645264 76.398233) (xy 163.096113 76.289) (xy 163.039887 76.289) + (xy 162.490736 76.398233) (xy 162.025189 76.709302) (xy 161.71412 77.174849) (xy 161.604887 77.724) (xy 161.71412 78.273151) + (xy 162.025189 78.738698) (xy 162.490736 79.049767) (xy 163.039887 79.159) (xy 163.096113 79.159) (xy 163.645264 79.049767) + (xy 164.110811 78.738698) (xy 164.29 78.470523) (xy 164.29 99.29) (xy 135.71 99.29) (xy 135.71 97.282) + (xy 137.526764 97.282) (xy 137.613161 97.716346) (xy 137.859198 98.084566) (xy 138.227418 98.330603) (xy 138.661764 98.417) + (xy 138.706236 98.417) (xy 139.140582 98.330603) (xy 139.508802 98.084566) (xy 139.754839 97.716346) (xy 139.841236 97.282) + (xy 139.754839 96.847654) (xy 139.740917 96.826818) (xy 139.819 96.63831) (xy 139.819 96.491887) (xy 141.313 96.491887) + (xy 141.313 96.548113) (xy 141.422233 97.097264) (xy 141.733302 97.562811) (xy 142.198849 97.87388) (xy 142.748 97.983113) + (xy 143.297151 97.87388) (xy 143.762698 97.562811) (xy 144.073767 97.097264) (xy 144.183 96.548113) (xy 144.183 96.491887) + (xy 144.143659 96.294104) (xy 146.709501 96.294104) (xy 146.746648 96.509217) (xy 147.174972 96.652112) (xy 147.625375 96.620217) + (xy 147.893352 96.509217) (xy 147.896344 96.491887) (xy 150.965 96.491887) (xy 150.965 96.548113) (xy 151.074233 97.097264) + (xy 151.385302 97.562811) (xy 151.850849 97.87388) (xy 152.4 97.983113) (xy 152.949151 97.87388) (xy 153.414698 97.562811) + (xy 153.725767 97.097264) (xy 153.771163 96.869041) (xy 155.072086 96.869041) (xy 155.311611 97.375134) (xy 155.726577 97.751041) + (xy 156.114961 97.911904) (xy 156.337 97.789915) (xy 156.337 96.647) (xy 156.591 96.647) (xy 156.591 97.789915) + (xy 156.813039 97.911904) (xy 157.201423 97.751041) (xy 157.616389 97.375134) (xy 157.855914 96.869041) (xy 157.734629 96.647) + (xy 156.591 96.647) (xy 156.337 96.647) (xy 155.193371 96.647) (xy 155.072086 96.869041) (xy 153.771163 96.869041) + (xy 153.835 96.548113) (xy 153.835 96.491887) (xy 153.771164 96.170959) (xy 155.072086 96.170959) (xy 155.193371 96.393) + (xy 156.337 96.393) (xy 156.337 95.250085) (xy 156.591 95.250085) (xy 156.591 96.393) (xy 157.734629 96.393) + (xy 157.855914 96.170959) (xy 157.616389 95.664866) (xy 157.201423 95.288959) (xy 156.813039 95.128096) (xy 156.591 95.250085) + (xy 156.337 95.250085) (xy 156.114961 95.128096) (xy 155.726577 95.288959) (xy 155.311611 95.664866) (xy 155.072086 96.170959) + (xy 153.771164 96.170959) (xy 153.725767 95.942736) (xy 153.414698 95.477189) (xy 152.949151 95.16612) (xy 152.4 95.056887) + (xy 151.850849 95.16612) (xy 151.385302 95.477189) (xy 151.074233 95.942736) (xy 150.965 96.491887) (xy 147.896344 96.491887) + (xy 147.930499 96.294104) (xy 147.32 95.683605) (xy 146.709501 96.294104) (xy 144.143659 96.294104) (xy 144.073767 95.942736) + (xy 143.762698 95.477189) (xy 143.585775 95.358972) (xy 146.171888 95.358972) (xy 146.203783 95.809375) (xy 146.314783 96.077352) + (xy 146.529896 96.114499) (xy 147.140395 95.504) (xy 146.529896 94.893501) (xy 146.314783 94.930648) (xy 146.171888 95.358972) + (xy 143.585775 95.358972) (xy 143.297151 95.16612) (xy 142.748 95.056887) (xy 142.198849 95.16612) (xy 141.733302 95.477189) + (xy 141.422233 95.942736) (xy 141.313 96.491887) (xy 139.819 96.491887) (xy 139.819 96.29775) (xy 139.66025 96.139) + (xy 138.811 96.139) (xy 138.811 96.159) (xy 138.766564 96.159) (xy 138.706236 96.147) (xy 138.661764 96.147) + (xy 138.601436 96.159) (xy 138.557 96.159) (xy 138.557 96.139) (xy 137.70775 96.139) (xy 137.549 96.29775) + (xy 137.549 96.63831) (xy 137.627083 96.826818) (xy 137.613161 96.847654) (xy 137.526764 97.282) (xy 135.71 97.282) + (xy 135.71 95.38569) (xy 137.549 95.38569) (xy 137.549 95.72625) (xy 137.70775 95.885) (xy 138.557 95.885) + (xy 138.557 95.03575) (xy 138.811 95.03575) (xy 138.811 95.885) (xy 139.66025 95.885) (xy 139.819 95.72625) + (xy 139.819 95.38569) (xy 139.722327 95.152301) (xy 139.543698 94.973673) (xy 139.310309 94.877) (xy 138.96975 94.877) + (xy 138.811 95.03575) (xy 138.557 95.03575) (xy 138.39825 94.877) (xy 138.057691 94.877) (xy 137.824302 94.973673) + (xy 137.645673 95.152301) (xy 137.549 95.38569) (xy 135.71 95.38569) (xy 135.71 92.427887) (xy 137.249 92.427887) + (xy 137.249 92.484113) (xy 137.358233 93.033264) (xy 137.669302 93.498811) (xy 138.134849 93.80988) (xy 138.684 93.919113) + (xy 139.233151 93.80988) (xy 139.698698 93.498811) (xy 140.009767 93.033264) (xy 140.119 92.484113) (xy 140.119 92.464) + (xy 146.17256 92.464) (xy 146.17256 93.464) (xy 146.216838 93.699317) (xy 146.35591 93.915441) (xy 146.56811 94.060431) + (xy 146.82 94.11144) (xy 147.455106 94.11144) (xy 147.454892 94.356606) (xy 147.014625 94.387783) (xy 146.746648 94.498783) + (xy 146.709501 94.713896) (xy 147.32 95.324395) (xy 147.334143 95.310253) (xy 147.513748 95.489858) (xy 147.499605 95.504) + (xy 148.110104 96.114499) (xy 148.325217 96.077352) (xy 148.468112 95.649028) (xy 148.448273 95.368877) (xy 148.814775 95.369197) + (xy 149.232086 95.196767) (xy 149.551645 94.877765) (xy 149.724803 94.460756) (xy 149.725197 94.009225) (xy 149.552767 93.591914) + (xy 149.403043 93.441928) (xy 160.009 93.441928) (xy 160.009 93.502072) (xy 160.125845 94.089491) (xy 160.458591 94.587481) + (xy 160.956581 94.920227) (xy 161.544 95.037072) (xy 162.131419 94.920227) (xy 162.629409 94.587481) (xy 162.962155 94.089491) + (xy 163.079 93.502072) (xy 163.079 93.441928) (xy 162.962155 92.854509) (xy 162.629409 92.356519) (xy 162.391418 92.197499) + (xy 162.781966 91.839576) (xy 163.035046 91.296742) (xy 162.914997 91.059) (xy 161.671 91.059) (xy 161.671 91.079) + (xy 161.417 91.079) (xy 161.417 91.059) (xy 160.173003 91.059) (xy 160.052954 91.296742) (xy 160.306034 91.839576) + (xy 160.696582 92.197499) (xy 160.458591 92.356519) (xy 160.125845 92.854509) (xy 160.009 93.441928) (xy 149.403043 93.441928) + (xy 149.233765 93.272355) (xy 148.816756 93.099197) (xy 148.46744 93.098892) (xy 148.46744 92.464) (xy 148.423162 92.228683) + (xy 148.28409 92.012559) (xy 148.07189 91.867569) (xy 147.82 91.81656) (xy 146.82 91.81656) (xy 146.584683 91.860838) + (xy 146.368559 91.99991) (xy 146.223569 92.21211) (xy 146.17256 92.464) (xy 140.119 92.464) (xy 140.119 92.427887) + (xy 140.009767 91.878736) (xy 139.698698 91.413189) (xy 139.233151 91.10212) (xy 138.684 90.992887) (xy 138.134849 91.10212) + (xy 137.669302 91.413189) (xy 137.358233 91.878736) (xy 137.249 92.427887) (xy 135.71 92.427887) (xy 135.71 86.644187) + (xy 141.312752 86.644187) (xy 141.530757 87.1718) (xy 141.934077 87.575824) (xy 142.461309 87.79475) (xy 143.032187 87.795248) + (xy 143.5598 87.577243) (xy 143.963824 87.173923) (xy 144.18275 86.646691) (xy 144.182993 86.368) (xy 146.17256 86.368) + (xy 146.17256 87.368) (xy 146.216838 87.603317) (xy 146.35591 87.819441) (xy 146.56811 87.964431) (xy 146.82 88.01544) + (xy 147.455106 88.01544) (xy 147.454881 88.273117) (xy 147.095225 88.272803) (xy 146.677914 88.445233) (xy 146.358355 88.764235) + (xy 146.185197 89.181244) (xy 146.184803 89.632775) (xy 146.357233 90.050086) (xy 146.676235 90.369645) (xy 147.093244 90.542803) + (xy 147.544775 90.543197) (xy 147.962086 90.370767) (xy 148.281645 90.051765) (xy 148.454803 89.634756) (xy 148.455119 89.272883) + (xy 148.814775 89.273197) (xy 149.232086 89.100767) (xy 149.551645 88.781765) (xy 149.724803 88.364756) (xy 149.725053 88.077749) + (xy 149.889401 87.913401) (xy 150.054148 87.666839) (xy 150.112 87.376) (xy 150.112 86.644187) (xy 150.964752 86.644187) + (xy 151.182757 87.1718) (xy 151.586077 87.575824) (xy 152.113309 87.79475) (xy 152.684187 87.795248) (xy 153.2118 87.577243) + (xy 153.615824 87.173923) (xy 153.83475 86.646691) (xy 153.834752 86.644187) (xy 155.028752 86.644187) (xy 155.246757 87.1718) + (xy 155.650077 87.575824) (xy 156.177309 87.79475) (xy 156.748187 87.795248) (xy 157.2758 87.577243) (xy 157.361191 87.492) + (xy 159.99656 87.492) (xy 159.99656 89.292) (xy 160.040838 89.527317) (xy 160.17991 89.743441) (xy 160.39211 89.888431) + (xy 160.443146 89.898766) (xy 160.306034 90.024424) (xy 160.052954 90.567258) (xy 160.173003 90.805) (xy 161.417 90.805) + (xy 161.417 90.785) (xy 161.671 90.785) (xy 161.671 90.805) (xy 162.914997 90.805) (xy 163.035046 90.567258) + (xy 162.781966 90.024424) (xy 162.647462 89.901156) (xy 162.679317 89.895162) (xy 162.895441 89.75609) (xy 163.040431 89.54389) + (xy 163.09144 89.292) (xy 163.09144 87.492) (xy 163.047162 87.256683) (xy 162.90809 87.040559) (xy 162.69589 86.895569) + (xy 162.444 86.84456) (xy 160.644 86.84456) (xy 160.408683 86.888838) (xy 160.192559 87.02791) (xy 160.047569 87.24011) + (xy 159.99656 87.492) (xy 157.361191 87.492) (xy 157.679824 87.173923) (xy 157.89875 86.646691) (xy 157.899248 86.075813) + (xy 157.681243 85.5482) (xy 157.277923 85.144176) (xy 156.750691 84.92525) (xy 156.179813 84.924752) (xy 155.6522 85.142757) + (xy 155.248176 85.546077) (xy 155.02925 86.073309) (xy 155.028752 86.644187) (xy 153.834752 86.644187) (xy 153.835248 86.075813) + (xy 153.617243 85.5482) (xy 153.213923 85.144176) (xy 152.686691 84.92525) (xy 152.115813 84.924752) (xy 151.5882 85.142757) + (xy 151.184176 85.546077) (xy 150.96525 86.073309) (xy 150.964752 86.644187) (xy 150.112 86.644187) (xy 150.112 86.166802) + (xy 153.222802 83.056) (xy 157.283005 83.056) (xy 157.453189 83.310698) (xy 157.918736 83.621767) (xy 158.467887 83.731) + (xy 158.524113 83.731) (xy 159.073264 83.621767) (xy 159.538811 83.310698) (xy 159.84988 82.845151) (xy 159.908589 82.55) + (xy 160.894764 82.55) (xy 160.981161 82.984346) (xy 160.996805 83.007759) (xy 160.955569 83.06811) (xy 160.90456 83.32) + (xy 160.90456 84.32) (xy 160.948838 84.555317) (xy 161.08791 84.771441) (xy 161.30011 84.916431) (xy 161.552 84.96744) + (xy 162.552 84.96744) (xy 162.787317 84.923162) (xy 163.003441 84.78409) (xy 163.148431 84.57189) (xy 163.19944 84.32) + (xy 163.19944 83.32) (xy 163.155162 83.084683) (xy 163.106414 83.008927) (xy 163.122839 82.984346) (xy 163.209236 82.55) + (xy 163.122839 82.115654) (xy 162.876802 81.747434) (xy 162.508582 81.501397) (xy 162.074236 81.415) (xy 162.029764 81.415) + (xy 161.595418 81.501397) (xy 161.227198 81.747434) (xy 160.981161 82.115654) (xy 160.894764 82.55) (xy 159.908589 82.55) + (xy 159.959113 82.296) (xy 159.84988 81.746849) (xy 159.538811 81.281302) (xy 159.073264 80.970233) (xy 158.524113 80.861) + (xy 158.467887 80.861) (xy 157.918736 80.970233) (xy 157.453189 81.281302) (xy 157.283005 81.536) (xy 152.908 81.536) + (xy 152.665414 81.584254) (xy 152.61716 81.593852) (xy 152.370599 81.758599) (xy 148.814599 85.314599) (xy 148.649852 85.561161) + (xy 148.592 85.852) (xy 148.592 87.003001) (xy 148.46744 87.002892) (xy 148.46744 86.368) (xy 148.423162 86.132683) + (xy 148.28409 85.916559) (xy 148.07189 85.771569) (xy 147.82 85.72056) (xy 146.82 85.72056) (xy 146.584683 85.764838) + (xy 146.368559 85.90391) (xy 146.223569 86.11611) (xy 146.17256 86.368) (xy 144.182993 86.368) (xy 144.183248 86.075813) + (xy 143.965243 85.5482) (xy 143.792074 85.374728) (xy 145.227854 83.938948) (xy 145.512775 83.939197) (xy 145.930086 83.766767) + (xy 146.133207 83.564) (xy 147.647731 83.564) (xy 148.049309 83.73075) (xy 148.620187 83.731248) (xy 149.1478 83.513243) + (xy 149.551824 83.109923) (xy 149.77075 82.582691) (xy 149.771248 82.011813) (xy 149.553243 81.4842) (xy 149.149923 81.080176) + (xy 148.622691 80.86125) (xy 148.051813 80.860752) (xy 147.5242 81.078757) (xy 147.120176 81.482077) (xy 146.90125 82.009309) + (xy 146.90122 82.044) (xy 146.133059 82.044) (xy 145.931765 81.842355) (xy 145.514756 81.669197) (xy 145.152883 81.668881) + (xy 145.153197 81.309225) (xy 144.980767 80.891914) (xy 144.661765 80.572355) (xy 144.244756 80.399197) (xy 143.793225 80.398803) + (xy 143.375914 80.571233) (xy 143.056355 80.890235) (xy 142.883197 81.307244) (xy 142.882892 81.65656) (xy 142.248 81.65656) + (xy 142.012683 81.700838) (xy 141.796559 81.83991) (xy 141.651569 82.05211) (xy 141.60056 82.304) (xy 141.60056 83.304) + (xy 141.644838 83.539317) (xy 141.78391 83.755441) (xy 141.99611 83.900431) (xy 142.248 83.95144) (xy 143.065758 83.95144) + (xy 142.210599 84.806599) (xy 142.045852 85.053161) (xy 142.036253 85.101416) (xy 141.9362 85.142757) (xy 141.532176 85.546077) + (xy 141.31325 86.073309) (xy 141.312752 86.644187) (xy 135.71 86.644187) (xy 135.71 82.580187) (xy 137.248752 82.580187) + (xy 137.466757 83.1078) (xy 137.870077 83.511824) (xy 138.397309 83.73075) (xy 138.968187 83.731248) (xy 139.4958 83.513243) + (xy 139.899824 83.109923) (xy 140.11875 82.582691) (xy 140.119248 82.011813) (xy 139.901243 81.4842) (xy 139.497923 81.080176) + (xy 138.970691 80.86125) (xy 138.399813 80.860752) (xy 137.8722 81.078757) (xy 137.468176 81.482077) (xy 137.24925 82.009309) + (xy 137.248752 82.580187) (xy 135.71 82.580187) (xy 135.71 77.724) (xy 136.610928 77.724) (xy 136.727773 78.311419) + (xy 137.060519 78.809409) (xy 137.558509 79.142155) (xy 138.145928 79.259) (xy 138.206072 79.259) (xy 138.793491 79.142155) + (xy 139.291481 78.809409) (xy 139.624227 78.311419) (xy 139.741072 77.724) (xy 139.624227 77.136581) (xy 139.415368 76.824) + (xy 144.24856 76.824) (xy 144.24856 78.624) (xy 144.292838 78.859317) (xy 144.43191 79.075441) (xy 144.64411 79.220431) + (xy 144.896 79.27144) (xy 146.696 79.27144) (xy 146.931317 79.227162) (xy 147.147441 79.08809) (xy 147.292431 78.87589) + (xy 147.34344 78.624) (xy 147.34344 78.00975) (xy 147.709 78.00975) (xy 147.709 78.350309) (xy 147.805673 78.583698) + (xy 147.984301 78.762327) (xy 148.21769 78.859) (xy 148.55825 78.859) (xy 148.717 78.70025) (xy 148.717 77.851) + (xy 147.86775 77.851) (xy 147.709 78.00975) (xy 147.34344 78.00975) (xy 147.34344 77.097691) (xy 147.709 77.097691) + (xy 147.709 77.43825) (xy 147.86775 77.597) (xy 148.717 77.597) (xy 148.717 76.74775) (xy 148.971 76.74775) + (xy 148.971 77.597) (xy 148.991 77.597) (xy 148.991 77.641436) (xy 148.979 77.701764) (xy 148.979 77.746236) + (xy 148.991 77.806564) (xy 148.991 77.851) (xy 148.971 77.851) (xy 148.971 78.70025) (xy 149.12975 78.859) + (xy 149.47031 78.859) (xy 149.658818 78.780917) (xy 149.679654 78.794839) (xy 150.114 78.881236) (xy 150.548346 78.794839) + (xy 150.916566 78.548802) (xy 151.162603 78.180582) (xy 151.196894 78.008187) (xy 151.472752 78.008187) (xy 151.690757 78.5358) + (xy 152.094077 78.939824) (xy 152.621309 79.15875) (xy 153.192187 79.159248) (xy 153.7198 78.941243) (xy 154.123824 78.537923) + (xy 154.34275 78.010691) (xy 154.343248 77.439813) (xy 154.125243 76.9122) (xy 153.721923 76.508176) (xy 153.194691 76.28925) + (xy 152.623813 76.288752) (xy 152.0962 76.506757) (xy 151.692176 76.910077) (xy 151.47325 77.437309) (xy 151.472752 78.008187) + (xy 151.196894 78.008187) (xy 151.249 77.746236) (xy 151.249 77.701764) (xy 151.162603 77.267418) (xy 150.916566 76.899198) + (xy 150.548346 76.653161) (xy 150.114 76.566764) (xy 149.679654 76.653161) (xy 149.658818 76.667083) (xy 149.47031 76.589) + (xy 149.12975 76.589) (xy 148.971 76.74775) (xy 148.717 76.74775) (xy 148.55825 76.589) (xy 148.21769 76.589) + (xy 147.984301 76.685673) (xy 147.805673 76.864302) (xy 147.709 77.097691) (xy 147.34344 77.097691) (xy 147.34344 76.824) + (xy 147.299162 76.588683) (xy 147.16009 76.372559) (xy 146.94789 76.227569) (xy 146.696 76.17656) (xy 144.896 76.17656) + (xy 144.660683 76.220838) (xy 144.444559 76.35991) (xy 144.299569 76.57211) (xy 144.24856 76.824) (xy 139.415368 76.824) + (xy 139.291481 76.638591) (xy 138.793491 76.305845) (xy 138.206072 76.189) (xy 138.145928 76.189) (xy 137.558509 76.305845) + (xy 137.060519 76.638591) (xy 136.727773 77.136581) (xy 136.610928 77.724) (xy 135.71 77.724) (xy 135.71 75.71) + (xy 164.29 75.71) + ) + ) + ) +) diff --git a/Electrical/Board_003/mbus_master.net b/Electrical/Board_003/mbus_master.net new file mode 100644 index 00000000..07490640 --- /dev/null +++ b/Electrical/Board_003/mbus_master.net @@ -0,0 +1,233 @@ +(export (version D) + (design + (source /usr/src/hlovdal/forks-github/AmsToMqttBridge/Electrical/Board_003/mbus_master.sch) + (date "to. 01. feb. 2018 kl. 20.58 +0100") + (tool "Eeschema 4.0.7") + (sheet (number 1) (name /) (tstamps /) + (title_block + (title) + (company) + (rev) + (date) + (source mbus_master.sch) + (comment (number 1) (value "")) + (comment (number 2) (value "")) + (comment (number 3) (value "")) + (comment (number 4) (value ""))))) + (components + (comp (ref J2) + (value Conn_01x02) + (footprint Pin_Headers:Pin_Header_Straight_1x02_Pitch1.27mm) + (libsource (lib conn) (part Conn_01x02)) + (sheetpath (names /) (tstamps /)) + (tstamp 5A6C5520)) + (comp (ref J1) + (value Conn_01x02) + (footprint Pin_Headers:Pin_Header_Straight_1x02_Pitch1.27mm) + (libsource (lib conn) (part Conn_01x02)) + (sheetpath (names /) (tstamps /)) + (tstamp 5A6C56AB)) + (comp (ref Q1) + (value BC337) + (footprint TO_SOT_Packages_THT:TO-92_Molded_Narrow) + (libsource (lib transistors) (part BC337)) + (sheetpath (names /) (tstamps /)) + (tstamp 5A6C58F3)) + (comp (ref R1) + (value 1k) + (footprint Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal) + (libsource (lib device) (part R)) + (sheetpath (names /) (tstamps /)) + (tstamp 5A6C5956)) + (comp (ref D1) + (value D_Zener_Small_ALT) + (footprint Diodes_THT:D_A-405_P7.62mm_Horizontal) + (libsource (lib device) (part D_Zener_Small_ALT)) + (sheetpath (names /) (tstamps /)) + (tstamp 5A6C5A7F)) + (comp (ref J3) + (value Conn_01x02) + (footprint Pin_Headers:Pin_Header_Straight_1x02_Pitch1.27mm) + (libsource (lib conn) (part Conn_01x02)) + (sheetpath (names /) (tstamps /)) + (tstamp 5A6C5F4D)) + (comp (ref Q4) + (value BD136) + (footprint TO_SOT_Packages_THT:TO-126_Vertical) + (libsource (lib transistors) (part BD136)) + (sheetpath (names /) (tstamps /)) + (tstamp 5A6C614C)) + (comp (ref R6) + (value 220k) + (footprint Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal) + (libsource (lib device) (part R)) + (sheetpath (names /) (tstamps /)) + (tstamp 5A70E602)) + (comp (ref R5) + (value 22k) + (footprint Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal) + (libsource (lib device) (part R)) + (sheetpath (names /) (tstamps /)) + (tstamp 5A70EB33)) + (comp (ref Q3) + (value BC337) + (footprint TO_SOT_Packages_THT:TO-92_Molded_Narrow) + (libsource (lib transistors) (part BC337)) + (sheetpath (names /) (tstamps /)) + (tstamp 5A70ED17)) + (comp (ref Q2) + (value BC337) + (footprint TO_SOT_Packages_THT:TO-92_Molded_Narrow) + (libsource (lib transistors) (part BC337)) + (sheetpath (names /) (tstamps /)) + (tstamp 5A70EDBB)) + (comp (ref R4) + (value 150) + (footprint Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal) + (libsource (lib device) (part R)) + (sheetpath (names /) (tstamps /)) + (tstamp 5A70EE1E)) + (comp (ref R2) + (value 6k8) + (footprint Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal) + (libsource (lib device) (part R)) + (sheetpath (names /) (tstamps /)) + (tstamp 5A70EEBF)) + (comp (ref R3) + (value 1) + (footprint Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal) + (libsource (lib device) (part R)) + (sheetpath (names /) (tstamps /)) + (tstamp 5A70EF3B))) + (libparts + (libpart (lib transistors) (part BC547) + (aliases + (alias BC546) + (alias BC548) + (alias BC549) + (alias BC550) + (alias BC337) + (alias BC338)) + (description "45V Vce, 0.1A Ic, NPN, Small Signal Transistor, TO-92") + (docs http://www.fairchildsemi.com/ds/BC/BC547.pdf) + (footprints + (fp TO?92*)) + (fields + (field (name Reference) Q) + (field (name Value) BC547) + (field (name Footprint) TO_SOT_Packages_THT:TO-92_Molded_Narrow)) + (pins + (pin (num 1) (name C) (type passive)) + (pin (num 2) (name B) (type input)) + (pin (num 3) (name E) (type passive)))) + (libpart (lib transistors) (part BD140) + (aliases + (alias BD136) + (alias BD138) + (alias BD234) + (alias BD236) + (alias BD238)) + (description "Vce 80V, Ic 1.5A, Low Voltage Transistor, TO-126") + (docs http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00001225.pdf) + (footprints + (fp TO?126*)) + (fields + (field (name Reference) Q) + (field (name Value) BD140) + (field (name Footprint) TO_SOT_Packages_THT:TO-126_Vertical)) + (pins + (pin (num 1) (name E) (type passive)) + (pin (num 2) (name C) (type passive)) + (pin (num 3) (name B) (type input)))) + (libpart (lib conn) (part Conn_01x02) + (description "Generic connector, single row, 01x02") + (docs ~) + (footprints + (fp Connector*:*_??x*mm*) + (fp Connector*:*1x??x*mm*) + (fp Pin?Header?Straight?1X*) + (fp Pin?Header?Angled?1X*) + (fp Socket?Strip?Straight?1X*) + (fp Socket?Strip?Angled?1X*)) + (fields + (field (name Reference) J) + (field (name Value) Conn_01x02)) + (pins + (pin (num 1) (name Pin_1) (type passive)) + (pin (num 2) (name Pin_2) (type passive)))) + (libpart (lib device) (part D_Zener_Small_ALT) + (description "Zener Diode, small symbol, alternativ symbol") + (docs https://en.wikipedia.org/wiki/Zener_diode) + (footprints + (fp TO-???*) + (fp *SingleDiode) + (fp *_Diode_*) + (fp *SingleDiode*) + (fp D_*)) + (fields + (field (name Reference) D) + (field (name Value) D_Zener_Small_ALT)) + (pins + (pin (num 1) (name K) (type passive)) + (pin (num 2) (name A) (type passive)))) + (libpart (lib device) (part R) + (description Resistor) + (footprints + (fp R_*) + (fp R_*)) + (fields + (field (name Reference) R) + (field (name Value) R)) + (pins + (pin (num 1) (name ~) (type passive)) + (pin (num 2) (name ~) (type passive))))) + (libraries + (library (logical device) + (uri /usr/share/kicad/library/device.lib)) + (library (logical transistors) + (uri /usr/share/kicad/library/transistors.lib)) + (library (logical conn) + (uri /usr/share/kicad/library/conn.lib))) + (nets + (net (code 1) (name "Net-(Q2-Pad2)") + (node (ref Q2) (pin 2)) + (node (ref R3) (pin 2))) + (net (code 2) (name "Net-(Q2-Pad1)") + (node (ref Q2) (pin 1)) + (node (ref Q3) (pin 2)) + (node (ref R2) (pin 2))) + (net (code 3) (name GND) + (node (ref J2) (pin 1)) + (node (ref Q4) (pin 2)) + (node (ref J1) (pin 1)) + (node (ref Q1) (pin 3)) + (node (ref R5) (pin 2))) + (net (code 4) (name /MBus-) + (node (ref J3) (pin 1)) + (node (ref Q4) (pin 1)) + (node (ref R6) (pin 2))) + (net (code 5) (name "Net-(Q3-Pad3)") + (node (ref R3) (pin 1)) + (node (ref R4) (pin 1)) + (node (ref Q3) (pin 3))) + (net (code 6) (name "Net-(Q1-Pad1)") + (node (ref Q2) (pin 3)) + (node (ref Q1) (pin 1)) + (node (ref R4) (pin 2))) + (net (code 7) (name "Net-(J1-Pad2)") + (node (ref R1) (pin 2)) + (node (ref J1) (pin 2))) + (net (code 8) (name "Net-(Q1-Pad2)") + (node (ref Q1) (pin 2)) + (node (ref R1) (pin 1))) + (net (code 9) (name /EXT_PWR) + (node (ref R6) (pin 1)) + (node (ref D1) (pin 1)) + (node (ref J3) (pin 2)) + (node (ref J2) (pin 2))) + (net (code 10) (name "Net-(D1-Pad2)") + (node (ref Q4) (pin 3)) + (node (ref D1) (pin 2)) + (node (ref R5) (pin 1)) + (node (ref Q3) (pin 1)) + (node (ref R2) (pin 1))))) \ No newline at end of file diff --git a/Electrical/Board_003/mbus_master.pro b/Electrical/Board_003/mbus_master.pro new file mode 100644 index 00000000..8e1ff761 --- /dev/null +++ b/Electrical/Board_003/mbus_master.pro @@ -0,0 +1,63 @@ +update=lø. 27. jan. 2018 kl. 11.31 +0100 +version=1 +last_client=kicad +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=switches +LibName4=relays +LibName5=motors +LibName6=transistors +LibName7=conn +LibName8=linear +LibName9=regul +LibName10=74xx +LibName11=cmos4000 +LibName12=adc-dac +LibName13=memory +LibName14=xilinx +LibName15=microcontrollers +LibName16=dsp +LibName17=microchip +LibName18=analog_switches +LibName19=motorola +LibName20=texas +LibName21=intel +LibName22=audio +LibName23=interface +LibName24=digital-audio +LibName25=philips +LibName26=display +LibName27=cypress +LibName28=siliconi +LibName29=opto +LibName30=atmel +LibName31=contrib +LibName32=valves +[general] +version=1 diff --git a/Electrical/Board_003/mbus_master.sch b/Electrical/Board_003/mbus_master.sch new file mode 100644 index 00000000..d1a47e55 --- /dev/null +++ b/Electrical/Board_003/mbus_master.sch @@ -0,0 +1,394 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:switches +LIBS:relays +LIBS:motors +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:mbus_master-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Conn_01x02 J2 +U 1 1 5A6C5520 +P 2900 3300 +F 0 "J2" H 2900 3400 50 0000 C CNN +F 1 "Conn_01x02" H 2900 3100 50 0000 C CNN +F 2 "Pin_Headers:Pin_Header_Straight_1x02_Pitch1.27mm" H 2900 3300 50 0001 C CNN +F 3 "" H 2900 3300 50 0001 C CNN + 1 2900 3300 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 5A6C5572 +P 3600 3400 +F 0 "#PWR01" H 3600 3150 50 0001 C CNN +F 1 "GND" H 3600 3250 50 0000 C CNN +F 2 "" H 3600 3400 50 0001 C CNN +F 3 "" H 3600 3400 50 0001 C CNN + 1 3600 3400 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 5A6C558D +P 3250 3400 +F 0 "#FLG02" H 3250 3475 50 0001 C CNN +F 1 "PWR_FLAG" H 3250 3550 50 0000 C CNN +F 2 "" H 3250 3400 50 0001 C CNN +F 3 "" H 3250 3400 50 0001 C CNN + 1 3250 3400 + -1 0 0 1 +$EndComp +Wire Wire Line + 3100 3200 8450 3200 +Wire Wire Line + 3100 3300 3600 3300 +Wire Wire Line + 3600 3300 3600 3400 +Wire Wire Line + 3250 3400 3250 3300 +Connection ~ 3250 3300 +$Comp +L PWR_FLAG #FLG03 +U 1 1 5A6C5614 +P 3250 3050 +F 0 "#FLG03" H 3250 3125 50 0001 C CNN +F 1 "PWR_FLAG" H 3250 3200 50 0000 C CNN +F 2 "" H 3250 3050 50 0001 C CNN +F 3 "" H 3250 3050 50 0001 C CNN + 1 3250 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3250 3050 3250 3200 +Connection ~ 3250 3200 +Text Label 3600 3200 1 60 ~ 0 +EXT_PWR +Text Notes 2050 3350 0 60 ~ 0 +External power\n25-40V +$Comp +L Conn_01x02 J1 +U 1 1 5A6C56AB +P 2300 6800 +F 0 "J1" H 2300 6900 50 0000 C CNN +F 1 "Conn_01x02" H 2300 6600 50 0000 C CNN +F 2 "Pin_Headers:Pin_Header_Straight_1x02_Pitch1.27mm" H 2300 6800 50 0001 C CNN +F 3 "" H 2300 6800 50 0001 C CNN + 1 2300 6800 + -1 0 0 1 +$EndComp +Text Notes 1300 6800 0 60 ~ 0 +Input signal, TTL\nSendt to m-bus +$Comp +L GND #PWR04 +U 1 1 5A6C5767 +P 2650 6900 +F 0 "#PWR04" H 2650 6650 50 0001 C CNN +F 1 "GND" H 2650 6750 50 0000 C CNN +F 2 "" H 2650 6900 50 0001 C CNN +F 3 "" H 2650 6900 50 0001 C CNN + 1 2650 6900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2500 6800 2650 6800 +Wire Wire Line + 2650 6800 2650 6900 +$Comp +L BC337 Q1 +U 1 1 5A6C58F3 +P 3750 6700 +F 0 "Q1" H 3950 6775 50 0000 L CNN +F 1 "BC337" H 3950 6700 50 0000 L CNN +F 2 "TO_SOT_Packages_THT:TO-92_Molded_Narrow" H 3950 6625 50 0001 L CIN +F 3 "" H 3750 6700 50 0001 L CNN + 1 3750 6700 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5A6C5956 +P 3200 6700 +F 0 "R1" V 3280 6700 50 0000 C CNN +F 1 "1k" V 3200 6700 50 0000 C CNN +F 2 "Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" V 3130 6700 50 0001 C CNN +F 3 "" H 3200 6700 50 0001 C CNN + 1 3200 6700 + 0 1 1 0 +$EndComp +Wire Wire Line + 2500 6700 3050 6700 +Wire Wire Line + 3350 6700 3550 6700 +$Comp +L GND #PWR05 +U 1 1 5A6C59DD +P 3850 7100 +F 0 "#PWR05" H 3850 6850 50 0001 C CNN +F 1 "GND" H 3850 6950 50 0000 C CNN +F 2 "" H 3850 7100 50 0001 C CNN +F 3 "" H 3850 7100 50 0001 C CNN + 1 3850 7100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3850 6900 3850 7100 +$Comp +L D_Zener_Small_ALT D1 +U 1 1 5A6C5A7F +P 5750 3500 +F 0 "D1" H 5750 3590 50 0000 C CNN +F 1 "D_Zener_Small_ALT" H 5750 3410 50 0001 C CNN +F 2 "Diodes_THT:D_A-405_P7.62mm_Horizontal" V 5750 3500 50 0001 C CNN +F 3 "" V 5750 3500 50 0001 C CNN + 1 5750 3500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR06 +U 1 1 5A6C5BFD +P 5750 4800 +F 0 "#PWR06" H 5750 4550 50 0001 C CNN +F 1 "GND" H 5750 4650 50 0000 C CNN +F 2 "" H 5750 4800 50 0001 C CNN +F 3 "" H 5750 4800 50 0001 C CNN + 1 5750 4800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5750 4600 5750 4800 +Wire Wire Line + 5750 3200 5750 3400 +Wire Wire Line + 5750 3600 5750 4300 +Wire Wire Line + 4700 6500 3850 6500 +Wire Wire Line + 4700 4000 7250 4000 +Connection ~ 5750 4000 +$Comp +L Conn_01x02 J3 +U 1 1 5A6C5F4D +P 9000 3450 +F 0 "J3" H 9000 3550 50 0000 C CNN +F 1 "Conn_01x02" H 9000 3250 50 0000 C CNN +F 2 "Pin_Headers:Pin_Header_Straight_1x02_Pitch1.27mm" H 9000 3450 50 0001 C CNN +F 3 "" H 9000 3450 50 0001 C CNN + 1 9000 3450 + 1 0 0 1 +$EndComp +Wire Wire Line + 8800 3350 8450 3350 +Wire Wire Line + 8450 3350 8450 3200 +Connection ~ 5750 3200 +Text Label 8100 3200 0 60 ~ 0 +MBus+ +Text Label 8100 3750 0 60 ~ 0 +MBus- +$Comp +L BD136 Q4 +U 1 1 5A6C614C +P 7450 4000 +F 0 "Q4" H 7650 4075 50 0000 L CNN +F 1 "BD136" H 7650 4000 50 0000 L CNN +F 2 "TO_SOT_Packages_THT:TO-126_Vertical" H 7650 3925 50 0001 L CIN +F 3 "" H 7450 4000 50 0001 L CNN + 1 7450 4000 + 1 0 0 1 +$EndComp +Wire Wire Line + 7550 3200 7550 3350 +Connection ~ 7550 3200 +$Comp +L GND #PWR07 +U 1 1 5A6C640E +P 7550 4800 +F 0 "#PWR07" H 7550 4550 50 0001 C CNN +F 1 "GND" H 7550 4650 50 0000 C CNN +F 2 "" H 7550 4800 50 0001 C CNN +F 3 "" H 7550 4800 50 0001 C CNN + 1 7550 4800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7550 4200 7550 4800 +Wire Wire Line + 7550 3750 8450 3750 +Wire Wire Line + 8450 3750 8450 3450 +Wire Wire Line + 8450 3450 8800 3450 +Connection ~ 7550 3750 +Text Notes 9250 3450 0 60 ~ 0 +M-bus output signal +Wire Wire Line + 7550 3650 7550 3800 +Text Notes 3000 1650 0 60 ~ 0 +Schematic based on https://github.com/rscada/libmbus/blob/master/hardware/MBus_USB.pdf\nmentioned in https://electronics.stackexchange.com/a/214477/568.\n\nRemoved all Rx support. Made more robust by using a zener diode so that the voltage drop is exact and that supply voltage does not matter. +Wire Notes Line + 2900 1250 8750 1250 +Wire Notes Line + 8750 1250 8750 1800 +Wire Notes Line + 8750 1800 2900 1800 +Wire Notes Line + 2900 1800 2900 1250 +$Comp +L R R6 +U 1 1 5A70E602 +P 7550 3500 +F 0 "R6" V 7630 3500 50 0000 C CNN +F 1 "220k" V 7550 3500 50 0000 C CNN +F 2 "Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" V 7480 3500 50 0001 C CNN +F 3 "" H 7550 3500 50 0001 C CNN + 1 7550 3500 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 5A70EB33 +P 5750 4450 +F 0 "R5" V 5830 4450 50 0000 C CNN +F 1 "22k" V 5750 4450 50 0000 C CNN +F 2 "Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" V 5680 4450 50 0001 C CNN +F 3 "" H 5750 4450 50 0001 C CNN + 1 5750 4450 + 1 0 0 -1 +$EndComp +$Comp +L BC337 Q3 +U 1 1 5A70ED17 +P 4900 4800 +F 0 "Q3" H 5100 4875 50 0000 L CNN +F 1 "BC337" H 5100 4800 50 0000 L CNN +F 2 "TO_SOT_Packages_THT:TO-92_Molded_Narrow" H 5100 4725 50 0001 L CIN +F 3 "" H 4900 4800 50 0001 L CNN + 1 4900 4800 + 1 0 0 -1 +$EndComp +$Comp +L BC337 Q2 +U 1 1 5A70EDBB +P 4200 5100 +F 0 "Q2" H 4400 5175 50 0000 L CNN +F 1 "BC337" H 4400 5100 50 0000 L CNN +F 2 "TO_SOT_Packages_THT:TO-92_Molded_Narrow" H 4400 5025 50 0001 L CIN +F 3 "" H 4200 5100 50 0001 L CNN + 1 4200 5100 + -1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 5A70EE1E +P 5000 5400 +F 0 "R4" V 5080 5400 50 0000 C CNN +F 1 "150" V 5000 5400 50 0000 C CNN +F 2 "Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" V 4930 5400 50 0001 C CNN +F 3 "" H 5000 5400 50 0001 C CNN + 1 5000 5400 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5A70EEBF +P 4100 4500 +F 0 "R2" V 4180 4500 50 0000 C CNN +F 1 "6k8" V 4100 4500 50 0000 C CNN +F 2 "Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" V 4030 4500 50 0001 C CNN +F 3 "" H 4100 4500 50 0001 C CNN + 1 4100 4500 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 5A70EF3B +P 4650 5100 +F 0 "R3" V 4730 5100 50 0000 C CNN +F 1 "1" V 4650 5100 50 0000 C CNN +F 2 "Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" V 4580 5100 50 0001 C CNN +F 3 "" H 4650 5100 50 0001 C CNN + 1 4650 5100 + 0 1 1 0 +$EndComp +Wire Wire Line + 5000 5000 5000 5250 +Wire Wire Line + 4800 5100 5000 5100 +Connection ~ 5000 5100 +Wire Wire Line + 4400 5100 4500 5100 +Wire Wire Line + 4100 4650 4100 4900 +Wire Wire Line + 4700 4800 4100 4800 +Connection ~ 4100 4800 +Wire Wire Line + 4100 5300 4100 5700 +Wire Wire Line + 4100 5700 5000 5700 +Wire Wire Line + 5000 5700 5000 5550 +Connection ~ 4700 5700 +Wire Wire Line + 4100 4350 4100 4250 +Wire Wire Line + 4100 4250 5000 4250 +Wire Wire Line + 5000 4250 5000 4600 +Wire Wire Line + 4700 4000 4700 4250 +Connection ~ 4700 4250 +Wire Notes Line + 3700 4150 5300 4150 +Wire Notes Line + 5300 4150 5300 6200 +Wire Notes Line + 5300 6200 3700 6200 +Wire Notes Line + 3700 6200 3700 4150 +Text Notes 4100 6000 0 60 ~ 0 +Current limit, ca 8mA +Wire Wire Line + 4700 6500 4700 5700 +$EndSCHEMATC diff --git a/Electrical/Board_003/simulation/.gitignore b/Electrical/Board_003/simulation/.gitignore new file mode 100644 index 00000000..7090d188 --- /dev/null +++ b/Electrical/Board_003/simulation/.gitignore @@ -0,0 +1 @@ +*.dat.ngspice diff --git a/Electrical/Board_003/simulation/README.md b/Electrical/Board_003/simulation/README.md new file mode 100644 index 00000000..1a199dca --- /dev/null +++ b/Electrical/Board_003/simulation/README.md @@ -0,0 +1,11 @@ + +This directory contains various simulation of the M-Bus part of [MBus_USB.pdf](../doc/MBus_USB.pdf?raw=true). +The simulattions are done with [qucs-s](https://ra3xdh.github.io/) using [ngspice](http://ngspice.sourceforge.net) +as simulation backend. + +The first simulation is as close to the original as possible and gradulally changed to +remove receiving parts and using a zener diode to have a constant 12V voltage drop +regardless of the power supply. The final version works with any voltage in M-Bus range. + +![](mbus_master_004.png) + diff --git a/Electrical/Board_003/simulation/current_limit.png b/Electrical/Board_003/simulation/current_limit.png new file mode 100644 index 00000000..b2a3f59c Binary files /dev/null and b/Electrical/Board_003/simulation/current_limit.png differ diff --git a/Electrical/Board_003/simulation/current_limit.qucs-s.dpl b/Electrical/Board_003/simulation/current_limit.qucs-s.dpl new file mode 100644 index 00000000..6841e561 --- /dev/null +++ b/Electrical/Board_003/simulation/current_limit.qucs-s.dpl @@ -0,0 +1,33 @@ + + + + + + + + + + + + + + + + + + + + + + + + <"ngspice/current_limit:i(pr1)" #0000ff 0 3 0 0 0> + <"ngspice/current_limit:i(pr2)" #ff0000 0 3 0 0 0> + <"ngspice/current_limit:i(pr3)" #ff00ff 0 3 0 0 0> + + + <"ngspice/current_limit:v(out)" #0000ff 0 3 0 0 0> + + + + diff --git a/Electrical/Board_003/simulation/current_limit.qucs-s.sch b/Electrical/Board_003/simulation/current_limit.qucs-s.sch new file mode 100644 index 00000000..8b04ccd9 --- /dev/null +++ b/Electrical/Board_003/simulation/current_limit.qucs-s.sch @@ -0,0 +1,80 @@ + + + + + + + + + + + + + + + + + + + <_BJT BC337AP_2 1 280 210 -96 -26 1 2 "npn" 0 "3.94e-14" 0 "1" 0 "0.974" 0 "0.8" 0 "0.1" 0 "109.4" 0 "14.25" 0 "7.4e-15" 0 "1.3" 0 "3.16e-13" 0 "1.2" 0 "175" 0 "20.5" 0 "0" 0 "0" 0 "0.0539" 0 "0.1259" 0 "1.1" 0 "6.3e-11" 0 "0.75" 0 "0.33" 0 "1.58e-11" 0 "0.505" 0 "0.39" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "7.5e-10" 0 "0" 0 "0" 0 "0" 0 "8.5e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + <_BJT BC337AP_1 1 500 150 8 -26 0 0 "npn" 0 "3.94e-14" 0 "1" 0 "0.974" 0 "0.8" 0 "0.1" 0 "109.4" 0 "14.25" 0 "7.4e-15" 0 "1.3" 0 "3.16e-13" 0 "1.2" 0 "175" 0 "20.5" 0 "0" 0 "0" 0 "0.0539" 0 "0.1259" 0 "1.1" 0 "6.3e-11" 0 "0.75" 0 "0.33" 0 "1.58e-11" 0 "0.505" 0 "0.39" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "7.5e-10" 0 "0" 0 "0" 0 "0" 0 "8.5e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + + + + + + + <.DC DC1 1 30 360 0 38 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0> + <.SW SW2 0 650 230 0 61 0 0 "DC1" 1 "lin" 1 "V1" 1 "20V" 1 "40V" 1 "21" 1 "false" 0> + + + + + + + <.SW SW3 0 910 300 0 61 0 0 "DC1" 1 "lin" 1 "R5" 1 "100" 1 "10k" 1 "300" 1 "false" 0> + <.SW SW1 1 30 110 0 61 0 0 "DC1" 1 "lin" 1 "R4" 1 "30 Ohm" 1 "200 Ohm" 1 "35" 1 "false" 0> + + + + <500 180 500 210 "" 0 0 0 ""> + <500 400 500 440 "" 0 0 0 ""> + <280 240 280 300 "" 0 0 0 ""> + <280 360 280 440 "" 0 0 0 ""> + <500 -60 500 -50 "" 0 0 0 ""> + <80 -20 80 20 "" 0 0 0 ""> + <80 -150 80 -80 "" 0 0 0 ""> + <80 -150 200 -150 "" 0 0 0 ""> + <500 -150 500 -130 "" 0 0 0 ""> + <260 -150 500 -150 "" 0 0 0 ""> + <390 210 500 210 "" 0 0 0 ""> + <310 210 330 210 "" 0 0 0 ""> + <280 150 280 180 "" 0 0 0 ""> + <280 -20 500 -20 "" 0 0 0 ""> + <280 -20 280 0 "" 0 0 0 ""> + <280 60 280 150 "" 0 0 0 ""> + <500 -20 500 10 "out" 530 -40 9 ""> + <500 70 500 120 "" 0 0 0 ""> + <280 150 340 150 "" 0 0 0 ""> + <400 150 470 150 "" 0 0 0 ""> + <500 210 500 240 "" 0 0 0 ""> + <500 300 500 340 "" 0 0 0 ""> + <570 -130 570 -110 "" 0 0 0 ""> + <500 -130 500 -120 "" 0 0 0 ""> + <500 -130 570 -130 "" 0 0 0 ""> + <570 -90 570 -50 "" 0 0 0 ""> + <500 -50 500 -20 "" 0 0 0 ""> + <500 -50 570 -50 "" 0 0 0 ""> + <500 -150 500 -150 "in" 530 -180 0 ""> + + + + <"ngspice/current_limit:v(in)" #0000ff 0 3 0 0 0> + <"ngspice/current_limit:v(out)" #ff0000 0 3 0 0 0> + <"ngspice/current_limit:v(pr5)" #ff00ff 0 3 0 0 0> + + + + + diff --git a/Electrical/Board_003/simulation/mbus_master_001.qucs-s.dpl b/Electrical/Board_003/simulation/mbus_master_001.qucs-s.dpl new file mode 100644 index 00000000..be5f3111 --- /dev/null +++ b/Electrical/Board_003/simulation/mbus_master_001.qucs-s.dpl @@ -0,0 +1,40 @@ + + + + + + + + + + + + + + + + + + + + + + + + <"ngspice/mbus_master:tran.v(txd)" #0000ff 0 3 0 0 0> + <"ngspice/mbus_master:tran.v(mbusminus)" #ff0000 0 3 0 0 0> + <"ngspice/mbus_master:tran.v(mbusplus)" #ff00ff 0 3 0 0 0> + + + <"ngspice/mbus_master:tran.v(npnbase)" #0000ff 0 3 0 0 0> + <"ngspice/mbus_master:tran.v(rx)" #ff0000 0 3 0 0 0> + <"ngspice/mbus_master:tran.v(baseq1)" #ff00ff 0 3 0 0 0> + + + <"ngspice/mbus_master:tran.v(mbusminus)" #0000ff 0 3 0 0 0> + <"ngspice/mbus_master:tran.v(mbusplus)" #ff0000 0 3 0 0 0> + <"ngspice/mbus_master:tran.v(txd)" #ff00ff 0 3 0 0 0> + + + + diff --git a/Electrical/Board_003/simulation/mbus_master_001.qucs-s.sch b/Electrical/Board_003/simulation/mbus_master_001.qucs-s.sch new file mode 100644 index 00000000..6e8575d1 --- /dev/null +++ b/Electrical/Board_003/simulation/mbus_master_001.qucs-s.sch @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + <_BJT BC337AP_1 1 460 340 8 -26 0 0 "npn" 0 "3.94e-14" 0 "1" 0 "0.974" 0 "0.8" 0 "0.1" 0 "109.4" 0 "14.25" 0 "7.4e-15" 0 "1.3" 0 "3.16e-13" 0 "1.2" 0 "175" 0 "20.5" 0 "0" 0 "0" 0 "0.0539" 0 "0.1259" 0 "1.1" 0 "6.3e-11" 0 "0.75" 0 "0.33" 0 "1.58e-11" 0 "0.505" 0 "0.39" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "7.5e-10" 0 "0" 0 "0" 0 "0" 0 "8.5e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + + + + + + <_BJT BD136_138_140_1 1 900 270 8 -26 1 0 "pnp" 0 "2.9537e-13" 0 "1" 0 "1.021" 0 "1.0993" 0 "0.1" 0 "137" 0 "8.41" 0 "1.8002e-13" 0 "1.5" 0 "7.0433e-12" 0 "1.38" 0 "201.4" 0 "23.765" 0 "0.01" 0 "0.011" 0 "0.01" 0 "0.1109" 0 "1.98" 0 "2.1982e-10" 0 "0.7211" 0 "0.3685" 0 "6.8291e-11" 0 "0.5499" 0 "0.3668" 0 "0.5287" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1.4883" 0 "3" 0 "1.2343" 0 "26.85" 0 "1" 0> + + + <_BJT BC337AP_2 1 800 340 18 -26 1 2 "npn" 0 "3.94e-14" 0 "1" 0 "0.974" 0 "0.8" 0 "0.1" 0 "109.4" 0 "14.25" 0 "7.4e-15" 0 "1.3" 0 "3.16e-13" 0 "1.2" 0 "175" 0 "20.5" 0 "0" 0 "0" 0 "0.0539" 0 "0.1259" 0 "1.1" 0 "6.3e-11" 0 "0.75" 0 "0.33" 0 "1.58e-11" 0 "0.505" 0 "0.39" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "7.5e-10" 0 "0" 0 "0" 0 "0" 0 "8.5e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + + <.DC DC1 1 190 500 0 38 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0> + <.TR TR1 1 200 580 0 61 0 0 "lin" 1 "0" 1 "5 ms" 1 "101" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0> + + + + + + + + + + <200 90 200 140 "" 0 0 0 ""> + <200 90 600 90 "" 0 0 0 ""> + <200 200 200 230 "" 0 0 0 ""> + <200 400 200 420 "" 0 0 0 ""> + <200 340 310 340 "TxD" 290 310 56 ""> + <460 270 600 270 "" 0 0 0 ""> + <460 270 460 310 "" 0 0 0 ""> + <370 340 430 340 "baseq1" 380 290 22 ""> + <460 370 460 440 "" 0 0 0 ""> + <600 420 600 440 "" 0 0 0 ""> + <600 90 600 140 "" 0 0 0 ""> + <600 200 600 270 "" 0 0 0 ""> + <600 270 600 360 "" 0 0 0 ""> + <600 90 700 90 "" 0 0 0 ""> + <900 90 900 140 "mbusplus" 990 100 10 ""> + <900 200 900 240 "mbusminus" 980 200 4 ""> + <600 270 870 270 "pnpbase" 799 241 160 ""> + <900 300 900 340 "" 0 0 0 ""> + <900 420 900 440 "" 0 0 0 ""> + <700 200 700 290 "" 0 0 0 ""> + <700 400 700 440 "" 0 0 0 ""> + <900 340 900 360 "" 0 0 0 ""> + <830 340 900 340 "npnbase" 810 380 30 ""> + <800 290 800 310 "" 0 0 0 ""> + <700 290 700 340 "rx" 720 310 8 ""> + <700 290 800 290 "" 0 0 0 ""> + <700 90 900 90 "" 0 0 0 ""> + <700 90 700 140 "" 0 0 0 ""> + <420 640 420 680 "" 0 0 0 ""> + <420 540 420 580 "" 0 0 0 ""> + <420 540 480 540 "" 0 0 0 ""> + <540 540 670 540 "" 0 0 0 ""> + <670 290 670 540 "" 0 0 0 ""> + <670 290 700 290 "" 0 0 0 ""> + <800 370 800 440 "" 0 0 0 ""> + + + + <"ngspice/mbus_master:tran.v(txd)" #0000ff 0 3 0 0 0> + <"ngspice/mbus_master:tran.mbusdiff" #ff0000 0 3 0 0 0> + + + + + diff --git a/Electrical/Board_003/simulation/mbus_master_002.qucs-s.dpl b/Electrical/Board_003/simulation/mbus_master_002.qucs-s.dpl new file mode 100644 index 00000000..6ad181a3 --- /dev/null +++ b/Electrical/Board_003/simulation/mbus_master_002.qucs-s.dpl @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + <"ngspice/mbus_master_002:tran.v(mbusminus)" #0000ff 0 3 0 0 0> + <"ngspice/mbus_master_002:tran.v(txd)" #ff0000 0 3 0 0 0> + + + <"ngspice/mbus_master_002:tran.vdrop" #ff00ff 0 3 0 0 0> + + <"ngspice/mbus_master_002:tran.v(txd)" #ff0000 0 3 0 0 0> + + + + diff --git a/Electrical/Board_003/simulation/mbus_master_002.qucs-s.sch b/Electrical/Board_003/simulation/mbus_master_002.qucs-s.sch new file mode 100644 index 00000000..60f2b876 --- /dev/null +++ b/Electrical/Board_003/simulation/mbus_master_002.qucs-s.sch @@ -0,0 +1,66 @@ + + + + + + + + + + + + + + + + + + + + + + <_BJT BC337AP_1 1 460 340 8 -26 0 0 "npn" 0 "3.94e-14" 0 "1" 0 "0.974" 0 "0.8" 0 "0.1" 0 "109.4" 0 "14.25" 0 "7.4e-15" 0 "1.3" 0 "3.16e-13" 0 "1.2" 0 "175" 0 "20.5" 0 "0" 0 "0" 0 "0.0539" 0 "0.1259" 0 "1.1" 0 "6.3e-11" 0 "0.75" 0 "0.33" 0 "1.58e-11" 0 "0.505" 0 "0.39" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "7.5e-10" 0 "0" 0 "0" 0 "0" 0 "8.5e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + + + + + <_BJT BD136_138_140_1 1 900 270 8 -26 1 0 "pnp" 0 "2.9537e-13" 0 "1" 0 "1.021" 0 "1.0993" 0 "0.1" 0 "137" 0 "8.41" 0 "1.8002e-13" 0 "1.5" 0 "7.0433e-12" 0 "1.38" 0 "201.4" 0 "23.765" 0 "0.01" 0 "0.011" 0 "0.01" 0 "0.1109" 0 "1.98" 0 "2.1982e-10" 0 "0.7211" 0 "0.3685" 0 "6.8291e-11" 0 "0.5499" 0 "0.3668" 0 "0.5287" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1.4883" 0 "3" 0 "1.2343" 0 "26.85" 0 "1" 0> + + <.DC DC1 1 190 500 0 38 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0> + <.TR TR1 1 200 580 0 61 0 0 "lin" 1 "0" 1 "5 ms" 1 "101" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0> + + <.SW SW1 1 460 570 0 59 0 0 "DC1" 1 "lin" 1 "V1" 1 "34V" 1 "12V" 1 "111" 1 "false" 0> + + + + + <200 90 200 140 "" 0 0 0 ""> + <200 90 600 90 "" 0 0 0 ""> + <200 200 200 230 "" 0 0 0 ""> + <200 400 200 420 "" 0 0 0 ""> + <460 270 600 270 "" 0 0 0 ""> + <460 270 460 310 "" 0 0 0 ""> + <460 370 460 440 "" 0 0 0 ""> + <600 420 600 440 "" 0 0 0 ""> + <600 90 600 140 "" 0 0 0 ""> + <600 200 600 270 "" 0 0 0 ""> + <600 270 600 360 "" 0 0 0 ""> + <600 90 900 90 "" 0 0 0 ""> + <900 90 900 140 "mbusplus" 990 100 10 ""> + <900 200 900 240 "mbusminus" 980 200 4 ""> + <600 270 870 270 "pnpbase" 799 241 160 ""> + <900 300 900 440 "" 0 0 0 ""> + <370 340 430 340 "baseq1" 380 290 22 ""> + <200 340 310 340 "TxD" 290 310 56 ""> + + + + <"ngspice/mbus_master_002:v(mbusplus)" #0000ff 0 3 0 0 0> + <"ngspice/mbus_master_002:v(mbusminus)" #ff0000 0 3 0 0 0> + + + + + + diff --git a/Electrical/Board_003/simulation/mbus_master_003.qucs-s.dpl b/Electrical/Board_003/simulation/mbus_master_003.qucs-s.dpl new file mode 100644 index 00000000..95597e2b --- /dev/null +++ b/Electrical/Board_003/simulation/mbus_master_003.qucs-s.dpl @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + <"ngspice/mbus_master_003:tran.v(pnpbase)" #ff0000 0 3 0 0 0> + + + <"ngspice/mbus_master_003:tran.i(pr1)" #ff00ff 0 3 0 0 0> + <"ngspice/mbus_master_003:tran.i(pr2)" #ff00ff 0 3 0 0 0> + + + + diff --git a/Electrical/Board_003/simulation/mbus_master_003.qucs-s.sch b/Electrical/Board_003/simulation/mbus_master_003.qucs-s.sch new file mode 100644 index 00000000..a4f6b76b --- /dev/null +++ b/Electrical/Board_003/simulation/mbus_master_003.qucs-s.sch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + <_BJT BC337AP_1 1 460 340 8 -26 0 0 "npn" 0 "3.94e-14" 0 "1" 0 "0.974" 0 "0.8" 0 "0.1" 0 "109.4" 0 "14.25" 0 "7.4e-15" 0 "1.3" 0 "3.16e-13" 0 "1.2" 0 "175" 0 "20.5" 0 "0" 0 "0" 0 "0.0539" 0 "0.1259" 0 "1.1" 0 "6.3e-11" 0 "0.75" 0 "0.33" 0 "1.58e-11" 0 "0.505" 0 "0.39" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "7.5e-10" 0 "0" 0 "0" 0 "0" 0 "8.5e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + + <_BJT BD136_138_140_1 1 900 270 8 -26 1 0 "pnp" 0 "2.9537e-13" 0 "1" 0 "1.021" 0 "1.0993" 0 "0.1" 0 "137" 0 "8.41" 0 "1.8002e-13" 0 "1.5" 0 "7.0433e-12" 0 "1.38" 0 "201.4" 0 "23.765" 0 "0.01" 0 "0.011" 0 "0.01" 0 "0.1109" 0 "1.98" 0 "2.1982e-10" 0 "0.7211" 0 "0.3685" 0 "6.8291e-11" 0 "0.5499" 0 "0.3668" 0 "0.5287" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1.4883" 0 "3" 0 "1.2343" 0 "26.85" 0 "1" 0> + + <.DC DC1 1 190 500 0 38 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0> + <.TR TR1 1 200 580 0 61 0 0 "lin" 1 "0" 1 "5 ms" 1 "101" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0> + + <.SW SW1 1 460 570 0 59 0 0 "DC1" 1 "lin" 1 "V1" 1 "34V" 1 "12V" 1 "111" 1 "false" 0> + + + + + + + + + + + <200 90 200 140 "" 0 0 0 ""> + <200 90 600 90 "" 0 0 0 ""> + <200 200 200 230 "" 0 0 0 ""> + <200 400 200 420 "" 0 0 0 ""> + <460 270 600 270 "" 0 0 0 ""> + <460 270 460 310 "" 0 0 0 ""> + <460 370 460 440 "" 0 0 0 ""> + <900 90 900 140 "mbusplus" 990 100 10 ""> + <900 200 900 240 "mbusminus" 980 200 4 ""> + <370 340 430 340 "baseq1" 380 290 22 ""> + <200 340 310 340 "TxD" 290 310 56 ""> + <730 270 870 270 "pnpbase" 820 240 52 ""> + <900 300 900 340 "" 0 0 0 ""> + <900 400 900 440 "" 0 0 0 ""> + <600 90 900 90 "" 0 0 0 ""> + <600 90 600 160 "" 0 0 0 ""> + <600 270 670 270 "" 0 0 0 ""> + <600 220 600 270 "" 0 0 0 ""> + <600 270 600 360 "" 0 0 0 ""> + <600 420 600 440 "" 0 0 0 ""> + + + + <"ngspice/mbus_master_003:v(mbusplus)" #ff00ff 0 3 0 0 0> + <"ngspice/mbus_master_003:v(mbusminus)" #00ff00 0 3 0 0 0> + <"ngspice/mbus_master_003:v(pnpbase)" #00ffff 0 3 0 0 0> + + + + + + + diff --git a/Electrical/Board_003/simulation/mbus_master_004.png b/Electrical/Board_003/simulation/mbus_master_004.png new file mode 100644 index 00000000..102a1336 Binary files /dev/null and b/Electrical/Board_003/simulation/mbus_master_004.png differ diff --git a/Electrical/Board_003/simulation/mbus_master_004.qucs-s.dpl b/Electrical/Board_003/simulation/mbus_master_004.qucs-s.dpl new file mode 100644 index 00000000..241e6f01 --- /dev/null +++ b/Electrical/Board_003/simulation/mbus_master_004.qucs-s.dpl @@ -0,0 +1,33 @@ + + + + + + + + + + + + + + + + + + + + + + + + <"ngspice/mbus_master_004:i(pr1)" #0000ff 0 3 0 0 0> + <"ngspice/mbus_master_004:i(pr2)" #ff0000 0 3 0 0 0> + <"ngspice/mbus_master_004:i(pr4)" #00ff00 0 3 0 0 0> + + + <"ngspice/mbus_master_004:i(pr3)" #ff00ff 0 3 0 0 0> + + + + diff --git a/Electrical/Board_003/simulation/mbus_master_004.qucs-s.sch b/Electrical/Board_003/simulation/mbus_master_004.qucs-s.sch new file mode 100644 index 00000000..f9e13937 --- /dev/null +++ b/Electrical/Board_003/simulation/mbus_master_004.qucs-s.sch @@ -0,0 +1,105 @@ + + + + + + + + + + + + + + + + + + + + + + <.TR TR1 1 1330 650 0 61 0 0 "lin" 1 "0" 1 "5 ms" 1 "101" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0> + <.SW SW1 1 1540 630 0 59 0 0 "DC1" 1 "lin" 1 "V1" 1 "34V" 1 "12V" 1 "111" 1 "false" 0> + + + + + + <_BJT BC337AP_1 1 460 670 8 -26 0 0 "npn" 0 "3.94e-14" 0 "1" 0 "0.974" 0 "0.8" 0 "0.1" 0 "109.4" 0 "14.25" 0 "7.4e-15" 0 "1.3" 0 "3.16e-13" 0 "1.2" 0 "175" 0 "20.5" 0 "0" 0 "0" 0 "0.0539" 0 "0.1259" 0 "1.1" 0 "6.3e-11" 0 "0.75" 0 "0.33" 0 "1.58e-11" 0 "0.505" 0 "0.39" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "7.5e-10" 0 "0" 0 "0" 0 "0" 0 "8.5e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + <_BJT BD136_138_140_1 1 900 530 8 -26 1 0 "pnp" 0 "2.9537e-13" 0 "1" 0 "1.021" 0 "1.0993" 0 "0.1" 0 "137" 0 "8.41" 0 "1.8002e-13" 0 "1.5" 0 "7.0433e-12" 0 "1.38" 0 "201.4" 0 "23.765" 0 "0.01" 0 "0.011" 0 "0.01" 0 "0.1109" 0 "1.98" 0 "2.1982e-10" 0 "0.7211" 0 "0.3685" 0 "6.8291e-11" 0 "0.5499" 0 "0.3668" 0 "0.5287" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1.4883" 0 "3" 0 "1.2343" 0 "26.85" 0 "1" 0> + + + + <_BJT BC337AP_2 1 370 420 -96 -26 1 2 "npn" 0 "3.94e-14" 0 "1" 0 "0.974" 0 "0.8" 0 "0.1" 0 "109.4" 0 "14.25" 0 "7.4e-15" 0 "1.3" 0 "3.16e-13" 0 "1.2" 0 "175" 0 "20.5" 0 "0" 0 "0" 0 "0.0539" 0 "0.1259" 0 "1.1" 0 "6.3e-11" 0 "0.75" 0 "0.33" 0 "1.58e-11" 0 "0.505" 0 "0.39" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "7.5e-10" 0 "0" 0 "0" 0 "0" 0 "8.5e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + <_BJT BC337AP_3 1 500 370 8 -26 0 0 "npn" 0 "3.94e-14" 0 "1" 0 "0.974" 0 "0.8" 0 "0.1" 0 "109.4" 0 "14.25" 0 "7.4e-15" 0 "1.3" 0 "3.16e-13" 0 "1.2" 0 "175" 0 "20.5" 0 "0" 0 "0" 0 "0.0539" 0 "0.1259" 0 "1.1" 0 "6.3e-11" 0 "0.75" 0 "0.33" 0 "1.58e-11" 0 "0.505" 0 "0.39" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "7.5e-10" 0 "0" 0 "0" 0 "0" 0 "8.5e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + + + + + + + <.DC DC1 1 1100 560 0 38 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0> + <.SW SW2 1 1090 670 0 59 0 0 "SW1" 1 "lin" 1 "R5" 1 "1k" 1 "200k" 1 "200" 1 "false" 0> + + + <200 90 200 140 "" 0 0 0 ""> + <200 90 640 90 "" 0 0 0 ""> + <200 200 200 230 "" 0 0 0 ""> + <900 90 900 110 "mbusplus" 940 70 10 ""> + <900 690 900 810 "" 0 0 0 ""> + <200 770 200 800 "" 0 0 0 ""> + <460 700 460 800 "" 0 0 0 ""> + <350 670 430 670 "baseq1" 390 720 42 ""> + <200 670 200 710 "" 0 0 0 ""> + <200 670 290 670 "TxD" 220 610 56 ""> + <900 180 900 190 "" 0 0 0 ""> + <900 560 900 630 "" 0 0 0 ""> + <1010 110 1010 150 "" 0 0 0 ""> + <900 110 900 120 "" 0 0 0 ""> + <900 110 1010 110 "" 0 0 0 ""> + <1010 170 1010 190 "" 0 0 0 ""> + <900 190 900 500 "mbusminus" 940 240 14 ""> + <900 190 1010 190 "" 0 0 0 ""> + <460 610 460 640 "" 0 0 0 ""> + <460 520 460 550 "" 0 0 0 ""> + <370 520 460 520 "" 0 0 0 ""> + <370 450 370 520 "" 0 0 0 ""> + <370 290 430 290 "" 0 0 0 ""> + <500 290 500 340 "" 0 0 0 ""> + <370 350 370 370 "" 0 0 0 ""> + <370 370 370 390 "" 0 0 0 ""> + <370 370 470 370 "" 0 0 0 ""> + <470 420 500 420 "" 0 0 0 ""> + <400 420 410 420 "" 0 0 0 ""> + <500 500 500 520 "" 0 0 0 ""> + <500 420 500 440 "" 0 0 0 ""> + <500 400 500 420 "" 0 0 0 ""> + <460 520 500 520 "" 0 0 0 ""> + <640 530 680 530 "" 0 0 0 ""> + <740 530 870 530 "pnpbase" 790 480 42 ""> + <640 530 640 600 "" 0 0 0 ""> + <640 660 640 700 "" 0 0 0 ""> + <640 760 640 800 "" 0 0 0 ""> + <430 290 500 290 "" 0 0 0 ""> + <430 240 430 290 "" 0 0 0 ""> + <640 240 640 530 "" 0 0 0 ""> + <430 240 640 240 "" 0 0 0 ""> + <640 180 640 240 "" 0 0 0 ""> + <640 90 900 90 "" 0 0 0 ""> + <640 90 640 120 "" 0 0 0 ""> + + + + <"ngspice/mbus_master_004:v(mbusplus)" #00ff00 0 3 0 0 0> + <"ngspice/mbus_master_004:v(mbusminus)" #00ffff 0 3 0 0 0> + <"ngspice/mbus_master_004:v(vdrop)" #ff090d 0 3 0 0 0> + + + + + + diff --git a/Electrical/Board_003/simulation/minimaster_001.qucs-s.dpl b/Electrical/Board_003/simulation/minimaster_001.qucs-s.dpl new file mode 100644 index 00000000..9d96c8ae --- /dev/null +++ b/Electrical/Board_003/simulation/minimaster_001.qucs-s.dpl @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + <"ngspice/minimaster_001:tran.v(mbusminus)" #0000ff 0 3 0 0 0> + <"ngspice/minimaster_001:tran.v(mbusplus)" #ff0000 0 3 0 0 0> + <"ngspice/minimaster_001:tran.v(txd)" #ff00ff 0 3 0 0 0> + + + + diff --git a/Electrical/Board_003/simulation/minimaster_001.qucs-s.sch b/Electrical/Board_003/simulation/minimaster_001.qucs-s.sch new file mode 100644 index 00000000..a029ebfe --- /dev/null +++ b/Electrical/Board_003/simulation/minimaster_001.qucs-s.sch @@ -0,0 +1,124 @@ + + + + + + + + + + + + + + + + + + + + + + + + + <.DC DC1 1 110 260 0 37 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0> + <_BJT BC337AP_1 1 1640 330 8 -26 0 0 "npn" 0 "3.94e-14" 0 "1" 0 "0.974" 0 "0.8" 0 "0.1" 0 "109.4" 0 "14.25" 0 "7.4e-15" 0 "1.3" 0 "3.16e-13" 0 "1.2" 0 "175" 0 "20.5" 0 "0" 0 "0" 0 "0.0539" 0 "0.1259" 0 "1.1" 0 "6.3e-11" 0 "0.75" 0 "0.33" 0 "1.58e-11" 0 "0.505" 0 "0.39" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "7.5e-10" 0 "0" 0 "0" 0 "0" 0 "8.5e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + + + + + + + <_BJT BC337AP_2 1 1540 550 8 -26 0 0 "npn" 0 "3.94e-14" 0 "1" 0 "0.974" 0 "0.8" 0 "0.1" 0 "109.4" 0 "14.25" 0 "7.4e-15" 0 "1.3" 0 "3.16e-13" 0 "1.2" 0 "175" 0 "20.5" 0 "0" 0 "0" 0 "0.0539" 0 "0.1259" 0 "1.1" 0 "6.3e-11" 0 "0.75" 0 "0.33" 0 "1.58e-11" 0 "0.505" 0 "0.39" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "7.5e-10" 0 "0" 0 "0" 0 "0" 0 "8.5e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + + <.TR TR1 1 140 440 0 60 0 0 "lin" 1 "0" 1 "5 ms" 1 "101" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0> + + <_BJT BC558AP_2 1 1100 170 28 -28 0 2 "pnp" 0 "1.15e-14" 0 "0.9872" 0 "0.996" 0 "0.1" 0 "0.012" 0 "84.56" 0 "8.15" 0 "5e-14" 0 "1.4" 0 "1.43e-14" 0 "1.1" 0 "330" 0 "13" 0 "0" 0 "0" 0 "0.95" 0 "0.4" 0 "0.2" 0 "1.6e-11" 0 "0.75" 0 "0.33" 0 "1.05e-11" 0 "0.565" 0 "0.415" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "4.93e-10" 0 "0" 0 "0" 0 "0" 0 "7.355e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + + + <_BJT BC558AP_1 1 970 390 12 41 1 1 "pnp" 0 "1.15e-14" 0 "0.9872" 0 "0.996" 0 "0.1" 0 "0.012" 0 "84.56" 0 "8.15" 0 "5e-14" 0 "1.4" 0 "1.43e-14" 0 "1.1" 0 "330" 0 "13" 0 "0" 0 "0" 0 "0.95" 0 "0.4" 0 "0.2" 0 "1.6e-11" 0 "0.75" 0 "0.33" 0 "1.05e-11" 0 "0.565" 0 "0.415" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "4.93e-10" 0 "0" 0 "0" 0 "0" 0 "7.355e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + + + <_BJT BC558AP_3 1 980 270 -101 -1 0 2 "pnp" 0 "1.15e-14" 0 "0.9872" 0 "0.996" 0 "0.1" 0 "0.012" 0 "84.56" 0 "8.15" 0 "5e-14" 0 "1.4" 0 "1.43e-14" 0 "1.1" 0 "330" 0 "13" 0 "0" 0 "0" 0 "0.95" 0 "0.4" 0 "0.2" 0 "1.6e-11" 0 "0.75" 0 "0.33" 0 "1.05e-11" 0 "0.565" 0 "0.415" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "4.93e-10" 0 "0" 0 "0" 0 "0" 0 "7.355e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + + + + + <220 60 320 60 "" 0 0 0 ""> + <220 120 220 150 "" 0 0 0 ""> + <170 700 200 700 "" 0 0 0 ""> + <200 700 290 700 "" 0 0 0 ""> + <200 760 290 760 "" 0 0 0 ""> + <220 120 320 120 "" 0 0 0 ""> + <320 60 1100 60 "" 0 0 0 ""> + <290 760 400 760 "" 0 0 0 ""> + <1540 720 1540 760 "" 0 0 0 ""> + <1540 60 1540 100 "" 0 0 0 ""> + <1540 160 1540 330 "" 0 0 0 ""> + <1540 330 1610 330 "" 0 0 0 ""> + <1640 360 1640 630 "mbusplus" 1670 480 151 ""> + <1540 760 1640 760 "" 0 0 0 ""> + <1640 690 1640 760 "mbusminus" 1670 700 45 ""> + <1190 420 1190 430 "" 0 0 0 ""> + <1190 420 1240 420 "" 0 0 0 ""> + <1240 420 1240 460 "" 0 0 0 ""> + <1240 520 1240 550 "" 0 0 0 ""> + <1240 660 1240 680 "" 0 0 0 ""> + <1240 760 1540 760 "" 0 0 0 ""> + <1240 740 1240 760 "" 0 0 0 ""> + <1540 580 1540 620 "" 0 0 0 ""> + <1540 330 1540 520 "" 0 0 0 ""> + <1240 550 1240 600 "" 0 0 0 ""> + <1240 550 1510 550 "" 0 0 0 ""> + <1540 620 1540 660 "" 0 0 0 ""> + <970 760 1100 760 "" 0 0 0 ""> + <970 680 970 760 "" 0 0 0 ""> + <640 480 880 480 "" 0 0 0 ""> + <400 480 580 480 "TxD" 500 450 68 ""> + <1540 60 1640 60 "" 0 0 0 ""> + <1640 60 1640 100 "" 0 0 0 ""> + <1640 160 1640 170 "" 0 0 0 ""> + <1100 60 1540 60 "" 0 0 0 ""> + <1100 60 1100 140 "" 0 0 0 ""> + <1640 170 1640 300 "" 0 0 0 ""> + <1130 170 1640 170 "" 0 0 0 ""> + <1100 200 1100 220 "" 0 0 0 ""> + <1100 760 1240 760 "" 0 0 0 ""> + <1060 220 1100 220 "" 0 0 0 ""> + <720 220 980 220 "" 0 0 0 ""> + <540 220 660 220 "" 0 0 0 ""> + <970 420 970 480 "" 0 0 0 ""> + <1000 390 1380 390 "" 0 0 0 ""> + <1380 390 1380 410 "" 0 0 0 ""> + <1380 620 1540 620 "" 0 0 0 ""> + <1380 470 1380 620 "" 0 0 0 ""> + <880 390 940 390 "" 0 0 0 ""> + <970 480 970 620 "" 0 0 0 ""> + <880 480 970 480 "" 0 0 0 ""> + <880 460 880 480 "" 0 0 0 ""> + <880 390 880 400 "" 0 0 0 ""> + <710 390 880 390 "" 0 0 0 ""> + <1100 220 1100 270 "" 0 0 0 ""> + <1100 350 1100 360 "" 0 0 0 ""> + <980 220 1000 220 "" 0 0 0 ""> + <980 220 980 240 "" 0 0 0 ""> + <1100 270 1100 290 "" 0 0 0 ""> + <1010 270 1100 270 "" 0 0 0 ""> + <980 300 980 360 "" 0 0 0 ""> + <1100 360 1100 760 "" 0 0 0 ""> + <980 360 1100 360 "" 0 0 0 ""> + <400 540 400 580 "" 0 0 0 ""> + <400 760 970 760 "" 0 0 0 ""> + <400 640 400 760 "" 0 0 0 ""> + + + + + + diff --git a/Electrical/Board_003/simulation/minimaster_002.qucs-s.dpl b/Electrical/Board_003/simulation/minimaster_002.qucs-s.dpl new file mode 100644 index 00000000..3a1a3a7d --- /dev/null +++ b/Electrical/Board_003/simulation/minimaster_002.qucs-s.dpl @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + + + + + <"ngspice/minimaster_002:v(txd)" #0000ff 0 3 0 0 0> + + <"ngspice/minimaster_002:v(mbusplus)" #ff0000 0 3 0 0 0> + + + + + diff --git a/Electrical/Board_003/simulation/minimaster_002.qucs-s.sch b/Electrical/Board_003/simulation/minimaster_002.qucs-s.sch new file mode 100644 index 00000000..82c5eae2 --- /dev/null +++ b/Electrical/Board_003/simulation/minimaster_002.qucs-s.sch @@ -0,0 +1,102 @@ + + + + + + + + + + + + + + + + + + + + + + + + + <.DC DC1 1 110 260 0 37 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0> + <_BJT BC337AP_1 1 1640 330 8 -26 0 0 "npn" 0 "3.94e-14" 0 "1" 0 "0.974" 0 "0.8" 0 "0.1" 0 "109.4" 0 "14.25" 0 "7.4e-15" 0 "1.3" 0 "3.16e-13" 0 "1.2" 0 "175" 0 "20.5" 0 "0" 0 "0" 0 "0.0539" 0 "0.1259" 0 "1.1" 0 "6.3e-11" 0 "0.75" 0 "0.33" 0 "1.58e-11" 0 "0.505" 0 "0.39" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "7.5e-10" 0 "0" 0 "0" 0 "0" 0 "8.5e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + + + + + + + <_BJT BC337AP_2 1 1540 550 8 -26 0 0 "npn" 0 "3.94e-14" 0 "1" 0 "0.974" 0 "0.8" 0 "0.1" 0 "109.4" 0 "14.25" 0 "7.4e-15" 0 "1.3" 0 "3.16e-13" 0 "1.2" 0 "175" 0 "20.5" 0 "0" 0 "0" 0 "0.0539" 0 "0.1259" 0 "1.1" 0 "6.3e-11" 0 "0.75" 0 "0.33" 0 "1.58e-11" 0 "0.505" 0 "0.39" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "7.5e-10" 0 "0" 0 "0" 0 "0" 0 "8.5e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + + + <_BJT BC558AP_1 1 970 390 12 41 1 1 "pnp" 0 "1.15e-14" 0 "0.9872" 0 "0.996" 0 "0.1" 0 "0.012" 0 "84.56" 0 "8.15" 0 "5e-14" 0 "1.4" 0 "1.43e-14" 0 "1.1" 0 "330" 0 "13" 0 "0" 0 "0" 0 "0.95" 0 "0.4" 0 "0.2" 0 "1.6e-11" 0 "0.75" 0 "0.33" 0 "1.05e-11" 0 "0.565" 0 "0.415" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "4.93e-10" 0 "0" 0 "0" 0 "0" 0 "7.355e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + + + + <.SW SW1 1 360 180 0 59 0 0 "DC1" 1 "lin" 1 "V3" 1 "0V" 1 "7V" 1 "141" 1 "false" 0> + + + + <220 60 320 60 "" 0 0 0 ""> + <220 120 220 150 "" 0 0 0 ""> + <170 700 200 700 "" 0 0 0 ""> + <200 700 290 700 "" 0 0 0 ""> + <200 760 290 760 "" 0 0 0 ""> + <220 120 320 120 "" 0 0 0 ""> + <320 60 1540 60 "" 0 0 0 ""> + <290 760 970 760 "" 0 0 0 ""> + <1540 720 1540 760 "" 0 0 0 ""> + <1540 60 1540 100 "" 0 0 0 ""> + <1540 160 1540 330 "" 0 0 0 ""> + <1540 330 1610 330 "" 0 0 0 ""> + <1640 360 1640 630 "mbusplus" 1670 480 151 ""> + <1540 760 1640 760 "" 0 0 0 ""> + <1640 690 1640 760 "mbusminus" 1670 700 45 ""> + <1190 420 1190 430 "" 0 0 0 ""> + <1190 420 1240 420 "" 0 0 0 ""> + <1240 420 1240 460 "" 0 0 0 ""> + <1240 520 1240 550 "" 0 0 0 ""> + <1240 660 1240 680 "" 0 0 0 ""> + <1240 760 1540 760 "" 0 0 0 ""> + <1240 740 1240 760 "" 0 0 0 ""> + <1540 580 1540 620 "" 0 0 0 ""> + <1540 330 1540 520 "" 0 0 0 ""> + <1240 550 1240 600 "" 0 0 0 ""> + <1240 550 1510 550 "" 0 0 0 ""> + <1540 620 1540 660 "" 0 0 0 ""> + <970 760 1240 760 "" 0 0 0 ""> + <970 680 970 760 "" 0 0 0 ""> + <640 480 880 480 "" 0 0 0 ""> + <400 480 580 480 "TxD" 500 450 68 ""> + <1540 60 1640 60 "" 0 0 0 ""> + <1640 60 1640 100 "" 0 0 0 ""> + <1640 160 1640 300 "" 0 0 0 ""> + <970 420 970 480 "" 0 0 0 ""> + <1000 390 1380 390 "" 0 0 0 ""> + <1380 390 1380 410 "" 0 0 0 ""> + <1380 620 1540 620 "" 0 0 0 ""> + <1380 470 1380 620 "" 0 0 0 ""> + <880 390 940 390 "" 0 0 0 ""> + <970 480 970 620 "" 0 0 0 ""> + <880 480 970 480 "" 0 0 0 ""> + <880 460 880 480 "" 0 0 0 ""> + <880 390 880 400 "" 0 0 0 ""> + <710 390 880 390 "" 0 0 0 ""> + <400 540 400 580 "" 0 0 0 ""> + + + + <"ngspice/minimaster_002:v(mbusplus)" #0000ff 0 3 0 0 0> + <"ngspice/minimaster_002:v(txd)" #ff0000 0 3 0 0 0> + + + + + diff --git a/Electrical/Board_003/simulation/minimaster_003.qucs-s.dpl b/Electrical/Board_003/simulation/minimaster_003.qucs-s.dpl new file mode 100644 index 00000000..bb06e2dc --- /dev/null +++ b/Electrical/Board_003/simulation/minimaster_003.qucs-s.dpl @@ -0,0 +1,41 @@ + + + + + + + + + + + + + + + + + + + + + + + + <"ngspice/minimaster_003:v(t2base)" #0000ff 0 3 0 0 0> + + + <"ngspice/minimaster_003:v(t5base)" #0000ff 0 3 0 0 0> + + + <"ngspice/minimaster_003:v(t4base)" #0000ff 0 3 0 0 0> + <"ngspice/minimaster_003:v(t4emitter)" #ff0000 0 3 0 0 0> + + + <"ngspice/minimaster_003:i(pr2)" #0000ff 0 3 0 0 0> + + + <"ngspice/minimaster_003:i(pr1)" #0000ff 0 3 0 0 0> + + + + diff --git a/Electrical/Board_003/simulation/minimaster_003.qucs-s.sch b/Electrical/Board_003/simulation/minimaster_003.qucs-s.sch new file mode 100644 index 00000000..f94a42b8 --- /dev/null +++ b/Electrical/Board_003/simulation/minimaster_003.qucs-s.sch @@ -0,0 +1,109 @@ + + + + + + + + + + + + + + + + + + + + + + + + + <.DC DC1 1 110 260 0 37 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0> + <_BJT BC337AP_1 1 1640 330 8 -26 0 0 "npn" 0 "3.94e-14" 0 "1" 0 "0.974" 0 "0.8" 0 "0.1" 0 "109.4" 0 "14.25" 0 "7.4e-15" 0 "1.3" 0 "3.16e-13" 0 "1.2" 0 "175" 0 "20.5" 0 "0" 0 "0" 0 "0.0539" 0 "0.1259" 0 "1.1" 0 "6.3e-11" 0 "0.75" 0 "0.33" 0 "1.58e-11" 0 "0.505" 0 "0.39" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "7.5e-10" 0 "0" 0 "0" 0 "0" 0 "8.5e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + + + + + + + + + + + <_BJT BC558AP_1 1 1080 430 12 -11 1 0 "pnp" 0 "1.15e-14" 0 "0.9872" 0 "0.996" 0 "0.1" 0 "0.012" 0 "84.56" 0 "8.15" 0 "5e-14" 0 "1.4" 0 "1.43e-14" 0 "1.1" 0 "330" 0 "13" 0 "0" 0 "0" 0 "0.95" 0 "0.4" 0 "0.2" 0 "1.6e-11" 0 "0.75" 0 "0.33" 0 "1.05e-11" 0 "0.565" 0 "0.415" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "4.93e-10" 0 "0" 0 "0" 0 "0" 0 "7.355e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + + <.SW SW1 1 360 180 0 59 0 0 "DC1" 1 "lin" 1 "V3" 1 "0V" 1 "15V" 1 "301" 1 "false" 0> + + + <_BJT BC337AP_2 1 1540 450 8 -26 0 0 "npn" 0 "3.94e-14" 0 "1" 0 "0.974" 0 "0.8" 0 "0.1" 0 "109.4" 0 "14.25" 0 "7.4e-15" 0 "1.3" 0 "3.16e-13" 0 "1.2" 0 "175" 0 "20.5" 0 "0" 0 "0" 0 "0.0539" 0 "0.1259" 0 "1.1" 0 "6.3e-11" 0 "0.75" 0 "0.33" 0 "1.58e-11" 0 "0.505" 0 "0.39" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "7.5e-10" 0 "0" 0 "0" 0 "0" 0 "8.5e-08" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0" 0 "3" 0 "1.11" 0 "26.85" 0 "1" 0> + + + + <220 60 320 60 "" 0 0 0 ""> + <220 120 220 150 "" 0 0 0 ""> + <170 700 200 700 "" 0 0 0 ""> + <200 700 290 700 "" 0 0 0 ""> + <200 760 290 760 "" 0 0 0 ""> + <220 120 320 120 "" 0 0 0 ""> + <320 60 1540 60 "" 0 0 0 ""> + <290 760 700 760 "" 0 0 0 ""> + <1540 720 1540 760 "" 0 0 0 ""> + <1540 60 1540 100 "" 0 0 0 ""> + <1540 160 1540 330 "" 0 0 0 ""> + <1540 330 1610 330 "t5base" 1570 290 36 ""> + <1640 360 1640 630 "mbusplus" 1670 480 151 ""> + <1540 760 1640 760 "" 0 0 0 ""> + <1640 690 1640 760 "mbusminus" 1670 700 45 ""> + <640 480 700 480 "" 0 0 0 ""> + <400 480 580 480 "TxD" 500 450 68 ""> + <400 540 400 580 "" 0 0 0 ""> + <1540 560 1540 660 "" 0 0 0 ""> + <1420 760 1540 760 "" 0 0 0 ""> + <1420 740 1420 760 "" 0 0 0 ""> + <1420 660 1420 680 "" 0 0 0 ""> + <700 760 1420 760 "" 0 0 0 ""> + <700 640 700 760 "" 0 0 0 ""> + <1080 560 1540 560 "" 0 0 0 ""> + <1080 550 1080 560 "" 0 0 0 ""> + <700 480 700 580 "" 0 0 0 ""> + <1080 460 1080 490 "" 0 0 0 ""> + <720 380 720 400 "" 0 0 0 ""> + <720 380 880 380 "" 0 0 0 ""> + <880 380 880 400 "" 0 0 0 ""> + <1080 380 1080 400 "" 0 0 0 ""> + <880 380 1080 380 "" 0 0 0 ""> + <1640 60 1640 300 "" 0 0 0 ""> + <1540 60 1640 60 "" 0 0 0 ""> + <880 540 880 560 "" 0 0 0 ""> + <770 560 880 560 "" 0 0 0 ""> + <770 480 770 560 "" 0 0 0 ""> + <700 480 770 480 "" 0 0 0 ""> + <880 560 990 560 "" 0 0 0 ""> + <990 430 990 560 "t2base" 1020 470 70 ""> + <990 430 1050 430 "" 0 0 0 ""> + <880 460 880 480 "" 0 0 0 ""> + <1360 350 1360 380 "" 0 0 0 ""> + <1360 350 1420 350 "" 0 0 0 ""> + <1420 350 1420 370 "" 0 0 0 ""> + <1420 430 1420 450 "" 0 0 0 ""> + <1540 480 1540 560 "t4emitter" 1570 490 38 ""> + <1540 330 1540 420 "" 0 0 0 ""> + <1420 450 1510 450 "t4base" 1470 420 46 ""> + <1420 450 1420 480 "" 0 0 0 ""> + <1420 540 1420 600 "" 0 0 0 ""> + + + + <"ngspice/minimaster_002:v(mbusplus)" #0000ff 0 3 0 0 0> + <"ngspice/minimaster_002:v(txd)" #ff0000 0 3 0 0 0> + + + + + diff --git a/Electrical/Board_003/zener_not_ok.png b/Electrical/Board_003/zener_not_ok.png new file mode 100644 index 00000000..a6cf22e2 Binary files /dev/null and b/Electrical/Board_003/zener_not_ok.png differ diff --git a/Electrical/Board_003/zener_ok.png b/Electrical/Board_003/zener_ok.png new file mode 100644 index 00000000..9724fba1 Binary files /dev/null and b/Electrical/Board_003/zener_ok.png differ diff --git a/Electrical/README.md b/Electrical/README.md index c749a85b..3dd118fe 100644 --- a/Electrical/README.md +++ b/Electrical/README.md @@ -28,3 +28,13 @@ This [board design](Board_002) is a newer alternative to the original. It ### Status Unfinished, just started. + +## Board 3 + +This [board](Board_003) is a M-bus master simulator to be able to develop and +test the other boards without being dependent on having and using a real +AMS unit. + +### Status + +Implementation done.