github.com/YosysHQ.nextpnr
1
0
Fork 0
mirror of https://github.com/YosysHQ/nextpnr.git synced 2026-01-11 23:53:21 +00:00
Code Issues Releases Wiki Activity

Clean up CarryGenCell config

Browse Source
This commit is contained in:
Lofty 2025-07-01 11:06:28 +01:00
parent 9fa4bb8ba2
commit 012f78c9e3
1 changed files with 15 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
himbaechel/uarch/gatemate/pack_mult.cc
View File

@ -48,8 +48,7 @@ ZeroDriver::ZeroDriver(CellInfo *lower, CellInfo *upper, IdString name) : lower{
upper->params[id_C_O2] = Property(0b11, 2); // COMB2OUT -> OUT2
}
APassThroughCell::APassThroughCell(CellInfo *lower, CellInfo *upper, IdString name)
: lower{lower}, upper{upper}
APassThroughCell::APassThroughCell(CellInfo *lower, CellInfo *upper, IdString name) : lower{lower}, upper{upper}
{
lower->params[id_INIT_L02] = Property(LUT_D0, 4); // IN5
lower->params[id_INIT_L03] = Property(LUT_ZERO, 4); // (unused)
@ -79,10 +78,8 @@ void APassThroughCell::clean_up(Context *ctx)
NPNR_ASSERT(upper_net != nullptr);
{
bool net_is_gnd =
lower_net->name == ctx->idf("$PACKER_GND");
bool net_is_vcc =
lower_net->name == ctx->idf("$PACKER_VCC");
bool net_is_gnd = lower_net->name == ctx->idf("$PACKER_GND");
bool net_is_vcc = lower_net->name == ctx->idf("$PACKER_VCC");
if (net_is_gnd || net_is_vcc) {
lower->params[id_INIT_L02] = Property(LUT_ZERO, 4);
lower->params[id_INIT_L11] = Property(LUT_ZERO, 4);
@ -92,10 +89,8 @@ void APassThroughCell::clean_up(Context *ctx)
}
{
bool net_is_gnd =
upper_net->name == ctx->idf("$PACKER_GND");
bool net_is_vcc =
upper_net->name == ctx->idf("$PACKER_VCC");
bool net_is_gnd = upper_net->name == ctx->idf("$PACKER_GND");
bool net_is_vcc = upper_net->name == ctx->idf("$PACKER_VCC");
if (net_is_gnd || net_is_vcc) {
upper->params[id_INIT_L00] = Property(LUT_ZERO, 4);
upper->params[id_INIT_L10] = Property(net_is_vcc ? LUT_ONE : LUT_ZERO, 4);
@ -149,21 +144,19 @@ void BPassThroughCell::clean_up(Context *ctx)
}
}
CarryGenCell::CarryGenCell(CellInfo *lower, CellInfo *upper, IdString name, bool is_even_x, bool enable_cinx)
CarryGenCell::CarryGenCell(CellInfo *lower, CellInfo *upper, IdString name, bool is_odd_x, bool enable_cinx)
: lower{lower}, upper{upper}
{
// TODO: simplify AND with zero/OR with zero into something more sensical.
lower->params[id_INIT_L02] = Property(LUT_D1, 4); // PINY1
lower->params[id_INIT_L03] = Property(LUT_ZERO, 4); // (unused)
lower->params[id_INIT_L11] = Property(is_even_x ? LUT_AND : LUT_OR, 4);
lower->params[id_INIT_L20] = Property(is_even_x ? LUT_AND : LUT_OR, 4);
lower->params[id_INIT_L03] = Property(LUT_ZERO, 4); // (overriden by CIN)
lower->params[id_INIT_L11] = Property(is_odd_x ? LUT_OR : LUT_ZERO, 4);
lower->params[id_INIT_L20] = Property(is_odd_x ? LUT_OR : LUT_ZERO, 4);
lower->params[id_INIT_L30] = Property(LUT_INV_D0, 4); // OUT1 -> COMP_OUT
lower->params[id_C_FUNCTION] = Property(C_EN_CIN, 3);
upper->params[id_INIT_L00] = Property(enable_cinx ? LUT_ONE : LUT_ZERO, 4); // ???
upper->params[id_INIT_L01] = Property(LUT_D1, 4); // CINX
upper->params[id_INIT_L10] = Property(is_even_x ? LUT_AND : LUT_OR, 4);
upper->params[id_INIT_L00] = Property(LUT_ZERO, 4); // (unused)
upper->params[id_INIT_L01] = Property(enable_cinx ? LUT_D1 : LUT_ZERO, 4); // CINX
upper->params[id_INIT_L10] = Property(LUT_D1, 4);
upper->params[id_C_I2] = Property(1, 1); // CINX for L01
upper->params[id_C_I3] = Property(1, 1); // PINY1 for L02
@ -320,7 +313,7 @@ void GateMatePacker::pack_mult()
{
auto *carry_lower = create_cell_ptr(id_CPE_HALF_L, ctx->idf("%s$carry_lower", name.c_str(ctx)));
auto *carry_upper = create_cell_ptr(id_CPE_HALF_U, ctx->idf("%s$carry_upper", name.c_str(ctx)));
col.carry = CarryGenCell{carry_lower, carry_upper, name, is_even_x, carry_enable_cinx};
col.carry = CarryGenCell{carry_lower, carry_upper, name, !is_even_x, carry_enable_cinx};
}
{
@ -458,8 +451,8 @@ void GateMatePacker::pack_mult()
mult->movePortTo(ctx->idf("A[%d]", a), cpe_half, id_IN1);
// Connect A passthrough output to multiplier inputs.
auto *a_net =
ctx->createNet(ctx->idf("%s$%s$a%d_passthru", cpe_half->name.c_str(ctx), cpe_half->ports.at(id_IN1).net->name.c_str(ctx), a));
auto *a_net = ctx->createNet(ctx->idf("%s$%s$a%d_passthru", cpe_half->name.c_str(ctx),
cpe_half->ports.at(id_IN1).net->name.c_str(ctx), a));
cpe_half->connectPort(id_OUT, a_net);
// This may be GND/VCC; if so, clean it up.