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interchange: Add LIFCL-40 EVN tests

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat
2021-06-01 08:57:46 +01:00
parent 24ae205f20
commit 0426ba4e87
12 changed files with 85 additions and 4 deletions
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2
fpga_interchange/examples/tests/counter/CMakeLists.txt
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@@ -11,7 +11,7 @@ add_interchange_group_test(
add_interchange_group_test(
name counter
family ${family}
board_list lifcl17
board_list lifcl17 lifcl40evn
tcl run_nexus.tcl
sources counter.v
techmap ../../remap_nexus.v

13
fpga_interchange/examples/tests/counter/lifcl40evn.xdc Normal file
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@@ -0,0 +1,13 @@
set_property PACKAGE_PIN L13 [get_ports clk]
set_property PACKAGE_PIN G19 [get_ports rst]
set_property PACKAGE_PIN E17 [get_ports io_led[4]]
set_property PACKAGE_PIN F13 [get_ports io_led[5]]
set_property PACKAGE_PIN G13 [get_ports io_led[6]]
set_property PACKAGE_PIN F14 [get_ports io_led[7]]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]]

11
fpga_interchange/examples/tests/lut_nexus/CMakeLists.txt
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@@ -8,3 +8,14 @@ add_interchange_test(
sources lut.v
skip_dcp
)
add_interchange_test(
name lut_nexus40
family ${family}
device LIFCL-40
package CABGA400
tcl run.tcl
xdc empty.xdc
sources lut.v
skip_dcp
)

9
fpga_interchange/examples/tests/wire/CMakeLists.txt
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@@ -6,3 +6,12 @@ add_interchange_group_test(
sources wire.v
output_fasm
)
add_interchange_group_test(
name wire
family ${family}
board_list lifcl40evn
tcl run_nexus.tcl
sources wire.v
skip_dcp
)

5
fpga_interchange/examples/tests/wire/lifcl40evn.xdc Normal file
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@@ -0,0 +1,5 @@
set_property PACKAGE_PIN G19 [get_ports i]
set_property PACKAGE_PIN E17 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports i]
set_property IOSTANDARD LVCMOS33 [get_ports o]

14
fpga_interchange/examples/tests/wire/run_nexus.tcl Normal file
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@@ -0,0 +1,14 @@
yosys -import
read_verilog $::env(SOURCES)
synth_nexus -nolutram -nowidelut -nobram -noccu2 -nodsp
# opt_expr -undriven makes sure all nets are driven, if only by the $undef
# net.
opt_expr -undriven
opt_clean
setundef -zero -params
write_json $::env(OUT_JSON)