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mirror of https://github.com/YosysHQ/nextpnr.git synced 2026-05-02 22:32:35 +00:00

clangformat

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat
2024-01-12 10:09:28 +01:00
parent d00fdc8f7a
commit 2afb1f632e
11 changed files with 243 additions and 210 deletions

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@@ -185,7 +185,8 @@ template <typename R> struct BaseArch : ArchAPI<R>
return empty_if_possible<typename R::BelAttrsRangeT>();
}
virtual typename R::CellBelPinRangeT getBelPinsForCellPin(const CellInfo * /*cell_info*/, IdString pin) const override
virtual typename R::CellBelPinRangeT getBelPinsForCellPin(const CellInfo * /*cell_info*/,
IdString pin) const override
{
return return_if_match<std::array<IdString, 1>, typename R::CellBelPinRangeT>({pin});
}
@@ -314,7 +315,8 @@ template <typename R> struct BaseArch : ArchAPI<R>
};
// Delay methods
virtual bool getArcDelayOverride(const NetInfo * /*net_info*/, const PortRef &/*sink*/, DelayQuad &/*delay*/) const override
virtual bool getArcDelayOverride(const NetInfo * /*net_info*/, const PortRef & /*sink*/,
DelayQuad & /*delay*/) const override
{
return false;
}
@@ -330,15 +332,18 @@ template <typename R> struct BaseArch : ArchAPI<R>
virtual DecalXY getGroupDecal(GroupId /*group*/) const override { return DecalXY(); }
// Cell timing methods
virtual bool getCellDelay(const CellInfo * /*cell*/, IdString /*fromPort*/, IdString /*toPort*/, DelayQuad &/*delay*/) const override
virtual bool getCellDelay(const CellInfo * /*cell*/, IdString /*fromPort*/, IdString /*toPort*/,
DelayQuad & /*delay*/) const override
{
return false;
}
virtual TimingPortClass getPortTimingClass(const CellInfo * /*cell*/, IdString /*port*/, int &/*clockInfoCount*/) const override
virtual TimingPortClass getPortTimingClass(const CellInfo * /*cell*/, IdString /*port*/,
int & /*clockInfoCount*/) const override
{
return TMG_IGNORE;
}
virtual TimingClockingInfo getPortClockingInfo(const CellInfo * /*cell*/, IdString /*port*/, int /*index*/) const override
virtual TimingClockingInfo getPortClockingInfo(const CellInfo * /*cell*/, IdString /*port*/,
int /*index*/) const override
{
NPNR_ASSERT_FALSE("unreachable");
}

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@@ -34,7 +34,7 @@ class CommandHandler
{
public:
CommandHandler(int argc, char **argv);
virtual ~CommandHandler() { }
virtual ~CommandHandler() {}
int exec();
void load_json(Context *ctx, std::string filename);
@@ -45,9 +45,9 @@ class CommandHandler
virtual void setupArchContext(Context *ctx) = 0;
virtual std::unique_ptr<Context> createContext(dict<std::string, Property> &values) = 0;
virtual po::options_description getArchOptions() = 0;
virtual void validate() { }
virtual void customAfterLoad(Context * /*ctx*/) { }
virtual void customBitstream(Context * /*ctx*/) { }
virtual void validate() {}
virtual void customAfterLoad(Context * /*ctx*/) {}
virtual void customBitstream(Context * /*ctx*/) {}
void conflicting_options(const boost::program_options::variables_map &vm, const char *opt1, const char *opt2);
private:

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@@ -380,8 +380,8 @@ template <typename K, typename T, typename OPS> class dict
using iterator_category = std::forward_iterator_tag;
using value_type = std::pair<K, T>;
using difference_type = std::ptrdiff_t;
using pointer = const std::pair<K, T>*;
using reference = const std::pair<K, T>&;
using pointer = const std::pair<K, T> *;
using reference = const std::pair<K, T> &;
const_iterator() {}
const_iterator operator++()
{
@@ -413,8 +413,8 @@ template <typename K, typename T, typename OPS> class dict
using iterator_category = std::forward_iterator_tag;
using value_type = std::pair<K, T>;
using difference_type = std::ptrdiff_t;
using pointer = std::pair<K, T>*;
using reference = std::pair<K, T>&;
using pointer = std::pair<K, T> *;
using reference = std::pair<K, T> &;
iterator() {}
iterator operator++()
{
@@ -831,8 +831,8 @@ template <typename K, typename OPS> class pool
using iterator_category = std::forward_iterator_tag;
using value_type = K;
using difference_type = std::ptrdiff_t;
using pointer = const K*;
using reference = const K&;
using pointer = const K *;
using reference = const K &;
const_iterator() {}
const_iterator operator++()
{
@@ -858,8 +858,8 @@ template <typename K, typename OPS> class pool
using iterator_category = std::forward_iterator_tag;
using value_type = K;
using difference_type = std::ptrdiff_t;
using pointer = K*;
using reference = K&;
using pointer = K *;
using reference = K &;
iterator() {}
iterator operator++()
{
@@ -1068,8 +1068,8 @@ template <typename K, int offset, typename OPS> class idict
using iterator_category = std::forward_iterator_tag;
using value_type = K;
using difference_type = std::ptrdiff_t;
using pointer = const K*;
using reference = const K&;
using pointer = const K *;
using reference = const K &;
const_iterator() {}
const_iterator operator++()
{

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@@ -35,10 +35,10 @@ struct IdStringList
{
SSOArray<IdString, 4> ids;
IdStringList() : ids(1, IdString()) { }
explicit IdStringList(size_t n) : ids(n, IdString()) { }
explicit IdStringList(IdString id) : ids(1, id) { }
template <typename Tlist> explicit IdStringList(const Tlist &list) : ids(list) { }
IdStringList() : ids(1, IdString()) {}
explicit IdStringList(size_t n) : ids(n, IdString()) {}
explicit IdStringList(IdString id) : ids(1, id) {}
template <typename Tlist> explicit IdStringList(const Tlist &list) : ids(list) {}
static IdStringList parse(Context *ctx, const std::string &str);
void build_str(const Context *ctx, std::string &str) const;

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@@ -81,8 +81,8 @@ struct PortRef
struct DelayPair
{
DelayPair(){};
explicit DelayPair(delay_t delay) : min_delay(delay), max_delay(delay) { }
DelayPair(delay_t min_delay, delay_t max_delay) : min_delay(min_delay), max_delay(max_delay) { }
explicit DelayPair(delay_t delay) : min_delay(delay), max_delay(delay) {}
DelayPair(delay_t min_delay, delay_t max_delay) : min_delay(min_delay), max_delay(max_delay) {}
delay_t minDelay() const { return min_delay; }
delay_t maxDelay() const { return max_delay; }
delay_t min_delay, max_delay;
@@ -100,12 +100,14 @@ struct DelayPair
struct DelayQuad
{
DelayPair rise, fall;
DelayQuad() { }
explicit DelayQuad(delay_t delay) : rise(delay), fall(delay) { }
DelayQuad(delay_t min_delay, delay_t max_delay) : rise(min_delay, max_delay), fall(min_delay, max_delay) { }
DelayQuad(DelayPair rise, DelayPair fall) : rise(rise), fall(fall) { }
DelayQuad() {}
explicit DelayQuad(delay_t delay) : rise(delay), fall(delay) {}
DelayQuad(delay_t min_delay, delay_t max_delay) : rise(min_delay, max_delay), fall(min_delay, max_delay) {}
DelayQuad(DelayPair rise, DelayPair fall) : rise(rise), fall(fall) {}
DelayQuad(delay_t min_rise, delay_t max_rise, delay_t min_fall, delay_t max_fall)
: rise(min_rise, max_rise), fall(min_fall, max_fall) { }
: rise(min_rise, max_rise), fall(min_fall, max_fall)
{
}
delay_t minRiseDelay() const { return rise.minDelay(); }
delay_t maxRiseDelay() const { return rise.maxDelay(); }
@@ -124,7 +126,7 @@ struct ClockConstraint;
struct NetInfo : ArchNetInfo
{
explicit NetInfo(IdString name) : name(name) { }
explicit NetInfo(IdString name) : name(name) {}
IdString name, hierpath;
int32_t udata = 0;
@@ -203,14 +205,20 @@ struct PseudoCell
struct RegionPlug : PseudoCell
{
RegionPlug(Loc loc) : loc(loc) { } // 'loc' is a notional location for the placer only
RegionPlug(Loc loc) : loc(loc) {} // 'loc' is a notional location for the placer only
Loc getLocation() const override { return loc; }
WireId getPortWire(IdString port) const override { return port_wires.at(port); }
// TODO: partial reconfiguration region timing
bool getDelay(IdString /*fromPort*/, IdString /*toPort*/, DelayQuad &/*delay*/) const override { return false; }
TimingPortClass getPortTimingClass(IdString /*port*/, int &/*clockInfoCount*/) const override { return TMG_IGNORE; }
TimingClockingInfo getPortClockingInfo(IdString /*port*/, int /*index*/) const override { return TimingClockingInfo{}; }
bool getDelay(IdString /*fromPort*/, IdString /*toPort*/, DelayQuad & /*delay*/) const override { return false; }
TimingPortClass getPortTimingClass(IdString /*port*/, int & /*clockInfoCount*/) const override
{
return TMG_IGNORE;
}
TimingClockingInfo getPortClockingInfo(IdString /*port*/, int /*index*/) const override
{
return TimingClockingInfo{};
}
dict<IdString, WireId> port_wires;
Loc loc;
@@ -218,7 +226,7 @@ struct RegionPlug : PseudoCell
struct CellInfo : ArchCellInfo
{
CellInfo(Context *ctx, IdString name, IdString type) : ctx(ctx), name(name), type(type) { }
CellInfo(Context *ctx, IdString name, IdString type) : ctx(ctx), name(name), type(type) {}
Context *ctx = nullptr;
IdString name, type, hierpath;

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@@ -290,7 +290,7 @@ template <typename T1, typename T2> struct pair_wrapper
x.second = val.cast<T2>();
}
static int len(T &/*x*/) { return 2; }
static int len(T & /*x*/) { return 2; }
static iter_pair<T &, int> iter(T &x) { return iter_pair<T &, int>(boost::ref(x), 0); };
@@ -348,7 +348,7 @@ template <typename T1, typename T2, typename value_conv> struct map_pair_wrapper
x.base.first));
}
static int len(wrapped_pair &/*x*/) { return 2; }
static int len(wrapped_pair & /*x*/) { return 2; }
static iter_pair<wrapped_pair &, int> iter(wrapped_pair &x)
{
@@ -472,11 +472,11 @@ template <typename T1, typename T2> struct map_pair_wrapper_uptr
if (i >= 2 || i < 0)
KeyError();
return i == 1 ? py::cast(PythonConversion::ContextualWrapper<V &>(x.ctx, *x.base.second.get()))
: py::cast(PythonConversion::string_converter<decltype(x.base.first)>().to_str(x.ctx,
x.base.first));
: py::cast(PythonConversion::string_converter<decltype(x.base.first)>().to_str(x.ctx,
x.base.first));
}
static int len(wrapped_pair &/*x*/) { return 2; }
static int len(wrapped_pair & /*x*/) { return 2; }
static iter_pair<wrapped_pair &, int> iter(wrapped_pair &x)
{

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@@ -35,7 +35,7 @@ template <typename T> struct ContextualWrapper
Context *ctx;
T base;
inline ContextualWrapper(Context *c, T x) : ctx(c), base(x) { }
inline ContextualWrapper(Context *c, T x) : ctx(c), base(x) {}
inline operator T() { return base; }
typedef T base_type;

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@@ -24,7 +24,7 @@ NEXTPNR_NAMESPACE_BEGIN
struct TimingOptCfg
{
TimingOptCfg(Context * /*ctx*/) { }
TimingOptCfg(Context * /*ctx*/) {}
// The timing optimiser will *only* optimise cells of these types
// Normally these would only be logic cells (or tiles if applicable), the algorithm makes little sense