From 3eda1edec883ae639ee75c18dc00a2c7f8038f0e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 20 Jun 2025 12:40:12 +0200 Subject: [PATCH] Fixes --- himbaechel/uarch/gatemate/pack.cc | 4 +--- himbaechel/uarch/gatemate/pack_cpe.cc | 13 ++++--------- himbaechel/uarch/gatemate/route_clock.cc | 2 +- 3 files changed, 6 insertions(+), 13 deletions(-) diff --git a/himbaechel/uarch/gatemate/pack.cc b/himbaechel/uarch/gatemate/pack.cc index 1ef541b6..23931844 100644 --- a/himbaechel/uarch/gatemate/pack.cc +++ b/himbaechel/uarch/gatemate/pack.cc @@ -84,7 +84,6 @@ CellInfo *GateMatePacker::move_ram_o(CellInfo *cell, IdString origPort, bool pla } else { cpe_loc = uarch->getRelativeConstraint(fixed, origPort); BelId b = ctx->getBelByLocation(cpe_loc); - printf("CPE_L2T4 %d,%d,%d\n",cpe_loc.x, cpe_loc.y, cpe_loc.z); ctx->bindBel(b, cpe_half, PlaceStrength::STRENGTH_FIXED); } if (net->name == ctx->id("$PACKER_GND")) { @@ -108,7 +107,6 @@ CellInfo *GateMatePacker::move_ram_o(CellInfo *cell, IdString origPort, bool pla cpe_ramio->constr_z = +4; } else { cpe_loc.z += 4; - printf("CPE_RAMIO %d,%d,%d\n",cpe_loc.x, cpe_loc.y, cpe_loc.z); BelId b = ctx->getBelByLocation(cpe_loc); ctx->bindBel(b, cpe_ramio, PlaceStrength::STRENGTH_FIXED); } @@ -169,7 +167,7 @@ CellInfo *GateMatePacker::move_ram_io(CellInfo *cell, IdString iPort, IdString o cell->movePortTo(oPort, cpe_half, id_IN1); } cpe_half->params[id_INIT_L10] = Property(0b1010, 4); - cpe_half->params[id_C_O] = Property(0b11, 2); + //cpe_half->params[id_C_O] = Property(0b11, 2); cpe_half->params[id_C_RAM_O] = Property(1, 1); NetInfo *ram_o = ctx->createNet(ctx->idf("%s$ram_o", cpe_half->name.c_str(ctx))); diff --git a/himbaechel/uarch/gatemate/pack_cpe.cc b/himbaechel/uarch/gatemate/pack_cpe.cc index d3c778d5..62d60538 100644 --- a/himbaechel/uarch/gatemate/pack_cpe.cc +++ b/himbaechel/uarch/gatemate/pack_cpe.cc @@ -279,19 +279,14 @@ void GateMatePacker::pack_cpe() } for (auto &cell : dff_list) { CellInfo &ci = *cell; - printf("1\n"); CellInfo *lt = create_cell_ptr(id_CPE_LT, ctx->idf("%s$lt", ci.name.c_str(ctx))); lt->cluster = ci.name; lt->constr_abs_z = false; lt->constr_z = -2; ci.cluster = ci.name; ci.constr_children.push_back(lt); - printf("2\n"); ci.renamePort(id_Q, id_DOUT); NetInfo *d_net = ci.getPort(id_D); -printf("3\n"); - if (!d_net) - printf("NULL\n"); if (d_net->name == ctx->id("$PACKER_GND")) { lt->params[id_INIT_L00] = Property(0b0000, 4); ci.disconnectPort(id_D); @@ -301,17 +296,17 @@ printf("3\n"); } else { lt->params[id_INIT_L00] = Property(0b1010, 4); } -printf("4\n"); - ci.params[id_INIT_L10] = Property(0b1010, 4); + lt->params[id_INIT_L10] = Property(0b1010, 4); ci.movePortTo(id_D, lt, id_IN1); dff_to_cpe(&ci); -printf("5\n"); ci.type = id_CPE_FF; NetInfo *conn = ctx->createNet(ctx->idf("%s$di", ci.name.c_str(ctx))); lt->connectPort(id_OUT, conn); + ci.ports[id_DIN].name = id_DIN; + ci.ports[id_DIN].type = PORT_IN; ci.connectPort(id_DIN, conn); -printf("6\n"); } + dff_list.clear(); } static bool is_addf_ci(NetInfo *net) diff --git a/himbaechel/uarch/gatemate/route_clock.cc b/himbaechel/uarch/gatemate/route_clock.cc index bc8427fb..4179736d 100644 --- a/himbaechel/uarch/gatemate/route_clock.cc +++ b/himbaechel/uarch/gatemate/route_clock.cc @@ -49,7 +49,7 @@ void GateMateImpl::route_clock() auto reserved_wires = dict{}; auto feeds_clk_port = [](PortRef &port) { - return port.cell->type.in(id_CPE_LT, id_CPE_LT_L, id_CPE_LT_U) && port.port.in(id_CLK); + return port.cell->type.in(id_CPE_FF, id_CPE_FF_L, id_CPE_FF_U) && port.port.in(id_CLK); }; auto feeds_ddr_port = [&](NetInfo *net, PortRef &port) {