mirror of
https://github.com/YosysHQ/nextpnr.git
synced 2026-05-03 06:38:34 +00:00
Split up common into kernel,place,route
Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat
428
common/kernel/context.cc
Normal file
428
common/kernel/context.cc
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@@ -0,0 +1,428 @@
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "context.h"
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#include "log.h"
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#include "nextpnr_namespaces.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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WireId Context::getNetinfoSourceWire(const NetInfo *net_info) const
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{
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if (net_info->driver.cell == nullptr)
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return WireId();
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auto src_bel = net_info->driver.cell->bel;
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if (src_bel == BelId())
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return WireId();
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auto bel_pins = getBelPinsForCellPin(net_info->driver.cell, net_info->driver.port);
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auto iter = bel_pins.begin();
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if (iter == bel_pins.end())
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return WireId();
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WireId driver = getBelPinWire(src_bel, *iter);
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++iter;
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NPNR_ASSERT(iter == bel_pins.end()); // assert there is only one driver bel pin;
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return driver;
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}
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SSOArray<WireId, 2> Context::getNetinfoSinkWires(const NetInfo *net_info, const PortRef &user_info) const
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{
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auto dst_bel = user_info.cell->bel;
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if (dst_bel == BelId())
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return SSOArray<WireId, 2>(0, WireId());
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size_t bel_pin_count = 0;
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// We use an SSOArray here because it avoids any heap allocation for the 99.9% case of 1 or 2 sink wires
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// but as SSOArray doesn't (currently) support resizing to keep things simple it does mean we have to do
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// two loops
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for (auto s : getBelPinsForCellPin(user_info.cell, user_info.port)) {
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(void)s; // unused
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++bel_pin_count;
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}
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SSOArray<WireId, 2> result(bel_pin_count, WireId());
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bel_pin_count = 0;
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for (auto pin : getBelPinsForCellPin(user_info.cell, user_info.port)) {
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result[bel_pin_count++] = getBelPinWire(dst_bel, pin);
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}
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return result;
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}
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size_t Context::getNetinfoSinkWireCount(const NetInfo *net_info, const PortRef &sink) const
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{
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size_t count = 0;
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for (auto s : getNetinfoSinkWires(net_info, sink)) {
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(void)s; // unused
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++count;
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}
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return count;
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}
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WireId Context::getNetinfoSinkWire(const NetInfo *net_info, const PortRef &sink, size_t phys_idx) const
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{
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size_t count = 0;
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for (auto s : getNetinfoSinkWires(net_info, sink)) {
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if (count == phys_idx)
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return s;
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++count;
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}
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/* TODO: This should be an assertion failure, but for the zero-wire case of unplaced sinks; legacy code currently
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assumes WireId Remove once the refactoring process is complete.
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*/
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return WireId();
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}
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delay_t Context::predictArcDelay(const NetInfo *net_info, const PortRef &sink) const
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{
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if (net_info->driver.cell == nullptr || net_info->driver.cell->bel == BelId() || sink.cell->bel == BelId())
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return 0;
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IdString driver_pin, sink_pin;
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// Pick the first pin for a prediction; assume all will be similar enouhg
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for (auto pin : getBelPinsForCellPin(net_info->driver.cell, net_info->driver.port)) {
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driver_pin = pin;
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break;
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}
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for (auto pin : getBelPinsForCellPin(sink.cell, sink.port)) {
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sink_pin = pin;
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break;
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}
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if (driver_pin == IdString() || sink_pin == IdString())
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return 0;
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return predictDelay(net_info->driver.cell->bel, driver_pin, sink.cell->bel, sink_pin);
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}
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delay_t Context::getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &user_info) const
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{
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#ifdef ARCH_ECP5
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if (net_info->is_global)
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return 0;
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#endif
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if (net_info->wires.empty())
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return predictArcDelay(net_info, user_info);
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WireId src_wire = getNetinfoSourceWire(net_info);
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if (src_wire == WireId())
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return 0;
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delay_t max_delay = 0;
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for (auto dst_wire : getNetinfoSinkWires(net_info, user_info)) {
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WireId cursor = dst_wire;
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delay_t delay = 0;
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while (cursor != WireId() && cursor != src_wire) {
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auto it = net_info->wires.find(cursor);
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if (it == net_info->wires.end())
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break;
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PipId pip = it->second.pip;
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if (pip == PipId())
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break;
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delay += getPipDelay(pip).maxDelay();
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delay += getWireDelay(cursor).maxDelay();
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cursor = getPipSrcWire(pip);
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}
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if (cursor == src_wire)
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max_delay = std::max(max_delay, delay + getWireDelay(src_wire).maxDelay()); // routed
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else
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max_delay = std::max(max_delay, predictArcDelay(net_info, user_info)); // unrouted
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}
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return max_delay;
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}
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static uint32_t xorshift32(uint32_t x)
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{
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x ^= x << 13;
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x ^= x >> 17;
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x ^= x << 5;
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return x;
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}
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uint32_t Context::checksum() const
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{
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uint32_t cksum = xorshift32(123456789);
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uint32_t cksum_nets_sum = 0;
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for (auto &it : nets) {
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auto &ni = *it.second;
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uint32_t x = 123456789;
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x = xorshift32(x + xorshift32(it.first.index));
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x = xorshift32(x + xorshift32(ni.name.index));
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if (ni.driver.cell)
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x = xorshift32(x + xorshift32(ni.driver.cell->name.index));
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x = xorshift32(x + xorshift32(ni.driver.port.index));
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x = xorshift32(x + xorshift32(getDelayChecksum(ni.driver.budget)));
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for (auto &u : ni.users) {
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if (u.cell)
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x = xorshift32(x + xorshift32(u.cell->name.index));
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x = xorshift32(x + xorshift32(u.port.index));
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x = xorshift32(x + xorshift32(getDelayChecksum(u.budget)));
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}
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uint32_t attr_x_sum = 0;
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for (auto &a : ni.attrs) {
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uint32_t attr_x = 123456789;
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attr_x = xorshift32(attr_x + xorshift32(a.first.index));
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for (char ch : a.second.str)
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attr_x = xorshift32(attr_x + xorshift32((int)ch));
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attr_x_sum += attr_x;
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}
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x = xorshift32(x + xorshift32(attr_x_sum));
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uint32_t wire_x_sum = 0;
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for (auto &w : ni.wires) {
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uint32_t wire_x = 123456789;
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wire_x = xorshift32(wire_x + xorshift32(getWireChecksum(w.first)));
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wire_x = xorshift32(wire_x + xorshift32(getPipChecksum(w.second.pip)));
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wire_x = xorshift32(wire_x + xorshift32(int(w.second.strength)));
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wire_x_sum += wire_x;
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}
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x = xorshift32(x + xorshift32(wire_x_sum));
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cksum_nets_sum += x;
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}
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cksum = xorshift32(cksum + xorshift32(cksum_nets_sum));
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uint32_t cksum_cells_sum = 0;
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for (auto &it : cells) {
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auto &ci = *it.second;
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uint32_t x = 123456789;
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x = xorshift32(x + xorshift32(it.first.index));
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x = xorshift32(x + xorshift32(ci.name.index));
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x = xorshift32(x + xorshift32(ci.type.index));
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uint32_t port_x_sum = 0;
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for (auto &p : ci.ports) {
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uint32_t port_x = 123456789;
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port_x = xorshift32(port_x + xorshift32(p.first.index));
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port_x = xorshift32(port_x + xorshift32(p.second.name.index));
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if (p.second.net)
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port_x = xorshift32(port_x + xorshift32(p.second.net->name.index));
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port_x = xorshift32(port_x + xorshift32(p.second.type));
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port_x_sum += port_x;
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}
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x = xorshift32(x + xorshift32(port_x_sum));
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uint32_t attr_x_sum = 0;
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for (auto &a : ci.attrs) {
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uint32_t attr_x = 123456789;
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attr_x = xorshift32(attr_x + xorshift32(a.first.index));
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for (char ch : a.second.str)
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attr_x = xorshift32(attr_x + xorshift32((int)ch));
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attr_x_sum += attr_x;
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}
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x = xorshift32(x + xorshift32(attr_x_sum));
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uint32_t param_x_sum = 0;
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for (auto &p : ci.params) {
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uint32_t param_x = 123456789;
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param_x = xorshift32(param_x + xorshift32(p.first.index));
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for (char ch : p.second.str)
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param_x = xorshift32(param_x + xorshift32((int)ch));
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param_x_sum += param_x;
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}
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x = xorshift32(x + xorshift32(param_x_sum));
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x = xorshift32(x + xorshift32(getBelChecksum(ci.bel)));
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x = xorshift32(x + xorshift32(ci.belStrength));
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cksum_cells_sum += x;
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}
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cksum = xorshift32(cksum + xorshift32(cksum_cells_sum));
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return cksum;
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}
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void Context::check() const
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{
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bool check_failed = false;
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#define CHECK_FAIL(...) \
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do { \
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log_nonfatal_error(__VA_ARGS__); \
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check_failed = true; \
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} while (false)
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for (auto &n : nets) {
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auto ni = n.second.get();
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if (n.first != ni->name)
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CHECK_FAIL("net key '%s' not equal to name '%s'\n", nameOf(n.first), nameOf(ni->name));
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for (auto &w : ni->wires) {
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if (ni != getBoundWireNet(w.first))
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CHECK_FAIL("net '%s' not bound to wire '%s' in wires map\n", nameOf(n.first), nameOfWire(w.first));
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if (w.second.pip != PipId()) {
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if (w.first != getPipDstWire(w.second.pip))
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CHECK_FAIL("net '%s' has dest mismatch '%s' vs '%s' in for pip '%s'\n", nameOf(n.first),
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nameOfWire(w.first), nameOfWire(getPipDstWire(w.second.pip)), nameOfPip(w.second.pip));
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if (ni != getBoundPipNet(w.second.pip))
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CHECK_FAIL("net '%s' not bound to pip '%s' in wires map\n", nameOf(n.first),
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nameOfPip(w.second.pip));
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}
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}
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if (ni->driver.cell != nullptr) {
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if (!ni->driver.cell->ports.count(ni->driver.port)) {
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CHECK_FAIL("net '%s' driver port '%s' missing on cell '%s'\n", nameOf(n.first), nameOf(ni->driver.port),
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nameOf(ni->driver.cell));
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} else {
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const NetInfo *p_net = ni->driver.cell->ports.at(ni->driver.port).net;
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if (p_net != ni)
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CHECK_FAIL("net '%s' driver port '%s.%s' connected to incorrect net '%s'\n", nameOf(n.first),
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nameOf(ni->driver.cell), nameOf(ni->driver.port), p_net ? nameOf(p_net) : "<nullptr>");
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}
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}
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for (auto user : ni->users) {
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if (!user.cell->ports.count(user.port)) {
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CHECK_FAIL("net '%s' user port '%s' missing on cell '%s'\n", nameOf(n.first), nameOf(user.port),
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nameOf(user.cell));
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} else {
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const NetInfo *p_net = user.cell->ports.at(user.port).net;
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if (p_net != ni)
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CHECK_FAIL("net '%s' user port '%s.%s' connected to incorrect net '%s'\n", nameOf(n.first),
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nameOf(user.cell), nameOf(user.port), p_net ? nameOf(p_net) : "<nullptr>");
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}
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}
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}
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#ifdef CHECK_WIRES
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for (auto w : getWires()) {
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auto ni = getBoundWireNet(w);
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if (ni != nullptr) {
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if (!ni->wires.count(w))
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CHECK_FAIL("wire '%s' missing in wires map of bound net '%s'\n", nameOfWire(w), nameOf(ni));
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}
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}
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#endif
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for (auto &c : cells) {
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auto ci = c.second.get();
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if (c.first != ci->name)
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CHECK_FAIL("cell key '%s' not equal to name '%s'\n", nameOf(c.first), nameOf(ci->name));
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if (ci->bel != BelId()) {
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if (getBoundBelCell(c.second->bel) != ci)
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CHECK_FAIL("cell '%s' not bound to bel '%s' in bel field\n", nameOf(c.first), nameOfBel(ci->bel));
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}
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for (auto &port : c.second->ports) {
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NetInfo *net = port.second.net;
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if (net != nullptr) {
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if (nets.find(net->name) == nets.end()) {
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CHECK_FAIL("cell port '%s.%s' connected to non-existent net '%s'\n", nameOf(c.first),
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nameOf(port.first), nameOf(net->name));
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} else if (port.second.type == PORT_OUT) {
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if (net->driver.cell != c.second.get() || net->driver.port != port.first) {
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CHECK_FAIL("output cell port '%s.%s' not in driver field of net '%s'\n", nameOf(c.first),
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nameOf(port.first), nameOf(net));
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}
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} else if (port.second.type == PORT_IN) {
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if (!port.second.user_idx)
|
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CHECK_FAIL("input cell port '%s.%s' on net '%s' has no user index\n", nameOf(c.first),
|
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nameOf(port.first), nameOf(net));
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auto net_user = net->users.at(port.second.user_idx);
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if (net_user.cell != c.second.get() || net_user.port != port.first)
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CHECK_FAIL("input cell port '%s.%s' not in associated user entry of net '%s'\n",
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nameOf(c.first), nameOf(port.first), nameOf(net));
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}
|
||||
}
|
||||
}
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||||
}
|
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#undef CHECK_FAIL
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||||
|
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if (check_failed)
|
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log_error("INTERNAL CHECK FAILED: please report this error with the design and full log output. Failure "
|
||||
"details are above this message.\n");
|
||||
}
|
||||
|
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namespace {
|
||||
struct FixupHierarchyWorker
|
||||
{
|
||||
FixupHierarchyWorker(Context *ctx) : ctx(ctx){};
|
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Context *ctx;
|
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void run()
|
||||
{
|
||||
trim_hierarchy(ctx->top_module);
|
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rebuild_hierarchy();
|
||||
};
|
||||
// Remove cells and nets that no longer exist in the netlist
|
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std::vector<IdString> todelete_cells, todelete_nets;
|
||||
void trim_hierarchy(IdString path)
|
||||
{
|
||||
auto &h = ctx->hierarchy.at(path);
|
||||
todelete_cells.clear();
|
||||
todelete_nets.clear();
|
||||
for (auto &lc : h.leaf_cells) {
|
||||
if (!ctx->cells.count(lc.second))
|
||||
todelete_cells.push_back(lc.first);
|
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}
|
||||
for (auto &n : h.nets)
|
||||
if (!ctx->nets.count(n.second))
|
||||
todelete_nets.push_back(n.first);
|
||||
for (auto tdc : todelete_cells) {
|
||||
h.leaf_cells_by_gname.erase(h.leaf_cells.at(tdc));
|
||||
h.leaf_cells.erase(tdc);
|
||||
}
|
||||
for (auto tdn : todelete_nets) {
|
||||
h.nets_by_gname.erase(h.nets.at(tdn));
|
||||
h.nets.erase(tdn);
|
||||
}
|
||||
for (auto &sc : h.hier_cells)
|
||||
trim_hierarchy(sc.second);
|
||||
}
|
||||
|
||||
IdString construct_local_name(HierarchicalCell &hc, IdString global_name, bool is_cell)
|
||||
{
|
||||
std::string gn = global_name.str(ctx);
|
||||
auto dp = gn.find_last_of('.');
|
||||
if (dp != std::string::npos)
|
||||
gn = gn.substr(dp + 1);
|
||||
IdString name = ctx->id(gn);
|
||||
// Make sure name is unique
|
||||
int adder = 0;
|
||||
while (is_cell ? hc.leaf_cells.count(name) : hc.nets.count(name)) {
|
||||
++adder;
|
||||
name = ctx->id(gn + "$" + std::to_string(adder));
|
||||
}
|
||||
return name;
|
||||
}
|
||||
|
||||
// Update hierarchy structure for nets and cells that have hiercell set
|
||||
void rebuild_hierarchy()
|
||||
{
|
||||
for (auto &cell : ctx->cells) {
|
||||
CellInfo *ci = cell.second.get();
|
||||
if (ci->hierpath == IdString())
|
||||
ci->hierpath = ctx->top_module;
|
||||
auto &hc = ctx->hierarchy.at(ci->hierpath);
|
||||
if (hc.leaf_cells_by_gname.count(ci->name))
|
||||
continue; // already known
|
||||
IdString local_name = construct_local_name(hc, ci->name, true);
|
||||
hc.leaf_cells_by_gname[ci->name] = local_name;
|
||||
hc.leaf_cells[local_name] = ci->name;
|
||||
}
|
||||
}
|
||||
};
|
||||
} // namespace
|
||||
|
||||
void Context::fixupHierarchy() { FixupHierarchyWorker(this).run(); }
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
Reference in New Issue
Block a user