From 4a92942acb653d9c2223cdffe4b78cc6d21e162f Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 29 Jun 2025 15:26:56 +0200
Subject: [PATCH] Make code more c++ compliant

---
 himbaechel/uarch/gatemate/bitstream.cc     | 2 +-
 himbaechel/uarch/gatemate/pack_clocking.cc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/himbaechel/uarch/gatemate/bitstream.cc b/himbaechel/uarch/gatemate/bitstream.cc
index d65d8d78..72c4cd31 100644
--- a/himbaechel/uarch/gatemate/bitstream.cc
+++ b/himbaechel/uarch/gatemate/bitstream.cc
@@ -221,7 +221,7 @@ struct BitstreamBackend
     {
         ChipConfig cc;
         cc.chip_name = device;
-        int bank[uarch->dies][9] = {0};
+        std::vector<std::vector<int>> bank(uarch->dies, std::vector<int>(9, 0));
         for (auto &cell : ctx->cells) {
             CfgLoc loc = get_config_loc(cell.second.get()->bel.tile);
             auto &params = cell.second.get()->params;
diff --git a/himbaechel/uarch/gatemate/pack_clocking.cc b/himbaechel/uarch/gatemate/pack_clocking.cc
index f3d347b0..63e01d30 100644
--- a/himbaechel/uarch/gatemate/pack_clocking.cc
+++ b/himbaechel/uarch/gatemate/pack_clocking.cc
@@ -329,7 +329,7 @@ void GateMatePacker::remove_clocking()
 
 void GateMatePacker::pack_pll()
 {
-    int pll_index[uarch->dies] = {0};
+    std::vector<int> pll_index(uarch->dies, 0);
     log_info("Packing PLLss..\n");
     for (auto &cell : ctx->cells) {
         CellInfo &ci = *cell.second;