github.com/YosysHQ.nextpnr
1
0
Fork 0
mirror of https://github.com/YosysHQ/nextpnr.git synced 2026-05-04 23:25:13 +00:00
Code Issues Releases Wiki Activity

WIP: adding timing budget to placer

Browse Source 
Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah
2018-06-20 17:08:57 +02:00
parent 15c5c9c425
commit 4fc9625040
4 changed files with 23 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
common/place_sa.cc
View File

@@ -314,7 +314,9 @@ class SAPlacer
load_cell->bel, ctx->portPinFromId(load.port));
// wirelength += std::abs(load_x - driver_x) + std::abs(load_y -
// driver_y);
wirelength += ctx->estimateDelay(drv_wire, user_wire);
delay_t raw_wl = ctx->estimateDelay(drv_wire, user_wire);
wirelength += 100 * (ctx->getDelayNS(raw_wl) / ctx->getDelayNS(load.budget));
// wirelength += pow(ctx->estimateDelay(drv_wire, user_wire), 2.0);
}
return wirelength;
}
@@ -376,9 +378,8 @@ class SAPlacer
delta = new_wirelength - curr_wirelength;
n_move++;
// SA acceptance criterea
if (delta < 0 ||
(temp > 1e-6 &&
(ctx->rng() / float(0x3fffffff)) <= std::exp(-delta / temp))) {
if (delta < 0 || (temp > 1e-6 && (ctx->rng() / float(0x3fffffff)) <=
std::exp(-delta / temp))) {
n_accept++;
if (delta < 0)
improved = true;

7
common/timing.cc
View File

@@ -101,6 +101,8 @@ void assign_budget(Context *ctx, float default_clock)
}
}
}
const bool debug = true;
// Post-allocation check
for (auto net : ctx->nets) {
for (auto user : net.second->users) {
@@ -109,6 +111,11 @@ void assign_budget(Context *ctx, float default_clock)
"timing budget of %fns\n",
user.cell->name.c_str(ctx), user.port.c_str(ctx),
net.first.c_str(ctx), ctx->getDelayNS(user.budget));
if (debug)
log_warning("port %s.%s, connected to net '%s', has "
"timing budget of %fns\n",
user.cell->name.c_str(ctx), user.port.c_str(ctx),
net.first.c_str(ctx), ctx->getDelayNS(user.budget));
}
}
}