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gatemate: fix SER_CLK wiring from CLKIN to PLL (#1523)

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* gatemate: fix SER_CLK wiring from CLKIN to PLL

* fix some output formatting

---------

Co-authored-by: Patrick Urban <patrick.urban@web.de>
This commit is contained in:
Miodrag Milanović 2025-07-29 11:26:49 +02:00 committed by GitHub
parent af6e9aa6a3
commit 7e68bea863
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GPG Key ID: B5690EEEBB952194
2 changed files with 26 additions and 18 deletions
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40
himbaechel/uarch/gatemate/pack_clocking.cc
View File

@ -275,14 +275,14 @@ void GateMatePacker::insert_bufg(CellInfo *cell, IdString port)
NetInfo *net = ctx->createNet(ctx->idf("%s", bufg->name.c_str(ctx)));
cell->connectPort(port, net);
bufg->connectPort(id_I, net);
log_info("Added BUFG for cell '%s' signal %s\n", cell->name.c_str(ctx), port.c_str(ctx));
log_info(" Added BUFG for cell '%s' signal %s\n", cell->name.c_str(ctx), port.c_str(ctx));
}
}
}
void GateMatePacker::insert_pll_bufg()
{
log_info("Insert BUFGs for PLLs..\n");
log_info("Insert clocking cells..\n");
for (int i = 0; i < uarch->dies; i++) {
Loc fixed_loc = uarch->locations[std::make_pair(id_CLKIN, i)];
clkin.push_back(create_cell_ptr(id_CLKIN, ctx->idf("CLKIN%d", i)));
@ -293,6 +293,7 @@ void GateMatePacker::insert_pll_bufg()
BelId glbout_bel = ctx->getBelByLocation(fixed_loc);
ctx->bindBel(glbout_bel, glbout.back(), PlaceStrength::STRENGTH_FIXED);
}
log_info("Insert BUFGs for PLLs..\n");
std::vector<CellInfo *> cells;
for (auto &cell : ctx->cells) {
CellInfo &ci = *cell.second;
@ -350,7 +351,7 @@ void GateMatePacker::pack_pll()
int die = uarch->preferred_die;
NetInfo *clk = ci.getPort(id_CLK_REF);
if (clk) {
if (clk && clk->driver.cell) { // Only for GPIO pins
if (ctx->getBelBucketForCellType(clk->driver.cell->type) == id_CC_BUFG) {
clk = clk->driver.cell->getPort(id_I);
}
@ -382,22 +383,29 @@ void GateMatePacker::pack_pll()
clk = ci.getPort(id_CLK_REF);
delay_t period = ctx->getDelayFromNS(1.0e9 / ctx->setting<float>("target_freq"));
if (clk) {
if (ctx->getBelBucketForCellType(clk->driver.cell->type) == id_CC_BUFG) {
NetInfo *in = clk->driver.cell->getPort(id_I);
ci.disconnectPort(id_CLK_REF);
ci.connectPort(id_CLK_REF, in);
clk = in;
if (clk->driver.cell) {
if (ctx->getBelBucketForCellType(clk->driver.cell->type) == id_CC_BUFG) {
NetInfo *in = clk->driver.cell->getPort(id_I);
ci.disconnectPort(id_CLK_REF);
ci.connectPort(id_CLK_REF, in);
clk = in;
}
if (ctx->getBelBucketForCellType(clk->driver.cell->type) != id_GPIO)
log_error("CLK_REF must be driven with GPIO pin.\n");
auto pad_info = uarch->bel_to_pad[clk->driver.cell->bel];
if (pad_info->flags == 0)
log_error("CLK_REF must be driven with CLK dedicated pin.\n");
clkin[die]->params[ctx->idf("REF%d", pll_index[die])] = Property(pad_info->flags - 1, 3);
clkin[die]->params[ctx->idf("REF%d_INV", pll_index[die])] = Property(Property::State::S0);
ci.movePortTo(id_CLK_REF, clkin[die], ctx->idf("CLK%d", pad_info->flags - 1));
} else {
// SER_CLK
clkin[die]->params[ctx->idf("REF%d", pll_index[die])] = Property(0b100, 3);
clkin[die]->params[ctx->idf("REF%d_INV", pll_index[die])] = Property(Property::State::S0);
ci.movePortTo(id_CLK_REF, clkin[die], id_SER_CLK);
}
if (ctx->getBelBucketForCellType(clk->driver.cell->type) != id_GPIO)
log_error("CLK_REF must be driven with GPIO pin.\n");
auto pad_info = uarch->bel_to_pad[clk->driver.cell->bel];
if (pad_info->flags == 0)
log_error("CLK_REF must be driven with CLK dedicated pin.\n");
if (clk->clkconstr)
period = clk->clkconstr->period.minDelay();
ci.movePortTo(id_CLK_REF, clkin[die], ctx->idf("CLK%d", pad_info->flags - 1));
NetInfo *conn = ctx->createNet(ctx->idf("%s_CLK_REF", ci.name.c_str(ctx)));
clkin[die]->connectPort(ctx->idf("CLK_REF%d", pll_index[die]), conn);
ci.connectPort(id_CLK_REF, conn);

4
himbaechel/uarch/gatemate/pll.cc
View File

@ -263,7 +263,7 @@ PllCfgRecord GateMatePacker::get_pll_settings(double f_ref, double f_core, int m
if (pll_cfg_arr[0].f_core_delta == 0) {
get_DCO_ext_feedback(f_core, f_ref, pll_cfg_arr[0], f_dco_min, f_dco_max, f_dco,
max_input_freq);
log_info("PLL fout= %.4f MHz (fout error %.5f%% of requested %.4f MHz)\n",
log_info(" PLL fout= %.4f MHz (fout error %.5f%% of requested %.4f MHz)\n",
pll_cfg_arr[0].f_core,
100 - (100 * std::min(pll_cfg_arr[0].f_core, f_core_par) /
std::max(pll_cfg_arr[0].f_core, f_core_par)),
@ -344,7 +344,7 @@ PllCfgRecord GateMatePacker::get_pll_settings(double f_ref, double f_core, int m
return a.core_weight < b.core_weight;
});
PllCfgRecord val = pll_cfg_arr.at(std::distance(pll_cfg_arr.begin(), it));
log_info("PLL fout= %.4f MHz (fout error %.5f%% of requested %.4f MHz)\n", val.f_core,
log_info(" PLL fout= %.4f MHz (fout error %.5f%% of requested %.4f MHz)\n", val.f_core,
100 - (100 * std::min(val.f_core, f_core_par) / std::max(val.f_core, f_core_par)), f_core);
return val;
}