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mirror of https://github.com/YosysHQ/nextpnr.git synced 2026-04-26 04:07:02 +00:00

Getting rid of users of old IdString API

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
2018-06-18 16:08:19 +02:00
parent 0dd185a141
commit 7ef4d0726b
6 changed files with 50 additions and 48 deletions

View File

@@ -58,7 +58,7 @@ void print_utilisation(const Context *ctx)
// Sort by Bel type
std::map<BelType, int> used_types;
for (auto cell : ctx->cells) {
used_types[belTypeFromId(cell.second->type)]++;
used_types[ctx->belTypeFromId(cell.second->type)]++;
}
std::map<BelType, int> available_types;
for (auto bel : ctx->getBels()) {
@@ -66,7 +66,7 @@ void print_utilisation(const Context *ctx)
}
log("\nDesign utilisation:\n");
for (auto type : available_types) {
log("\t%20s: %5d/%5d\n", belTypeToId(type.first).c_str(),
log("\t%20s: %5d/%5d\n", ctx->belTypeToId(type.first).c_str(),
get_or_default(used_types, type.first, 0), type.second);
}
}

View File

@@ -84,7 +84,7 @@ static void place_initial(Context *ctx, CellInfo *cell, rnd_state &rnd)
ctx->unbindBel(cell->bel);
cell->bel = BelId();
}
BelType targetType = belTypeFromId(cell->type);
BelType targetType = ctx->belTypeFromId(cell->type);
for (auto bel : ctx->getBels()) {
if (ctx->getBelType(bel) == targetType &&
isValidBelForCell(ctx, cell, bel)) {
@@ -140,7 +140,7 @@ struct SAState
};
// Get the total estimated wirelength for a net
static float get_wirelength(Arch *chip, NetInfo *net)
static float get_wirelength(Context *ctx, NetInfo *net)
{
float wirelength = 0;
int driver_x = 0, driver_y = 0;
@@ -151,9 +151,9 @@ static float get_wirelength(Arch *chip, NetInfo *net)
if (driver_cell->bel == BelId())
return 0;
consider_driver =
chip->estimatePosition(driver_cell->bel, driver_x, driver_y);
WireId drv_wire = chip->getWireBelPin(driver_cell->bel,
portPinFromId(net->driver.port));
ctx->estimatePosition(driver_cell->bel, driver_x, driver_y);
WireId drv_wire = ctx->getWireBelPin(driver_cell->bel,
ctx->portPinFromId(net->driver.port));
if (!consider_driver)
return 0;
for (auto load : net->users) {
@@ -162,12 +162,12 @@ static float get_wirelength(Arch *chip, NetInfo *net)
CellInfo *load_cell = load.cell;
if (load_cell->bel == BelId())
continue;
// chip->estimatePosition(load_cell->bel, load_x, load_y);
WireId user_wire =
chip->getWireBelPin(load_cell->bel, portPinFromId(load.port));
// ctx->estimatePosition(load_cell->bel, load_x, load_y);
WireId user_wire = ctx->getWireBelPin(load_cell->bel,
ctx->portPinFromId(load.port));
// wirelength += std::abs(load_x - driver_x) + std::abs(load_y -
// driver_y);
wirelength += chip->estimateDelay(drv_wire, user_wire);
wirelength += ctx->estimateDelay(drv_wire, user_wire);
}
return wirelength;
}
@@ -262,7 +262,7 @@ swap_fail:
BelId random_bel_for_cell(Context *ctx, CellInfo *cell, SAState &state,
rnd_state &rnd)
{
BelType targetType = belTypeFromId(cell->type);
BelType targetType = ctx->belTypeFromId(cell->type);
int x = 0, y = 0;
ctx->estimatePosition(cell->bel, x, y);
while (true) {
@@ -305,10 +305,10 @@ void place_design_sa(Context *ctx, int seed)
}
BelType bel_type = ctx->getBelType(bel);
if (bel_type != belTypeFromId(cell->type)) {
if (bel_type != ctx->belTypeFromId(cell->type)) {
log_error("Bel \'%s\' of type \'%s\' does not match cell "
"\'%s\' of type \'%s\'",
loc_name.c_str(), belTypeToId(bel_type).c_str(),
loc_name.c_str(), ctx->belTypeToId(bel_type).c_str(),
cell->name.c_str(), cell->type.c_str());
}

View File

@@ -93,7 +93,8 @@ struct Router
if (driver_port_it != net_info->driver.cell->pins.end())
driver_port = driver_port_it->second;
auto src_wire = ctx->getWireBelPin(src_bel, portPinFromId(driver_port));
auto src_wire =
ctx->getWireBelPin(src_bel, ctx->portPinFromId(driver_port));
if (src_wire == WireId())
log_error("No wire found for port %s (pin %s) on source cell %s "
@@ -134,7 +135,7 @@ struct Router
user_port = user_port_it->second;
auto dst_wire =
ctx->getWireBelPin(dst_bel, portPinFromId(user_port));
ctx->getWireBelPin(dst_bel, ctx->portPinFromId(user_port));
if (dst_wire == WireId())
log_error("No wire found for port %s (pin %s) on destination "
@@ -335,7 +336,8 @@ bool route_design(Context *ctx, bool verbose)
if (driver_port_it != net_info->driver.cell->pins.end())
driver_port = driver_port_it->second;
auto src_wire = ctx->getWireBelPin(src_bel, portPinFromId(driver_port));
auto src_wire =
ctx->getWireBelPin(src_bel, ctx->portPinFromId(driver_port));
if (src_wire == WireId())
continue;
@@ -354,7 +356,7 @@ bool route_design(Context *ctx, bool verbose)
user_port = user_port_it->second;
auto dst_wire =
ctx->getWireBelPin(dst_bel, portPinFromId(user_port));
ctx->getWireBelPin(dst_bel, ctx->portPinFromId(user_port));
if (dst_wire == WireId())
continue;