github.com/YosysHQ.nextpnr
1
0
Fork 0
mirror of https://github.com/YosysHQ/nextpnr.git synced 2026-04-27 20:47:52 +00:00
Code Issues Releases Wiki Activity

Remove wire alias API

Browse Source 
It has not actually been implemented in any router for over 2.5 years and causes nothing more than confusion. It can always be added back if it forms part of a future solution; possibly as part of a more general database structure rethink.

Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah
2020-10-15 09:36:15 +01:00
parent 576baa994f
commit b18ea204c2
8 changed files with 3 additions and 60 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
docs/generic.md
View File

@@ -28,10 +28,6 @@ Adds a pip (programmable connection between two named wires). Pip delays that co
Loc is constructed using `Loc(x, y, z)`. 'z' for pips is only important if region constraints (e.g. for partial reconfiguration regions) are used.
### void addAlias(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay);
Adds a wire alias (fixed connection between two named wires). Alias delays that correspond to delay estimates are important for router performance (as the router uses an A* type algorithm), even if timing is otherwise not of importance.
### void addBel(IdString name, IdString type, Loc loc, bool gb);
Adds a bel to the FPGA description. Bel type should match the type of cells in the netlist that are placed at this bel (see below for information on special bel types supported by the packer). Loc is constructed using `Loc(x, y, z)` and must be unique.