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Code Issues Releases Wiki Activity

gatemate: BUFG must be optional

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This commit is contained in:
Miodrag Milanovic 2025-09-10 14:42:47 +02:00
parent 8ac7ed161a
commit b8d2372019
3 changed files with 3 additions and 35 deletions
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2
himbaechel/uarch/gatemate/pack.cc
View File

@ -389,7 +389,7 @@ void GateMateImpl::pack()
packer.pack_constants();
packer.cleanup();
packer.pack_io();
packer.insert_pll_bufg();
packer.insert_clocking();
packer.sort_bufg();
packer.pack_pll();
packer.pack_bufg();

3
himbaechel/uarch/gatemate/pack.h
View File

@ -54,7 +54,7 @@ struct GateMatePacker
void pack_addf();
void pack_bufg();
void sort_bufg();
void insert_pll_bufg();
void insert_clocking();
void pack_pll();
void pack_misc();
void pack_mult();
@ -73,7 +73,6 @@ struct GateMatePacker
void rename_param(CellInfo *cell, IdString name, IdString new_name, int width);
void dff_to_cpe(CellInfo *dff);
void dff_update_params();
void insert_bufg(CellInfo *cell, IdString port);
void disconnect_if_gnd(CellInfo *cell, IdString input);
void pll_out(CellInfo *cell, IdString origPort, Loc fixed);

33
himbaechel/uarch/gatemate/pack_clocking.cc
View File

@ -263,24 +263,7 @@ void GateMatePacker::pll_out(CellInfo *cell, IdString origPort, Loc fixed)
}
}
void GateMatePacker::insert_bufg(CellInfo *cell, IdString port)
{
NetInfo *clk = cell->getPort(port);
if (clk) {
if (!(clk->users.entries() == 1 && (*clk->users.begin()).cell->type == id_CC_BUFG)) {
CellInfo *bufg =
create_cell_ptr(id_CC_BUFG, ctx->idf("%s$BUFG_%s", cell->name.c_str(ctx), port.c_str(ctx)));
cell->movePortTo(port, bufg, id_O);
cell->addOutput(port);
NetInfo *net = ctx->createNet(ctx->idf("%s", bufg->name.c_str(ctx)));
cell->connectPort(port, net);
bufg->connectPort(id_I, net);
log_info(" Added BUFG for cell '%s' signal %s\n", cell->name.c_str(ctx), port.c_str(ctx));
}
}
}
void GateMatePacker::insert_pll_bufg()
void GateMatePacker::insert_clocking()
{
log_info("Insert clocking cells..\n");
for (int i = 0; i < uarch->dies; i++) {
@ -293,20 +276,6 @@ void GateMatePacker::insert_pll_bufg()
BelId glbout_bel = ctx->getBelByLocation(fixed_loc);
ctx->bindBel(glbout_bel, glbout.back(), PlaceStrength::STRENGTH_FIXED);
}
log_info("Insert BUFGs for PLLs..\n");
std::vector<CellInfo *> cells;
for (auto &cell : ctx->cells) {
CellInfo &ci = *cell.second;
if (!ci.type.in(id_CC_PLL, id_CC_PLL_ADV))
continue;
cells.push_back(&ci);
}
for (auto &cell : cells) {
insert_bufg(cell, id_CLK0);
insert_bufg(cell, id_CLK90);
insert_bufg(cell, id_CLK180);
insert_bufg(cell, id_CLK270);
}
}
void GateMatePacker::remove_clocking()