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ice40: Introduce the concept of forPadIn SB_GB

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Those are cells that are created mainly to handle the various sources a
global network can be driven from other than a user net.

When the flag is set, this means the global network usually driven by
this BEL is in fact driven by something else and so that SB_GB BEL and
matching global network can't be used.

This is also what gets used to set the extra bits during bitstream
generation.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut
2018-11-19 01:57:47 +01:00
parent 325d46e284
commit bc9f2da470
5 changed files with 53 additions and 2 deletions
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18
ice40/bitstream.cc
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@@ -269,6 +269,9 @@ void write_asc(const Context *ctx, std::ostream &out)
config.at(y).at(x).resize(rows, std::vector<int8_t>(cols));
}
}
std::vector<std::tuple<int, int, int>> extra_bits;
out << ".comment from next-pnr" << std::endl;
switch (ctx->args.type) {
@@ -513,7 +516,16 @@ void write_asc(const Context *ctx, std::ostream &out)
}
}
} else if (cell.second->type == ctx->id("SB_GB")) {
// no cell config bits
if (cell.second->gbInfo.forPadIn) {
Loc gb_loc = ctx->getBelLocation(bel);
for (int i = 0; i < ci.num_global_networks; i++) {
if ((gb_loc.x == ci.global_network_info[i].gb_x) && (gb_loc.y == ci.global_network_info[i].gb_y)) {
extra_bits.push_back(std::make_tuple(ci.global_network_info[i].pi_eb_bank,
ci.global_network_info[i].pi_eb_x,
ci.global_network_info[i].pi_eb_y));
}
}
}
} else if (cell.second->type == ctx->id("ICESTORM_RAM")) {
const BelInfoPOD &beli = ci.bel_data[bel.index];
int x = beli.x, y = beli.y;
@@ -795,6 +807,10 @@ void write_asc(const Context *ctx, std::ostream &out)
}
}
// Write extra-bits
for (auto eb : extra_bits)
out << ".extra_bit " << std::get<0>(eb) << " " << std::get<1>(eb) << " " << std::get<2>(eb) << std::endl;
// Write symbols
// const bool write_symbols = 1;
for (auto wire : ctx->getWires()) {